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\ No newline at end of file
diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out
index a24bed6f..6db8e09d 100644
--- a/project/target/streams/compile/compileIncremental/_global/streams/out
+++ b/project/target/streams/compile/compileIncremental/_global/streams/out
@@ -1 +1 @@
-[debug] Full compilation, no sources in previous analysis.
+[debug] Full compilation, no sources in previous analysis.
diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out
index 49995276..f25042f2 100644
--- a/project/target/streams/compile/copyResources/_global/streams/out
+++ b/project/target/streams/compile/copyResources/_global/streams/out
@@ -1,2 +1,2 @@
-[debug] Copy resource mappings: 
-[debug] 	
+[debug] Copy resource mappings: 
+[debug] 	
diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir
index 0faac2f2..080206fd 100644
--- a/quasar_wrapper.fir
+++ b/quasar_wrapper.fir
@@ -95890,7 +95890,7 @@ circuit quasar_wrapper :
     node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 174:32]
     node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 173:103]
     io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 170:24]
-    node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 176:77]
+    node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 176:77]
     node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
@@ -114375,7 +114375,7 @@ circuit quasar_wrapper :
     io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11]
     io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11]
     io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11]
-    when UInt<1>("h00") : @[quasar.scala 241:26]
+    when UInt<1>("h01") : @[quasar.scala 241:26]
       inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32]
       axi4_to_ahb.clock <= clock
       axi4_to_ahb.reset <= reset
diff --git a/quasar_wrapper.v b/quasar_wrapper.v
index 58260b6a..b0f0d11e 100644
--- a/quasar_wrapper.v
+++ b/quasar_wrapper.v
@@ -38,6 +38,7 @@ module ifu_mem_ctl(
   output        io_dec_mem_ctrl_ifu_pmu_ic_hit,
   output        io_dec_mem_ctrl_ifu_pmu_bus_error,
   output        io_dec_mem_ctrl_ifu_pmu_bus_busy,
+  output        io_dec_mem_ctrl_ifu_pmu_bus_trxn,
   output        io_dec_mem_ctrl_ifu_ic_error_start,
   output        io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   output [70:0] io_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -52,8 +53,15 @@ module ifu_mem_ctl(
   input         io_ifc_dma_access_ok,
   input         io_ifu_bp_hit_taken_f,
   input         io_ifu_bp_inst_mask_f,
+  input         io_ifu_axi_ar_ready,
   output        io_ifu_axi_ar_valid,
+  output [2:0]  io_ifu_axi_ar_bits_id,
   output [31:0] io_ifu_axi_ar_bits_addr,
+  output        io_ifu_axi_r_ready,
+  input         io_ifu_axi_r_valid,
+  input  [2:0]  io_ifu_axi_r_bits_id,
+  input  [63:0] io_ifu_axi_r_bits_data,
+  input  [1:0]  io_ifu_axi_r_bits_resp,
   input         io_ifu_bus_clk_en,
   input         io_dma_mem_ctl_dma_iccm_req,
   input  [31:0] io_dma_mem_ctl_dma_mem_addr,
@@ -72,7 +80,10 @@ module ifu_mem_ctl(
   input  [77:0] io_iccm_rd_data_ecc,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
+  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
+  output [70:0] io_ic_wr_data_0,
+  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -90,6 +101,7 @@ module ifu_mem_ctl(
   input  [1:0]  io_ifu_fetch_val,
   output        io_ifu_ic_mb_empty,
   output        io_ic_dma_active,
+  output        io_ic_write_stall,
   output        io_iccm_dma_ecc_error,
   output        io_iccm_dma_rvalid,
   output [63:0] io_iccm_dma_rdata,
@@ -271,7 +283,7 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_161;
   reg [31:0] _RAND_162;
   reg [31:0] _RAND_163;
-  reg [31:0] _RAND_164;
+  reg [63:0] _RAND_164;
   reg [31:0] _RAND_165;
   reg [31:0] _RAND_166;
   reg [31:0] _RAND_167;
@@ -520,7 +532,7 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_410;
   reg [31:0] _RAND_411;
   reg [31:0] _RAND_412;
-  reg [95:0] _RAND_413;
+  reg [31:0] _RAND_413;
   reg [31:0] _RAND_414;
   reg [31:0] _RAND_415;
   reg [31:0] _RAND_416;
@@ -528,13 +540,13 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_418;
   reg [31:0] _RAND_419;
   reg [31:0] _RAND_420;
-  reg [63:0] _RAND_421;
+  reg [31:0] _RAND_421;
   reg [31:0] _RAND_422;
   reg [31:0] _RAND_423;
   reg [31:0] _RAND_424;
   reg [31:0] _RAND_425;
   reg [31:0] _RAND_426;
-  reg [63:0] _RAND_427;
+  reg [31:0] _RAND_427;
   reg [31:0] _RAND_428;
   reg [31:0] _RAND_429;
   reg [31:0] _RAND_430;
@@ -548,6 +560,38 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_438;
   reg [31:0] _RAND_439;
   reg [31:0] _RAND_440;
+  reg [31:0] _RAND_441;
+  reg [95:0] _RAND_442;
+  reg [31:0] _RAND_443;
+  reg [31:0] _RAND_444;
+  reg [31:0] _RAND_445;
+  reg [31:0] _RAND_446;
+  reg [31:0] _RAND_447;
+  reg [31:0] _RAND_448;
+  reg [31:0] _RAND_449;
+  reg [31:0] _RAND_450;
+  reg [31:0] _RAND_451;
+  reg [63:0] _RAND_452;
+  reg [31:0] _RAND_453;
+  reg [31:0] _RAND_454;
+  reg [31:0] _RAND_455;
+  reg [31:0] _RAND_456;
+  reg [31:0] _RAND_457;
+  reg [63:0] _RAND_458;
+  reg [31:0] _RAND_459;
+  reg [31:0] _RAND_460;
+  reg [31:0] _RAND_461;
+  reg [31:0] _RAND_462;
+  reg [31:0] _RAND_463;
+  reg [31:0] _RAND_464;
+  reg [31:0] _RAND_465;
+  reg [31:0] _RAND_466;
+  reg [31:0] _RAND_467;
+  reg [31:0] _RAND_468;
+  reg [31:0] _RAND_469;
+  reg [31:0] _RAND_470;
+  reg [31:0] _RAND_471;
+  reg [31:0] _RAND_472;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -933,6 +977,9 @@ module ifu_mem_ctl(
   reg [2:0] miss_state; // @[Reg.scala 27:20]
   wire  miss_pending = miss_state != 3'h0; // @[ifu_mem_ctl.scala 159:30]
   wire  _T_1 = _T | miss_pending; // @[ifu_mem_ctl.scala 91:71]
+  wire  _T_2 = _T_1 | io_exu_flush_final; // @[ifu_mem_ctl.scala 91:86]
+  reg  scnd_miss_req_q; // @[ifu_mem_ctl.scala 464:52]
+  wire  scnd_miss_req = scnd_miss_req_q & _T_319; // @[ifu_mem_ctl.scala 466:36]
   wire  debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 92:42]
   wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
   reg [30:0] ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 214:63]
@@ -1042,6 +1089,8 @@ module ifu_mem_ctl(
   wire  _GEN_41 = _T_2531 ? _T_2557 : _GEN_37; // @[Conditional.scala 39:67]
   wire  err_stop_fetch = _T_2526 ? 1'h0 : _GEN_41; // @[Conditional.scala 40:58]
   wire  _T_11 = _T_10 | err_stop_fetch; // @[ifu_mem_ctl.scala 97:112]
+  wire  _T_13 = io_ifu_axi_r_valid & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 99:44]
+  wire  _T_14 = _T_13 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 99:65]
   wire  _T_227 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 189:37]
   wire  _T_228 = ~_T_227; // @[ifu_mem_ctl.scala 189:23]
   reg  reset_all_tags; // @[ifu_mem_ctl.scala 637:53]
@@ -1054,10 +1103,36 @@ module ifu_mem_ctl(
   wire  _T_230 = _T_229 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 189:59]
   wire  _T_231 = ~miss_pending; // @[ifu_mem_ctl.scala 189:82]
   wire  _T_232 = _T_230 & _T_231; // @[ifu_mem_ctl.scala 189:80]
-  wire  ic_act_miss_f = _T_232 & _T_209; // @[ifu_mem_ctl.scala 189:114]
+  wire  _T_233 = _T_232 | scnd_miss_req; // @[ifu_mem_ctl.scala 189:97]
+  wire  ic_act_miss_f = _T_233 & _T_209; // @[ifu_mem_ctl.scala 189:114]
+  reg  ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 510:56]
+  reg  bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 463:61]
+  wire  ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 524:49]
+  wire  bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 552:41]
   reg  uncacheable_miss_ff; // @[ifu_mem_ctl.scala 216:62]
+  reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 533:56]
+  wire  _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 550:69]
+  wire  _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 550:101]
+  wire  bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 550:28]
+  wire  _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 529:68]
+  wire  _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 529:48]
+  wire  bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 529:91]
+  wire  _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 528:50]
+  wire  _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 528:48]
   wire  _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 528:72]
+  wire  bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 528:70]
+  wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 532:115]
+  wire [2:0] _T_2631 = bus_inc_data_beat_cnt ? _T_2629 : 3'h0; // @[Mux.scala 27:72]
+  wire  _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 530:32]
+  wire  _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 530:57]
+  wire  bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 530:55]
+  wire [2:0] _T_2632 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] bus_new_data_beat_count = _T_2631 | _T_2632; // @[Mux.scala 27:72]
+  wire  _T_15 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 99:112]
+  wire  _T_16 = _T_14 & _T_15; // @[ifu_mem_ctl.scala 99:85]
   wire  _T_17 = ~uncacheable_miss_ff; // @[ifu_mem_ctl.scala 100:5]
+  wire  _T_18 = _T_16 & _T_17; // @[ifu_mem_ctl.scala 99:118]
+  wire  _T_19 = miss_state == 3'h5; // @[ifu_mem_ctl.scala 100:41]
   wire  _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_26 = ic_act_miss_f & _T_319; // @[ifu_mem_ctl.scala 106:43]
   wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[ifu_mem_ctl.scala 106:27]
@@ -1138,27 +1213,55 @@ module ifu_mem_ctl(
   wire  _T_215 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 184:35]
   wire  _T_216 = _T_215 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 184:52]
   wire  ic_byp_hit_f = _T_216 & miss_pending; // @[ifu_mem_ctl.scala 184:73]
-  wire  _T_40 = ic_byp_hit_f & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 111:53]
+  reg  last_data_recieved_ff; // @[ifu_mem_ctl.scala 535:58]
+  wire  last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 562:35]
+  wire  _T_32 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 110:126]
+  wire  _T_33 = last_data_recieved_ff | _T_32; // @[ifu_mem_ctl.scala 110:106]
+  wire  _T_34 = ic_byp_hit_f & _T_33; // @[ifu_mem_ctl.scala 110:80]
+  wire  _T_35 = _T_34 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 110:140]
+  wire  _T_36 = io_dec_mem_ctrl_dec_tlu_force_halt | _T_35; // @[ifu_mem_ctl.scala 110:64]
+  wire  _T_38 = ~last_data_recieved_ff; // @[ifu_mem_ctl.scala 111:30]
+  wire  _T_39 = ic_byp_hit_f & _T_38; // @[ifu_mem_ctl.scala 111:27]
+  wire  _T_40 = _T_39 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 111:53]
+  wire  _T_42 = ~ic_byp_hit_f; // @[ifu_mem_ctl.scala 112:16]
+  wire  _T_44 = _T_42 & _T_319; // @[ifu_mem_ctl.scala 112:30]
+  wire  _T_46 = _T_44 & _T_32; // @[ifu_mem_ctl.scala 112:52]
+  wire  _T_47 = _T_46 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 112:85]
+  wire  _T_51 = _T_32 & _T_17; // @[ifu_mem_ctl.scala 113:49]
   wire  _T_54 = ic_byp_hit_f & _T_319; // @[ifu_mem_ctl.scala 114:33]
+  wire  _T_56 = ~_T_32; // @[ifu_mem_ctl.scala 114:57]
+  wire  _T_57 = _T_54 & _T_56; // @[ifu_mem_ctl.scala 114:55]
   wire  ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[ifu_mem_ctl.scala 102:52]
   wire  _T_58 = ~ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 114:91]
-  wire  _T_59 = _T_54 & _T_58; // @[ifu_mem_ctl.scala 114:89]
+  wire  _T_59 = _T_57 & _T_58; // @[ifu_mem_ctl.scala 114:89]
   wire  _T_61 = _T_59 & _T_17; // @[ifu_mem_ctl.scala 114:113]
+  wire  _T_64 = bus_ifu_wr_en_ff & _T_319; // @[ifu_mem_ctl.scala 115:39]
+  wire  _T_67 = _T_64 & _T_56; // @[ifu_mem_ctl.scala 115:61]
+  wire  _T_69 = _T_67 & _T_58; // @[ifu_mem_ctl.scala 115:95]
+  wire  _T_71 = _T_69 & _T_17; // @[ifu_mem_ctl.scala 115:119]
+  wire  _T_79 = _T_46 & _T_17; // @[ifu_mem_ctl.scala 116:100]
   wire  _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 117:44]
-  wire [2:0] _T_86 = _T_81 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 117:22]
-  wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_86; // @[ifu_mem_ctl.scala 114:18]
-  wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_89; // @[ifu_mem_ctl.scala 111:12]
-  wire [2:0] _T_93 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 110:27]
+  wire  _T_84 = _T_81 & _T_56; // @[ifu_mem_ctl.scala 117:68]
+  wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 117:22]
+  wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[ifu_mem_ctl.scala 116:20]
+  wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[ifu_mem_ctl.scala 115:20]
+  wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[ifu_mem_ctl.scala 114:18]
+  wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[ifu_mem_ctl.scala 113:16]
+  wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[ifu_mem_ctl.scala 112:14]
+  wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[ifu_mem_ctl.scala 111:12]
+  wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 110:27]
   wire  _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_2280 = byp_fetch_index[4:1] == 4'hf; // @[ifu_mem_ctl.scala 374:60]
   wire  _T_2281 = _T_2280 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 374:94]
   wire  stream_eol_f = _T_2281 & stream_hit_f; // @[ifu_mem_ctl.scala 374:112]
   wire  _T_108 = _T_81 | stream_eol_f; // @[ifu_mem_ctl.scala 125:72]
-  wire  _T_113 = _T_108 & _T_2623; // @[ifu_mem_ctl.scala 125:122]
+  wire  _T_111 = _T_108 & _T_56; // @[ifu_mem_ctl.scala 125:87]
+  wire  _T_113 = _T_111 & _T_2623; // @[ifu_mem_ctl.scala 125:122]
   wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 125:27]
   wire  _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
-  wire  _T_126 = io_exu_flush_final & _T_2623; // @[ifu_mem_ctl.scala 129:82]
+  wire  _T_124 = io_exu_flush_final & _T_56; // @[ifu_mem_ctl.scala 129:48]
+  wire  _T_126 = _T_124 & _T_2623; // @[ifu_mem_ctl.scala 129:82]
   wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 129:27]
   wire  _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_236 = io_ic_rd_hit == 2'h0; // @[ifu_mem_ctl.scala 190:28]
@@ -1173,19 +1276,22 @@ module ifu_mem_ctl(
   wire  _T_247 = ~sel_mb_addr_ff; // @[ifu_mem_ctl.scala 191:116]
   wire  _T_248 = _T_246 & _T_247; // @[ifu_mem_ctl.scala 191:114]
   wire  ic_miss_under_miss_f = _T_248 & _T_209; // @[ifu_mem_ctl.scala 191:132]
-  wire  _T_137 = ic_miss_under_miss_f & _T_2623; // @[ifu_mem_ctl.scala 133:84]
+  wire  _T_135 = ic_miss_under_miss_f & _T_56; // @[ifu_mem_ctl.scala 133:50]
+  wire  _T_137 = _T_135 & _T_2623; // @[ifu_mem_ctl.scala 133:84]
   wire  _T_256 = _T_230 & _T_239; // @[ifu_mem_ctl.scala 192:85]
   wire  _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 193:39]
   wire  _T_260 = _T_259 | uncacheable_miss_ff; // @[ifu_mem_ctl.scala 193:91]
   wire  ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[ifu_mem_ctl.scala 192:117]
-  wire  _T_143 = ic_ignore_2nd_miss_f & _T_2623; // @[ifu_mem_ctl.scala 134:69]
+  wire  _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[ifu_mem_ctl.scala 134:35]
+  wire  _T_143 = _T_141 & _T_2623; // @[ifu_mem_ctl.scala 134:69]
   wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[ifu_mem_ctl.scala 134:12]
   wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[ifu_mem_ctl.scala 133:27]
   wire  _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_155 = io_exu_flush_final ? 3'h2 : 3'h1; // @[ifu_mem_ctl.scala 138:75]
+  wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[ifu_mem_ctl.scala 139:12]
+  wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[ifu_mem_ctl.scala 138:75]
   wire [2:0] _T_156 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_155; // @[ifu_mem_ctl.scala 138:27]
   wire  _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_164 = io_exu_flush_final ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 143:75]
+  wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[ifu_mem_ctl.scala 143:75]
   wire [2:0] _T_165 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_164; // @[ifu_mem_ctl.scala 143:27]
   wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67]
@@ -1195,31 +1301,43 @@ module ifu_mem_ctl(
   wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67]
   wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58]
+  wire  _T_20 = miss_nxtstate == 3'h5; // @[ifu_mem_ctl.scala 100:73]
+  wire  _T_21 = _T_19 | _T_20; // @[ifu_mem_ctl.scala 100:57]
+  wire  _T_22 = _T_18 & _T_21; // @[ifu_mem_ctl.scala 100:26]
   wire  _T_30 = ic_act_miss_f & _T_2623; // @[ifu_mem_ctl.scala 107:38]
   wire  _T_94 = io_dec_mem_ctrl_dec_tlu_force_halt | io_exu_flush_final; // @[ifu_mem_ctl.scala 118:59]
   wire  _T_95 = _T_94 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 118:80]
   wire  _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 118:95]
+  wire  _T_98 = _T_96 | _T_32; // @[ifu_mem_ctl.scala 118:118]
+  wire  _T_100 = bus_ifu_wr_en_ff & _T_17; // @[ifu_mem_ctl.scala 118:171]
+  wire  _T_101 = _T_98 | _T_100; // @[ifu_mem_ctl.scala 118:151]
   wire  _T_103 = io_exu_flush_final | flush_final_f; // @[ifu_mem_ctl.scala 122:43]
   wire  _T_104 = _T_103 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 122:59]
   wire  _T_105 = _T_104 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 122:74]
-  wire  _T_120 = _T_108 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:118]
-  wire  _T_131 = io_exu_flush_final | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 130:76]
-  wire  _T_149 = ic_miss_under_miss_f | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 135:78]
+  wire  _T_119 = _T_108 | _T_32; // @[ifu_mem_ctl.scala 126:84]
+  wire  _T_120 = _T_119 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:118]
+  wire  _T_130 = io_exu_flush_final | _T_32; // @[ifu_mem_ctl.scala 130:43]
+  wire  _T_131 = _T_130 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 130:76]
+  wire  _T_148 = _T_32 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 135:55]
+  wire  _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 135:78]
   wire  _T_150 = _T_149 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 135:101]
-  wire  _GEN_1 = _T_160 & _T_131; // @[Conditional.scala 39:67]
-  wire  _GEN_3 = _T_151 ? _T_131 : _GEN_1; // @[Conditional.scala 39:67]
+  wire  _T_158 = _T_32 | io_exu_flush_final; // @[ifu_mem_ctl.scala 140:55]
+  wire  _T_159 = _T_158 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 140:76]
+  wire  _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67]
+  wire  _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67]
   wire  _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67]
   wire  _GEN_7 = _T_121 ? _T_131 : _GEN_5; // @[Conditional.scala 39:67]
   wire  _GEN_9 = _T_106 ? _T_120 : _GEN_7; // @[Conditional.scala 39:67]
   wire  _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67]
-  wire  _GEN_13 = _T_31 ? _T_96 : _GEN_11; // @[Conditional.scala 39:67]
+  wire  _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67]
   wire  miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58]
   wire  _T_174 = ~flush_final_f; // @[ifu_mem_ctl.scala 160:95]
   wire  _T_175 = _T_2283 & _T_174; // @[ifu_mem_ctl.scala 160:93]
   wire  crit_wd_byp_ok_ff = _T_2284 | _T_175; // @[ifu_mem_ctl.scala 160:58]
+  wire  _T_178 = miss_pending & _T_56; // @[ifu_mem_ctl.scala 161:36]
   wire  _T_180 = _T_2283 & io_exu_flush_final; // @[ifu_mem_ctl.scala 161:106]
   wire  _T_181 = ~_T_180; // @[ifu_mem_ctl.scala 161:72]
-  wire  _T_182 = miss_pending & _T_181; // @[ifu_mem_ctl.scala 161:70]
+  wire  _T_182 = _T_178 & _T_181; // @[ifu_mem_ctl.scala 161:70]
   wire  _T_184 = _T_2283 & crit_byp_hit_f; // @[ifu_mem_ctl.scala 162:57]
   wire  _T_185 = ~_T_184; // @[ifu_mem_ctl.scala 162:23]
   wire  _T_186 = _T_182 & _T_185; // @[ifu_mem_ctl.scala 161:128]
@@ -1227,6 +1345,9 @@ module ifu_mem_ctl(
   wire  _T_188 = miss_nxtstate == 3'h4; // @[ifu_mem_ctl.scala 163:36]
   wire  _T_189 = miss_pending & _T_188; // @[ifu_mem_ctl.scala 163:19]
   wire  sel_hold_imb = _T_187 | _T_189; // @[ifu_mem_ctl.scala 162:93]
+  wire  _T_191 = _T_19 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 165:57]
+  wire  sel_hold_imb_scnd = _T_191 & _T_174; // @[ifu_mem_ctl.scala 165:81]
+  reg  way_status_mb_scnd_ff; // @[ifu_mem_ctl.scala 173:64]
   reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 669:14]
   wire  _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 665:80]
   reg  way_status_out_0; // @[Reg.scala 27:20]
@@ -1741,6 +1862,13 @@ module ifu_mem_ctl(
   wire  way_status = _T_5052 | _T_4926; // @[Mux.scala 27:72]
   wire  _T_195 = ~reset_all_tags; // @[ifu_mem_ctl.scala 168:96]
   wire [1:0] _T_197 = _T_195 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[ifu_mem_ctl.scala 168:113]
+  reg [1:0] tagv_mb_scnd_ff; // @[ifu_mem_ctl.scala 174:58]
+  reg  uncacheable_miss_scnd_ff; // @[ifu_mem_ctl.scala 170:67]
+  reg [30:0] imb_scnd_ff; // @[ifu_mem_ctl.scala 172:54]
+  wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 514:46]
+  wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[ifu_mem_ctl.scala 177:45]
   wire  _T_212 = _T_231 | _T_239; // @[ifu_mem_ctl.scala 182:59]
   wire  _T_214 = _T_212 | _T_2268; // @[ifu_mem_ctl.scala 182:91]
   wire  ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[ifu_mem_ctl.scala 182:41]
@@ -1751,6 +1879,21 @@ module ifu_mem_ctl(
   wire  _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[ifu_mem_ctl.scala 195:31]
   wire  _T_263 = _T_262 | ic_iccm_hit_f; // @[ifu_mem_ctl.scala 195:46]
   wire  _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 195:94]
+  wire  _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 196:84]
+  wire  uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[ifu_mem_ctl.scala 196:32]
+  wire  _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 199:79]
+  wire  _T_275 = _T_274 & scnd_miss_req; // @[ifu_mem_ctl.scala 199:135]
+  reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 512:51]
+  wire  _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 558:48]
+  wire  _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 558:52]
+  wire  bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 558:73]
+  reg  ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 276:61]
+  wire  ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 275:55]
+  wire  _T_276 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 199:153]
+  wire  scnd_miss_index_match = _T_275 & _T_276; // @[ifu_mem_ctl.scala 199:151]
+  wire  _T_277 = ~scnd_miss_index_match; // @[ifu_mem_ctl.scala 202:47]
+  wire  _T_278 = scnd_miss_req & _T_277; // @[ifu_mem_ctl.scala 202:45]
+  wire  _T_280 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 203:26]
   reg  way_status_mb_ff; // @[ifu_mem_ctl.scala 223:59]
   wire  _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 720:33]
   reg [1:0] tagv_mb_ff; // @[ifu_mem_ctl.scala 224:53]
@@ -1758,15 +1901,21 @@ module ifu_mem_ctl(
   wire  _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 720:67]
   wire  _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 720:86]
   wire  replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 720:84]
+  wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire  _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:50]
   wire  _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:66]
   wire  _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:85]
   wire  _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:100]
   wire  replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 721:83]
+  wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58]
+  wire [1:0] _T_289 = _T_287 & _T_288; // @[ifu_mem_ctl.scala 207:110]
+  wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[ifu_mem_ctl.scala 207:62]
   wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[ifu_mem_ctl.scala 208:56]
+  wire  _T_297 = ~scnd_miss_req_q; // @[ifu_mem_ctl.scala 211:36]
+  wire  _T_298 = miss_pending & _T_297; // @[ifu_mem_ctl.scala 211:34]
   reg  reset_ic_ff; // @[ifu_mem_ctl.scala 212:48]
   wire  _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 211:72]
-  wire  reset_ic_in = miss_pending & _T_299; // @[ifu_mem_ctl.scala 211:53]
+  wire  reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 211:53]
   reg  fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 213:62]
   reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 222:48]
   wire  _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 221:57]
@@ -1780,48 +1929,296 @@ module ifu_mem_ctl(
   reg  ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68]
   reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55]
   wire  _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55]
+  wire  _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82]
+  wire  _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55]
+  wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2289}; // @[Cat.scala 29:58]
+  wire  _T_2290 = other_tag == 3'h0; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2314 = _T_2290 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
+  wire  _T_2293 = other_tag == 3'h1; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2315 = _T_2293 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
+  wire  _T_2322 = _T_2314 | _T_2315; // @[Mux.scala 27:72]
+  wire  _T_2296 = other_tag == 3'h2; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2316 = _T_2296 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
+  wire  _T_2323 = _T_2322 | _T_2316; // @[Mux.scala 27:72]
+  wire  _T_2299 = other_tag == 3'h3; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2317 = _T_2299 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
+  wire  _T_2324 = _T_2323 | _T_2317; // @[Mux.scala 27:72]
+  wire  _T_2302 = other_tag == 3'h4; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2318 = _T_2302 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
+  wire  _T_2325 = _T_2324 | _T_2318; // @[Mux.scala 27:72]
+  wire  _T_2305 = other_tag == 3'h5; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2319 = _T_2305 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
+  wire  _T_2326 = _T_2325 | _T_2319; // @[Mux.scala 27:72]
+  wire  _T_2308 = other_tag == 3'h6; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2320 = _T_2308 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
+  wire  _T_2327 = _T_2326 | _T_2320; // @[Mux.scala 27:72]
+  wire  _T_2311 = other_tag == 3'h7; // @[ifu_mem_ctl.scala 379:81]
+  wire  _T_2321 = _T_2311 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
+  wire  second_half_available = _T_2327 | _T_2321; // @[Mux.scala 27:72]
+  wire  write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 380:46]
+  wire  _T_332 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 238:35]
+  wire  _T_334 = _T_332 & _T_17; // @[ifu_mem_ctl.scala 238:55]
   reg  ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 555:61]
   wire  _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 556:53]
   wire  reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 556:84]
-  wire [30:0] _T_338 = {imb_ff[30:5],3'h0,imb_ff[1:0]}; // @[Cat.scala 29:58]
-  wire  _T_339 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 240:37]
-  wire [30:0] _T_340 = reset_tag_valid_for_miss ? _T_338 : 31'h0; // @[Mux.scala 27:72]
+  wire  sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 238:79]
+  wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_339 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 240:37]
+  wire [30:0] _T_340 = sel_mb_addr ? _T_338 : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72]
-  wire [30:0] ifu_status_wr_addr = reset_tag_valid_for_miss ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31]
+  wire  _T_346 = _T_334 & last_beat; // @[ifu_mem_ctl.scala 242:85]
+  wire  _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 553:84]
+  wire  _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 553:82]
+  wire  bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 553:108]
+  wire  _T_347 = _T_346 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 242:97]
+  wire  sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 242:119]
+  wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31]
+  reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 513:48]
+  wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 276:13]
+  wire  _T_571 = ^_T_570; // @[lib.scala 276:20]
+  wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 276:30]
+  wire [7:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[lib.scala 276:30]
+  wire [14:0] _T_585 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_577}; // @[lib.scala 276:30]
+  wire [7:0] _T_592 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[lib.scala 276:30]
+  wire [30:0] _T_601 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_585}; // @[lib.scala 276:30]
+  wire  _T_602 = ^_T_601; // @[lib.scala 276:37]
+  wire [6:0] _T_608 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[lib.scala 276:47]
+  wire [14:0] _T_616 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_608}; // @[lib.scala 276:47]
+  wire [30:0] _T_632 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_616}; // @[lib.scala 276:47]
+  wire  _T_633 = ^_T_632; // @[lib.scala 276:54]
+  wire [6:0] _T_639 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[lib.scala 276:64]
+  wire [14:0] _T_647 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_639}; // @[lib.scala 276:64]
+  wire [30:0] _T_663 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_584,_T_647}; // @[lib.scala 276:64]
+  wire  _T_664 = ^_T_663; // @[lib.scala 276:71]
+  wire [7:0] _T_671 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[lib.scala 276:81]
+  wire [16:0] _T_680 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_671}; // @[lib.scala 276:81]
+  wire [8:0] _T_688 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:81]
+  wire [17:0] _T_697 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_688}; // @[lib.scala 276:81]
+  wire [34:0] _T_698 = {_T_697,_T_680}; // @[lib.scala 276:81]
+  wire  _T_699 = ^_T_698; // @[lib.scala 276:88]
+  wire [7:0] _T_706 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:98]
+  wire [16:0] _T_715 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_706}; // @[lib.scala 276:98]
+  wire [8:0] _T_723 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:98]
+  wire [17:0] _T_732 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_723}; // @[lib.scala 276:98]
+  wire [34:0] _T_733 = {_T_732,_T_715}; // @[lib.scala 276:98]
+  wire  _T_734 = ^_T_733; // @[lib.scala 276:105]
+  wire [7:0] _T_741 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:115]
+  wire [16:0] _T_750 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_741}; // @[lib.scala 276:115]
+  wire [8:0] _T_758 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[lib.scala 276:115]
+  wire [17:0] _T_767 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_758}; // @[lib.scala 276:115]
+  wire [34:0] _T_768 = {_T_767,_T_750}; // @[lib.scala 276:115]
+  wire  _T_769 = ^_T_768; // @[lib.scala 276:122]
+  wire [3:0] _T_2330 = {ifu_bus_rid_ff[2:1],_T_2289,1'h1}; // @[Cat.scala 29:58]
+  wire  _T_2331 = _T_2330 == 4'h0; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_0; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2378 = _T_2331 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire  _T_2334 = _T_2330 == 4'h1; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_1; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2379 = _T_2334 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2394 = _T_2378 | _T_2379; // @[Mux.scala 27:72]
+  wire  _T_2337 = _T_2330 == 4'h2; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_2; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2380 = _T_2337 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2395 = _T_2394 | _T_2380; // @[Mux.scala 27:72]
+  wire  _T_2340 = _T_2330 == 4'h3; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_3; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2381 = _T_2340 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2396 = _T_2395 | _T_2381; // @[Mux.scala 27:72]
+  wire  _T_2343 = _T_2330 == 4'h4; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_4; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2382 = _T_2343 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2397 = _T_2396 | _T_2382; // @[Mux.scala 27:72]
+  wire  _T_2346 = _T_2330 == 4'h5; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_5; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2383 = _T_2346 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2398 = _T_2397 | _T_2383; // @[Mux.scala 27:72]
+  wire  _T_2349 = _T_2330 == 4'h6; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_6; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2384 = _T_2349 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2399 = _T_2398 | _T_2384; // @[Mux.scala 27:72]
+  wire  _T_2352 = _T_2330 == 4'h7; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_7; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2385 = _T_2352 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2400 = _T_2399 | _T_2385; // @[Mux.scala 27:72]
+  wire  _T_2355 = _T_2330 == 4'h8; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_8; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2386 = _T_2355 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2401 = _T_2400 | _T_2386; // @[Mux.scala 27:72]
+  wire  _T_2358 = _T_2330 == 4'h9; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_9; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2387 = _T_2358 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2402 = _T_2401 | _T_2387; // @[Mux.scala 27:72]
+  wire  _T_2361 = _T_2330 == 4'ha; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_10; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2388 = _T_2361 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2403 = _T_2402 | _T_2388; // @[Mux.scala 27:72]
+  wire  _T_2364 = _T_2330 == 4'hb; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_11; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2389 = _T_2364 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2404 = _T_2403 | _T_2389; // @[Mux.scala 27:72]
+  wire  _T_2367 = _T_2330 == 4'hc; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_12; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2390 = _T_2367 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2405 = _T_2404 | _T_2390; // @[Mux.scala 27:72]
+  wire  _T_2370 = _T_2330 == 4'hd; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_13; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2391 = _T_2370 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2406 = _T_2405 | _T_2391; // @[Mux.scala 27:72]
+  wire  _T_2373 = _T_2330 == 4'he; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_14; // @[ifu_mem_ctl.scala 316:65]
+  wire [31:0] _T_2392 = _T_2373 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2407 = _T_2406 | _T_2392; // @[Mux.scala 27:72]
+  wire  _T_2376 = _T_2330 == 4'hf; // @[ifu_mem_ctl.scala 381:89]
+  reg [31:0] ic_miss_buff_data_15; // @[ifu_mem_ctl.scala 317:67]
+  wire [31:0] _T_2393 = _T_2376 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2408 = _T_2407 | _T_2393; // @[Mux.scala 27:72]
+  wire [3:0] _T_2410 = {ifu_bus_rid_ff[2:1],_T_2289,1'h0}; // @[Cat.scala 29:58]
+  wire  _T_2411 = _T_2410 == 4'h0; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2458 = _T_2411 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire  _T_2414 = _T_2410 == 4'h1; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2459 = _T_2414 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2474 = _T_2458 | _T_2459; // @[Mux.scala 27:72]
+  wire  _T_2417 = _T_2410 == 4'h2; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2460 = _T_2417 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2475 = _T_2474 | _T_2460; // @[Mux.scala 27:72]
+  wire  _T_2420 = _T_2410 == 4'h3; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2461 = _T_2420 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2476 = _T_2475 | _T_2461; // @[Mux.scala 27:72]
+  wire  _T_2423 = _T_2410 == 4'h4; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2462 = _T_2423 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2477 = _T_2476 | _T_2462; // @[Mux.scala 27:72]
+  wire  _T_2426 = _T_2410 == 4'h5; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2463 = _T_2426 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2478 = _T_2477 | _T_2463; // @[Mux.scala 27:72]
+  wire  _T_2429 = _T_2410 == 4'h6; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2464 = _T_2429 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2479 = _T_2478 | _T_2464; // @[Mux.scala 27:72]
+  wire  _T_2432 = _T_2410 == 4'h7; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2465 = _T_2432 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2480 = _T_2479 | _T_2465; // @[Mux.scala 27:72]
+  wire  _T_2435 = _T_2410 == 4'h8; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2466 = _T_2435 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2481 = _T_2480 | _T_2466; // @[Mux.scala 27:72]
+  wire  _T_2438 = _T_2410 == 4'h9; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2467 = _T_2438 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2482 = _T_2481 | _T_2467; // @[Mux.scala 27:72]
+  wire  _T_2441 = _T_2410 == 4'ha; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2468 = _T_2441 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2483 = _T_2482 | _T_2468; // @[Mux.scala 27:72]
+  wire  _T_2444 = _T_2410 == 4'hb; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2469 = _T_2444 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2484 = _T_2483 | _T_2469; // @[Mux.scala 27:72]
+  wire  _T_2447 = _T_2410 == 4'hc; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2470 = _T_2447 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2485 = _T_2484 | _T_2470; // @[Mux.scala 27:72]
+  wire  _T_2450 = _T_2410 == 4'hd; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2471 = _T_2450 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2486 = _T_2485 | _T_2471; // @[Mux.scala 27:72]
+  wire  _T_2453 = _T_2410 == 4'he; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2472 = _T_2453 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2487 = _T_2486 | _T_2472; // @[Mux.scala 27:72]
+  wire  _T_2456 = _T_2410 == 4'hf; // @[ifu_mem_ctl.scala 382:66]
+  wire [31:0] _T_2473 = _T_2456 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2488 = _T_2487 | _T_2473; // @[Mux.scala 27:72]
+  wire [63:0] ic_miss_buff_half = {_T_2408,_T_2488}; // @[Cat.scala 29:58]
+  wire [6:0] _T_992 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[lib.scala 276:13]
+  wire  _T_993 = ^_T_992; // @[lib.scala 276:20]
+  wire [6:0] _T_999 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[lib.scala 276:30]
+  wire [7:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[lib.scala 276:30]
+  wire [14:0] _T_1007 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_999}; // @[lib.scala 276:30]
+  wire [7:0] _T_1014 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[lib.scala 276:30]
+  wire [30:0] _T_1023 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1007}; // @[lib.scala 276:30]
+  wire  _T_1024 = ^_T_1023; // @[lib.scala 276:37]
+  wire [6:0] _T_1030 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[lib.scala 276:47]
+  wire [14:0] _T_1038 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1030}; // @[lib.scala 276:47]
+  wire [30:0] _T_1054 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1038}; // @[lib.scala 276:47]
+  wire  _T_1055 = ^_T_1054; // @[lib.scala 276:54]
+  wire [6:0] _T_1061 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[lib.scala 276:64]
+  wire [14:0] _T_1069 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1061}; // @[lib.scala 276:64]
+  wire [30:0] _T_1085 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1006,_T_1069}; // @[lib.scala 276:64]
+  wire  _T_1086 = ^_T_1085; // @[lib.scala 276:71]
+  wire [7:0] _T_1093 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[lib.scala 276:81]
+  wire [16:0] _T_1102 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1093}; // @[lib.scala 276:81]
+  wire [8:0] _T_1110 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:81]
+  wire [17:0] _T_1119 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1110}; // @[lib.scala 276:81]
+  wire [34:0] _T_1120 = {_T_1119,_T_1102}; // @[lib.scala 276:81]
+  wire  _T_1121 = ^_T_1120; // @[lib.scala 276:88]
+  wire [7:0] _T_1128 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[lib.scala 276:98]
+  wire [16:0] _T_1137 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1128}; // @[lib.scala 276:98]
+  wire [8:0] _T_1145 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:98]
+  wire [17:0] _T_1154 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1145}; // @[lib.scala 276:98]
+  wire [34:0] _T_1155 = {_T_1154,_T_1137}; // @[lib.scala 276:98]
+  wire  _T_1156 = ^_T_1155; // @[lib.scala 276:105]
+  wire [7:0] _T_1163 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[lib.scala 276:115]
+  wire [16:0] _T_1172 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1163}; // @[lib.scala 276:115]
+  wire [8:0] _T_1180 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[lib.scala 276:115]
+  wire [17:0] _T_1189 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1180}; // @[lib.scala 276:115]
+  wire [34:0] _T_1190 = {_T_1189,_T_1172}; // @[lib.scala 276:115]
+  wire  _T_1191 = ^_T_1190; // @[lib.scala 276:122]
+  wire [70:0] _T_1236 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff}; // @[Cat.scala 29:58]
+  wire [70:0] _T_1235 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488}; // @[Cat.scala 29:58]
+  wire [141:0] _T_1237 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff,_T_1235}; // @[Cat.scala 29:58]
+  wire [141:0] _T_1240 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488,_T_1236}; // @[Cat.scala 29:58]
+  wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1237 : _T_1240; // @[ifu_mem_ctl.scala 267:28]
   wire  _T_1199 = |io_ic_eccerr; // @[ifu_mem_ctl.scala 256:73]
   wire  _T_1200 = _T_1199 & ic_act_hit_f; // @[ifu_mem_ctl.scala 256:100]
   wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 328:28]
   wire  _T_1404 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 330:114]
+  wire  bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 551:35]
+  wire  _T_1289 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_0 = bus_ifu_wr_en & _T_1289; // @[ifu_mem_ctl.scala 312:73]
   wire  _T_1330 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 319:118]
-  wire  ic_miss_buff_data_valid_in_0 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1331 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1331; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1427 = _T_1404 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
   wire  _T_1407 = bypass_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_1 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1290 = io_ifu_axi_r_bits_id == 3'h1; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_1 = bus_ifu_wr_en & _T_1290; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1334 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1334; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1428 = _T_1407 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
   wire  _T_1435 = _T_1427 | _T_1428; // @[Mux.scala 27:72]
   wire  _T_1410 = bypass_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_2 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1291 = io_ifu_axi_r_bits_id == 3'h2; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_2 = bus_ifu_wr_en & _T_1291; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1337 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1337; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1429 = _T_1410 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
   wire  _T_1436 = _T_1435 | _T_1429; // @[Mux.scala 27:72]
   wire  _T_1413 = bypass_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_3 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1292 = io_ifu_axi_r_bits_id == 3'h3; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_3 = bus_ifu_wr_en & _T_1292; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1340 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1340; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1430 = _T_1413 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
   wire  _T_1437 = _T_1436 | _T_1430; // @[Mux.scala 27:72]
   wire  _T_1416 = bypass_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_4 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1293 = io_ifu_axi_r_bits_id == 3'h4; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_4 = bus_ifu_wr_en & _T_1293; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1343 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1343; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1431 = _T_1416 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
   wire  _T_1438 = _T_1437 | _T_1431; // @[Mux.scala 27:72]
   wire  _T_1419 = bypass_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_5 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1294 = io_ifu_axi_r_bits_id == 3'h5; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_5 = bus_ifu_wr_en & _T_1294; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1346 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1346; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1432 = _T_1419 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
   wire  _T_1439 = _T_1438 | _T_1432; // @[Mux.scala 27:72]
   wire  _T_1422 = bypass_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_6 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1295 = io_ifu_axi_r_bits_id == 3'h6; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_6 = bus_ifu_wr_en & _T_1295; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1349 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1349; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1433 = _T_1422 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
   wire  _T_1440 = _T_1439 | _T_1433; // @[Mux.scala 27:72]
   wire  _T_1425 = bypass_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 330:114]
-  wire  ic_miss_buff_data_valid_in_7 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  _T_1296 = io_ifu_axi_r_bits_id == 3'h7; // @[ifu_mem_ctl.scala 312:91]
+  wire  write_fill_data_7 = bus_ifu_wr_en & _T_1296; // @[ifu_mem_ctl.scala 312:73]
+  wire  _T_1352 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
+  wire  ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1352; // @[ifu_mem_ctl.scala 319:88]
   wire  _T_1434 = _T_1425 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
   wire  bypass_valid_value_check = _T_1440 | _T_1434; // @[Mux.scala 27:72]
   wire  _T_1443 = ~bypass_index[1]; // @[ifu_mem_ctl.scala 331:58]
@@ -2691,7 +3088,239 @@ module ifu_mem_ctl(
   wire [63:0] ic_final_data = _T_1263 & io_ic_rd_data; // @[ifu_mem_ctl.scala 288:92]
   wire [63:0] _T_1265 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
   wire [63:0] _T_1266 = _T_1265 & io_iccm_rd_data; // @[ifu_mem_ctl.scala 292:69]
-  wire [79:0] ic_premux_data_temp = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88]
+  wire [63:0] _T_1268 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58]
+  wire  _T_1662 = byp_fetch_index_inc_0 == 4'h0; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1710 = _T_1662 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire  _T_1665 = byp_fetch_index_inc_0 == 4'h1; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1711 = _T_1665 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1726 = _T_1710 | _T_1711; // @[Mux.scala 27:72]
+  wire  _T_1668 = byp_fetch_index_inc_0 == 4'h2; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1712 = _T_1668 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1727 = _T_1726 | _T_1712; // @[Mux.scala 27:72]
+  wire  _T_1671 = byp_fetch_index_inc_0 == 4'h3; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1713 = _T_1671 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1728 = _T_1727 | _T_1713; // @[Mux.scala 27:72]
+  wire  _T_1674 = byp_fetch_index_inc_0 == 4'h4; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1714 = _T_1674 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1729 = _T_1728 | _T_1714; // @[Mux.scala 27:72]
+  wire  _T_1677 = byp_fetch_index_inc_0 == 4'h5; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1715 = _T_1677 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1730 = _T_1729 | _T_1715; // @[Mux.scala 27:72]
+  wire  _T_1680 = byp_fetch_index_inc_0 == 4'h6; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1716 = _T_1680 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1731 = _T_1730 | _T_1716; // @[Mux.scala 27:72]
+  wire  _T_1683 = byp_fetch_index_inc_0 == 4'h7; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1717 = _T_1683 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1732 = _T_1731 | _T_1717; // @[Mux.scala 27:72]
+  wire  _T_1686 = byp_fetch_index_inc_0 == 4'h8; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1718 = _T_1686 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1733 = _T_1732 | _T_1718; // @[Mux.scala 27:72]
+  wire  _T_1689 = byp_fetch_index_inc_0 == 4'h9; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1719 = _T_1689 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1734 = _T_1733 | _T_1719; // @[Mux.scala 27:72]
+  wire  _T_1692 = byp_fetch_index_inc_0 == 4'ha; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1720 = _T_1692 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1735 = _T_1734 | _T_1720; // @[Mux.scala 27:72]
+  wire  _T_1695 = byp_fetch_index_inc_0 == 4'hb; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1721 = _T_1695 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1736 = _T_1735 | _T_1721; // @[Mux.scala 27:72]
+  wire  _T_1698 = byp_fetch_index_inc_0 == 4'hc; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1722 = _T_1698 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1737 = _T_1736 | _T_1722; // @[Mux.scala 27:72]
+  wire  _T_1701 = byp_fetch_index_inc_0 == 4'hd; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1723 = _T_1701 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1738 = _T_1737 | _T_1723; // @[Mux.scala 27:72]
+  wire  _T_1704 = byp_fetch_index_inc_0 == 4'he; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1724 = _T_1704 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1739 = _T_1738 | _T_1724; // @[Mux.scala 27:72]
+  wire  _T_1707 = byp_fetch_index_inc_0 == 4'hf; // @[ifu_mem_ctl.scala 358:73]
+  wire [15:0] _T_1725 = _T_1707 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1740 = _T_1739 | _T_1725; // @[Mux.scala 27:72]
+  wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58]
+  wire  _T_1742 = byp_fetch_index_1 == 4'h0; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1790 = _T_1742 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire  _T_1745 = byp_fetch_index_1 == 4'h1; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1791 = _T_1745 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1806 = _T_1790 | _T_1791; // @[Mux.scala 27:72]
+  wire  _T_1748 = byp_fetch_index_1 == 4'h2; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1792 = _T_1748 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1807 = _T_1806 | _T_1792; // @[Mux.scala 27:72]
+  wire  _T_1751 = byp_fetch_index_1 == 4'h3; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1793 = _T_1751 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1808 = _T_1807 | _T_1793; // @[Mux.scala 27:72]
+  wire  _T_1754 = byp_fetch_index_1 == 4'h4; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1794 = _T_1754 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1809 = _T_1808 | _T_1794; // @[Mux.scala 27:72]
+  wire  _T_1757 = byp_fetch_index_1 == 4'h5; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1795 = _T_1757 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1810 = _T_1809 | _T_1795; // @[Mux.scala 27:72]
+  wire  _T_1760 = byp_fetch_index_1 == 4'h6; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1796 = _T_1760 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1811 = _T_1810 | _T_1796; // @[Mux.scala 27:72]
+  wire  _T_1763 = byp_fetch_index_1 == 4'h7; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1797 = _T_1763 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1812 = _T_1811 | _T_1797; // @[Mux.scala 27:72]
+  wire  _T_1766 = byp_fetch_index_1 == 4'h8; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1798 = _T_1766 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1813 = _T_1812 | _T_1798; // @[Mux.scala 27:72]
+  wire  _T_1769 = byp_fetch_index_1 == 4'h9; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1799 = _T_1769 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1814 = _T_1813 | _T_1799; // @[Mux.scala 27:72]
+  wire  _T_1772 = byp_fetch_index_1 == 4'ha; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1800 = _T_1772 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1815 = _T_1814 | _T_1800; // @[Mux.scala 27:72]
+  wire  _T_1775 = byp_fetch_index_1 == 4'hb; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1801 = _T_1775 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1816 = _T_1815 | _T_1801; // @[Mux.scala 27:72]
+  wire  _T_1778 = byp_fetch_index_1 == 4'hc; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1802 = _T_1778 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1817 = _T_1816 | _T_1802; // @[Mux.scala 27:72]
+  wire  _T_1781 = byp_fetch_index_1 == 4'hd; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1803 = _T_1781 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1818 = _T_1817 | _T_1803; // @[Mux.scala 27:72]
+  wire  _T_1784 = byp_fetch_index_1 == 4'he; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1804 = _T_1784 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1819 = _T_1818 | _T_1804; // @[Mux.scala 27:72]
+  wire  _T_1787 = byp_fetch_index_1 == 4'hf; // @[ifu_mem_ctl.scala 358:179]
+  wire [31:0] _T_1805 = _T_1787 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1820 = _T_1819 | _T_1805; // @[Mux.scala 27:72]
+  wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58]
+  wire  _T_1822 = byp_fetch_index_0 == 4'h0; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1870 = _T_1822 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire  _T_1825 = byp_fetch_index_0 == 4'h1; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1871 = _T_1825 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1886 = _T_1870 | _T_1871; // @[Mux.scala 27:72]
+  wire  _T_1828 = byp_fetch_index_0 == 4'h2; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1872 = _T_1828 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1887 = _T_1886 | _T_1872; // @[Mux.scala 27:72]
+  wire  _T_1831 = byp_fetch_index_0 == 4'h3; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1873 = _T_1831 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1888 = _T_1887 | _T_1873; // @[Mux.scala 27:72]
+  wire  _T_1834 = byp_fetch_index_0 == 4'h4; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1874 = _T_1834 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1889 = _T_1888 | _T_1874; // @[Mux.scala 27:72]
+  wire  _T_1837 = byp_fetch_index_0 == 4'h5; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1875 = _T_1837 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1890 = _T_1889 | _T_1875; // @[Mux.scala 27:72]
+  wire  _T_1840 = byp_fetch_index_0 == 4'h6; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1876 = _T_1840 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1891 = _T_1890 | _T_1876; // @[Mux.scala 27:72]
+  wire  _T_1843 = byp_fetch_index_0 == 4'h7; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1877 = _T_1843 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1892 = _T_1891 | _T_1877; // @[Mux.scala 27:72]
+  wire  _T_1846 = byp_fetch_index_0 == 4'h8; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1878 = _T_1846 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1893 = _T_1892 | _T_1878; // @[Mux.scala 27:72]
+  wire  _T_1849 = byp_fetch_index_0 == 4'h9; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1879 = _T_1849 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1894 = _T_1893 | _T_1879; // @[Mux.scala 27:72]
+  wire  _T_1852 = byp_fetch_index_0 == 4'ha; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1880 = _T_1852 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1895 = _T_1894 | _T_1880; // @[Mux.scala 27:72]
+  wire  _T_1855 = byp_fetch_index_0 == 4'hb; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1881 = _T_1855 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1896 = _T_1895 | _T_1881; // @[Mux.scala 27:72]
+  wire  _T_1858 = byp_fetch_index_0 == 4'hc; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1882 = _T_1858 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1897 = _T_1896 | _T_1882; // @[Mux.scala 27:72]
+  wire  _T_1861 = byp_fetch_index_0 == 4'hd; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1883 = _T_1861 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1898 = _T_1897 | _T_1883; // @[Mux.scala 27:72]
+  wire  _T_1864 = byp_fetch_index_0 == 4'he; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1884 = _T_1864 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1899 = _T_1898 | _T_1884; // @[Mux.scala 27:72]
+  wire  _T_1867 = byp_fetch_index_0 == 4'hf; // @[ifu_mem_ctl.scala 358:285]
+  wire [31:0] _T_1885 = _T_1867 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1900 = _T_1899 | _T_1885; // @[Mux.scala 27:72]
+  wire [79:0] _T_1903 = {_T_1740,_T_1820,_T_1900}; // @[Cat.scala 29:58]
+  wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58]
+  wire  _T_1904 = byp_fetch_index_inc_1 == 4'h0; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1952 = _T_1904 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire  _T_1907 = byp_fetch_index_inc_1 == 4'h1; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1953 = _T_1907 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1968 = _T_1952 | _T_1953; // @[Mux.scala 27:72]
+  wire  _T_1910 = byp_fetch_index_inc_1 == 4'h2; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1954 = _T_1910 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1969 = _T_1968 | _T_1954; // @[Mux.scala 27:72]
+  wire  _T_1913 = byp_fetch_index_inc_1 == 4'h3; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1955 = _T_1913 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1970 = _T_1969 | _T_1955; // @[Mux.scala 27:72]
+  wire  _T_1916 = byp_fetch_index_inc_1 == 4'h4; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1956 = _T_1916 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1971 = _T_1970 | _T_1956; // @[Mux.scala 27:72]
+  wire  _T_1919 = byp_fetch_index_inc_1 == 4'h5; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1957 = _T_1919 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1972 = _T_1971 | _T_1957; // @[Mux.scala 27:72]
+  wire  _T_1922 = byp_fetch_index_inc_1 == 4'h6; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1958 = _T_1922 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1973 = _T_1972 | _T_1958; // @[Mux.scala 27:72]
+  wire  _T_1925 = byp_fetch_index_inc_1 == 4'h7; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1959 = _T_1925 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1974 = _T_1973 | _T_1959; // @[Mux.scala 27:72]
+  wire  _T_1928 = byp_fetch_index_inc_1 == 4'h8; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1960 = _T_1928 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1975 = _T_1974 | _T_1960; // @[Mux.scala 27:72]
+  wire  _T_1931 = byp_fetch_index_inc_1 == 4'h9; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1961 = _T_1931 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1976 = _T_1975 | _T_1961; // @[Mux.scala 27:72]
+  wire  _T_1934 = byp_fetch_index_inc_1 == 4'ha; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1962 = _T_1934 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1977 = _T_1976 | _T_1962; // @[Mux.scala 27:72]
+  wire  _T_1937 = byp_fetch_index_inc_1 == 4'hb; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1963 = _T_1937 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1978 = _T_1977 | _T_1963; // @[Mux.scala 27:72]
+  wire  _T_1940 = byp_fetch_index_inc_1 == 4'hc; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1964 = _T_1940 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1979 = _T_1978 | _T_1964; // @[Mux.scala 27:72]
+  wire  _T_1943 = byp_fetch_index_inc_1 == 4'hd; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1965 = _T_1943 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1980 = _T_1979 | _T_1965; // @[Mux.scala 27:72]
+  wire  _T_1946 = byp_fetch_index_inc_1 == 4'he; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1966 = _T_1946 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1981 = _T_1980 | _T_1966; // @[Mux.scala 27:72]
+  wire  _T_1949 = byp_fetch_index_inc_1 == 4'hf; // @[ifu_mem_ctl.scala 359:73]
+  wire [15:0] _T_1967 = _T_1949 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_1982 = _T_1981 | _T_1967; // @[Mux.scala 27:72]
+  wire [31:0] _T_2032 = _T_1662 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2033 = _T_1665 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2048 = _T_2032 | _T_2033; // @[Mux.scala 27:72]
+  wire [31:0] _T_2034 = _T_1668 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2049 = _T_2048 | _T_2034; // @[Mux.scala 27:72]
+  wire [31:0] _T_2035 = _T_1671 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2050 = _T_2049 | _T_2035; // @[Mux.scala 27:72]
+  wire [31:0] _T_2036 = _T_1674 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2051 = _T_2050 | _T_2036; // @[Mux.scala 27:72]
+  wire [31:0] _T_2037 = _T_1677 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2052 = _T_2051 | _T_2037; // @[Mux.scala 27:72]
+  wire [31:0] _T_2038 = _T_1680 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2053 = _T_2052 | _T_2038; // @[Mux.scala 27:72]
+  wire [31:0] _T_2039 = _T_1683 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2054 = _T_2053 | _T_2039; // @[Mux.scala 27:72]
+  wire [31:0] _T_2040 = _T_1686 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2055 = _T_2054 | _T_2040; // @[Mux.scala 27:72]
+  wire [31:0] _T_2041 = _T_1689 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2056 = _T_2055 | _T_2041; // @[Mux.scala 27:72]
+  wire [31:0] _T_2042 = _T_1692 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2057 = _T_2056 | _T_2042; // @[Mux.scala 27:72]
+  wire [31:0] _T_2043 = _T_1695 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2058 = _T_2057 | _T_2043; // @[Mux.scala 27:72]
+  wire [31:0] _T_2044 = _T_1698 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72]
+  wire [31:0] _T_2045 = _T_1701 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72]
+  wire [31:0] _T_2046 = _T_1704 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72]
+  wire [31:0] _T_2047 = _T_1707 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72]
+  wire [79:0] _T_2145 = {_T_1982,_T_2062,_T_1820}; // @[Cat.scala 29:58]
+  wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1903 : _T_2145; // @[ifu_mem_ctl.scala 357:37]
+  wire [79:0] _T_2150 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
+  wire [79:0] ic_byp_data_only_new = _T_1614 ? ic_byp_data_only_pre_new : _T_2150; // @[ifu_mem_ctl.scala 361:30]
+  wire [79:0] _GEN_437 = {{16'd0}, _T_1268}; // @[ifu_mem_ctl.scala 292:114]
+  wire [79:0] _T_1269 = _GEN_437 & ic_byp_data_only_new; // @[ifu_mem_ctl.scala 292:114]
+  wire [79:0] _GEN_438 = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88]
+  wire [79:0] ic_premux_data_temp = _GEN_438 | _T_1269; // @[ifu_mem_ctl.scala 292:88]
   wire  fetch_req_f_qual = io_ic_hit_f & _T_319; // @[ifu_mem_ctl.scala 299:38]
   reg  ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 783:66]
   wire [1:0] _T_1277 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 304:10]
@@ -2703,14 +3332,25 @@ module ifu_mem_ctl(
   wire  _T_1285 = err_stop_state != 2'h2; // @[ifu_mem_ctl.scala 305:131]
   wire  _T_1286 = _T_1284 & _T_1285; // @[ifu_mem_ctl.scala 305:114]
   wire [6:0] _T_1358 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58]
-  wire  ic_miss_buff_data_error_in_0 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_1 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_2 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_3 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_4 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_5 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_6 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_7 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  _T_1364 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 557:47]
+  wire  _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 557:50]
+  wire  bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 557:68]
+  wire  ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1364; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1368 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1368; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1372 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1372; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1376 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1376; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1380 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1380; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1384 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1384; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1388 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1388; // @[ifu_mem_ctl.scala 323:72]
+  wire  _T_1392 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1392; // @[ifu_mem_ctl.scala 323:72]
   wire [6:0] _T_1398 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58]
   reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20]
   wire  _T_2500 = 3'h0 == perr_state; // @[Conditional.scala 37:30]
@@ -2759,9 +3399,46 @@ module ifu_mem_ctl(
   wire  _T_2591 = ic_act_miss_f | bus_cmd_req_hold; // @[ifu_mem_ctl.scala 471:45]
   reg  ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 472:55]
   wire  _T_2592 = _T_2591 | ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:64]
+  wire  _T_2594 = _T_2592 & _T_2623; // @[ifu_mem_ctl.scala 471:85]
+  reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20]
+  wire  _T_2596 = bus_cmd_beat_count == 3'h7; // @[ifu_mem_ctl.scala 471:146]
+  wire  _T_2597 = _T_2596 & ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:177]
+  wire  _T_2598 = _T_2597 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 471:197]
+  wire  _T_2599 = _T_2598 & miss_pending; // @[ifu_mem_ctl.scala 471:217]
+  wire  _T_2600 = ~_T_2599; // @[ifu_mem_ctl.scala 471:125]
+  wire  ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 522:45]
+  wire  _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 526:35]
+  wire  _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 526:53]
+  wire  bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 526:68]
+  wire  _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61]
+  wire  _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59]
+  wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58]
   wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  reg  ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 509:57]
   reg  ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 511:53]
+  wire  ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 523:51]
+  wire  _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 534:73]
+  wire  _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 534:71]
+  wire  _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 534:114]
+  wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 539:45]
+  wire  _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 542:48]
+  wire  _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 542:68]
+  wire  bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 542:83]
+  wire  bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 544:57]
+  wire  _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 545:31]
+  wire  _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 545:71]
+  wire  _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 545:87]
+  wire  _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 545:55]
+  wire  bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 545:53]
+  wire  _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 546:46]
+  wire  bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 546:62]
+  wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 548:46]
+  wire [2:0] _T_2665 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_2666 = bus_inc_cmd_beat_cnt ? _T_2663 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_2667 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_2669 = _T_2665 | _T_2666; // @[Mux.scala 27:72]
+  wire [2:0] bus_new_cmd_beat_count = _T_2669 | _T_2667; // @[Mux.scala 27:72]
   reg  ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 560:62]
   wire  _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 565:50]
   wire  _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 565:47]
@@ -3120,12 +3797,28 @@ module ifu_mem_ctl(
   wire  _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 633:28]
   wire  _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 633:50]
   wire  _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 633:81]
+  wire [1:0] _T_3974 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire  _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 727:74]
+  wire  bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 727:98]
+  wire  _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 727:74]
+  wire  bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 727:98]
+  wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58]
+  wire  _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 636:106]
+  wire  _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 636:104]
+  wire  _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 636:77]
+  wire  _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 636:172]
+  wire  _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 636:170]
+  wire  _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 636:44]
   wire  _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 639:64]
   wire  _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 639:50]
-  wire  ic_valid = _T_3993 & _T_339; // @[ifu_mem_ctl.scala 639:79]
+  wire  _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 639:48]
+  wire  _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 639:81]
+  wire  ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 639:79]
   wire  _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 640:82]
   reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 643:14]
   wire  _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 646:74]
+  wire  _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 726:45]
+  wire  way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 726:58]
   reg  way_status_wr_en_ff; // @[ifu_mem_ctl.scala 648:14]
   wire  way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 722:41]
   reg  way_status_new_ff; // @[ifu_mem_ctl.scala 654:14]
@@ -3145,9 +3838,17 @@ module ifu_mem_ctl(
   wire  _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136]
   wire  _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 660:128]
   wire  _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136]
+  wire  _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 729:84]
+  wire  _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 729:108]
+  wire  bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 729:123]
   wire  wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 730:84]
+  wire  _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 731:73]
+  wire  _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 729:84]
+  wire  _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 729:108]
+  wire  bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 729:123]
   wire  wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 730:84]
-  wire [1:0] ifu_tag_wren = {wren_reset_miss_1,wren_reset_miss_0}; // @[Cat.scala 29:58]
+  wire  _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 731:73]
+  wire [1:0] ifu_tag_wren = {_T_9786,_T_9785}; // @[Cat.scala 29:58]
   wire [1:0] _T_9821 = _T_4000 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 765:90]
   reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 675:14]
@@ -4357,7 +5058,10 @@ module ifu_mem_ctl(
   reg  _T_9799; // @[ifu_mem_ctl.scala 752:70]
   reg  _T_9800; // @[ifu_mem_ctl.scala 753:69]
   reg  _T_9801; // @[ifu_mem_ctl.scala 754:72]
+  wire  _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 755:93]
+  wire  _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 755:91]
   reg  _T_9805; // @[ifu_mem_ctl.scala 755:71]
+  reg  _T_9806; // @[ifu_mem_ctl.scala 756:71]
   wire  _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 763:84]
   wire  _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 763:150]
   wire  _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 764:63]
@@ -4947,13 +5651,16 @@ module ifu_mem_ctl(
   assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 753:34]
   assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 754:37]
   assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 755:36]
+  assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 756:36]
   assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1200 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 256:38]
   assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 612:46]
   assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1212; // @[ifu_mem_ctl.scala 263:40]
   assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 770:46]
   assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39]
   assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23]
+  assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25]
   assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27]
+  assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22]
   assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19]
   assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27]
   assign io_iccm_correction_state = _T_2526 ? 1'h0 : _GEN_42; // @[ifu_mem_ctl.scala 430:28 ifu_mem_ctl.scala 442:32 ifu_mem_ctl.scala 449:32 ifu_mem_ctl.scala 456:32]
@@ -4963,7 +5670,10 @@ module ifu_mem_ctl(
   assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 576:19]
   assign io_ic_rw_addr = _T_340 | _T_341; // @[ifu_mem_ctl.scala 244:17]
   assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 747:19]
+  assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 635:15]
   assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 626:15]
+  assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 253:17]
+  assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 253:17]
   assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 254:23]
   assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 759:20]
   assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 761:21]
@@ -4972,8 +5682,9 @@ module ifu_mem_ctl(
   assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 763:19]
   assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 295:21]
   assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[ifu_mem_ctl.scala 296:25]
-  assign io_ifu_ic_mb_empty = _T_325 | _T_231; // @[ifu_mem_ctl.scala 234:22]
+  assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[ifu_mem_ctl.scala 234:22]
   assign io_ic_dma_active = _T_11 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 97:20]
+  assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 636:21]
   assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 595:25]
   assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 593:22]
   assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 597:21]
@@ -4994,202 +5705,202 @@ module ifu_mem_ctl(
   assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[lib.scala 345:16]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_2_io_en = _T_1 | io_exu_flush_final; // @[lib.scala 345:16]
+  assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[lib.scala 345:16]
   assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_3_io_en = _T_309 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[lib.scala 345:16]
   assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_4_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_5_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_6_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_7_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_8_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_9_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_12_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_12_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_13_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_13_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_14_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_14_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_15_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_15_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_16_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_16_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_17_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_17_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_18_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_18_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_19_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_19_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_20_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_20_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_21_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_21_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_22_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_22_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_23_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_23_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_24_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_24_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_25_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_25_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_26_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_26_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_27_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_27_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_28_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_28_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_29_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_29_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_30_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_30_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_31_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_31_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_32_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_32_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_33_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_33_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_34_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_35_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_35_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_36_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_36_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_37_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_37_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_38_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_38_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_39_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_39_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_40_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_40_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_41_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_41_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_42_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_42_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_43_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_43_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_44_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_44_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_45_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_45_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_46_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_46_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_47_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_47_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_48_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_48_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_49_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_49_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_50_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_50_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_51_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_51_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_52_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_52_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_53_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_53_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_54_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_54_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_55_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_55_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_56_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_56_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_57_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_57_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_58_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_58_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_59_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_59_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_60_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_60_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
   assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_61_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_61_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
   assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_62_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_62_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
   assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_63_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_63_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
   assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_64_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_64_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
   assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_65_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_65_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
   assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_66_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_66_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
   assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_67_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_67_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
   assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_68_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[lib.scala 345:16]
@@ -5311,881 +6022,945 @@ initial begin
   _RAND_2 = {1{`RANDOM}};
   miss_state = _RAND_2[2:0];
   _RAND_3 = {1{`RANDOM}};
-  ifu_fetch_addr_int_f = _RAND_3[30:0];
+  scnd_miss_req_q = _RAND_3[0:0];
   _RAND_4 = {1{`RANDOM}};
-  ifc_iccm_access_f = _RAND_4[0:0];
+  ifu_fetch_addr_int_f = _RAND_4[30:0];
   _RAND_5 = {1{`RANDOM}};
-  iccm_dma_rvalid_in = _RAND_5[0:0];
+  ifc_iccm_access_f = _RAND_5[0:0];
   _RAND_6 = {1{`RANDOM}};
-  dma_iccm_req_f = _RAND_6[0:0];
+  iccm_dma_rvalid_in = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  perr_state = _RAND_7[2:0];
+  dma_iccm_req_f = _RAND_7[0:0];
   _RAND_8 = {1{`RANDOM}};
-  err_stop_state = _RAND_8[1:0];
+  perr_state = _RAND_8[2:0];
   _RAND_9 = {1{`RANDOM}};
-  reset_all_tags = _RAND_9[0:0];
+  err_stop_state = _RAND_9[1:0];
   _RAND_10 = {1{`RANDOM}};
-  ifc_region_acc_fault_final_f = _RAND_10[0:0];
+  reset_all_tags = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  uncacheable_miss_ff = _RAND_11[0:0];
+  ifc_region_acc_fault_final_f = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  ic_miss_buff_data_valid = _RAND_12[7:0];
+  ifu_bus_rvalid_unq_ff = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  imb_ff = _RAND_13[30:0];
+  bus_ifu_bus_clk_en_ff = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  sel_mb_addr_ff = _RAND_14[0:0];
+  uncacheable_miss_ff = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  ifu_ic_rw_int_addr_ff = _RAND_15[6:0];
+  bus_data_beat_count = _RAND_15[2:0];
   _RAND_16 = {1{`RANDOM}};
-  way_status_out_0 = _RAND_16[0:0];
+  ic_miss_buff_data_valid = _RAND_16[7:0];
   _RAND_17 = {1{`RANDOM}};
-  way_status_out_1 = _RAND_17[0:0];
+  imb_ff = _RAND_17[30:0];
   _RAND_18 = {1{`RANDOM}};
-  way_status_out_2 = _RAND_18[0:0];
+  last_data_recieved_ff = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  way_status_out_3 = _RAND_19[0:0];
+  sel_mb_addr_ff = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  way_status_out_4 = _RAND_20[0:0];
+  way_status_mb_scnd_ff = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  way_status_out_5 = _RAND_21[0:0];
+  ifu_ic_rw_int_addr_ff = _RAND_21[6:0];
   _RAND_22 = {1{`RANDOM}};
-  way_status_out_6 = _RAND_22[0:0];
+  way_status_out_0 = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  way_status_out_7 = _RAND_23[0:0];
+  way_status_out_1 = _RAND_23[0:0];
   _RAND_24 = {1{`RANDOM}};
-  way_status_out_8 = _RAND_24[0:0];
+  way_status_out_2 = _RAND_24[0:0];
   _RAND_25 = {1{`RANDOM}};
-  way_status_out_9 = _RAND_25[0:0];
+  way_status_out_3 = _RAND_25[0:0];
   _RAND_26 = {1{`RANDOM}};
-  way_status_out_10 = _RAND_26[0:0];
+  way_status_out_4 = _RAND_26[0:0];
   _RAND_27 = {1{`RANDOM}};
-  way_status_out_11 = _RAND_27[0:0];
+  way_status_out_5 = _RAND_27[0:0];
   _RAND_28 = {1{`RANDOM}};
-  way_status_out_12 = _RAND_28[0:0];
+  way_status_out_6 = _RAND_28[0:0];
   _RAND_29 = {1{`RANDOM}};
-  way_status_out_13 = _RAND_29[0:0];
+  way_status_out_7 = _RAND_29[0:0];
   _RAND_30 = {1{`RANDOM}};
-  way_status_out_14 = _RAND_30[0:0];
+  way_status_out_8 = _RAND_30[0:0];
   _RAND_31 = {1{`RANDOM}};
-  way_status_out_15 = _RAND_31[0:0];
+  way_status_out_9 = _RAND_31[0:0];
   _RAND_32 = {1{`RANDOM}};
-  way_status_out_16 = _RAND_32[0:0];
+  way_status_out_10 = _RAND_32[0:0];
   _RAND_33 = {1{`RANDOM}};
-  way_status_out_17 = _RAND_33[0:0];
+  way_status_out_11 = _RAND_33[0:0];
   _RAND_34 = {1{`RANDOM}};
-  way_status_out_18 = _RAND_34[0:0];
+  way_status_out_12 = _RAND_34[0:0];
   _RAND_35 = {1{`RANDOM}};
-  way_status_out_19 = _RAND_35[0:0];
+  way_status_out_13 = _RAND_35[0:0];
   _RAND_36 = {1{`RANDOM}};
-  way_status_out_20 = _RAND_36[0:0];
+  way_status_out_14 = _RAND_36[0:0];
   _RAND_37 = {1{`RANDOM}};
-  way_status_out_21 = _RAND_37[0:0];
+  way_status_out_15 = _RAND_37[0:0];
   _RAND_38 = {1{`RANDOM}};
-  way_status_out_22 = _RAND_38[0:0];
+  way_status_out_16 = _RAND_38[0:0];
   _RAND_39 = {1{`RANDOM}};
-  way_status_out_23 = _RAND_39[0:0];
+  way_status_out_17 = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  way_status_out_24 = _RAND_40[0:0];
+  way_status_out_18 = _RAND_40[0:0];
   _RAND_41 = {1{`RANDOM}};
-  way_status_out_25 = _RAND_41[0:0];
+  way_status_out_19 = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  way_status_out_26 = _RAND_42[0:0];
+  way_status_out_20 = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  way_status_out_27 = _RAND_43[0:0];
+  way_status_out_21 = _RAND_43[0:0];
   _RAND_44 = {1{`RANDOM}};
-  way_status_out_28 = _RAND_44[0:0];
+  way_status_out_22 = _RAND_44[0:0];
   _RAND_45 = {1{`RANDOM}};
-  way_status_out_29 = _RAND_45[0:0];
+  way_status_out_23 = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  way_status_out_30 = _RAND_46[0:0];
+  way_status_out_24 = _RAND_46[0:0];
   _RAND_47 = {1{`RANDOM}};
-  way_status_out_31 = _RAND_47[0:0];
+  way_status_out_25 = _RAND_47[0:0];
   _RAND_48 = {1{`RANDOM}};
-  way_status_out_32 = _RAND_48[0:0];
+  way_status_out_26 = _RAND_48[0:0];
   _RAND_49 = {1{`RANDOM}};
-  way_status_out_33 = _RAND_49[0:0];
+  way_status_out_27 = _RAND_49[0:0];
   _RAND_50 = {1{`RANDOM}};
-  way_status_out_34 = _RAND_50[0:0];
+  way_status_out_28 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  way_status_out_35 = _RAND_51[0:0];
+  way_status_out_29 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  way_status_out_36 = _RAND_52[0:0];
+  way_status_out_30 = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  way_status_out_37 = _RAND_53[0:0];
+  way_status_out_31 = _RAND_53[0:0];
   _RAND_54 = {1{`RANDOM}};
-  way_status_out_38 = _RAND_54[0:0];
+  way_status_out_32 = _RAND_54[0:0];
   _RAND_55 = {1{`RANDOM}};
-  way_status_out_39 = _RAND_55[0:0];
+  way_status_out_33 = _RAND_55[0:0];
   _RAND_56 = {1{`RANDOM}};
-  way_status_out_40 = _RAND_56[0:0];
+  way_status_out_34 = _RAND_56[0:0];
   _RAND_57 = {1{`RANDOM}};
-  way_status_out_41 = _RAND_57[0:0];
+  way_status_out_35 = _RAND_57[0:0];
   _RAND_58 = {1{`RANDOM}};
-  way_status_out_42 = _RAND_58[0:0];
+  way_status_out_36 = _RAND_58[0:0];
   _RAND_59 = {1{`RANDOM}};
-  way_status_out_43 = _RAND_59[0:0];
+  way_status_out_37 = _RAND_59[0:0];
   _RAND_60 = {1{`RANDOM}};
-  way_status_out_44 = _RAND_60[0:0];
+  way_status_out_38 = _RAND_60[0:0];
   _RAND_61 = {1{`RANDOM}};
-  way_status_out_45 = _RAND_61[0:0];
+  way_status_out_39 = _RAND_61[0:0];
   _RAND_62 = {1{`RANDOM}};
-  way_status_out_46 = _RAND_62[0:0];
+  way_status_out_40 = _RAND_62[0:0];
   _RAND_63 = {1{`RANDOM}};
-  way_status_out_47 = _RAND_63[0:0];
+  way_status_out_41 = _RAND_63[0:0];
   _RAND_64 = {1{`RANDOM}};
-  way_status_out_48 = _RAND_64[0:0];
+  way_status_out_42 = _RAND_64[0:0];
   _RAND_65 = {1{`RANDOM}};
-  way_status_out_49 = _RAND_65[0:0];
+  way_status_out_43 = _RAND_65[0:0];
   _RAND_66 = {1{`RANDOM}};
-  way_status_out_50 = _RAND_66[0:0];
+  way_status_out_44 = _RAND_66[0:0];
   _RAND_67 = {1{`RANDOM}};
-  way_status_out_51 = _RAND_67[0:0];
+  way_status_out_45 = _RAND_67[0:0];
   _RAND_68 = {1{`RANDOM}};
-  way_status_out_52 = _RAND_68[0:0];
+  way_status_out_46 = _RAND_68[0:0];
   _RAND_69 = {1{`RANDOM}};
-  way_status_out_53 = _RAND_69[0:0];
+  way_status_out_47 = _RAND_69[0:0];
   _RAND_70 = {1{`RANDOM}};
-  way_status_out_54 = _RAND_70[0:0];
+  way_status_out_48 = _RAND_70[0:0];
   _RAND_71 = {1{`RANDOM}};
-  way_status_out_55 = _RAND_71[0:0];
+  way_status_out_49 = _RAND_71[0:0];
   _RAND_72 = {1{`RANDOM}};
-  way_status_out_56 = _RAND_72[0:0];
+  way_status_out_50 = _RAND_72[0:0];
   _RAND_73 = {1{`RANDOM}};
-  way_status_out_57 = _RAND_73[0:0];
+  way_status_out_51 = _RAND_73[0:0];
   _RAND_74 = {1{`RANDOM}};
-  way_status_out_58 = _RAND_74[0:0];
+  way_status_out_52 = _RAND_74[0:0];
   _RAND_75 = {1{`RANDOM}};
-  way_status_out_59 = _RAND_75[0:0];
+  way_status_out_53 = _RAND_75[0:0];
   _RAND_76 = {1{`RANDOM}};
-  way_status_out_60 = _RAND_76[0:0];
+  way_status_out_54 = _RAND_76[0:0];
   _RAND_77 = {1{`RANDOM}};
-  way_status_out_61 = _RAND_77[0:0];
+  way_status_out_55 = _RAND_77[0:0];
   _RAND_78 = {1{`RANDOM}};
-  way_status_out_62 = _RAND_78[0:0];
+  way_status_out_56 = _RAND_78[0:0];
   _RAND_79 = {1{`RANDOM}};
-  way_status_out_63 = _RAND_79[0:0];
+  way_status_out_57 = _RAND_79[0:0];
   _RAND_80 = {1{`RANDOM}};
-  way_status_out_64 = _RAND_80[0:0];
+  way_status_out_58 = _RAND_80[0:0];
   _RAND_81 = {1{`RANDOM}};
-  way_status_out_65 = _RAND_81[0:0];
+  way_status_out_59 = _RAND_81[0:0];
   _RAND_82 = {1{`RANDOM}};
-  way_status_out_66 = _RAND_82[0:0];
+  way_status_out_60 = _RAND_82[0:0];
   _RAND_83 = {1{`RANDOM}};
-  way_status_out_67 = _RAND_83[0:0];
+  way_status_out_61 = _RAND_83[0:0];
   _RAND_84 = {1{`RANDOM}};
-  way_status_out_68 = _RAND_84[0:0];
+  way_status_out_62 = _RAND_84[0:0];
   _RAND_85 = {1{`RANDOM}};
-  way_status_out_69 = _RAND_85[0:0];
+  way_status_out_63 = _RAND_85[0:0];
   _RAND_86 = {1{`RANDOM}};
-  way_status_out_70 = _RAND_86[0:0];
+  way_status_out_64 = _RAND_86[0:0];
   _RAND_87 = {1{`RANDOM}};
-  way_status_out_71 = _RAND_87[0:0];
+  way_status_out_65 = _RAND_87[0:0];
   _RAND_88 = {1{`RANDOM}};
-  way_status_out_72 = _RAND_88[0:0];
+  way_status_out_66 = _RAND_88[0:0];
   _RAND_89 = {1{`RANDOM}};
-  way_status_out_73 = _RAND_89[0:0];
+  way_status_out_67 = _RAND_89[0:0];
   _RAND_90 = {1{`RANDOM}};
-  way_status_out_74 = _RAND_90[0:0];
+  way_status_out_68 = _RAND_90[0:0];
   _RAND_91 = {1{`RANDOM}};
-  way_status_out_75 = _RAND_91[0:0];
+  way_status_out_69 = _RAND_91[0:0];
   _RAND_92 = {1{`RANDOM}};
-  way_status_out_76 = _RAND_92[0:0];
+  way_status_out_70 = _RAND_92[0:0];
   _RAND_93 = {1{`RANDOM}};
-  way_status_out_77 = _RAND_93[0:0];
+  way_status_out_71 = _RAND_93[0:0];
   _RAND_94 = {1{`RANDOM}};
-  way_status_out_78 = _RAND_94[0:0];
+  way_status_out_72 = _RAND_94[0:0];
   _RAND_95 = {1{`RANDOM}};
-  way_status_out_79 = _RAND_95[0:0];
+  way_status_out_73 = _RAND_95[0:0];
   _RAND_96 = {1{`RANDOM}};
-  way_status_out_80 = _RAND_96[0:0];
+  way_status_out_74 = _RAND_96[0:0];
   _RAND_97 = {1{`RANDOM}};
-  way_status_out_81 = _RAND_97[0:0];
+  way_status_out_75 = _RAND_97[0:0];
   _RAND_98 = {1{`RANDOM}};
-  way_status_out_82 = _RAND_98[0:0];
+  way_status_out_76 = _RAND_98[0:0];
   _RAND_99 = {1{`RANDOM}};
-  way_status_out_83 = _RAND_99[0:0];
+  way_status_out_77 = _RAND_99[0:0];
   _RAND_100 = {1{`RANDOM}};
-  way_status_out_84 = _RAND_100[0:0];
+  way_status_out_78 = _RAND_100[0:0];
   _RAND_101 = {1{`RANDOM}};
-  way_status_out_85 = _RAND_101[0:0];
+  way_status_out_79 = _RAND_101[0:0];
   _RAND_102 = {1{`RANDOM}};
-  way_status_out_86 = _RAND_102[0:0];
+  way_status_out_80 = _RAND_102[0:0];
   _RAND_103 = {1{`RANDOM}};
-  way_status_out_87 = _RAND_103[0:0];
+  way_status_out_81 = _RAND_103[0:0];
   _RAND_104 = {1{`RANDOM}};
-  way_status_out_88 = _RAND_104[0:0];
+  way_status_out_82 = _RAND_104[0:0];
   _RAND_105 = {1{`RANDOM}};
-  way_status_out_89 = _RAND_105[0:0];
+  way_status_out_83 = _RAND_105[0:0];
   _RAND_106 = {1{`RANDOM}};
-  way_status_out_90 = _RAND_106[0:0];
+  way_status_out_84 = _RAND_106[0:0];
   _RAND_107 = {1{`RANDOM}};
-  way_status_out_91 = _RAND_107[0:0];
+  way_status_out_85 = _RAND_107[0:0];
   _RAND_108 = {1{`RANDOM}};
-  way_status_out_92 = _RAND_108[0:0];
+  way_status_out_86 = _RAND_108[0:0];
   _RAND_109 = {1{`RANDOM}};
-  way_status_out_93 = _RAND_109[0:0];
+  way_status_out_87 = _RAND_109[0:0];
   _RAND_110 = {1{`RANDOM}};
-  way_status_out_94 = _RAND_110[0:0];
+  way_status_out_88 = _RAND_110[0:0];
   _RAND_111 = {1{`RANDOM}};
-  way_status_out_95 = _RAND_111[0:0];
+  way_status_out_89 = _RAND_111[0:0];
   _RAND_112 = {1{`RANDOM}};
-  way_status_out_96 = _RAND_112[0:0];
+  way_status_out_90 = _RAND_112[0:0];
   _RAND_113 = {1{`RANDOM}};
-  way_status_out_97 = _RAND_113[0:0];
+  way_status_out_91 = _RAND_113[0:0];
   _RAND_114 = {1{`RANDOM}};
-  way_status_out_98 = _RAND_114[0:0];
+  way_status_out_92 = _RAND_114[0:0];
   _RAND_115 = {1{`RANDOM}};
-  way_status_out_99 = _RAND_115[0:0];
+  way_status_out_93 = _RAND_115[0:0];
   _RAND_116 = {1{`RANDOM}};
-  way_status_out_100 = _RAND_116[0:0];
+  way_status_out_94 = _RAND_116[0:0];
   _RAND_117 = {1{`RANDOM}};
-  way_status_out_101 = _RAND_117[0:0];
+  way_status_out_95 = _RAND_117[0:0];
   _RAND_118 = {1{`RANDOM}};
-  way_status_out_102 = _RAND_118[0:0];
+  way_status_out_96 = _RAND_118[0:0];
   _RAND_119 = {1{`RANDOM}};
-  way_status_out_103 = _RAND_119[0:0];
+  way_status_out_97 = _RAND_119[0:0];
   _RAND_120 = {1{`RANDOM}};
-  way_status_out_104 = _RAND_120[0:0];
+  way_status_out_98 = _RAND_120[0:0];
   _RAND_121 = {1{`RANDOM}};
-  way_status_out_105 = _RAND_121[0:0];
+  way_status_out_99 = _RAND_121[0:0];
   _RAND_122 = {1{`RANDOM}};
-  way_status_out_106 = _RAND_122[0:0];
+  way_status_out_100 = _RAND_122[0:0];
   _RAND_123 = {1{`RANDOM}};
-  way_status_out_107 = _RAND_123[0:0];
+  way_status_out_101 = _RAND_123[0:0];
   _RAND_124 = {1{`RANDOM}};
-  way_status_out_108 = _RAND_124[0:0];
+  way_status_out_102 = _RAND_124[0:0];
   _RAND_125 = {1{`RANDOM}};
-  way_status_out_109 = _RAND_125[0:0];
+  way_status_out_103 = _RAND_125[0:0];
   _RAND_126 = {1{`RANDOM}};
-  way_status_out_110 = _RAND_126[0:0];
+  way_status_out_104 = _RAND_126[0:0];
   _RAND_127 = {1{`RANDOM}};
-  way_status_out_111 = _RAND_127[0:0];
+  way_status_out_105 = _RAND_127[0:0];
   _RAND_128 = {1{`RANDOM}};
-  way_status_out_112 = _RAND_128[0:0];
+  way_status_out_106 = _RAND_128[0:0];
   _RAND_129 = {1{`RANDOM}};
-  way_status_out_113 = _RAND_129[0:0];
+  way_status_out_107 = _RAND_129[0:0];
   _RAND_130 = {1{`RANDOM}};
-  way_status_out_114 = _RAND_130[0:0];
+  way_status_out_108 = _RAND_130[0:0];
   _RAND_131 = {1{`RANDOM}};
-  way_status_out_115 = _RAND_131[0:0];
+  way_status_out_109 = _RAND_131[0:0];
   _RAND_132 = {1{`RANDOM}};
-  way_status_out_116 = _RAND_132[0:0];
+  way_status_out_110 = _RAND_132[0:0];
   _RAND_133 = {1{`RANDOM}};
-  way_status_out_117 = _RAND_133[0:0];
+  way_status_out_111 = _RAND_133[0:0];
   _RAND_134 = {1{`RANDOM}};
-  way_status_out_118 = _RAND_134[0:0];
+  way_status_out_112 = _RAND_134[0:0];
   _RAND_135 = {1{`RANDOM}};
-  way_status_out_119 = _RAND_135[0:0];
+  way_status_out_113 = _RAND_135[0:0];
   _RAND_136 = {1{`RANDOM}};
-  way_status_out_120 = _RAND_136[0:0];
+  way_status_out_114 = _RAND_136[0:0];
   _RAND_137 = {1{`RANDOM}};
-  way_status_out_121 = _RAND_137[0:0];
+  way_status_out_115 = _RAND_137[0:0];
   _RAND_138 = {1{`RANDOM}};
-  way_status_out_122 = _RAND_138[0:0];
+  way_status_out_116 = _RAND_138[0:0];
   _RAND_139 = {1{`RANDOM}};
-  way_status_out_123 = _RAND_139[0:0];
+  way_status_out_117 = _RAND_139[0:0];
   _RAND_140 = {1{`RANDOM}};
-  way_status_out_124 = _RAND_140[0:0];
+  way_status_out_118 = _RAND_140[0:0];
   _RAND_141 = {1{`RANDOM}};
-  way_status_out_125 = _RAND_141[0:0];
+  way_status_out_119 = _RAND_141[0:0];
   _RAND_142 = {1{`RANDOM}};
-  way_status_out_126 = _RAND_142[0:0];
+  way_status_out_120 = _RAND_142[0:0];
   _RAND_143 = {1{`RANDOM}};
-  way_status_out_127 = _RAND_143[0:0];
+  way_status_out_121 = _RAND_143[0:0];
   _RAND_144 = {1{`RANDOM}};
-  way_status_mb_ff = _RAND_144[0:0];
+  way_status_out_122 = _RAND_144[0:0];
   _RAND_145 = {1{`RANDOM}};
-  tagv_mb_ff = _RAND_145[1:0];
+  way_status_out_123 = _RAND_145[0:0];
   _RAND_146 = {1{`RANDOM}};
-  reset_ic_ff = _RAND_146[0:0];
+  way_status_out_124 = _RAND_146[0:0];
   _RAND_147 = {1{`RANDOM}};
-  fetch_uncacheable_ff = _RAND_147[0:0];
+  way_status_out_125 = _RAND_147[0:0];
   _RAND_148 = {1{`RANDOM}};
-  miss_addr = _RAND_148[25:0];
+  way_status_out_126 = _RAND_148[0:0];
   _RAND_149 = {1{`RANDOM}};
-  ifc_region_acc_fault_f = _RAND_149[0:0];
+  way_status_out_127 = _RAND_149[0:0];
   _RAND_150 = {1{`RANDOM}};
-  bus_rd_addr_count = _RAND_150[2:0];
+  tagv_mb_scnd_ff = _RAND_150[1:0];
   _RAND_151 = {1{`RANDOM}};
-  ic_act_miss_f_delayed = _RAND_151[0:0];
+  uncacheable_miss_scnd_ff = _RAND_151[0:0];
   _RAND_152 = {1{`RANDOM}};
-  ic_crit_wd_rdy_new_ff = _RAND_152[0:0];
+  imb_scnd_ff = _RAND_152[30:0];
   _RAND_153 = {1{`RANDOM}};
-  ic_miss_buff_data_error = _RAND_153[7:0];
+  ifu_bus_rid_ff = _RAND_153[2:0];
   _RAND_154 = {1{`RANDOM}};
-  ic_debug_ict_array_sel_ff = _RAND_154[0:0];
+  ifu_bus_rresp_ff = _RAND_154[1:0];
   _RAND_155 = {1{`RANDOM}};
-  ic_tag_valid_out_1_0 = _RAND_155[0:0];
+  ifu_wr_data_comb_err_ff = _RAND_155[0:0];
   _RAND_156 = {1{`RANDOM}};
-  ic_tag_valid_out_1_1 = _RAND_156[0:0];
+  way_status_mb_ff = _RAND_156[0:0];
   _RAND_157 = {1{`RANDOM}};
-  ic_tag_valid_out_1_2 = _RAND_157[0:0];
+  tagv_mb_ff = _RAND_157[1:0];
   _RAND_158 = {1{`RANDOM}};
-  ic_tag_valid_out_1_3 = _RAND_158[0:0];
+  reset_ic_ff = _RAND_158[0:0];
   _RAND_159 = {1{`RANDOM}};
-  ic_tag_valid_out_1_4 = _RAND_159[0:0];
+  fetch_uncacheable_ff = _RAND_159[0:0];
   _RAND_160 = {1{`RANDOM}};
-  ic_tag_valid_out_1_5 = _RAND_160[0:0];
+  miss_addr = _RAND_160[25:0];
   _RAND_161 = {1{`RANDOM}};
-  ic_tag_valid_out_1_6 = _RAND_161[0:0];
+  ifc_region_acc_fault_f = _RAND_161[0:0];
   _RAND_162 = {1{`RANDOM}};
-  ic_tag_valid_out_1_7 = _RAND_162[0:0];
+  bus_rd_addr_count = _RAND_162[2:0];
   _RAND_163 = {1{`RANDOM}};
-  ic_tag_valid_out_1_8 = _RAND_163[0:0];
-  _RAND_164 = {1{`RANDOM}};
-  ic_tag_valid_out_1_9 = _RAND_164[0:0];
+  ic_act_miss_f_delayed = _RAND_163[0:0];
+  _RAND_164 = {2{`RANDOM}};
+  ifu_bus_rdata_ff = _RAND_164[63:0];
   _RAND_165 = {1{`RANDOM}};
-  ic_tag_valid_out_1_10 = _RAND_165[0:0];
+  ic_miss_buff_data_0 = _RAND_165[31:0];
   _RAND_166 = {1{`RANDOM}};
-  ic_tag_valid_out_1_11 = _RAND_166[0:0];
+  ic_miss_buff_data_1 = _RAND_166[31:0];
   _RAND_167 = {1{`RANDOM}};
-  ic_tag_valid_out_1_12 = _RAND_167[0:0];
+  ic_miss_buff_data_2 = _RAND_167[31:0];
   _RAND_168 = {1{`RANDOM}};
-  ic_tag_valid_out_1_13 = _RAND_168[0:0];
+  ic_miss_buff_data_3 = _RAND_168[31:0];
   _RAND_169 = {1{`RANDOM}};
-  ic_tag_valid_out_1_14 = _RAND_169[0:0];
+  ic_miss_buff_data_4 = _RAND_169[31:0];
   _RAND_170 = {1{`RANDOM}};
-  ic_tag_valid_out_1_15 = _RAND_170[0:0];
+  ic_miss_buff_data_5 = _RAND_170[31:0];
   _RAND_171 = {1{`RANDOM}};
-  ic_tag_valid_out_1_16 = _RAND_171[0:0];
+  ic_miss_buff_data_6 = _RAND_171[31:0];
   _RAND_172 = {1{`RANDOM}};
-  ic_tag_valid_out_1_17 = _RAND_172[0:0];
+  ic_miss_buff_data_7 = _RAND_172[31:0];
   _RAND_173 = {1{`RANDOM}};
-  ic_tag_valid_out_1_18 = _RAND_173[0:0];
+  ic_miss_buff_data_8 = _RAND_173[31:0];
   _RAND_174 = {1{`RANDOM}};
-  ic_tag_valid_out_1_19 = _RAND_174[0:0];
+  ic_miss_buff_data_9 = _RAND_174[31:0];
   _RAND_175 = {1{`RANDOM}};
-  ic_tag_valid_out_1_20 = _RAND_175[0:0];
+  ic_miss_buff_data_10 = _RAND_175[31:0];
   _RAND_176 = {1{`RANDOM}};
-  ic_tag_valid_out_1_21 = _RAND_176[0:0];
+  ic_miss_buff_data_11 = _RAND_176[31:0];
   _RAND_177 = {1{`RANDOM}};
-  ic_tag_valid_out_1_22 = _RAND_177[0:0];
+  ic_miss_buff_data_12 = _RAND_177[31:0];
   _RAND_178 = {1{`RANDOM}};
-  ic_tag_valid_out_1_23 = _RAND_178[0:0];
+  ic_miss_buff_data_13 = _RAND_178[31:0];
   _RAND_179 = {1{`RANDOM}};
-  ic_tag_valid_out_1_24 = _RAND_179[0:0];
+  ic_miss_buff_data_14 = _RAND_179[31:0];
   _RAND_180 = {1{`RANDOM}};
-  ic_tag_valid_out_1_25 = _RAND_180[0:0];
+  ic_miss_buff_data_15 = _RAND_180[31:0];
   _RAND_181 = {1{`RANDOM}};
-  ic_tag_valid_out_1_26 = _RAND_181[0:0];
+  ic_crit_wd_rdy_new_ff = _RAND_181[0:0];
   _RAND_182 = {1{`RANDOM}};
-  ic_tag_valid_out_1_27 = _RAND_182[0:0];
+  ic_miss_buff_data_error = _RAND_182[7:0];
   _RAND_183 = {1{`RANDOM}};
-  ic_tag_valid_out_1_28 = _RAND_183[0:0];
+  ic_debug_ict_array_sel_ff = _RAND_183[0:0];
   _RAND_184 = {1{`RANDOM}};
-  ic_tag_valid_out_1_29 = _RAND_184[0:0];
+  ic_tag_valid_out_1_0 = _RAND_184[0:0];
   _RAND_185 = {1{`RANDOM}};
-  ic_tag_valid_out_1_30 = _RAND_185[0:0];
+  ic_tag_valid_out_1_1 = _RAND_185[0:0];
   _RAND_186 = {1{`RANDOM}};
-  ic_tag_valid_out_1_31 = _RAND_186[0:0];
+  ic_tag_valid_out_1_2 = _RAND_186[0:0];
   _RAND_187 = {1{`RANDOM}};
-  ic_tag_valid_out_1_32 = _RAND_187[0:0];
+  ic_tag_valid_out_1_3 = _RAND_187[0:0];
   _RAND_188 = {1{`RANDOM}};
-  ic_tag_valid_out_1_33 = _RAND_188[0:0];
+  ic_tag_valid_out_1_4 = _RAND_188[0:0];
   _RAND_189 = {1{`RANDOM}};
-  ic_tag_valid_out_1_34 = _RAND_189[0:0];
+  ic_tag_valid_out_1_5 = _RAND_189[0:0];
   _RAND_190 = {1{`RANDOM}};
-  ic_tag_valid_out_1_35 = _RAND_190[0:0];
+  ic_tag_valid_out_1_6 = _RAND_190[0:0];
   _RAND_191 = {1{`RANDOM}};
-  ic_tag_valid_out_1_36 = _RAND_191[0:0];
+  ic_tag_valid_out_1_7 = _RAND_191[0:0];
   _RAND_192 = {1{`RANDOM}};
-  ic_tag_valid_out_1_37 = _RAND_192[0:0];
+  ic_tag_valid_out_1_8 = _RAND_192[0:0];
   _RAND_193 = {1{`RANDOM}};
-  ic_tag_valid_out_1_38 = _RAND_193[0:0];
+  ic_tag_valid_out_1_9 = _RAND_193[0:0];
   _RAND_194 = {1{`RANDOM}};
-  ic_tag_valid_out_1_39 = _RAND_194[0:0];
+  ic_tag_valid_out_1_10 = _RAND_194[0:0];
   _RAND_195 = {1{`RANDOM}};
-  ic_tag_valid_out_1_40 = _RAND_195[0:0];
+  ic_tag_valid_out_1_11 = _RAND_195[0:0];
   _RAND_196 = {1{`RANDOM}};
-  ic_tag_valid_out_1_41 = _RAND_196[0:0];
+  ic_tag_valid_out_1_12 = _RAND_196[0:0];
   _RAND_197 = {1{`RANDOM}};
-  ic_tag_valid_out_1_42 = _RAND_197[0:0];
+  ic_tag_valid_out_1_13 = _RAND_197[0:0];
   _RAND_198 = {1{`RANDOM}};
-  ic_tag_valid_out_1_43 = _RAND_198[0:0];
+  ic_tag_valid_out_1_14 = _RAND_198[0:0];
   _RAND_199 = {1{`RANDOM}};
-  ic_tag_valid_out_1_44 = _RAND_199[0:0];
+  ic_tag_valid_out_1_15 = _RAND_199[0:0];
   _RAND_200 = {1{`RANDOM}};
-  ic_tag_valid_out_1_45 = _RAND_200[0:0];
+  ic_tag_valid_out_1_16 = _RAND_200[0:0];
   _RAND_201 = {1{`RANDOM}};
-  ic_tag_valid_out_1_46 = _RAND_201[0:0];
+  ic_tag_valid_out_1_17 = _RAND_201[0:0];
   _RAND_202 = {1{`RANDOM}};
-  ic_tag_valid_out_1_47 = _RAND_202[0:0];
+  ic_tag_valid_out_1_18 = _RAND_202[0:0];
   _RAND_203 = {1{`RANDOM}};
-  ic_tag_valid_out_1_48 = _RAND_203[0:0];
+  ic_tag_valid_out_1_19 = _RAND_203[0:0];
   _RAND_204 = {1{`RANDOM}};
-  ic_tag_valid_out_1_49 = _RAND_204[0:0];
+  ic_tag_valid_out_1_20 = _RAND_204[0:0];
   _RAND_205 = {1{`RANDOM}};
-  ic_tag_valid_out_1_50 = _RAND_205[0:0];
+  ic_tag_valid_out_1_21 = _RAND_205[0:0];
   _RAND_206 = {1{`RANDOM}};
-  ic_tag_valid_out_1_51 = _RAND_206[0:0];
+  ic_tag_valid_out_1_22 = _RAND_206[0:0];
   _RAND_207 = {1{`RANDOM}};
-  ic_tag_valid_out_1_52 = _RAND_207[0:0];
+  ic_tag_valid_out_1_23 = _RAND_207[0:0];
   _RAND_208 = {1{`RANDOM}};
-  ic_tag_valid_out_1_53 = _RAND_208[0:0];
+  ic_tag_valid_out_1_24 = _RAND_208[0:0];
   _RAND_209 = {1{`RANDOM}};
-  ic_tag_valid_out_1_54 = _RAND_209[0:0];
+  ic_tag_valid_out_1_25 = _RAND_209[0:0];
   _RAND_210 = {1{`RANDOM}};
-  ic_tag_valid_out_1_55 = _RAND_210[0:0];
+  ic_tag_valid_out_1_26 = _RAND_210[0:0];
   _RAND_211 = {1{`RANDOM}};
-  ic_tag_valid_out_1_56 = _RAND_211[0:0];
+  ic_tag_valid_out_1_27 = _RAND_211[0:0];
   _RAND_212 = {1{`RANDOM}};
-  ic_tag_valid_out_1_57 = _RAND_212[0:0];
+  ic_tag_valid_out_1_28 = _RAND_212[0:0];
   _RAND_213 = {1{`RANDOM}};
-  ic_tag_valid_out_1_58 = _RAND_213[0:0];
+  ic_tag_valid_out_1_29 = _RAND_213[0:0];
   _RAND_214 = {1{`RANDOM}};
-  ic_tag_valid_out_1_59 = _RAND_214[0:0];
+  ic_tag_valid_out_1_30 = _RAND_214[0:0];
   _RAND_215 = {1{`RANDOM}};
-  ic_tag_valid_out_1_60 = _RAND_215[0:0];
+  ic_tag_valid_out_1_31 = _RAND_215[0:0];
   _RAND_216 = {1{`RANDOM}};
-  ic_tag_valid_out_1_61 = _RAND_216[0:0];
+  ic_tag_valid_out_1_32 = _RAND_216[0:0];
   _RAND_217 = {1{`RANDOM}};
-  ic_tag_valid_out_1_62 = _RAND_217[0:0];
+  ic_tag_valid_out_1_33 = _RAND_217[0:0];
   _RAND_218 = {1{`RANDOM}};
-  ic_tag_valid_out_1_63 = _RAND_218[0:0];
+  ic_tag_valid_out_1_34 = _RAND_218[0:0];
   _RAND_219 = {1{`RANDOM}};
-  ic_tag_valid_out_1_64 = _RAND_219[0:0];
+  ic_tag_valid_out_1_35 = _RAND_219[0:0];
   _RAND_220 = {1{`RANDOM}};
-  ic_tag_valid_out_1_65 = _RAND_220[0:0];
+  ic_tag_valid_out_1_36 = _RAND_220[0:0];
   _RAND_221 = {1{`RANDOM}};
-  ic_tag_valid_out_1_66 = _RAND_221[0:0];
+  ic_tag_valid_out_1_37 = _RAND_221[0:0];
   _RAND_222 = {1{`RANDOM}};
-  ic_tag_valid_out_1_67 = _RAND_222[0:0];
+  ic_tag_valid_out_1_38 = _RAND_222[0:0];
   _RAND_223 = {1{`RANDOM}};
-  ic_tag_valid_out_1_68 = _RAND_223[0:0];
+  ic_tag_valid_out_1_39 = _RAND_223[0:0];
   _RAND_224 = {1{`RANDOM}};
-  ic_tag_valid_out_1_69 = _RAND_224[0:0];
+  ic_tag_valid_out_1_40 = _RAND_224[0:0];
   _RAND_225 = {1{`RANDOM}};
-  ic_tag_valid_out_1_70 = _RAND_225[0:0];
+  ic_tag_valid_out_1_41 = _RAND_225[0:0];
   _RAND_226 = {1{`RANDOM}};
-  ic_tag_valid_out_1_71 = _RAND_226[0:0];
+  ic_tag_valid_out_1_42 = _RAND_226[0:0];
   _RAND_227 = {1{`RANDOM}};
-  ic_tag_valid_out_1_72 = _RAND_227[0:0];
+  ic_tag_valid_out_1_43 = _RAND_227[0:0];
   _RAND_228 = {1{`RANDOM}};
-  ic_tag_valid_out_1_73 = _RAND_228[0:0];
+  ic_tag_valid_out_1_44 = _RAND_228[0:0];
   _RAND_229 = {1{`RANDOM}};
-  ic_tag_valid_out_1_74 = _RAND_229[0:0];
+  ic_tag_valid_out_1_45 = _RAND_229[0:0];
   _RAND_230 = {1{`RANDOM}};
-  ic_tag_valid_out_1_75 = _RAND_230[0:0];
+  ic_tag_valid_out_1_46 = _RAND_230[0:0];
   _RAND_231 = {1{`RANDOM}};
-  ic_tag_valid_out_1_76 = _RAND_231[0:0];
+  ic_tag_valid_out_1_47 = _RAND_231[0:0];
   _RAND_232 = {1{`RANDOM}};
-  ic_tag_valid_out_1_77 = _RAND_232[0:0];
+  ic_tag_valid_out_1_48 = _RAND_232[0:0];
   _RAND_233 = {1{`RANDOM}};
-  ic_tag_valid_out_1_78 = _RAND_233[0:0];
+  ic_tag_valid_out_1_49 = _RAND_233[0:0];
   _RAND_234 = {1{`RANDOM}};
-  ic_tag_valid_out_1_79 = _RAND_234[0:0];
+  ic_tag_valid_out_1_50 = _RAND_234[0:0];
   _RAND_235 = {1{`RANDOM}};
-  ic_tag_valid_out_1_80 = _RAND_235[0:0];
+  ic_tag_valid_out_1_51 = _RAND_235[0:0];
   _RAND_236 = {1{`RANDOM}};
-  ic_tag_valid_out_1_81 = _RAND_236[0:0];
+  ic_tag_valid_out_1_52 = _RAND_236[0:0];
   _RAND_237 = {1{`RANDOM}};
-  ic_tag_valid_out_1_82 = _RAND_237[0:0];
+  ic_tag_valid_out_1_53 = _RAND_237[0:0];
   _RAND_238 = {1{`RANDOM}};
-  ic_tag_valid_out_1_83 = _RAND_238[0:0];
+  ic_tag_valid_out_1_54 = _RAND_238[0:0];
   _RAND_239 = {1{`RANDOM}};
-  ic_tag_valid_out_1_84 = _RAND_239[0:0];
+  ic_tag_valid_out_1_55 = _RAND_239[0:0];
   _RAND_240 = {1{`RANDOM}};
-  ic_tag_valid_out_1_85 = _RAND_240[0:0];
+  ic_tag_valid_out_1_56 = _RAND_240[0:0];
   _RAND_241 = {1{`RANDOM}};
-  ic_tag_valid_out_1_86 = _RAND_241[0:0];
+  ic_tag_valid_out_1_57 = _RAND_241[0:0];
   _RAND_242 = {1{`RANDOM}};
-  ic_tag_valid_out_1_87 = _RAND_242[0:0];
+  ic_tag_valid_out_1_58 = _RAND_242[0:0];
   _RAND_243 = {1{`RANDOM}};
-  ic_tag_valid_out_1_88 = _RAND_243[0:0];
+  ic_tag_valid_out_1_59 = _RAND_243[0:0];
   _RAND_244 = {1{`RANDOM}};
-  ic_tag_valid_out_1_89 = _RAND_244[0:0];
+  ic_tag_valid_out_1_60 = _RAND_244[0:0];
   _RAND_245 = {1{`RANDOM}};
-  ic_tag_valid_out_1_90 = _RAND_245[0:0];
+  ic_tag_valid_out_1_61 = _RAND_245[0:0];
   _RAND_246 = {1{`RANDOM}};
-  ic_tag_valid_out_1_91 = _RAND_246[0:0];
+  ic_tag_valid_out_1_62 = _RAND_246[0:0];
   _RAND_247 = {1{`RANDOM}};
-  ic_tag_valid_out_1_92 = _RAND_247[0:0];
+  ic_tag_valid_out_1_63 = _RAND_247[0:0];
   _RAND_248 = {1{`RANDOM}};
-  ic_tag_valid_out_1_93 = _RAND_248[0:0];
+  ic_tag_valid_out_1_64 = _RAND_248[0:0];
   _RAND_249 = {1{`RANDOM}};
-  ic_tag_valid_out_1_94 = _RAND_249[0:0];
+  ic_tag_valid_out_1_65 = _RAND_249[0:0];
   _RAND_250 = {1{`RANDOM}};
-  ic_tag_valid_out_1_95 = _RAND_250[0:0];
+  ic_tag_valid_out_1_66 = _RAND_250[0:0];
   _RAND_251 = {1{`RANDOM}};
-  ic_tag_valid_out_1_96 = _RAND_251[0:0];
+  ic_tag_valid_out_1_67 = _RAND_251[0:0];
   _RAND_252 = {1{`RANDOM}};
-  ic_tag_valid_out_1_97 = _RAND_252[0:0];
+  ic_tag_valid_out_1_68 = _RAND_252[0:0];
   _RAND_253 = {1{`RANDOM}};
-  ic_tag_valid_out_1_98 = _RAND_253[0:0];
+  ic_tag_valid_out_1_69 = _RAND_253[0:0];
   _RAND_254 = {1{`RANDOM}};
-  ic_tag_valid_out_1_99 = _RAND_254[0:0];
+  ic_tag_valid_out_1_70 = _RAND_254[0:0];
   _RAND_255 = {1{`RANDOM}};
-  ic_tag_valid_out_1_100 = _RAND_255[0:0];
+  ic_tag_valid_out_1_71 = _RAND_255[0:0];
   _RAND_256 = {1{`RANDOM}};
-  ic_tag_valid_out_1_101 = _RAND_256[0:0];
+  ic_tag_valid_out_1_72 = _RAND_256[0:0];
   _RAND_257 = {1{`RANDOM}};
-  ic_tag_valid_out_1_102 = _RAND_257[0:0];
+  ic_tag_valid_out_1_73 = _RAND_257[0:0];
   _RAND_258 = {1{`RANDOM}};
-  ic_tag_valid_out_1_103 = _RAND_258[0:0];
+  ic_tag_valid_out_1_74 = _RAND_258[0:0];
   _RAND_259 = {1{`RANDOM}};
-  ic_tag_valid_out_1_104 = _RAND_259[0:0];
+  ic_tag_valid_out_1_75 = _RAND_259[0:0];
   _RAND_260 = {1{`RANDOM}};
-  ic_tag_valid_out_1_105 = _RAND_260[0:0];
+  ic_tag_valid_out_1_76 = _RAND_260[0:0];
   _RAND_261 = {1{`RANDOM}};
-  ic_tag_valid_out_1_106 = _RAND_261[0:0];
+  ic_tag_valid_out_1_77 = _RAND_261[0:0];
   _RAND_262 = {1{`RANDOM}};
-  ic_tag_valid_out_1_107 = _RAND_262[0:0];
+  ic_tag_valid_out_1_78 = _RAND_262[0:0];
   _RAND_263 = {1{`RANDOM}};
-  ic_tag_valid_out_1_108 = _RAND_263[0:0];
+  ic_tag_valid_out_1_79 = _RAND_263[0:0];
   _RAND_264 = {1{`RANDOM}};
-  ic_tag_valid_out_1_109 = _RAND_264[0:0];
+  ic_tag_valid_out_1_80 = _RAND_264[0:0];
   _RAND_265 = {1{`RANDOM}};
-  ic_tag_valid_out_1_110 = _RAND_265[0:0];
+  ic_tag_valid_out_1_81 = _RAND_265[0:0];
   _RAND_266 = {1{`RANDOM}};
-  ic_tag_valid_out_1_111 = _RAND_266[0:0];
+  ic_tag_valid_out_1_82 = _RAND_266[0:0];
   _RAND_267 = {1{`RANDOM}};
-  ic_tag_valid_out_1_112 = _RAND_267[0:0];
+  ic_tag_valid_out_1_83 = _RAND_267[0:0];
   _RAND_268 = {1{`RANDOM}};
-  ic_tag_valid_out_1_113 = _RAND_268[0:0];
+  ic_tag_valid_out_1_84 = _RAND_268[0:0];
   _RAND_269 = {1{`RANDOM}};
-  ic_tag_valid_out_1_114 = _RAND_269[0:0];
+  ic_tag_valid_out_1_85 = _RAND_269[0:0];
   _RAND_270 = {1{`RANDOM}};
-  ic_tag_valid_out_1_115 = _RAND_270[0:0];
+  ic_tag_valid_out_1_86 = _RAND_270[0:0];
   _RAND_271 = {1{`RANDOM}};
-  ic_tag_valid_out_1_116 = _RAND_271[0:0];
+  ic_tag_valid_out_1_87 = _RAND_271[0:0];
   _RAND_272 = {1{`RANDOM}};
-  ic_tag_valid_out_1_117 = _RAND_272[0:0];
+  ic_tag_valid_out_1_88 = _RAND_272[0:0];
   _RAND_273 = {1{`RANDOM}};
-  ic_tag_valid_out_1_118 = _RAND_273[0:0];
+  ic_tag_valid_out_1_89 = _RAND_273[0:0];
   _RAND_274 = {1{`RANDOM}};
-  ic_tag_valid_out_1_119 = _RAND_274[0:0];
+  ic_tag_valid_out_1_90 = _RAND_274[0:0];
   _RAND_275 = {1{`RANDOM}};
-  ic_tag_valid_out_1_120 = _RAND_275[0:0];
+  ic_tag_valid_out_1_91 = _RAND_275[0:0];
   _RAND_276 = {1{`RANDOM}};
-  ic_tag_valid_out_1_121 = _RAND_276[0:0];
+  ic_tag_valid_out_1_92 = _RAND_276[0:0];
   _RAND_277 = {1{`RANDOM}};
-  ic_tag_valid_out_1_122 = _RAND_277[0:0];
+  ic_tag_valid_out_1_93 = _RAND_277[0:0];
   _RAND_278 = {1{`RANDOM}};
-  ic_tag_valid_out_1_123 = _RAND_278[0:0];
+  ic_tag_valid_out_1_94 = _RAND_278[0:0];
   _RAND_279 = {1{`RANDOM}};
-  ic_tag_valid_out_1_124 = _RAND_279[0:0];
+  ic_tag_valid_out_1_95 = _RAND_279[0:0];
   _RAND_280 = {1{`RANDOM}};
-  ic_tag_valid_out_1_125 = _RAND_280[0:0];
+  ic_tag_valid_out_1_96 = _RAND_280[0:0];
   _RAND_281 = {1{`RANDOM}};
-  ic_tag_valid_out_1_126 = _RAND_281[0:0];
+  ic_tag_valid_out_1_97 = _RAND_281[0:0];
   _RAND_282 = {1{`RANDOM}};
-  ic_tag_valid_out_1_127 = _RAND_282[0:0];
+  ic_tag_valid_out_1_98 = _RAND_282[0:0];
   _RAND_283 = {1{`RANDOM}};
-  ic_tag_valid_out_0_0 = _RAND_283[0:0];
+  ic_tag_valid_out_1_99 = _RAND_283[0:0];
   _RAND_284 = {1{`RANDOM}};
-  ic_tag_valid_out_0_1 = _RAND_284[0:0];
+  ic_tag_valid_out_1_100 = _RAND_284[0:0];
   _RAND_285 = {1{`RANDOM}};
-  ic_tag_valid_out_0_2 = _RAND_285[0:0];
+  ic_tag_valid_out_1_101 = _RAND_285[0:0];
   _RAND_286 = {1{`RANDOM}};
-  ic_tag_valid_out_0_3 = _RAND_286[0:0];
+  ic_tag_valid_out_1_102 = _RAND_286[0:0];
   _RAND_287 = {1{`RANDOM}};
-  ic_tag_valid_out_0_4 = _RAND_287[0:0];
+  ic_tag_valid_out_1_103 = _RAND_287[0:0];
   _RAND_288 = {1{`RANDOM}};
-  ic_tag_valid_out_0_5 = _RAND_288[0:0];
+  ic_tag_valid_out_1_104 = _RAND_288[0:0];
   _RAND_289 = {1{`RANDOM}};
-  ic_tag_valid_out_0_6 = _RAND_289[0:0];
+  ic_tag_valid_out_1_105 = _RAND_289[0:0];
   _RAND_290 = {1{`RANDOM}};
-  ic_tag_valid_out_0_7 = _RAND_290[0:0];
+  ic_tag_valid_out_1_106 = _RAND_290[0:0];
   _RAND_291 = {1{`RANDOM}};
-  ic_tag_valid_out_0_8 = _RAND_291[0:0];
+  ic_tag_valid_out_1_107 = _RAND_291[0:0];
   _RAND_292 = {1{`RANDOM}};
-  ic_tag_valid_out_0_9 = _RAND_292[0:0];
+  ic_tag_valid_out_1_108 = _RAND_292[0:0];
   _RAND_293 = {1{`RANDOM}};
-  ic_tag_valid_out_0_10 = _RAND_293[0:0];
+  ic_tag_valid_out_1_109 = _RAND_293[0:0];
   _RAND_294 = {1{`RANDOM}};
-  ic_tag_valid_out_0_11 = _RAND_294[0:0];
+  ic_tag_valid_out_1_110 = _RAND_294[0:0];
   _RAND_295 = {1{`RANDOM}};
-  ic_tag_valid_out_0_12 = _RAND_295[0:0];
+  ic_tag_valid_out_1_111 = _RAND_295[0:0];
   _RAND_296 = {1{`RANDOM}};
-  ic_tag_valid_out_0_13 = _RAND_296[0:0];
+  ic_tag_valid_out_1_112 = _RAND_296[0:0];
   _RAND_297 = {1{`RANDOM}};
-  ic_tag_valid_out_0_14 = _RAND_297[0:0];
+  ic_tag_valid_out_1_113 = _RAND_297[0:0];
   _RAND_298 = {1{`RANDOM}};
-  ic_tag_valid_out_0_15 = _RAND_298[0:0];
+  ic_tag_valid_out_1_114 = _RAND_298[0:0];
   _RAND_299 = {1{`RANDOM}};
-  ic_tag_valid_out_0_16 = _RAND_299[0:0];
+  ic_tag_valid_out_1_115 = _RAND_299[0:0];
   _RAND_300 = {1{`RANDOM}};
-  ic_tag_valid_out_0_17 = _RAND_300[0:0];
+  ic_tag_valid_out_1_116 = _RAND_300[0:0];
   _RAND_301 = {1{`RANDOM}};
-  ic_tag_valid_out_0_18 = _RAND_301[0:0];
+  ic_tag_valid_out_1_117 = _RAND_301[0:0];
   _RAND_302 = {1{`RANDOM}};
-  ic_tag_valid_out_0_19 = _RAND_302[0:0];
+  ic_tag_valid_out_1_118 = _RAND_302[0:0];
   _RAND_303 = {1{`RANDOM}};
-  ic_tag_valid_out_0_20 = _RAND_303[0:0];
+  ic_tag_valid_out_1_119 = _RAND_303[0:0];
   _RAND_304 = {1{`RANDOM}};
-  ic_tag_valid_out_0_21 = _RAND_304[0:0];
+  ic_tag_valid_out_1_120 = _RAND_304[0:0];
   _RAND_305 = {1{`RANDOM}};
-  ic_tag_valid_out_0_22 = _RAND_305[0:0];
+  ic_tag_valid_out_1_121 = _RAND_305[0:0];
   _RAND_306 = {1{`RANDOM}};
-  ic_tag_valid_out_0_23 = _RAND_306[0:0];
+  ic_tag_valid_out_1_122 = _RAND_306[0:0];
   _RAND_307 = {1{`RANDOM}};
-  ic_tag_valid_out_0_24 = _RAND_307[0:0];
+  ic_tag_valid_out_1_123 = _RAND_307[0:0];
   _RAND_308 = {1{`RANDOM}};
-  ic_tag_valid_out_0_25 = _RAND_308[0:0];
+  ic_tag_valid_out_1_124 = _RAND_308[0:0];
   _RAND_309 = {1{`RANDOM}};
-  ic_tag_valid_out_0_26 = _RAND_309[0:0];
+  ic_tag_valid_out_1_125 = _RAND_309[0:0];
   _RAND_310 = {1{`RANDOM}};
-  ic_tag_valid_out_0_27 = _RAND_310[0:0];
+  ic_tag_valid_out_1_126 = _RAND_310[0:0];
   _RAND_311 = {1{`RANDOM}};
-  ic_tag_valid_out_0_28 = _RAND_311[0:0];
+  ic_tag_valid_out_1_127 = _RAND_311[0:0];
   _RAND_312 = {1{`RANDOM}};
-  ic_tag_valid_out_0_29 = _RAND_312[0:0];
+  ic_tag_valid_out_0_0 = _RAND_312[0:0];
   _RAND_313 = {1{`RANDOM}};
-  ic_tag_valid_out_0_30 = _RAND_313[0:0];
+  ic_tag_valid_out_0_1 = _RAND_313[0:0];
   _RAND_314 = {1{`RANDOM}};
-  ic_tag_valid_out_0_31 = _RAND_314[0:0];
+  ic_tag_valid_out_0_2 = _RAND_314[0:0];
   _RAND_315 = {1{`RANDOM}};
-  ic_tag_valid_out_0_32 = _RAND_315[0:0];
+  ic_tag_valid_out_0_3 = _RAND_315[0:0];
   _RAND_316 = {1{`RANDOM}};
-  ic_tag_valid_out_0_33 = _RAND_316[0:0];
+  ic_tag_valid_out_0_4 = _RAND_316[0:0];
   _RAND_317 = {1{`RANDOM}};
-  ic_tag_valid_out_0_34 = _RAND_317[0:0];
+  ic_tag_valid_out_0_5 = _RAND_317[0:0];
   _RAND_318 = {1{`RANDOM}};
-  ic_tag_valid_out_0_35 = _RAND_318[0:0];
+  ic_tag_valid_out_0_6 = _RAND_318[0:0];
   _RAND_319 = {1{`RANDOM}};
-  ic_tag_valid_out_0_36 = _RAND_319[0:0];
+  ic_tag_valid_out_0_7 = _RAND_319[0:0];
   _RAND_320 = {1{`RANDOM}};
-  ic_tag_valid_out_0_37 = _RAND_320[0:0];
+  ic_tag_valid_out_0_8 = _RAND_320[0:0];
   _RAND_321 = {1{`RANDOM}};
-  ic_tag_valid_out_0_38 = _RAND_321[0:0];
+  ic_tag_valid_out_0_9 = _RAND_321[0:0];
   _RAND_322 = {1{`RANDOM}};
-  ic_tag_valid_out_0_39 = _RAND_322[0:0];
+  ic_tag_valid_out_0_10 = _RAND_322[0:0];
   _RAND_323 = {1{`RANDOM}};
-  ic_tag_valid_out_0_40 = _RAND_323[0:0];
+  ic_tag_valid_out_0_11 = _RAND_323[0:0];
   _RAND_324 = {1{`RANDOM}};
-  ic_tag_valid_out_0_41 = _RAND_324[0:0];
+  ic_tag_valid_out_0_12 = _RAND_324[0:0];
   _RAND_325 = {1{`RANDOM}};
-  ic_tag_valid_out_0_42 = _RAND_325[0:0];
+  ic_tag_valid_out_0_13 = _RAND_325[0:0];
   _RAND_326 = {1{`RANDOM}};
-  ic_tag_valid_out_0_43 = _RAND_326[0:0];
+  ic_tag_valid_out_0_14 = _RAND_326[0:0];
   _RAND_327 = {1{`RANDOM}};
-  ic_tag_valid_out_0_44 = _RAND_327[0:0];
+  ic_tag_valid_out_0_15 = _RAND_327[0:0];
   _RAND_328 = {1{`RANDOM}};
-  ic_tag_valid_out_0_45 = _RAND_328[0:0];
+  ic_tag_valid_out_0_16 = _RAND_328[0:0];
   _RAND_329 = {1{`RANDOM}};
-  ic_tag_valid_out_0_46 = _RAND_329[0:0];
+  ic_tag_valid_out_0_17 = _RAND_329[0:0];
   _RAND_330 = {1{`RANDOM}};
-  ic_tag_valid_out_0_47 = _RAND_330[0:0];
+  ic_tag_valid_out_0_18 = _RAND_330[0:0];
   _RAND_331 = {1{`RANDOM}};
-  ic_tag_valid_out_0_48 = _RAND_331[0:0];
+  ic_tag_valid_out_0_19 = _RAND_331[0:0];
   _RAND_332 = {1{`RANDOM}};
-  ic_tag_valid_out_0_49 = _RAND_332[0:0];
+  ic_tag_valid_out_0_20 = _RAND_332[0:0];
   _RAND_333 = {1{`RANDOM}};
-  ic_tag_valid_out_0_50 = _RAND_333[0:0];
+  ic_tag_valid_out_0_21 = _RAND_333[0:0];
   _RAND_334 = {1{`RANDOM}};
-  ic_tag_valid_out_0_51 = _RAND_334[0:0];
+  ic_tag_valid_out_0_22 = _RAND_334[0:0];
   _RAND_335 = {1{`RANDOM}};
-  ic_tag_valid_out_0_52 = _RAND_335[0:0];
+  ic_tag_valid_out_0_23 = _RAND_335[0:0];
   _RAND_336 = {1{`RANDOM}};
-  ic_tag_valid_out_0_53 = _RAND_336[0:0];
+  ic_tag_valid_out_0_24 = _RAND_336[0:0];
   _RAND_337 = {1{`RANDOM}};
-  ic_tag_valid_out_0_54 = _RAND_337[0:0];
+  ic_tag_valid_out_0_25 = _RAND_337[0:0];
   _RAND_338 = {1{`RANDOM}};
-  ic_tag_valid_out_0_55 = _RAND_338[0:0];
+  ic_tag_valid_out_0_26 = _RAND_338[0:0];
   _RAND_339 = {1{`RANDOM}};
-  ic_tag_valid_out_0_56 = _RAND_339[0:0];
+  ic_tag_valid_out_0_27 = _RAND_339[0:0];
   _RAND_340 = {1{`RANDOM}};
-  ic_tag_valid_out_0_57 = _RAND_340[0:0];
+  ic_tag_valid_out_0_28 = _RAND_340[0:0];
   _RAND_341 = {1{`RANDOM}};
-  ic_tag_valid_out_0_58 = _RAND_341[0:0];
+  ic_tag_valid_out_0_29 = _RAND_341[0:0];
   _RAND_342 = {1{`RANDOM}};
-  ic_tag_valid_out_0_59 = _RAND_342[0:0];
+  ic_tag_valid_out_0_30 = _RAND_342[0:0];
   _RAND_343 = {1{`RANDOM}};
-  ic_tag_valid_out_0_60 = _RAND_343[0:0];
+  ic_tag_valid_out_0_31 = _RAND_343[0:0];
   _RAND_344 = {1{`RANDOM}};
-  ic_tag_valid_out_0_61 = _RAND_344[0:0];
+  ic_tag_valid_out_0_32 = _RAND_344[0:0];
   _RAND_345 = {1{`RANDOM}};
-  ic_tag_valid_out_0_62 = _RAND_345[0:0];
+  ic_tag_valid_out_0_33 = _RAND_345[0:0];
   _RAND_346 = {1{`RANDOM}};
-  ic_tag_valid_out_0_63 = _RAND_346[0:0];
+  ic_tag_valid_out_0_34 = _RAND_346[0:0];
   _RAND_347 = {1{`RANDOM}};
-  ic_tag_valid_out_0_64 = _RAND_347[0:0];
+  ic_tag_valid_out_0_35 = _RAND_347[0:0];
   _RAND_348 = {1{`RANDOM}};
-  ic_tag_valid_out_0_65 = _RAND_348[0:0];
+  ic_tag_valid_out_0_36 = _RAND_348[0:0];
   _RAND_349 = {1{`RANDOM}};
-  ic_tag_valid_out_0_66 = _RAND_349[0:0];
+  ic_tag_valid_out_0_37 = _RAND_349[0:0];
   _RAND_350 = {1{`RANDOM}};
-  ic_tag_valid_out_0_67 = _RAND_350[0:0];
+  ic_tag_valid_out_0_38 = _RAND_350[0:0];
   _RAND_351 = {1{`RANDOM}};
-  ic_tag_valid_out_0_68 = _RAND_351[0:0];
+  ic_tag_valid_out_0_39 = _RAND_351[0:0];
   _RAND_352 = {1{`RANDOM}};
-  ic_tag_valid_out_0_69 = _RAND_352[0:0];
+  ic_tag_valid_out_0_40 = _RAND_352[0:0];
   _RAND_353 = {1{`RANDOM}};
-  ic_tag_valid_out_0_70 = _RAND_353[0:0];
+  ic_tag_valid_out_0_41 = _RAND_353[0:0];
   _RAND_354 = {1{`RANDOM}};
-  ic_tag_valid_out_0_71 = _RAND_354[0:0];
+  ic_tag_valid_out_0_42 = _RAND_354[0:0];
   _RAND_355 = {1{`RANDOM}};
-  ic_tag_valid_out_0_72 = _RAND_355[0:0];
+  ic_tag_valid_out_0_43 = _RAND_355[0:0];
   _RAND_356 = {1{`RANDOM}};
-  ic_tag_valid_out_0_73 = _RAND_356[0:0];
+  ic_tag_valid_out_0_44 = _RAND_356[0:0];
   _RAND_357 = {1{`RANDOM}};
-  ic_tag_valid_out_0_74 = _RAND_357[0:0];
+  ic_tag_valid_out_0_45 = _RAND_357[0:0];
   _RAND_358 = {1{`RANDOM}};
-  ic_tag_valid_out_0_75 = _RAND_358[0:0];
+  ic_tag_valid_out_0_46 = _RAND_358[0:0];
   _RAND_359 = {1{`RANDOM}};
-  ic_tag_valid_out_0_76 = _RAND_359[0:0];
+  ic_tag_valid_out_0_47 = _RAND_359[0:0];
   _RAND_360 = {1{`RANDOM}};
-  ic_tag_valid_out_0_77 = _RAND_360[0:0];
+  ic_tag_valid_out_0_48 = _RAND_360[0:0];
   _RAND_361 = {1{`RANDOM}};
-  ic_tag_valid_out_0_78 = _RAND_361[0:0];
+  ic_tag_valid_out_0_49 = _RAND_361[0:0];
   _RAND_362 = {1{`RANDOM}};
-  ic_tag_valid_out_0_79 = _RAND_362[0:0];
+  ic_tag_valid_out_0_50 = _RAND_362[0:0];
   _RAND_363 = {1{`RANDOM}};
-  ic_tag_valid_out_0_80 = _RAND_363[0:0];
+  ic_tag_valid_out_0_51 = _RAND_363[0:0];
   _RAND_364 = {1{`RANDOM}};
-  ic_tag_valid_out_0_81 = _RAND_364[0:0];
+  ic_tag_valid_out_0_52 = _RAND_364[0:0];
   _RAND_365 = {1{`RANDOM}};
-  ic_tag_valid_out_0_82 = _RAND_365[0:0];
+  ic_tag_valid_out_0_53 = _RAND_365[0:0];
   _RAND_366 = {1{`RANDOM}};
-  ic_tag_valid_out_0_83 = _RAND_366[0:0];
+  ic_tag_valid_out_0_54 = _RAND_366[0:0];
   _RAND_367 = {1{`RANDOM}};
-  ic_tag_valid_out_0_84 = _RAND_367[0:0];
+  ic_tag_valid_out_0_55 = _RAND_367[0:0];
   _RAND_368 = {1{`RANDOM}};
-  ic_tag_valid_out_0_85 = _RAND_368[0:0];
+  ic_tag_valid_out_0_56 = _RAND_368[0:0];
   _RAND_369 = {1{`RANDOM}};
-  ic_tag_valid_out_0_86 = _RAND_369[0:0];
+  ic_tag_valid_out_0_57 = _RAND_369[0:0];
   _RAND_370 = {1{`RANDOM}};
-  ic_tag_valid_out_0_87 = _RAND_370[0:0];
+  ic_tag_valid_out_0_58 = _RAND_370[0:0];
   _RAND_371 = {1{`RANDOM}};
-  ic_tag_valid_out_0_88 = _RAND_371[0:0];
+  ic_tag_valid_out_0_59 = _RAND_371[0:0];
   _RAND_372 = {1{`RANDOM}};
-  ic_tag_valid_out_0_89 = _RAND_372[0:0];
+  ic_tag_valid_out_0_60 = _RAND_372[0:0];
   _RAND_373 = {1{`RANDOM}};
-  ic_tag_valid_out_0_90 = _RAND_373[0:0];
+  ic_tag_valid_out_0_61 = _RAND_373[0:0];
   _RAND_374 = {1{`RANDOM}};
-  ic_tag_valid_out_0_91 = _RAND_374[0:0];
+  ic_tag_valid_out_0_62 = _RAND_374[0:0];
   _RAND_375 = {1{`RANDOM}};
-  ic_tag_valid_out_0_92 = _RAND_375[0:0];
+  ic_tag_valid_out_0_63 = _RAND_375[0:0];
   _RAND_376 = {1{`RANDOM}};
-  ic_tag_valid_out_0_93 = _RAND_376[0:0];
+  ic_tag_valid_out_0_64 = _RAND_376[0:0];
   _RAND_377 = {1{`RANDOM}};
-  ic_tag_valid_out_0_94 = _RAND_377[0:0];
+  ic_tag_valid_out_0_65 = _RAND_377[0:0];
   _RAND_378 = {1{`RANDOM}};
-  ic_tag_valid_out_0_95 = _RAND_378[0:0];
+  ic_tag_valid_out_0_66 = _RAND_378[0:0];
   _RAND_379 = {1{`RANDOM}};
-  ic_tag_valid_out_0_96 = _RAND_379[0:0];
+  ic_tag_valid_out_0_67 = _RAND_379[0:0];
   _RAND_380 = {1{`RANDOM}};
-  ic_tag_valid_out_0_97 = _RAND_380[0:0];
+  ic_tag_valid_out_0_68 = _RAND_380[0:0];
   _RAND_381 = {1{`RANDOM}};
-  ic_tag_valid_out_0_98 = _RAND_381[0:0];
+  ic_tag_valid_out_0_69 = _RAND_381[0:0];
   _RAND_382 = {1{`RANDOM}};
-  ic_tag_valid_out_0_99 = _RAND_382[0:0];
+  ic_tag_valid_out_0_70 = _RAND_382[0:0];
   _RAND_383 = {1{`RANDOM}};
-  ic_tag_valid_out_0_100 = _RAND_383[0:0];
+  ic_tag_valid_out_0_71 = _RAND_383[0:0];
   _RAND_384 = {1{`RANDOM}};
-  ic_tag_valid_out_0_101 = _RAND_384[0:0];
+  ic_tag_valid_out_0_72 = _RAND_384[0:0];
   _RAND_385 = {1{`RANDOM}};
-  ic_tag_valid_out_0_102 = _RAND_385[0:0];
+  ic_tag_valid_out_0_73 = _RAND_385[0:0];
   _RAND_386 = {1{`RANDOM}};
-  ic_tag_valid_out_0_103 = _RAND_386[0:0];
+  ic_tag_valid_out_0_74 = _RAND_386[0:0];
   _RAND_387 = {1{`RANDOM}};
-  ic_tag_valid_out_0_104 = _RAND_387[0:0];
+  ic_tag_valid_out_0_75 = _RAND_387[0:0];
   _RAND_388 = {1{`RANDOM}};
-  ic_tag_valid_out_0_105 = _RAND_388[0:0];
+  ic_tag_valid_out_0_76 = _RAND_388[0:0];
   _RAND_389 = {1{`RANDOM}};
-  ic_tag_valid_out_0_106 = _RAND_389[0:0];
+  ic_tag_valid_out_0_77 = _RAND_389[0:0];
   _RAND_390 = {1{`RANDOM}};
-  ic_tag_valid_out_0_107 = _RAND_390[0:0];
+  ic_tag_valid_out_0_78 = _RAND_390[0:0];
   _RAND_391 = {1{`RANDOM}};
-  ic_tag_valid_out_0_108 = _RAND_391[0:0];
+  ic_tag_valid_out_0_79 = _RAND_391[0:0];
   _RAND_392 = {1{`RANDOM}};
-  ic_tag_valid_out_0_109 = _RAND_392[0:0];
+  ic_tag_valid_out_0_80 = _RAND_392[0:0];
   _RAND_393 = {1{`RANDOM}};
-  ic_tag_valid_out_0_110 = _RAND_393[0:0];
+  ic_tag_valid_out_0_81 = _RAND_393[0:0];
   _RAND_394 = {1{`RANDOM}};
-  ic_tag_valid_out_0_111 = _RAND_394[0:0];
+  ic_tag_valid_out_0_82 = _RAND_394[0:0];
   _RAND_395 = {1{`RANDOM}};
-  ic_tag_valid_out_0_112 = _RAND_395[0:0];
+  ic_tag_valid_out_0_83 = _RAND_395[0:0];
   _RAND_396 = {1{`RANDOM}};
-  ic_tag_valid_out_0_113 = _RAND_396[0:0];
+  ic_tag_valid_out_0_84 = _RAND_396[0:0];
   _RAND_397 = {1{`RANDOM}};
-  ic_tag_valid_out_0_114 = _RAND_397[0:0];
+  ic_tag_valid_out_0_85 = _RAND_397[0:0];
   _RAND_398 = {1{`RANDOM}};
-  ic_tag_valid_out_0_115 = _RAND_398[0:0];
+  ic_tag_valid_out_0_86 = _RAND_398[0:0];
   _RAND_399 = {1{`RANDOM}};
-  ic_tag_valid_out_0_116 = _RAND_399[0:0];
+  ic_tag_valid_out_0_87 = _RAND_399[0:0];
   _RAND_400 = {1{`RANDOM}};
-  ic_tag_valid_out_0_117 = _RAND_400[0:0];
+  ic_tag_valid_out_0_88 = _RAND_400[0:0];
   _RAND_401 = {1{`RANDOM}};
-  ic_tag_valid_out_0_118 = _RAND_401[0:0];
+  ic_tag_valid_out_0_89 = _RAND_401[0:0];
   _RAND_402 = {1{`RANDOM}};
-  ic_tag_valid_out_0_119 = _RAND_402[0:0];
+  ic_tag_valid_out_0_90 = _RAND_402[0:0];
   _RAND_403 = {1{`RANDOM}};
-  ic_tag_valid_out_0_120 = _RAND_403[0:0];
+  ic_tag_valid_out_0_91 = _RAND_403[0:0];
   _RAND_404 = {1{`RANDOM}};
-  ic_tag_valid_out_0_121 = _RAND_404[0:0];
+  ic_tag_valid_out_0_92 = _RAND_404[0:0];
   _RAND_405 = {1{`RANDOM}};
-  ic_tag_valid_out_0_122 = _RAND_405[0:0];
+  ic_tag_valid_out_0_93 = _RAND_405[0:0];
   _RAND_406 = {1{`RANDOM}};
-  ic_tag_valid_out_0_123 = _RAND_406[0:0];
+  ic_tag_valid_out_0_94 = _RAND_406[0:0];
   _RAND_407 = {1{`RANDOM}};
-  ic_tag_valid_out_0_124 = _RAND_407[0:0];
+  ic_tag_valid_out_0_95 = _RAND_407[0:0];
   _RAND_408 = {1{`RANDOM}};
-  ic_tag_valid_out_0_125 = _RAND_408[0:0];
+  ic_tag_valid_out_0_96 = _RAND_408[0:0];
   _RAND_409 = {1{`RANDOM}};
-  ic_tag_valid_out_0_126 = _RAND_409[0:0];
+  ic_tag_valid_out_0_97 = _RAND_409[0:0];
   _RAND_410 = {1{`RANDOM}};
-  ic_tag_valid_out_0_127 = _RAND_410[0:0];
+  ic_tag_valid_out_0_98 = _RAND_410[0:0];
   _RAND_411 = {1{`RANDOM}};
-  ic_debug_way_ff = _RAND_411[1:0];
+  ic_tag_valid_out_0_99 = _RAND_411[0:0];
   _RAND_412 = {1{`RANDOM}};
-  ic_debug_rd_en_ff = _RAND_412[0:0];
-  _RAND_413 = {3{`RANDOM}};
-  _T_1212 = _RAND_413[70:0];
+  ic_tag_valid_out_0_100 = _RAND_412[0:0];
+  _RAND_413 = {1{`RANDOM}};
+  ic_tag_valid_out_0_101 = _RAND_413[0:0];
   _RAND_414 = {1{`RANDOM}};
-  ifc_region_acc_fault_memory_f = _RAND_414[0:0];
+  ic_tag_valid_out_0_102 = _RAND_414[0:0];
   _RAND_415 = {1{`RANDOM}};
-  perr_ic_index_ff = _RAND_415[6:0];
+  ic_tag_valid_out_0_103 = _RAND_415[0:0];
   _RAND_416 = {1{`RANDOM}};
-  dma_sb_err_state_ff = _RAND_416[0:0];
+  ic_tag_valid_out_0_104 = _RAND_416[0:0];
   _RAND_417 = {1{`RANDOM}};
-  bus_cmd_req_hold = _RAND_417[0:0];
+  ic_tag_valid_out_0_105 = _RAND_417[0:0];
   _RAND_418 = {1{`RANDOM}};
-  ifu_bus_cmd_valid = _RAND_418[0:0];
+  ic_tag_valid_out_0_106 = _RAND_418[0:0];
   _RAND_419 = {1{`RANDOM}};
-  ifu_bus_arvalid_ff = _RAND_419[0:0];
+  ic_tag_valid_out_0_107 = _RAND_419[0:0];
   _RAND_420 = {1{`RANDOM}};
-  ifc_dma_access_ok_prev = _RAND_420[0:0];
-  _RAND_421 = {2{`RANDOM}};
-  iccm_ecc_corr_data_ff = _RAND_421[38:0];
+  ic_tag_valid_out_0_108 = _RAND_420[0:0];
+  _RAND_421 = {1{`RANDOM}};
+  ic_tag_valid_out_0_109 = _RAND_421[0:0];
   _RAND_422 = {1{`RANDOM}};
-  dma_mem_addr_ff = _RAND_422[1:0];
+  ic_tag_valid_out_0_110 = _RAND_422[0:0];
   _RAND_423 = {1{`RANDOM}};
-  dma_mem_tag_ff = _RAND_423[2:0];
+  ic_tag_valid_out_0_111 = _RAND_423[0:0];
   _RAND_424 = {1{`RANDOM}};
-  iccm_dma_rtag_temp = _RAND_424[2:0];
+  ic_tag_valid_out_0_112 = _RAND_424[0:0];
   _RAND_425 = {1{`RANDOM}};
-  iccm_dma_rvalid_temp = _RAND_425[0:0];
+  ic_tag_valid_out_0_113 = _RAND_425[0:0];
   _RAND_426 = {1{`RANDOM}};
-  iccm_dma_ecc_error = _RAND_426[0:0];
-  _RAND_427 = {2{`RANDOM}};
-  iccm_dma_rdata_temp = _RAND_427[63:0];
+  ic_tag_valid_out_0_114 = _RAND_426[0:0];
+  _RAND_427 = {1{`RANDOM}};
+  ic_tag_valid_out_0_115 = _RAND_427[0:0];
   _RAND_428 = {1{`RANDOM}};
-  iccm_ecc_corr_index_ff = _RAND_428[13:0];
+  ic_tag_valid_out_0_116 = _RAND_428[0:0];
   _RAND_429 = {1{`RANDOM}};
-  iccm_rd_ecc_single_err_ff = _RAND_429[0:0];
+  ic_tag_valid_out_0_117 = _RAND_429[0:0];
   _RAND_430 = {1{`RANDOM}};
-  iccm_rw_addr_f = _RAND_430[13:0];
+  ic_tag_valid_out_0_118 = _RAND_430[0:0];
   _RAND_431 = {1{`RANDOM}};
-  ifu_status_wr_addr_ff = _RAND_431[6:0];
+  ic_tag_valid_out_0_119 = _RAND_431[0:0];
   _RAND_432 = {1{`RANDOM}};
-  way_status_wr_en_ff = _RAND_432[0:0];
+  ic_tag_valid_out_0_120 = _RAND_432[0:0];
   _RAND_433 = {1{`RANDOM}};
-  way_status_new_ff = _RAND_433[0:0];
+  ic_tag_valid_out_0_121 = _RAND_433[0:0];
   _RAND_434 = {1{`RANDOM}};
-  ifu_tag_wren_ff = _RAND_434[1:0];
+  ic_tag_valid_out_0_122 = _RAND_434[0:0];
   _RAND_435 = {1{`RANDOM}};
-  ic_valid_ff = _RAND_435[0:0];
+  ic_tag_valid_out_0_123 = _RAND_435[0:0];
   _RAND_436 = {1{`RANDOM}};
-  _T_9799 = _RAND_436[0:0];
+  ic_tag_valid_out_0_124 = _RAND_436[0:0];
   _RAND_437 = {1{`RANDOM}};
-  _T_9800 = _RAND_437[0:0];
+  ic_tag_valid_out_0_125 = _RAND_437[0:0];
   _RAND_438 = {1{`RANDOM}};
-  _T_9801 = _RAND_438[0:0];
+  ic_tag_valid_out_0_126 = _RAND_438[0:0];
   _RAND_439 = {1{`RANDOM}};
-  _T_9805 = _RAND_439[0:0];
+  ic_tag_valid_out_0_127 = _RAND_439[0:0];
   _RAND_440 = {1{`RANDOM}};
-  _T_9826 = _RAND_440[0:0];
+  ic_debug_way_ff = _RAND_440[1:0];
+  _RAND_441 = {1{`RANDOM}};
+  ic_debug_rd_en_ff = _RAND_441[0:0];
+  _RAND_442 = {3{`RANDOM}};
+  _T_1212 = _RAND_442[70:0];
+  _RAND_443 = {1{`RANDOM}};
+  ifc_region_acc_fault_memory_f = _RAND_443[0:0];
+  _RAND_444 = {1{`RANDOM}};
+  perr_ic_index_ff = _RAND_444[6:0];
+  _RAND_445 = {1{`RANDOM}};
+  dma_sb_err_state_ff = _RAND_445[0:0];
+  _RAND_446 = {1{`RANDOM}};
+  bus_cmd_req_hold = _RAND_446[0:0];
+  _RAND_447 = {1{`RANDOM}};
+  ifu_bus_cmd_valid = _RAND_447[0:0];
+  _RAND_448 = {1{`RANDOM}};
+  bus_cmd_beat_count = _RAND_448[2:0];
+  _RAND_449 = {1{`RANDOM}};
+  ifu_bus_arready_unq_ff = _RAND_449[0:0];
+  _RAND_450 = {1{`RANDOM}};
+  ifu_bus_arvalid_ff = _RAND_450[0:0];
+  _RAND_451 = {1{`RANDOM}};
+  ifc_dma_access_ok_prev = _RAND_451[0:0];
+  _RAND_452 = {2{`RANDOM}};
+  iccm_ecc_corr_data_ff = _RAND_452[38:0];
+  _RAND_453 = {1{`RANDOM}};
+  dma_mem_addr_ff = _RAND_453[1:0];
+  _RAND_454 = {1{`RANDOM}};
+  dma_mem_tag_ff = _RAND_454[2:0];
+  _RAND_455 = {1{`RANDOM}};
+  iccm_dma_rtag_temp = _RAND_455[2:0];
+  _RAND_456 = {1{`RANDOM}};
+  iccm_dma_rvalid_temp = _RAND_456[0:0];
+  _RAND_457 = {1{`RANDOM}};
+  iccm_dma_ecc_error = _RAND_457[0:0];
+  _RAND_458 = {2{`RANDOM}};
+  iccm_dma_rdata_temp = _RAND_458[63:0];
+  _RAND_459 = {1{`RANDOM}};
+  iccm_ecc_corr_index_ff = _RAND_459[13:0];
+  _RAND_460 = {1{`RANDOM}};
+  iccm_rd_ecc_single_err_ff = _RAND_460[0:0];
+  _RAND_461 = {1{`RANDOM}};
+  iccm_rw_addr_f = _RAND_461[13:0];
+  _RAND_462 = {1{`RANDOM}};
+  ifu_status_wr_addr_ff = _RAND_462[6:0];
+  _RAND_463 = {1{`RANDOM}};
+  way_status_wr_en_ff = _RAND_463[0:0];
+  _RAND_464 = {1{`RANDOM}};
+  way_status_new_ff = _RAND_464[0:0];
+  _RAND_465 = {1{`RANDOM}};
+  ifu_tag_wren_ff = _RAND_465[1:0];
+  _RAND_466 = {1{`RANDOM}};
+  ic_valid_ff = _RAND_466[0:0];
+  _RAND_467 = {1{`RANDOM}};
+  _T_9799 = _RAND_467[0:0];
+  _RAND_468 = {1{`RANDOM}};
+  _T_9800 = _RAND_468[0:0];
+  _RAND_469 = {1{`RANDOM}};
+  _T_9801 = _RAND_469[0:0];
+  _RAND_470 = {1{`RANDOM}};
+  _T_9805 = _RAND_470[0:0];
+  _RAND_471 = {1{`RANDOM}};
+  _T_9806 = _RAND_471[0:0];
+  _RAND_472 = {1{`RANDOM}};
+  _T_9826 = _RAND_472[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     flush_final_f = 1'h0;
@@ -6196,6 +6971,9 @@ initial begin
   if (reset) begin
     miss_state = 3'h0;
   end
+  if (reset) begin
+    scnd_miss_req_q = 1'h0;
+  end
   if (reset) begin
     ifu_fetch_addr_int_f = 31'h0;
   end
@@ -6220,18 +6998,33 @@ initial begin
   if (reset) begin
     ifc_region_acc_fault_final_f = 1'h0;
   end
+  if (reset) begin
+    ifu_bus_rvalid_unq_ff = 1'h0;
+  end
+  if (reset) begin
+    bus_ifu_bus_clk_en_ff = 1'h0;
+  end
   if (reset) begin
     uncacheable_miss_ff = 1'h0;
   end
+  if (reset) begin
+    bus_data_beat_count = 3'h0;
+  end
   if (reset) begin
     ic_miss_buff_data_valid = 8'h0;
   end
   if (reset) begin
     imb_ff = 31'h0;
   end
+  if (reset) begin
+    last_data_recieved_ff = 1'h0;
+  end
   if (reset) begin
     sel_mb_addr_ff = 1'h0;
   end
+  if (reset) begin
+    way_status_mb_scnd_ff = 1'h0;
+  end
   if (reset) begin
     ifu_ic_rw_int_addr_ff = 7'h0;
   end
@@ -6619,6 +7412,24 @@ initial begin
   if (reset) begin
     way_status_out_127 = 1'h0;
   end
+  if (reset) begin
+    tagv_mb_scnd_ff = 2'h0;
+  end
+  if (reset) begin
+    uncacheable_miss_scnd_ff = 1'h0;
+  end
+  if (reset) begin
+    imb_scnd_ff = 31'h0;
+  end
+  if (reset) begin
+    ifu_bus_rid_ff = 3'h0;
+  end
+  if (reset) begin
+    ifu_bus_rresp_ff = 2'h0;
+  end
+  if (reset) begin
+    ifu_wr_data_comb_err_ff = 1'h0;
+  end
   if (reset) begin
     way_status_mb_ff = 1'h0;
   end
@@ -6643,6 +7454,57 @@ initial begin
   if (reset) begin
     ic_act_miss_f_delayed = 1'h0;
   end
+  if (reset) begin
+    ifu_bus_rdata_ff = 64'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_0 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_1 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_2 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_3 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_4 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_5 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_6 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_7 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_8 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_9 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_10 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_11 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_12 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_13 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_14 = 32'h0;
+  end
+  if (reset) begin
+    ic_miss_buff_data_15 = 32'h0;
+  end
   if (reset) begin
     ic_crit_wd_rdy_new_ff = 1'h0;
   end
@@ -7444,6 +8306,12 @@ initial begin
   if (reset) begin
     ifu_bus_cmd_valid = 1'h0;
   end
+  if (reset) begin
+    bus_cmd_beat_count = 3'h0;
+  end
+  if (reset) begin
+    ifu_bus_arready_unq_ff = 1'h0;
+  end
   if (reset) begin
     ifu_bus_arvalid_ff = 1'h0;
   end
@@ -7507,6 +8375,9 @@ initial begin
   if (reset) begin
     _T_9805 = 1'h0;
   end
+  if (reset) begin
+    _T_9806 = 1'h0;
+  end
   if (reset) begin
     _T_9826 = 1'h0;
   end
@@ -7541,13 +8412,21 @@ end // initial
           miss_state <= 3'h2;
         end
       end else if (_T_31) begin
-        if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
+        if (_T_36) begin
           miss_state <= 3'h0;
         end else if (_T_40) begin
           miss_state <= 3'h3;
+        end else if (_T_47) begin
+          miss_state <= 3'h4;
+        end else if (_T_51) begin
+          miss_state <= 3'h0;
         end else if (_T_61) begin
           miss_state <= 3'h6;
-        end else if (_T_81) begin
+        end else if (_T_71) begin
+          miss_state <= 3'h6;
+        end else if (_T_79) begin
+          miss_state <= 3'h0;
+        end else if (_T_84) begin
           miss_state <= 3'h2;
         end else begin
           miss_state <= 3'h0;
@@ -7578,7 +8457,11 @@ end // initial
         if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
           miss_state <= 3'h0;
         end else if (io_exu_flush_final) begin
-          miss_state <= 3'h2;
+          if (_T_32) begin
+            miss_state <= 3'h0;
+          end else begin
+            miss_state <= 3'h2;
+          end
         end else begin
           miss_state <= 3'h1;
         end
@@ -7586,7 +8469,11 @@ end // initial
         if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
           miss_state <= 3'h0;
         end else if (io_exu_flush_final) begin
-          miss_state <= 3'h2;
+          if (_T_32) begin
+            miss_state <= 3'h0;
+          end else begin
+            miss_state <= 3'h2;
+          end
         end else begin
           miss_state <= 3'h0;
         end
@@ -7595,6 +8482,13 @@ end // initial
       end
     end
   end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      scnd_miss_req_q <= 1'h0;
+    end else begin
+      scnd_miss_req_q <= _T_22 & _T_319;
+    end
+  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       ifu_fetch_addr_int_f <= 31'h0;
@@ -7705,13 +8599,36 @@ end // initial
       ifc_region_acc_fault_final_f <= io_ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;
     end
   end
+  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ifu_bus_rvalid_unq_ff <= 1'h0;
+    end else begin
+      ifu_bus_rvalid_unq_ff <= io_ifu_axi_r_valid;
+    end
+  end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      bus_ifu_bus_clk_en_ff <= 1'h0;
+    end else begin
+      bus_ifu_bus_clk_en_ff <= io_ifu_bus_clk_en;
+    end
+  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       uncacheable_miss_ff <= 1'h0;
+    end else if (scnd_miss_req) begin
+      uncacheable_miss_ff <= uncacheable_miss_scnd_ff;
     end else if (!(sel_hold_imb)) begin
       uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
     end
   end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      bus_data_beat_count <= 3'h0;
+    end else begin
+      bus_data_beat_count <= _T_2631 | _T_2632;
+    end
+  end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       ic_miss_buff_data_valid <= 8'h0;
@@ -7722,15 +8639,31 @@ end // initial
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       imb_ff <= 31'h0;
+    end else if (scnd_miss_req) begin
+      imb_ff <= imb_scnd_ff;
     end else if (!(sel_hold_imb)) begin
       imb_ff <= io_ifc_fetch_addr_bf;
     end
   end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      last_data_recieved_ff <= 1'h0;
+    end else begin
+      last_data_recieved_ff <= _T_2639 | _T_2641;
+    end
+  end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       sel_mb_addr_ff <= 1'h0;
     end else begin
-      sel_mb_addr_ff <= _T_2687 & _T_17;
+      sel_mb_addr_ff <= _T_334 | reset_tag_valid_for_miss;
+    end
+  end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      way_status_mb_scnd_ff <= 1'h0;
+    end else if (!(_T_19)) begin
+      way_status_mb_scnd_ff <= way_status;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -8638,9 +9571,55 @@ end // initial
       way_status_out_127 <= way_status_new_ff;
     end
   end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      tagv_mb_scnd_ff <= 2'h0;
+    end else if (!(_T_19)) begin
+      tagv_mb_scnd_ff <= _T_198;
+    end
+  end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      uncacheable_miss_scnd_ff <= 1'h0;
+    end else if (!(sel_hold_imb_scnd)) begin
+      uncacheable_miss_scnd_ff <= io_ifc_fetch_uncacheable_bf;
+    end
+  end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      imb_scnd_ff <= 31'h0;
+    end else if (!(sel_hold_imb_scnd)) begin
+      imb_scnd_ff <= io_ifc_fetch_addr_bf;
+    end
+  end
+  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ifu_bus_rid_ff <= 3'h0;
+    end else begin
+      ifu_bus_rid_ff <= io_ifu_axi_r_bits_id;
+    end
+  end
+  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ifu_bus_rresp_ff <= 2'h0;
+    end else begin
+      ifu_bus_rresp_ff <= io_ifu_axi_r_bits_resp;
+    end
+  end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      ifu_wr_data_comb_err_ff <= 1'h0;
+    end else begin
+      ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err_data & _T_2627;
+    end
+  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       way_status_mb_ff <= 1'h0;
+    end else if (_T_278) begin
+      way_status_mb_ff <= way_status_mb_scnd_ff;
+    end else if (_T_280) begin
+      way_status_mb_ff <= replace_way_mb_any_0;
     end else if (!(miss_pending)) begin
       way_status_mb_ff <= way_status;
     end
@@ -8648,6 +9627,8 @@ end // initial
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       tagv_mb_ff <= 2'h0;
+    end else if (scnd_miss_req) begin
+      tagv_mb_ff <= _T_290;
     end else if (!(miss_pending)) begin
       tagv_mb_ff <= _T_295;
     end
@@ -8656,7 +9637,7 @@ end // initial
     if (reset) begin
       reset_ic_ff <= 1'h0;
     end else begin
-      reset_ic_ff <= miss_pending & _T_299;
+      reset_ic_ff <= _T_298 & _T_299;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
@@ -8671,6 +9652,8 @@ end // initial
       miss_addr <= 26'h0;
     end else if (_T_231) begin
       miss_addr <= imb_ff[30:5];
+    end else if (scnd_miss_req_q) begin
+      miss_addr <= imb_scnd_ff[30:5];
     end
   end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
@@ -8685,13 +9668,136 @@ end // initial
       bus_rd_addr_count <= 3'h0;
     end else if (_T_231) begin
       bus_rd_addr_count <= imb_ff[4:2];
+    end else if (scnd_miss_req_q) begin
+      bus_rd_addr_count <= imb_scnd_ff[4:2];
+    end else if (bus_cmd_sent) begin
+      bus_rd_addr_count <= _T_2647;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       ic_act_miss_f_delayed <= 1'h0;
     end else begin
-      ic_act_miss_f_delayed <= _T_232 & _T_209;
+      ic_act_miss_f_delayed <= _T_233 & _T_209;
+    end
+  end
+  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ifu_bus_rdata_ff <= 64'h0;
+    end else begin
+      ifu_bus_rdata_ff <= io_ifu_axi_r_bits_data;
+    end
+  end
+  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_0 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_0 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_1 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_1 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_2 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_2 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_3 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_3 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_4 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_4 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_5 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_5 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_6 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_6 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_7 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_7 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_8 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_8 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_9 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_9 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_10 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_10 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_11 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_11 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_12 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_12 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_13 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_13 <= io_ifu_axi_r_bits_data[63:32];
+    end
+  end
+  always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_14 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_14 <= io_ifu_axi_r_bits_data[31:0];
+    end
+  end
+  always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ic_miss_buff_data_15 <= 32'h0;
+    end else begin
+      ic_miss_buff_data_15 <= io_ifu_axi_r_bits_data[63:32];
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -10555,14 +11661,28 @@ end // initial
     if (reset) begin
       bus_cmd_req_hold <= 1'h0;
     end else begin
-      bus_cmd_req_hold <= _T_2591 & _T_2623;
+      bus_cmd_req_hold <= _T_2604 & _T_2623;
     end
   end
   always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin
     if (reset) begin
       ifu_bus_cmd_valid <= 1'h0;
     end else begin
-      ifu_bus_cmd_valid <= _T_2592 & _T_2623;
+      ifu_bus_cmd_valid <= _T_2594 & _T_2600;
+    end
+  end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+    if (reset) begin
+      bus_cmd_beat_count <= 3'h0;
+    end else if (bus_cmd_beat_en) begin
+      bus_cmd_beat_count <= bus_new_cmd_beat_count;
+    end
+  end
+  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
+    if (reset) begin
+      ifu_bus_arready_unq_ff <= 1'h0;
+    end else begin
+      ifu_bus_arready_unq_ff <= io_ifu_axi_ar_ready;
     end
   end
   always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
@@ -10668,7 +11788,7 @@ end // initial
     if (reset) begin
       way_status_wr_en_ff <= 1'h0;
     end else begin
-      way_status_wr_en_ff <= ic_act_hit_f | _T_4000;
+      way_status_wr_en_ff <= way_status_wr_en | _T_4000;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -10676,6 +11796,8 @@ end // initial
       way_status_new_ff <= 1'h0;
     end else if (_T_4000) begin
       way_status_new_ff <= io_ic_debug_wr_data[4];
+    end else if (_T_9777) begin
+      way_status_new_ff <= replace_way_mb_any_0;
     end else begin
       way_status_new_ff <= way_status_hit_new;
     end
@@ -10700,7 +11822,7 @@ end // initial
     if (reset) begin
       _T_9799 <= 1'h0;
     end else begin
-      _T_9799 <= _T_232 & _T_209;
+      _T_9799 <= _T_233 & _T_209;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
@@ -10721,7 +11843,14 @@ end // initial
     if (reset) begin
       _T_9805 <= 1'h0;
     end else begin
-      _T_9805 <= ifu_bus_arvalid_ff & miss_pending;
+      _T_9805 <= _T_9803 & miss_pending;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      _T_9806 <= 1'h0;
+    end else begin
+      _T_9806 <= _T_2618 & _T_2623;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -43002,6 +44131,7 @@ module ifu_ifc_ctl(
   input         io_ifu_bp_hit_taken_f,
   input  [30:0] io_ifu_bp_btb_target_f,
   input         io_ic_dma_active,
+  input         io_ic_write_stall,
   input         io_dec_ifc_dec_tlu_flush_noredir_wb,
   input  [31:0] io_dec_ifc_dec_tlu_mrac_ff,
   output        io_dec_ifc_ifu_pmu_fetch_stall,
@@ -43100,6 +44230,8 @@ module ifu_ifc_ctl(
   wire  _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[ifu_ifc_ctl.scala 86:51]
   wire  _T_40 = ~dma_stall; // @[ifu_ifc_ctl.scala 87:5]
   wire  _T_41 = _T_39 & _T_40; // @[ifu_ifc_ctl.scala 86:114]
+  wire  _T_42 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 87:18]
+  wire  _T_43 = _T_41 & _T_42; // @[ifu_ifc_ctl.scala 87:16]
   wire  _T_44 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 87:39]
   wire  _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 93:39]
   wire  _T_53 = _T_51 & _T_40; // @[ifu_ifc_ctl.scala 93:61]
@@ -43155,7 +44287,7 @@ module ifu_ifc_ctl(
   assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[ifu_ifc_ctl.scala 73:24]
   assign io_ifc_fetch_req_f = _T_164; // @[ifu_ifc_ctl.scala 145:22]
   assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[ifu_ifc_ctl.scala 143:31]
-  assign io_ifc_fetch_req_bf = _T_41 & _T_44; // @[ifu_ifc_ctl.scala 86:23]
+  assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[ifu_ifc_ctl.scala 86:23]
   assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 84:27]
   assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 137:25]
   assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 142:30]
@@ -43332,6 +44464,7 @@ module ifu(
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
+  output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
   output        io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
   output        io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   output [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -43375,7 +44508,10 @@ module ifu(
   input  [77:0] io_iccm_rd_data_ecc,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
+  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
+  output [70:0] io_ic_wr_data_0,
+  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -43390,8 +44526,14 @@ module ifu(
   output [1:0]  io_ic_debug_way,
   output [63:0] io_ic_premux_data,
   output        io_ic_sel_premux_data,
+  input         io_ifu_ar_ready,
   output        io_ifu_ar_valid,
+  output [2:0]  io_ifu_ar_bits_id,
   output [31:0] io_ifu_ar_bits_addr,
+  input         io_ifu_r_valid,
+  input  [2:0]  io_ifu_r_bits_id,
+  input  [63:0] io_ifu_r_bits_data,
+  input  [1:0]  io_ifu_r_bits_resp,
   input         io_ifu_bus_clk_en,
   input         io_ifu_dma_dma_ifc_dma_iccm_stall_any,
   input         io_ifu_dma_dma_mem_ctl_dma_iccm_req,
@@ -43427,6 +44569,7 @@ module ifu(
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 34:23]
   wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 34:23]
@@ -43441,8 +44584,15 @@ module ifu(
   wire  mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23]
   wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 34:23]
   wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 34:23]
@@ -43461,7 +44611,10 @@ module ifu(
   wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 34:23]
   wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 34:23]
   wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ic_rd_en; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 34:23]
   wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 34:23]
   wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 34:23]
   wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 34:23]
@@ -43479,6 +44632,7 @@ module ifu(
   wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ic_dma_active; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_write_stall; // @[ifu.scala 34:23]
   wire  mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 34:23]
   wire  mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 34:23]
   wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 34:23]
@@ -43597,6 +44751,7 @@ module ifu(
   wire  ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:23]
   wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_ic_dma_active; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ic_write_stall; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 37:23]
   wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 37:23]
@@ -43629,6 +44784,7 @@ module ifu(
     .io_dec_mem_ctrl_ifu_pmu_ic_hit(mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_dec_mem_ctrl_ifu_pmu_bus_error(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_dec_mem_ctrl_ifu_pmu_bus_busy(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy),
+    .io_dec_mem_ctrl_ifu_pmu_bus_trxn(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_dec_mem_ctrl_ifu_ic_error_start(mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start),
     .io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_dec_mem_ctrl_ifu_ic_debug_rd_data(mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -43643,8 +44799,15 @@ module ifu(
     .io_ifc_dma_access_ok(mem_ctl_io_ifc_dma_access_ok),
     .io_ifu_bp_hit_taken_f(mem_ctl_io_ifu_bp_hit_taken_f),
     .io_ifu_bp_inst_mask_f(mem_ctl_io_ifu_bp_inst_mask_f),
+    .io_ifu_axi_ar_ready(mem_ctl_io_ifu_axi_ar_ready),
     .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid),
+    .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id),
     .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr),
+    .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready),
+    .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid),
+    .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id),
+    .io_ifu_axi_r_bits_data(mem_ctl_io_ifu_axi_r_bits_data),
+    .io_ifu_axi_r_bits_resp(mem_ctl_io_ifu_axi_r_bits_resp),
     .io_ifu_bus_clk_en(mem_ctl_io_ifu_bus_clk_en),
     .io_dma_mem_ctl_dma_iccm_req(mem_ctl_io_dma_mem_ctl_dma_iccm_req),
     .io_dma_mem_ctl_dma_mem_addr(mem_ctl_io_dma_mem_ctl_dma_mem_addr),
@@ -43663,7 +44826,10 @@ module ifu(
     .io_iccm_rd_data_ecc(mem_ctl_io_iccm_rd_data_ecc),
     .io_ic_rw_addr(mem_ctl_io_ic_rw_addr),
     .io_ic_tag_valid(mem_ctl_io_ic_tag_valid),
+    .io_ic_wr_en(mem_ctl_io_ic_wr_en),
     .io_ic_rd_en(mem_ctl_io_ic_rd_en),
+    .io_ic_wr_data_0(mem_ctl_io_ic_wr_data_0),
+    .io_ic_wr_data_1(mem_ctl_io_ic_wr_data_1),
     .io_ic_debug_wr_data(mem_ctl_io_ic_debug_wr_data),
     .io_ic_debug_addr(mem_ctl_io_ic_debug_addr),
     .io_ic_rd_data(mem_ctl_io_ic_rd_data),
@@ -43681,6 +44847,7 @@ module ifu(
     .io_ifu_fetch_val(mem_ctl_io_ifu_fetch_val),
     .io_ifu_ic_mb_empty(mem_ctl_io_ifu_ic_mb_empty),
     .io_ic_dma_active(mem_ctl_io_ic_dma_active),
+    .io_ic_write_stall(mem_ctl_io_ic_write_stall),
     .io_iccm_dma_ecc_error(mem_ctl_io_iccm_dma_ecc_error),
     .io_iccm_dma_rvalid(mem_ctl_io_iccm_dma_rvalid),
     .io_iccm_dma_rdata(mem_ctl_io_iccm_dma_rdata),
@@ -43805,6 +44972,7 @@ module ifu(
     .io_ifu_bp_hit_taken_f(ifc_ctl_io_ifu_bp_hit_taken_f),
     .io_ifu_bp_btb_target_f(ifc_ctl_io_ifu_bp_btb_target_f),
     .io_ic_dma_active(ifc_ctl_io_ic_dma_active),
+    .io_ic_write_stall(ifc_ctl_io_ic_write_stall),
     .io_dec_ifc_dec_tlu_flush_noredir_wb(ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb),
     .io_dec_ifc_dec_tlu_mrac_ff(ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff),
     .io_dec_ifc_ifu_pmu_fetch_stall(ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall),
@@ -43844,6 +45012,7 @@ module ifu(
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 93:27]
@@ -43859,7 +45028,10 @@ module ifu(
   assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 107:19]
   assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 106:17]
   assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 106:17]
+  assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 106:17]
   assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 106:17]
+  assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 106:17]
+  assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 106:17]
   assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 106:17]
   assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 106:17]
   assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 106:17]
@@ -43869,6 +45041,7 @@ module ifu(
   assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 106:17]
   assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 106:17]
   assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22]
+  assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22]
   assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22]
   assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25]
   assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22]
@@ -43899,6 +45072,11 @@ module ifu(
   assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 100:32]
   assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 101:33]
   assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 102:33]
+  assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 103:22]
   assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 104:29]
   assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 105:26]
   assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 105:26]
@@ -43986,6 +45164,7 @@ module ifu(
   assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 48:33]
   assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 49:34]
   assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 50:28]
+  assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 51:29]
   assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 46:22]
   assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 46:22]
   assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 52:22]
@@ -49296,6 +50475,7 @@ module csr_tlu(
   output        io_trigger_pkt_any_3_execute,
   output        io_trigger_pkt_any_3_m,
   output [31:0] io_trigger_pkt_any_3_tdata2,
+  input         io_ifu_pmu_bus_trxn,
   input         io_dma_iccm_stall_any,
   input         io_dma_dccm_stall_any,
   input         io_lsu_store_stall_any,
@@ -49348,6 +50528,7 @@ module csr_tlu(
   input         io_lsu_pmu_bus_error,
   input         io_ifu_pmu_bus_error,
   input         io_lsu_pmu_bus_misaligned,
+  input         io_lsu_pmu_bus_trxn,
   input  [70:0] io_ifu_ic_debug_rd_data,
   output [3:0]  io_dec_tlu_meipt,
   input  [3:0]  io_pic_pl,
@@ -49359,7 +50540,6 @@ module csr_tlu(
   input         io_lsu_imprecise_error_load_any,
   input         io_lsu_imprecise_error_store_any,
   output [31:0] io_dec_tlu_mrac_ff,
-  output        io_dec_tlu_wb_coalescing_disable,
   output        io_dec_tlu_bpred_disable,
   output        io_dec_tlu_sideeffect_posted_disable,
   output        io_dec_tlu_core_ecc_disable,
@@ -50327,6 +51507,8 @@ module csr_tlu(
   wire  _T_1132 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
   wire  _T_1134 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97]
   wire  _T_1135 = _T_1134 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129]
+  wire  _T_1136 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
+  wire  _T_1138 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
   wire  _T_1140 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
   wire  _T_1142 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
   wire  _T_1144 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
@@ -50387,6 +51569,8 @@ module csr_tlu(
   wire  _T_1221 = _T_1128 & io_take_ext_int; // @[Mux.scala 27:72]
   wire  _T_1222 = _T_1130 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
   wire  _T_1223 = _T_1132 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1224 = _T_1136 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
+  wire  _T_1225 = _T_1138 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
   wire  _T_1226 = _T_1140 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
   wire  _T_1227 = _T_1142 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
   wire  _T_1228 = _T_1144 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
@@ -50441,7 +51625,9 @@ module csr_tlu(
   wire  _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72]
   wire  _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72]
   wire  _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72]
-  wire  _T_1282 = _T_1279 | _T_1226; // @[Mux.scala 27:72]
+  wire  _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72]
+  wire  _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72]
+  wire  _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72]
   wire  _T_1283 = _T_1282 | _T_1227; // @[Mux.scala 27:72]
   wire  _T_1284 = _T_1283 | _T_1228; // @[Mux.scala 27:72]
   wire  _T_1285 = _T_1284 | _T_1229; // @[Mux.scala 27:72]
@@ -50498,6 +51684,8 @@ module csr_tlu(
   wire  _T_1412 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
   wire  _T_1414 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
   wire  _T_1416 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1420 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
+  wire  _T_1422 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
   wire  _T_1424 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
   wire  _T_1426 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
   wire  _T_1428 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
@@ -50551,6 +51739,8 @@ module csr_tlu(
   wire  _T_1505 = _T_1412 & io_take_ext_int; // @[Mux.scala 27:72]
   wire  _T_1506 = _T_1414 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
   wire  _T_1507 = _T_1416 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1508 = _T_1420 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
+  wire  _T_1509 = _T_1422 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
   wire  _T_1510 = _T_1424 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
   wire  _T_1511 = _T_1426 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
   wire  _T_1512 = _T_1428 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
@@ -50605,7 +51795,9 @@ module csr_tlu(
   wire  _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72]
   wire  _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72]
   wire  _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72]
-  wire  _T_1566 = _T_1563 | _T_1510; // @[Mux.scala 27:72]
+  wire  _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72]
+  wire  _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72]
+  wire  _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72]
   wire  _T_1567 = _T_1566 | _T_1511; // @[Mux.scala 27:72]
   wire  _T_1568 = _T_1567 | _T_1512; // @[Mux.scala 27:72]
   wire  _T_1569 = _T_1568 | _T_1513; // @[Mux.scala 27:72]
@@ -50662,6 +51854,8 @@ module csr_tlu(
   wire  _T_1696 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
   wire  _T_1698 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
   wire  _T_1700 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1704 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
+  wire  _T_1706 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
   wire  _T_1708 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
   wire  _T_1710 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
   wire  _T_1712 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
@@ -50715,6 +51909,8 @@ module csr_tlu(
   wire  _T_1789 = _T_1696 & io_take_ext_int; // @[Mux.scala 27:72]
   wire  _T_1790 = _T_1698 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
   wire  _T_1791 = _T_1700 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1792 = _T_1704 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
+  wire  _T_1793 = _T_1706 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
   wire  _T_1794 = _T_1708 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
   wire  _T_1795 = _T_1710 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
   wire  _T_1796 = _T_1712 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
@@ -50769,7 +51965,9 @@ module csr_tlu(
   wire  _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72]
   wire  _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72]
   wire  _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72]
-  wire  _T_1850 = _T_1847 | _T_1794; // @[Mux.scala 27:72]
+  wire  _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72]
+  wire  _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72]
+  wire  _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72]
   wire  _T_1851 = _T_1850 | _T_1795; // @[Mux.scala 27:72]
   wire  _T_1852 = _T_1851 | _T_1796; // @[Mux.scala 27:72]
   wire  _T_1853 = _T_1852 | _T_1797; // @[Mux.scala 27:72]
@@ -50826,6 +52024,8 @@ module csr_tlu(
   wire  _T_1980 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
   wire  _T_1982 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
   wire  _T_1984 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1988 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
+  wire  _T_1990 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
   wire  _T_1992 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
   wire  _T_1994 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
   wire  _T_1996 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
@@ -50879,6 +52079,8 @@ module csr_tlu(
   wire  _T_2073 = _T_1980 & io_take_ext_int; // @[Mux.scala 27:72]
   wire  _T_2074 = _T_1982 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
   wire  _T_2075 = _T_1984 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_2076 = _T_1988 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
+  wire  _T_2077 = _T_1990 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
   wire  _T_2078 = _T_1992 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
   wire  _T_2079 = _T_1994 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
   wire  _T_2080 = _T_1996 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
@@ -50933,7 +52135,9 @@ module csr_tlu(
   wire  _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72]
   wire  _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72]
   wire  _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72]
-  wire  _T_2134 = _T_2131 | _T_2078; // @[Mux.scala 27:72]
+  wire  _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72]
+  wire  _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72]
+  wire  _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72]
   wire  _T_2135 = _T_2134 | _T_2079; // @[Mux.scala 27:72]
   wire  _T_2136 = _T_2135 | _T_2080; // @[Mux.scala 27:72]
   wire  _T_2137 = _T_2136 | _T_2081; // @[Mux.scala 27:72]
@@ -51446,7 +52650,6 @@ module csr_tlu(
   assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22]
   assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20]
   assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1807:21]
-  assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1767:39]
   assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1766:39]
   assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1765:39]
   assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1764:39]
@@ -53194,16 +54397,17 @@ module dec_tlu_ctl(
   input         io_tlu_mem_ifu_pmu_ic_hit,
   input         io_tlu_mem_ifu_pmu_bus_error,
   input         io_tlu_mem_ifu_pmu_bus_busy,
+  input         io_tlu_mem_ifu_pmu_bus_trxn,
   input         io_tlu_mem_ifu_ic_error_start,
   input         io_tlu_mem_ifu_iccm_rd_ecc_single_err,
   input  [70:0] io_tlu_mem_ifu_ic_debug_rd_data,
   input         io_tlu_mem_ifu_ic_debug_rd_data_valid,
   input         io_tlu_mem_ifu_miss_state_idle,
+  input         io_tlu_busbuff_lsu_pmu_bus_trxn,
   input         io_tlu_busbuff_lsu_pmu_bus_misaligned,
   input         io_tlu_busbuff_lsu_pmu_bus_error,
   input         io_tlu_busbuff_lsu_pmu_bus_busy,
   output        io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
-  output        io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
   output        io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
   input         io_tlu_busbuff_lsu_imprecise_error_load_any,
   input         io_tlu_busbuff_lsu_imprecise_error_store_any,
@@ -53373,6 +54577,7 @@ module dec_tlu_ctl(
   wire  csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 818:15]
   wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 818:15]
+  wire  csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 818:15]
@@ -53425,6 +54630,7 @@ module dec_tlu_ctl(
   wire  csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 818:15]
+  wire  csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15]
   wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 818:15]
   wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 818:15]
   wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 818:15]
@@ -53436,7 +54642,6 @@ module dec_tlu_ctl(
   wire  csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 818:15]
   wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 818:15]
-  wire  csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 818:15]
@@ -54460,6 +55665,7 @@ module dec_tlu_ctl(
     .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute),
     .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m),
     .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2),
+    .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn),
     .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any),
     .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any),
     .io_lsu_store_stall_any(csr_io_lsu_store_stall_any),
@@ -54512,6 +55718,7 @@ module dec_tlu_ctl(
     .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error),
     .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error),
     .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned),
+    .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn),
     .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data),
     .io_dec_tlu_meipt(csr_io_dec_tlu_meipt),
     .io_pic_pl(csr_io_pic_pl),
@@ -54523,7 +55730,6 @@ module dec_tlu_ctl(
     .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any),
     .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any),
     .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff),
-    .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable),
     .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable),
     .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable),
     .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable),
@@ -54850,7 +56056,6 @@ module dec_tlu_ctl(
   assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 882:52]
   assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 905:48]
   assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 906:52]
-  assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 902:52]
   assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 904:52]
   assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 876:52]
   assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 878:52]
@@ -54893,6 +56098,7 @@ module dec_tlu_ctl(
   assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 825:44]
   assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 826:44]
   assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 827:44]
+  assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 828:44]
   assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 829:44]
   assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 830:44]
   assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 831:44]
@@ -54926,6 +56132,7 @@ module dec_tlu_ctl(
   assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 856:44]
   assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 857:44]
   assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 858:44]
+  assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 859:44]
   assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 860:44]
   assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 861:44]
   assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 862:44]
@@ -56762,6 +57969,7 @@ module dec(
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
+  input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
   input         io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
   input         io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   input  [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -56854,11 +58062,11 @@ module dec(
   output        io_dec_exu_ib_exu_dec_debug_wdata_rs1_d,
   output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d,
   output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d,
+  input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
   output        io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable,
-  output        io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable,
   output        io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
   input         io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any,
   input         io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any,
@@ -57296,16 +58504,17 @@ module dec(
   wire  tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 120:19]
+  wire  tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 120:19]
   wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 120:19]
+  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19]
-  wire  tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19]
@@ -57751,16 +58960,17 @@ module dec(
     .io_tlu_mem_ifu_pmu_ic_hit(tlu_io_tlu_mem_ifu_pmu_ic_hit),
     .io_tlu_mem_ifu_pmu_bus_error(tlu_io_tlu_mem_ifu_pmu_bus_error),
     .io_tlu_mem_ifu_pmu_bus_busy(tlu_io_tlu_mem_ifu_pmu_bus_busy),
+    .io_tlu_mem_ifu_pmu_bus_trxn(tlu_io_tlu_mem_ifu_pmu_bus_trxn),
     .io_tlu_mem_ifu_ic_error_start(tlu_io_tlu_mem_ifu_ic_error_start),
     .io_tlu_mem_ifu_iccm_rd_ecc_single_err(tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err),
     .io_tlu_mem_ifu_ic_debug_rd_data(tlu_io_tlu_mem_ifu_ic_debug_rd_data),
     .io_tlu_mem_ifu_ic_debug_rd_data_valid(tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid),
     .io_tlu_mem_ifu_miss_state_idle(tlu_io_tlu_mem_ifu_miss_state_idle),
+    .io_tlu_busbuff_lsu_pmu_bus_trxn(tlu_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy),
     .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
-    .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
     .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
     .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any),
     .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any),
@@ -57947,7 +59157,6 @@ module dec(
   assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22]
   assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22]
   assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26]
-  assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26]
   assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26]
   assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18]
   assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14]
@@ -58134,11 +59343,13 @@ module dec(
   assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 202:18]
+  assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 202:18]
+  assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 222:26]
@@ -58191,14 +59402,25 @@ module dbg(
   input  [6:0]  io_dmi_reg_addr,
   input         io_dmi_reg_wr_en,
   input  [31:0] io_dmi_reg_wdata,
+  input         io_sb_axi_aw_ready,
   output        io_sb_axi_aw_valid,
   output [31:0] io_sb_axi_aw_bits_addr,
   output [2:0]  io_sb_axi_aw_bits_size,
+  input         io_sb_axi_w_ready,
   output        io_sb_axi_w_valid,
+  output [63:0] io_sb_axi_w_bits_data,
   output [7:0]  io_sb_axi_w_bits_strb,
+  output        io_sb_axi_b_ready,
+  input         io_sb_axi_b_valid,
+  input  [1:0]  io_sb_axi_b_bits_resp,
+  input         io_sb_axi_ar_ready,
   output        io_sb_axi_ar_valid,
   output [31:0] io_sb_axi_ar_bits_addr,
   output [2:0]  io_sb_axi_ar_bits_size,
+  output        io_sb_axi_r_ready,
+  input         io_sb_axi_r_valid,
+  input  [63:0] io_sb_axi_r_bits_data,
+  input  [1:0]  io_sb_axi_r_bits_resp,
   output        io_dbg_dec_dbg_ib_dbg_cmd_valid,
   output        io_dbg_dec_dbg_ib_dbg_cmd_write,
   output [1:0]  io_dbg_dec_dbg_ib_dbg_cmd_type,
@@ -58236,6 +59458,8 @@ module dbg(
   reg [31:0] _RAND_16;
   reg [31:0] _RAND_17;
   reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
 `endif // RANDOMIZE_REG_INIT
   wire [2:0] dbg_state;
   wire  dbg_state_en;
@@ -58245,6 +59469,7 @@ module dbg(
   wire [31:0] sbaddress0_reg;
   wire  sbcs_sbbusy_wren;
   wire  sbcs_sberror_wren;
+  wire [63:0] sb_bus_rdata;
   wire  sbaddress0_reg_wren1;
   wire [31:0] dmstatus_reg;
   wire  dmstatus_havereset;
@@ -58253,6 +59478,12 @@ module dbg(
   wire  dmstatus_running;
   wire  dmstatus_halted;
   wire  abstractcs_busy_wren;
+  wire  sb_bus_cmd_read;
+  wire  sb_bus_cmd_write_addr;
+  wire  sb_bus_cmd_write_data;
+  wire  sb_bus_rsp_read;
+  wire  sb_bus_rsp_error;
+  wire  sb_bus_rsp_write;
   wire  sbcs_sbbusy_din;
   wire [31:0] data1_reg;
   wire [31:0] sbcs_reg;
@@ -58329,14 +59560,23 @@ module dbg(
   wire  _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 143:76]
   wire  sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 143:74]
   wire  sbdata1_reg_wren0 = _T_83 & _T_30; // @[dbg.scala 145:60]
+  wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 148:49]
+  wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 149:33]
+  wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 151:49]
+  wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 152:33]
   wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] sbdata0_reg; // @[lib.scala 374:16]
   wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] sbdata1_reg; // @[lib.scala 374:16]
   wire  sbaddress0_reg_wren0 = _T_83 & _T_27; // @[dbg.scala 162:63]
   wire [31:0] _T_110 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_111 = _T_110 & io_dmi_reg_wdata; // @[dbg.scala 164:59]
@@ -58570,37 +59810,76 @@ module dbg(
   wire  _T_517 = _T_516 | sbcs_illegal_size; // @[dbg.scala 358:57]
   wire  _T_520 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
   wire  _T_527 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_528 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 370:38]
   wire  _T_529 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_530 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 373:48]
+  wire  _T_533 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 374:45]
+  wire  _T_534 = _T_533 & io_dbg_bus_clk_en; // @[dbg.scala 374:70]
   wire  _T_535 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_536 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 378:44]
   wire  _T_537 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_538 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 382:44]
   wire  _T_539 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_540 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 386:38]
+  wire  _T_541 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 387:40]
   wire  _T_542 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_543 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 392:39]
   wire  _T_545 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
   wire  _GEN_50 = _T_545 & sbcs_reg[16]; // @[Conditional.scala 39:67]
-  wire  _GEN_52 = _T_542 ? 1'h0 : _T_545; // @[Conditional.scala 39:67]
+  wire  _GEN_52 = _T_542 ? _T_543 : _T_545; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_542 & _T_541; // @[Conditional.scala 39:67]
+  wire  _GEN_55 = _T_542 ? 1'h0 : _T_545; // @[Conditional.scala 39:67]
   wire  _GEN_57 = _T_542 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67]
-  wire  _GEN_59 = _T_539 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_539 ? _T_540 : _GEN_52; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_539 ? _T_541 : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_62 = _T_539 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
   wire  _GEN_64 = _T_539 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
-  wire  _GEN_66 = _T_537 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_537 ? _T_538 : _GEN_59; // @[Conditional.scala 39:67]
+  wire  _GEN_67 = _T_537 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
+  wire  _GEN_69 = _T_537 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
   wire  _GEN_71 = _T_537 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
-  wire  _GEN_73 = _T_535 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_535 ? _T_536 : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_74 = _T_535 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
+  wire  _GEN_76 = _T_535 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
   wire  _GEN_78 = _T_535 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
-  wire  _GEN_80 = _T_529 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
+  wire  _GEN_80 = _T_529 ? _T_534 : _GEN_73; // @[Conditional.scala 39:67]
+  wire  _GEN_81 = _T_529 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
+  wire  _GEN_83 = _T_529 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67]
   wire  _GEN_85 = _T_529 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67]
-  wire  _GEN_87 = _T_527 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
+  wire  _GEN_87 = _T_527 ? _T_528 : _GEN_80; // @[Conditional.scala 39:67]
+  wire  _GEN_88 = _T_527 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
+  wire  _GEN_90 = _T_527 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67]
   wire  _GEN_92 = _T_527 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67]
   wire  _GEN_94 = _T_520 ? _T_517 : _GEN_87; // @[Conditional.scala 39:67]
-  wire  _GEN_95 = _T_520 & _T_514; // @[Conditional.scala 39:67]
-  wire  _GEN_97 = _T_520 ? 1'h0 : _GEN_87; // @[Conditional.scala 39:67]
+  wire  _GEN_95 = _T_520 ? _T_514 : _GEN_88; // @[Conditional.scala 39:67]
+  wire  _GEN_97 = _T_520 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67]
   wire  _GEN_99 = _T_520 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67]
   wire  _GEN_101 = _T_513 ? _T_517 : _GEN_94; // @[Conditional.scala 39:67]
   wire  _GEN_102 = _T_513 ? _T_514 : _GEN_95; // @[Conditional.scala 39:67]
   wire  _GEN_104 = _T_513 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67]
   wire  _GEN_106 = _T_513 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67]
   reg [3:0] _T_547; // @[Reg.scala 27:20]
+  wire  _T_554 = |io_sb_axi_r_bits_resp; // @[dbg.scala 413:69]
+  wire  _T_555 = sb_bus_rsp_read & _T_554; // @[dbg.scala 413:39]
+  wire  _T_557 = |io_sb_axi_b_bits_resp; // @[dbg.scala 413:122]
+  wire  _T_558 = sb_bus_rsp_write & _T_557; // @[dbg.scala 413:92]
   wire  _T_560 = sb_state == 4'h4; // @[dbg.scala 414:36]
   wire  _T_561 = sb_state == 4'h5; // @[dbg.scala 414:71]
   wire  _T_567 = sb_state == 4'h6; // @[dbg.scala 425:70]
+  wire [63:0] _T_573 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_577 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58]
+  wire [63:0] _T_578 = _T_573 & _T_577; // @[dbg.scala 426:65]
+  wire [63:0] _T_582 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_585 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58]
+  wire [63:0] _T_586 = _T_582 & _T_585; // @[dbg.scala 426:138]
+  wire [63:0] _T_587 = _T_578 | _T_586; // @[dbg.scala 426:96]
+  wire [63:0] _T_591 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_593 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58]
+  wire [63:0] _T_594 = _T_591 & _T_593; // @[dbg.scala 427:45]
+  wire [63:0] _T_595 = _T_587 | _T_594; // @[dbg.scala 426:168]
+  wire [63:0] _T_599 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_602 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
+  wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 427:119]
   wire [7:0] _T_608 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [14:0] _T_610 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 429:82]
   wire [14:0] _GEN_115 = {{7'd0}, _T_608}; // @[dbg.scala 429:67]
@@ -58620,6 +59899,24 @@ module dbg(
   wire [7:0] _T_633 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [14:0] _GEN_118 = {{7'd0}, _T_633}; // @[dbg.scala 431:100]
   wire [14:0] _T_635 = _T_629 | _GEN_118; // @[dbg.scala 431:100]
+  wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 448:99]
+  wire [6:0] _T_646 = 4'h8 * _GEN_119; // @[dbg.scala 448:99]
+  wire [63:0] _T_647 = io_sb_axi_r_bits_data >> _T_646; // @[dbg.scala 448:92]
+  wire [63:0] _T_648 = _T_647 & 64'hff; // @[dbg.scala 448:123]
+  wire [63:0] _T_649 = _T_573 & _T_648; // @[dbg.scala 448:59]
+  wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 449:86]
+  wire [6:0] _T_656 = 5'h10 * _GEN_120; // @[dbg.scala 449:86]
+  wire [63:0] _T_657 = io_sb_axi_r_bits_data >> _T_656; // @[dbg.scala 449:78]
+  wire [63:0] _T_658 = _T_657 & 64'hffff; // @[dbg.scala 449:110]
+  wire [63:0] _T_659 = _T_582 & _T_658; // @[dbg.scala 449:45]
+  wire [63:0] _T_660 = _T_649 | _T_659; // @[dbg.scala 448:140]
+  wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 450:86]
+  wire [6:0] _T_667 = 6'h20 * _GEN_121; // @[dbg.scala 450:86]
+  wire [63:0] _T_668 = io_sb_axi_r_bits_data >> _T_667; // @[dbg.scala 450:78]
+  wire [63:0] _T_669 = _T_668 & 64'hffffffff; // @[dbg.scala 450:107]
+  wire [63:0] _T_670 = _T_591 & _T_669; // @[dbg.scala 450:45]
+  wire [63:0] _T_671 = _T_660 | _T_670; // @[dbg.scala 449:129]
+  wire [63:0] _T_677 = _T_599 & io_sb_axi_r_bits_data; // @[dbg.scala 451:45]
   rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -58676,10 +59973,13 @@ module dbg(
   assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 415:26]
   assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 417:26]
   assign io_sb_axi_w_valid = _T_560 | _T_567; // @[dbg.scala 425:21]
+  assign io_sb_axi_w_bits_data = _T_595 | _T_603; // @[dbg.scala 426:25]
   assign io_sb_axi_w_bits_strb = _T_635[7:0]; // @[dbg.scala 429:25]
+  assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 446:21]
   assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 435:22]
   assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 436:26]
   assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 438:26]
+  assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 447:21]
   assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_482 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 333:35]
   assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 334:35]
   assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_471 ? 2'h2 : _T_491; // @[dbg.scala 335:34]
@@ -58699,6 +59999,7 @@ module dbg(
   assign sbaddress0_reg = _T_118; // @[dbg.scala 166:18]
   assign sbcs_sbbusy_wren = _T_502 ? sb_state_en : _GEN_104; // @[dbg.scala 342:20 dbg.scala 351:24 dbg.scala 399:24]
   assign sbcs_sberror_wren = _T_502 ? _T_508 : _GEN_102; // @[dbg.scala 344:21 dbg.scala 353:25 dbg.scala 359:25 dbg.scala 365:25 dbg.scala 387:25 dbg.scala 393:25]
+  assign sb_bus_rdata = _T_671 | _T_677; // @[dbg.scala 448:16]
   assign sbaddress0_reg_wren1 = _T_502 ? 1'h0 : _GEN_106; // @[dbg.scala 346:24 dbg.scala 401:28]
   assign dmstatus_reg = {_T_163,_T_159}; // @[dbg.scala 191:16]
   assign dmstatus_havereset = _T_192; // @[dbg.scala 208:22]
@@ -58707,6 +60008,12 @@ module dbg(
   assign dmstatus_running = ~_T_183; // @[dbg.scala 199:20]
   assign dmstatus_halted = _T_188; // @[dbg.scala 204:19]
   assign abstractcs_busy_wren = _T_300 ? 1'h0 : _GEN_36; // @[dbg.scala 266:24 dbg.scala 287:28 dbg.scala 305:28]
+  assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 408:19]
+  assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 409:25]
+  assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 410:25]
+  assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 411:19]
+  assign sb_bus_rsp_error = _T_555 | _T_558; // @[dbg.scala 413:20]
+  assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 412:20]
   assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 343:19 dbg.scala 352:23 dbg.scala 400:23]
   assign data1_reg = _T_299; // @[dbg.scala 259:13]
   assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 132:12]
@@ -58782,33 +60089,37 @@ initial begin
   _RAND_4 = {1{`RANDOM}};
   temp_sbcs_14_12 = _RAND_4[2:0];
   _RAND_5 = {1{`RANDOM}};
-  _T_118 = _RAND_5[31:0];
+  sbdata0_reg = _RAND_5[31:0];
   _RAND_6 = {1{`RANDOM}};
-  dm_temp = _RAND_6[3:0];
+  sbdata1_reg = _RAND_6[31:0];
   _RAND_7 = {1{`RANDOM}};
-  dm_temp_0 = _RAND_7[0:0];
+  _T_118 = _RAND_7[31:0];
   _RAND_8 = {1{`RANDOM}};
-  dmcontrol_wren_Q = _RAND_8[0:0];
+  dm_temp = _RAND_8[3:0];
   _RAND_9 = {1{`RANDOM}};
-  _T_185 = _RAND_9[0:0];
+  dm_temp_0 = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  _T_188 = _RAND_10[0:0];
+  dmcontrol_wren_Q = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  _T_192 = _RAND_11[0:0];
+  _T_185 = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  abs_temp_12 = _RAND_12[0:0];
+  _T_188 = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  abs_temp_10_8 = _RAND_13[2:0];
+  _T_192 = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  command_reg = _RAND_14[31:0];
+  abs_temp_12 = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  data0_reg = _RAND_15[31:0];
+  abs_temp_10_8 = _RAND_15[2:0];
   _RAND_16 = {1{`RANDOM}};
-  _T_299 = _RAND_16[31:0];
+  command_reg = _RAND_16[31:0];
   _RAND_17 = {1{`RANDOM}};
-  _T_468 = _RAND_17[2:0];
+  data0_reg = _RAND_17[31:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_547 = _RAND_18[3:0];
+  _T_299 = _RAND_18[31:0];
+  _RAND_19 = {1{`RANDOM}};
+  _T_468 = _RAND_19[2:0];
+  _RAND_20 = {1{`RANDOM}};
+  _T_547 = _RAND_20[3:0];
 `endif // RANDOMIZE_REG_INIT
   if (dbg_dm_rst_l) begin
     temp_sbcs_22 = 1'h0;
@@ -58825,6 +60136,12 @@ initial begin
   if (rst_not) begin
     temp_sbcs_14_12 = 3'h0;
   end
+  if (dbg_dm_rst_l) begin
+    sbdata0_reg = 32'h0;
+  end
+  if (dbg_dm_rst_l) begin
+    sbdata1_reg = 32'h0;
+  end
   if (dbg_dm_rst_l) begin
     _T_118 = 32'h0;
   end
@@ -58936,6 +60253,20 @@ end // initial
       end
     end
   end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      sbdata0_reg <= 32'h0;
+    end else begin
+      sbdata0_reg <= _T_95 | _T_99;
+    end
+  end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      sbdata1_reg <= 32'h0;
+    end else begin
+      sbdata1_reg <= _T_102 | _T_106;
+    end
+  end
   always @(posedge rvclkhdr_4_io_l1clk or posedge dbg_dm_rst_l) begin
     if (dbg_dm_rst_l) begin
       _T_118 <= 32'h0;
@@ -59104,7 +60435,13 @@ end // initial
       end else if (_T_527) begin
         _T_547 <= 4'h7;
       end else if (_T_529) begin
-        _T_547 <= 4'h6;
+        if (_T_530) begin
+          _T_547 <= 4'h8;
+        end else if (sb_bus_cmd_write_data) begin
+          _T_547 <= 4'h5;
+        end else begin
+          _T_547 <= 4'h6;
+        end
       end else if (_T_535) begin
         _T_547 <= 4'h8;
       end else if (_T_537) begin
@@ -66783,11 +68120,11 @@ module lsu_bus_buffer(
   input         clock,
   input         reset,
   input         io_scan_mode,
+  output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
   output        io_tlu_busbuff_lsu_pmu_bus_busy,
   input         io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
-  input         io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
   input         io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
   output        io_tlu_busbuff_lsu_imprecise_error_load_any,
   output        io_tlu_busbuff_lsu_imprecise_error_store_any,
@@ -66833,14 +68170,29 @@ module lsu_bus_buffer(
   input         io_ldst_dual_m,
   input         io_ldst_dual_r,
   input  [7:0]  io_ldst_byteen_ext_m,
+  input         io_lsu_axi_aw_ready,
   output        io_lsu_axi_aw_valid,
+  output [2:0]  io_lsu_axi_aw_bits_id,
   output [31:0] io_lsu_axi_aw_bits_addr,
   output [2:0]  io_lsu_axi_aw_bits_size,
+  input         io_lsu_axi_w_ready,
   output        io_lsu_axi_w_valid,
+  output [63:0] io_lsu_axi_w_bits_data,
   output [7:0]  io_lsu_axi_w_bits_strb,
+  output        io_lsu_axi_b_ready,
+  input         io_lsu_axi_b_valid,
+  input  [1:0]  io_lsu_axi_b_bits_resp,
+  input  [2:0]  io_lsu_axi_b_bits_id,
+  input         io_lsu_axi_ar_ready,
   output        io_lsu_axi_ar_valid,
+  output [2:0]  io_lsu_axi_ar_bits_id,
   output [31:0] io_lsu_axi_ar_bits_addr,
   output [2:0]  io_lsu_axi_ar_bits_size,
+  output        io_lsu_axi_r_ready,
+  input         io_lsu_axi_r_valid,
+  input  [2:0]  io_lsu_axi_r_bits_id,
+  input  [63:0] io_lsu_axi_r_bits_data,
+  input  [1:0]  io_lsu_axi_r_bits_resp,
   input         io_lsu_bus_clk_en,
   input         io_lsu_bus_clk_en_q,
   output        io_lsu_busreq_r,
@@ -66931,7 +68283,7 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_75;
   reg [31:0] _RAND_76;
   reg [31:0] _RAND_77;
-  reg [31:0] _RAND_78;
+  reg [63:0] _RAND_78;
   reg [31:0] _RAND_79;
   reg [31:0] _RAND_80;
   reg [31:0] _RAND_81;
@@ -66951,6 +68303,13 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_95;
   reg [31:0] _RAND_96;
   reg [31:0] _RAND_97;
+  reg [31:0] _RAND_98;
+  reg [31:0] _RAND_99;
+  reg [31:0] _RAND_100;
+  reg [31:0] _RAND_101;
+  reg [31:0] _RAND_102;
+  reg [31:0] _RAND_103;
+  reg [31:0] _RAND_104;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
@@ -67624,74 +68983,26 @@ module lsu_bus_buffer(
   wire  _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 206:56]
   wire  ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 206:54]
   wire  _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 208:36]
-  reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 251:55]
-  wire  _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 214:62]
-  wire  _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 214:48]
-  wire  _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 233:54]
-  wire  _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 233:80]
-  wire  _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 233:93]
-  wire  _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 233:129]
-  wire  _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 233:106]
-  wire  _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 233:152]
-  wire  _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 233:150]
-  wire  _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 233:175]
-  wire  ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 233:173]
-  wire  ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 234:20]
-  wire  _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 214:98]
-  wire  _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 214:82]
-  wire  _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 214:80]
-  wire  _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 215:5]
   wire  _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 209:44]
   wire  _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 209:42]
   wire  _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 209:61]
   wire  _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 209:120]
   wire  _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 209:100]
   wire  ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 209:74]
-  wire  _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 215:16]
   reg  ibuf_sideeffect; // @[Reg.scala 27:20]
-  wire  _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 215:35]
-  wire  _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 215:55]
-  wire  _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 215:53]
-  wire  _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 215:67]
-  wire  ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 214:32]
-  wire  _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 208:34]
+  wire  _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 208:34]
   wire  ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 208:49]
   reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 615:49]
   reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 614:49]
   reg [1:0] ibuf_tag; // @[Reg.scala 27:20]
   wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58]
-  wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 224:77]
-  wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 229:8]
   wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 230:8]
-  wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 228:46]
-  wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 229:8]
   wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 230:8]
-  wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 228:46]
-  wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 229:8]
   wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 230:8]
-  wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 228:46]
-  wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 229:8]
   wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 230:8]
-  wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 228:46]
-  wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58]
-  wire  _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 231:59]
-  wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 231:93]
-  wire  _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 235:65]
-  wire  _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 235:63]
-  wire  _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 235:96]
-  wire  _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 235:48]
-  wire  _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 235:96]
-  wire  _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 235:48]
-  wire  _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 235:96]
-  wire  _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 235:48]
-  wire  _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 235:96]
-  wire  _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 235:48]
-  wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58]
-  wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 236:45]
-  wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 236:45]
-  wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 236:45]
-  wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 236:45]
-  wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58]
+  wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58]
+  wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58]
+  wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58]
   wire  _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 238:58]
   wire  _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 238:93]
   reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20]
@@ -67700,24 +69011,10 @@ module lsu_bus_buffer(
   reg  ibuf_nomerge; // @[Reg.scala 27:20]
   reg  ibuf_unsign; // @[Reg.scala 27:20]
   reg [1:0] ibuf_sz; // @[Reg.scala 27:20]
-  wire  _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 521:64]
   wire  _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 521:91]
-  wire  _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 521:89]
-  wire  _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 521:64]
   wire  _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 521:91]
-  wire  _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 521:89]
-  wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 521:142]
-  wire  _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 521:64]
   wire  _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 521:91]
-  wire  _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 521:89]
-  wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 521:142]
-  wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 521:142]
-  wire  _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 521:64]
   wire  _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 521:91]
-  wire  _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 521:89]
-  wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 521:142]
-  wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 521:142]
-  wire  _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 261:43]
   wire  _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 522:73]
   wire  _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 522:73]
   wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 522:126]
@@ -67728,11 +69025,6 @@ module lsu_bus_buffer(
   wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 522:126]
   wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 522:126]
   wire  _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 261:72]
-  wire  _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 261:51]
-  reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 360:54]
-  wire  _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 261:97]
-  wire  _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 261:80]
-  wire  _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 261:114]
   wire  _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 377:58]
   wire  _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 377:45]
   wire  _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 377:63]
@@ -67767,18 +69059,9 @@ module lsu_bus_buffer(
   wire  _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 262:114]
   wire  _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 262:114]
   reg  buf_nomerge_0; // @[Reg.scala 27:20]
-  wire  _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72]
   reg  buf_nomerge_1; // @[Reg.scala 27:20]
-  wire  _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72]
   reg  buf_nomerge_2; // @[Reg.scala 27:20]
-  wire  _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72]
   reg  buf_nomerge_3; // @[Reg.scala 27:20]
-  wire  _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72]
-  wire  _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72]
-  wire  _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72]
-  wire  _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72]
-  wire  _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 262:31]
-  wire  _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 262:29]
   reg  _T_4330; // @[Reg.scala 27:20]
   reg  _T_4327; // @[Reg.scala 27:20]
   reg  _T_4324; // @[Reg.scala 27:20]
@@ -67792,7 +69075,6 @@ module lsu_bus_buffer(
   wire  _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72]
   wire  _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72]
   wire  _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 263:5]
-  wire  _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 262:140]
   wire  _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 265:58]
   wire  _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 265:72]
   wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72]
@@ -67804,12 +69086,6 @@ module lsu_bus_buffer(
   wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72]
   wire  _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 265:123]
   wire  obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 265:101]
-  wire  _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 263:119]
-  wire  obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 263:117]
-  wire  _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 264:75]
-  wire  _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 264:95]
-  wire  _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 264:79]
-  wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 264:123]
   wire  _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 523:63]
   wire  _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 523:74]
   wire  _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 523:63]
@@ -67954,12 +69230,18 @@ module lsu_bus_buffer(
   wire  _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 284:164]
   wire  _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 282:98]
   reg  obuf_write; // @[Reg.scala 27:20]
+  reg  obuf_cmd_done; // @[lsu_bus_buffer.scala 347:54]
+  reg  obuf_data_done; // @[lsu_bus_buffer.scala 348:55]
+  wire  _T_4856 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 555:54]
+  wire  _T_4857 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 555:75]
+  wire  _T_4858 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 555:153]
+  wire  _T_4859 = _T_4856 ? _T_4857 : _T_4858; // @[lsu_bus_buffer.scala 555:39]
+  wire  bus_cmd_ready = obuf_write ? _T_4859 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 555:23]
   wire  _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 286:48]
+  wire  _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 286:46]
   reg  obuf_nosend; // @[Reg.scala 27:20]
-  wire  _T_1233 = _T_1231 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60]
+  wire  _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60]
   wire  _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 286:29]
-  wire  _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 286:77]
-  wire  _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 286:75]
   reg [31:0] obuf_addr; // @[lib.scala 374:16]
   wire  _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 553:56]
   wire  _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 553:38]
@@ -67997,11 +69279,19 @@ module lsu_bus_buffer(
   wire  _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72]
   wire  bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72]
   wire  _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 286:118]
-  wire  _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 286:116]
+  wire  _T_1240 = _T_1234 & _T_1239; // @[lsu_bus_buffer.scala 286:116]
   wire  obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 286:142]
   wire  _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 288:47]
+  wire  bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40]
+  wire  _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35]
+  wire  bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 557:40]
+  wire  _T_4864 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 558:70]
+  wire  _T_4865 = _T_4863 & _T_4864; // @[lsu_bus_buffer.scala 558:52]
+  wire  _T_4866 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 558:112]
+  wire  bus_cmd_sent = _T_4865 | _T_4866; // @[lsu_bus_buffer.scala 558:89]
+  wire  _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 288:33]
   wire  _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 288:65]
-  wire  _T_1245 = _T_1242 & _T_1244; // @[lsu_bus_buffer.scala 288:63]
+  wire  _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 288:63]
   wire  _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:77]
   wire  obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 288:98]
   wire  obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 289:26]
@@ -68037,6 +69327,8 @@ module lsu_bus_buffer(
   wire  _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:104]
   wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58]
   wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 392:11]
+  wire  _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 303:39]
+  wire  _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 303:26]
   wire  _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 307:72]
   wire  _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 307:98]
   wire  _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 307:96]
@@ -68058,8 +69350,23 @@ module lsu_bus_buffer(
   wire  _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 321:128]
   wire  _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 322:20]
   wire  _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 322:18]
-  wire  obuf_nosend_in = _T_1348 & _T_1350; // @[lsu_bus_buffer.scala 321:177]
+  reg  obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 349:56]
+  wire  bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 559:38]
+  reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 350:55]
+  wire  _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 322:90]
+  wire  _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 322:70]
+  wire  _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 322:55]
+  wire  _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 322:53]
+  wire  _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 322:34]
+  wire  obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 321:177]
+  wire  _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 315:44]
+  wire  _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 315:42]
+  wire  _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 315:29]
+  wire  _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 315:61]
+  wire  _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 315:79]
+  wire  _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20]
   wire  _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37]
+  wire  _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35]
   wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58]
   wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58]
   wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46]
@@ -68099,6 +69406,34 @@ module lsu_bus_buffer(
   wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58]
   wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 326:8]
   wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 325:28]
+  wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 328:44]
+  wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72]
+  wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72]
+  wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72]
+  wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 329:8]
+  wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 328:26]
+  wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 330:44]
+  wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72]
+  wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72]
+  wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72]
+  wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58]
+  wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 331:8]
+  wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 330:26]
   wire  _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 337:30]
   wire  _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 337:43]
   wire  _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 337:59]
@@ -68151,10 +69486,20 @@ module lsu_bus_buffer(
   wire  _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80]
   wire  _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63]
   wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58]
+  wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 333:44]
+  wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 333:44]
+  wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58]
   wire  _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58]
   wire  _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93]
   reg [1:0] obuf_sz; // @[Reg.scala 27:20]
   reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
+  reg [63:0] obuf_data; // @[lib.scala 374:16]
   wire  _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65]
   wire  _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30]
   wire  _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 364:19]
@@ -68190,6 +69535,7 @@ module lsu_bus_buffer(
   wire  _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 363:76]
   wire  _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 363:65]
   wire  _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 364:30]
+  wire  _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 364:19]
   wire  _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 365:18]
   wire  _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 365:57]
   wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16]
@@ -68265,31 +69611,63 @@ module lsu_bus_buffer(
   wire  _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:104]
   wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58]
   wire  _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77]
-  wire  _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 443:97]
-  wire  _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 443:95]
   wire  _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
-  wire  _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 443:112]
   wire  _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144]
   wire  _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
   wire  _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:161]
   wire  _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 443:132]
   wire  _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 443:63]
   wire  _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
-  wire  _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46]
   wire  _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 560:39]
+  wire  _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 468:73]
+  wire  _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 468:52]
+  wire  _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:46]
   reg  _T_4307; // @[Reg.scala 27:20]
   reg  _T_4305; // @[Reg.scala 27:20]
   reg  _T_4303; // @[Reg.scala 27:20]
   reg  _T_4301; // @[Reg.scala 27:20]
   wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58]
+  reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 470:27]
+  wire  _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 471:44]
+  wire  _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 471:42]
+  wire  _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 471:74]
+  wire  _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 470:71]
+  wire  _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 469:25]
+  wire  _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 468:105]
+  wire  _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67]
+  wire  _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58]
   wire  _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
   wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 483:21]
-  wire  _GEN_53 = _T_3555 & buf_cmd_state_bus_en_0; // @[Conditional.scala 39:67]
+  reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20]
+  reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20]
+  reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20]
+  wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 483:58]
+  wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 483:38]
+  wire  _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 482:95]
+  wire  _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 482:45]
+  wire  _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67]
+  wire  _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67]
   wire  _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58]
   wire  _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -68309,7 +69687,7 @@ module lsu_bus_buffer(
   wire  _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67]
   wire  buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58]
   wire  _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 405:94]
-  wire  _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23]
+  wire  _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23]
   wire  _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 407:41]
   wire  _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 407:71]
   wire  _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 407:92]
@@ -68341,21 +69719,50 @@ module lsu_bus_buffer(
   wire  _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 408:97]
   wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58]
   wire  _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
-  wire  _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 443:112]
   wire  _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
   wire  _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 443:161]
   wire  _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 443:132]
   wire  _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 443:63]
   wire  _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
-  wire  _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73]
+  wire  _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 468:52]
+  wire  _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:46]
+  wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 470:27]
+  wire  _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 471:44]
+  wire  _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 471:42]
+  wire  _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 471:74]
+  wire  _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 470:71]
+  wire  _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 469:25]
+  wire  _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 468:105]
+  wire  _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67]
+  wire  _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67]
+  wire  _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58]
   wire  _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
   wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 483:21]
-  wire  _GEN_129 = _T_3748 & buf_cmd_state_bus_en_1; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 483:58]
+  wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 483:38]
+  wire  _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 482:95]
+  wire  _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 482:45]
+  wire  _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67]
+  wire  _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67]
+  wire  _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67]
   wire  _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58]
   wire  _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -68402,21 +69809,50 @@ module lsu_bus_buffer(
   wire  _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 408:97]
   wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58]
   wire  _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
-  wire  _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 443:112]
   wire  _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
   wire  _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 443:161]
   wire  _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 443:132]
   wire  _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 443:63]
   wire  _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
-  wire  _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73]
+  wire  _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 468:52]
+  wire  _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:46]
+  wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 470:27]
+  wire  _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 471:44]
+  wire  _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 471:42]
+  wire  _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 471:74]
+  wire  _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 470:71]
+  wire  _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 469:25]
+  wire  _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 468:105]
+  wire  _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67]
+  wire  _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67]
+  wire  _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58]
   wire  _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
   wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 483:21]
-  wire  _GEN_205 = _T_3941 & buf_cmd_state_bus_en_2; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 483:58]
+  wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 483:38]
+  wire  _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 482:95]
+  wire  _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 482:45]
+  wire  _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67]
+  wire  _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67]
+  wire  _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67]
   wire  _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58]
   wire  _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -68463,21 +69899,50 @@ module lsu_bus_buffer(
   wire  _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 408:97]
   wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58]
   wire  _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
-  wire  _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 443:112]
   wire  _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
   wire  _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 443:161]
   wire  _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 443:132]
   wire  _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 443:63]
   wire  _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
-  wire  _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73]
+  wire  _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 468:52]
+  wire  _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:46]
+  wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 470:47]
+  wire  _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 470:27]
+  wire  _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 471:44]
+  wire  _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 471:42]
+  wire  _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 471:94]
+  wire  _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 471:74]
+  wire  _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 470:71]
+  wire  _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 469:25]
+  wire  _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 468:105]
+  wire  _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67]
+  wire  _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67]
+  wire  _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58]
   wire  _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
   wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 483:21]
-  wire  _GEN_281 = _T_4134 & buf_cmd_state_bus_en_3; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 483:58]
+  wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 483:58]
+  wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 483:58]
+  wire  _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 483:38]
+  wire  _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 482:95]
+  wire  _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 482:45]
+  wire  _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67]
+  wire  _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67]
+  wire  _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67]
   wire  _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58]
   wire  _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -68635,11 +70100,7 @@ module lsu_bus_buffer(
   wire  _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 419:88]
   wire  _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 419:88]
   wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58]
-  wire  _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 425:63]
-  wire  _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 425:63]
-  wire  _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 425:63]
-  wire  _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 425:63]
-  wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58]
+  wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58]
   wire  _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 427:35]
   wire  _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 427:35]
   wire  _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 427:35]
@@ -68680,10 +70141,32 @@ module lsu_bus_buffer(
   wire  _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
   wire  _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
   wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58]
+  wire  _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 453:89]
+  wire  _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 453:104]
   wire  _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3594 = io_dec_tlu_force_halt | buf_write[0]; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
+  wire  _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
+  wire  _T_4872 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:64]
+  wire  bus_rsp_read_error = bus_rsp_read & _T_4872; // @[lsu_bus_buffer.scala 564:38]
+  wire  _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
+  wire  _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 475:91]
+  wire  _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 476:31]
+  wire  _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 476:46]
+  wire  _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 475:143]
+  wire  _T_4870 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 563:66]
+  wire  bus_rsp_write_error = bus_rsp_write & _T_4870; // @[lsu_bus_buffer.scala 563:40]
+  wire  _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 477:53]
+  wire  _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 476:88]
+  wire  _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 475:68]
+  wire  _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67]
+  wire  _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
+  wire  buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58]
+  wire  _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 465:73]
+  wire  _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
+  wire  _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 466:45]
@@ -68712,6 +70195,10 @@ module lsu_bus_buffer(
   wire  _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 467:53]
+  wire  _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
+  wire  _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
+  wire  _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 478:50]
+  wire  _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67]
@@ -68719,11 +70206,14 @@ module lsu_bus_buffer(
   wire  _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
   wire  _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
   wire  _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
+  wire  _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67]
   wire  _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
   wire  _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
   wire  _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67]
+  wire  _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67]
   wire  _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
   wire  _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67]
+  wire  _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
   wire  _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
   wire  buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58]
@@ -68731,7 +70221,22 @@ module lsu_bus_buffer(
   wire  _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3787 = io_dec_tlu_force_halt | buf_write[1]; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
+  wire  _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
+  wire  _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
+  wire  _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 475:91]
+  wire  _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 476:31]
+  wire  _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 476:46]
+  wire  _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 475:143]
+  wire  _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 477:53]
+  wire  _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 476:88]
+  wire  _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 475:68]
+  wire  _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67]
+  wire  _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67]
+  wire  _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67]
+  wire  buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58]
+  wire  _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
+  wire  _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 466:45]
@@ -68757,6 +70262,10 @@ module lsu_bus_buffer(
   wire  _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 467:53]
+  wire  _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
+  wire  _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
+  wire  _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 478:50]
+  wire  _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67]
@@ -68764,11 +70273,14 @@ module lsu_bus_buffer(
   wire  _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67]
   wire  _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67]
   wire  _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67]
+  wire  _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67]
   wire  _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67]
   wire  _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67]
   wire  _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67]
+  wire  _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67]
   wire  _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67]
   wire  _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67]
+  wire  _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67]
   wire  _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67]
   wire  buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58]
@@ -68776,7 +70288,22 @@ module lsu_bus_buffer(
   wire  _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3980 = io_dec_tlu_force_halt | buf_write[2]; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
+  wire  _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
+  wire  _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
+  wire  _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 475:91]
+  wire  _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 476:31]
+  wire  _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 476:46]
+  wire  _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 475:143]
+  wire  _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 477:53]
+  wire  _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 476:88]
+  wire  _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 475:68]
+  wire  _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67]
+  wire  _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67]
+  wire  _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67]
+  wire  buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58]
+  wire  _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
+  wire  _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 466:45]
@@ -68802,6 +70329,10 @@ module lsu_bus_buffer(
   wire  _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 467:53]
+  wire  _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
+  wire  _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
+  wire  _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 478:50]
+  wire  _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67]
@@ -68809,11 +70340,14 @@ module lsu_bus_buffer(
   wire  _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67]
   wire  _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67]
   wire  _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67]
+  wire  _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67]
   wire  _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67]
   wire  _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67]
   wire  _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67]
+  wire  _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67]
   wire  _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67]
   wire  _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67]
+  wire  _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67]
   wire  _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67]
   wire  buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58]
@@ -68821,7 +70355,22 @@ module lsu_bus_buffer(
   wire  _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_4173 = io_dec_tlu_force_halt | buf_write[3]; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
+  wire  _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
+  wire  _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
+  wire  _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 475:91]
+  wire  _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 476:31]
+  wire  _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 476:46]
+  wire  _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 475:143]
+  wire  _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 477:53]
+  wire  _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 476:88]
+  wire  _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 475:68]
+  wire  _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67]
+  wire  _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67]
+  wire  _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67]
+  wire  buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58]
+  wire  _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
+  wire  _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 466:45]
@@ -68847,6 +70396,10 @@ module lsu_bus_buffer(
   wire  _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 467:53]
+  wire  _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
+  wire  _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
+  wire  _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 478:50]
+  wire  _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67]
@@ -68854,11 +70407,14 @@ module lsu_bus_buffer(
   wire  _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67]
   wire  _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67]
   wire  _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67]
+  wire  _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67]
   wire  _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67]
   wire  _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67]
   wire  _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67]
+  wire  _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67]
   wire  _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67]
   wire  _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67]
+  wire  _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67]
   wire  _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67]
   wire  buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58]
@@ -68873,22 +70429,26 @@ module lsu_bus_buffer(
   reg  _T_4401; // @[lsu_bus_buffer.scala 517:80]
   reg  _T_4396; // @[lsu_bus_buffer.scala 517:80]
   wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58]
+  wire  _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 517:126]
+  wire  _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 517:126]
+  wire  _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 517:126]
+  wire  _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 517:126]
   wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
   wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 520:28]
   wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
   wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 520:94]
   wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 520:88]
-  wire [2:0] _GEN_376 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154]
-  wire [3:0] _T_4420 = _T_4419 + _GEN_376; // @[lsu_bus_buffer.scala 520:154]
+  wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154]
+  wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 520:154]
   wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 520:217]
-  wire [1:0] _GEN_377 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217]
-  wire [2:0] _T_4426 = _T_4425 + _GEN_377; // @[lsu_bus_buffer.scala 520:217]
-  wire [2:0] _GEN_378 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217]
-  wire [3:0] _T_4427 = _T_4426 + _GEN_378; // @[lsu_bus_buffer.scala 520:217]
+  wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217]
+  wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 520:217]
+  wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217]
+  wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 520:217]
   wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 520:169]
   wire  _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 526:52]
   wire  _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 526:92]
@@ -68944,8 +70504,8 @@ module lsu_bus_buffer(
   wire  _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 536:119]
   wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_379 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4610 = _GEN_379 | _T_4607; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72]
   wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
@@ -68991,8 +70551,8 @@ module lsu_bus_buffer(
   wire  _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72]
   wire  lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72]
   wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
-  wire [3:0] _GEN_380 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121]
-  wire [5:0] _T_4740 = _GEN_380 * 4'h8; // @[lsu_bus_buffer.scala 543:121]
+  wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121]
+  wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 543:121]
   wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 543:92]
   wire  _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 545:82]
   wire  _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 546:94]
@@ -69017,11 +70577,15 @@ module lsu_bus_buffer(
   wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72]
   wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72]
   wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72]
-  wire [63:0] _GEN_381 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72]
-  wire [63:0] _T_4776 = _GEN_381 | _T_4772; // @[Mux.scala 27:72]
+  wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72]
+  wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72]
   wire  _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37]
+  wire  _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52]
+  wire  _T_4876 = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:50]
   wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58]
   wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58]
+  wire  _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51]
+  wire  _T_4888 = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:49]
   wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire  _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37]
   wire  _T_4897 = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:51]
@@ -69047,8 +70611,8 @@ module lsu_bus_buffer(
   wire  _T_4954 = _T_4952 & buf_write[3]; // @[lsu_bus_buffer.scala 599:108]
   wire [1:0] _T_4957 = _T_4949 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_4958 = _T_4954 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_382 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4960 = _GEN_382 | _T_4957; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_394 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4960 = _GEN_394 | _T_4957; // @[Mux.scala 27:72]
   wire [1:0] lsu_imprecise_error_store_tag = _T_4960 | _T_4958; // @[Mux.scala 27:72]
   wire  _T_4962 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 601:97]
   wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53]
@@ -69057,8 +70621,15 @@ module lsu_bus_buffer(
   wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53]
   wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 602:53]
   wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 602:53]
+  wire  _T_4967 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 608:82]
   wire  _T_4970 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 609:60]
-  wire  _T_4977 = io_lsu_axi_aw_valid | io_lsu_axi_w_valid; // @[lsu_bus_buffer.scala 612:83]
+  wire  _T_4973 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 612:61]
+  wire  _T_4974 = io_lsu_axi_aw_valid & _T_4973; // @[lsu_bus_buffer.scala 612:59]
+  wire  _T_4975 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 612:107]
+  wire  _T_4976 = io_lsu_axi_w_valid & _T_4975; // @[lsu_bus_buffer.scala 612:105]
+  wire  _T_4977 = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 612:83]
+  wire  _T_4978 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 612:153]
+  wire  _T_4979 = io_lsu_axi_ar_valid & _T_4978; // @[lsu_bus_buffer.scala 612:151]
   wire  _T_4983 = ~io_flush_r; // @[lsu_bus_buffer.scala 616:75]
   wire  _T_4984 = io_lsu_busreq_m & _T_4983; // @[lsu_bus_buffer.scala 616:73]
   reg  _T_4987; // @[lsu_bus_buffer.scala 616:56]
@@ -69134,9 +70705,10 @@ module lsu_bus_buffer(
     .io_en(rvclkhdr_11_io_en),
     .io_scan_mode(rvclkhdr_11_io_scan_mode)
   );
+  assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4967 | _T_4866; // @[lsu_bus_buffer.scala 608:35]
   assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4970 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 609:41]
   assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 610:36]
-  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | io_lsu_axi_ar_valid; // @[lsu_bus_buffer.scala 612:35]
+  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | _T_4979; // @[lsu_bus_buffer.scala 612:35]
   assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4962; // @[lsu_bus_buffer.scala 601:47]
   assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4932 | _T_4930; // @[lsu_bus_buffer.scala 598:48]
   assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 602:47]
@@ -69148,14 +70720,19 @@ module lsu_bus_buffer(
   assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 535:48]
   assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 536:46]
   assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42]
-  assign io_lsu_axi_aw_valid = _T_4874 & _T_1239; // @[lsu_bus_buffer.scala 568:23]
+  assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 568:23]
+  assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25]
   assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27]
   assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27]
-  assign io_lsu_axi_w_valid = _T_4874 & _T_1239; // @[lsu_bus_buffer.scala 580:22]
+  assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 580:22]
+  assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26]
   assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26]
+  assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22]
   assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 585:23]
+  assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25]
   assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27]
   assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27]
+  assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22]
   assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19]
   assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30]
   assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 526:30]
@@ -69189,16 +70766,16 @@ module lsu_bus_buffer(
   assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_8_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17]
+  assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[lib.scala 371:17]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_9_io_en = _T_3721 & buf_state_en_1; // @[lib.scala 371:17]
+  assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[lib.scala 371:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = _T_3914 & buf_state_en_2; // @[lib.scala 371:17]
+  assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[lib.scala 371:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17]
+  assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[lib.scala 371:17]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -69304,65 +70881,65 @@ initial begin
   _RAND_33 = {1{`RANDOM}};
   ibuf_data = _RAND_33[31:0];
   _RAND_34 = {1{`RANDOM}};
-  ibuf_timer = _RAND_34[2:0];
+  ibuf_sideeffect = _RAND_34[0:0];
   _RAND_35 = {1{`RANDOM}};
-  ibuf_sideeffect = _RAND_35[0:0];
+  WrPtr1_r = _RAND_35[1:0];
   _RAND_36 = {1{`RANDOM}};
-  WrPtr1_r = _RAND_36[1:0];
+  WrPtr0_r = _RAND_36[1:0];
   _RAND_37 = {1{`RANDOM}};
-  WrPtr0_r = _RAND_37[1:0];
+  ibuf_tag = _RAND_37[1:0];
   _RAND_38 = {1{`RANDOM}};
-  ibuf_tag = _RAND_38[1:0];
+  ibuf_dualtag = _RAND_38[1:0];
   _RAND_39 = {1{`RANDOM}};
-  ibuf_dualtag = _RAND_39[1:0];
+  ibuf_dual = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  ibuf_dual = _RAND_40[0:0];
+  ibuf_samedw = _RAND_40[0:0];
   _RAND_41 = {1{`RANDOM}};
-  ibuf_samedw = _RAND_41[0:0];
+  ibuf_nomerge = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  ibuf_nomerge = _RAND_42[0:0];
+  ibuf_unsign = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  ibuf_unsign = _RAND_43[0:0];
+  ibuf_sz = _RAND_43[1:0];
   _RAND_44 = {1{`RANDOM}};
-  ibuf_sz = _RAND_44[1:0];
+  buf_nomerge_0 = _RAND_44[0:0];
   _RAND_45 = {1{`RANDOM}};
-  obuf_wr_timer = _RAND_45[2:0];
+  buf_nomerge_1 = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  buf_nomerge_0 = _RAND_46[0:0];
+  buf_nomerge_2 = _RAND_46[0:0];
   _RAND_47 = {1{`RANDOM}};
-  buf_nomerge_1 = _RAND_47[0:0];
+  buf_nomerge_3 = _RAND_47[0:0];
   _RAND_48 = {1{`RANDOM}};
-  buf_nomerge_2 = _RAND_48[0:0];
+  _T_4330 = _RAND_48[0:0];
   _RAND_49 = {1{`RANDOM}};
-  buf_nomerge_3 = _RAND_49[0:0];
+  _T_4327 = _RAND_49[0:0];
   _RAND_50 = {1{`RANDOM}};
-  _T_4330 = _RAND_50[0:0];
+  _T_4324 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  _T_4327 = _RAND_51[0:0];
+  _T_4321 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  _T_4324 = _RAND_52[0:0];
+  obuf_sideeffect = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  _T_4321 = _RAND_53[0:0];
+  buf_dual_3 = _RAND_53[0:0];
   _RAND_54 = {1{`RANDOM}};
-  obuf_sideeffect = _RAND_54[0:0];
+  buf_dual_2 = _RAND_54[0:0];
   _RAND_55 = {1{`RANDOM}};
-  buf_dual_3 = _RAND_55[0:0];
+  buf_dual_1 = _RAND_55[0:0];
   _RAND_56 = {1{`RANDOM}};
-  buf_dual_2 = _RAND_56[0:0];
+  buf_dual_0 = _RAND_56[0:0];
   _RAND_57 = {1{`RANDOM}};
-  buf_dual_1 = _RAND_57[0:0];
+  buf_samedw_3 = _RAND_57[0:0];
   _RAND_58 = {1{`RANDOM}};
-  buf_dual_0 = _RAND_58[0:0];
+  buf_samedw_2 = _RAND_58[0:0];
   _RAND_59 = {1{`RANDOM}};
-  buf_samedw_3 = _RAND_59[0:0];
+  buf_samedw_1 = _RAND_59[0:0];
   _RAND_60 = {1{`RANDOM}};
-  buf_samedw_2 = _RAND_60[0:0];
+  buf_samedw_0 = _RAND_60[0:0];
   _RAND_61 = {1{`RANDOM}};
-  buf_samedw_1 = _RAND_61[0:0];
+  obuf_write = _RAND_61[0:0];
   _RAND_62 = {1{`RANDOM}};
-  buf_samedw_0 = _RAND_62[0:0];
+  obuf_cmd_done = _RAND_62[0:0];
   _RAND_63 = {1{`RANDOM}};
-  obuf_write = _RAND_63[0:0];
+  obuf_data_done = _RAND_63[0:0];
   _RAND_64 = {1{`RANDOM}};
   obuf_nosend = _RAND_64[0:0];
   _RAND_65 = {1{`RANDOM}};
@@ -69376,61 +70953,75 @@ initial begin
   _RAND_69 = {1{`RANDOM}};
   buf_sz_3 = _RAND_69[1:0];
   _RAND_70 = {1{`RANDOM}};
-  buf_dualhi_3 = _RAND_70[0:0];
+  obuf_rdrsp_pend = _RAND_70[0:0];
   _RAND_71 = {1{`RANDOM}};
-  buf_dualhi_2 = _RAND_71[0:0];
+  obuf_rdrsp_tag = _RAND_71[2:0];
   _RAND_72 = {1{`RANDOM}};
-  buf_dualhi_1 = _RAND_72[0:0];
+  buf_dualhi_3 = _RAND_72[0:0];
   _RAND_73 = {1{`RANDOM}};
-  buf_dualhi_0 = _RAND_73[0:0];
+  buf_dualhi_2 = _RAND_73[0:0];
   _RAND_74 = {1{`RANDOM}};
-  obuf_sz = _RAND_74[1:0];
+  buf_dualhi_1 = _RAND_74[0:0];
   _RAND_75 = {1{`RANDOM}};
-  obuf_byteen = _RAND_75[7:0];
+  buf_dualhi_0 = _RAND_75[0:0];
   _RAND_76 = {1{`RANDOM}};
-  buf_rspageQ_0 = _RAND_76[3:0];
+  obuf_sz = _RAND_76[1:0];
   _RAND_77 = {1{`RANDOM}};
-  buf_rspageQ_1 = _RAND_77[3:0];
-  _RAND_78 = {1{`RANDOM}};
-  buf_rspageQ_2 = _RAND_78[3:0];
+  obuf_byteen = _RAND_77[7:0];
+  _RAND_78 = {2{`RANDOM}};
+  obuf_data = _RAND_78[63:0];
   _RAND_79 = {1{`RANDOM}};
-  buf_rspageQ_3 = _RAND_79[3:0];
+  buf_rspageQ_0 = _RAND_79[3:0];
   _RAND_80 = {1{`RANDOM}};
-  _T_4307 = _RAND_80[0:0];
+  buf_rspageQ_1 = _RAND_80[3:0];
   _RAND_81 = {1{`RANDOM}};
-  _T_4305 = _RAND_81[0:0];
+  buf_rspageQ_2 = _RAND_81[3:0];
   _RAND_82 = {1{`RANDOM}};
-  _T_4303 = _RAND_82[0:0];
+  buf_rspageQ_3 = _RAND_82[3:0];
   _RAND_83 = {1{`RANDOM}};
-  _T_4301 = _RAND_83[0:0];
+  _T_4307 = _RAND_83[0:0];
   _RAND_84 = {1{`RANDOM}};
-  buf_dualtag_0 = _RAND_84[1:0];
+  _T_4305 = _RAND_84[0:0];
   _RAND_85 = {1{`RANDOM}};
-  buf_dualtag_1 = _RAND_85[1:0];
+  _T_4303 = _RAND_85[0:0];
   _RAND_86 = {1{`RANDOM}};
-  buf_dualtag_2 = _RAND_86[1:0];
+  _T_4301 = _RAND_86[0:0];
   _RAND_87 = {1{`RANDOM}};
-  buf_dualtag_3 = _RAND_87[1:0];
+  buf_ldfwdtag_0 = _RAND_87[1:0];
   _RAND_88 = {1{`RANDOM}};
-  _T_4336 = _RAND_88[0:0];
+  buf_dualtag_0 = _RAND_88[1:0];
   _RAND_89 = {1{`RANDOM}};
-  _T_4339 = _RAND_89[0:0];
+  buf_ldfwdtag_3 = _RAND_89[1:0];
   _RAND_90 = {1{`RANDOM}};
-  _T_4342 = _RAND_90[0:0];
+  buf_ldfwdtag_2 = _RAND_90[1:0];
   _RAND_91 = {1{`RANDOM}};
-  _T_4345 = _RAND_91[0:0];
+  buf_ldfwdtag_1 = _RAND_91[1:0];
   _RAND_92 = {1{`RANDOM}};
-  _T_4411 = _RAND_92[0:0];
+  buf_dualtag_1 = _RAND_92[1:0];
   _RAND_93 = {1{`RANDOM}};
-  _T_4406 = _RAND_93[0:0];
+  buf_dualtag_2 = _RAND_93[1:0];
   _RAND_94 = {1{`RANDOM}};
-  _T_4401 = _RAND_94[0:0];
+  buf_dualtag_3 = _RAND_94[1:0];
   _RAND_95 = {1{`RANDOM}};
-  _T_4396 = _RAND_95[0:0];
+  _T_4336 = _RAND_95[0:0];
   _RAND_96 = {1{`RANDOM}};
-  lsu_nonblock_load_valid_r = _RAND_96[0:0];
+  _T_4339 = _RAND_96[0:0];
   _RAND_97 = {1{`RANDOM}};
-  _T_4987 = _RAND_97[0:0];
+  _T_4342 = _RAND_97[0:0];
+  _RAND_98 = {1{`RANDOM}};
+  _T_4345 = _RAND_98[0:0];
+  _RAND_99 = {1{`RANDOM}};
+  _T_4411 = _RAND_99[0:0];
+  _RAND_100 = {1{`RANDOM}};
+  _T_4406 = _RAND_100[0:0];
+  _RAND_101 = {1{`RANDOM}};
+  _T_4401 = _RAND_101[0:0];
+  _RAND_102 = {1{`RANDOM}};
+  _T_4396 = _RAND_102[0:0];
+  _RAND_103 = {1{`RANDOM}};
+  lsu_nonblock_load_valid_r = _RAND_103[0:0];
+  _RAND_104 = {1{`RANDOM}};
+  _T_4987 = _RAND_104[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     buf_addr_0 = 32'h0;
@@ -69534,9 +71125,6 @@ initial begin
   if (reset) begin
     ibuf_data = 32'h0;
   end
-  if (reset) begin
-    ibuf_timer = 3'h0;
-  end
   if (reset) begin
     ibuf_sideeffect = 1'h0;
   end
@@ -69567,9 +71155,6 @@ initial begin
   if (reset) begin
     ibuf_sz = 2'h0;
   end
-  if (reset) begin
-    obuf_wr_timer = 3'h0;
-  end
   if (reset) begin
     buf_nomerge_0 = 1'h0;
   end
@@ -69624,6 +71209,12 @@ initial begin
   if (reset) begin
     obuf_write = 1'h0;
   end
+  if (reset) begin
+    obuf_cmd_done = 1'h0;
+  end
+  if (reset) begin
+    obuf_data_done = 1'h0;
+  end
   if (reset) begin
     obuf_nosend = 1'h0;
   end
@@ -69642,6 +71233,12 @@ initial begin
   if (reset) begin
     buf_sz_3 = 2'h0;
   end
+  if (reset) begin
+    obuf_rdrsp_pend = 1'h0;
+  end
+  if (reset) begin
+    obuf_rdrsp_tag = 3'h0;
+  end
   if (reset) begin
     buf_dualhi_3 = 1'h0;
   end
@@ -69660,6 +71257,9 @@ initial begin
   if (reset) begin
     obuf_byteen = 8'h0;
   end
+  if (reset) begin
+    obuf_data = 64'h0;
+  end
   if (reset) begin
     buf_rspageQ_0 = 4'h0;
   end
@@ -69684,9 +71284,21 @@ initial begin
   if (reset) begin
     _T_4301 = 1'h0;
   end
+  if (reset) begin
+    buf_ldfwdtag_0 = 2'h0;
+  end
   if (reset) begin
     buf_dualtag_0 = 2'h0;
   end
+  if (reset) begin
+    buf_ldfwdtag_3 = 2'h0;
+  end
+  if (reset) begin
+    buf_ldfwdtag_2 = 2'h0;
+  end
+  if (reset) begin
+    buf_ldfwdtag_1 = 2'h0;
+  end
   if (reset) begin
     buf_dualtag_1 = 2'h0;
   end
@@ -69790,6 +71402,8 @@ end // initial
       end else if (_T_3555) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
+        end else if (_T_3559) begin
+          buf_state_0 <= 3'h5;
         end else begin
           buf_state_0 <= 3'h3;
         end
@@ -69852,6 +71466,8 @@ end // initial
       end else if (_T_3748) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
+        end else if (_T_3559) begin
+          buf_state_1 <= 3'h5;
         end else begin
           buf_state_1 <= 3'h3;
         end
@@ -69914,6 +71530,8 @@ end // initial
       end else if (_T_3941) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
+        end else if (_T_3559) begin
+          buf_state_2 <= 3'h5;
         end else begin
           buf_state_2 <= 3'h3;
         end
@@ -69976,6 +71594,8 @@ end // initial
       end else if (_T_4134) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
+        end else if (_T_3559) begin
+          buf_state_3 <= 3'h5;
         end else begin
           buf_state_3 <= 3'h3;
         end
@@ -70137,9 +71757,7 @@ end // initial
     if (reset) begin
       ibuf_byteen <= 4'h0;
     end else if (ibuf_wr_en) begin
-      if (_T_866) begin
-        ibuf_byteen <= _T_881;
-      end else if (io_ldst_dual_r) begin
+      if (io_ldst_dual_r) begin
         ibuf_byteen <= ldst_byteen_hi_r;
       end else begin
         ibuf_byteen <= ldst_byteen_lo_r;
@@ -70176,6 +71794,26 @@ end // initial
       end else begin
         buf_data_0 <= store_data_lo_r;
       end
+    end else if (_T_3551) begin
+      buf_data_0 <= 32'h0;
+    end else if (_T_3555) begin
+      if (buf_error_en_0) begin
+        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+      end else if (buf_addr_0[2]) begin
+        buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
+      end else begin
+        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+      end
+    end else if (_T_3589) begin
+      if (_T_3669) begin
+        if (buf_addr_0[2]) begin
+          buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
+        end else begin
+          buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+        end
+      end else begin
+        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+      end
     end else begin
       buf_data_0 <= 32'h0;
     end
@@ -70189,6 +71827,26 @@ end // initial
       end else begin
         buf_data_1 <= store_data_lo_r;
       end
+    end else if (_T_3744) begin
+      buf_data_1 <= 32'h0;
+    end else if (_T_3748) begin
+      if (buf_error_en_1) begin
+        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+      end else if (buf_addr_1[2]) begin
+        buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
+      end else begin
+        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+      end
+    end else if (_T_3782) begin
+      if (_T_3862) begin
+        if (buf_addr_1[2]) begin
+          buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
+        end else begin
+          buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+        end
+      end else begin
+        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+      end
     end else begin
       buf_data_1 <= 32'h0;
     end
@@ -70202,6 +71860,26 @@ end // initial
       end else begin
         buf_data_2 <= store_data_lo_r;
       end
+    end else if (_T_3937) begin
+      buf_data_2 <= 32'h0;
+    end else if (_T_3941) begin
+      if (buf_error_en_2) begin
+        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+      end else if (buf_addr_2[2]) begin
+        buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
+      end else begin
+        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+      end
+    end else if (_T_3975) begin
+      if (_T_4055) begin
+        if (buf_addr_2[2]) begin
+          buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
+        end else begin
+          buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+        end
+      end else begin
+        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+      end
     end else begin
       buf_data_2 <= 32'h0;
     end
@@ -70215,6 +71893,26 @@ end // initial
       end else begin
         buf_data_3 <= store_data_lo_r;
       end
+    end else if (_T_4130) begin
+      buf_data_3 <= 32'h0;
+    end else if (_T_4134) begin
+      if (buf_error_en_3) begin
+        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+      end else if (buf_addr_3[2]) begin
+        buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
+      end else begin
+        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+      end
+    end else if (_T_4168) begin
+      if (_T_4248) begin
+        if (buf_addr_3[2]) begin
+          buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
+        end else begin
+          buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+        end
+      end else begin
+        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+      end
     end else begin
       buf_data_3 <= 32'h0;
     end
@@ -70223,16 +71921,7 @@ end // initial
     if (reset) begin
       ibuf_data <= 32'h0;
     end else begin
-      ibuf_data <= {_T_922,_T_893};
-    end
-  end
-  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
-    if (reset) begin
-      ibuf_timer <= 3'h0;
-    end else if (ibuf_wr_en) begin
-      ibuf_timer <= 3'h0;
-    end else if (_T_923) begin
-      ibuf_timer <= _T_926;
+      ibuf_data <= {_T_922,_T_892};
     end
   end
   always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
@@ -70272,12 +71961,10 @@ end // initial
     if (reset) begin
       ibuf_tag <= 2'h0;
     end else if (ibuf_wr_en) begin
-      if (!(_T_866)) begin
-        if (io_ldst_dual_r) begin
-          ibuf_tag <= WrPtr1_r;
-        end else begin
-          ibuf_tag <= WrPtr0_r;
-        end
+      if (io_ldst_dual_r) begin
+        ibuf_tag <= WrPtr1_r;
+      end else begin
+        ibuf_tag <= WrPtr0_r;
       end
     end
   end
@@ -70323,15 +72010,6 @@ end // initial
       ibuf_sz <= ibuf_sz_in;
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_wr_timer <= 3'h0;
-    end else if (obuf_wr_en) begin
-      obuf_wr_timer <= 3'h0;
-    end else if (_T_1058) begin
-      obuf_wr_timer <= _T_1060;
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_nomerge_0 <= 1'h0;
@@ -70466,6 +72144,20 @@ end // initial
       end
     end
   end
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
+    if (reset) begin
+      obuf_cmd_done <= 1'h0;
+    end else begin
+      obuf_cmd_done <= _T_1305 & _T_4863;
+    end
+  end
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
+    if (reset) begin
+      obuf_data_done <= 1'h0;
+    end else begin
+      obuf_data_done <= _T_1305 & _T_4864;
+    end
+  end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_nosend <= 1'h0;
@@ -70526,6 +72218,20 @@ end // initial
       end
     end
   end
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
+    if (reset) begin
+      obuf_rdrsp_pend <= 1'h0;
+    end else begin
+      obuf_rdrsp_pend <= _T_1330 | _T_1334;
+    end
+  end
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
+    if (reset) begin
+      obuf_rdrsp_tag <= 3'h0;
+    end else if (_T_1332) begin
+      obuf_rdrsp_tag <= obuf_tag0;
+    end
+  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualhi_3 <= 1'h0;
@@ -70572,6 +72278,13 @@ end // initial
       obuf_byteen <= obuf_byteen_in;
     end
   end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+    if (reset) begin
+      obuf_data <= 64'h0;
+    end else begin
+      obuf_data <= {_T_1620,_T_1579};
+    end
+  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_0 <= 4'h0;
@@ -70652,6 +72365,21 @@ end // initial
       end
     end
   end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      buf_ldfwdtag_0 <= 2'h0;
+    end else if (buf_ldfwd_en_0) begin
+      if (_T_3528) begin
+        buf_ldfwdtag_0 <= 2'h0;
+      end else if (_T_3551) begin
+        buf_ldfwdtag_0 <= 2'h0;
+      end else if (_T_3555) begin
+        buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0];
+      end else begin
+        buf_ldfwdtag_0 <= 2'h0;
+      end
+    end
+  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualtag_0 <= 2'h0;
@@ -70665,6 +72393,51 @@ end // initial
       end
     end
   end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      buf_ldfwdtag_3 <= 2'h0;
+    end else if (buf_ldfwd_en_3) begin
+      if (_T_4107) begin
+        buf_ldfwdtag_3 <= 2'h0;
+      end else if (_T_4130) begin
+        buf_ldfwdtag_3 <= 2'h0;
+      end else if (_T_4134) begin
+        buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0];
+      end else begin
+        buf_ldfwdtag_3 <= 2'h0;
+      end
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      buf_ldfwdtag_2 <= 2'h0;
+    end else if (buf_ldfwd_en_2) begin
+      if (_T_3914) begin
+        buf_ldfwdtag_2 <= 2'h0;
+      end else if (_T_3937) begin
+        buf_ldfwdtag_2 <= 2'h0;
+      end else if (_T_3941) begin
+        buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0];
+      end else begin
+        buf_ldfwdtag_2 <= 2'h0;
+      end
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      buf_ldfwdtag_1 <= 2'h0;
+    end else if (buf_ldfwd_en_1) begin
+      if (_T_3721) begin
+        buf_ldfwdtag_1 <= 2'h0;
+      end else if (_T_3744) begin
+        buf_ldfwdtag_1 <= 2'h0;
+      end else if (_T_3748) begin
+        buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0];
+      end else begin
+        buf_ldfwdtag_1 <= 2'h0;
+      end
+    end
+  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualtag_1 <= 2'h0;
@@ -70736,28 +72509,28 @@ end // initial
     if (reset) begin
       _T_4411 <= 1'h0;
     end else begin
-      _T_4411 <= buf_error[3] & _T_4409;
+      _T_4411 <= _T_4408 & _T_4409;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4406 <= 1'h0;
     end else begin
-      _T_4406 <= buf_error[2] & _T_4404;
+      _T_4406 <= _T_4403 & _T_4404;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4401 <= 1'h0;
     end else begin
-      _T_4401 <= buf_error[1] & _T_4399;
+      _T_4401 <= _T_4398 & _T_4399;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4396 <= 1'h0;
     end else begin
-      _T_4396 <= buf_error[0] & _T_4394;
+      _T_4396 <= _T_4393 & _T_4394;
     end
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
@@ -70779,11 +72552,11 @@ module lsu_bus_intf(
   input         clock,
   input         reset,
   input         io_scan_mode,
+  output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
   output        io_tlu_busbuff_lsu_pmu_bus_busy,
   input         io_tlu_busbuff_dec_tlu_external_ldfwd_disable,
-  input         io_tlu_busbuff_dec_tlu_wb_coalescing_disable,
   input         io_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
   output        io_tlu_busbuff_lsu_imprecise_error_load_any,
   output        io_tlu_busbuff_lsu_imprecise_error_store_any,
@@ -70797,14 +72570,27 @@ module lsu_bus_intf(
   input         io_lsu_free_c2_clk,
   input         io_free_clk,
   input         io_lsu_busm_clk,
+  input         io_axi_aw_ready,
   output        io_axi_aw_valid,
+  output [2:0]  io_axi_aw_bits_id,
   output [31:0] io_axi_aw_bits_addr,
   output [2:0]  io_axi_aw_bits_size,
+  input         io_axi_w_ready,
   output        io_axi_w_valid,
+  output [63:0] io_axi_w_bits_data,
   output [7:0]  io_axi_w_bits_strb,
+  input         io_axi_b_valid,
+  input  [1:0]  io_axi_b_bits_resp,
+  input  [2:0]  io_axi_b_bits_id,
+  input         io_axi_ar_ready,
   output        io_axi_ar_valid,
+  output [2:0]  io_axi_ar_bits_id,
   output [31:0] io_axi_ar_bits_addr,
   output [2:0]  io_axi_ar_bits_size,
+  input         io_axi_r_valid,
+  input  [2:0]  io_axi_r_bits_id,
+  input  [63:0] io_axi_r_bits_data,
+  input  [1:0]  io_axi_r_bits_resp,
   input         io_dec_lsu_valid_raw_d,
   input         io_lsu_busreq_m,
   input         io_lsu_pkt_m_valid,
@@ -70856,11 +72642,11 @@ module lsu_bus_intf(
   wire  bus_buffer_clock; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_reset; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 101:39]
@@ -70906,14 +72692,29 @@ module lsu_bus_intf(
   wire  bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 101:39]
   wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39]
+  wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39]
   wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39]
   wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39]
+  wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39]
   wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39]
+  wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 101:39]
+  wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39]
+  wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39]
   wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39]
   wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39]
+  wire  bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39]
+  wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39]
+  wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 101:39]
+  wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 101:39]
@@ -71109,11 +72910,11 @@ module lsu_bus_intf(
     .clock(bus_buffer_clock),
     .reset(bus_buffer_reset),
     .io_scan_mode(bus_buffer_io_scan_mode),
+    .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy),
     .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
-    .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
     .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
     .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any),
     .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any),
@@ -71159,14 +72960,29 @@ module lsu_bus_intf(
     .io_ldst_dual_m(bus_buffer_io_ldst_dual_m),
     .io_ldst_dual_r(bus_buffer_io_ldst_dual_r),
     .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m),
+    .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready),
     .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid),
+    .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id),
     .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr),
     .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size),
+    .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready),
     .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid),
+    .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data),
     .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb),
+    .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready),
+    .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid),
+    .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp),
+    .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id),
+    .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready),
     .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid),
+    .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id),
     .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr),
     .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size),
+    .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready),
+    .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid),
+    .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id),
+    .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data),
+    .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp),
     .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en),
     .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q),
     .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r),
@@ -71178,6 +72994,7 @@ module lsu_bus_intf(
     .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo),
     .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi)
   );
+  assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 104:18]
@@ -71185,11 +73002,14 @@ module lsu_bus_intf(
   assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18]
   assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43]
+  assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43]
+  assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43]
+  assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43]
   assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38]
@@ -71209,7 +73029,6 @@ module lsu_bus_intf(
   assign bus_buffer_reset = reset;
   assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 103:29]
   assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 104:18]
-  assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 104:18]
   assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 104:18]
   assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 106:51]
   assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 107:51]
@@ -71244,6 +73063,16 @@ module lsu_bus_intf(
   assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 147:51]
   assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 148:51]
   assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 149:51]
+  assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 130:43]
+  assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 130:43]
   assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 131:51]
   assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 151:51]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
@@ -71375,11 +73204,11 @@ module lsu(
   input  [31:0] io_lsu_pic_picm_rd_data,
   input  [31:0] io_lsu_exu_exu_lsu_rs1_d,
   input  [31:0] io_lsu_exu_exu_lsu_rs2_d,
+  output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
   input         io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable,
-  input         io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable,
   input         io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable,
   output        io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any,
   output        io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any,
@@ -71404,14 +73233,27 @@ module lsu(
   input  [38:0] io_dccm_rd_data_hi,
   output        io_lsu_tlu_lsu_pmu_load_external_m,
   output        io_lsu_tlu_lsu_pmu_store_external_m,
+  input         io_axi_aw_ready,
   output        io_axi_aw_valid,
+  output [2:0]  io_axi_aw_bits_id,
   output [31:0] io_axi_aw_bits_addr,
   output [2:0]  io_axi_aw_bits_size,
+  input         io_axi_w_ready,
   output        io_axi_w_valid,
+  output [63:0] io_axi_w_bits_data,
   output [7:0]  io_axi_w_bits_strb,
+  input         io_axi_b_valid,
+  input  [1:0]  io_axi_b_bits_resp,
+  input  [2:0]  io_axi_b_bits_id,
+  input         io_axi_ar_ready,
   output        io_axi_ar_valid,
+  output [2:0]  io_axi_ar_bits_id,
   output [31:0] io_axi_ar_bits_addr,
   output [2:0]  io_axi_ar_bits_size,
+  input         io_axi_r_valid,
+  input  [2:0]  io_axi_r_bits_id,
+  input  [63:0] io_axi_r_bits_data,
+  input  [1:0]  io_axi_r_bits_resp,
   input         io_dec_tlu_flush_lower_r,
   input         io_dec_tlu_i0_kill_writeb_r,
   input         io_dec_tlu_force_halt,
@@ -71827,11 +73669,11 @@ module lsu(
   wire  bus_intf_clock; // @[lsu.scala 68:30]
   wire  bus_intf_reset; // @[lsu.scala 68:30]
   wire  bus_intf_io_scan_mode; // @[lsu.scala 68:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30]
-  wire  bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30]
@@ -71845,14 +73687,27 @@ module lsu(
   wire  bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 68:30]
   wire  bus_intf_io_free_clk; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_busm_clk; // @[lsu.scala 68:30]
+  wire  bus_intf_io_axi_aw_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30]
+  wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30]
   wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30]
   wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30]
+  wire  bus_intf_io_axi_w_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_w_valid; // @[lsu.scala 68:30]
+  wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30]
   wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 68:30]
+  wire  bus_intf_io_axi_b_valid; // @[lsu.scala 68:30]
+  wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 68:30]
+  wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 68:30]
+  wire  bus_intf_io_axi_ar_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30]
+  wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30]
   wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30]
   wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30]
+  wire  bus_intf_io_axi_r_valid; // @[lsu.scala 68:30]
+  wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30]
+  wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30]
+  wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 68:30]
   wire  bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_busreq_m; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 68:30]
@@ -72294,11 +74149,11 @@ module lsu(
     .clock(bus_intf_clock),
     .reset(bus_intf_reset),
     .io_scan_mode(bus_intf_io_scan_mode),
+    .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy),
     .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable),
-    .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable),
     .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
     .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any),
     .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any),
@@ -72312,14 +74167,27 @@ module lsu(
     .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk),
     .io_free_clk(bus_intf_io_free_clk),
     .io_lsu_busm_clk(bus_intf_io_lsu_busm_clk),
+    .io_axi_aw_ready(bus_intf_io_axi_aw_ready),
     .io_axi_aw_valid(bus_intf_io_axi_aw_valid),
+    .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr),
     .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size),
+    .io_axi_w_ready(bus_intf_io_axi_w_ready),
     .io_axi_w_valid(bus_intf_io_axi_w_valid),
+    .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data),
     .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb),
+    .io_axi_b_valid(bus_intf_io_axi_b_valid),
+    .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp),
+    .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id),
+    .io_axi_ar_ready(bus_intf_io_axi_ar_ready),
     .io_axi_ar_valid(bus_intf_io_axi_ar_valid),
+    .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr),
     .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size),
+    .io_axi_r_valid(bus_intf_io_axi_r_valid),
+    .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id),
+    .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data),
+    .io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp),
     .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d),
     .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m),
     .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid),
@@ -72372,6 +74240,7 @@ module lsu(
   assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 196:14]
   assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 196:14]
   assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 196:14]
+  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 286:26]
@@ -72397,11 +74266,14 @@ module lsu(
   assign io_lsu_tlu_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 105:39]
   assign io_lsu_tlu_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 106:39]
   assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49]
+  assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49]
   assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49]
   assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49]
   assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49]
+  assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49]
   assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49]
   assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49]
+  assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49]
   assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49]
   assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49]
   assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19]
@@ -72638,7 +74510,6 @@ module lsu(
   assign bus_intf_reset = reset;
   assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49]
   assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26]
-  assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26]
   assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26]
   assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49]
   assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49]
@@ -72649,6 +74520,16 @@ module lsu(
   assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 293:49]
   assign bus_intf_io_free_clk = io_free_clk; // @[lsu.scala 294:49]
   assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[lsu.scala 295:49]
+  assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 314:49]
+  assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 314:49]
   assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 296:49]
   assign bus_intf_io_lsu_busreq_m = _T_39 & _T_40; // @[lsu.scala 297:49]
   assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 305:49]
@@ -76412,8 +78293,21 @@ module dma_ctrl(
   input  [2:0]  io_iccm_dma_rtag,
   input  [63:0] io_iccm_dma_rdata,
   input         io_iccm_ready,
+  output        io_dma_axi_aw_ready,
+  input         io_dma_axi_aw_valid,
+  input  [31:0] io_dma_axi_aw_bits_addr,
+  input  [2:0]  io_dma_axi_aw_bits_size,
+  output        io_dma_axi_w_ready,
+  input         io_dma_axi_w_valid,
+  input  [63:0] io_dma_axi_w_bits_data,
+  input  [7:0]  io_dma_axi_w_bits_strb,
   output        io_dma_axi_b_valid,
+  output        io_dma_axi_ar_ready,
+  input         io_dma_axi_ar_valid,
+  input  [31:0] io_dma_axi_ar_bits_addr,
+  input  [2:0]  io_dma_axi_ar_bits_size,
   output        io_dma_axi_r_valid,
+  output [63:0] io_dma_axi_r_bits_data,
   output [1:0]  io_dma_axi_r_bits_resp,
   output        io_lsu_dma_dma_lsc_ctl_dma_dccm_req,
   output [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr,
@@ -76486,18 +78380,29 @@ module dma_ctrl(
   reg [31:0] _RAND_46;
   reg [31:0] _RAND_47;
   reg [31:0] _RAND_48;
-  reg [31:0] _RAND_49;
+  reg [63:0] _RAND_49;
   reg [31:0] _RAND_50;
   reg [31:0] _RAND_51;
   reg [31:0] _RAND_52;
   reg [31:0] _RAND_53;
-  reg [63:0] _RAND_54;
-  reg [63:0] _RAND_55;
-  reg [63:0] _RAND_56;
-  reg [63:0] _RAND_57;
-  reg [63:0] _RAND_58;
+  reg [31:0] _RAND_54;
+  reg [31:0] _RAND_55;
+  reg [31:0] _RAND_56;
+  reg [31:0] _RAND_57;
+  reg [31:0] _RAND_58;
   reg [31:0] _RAND_59;
   reg [31:0] _RAND_60;
+  reg [31:0] _RAND_61;
+  reg [31:0] _RAND_62;
+  reg [31:0] _RAND_63;
+  reg [31:0] _RAND_64;
+  reg [63:0] _RAND_65;
+  reg [63:0] _RAND_66;
+  reg [63:0] _RAND_67;
+  reg [63:0] _RAND_68;
+  reg [63:0] _RAND_69;
+  reg [31:0] _RAND_70;
+  reg [31:0] _RAND_71;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
@@ -76578,29 +78483,53 @@ module dma_ctrl(
   wire  dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39]
   wire  dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39]
   wire  dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28]
+  reg  wrbuf_vld; // @[dma_ctrl.scala 415:59]
+  reg  wrbuf_data_vld; // @[dma_ctrl.scala 417:59]
+  wire  _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43]
+  reg  rdbuf_vld; // @[dma_ctrl.scala 441:47]
+  wire  _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60]
+  reg  axi_mstr_priority; // @[Reg.scala 27:20]
+  wire  axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31]
+  reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
+  reg [31:0] rdbuf_addr; // @[lib.scala 374:16]
+  wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43]
   wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91]
   wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91]
   wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83]
-  wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : 19'h0; // @[dma_ctrl.scala 195:34]
+  reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
+  wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 195:34]
   wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
-  wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : 3'h0; // @[dma_ctrl.scala 197:33]
-  wire  fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 199:33]
+  reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
+  reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
+  wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45]
+  wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33]
+  wire  fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33]
+  wire  bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69]
+  reg  fifo_full; // @[dma_ctrl.scala 373:12]
   reg  dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12]
+  wire  _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39]
+  wire  dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27]
+  wire  axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54]
+  wire  _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80]
   wire  _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136]
+  wire  _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101]
   reg [2:0] WrPtr; // @[Reg.scala 27:20]
   wire  _T_33 = 3'h0 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_34 = _T_31 & _T_33; // @[dma_ctrl.scala 206:181]
+  wire  _T_34 = _T_32 & _T_33; // @[dma_ctrl.scala 206:181]
   wire  _T_41 = 3'h1 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_42 = _T_31 & _T_41; // @[dma_ctrl.scala 206:181]
+  wire  _T_42 = _T_32 & _T_41; // @[dma_ctrl.scala 206:181]
   wire  _T_49 = 3'h2 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_50 = _T_31 & _T_49; // @[dma_ctrl.scala 206:181]
+  wire  _T_50 = _T_32 & _T_49; // @[dma_ctrl.scala 206:181]
   wire  _T_57 = 3'h3 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_58 = _T_31 & _T_57; // @[dma_ctrl.scala 206:181]
+  wire  _T_58 = _T_32 & _T_57; // @[dma_ctrl.scala 206:181]
   wire  _T_65 = 3'h4 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_66 = _T_31 & _T_65; // @[dma_ctrl.scala 206:181]
+  wire  _T_66 = _T_32 & _T_65; // @[dma_ctrl.scala 206:181]
   wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58]
+  wire  _T_71 = axi_mstr_prty_en & fifo_write_in; // @[dma_ctrl.scala 208:73]
+  wire  _T_72 = _T_71 & io_dma_bus_clk_en; // @[dma_ctrl.scala 208:89]
   wire  _T_75 = _T_31 & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 208:181]
-  wire  _T_78 = _T_75 & _T_33; // @[dma_ctrl.scala 208:217]
+  wire  _T_76 = _T_72 | _T_75; // @[dma_ctrl.scala 208:110]
+  wire  _T_78 = _T_76 & _T_33; // @[dma_ctrl.scala 208:217]
   reg  _T_598; // @[dma_ctrl.scala 226:82]
   reg  _T_591; // @[dma_ctrl.scala 226:82]
   reg  _T_584; // @[dma_ctrl.scala 226:82]
@@ -76719,7 +78648,7 @@ module dma_ctrl(
   wire  _T_86 = 3'h0 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_87 = io_iccm_dma_rvalid & _T_86; // @[dma_ctrl.scala 208:416]
   wire  _T_88 = _T_85 | _T_87; // @[dma_ctrl.scala 208:394]
-  wire  _T_96 = _T_75 & _T_41; // @[dma_ctrl.scala 208:217]
+  wire  _T_96 = _T_76 & _T_41; // @[dma_ctrl.scala 208:217]
   wire  _T_98 = 3'h1 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_99 = _T_79 & _T_98; // @[dma_ctrl.scala 208:281]
   wire  _T_100 = _T_96 | _T_99; // @[dma_ctrl.scala 208:236]
@@ -76729,7 +78658,7 @@ module dma_ctrl(
   wire  _T_104 = 3'h1 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_105 = io_iccm_dma_rvalid & _T_104; // @[dma_ctrl.scala 208:416]
   wire  _T_106 = _T_103 | _T_105; // @[dma_ctrl.scala 208:394]
-  wire  _T_114 = _T_75 & _T_49; // @[dma_ctrl.scala 208:217]
+  wire  _T_114 = _T_76 & _T_49; // @[dma_ctrl.scala 208:217]
   wire  _T_116 = 3'h2 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_117 = _T_79 & _T_116; // @[dma_ctrl.scala 208:281]
   wire  _T_118 = _T_114 | _T_117; // @[dma_ctrl.scala 208:236]
@@ -76739,7 +78668,7 @@ module dma_ctrl(
   wire  _T_122 = 3'h2 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_123 = io_iccm_dma_rvalid & _T_122; // @[dma_ctrl.scala 208:416]
   wire  _T_124 = _T_121 | _T_123; // @[dma_ctrl.scala 208:394]
-  wire  _T_132 = _T_75 & _T_57; // @[dma_ctrl.scala 208:217]
+  wire  _T_132 = _T_76 & _T_57; // @[dma_ctrl.scala 208:217]
   wire  _T_134 = 3'h3 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_135 = _T_79 & _T_134; // @[dma_ctrl.scala 208:281]
   wire  _T_136 = _T_132 | _T_135; // @[dma_ctrl.scala 208:236]
@@ -76749,7 +78678,7 @@ module dma_ctrl(
   wire  _T_140 = 3'h3 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_141 = io_iccm_dma_rvalid & _T_140; // @[dma_ctrl.scala 208:416]
   wire  _T_142 = _T_139 | _T_141; // @[dma_ctrl.scala 208:394]
-  wire  _T_150 = _T_75 & _T_65; // @[dma_ctrl.scala 208:217]
+  wire  _T_150 = _T_76 & _T_65; // @[dma_ctrl.scala 208:217]
   wire  _T_152 = 3'h4 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_153 = _T_79 & _T_152; // @[dma_ctrl.scala 208:281]
   wire  _T_154 = _T_150 | _T_153; // @[dma_ctrl.scala 208:236]
@@ -76870,22 +78799,26 @@ module dma_ctrl(
   wire  _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75]
   wire  _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91]
   wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
+  wire  bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:83]
+  wire  _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99]
+  wire  _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120]
   reg [2:0] RspPtr; // @[Reg.scala 27:20]
   wire  _T_408 = 3'h0 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_409 = io_dma_dbg_cmd_done & _T_408; // @[dma_ctrl.scala 220:143]
+  wire  _T_409 = _T_407 & _T_408; // @[dma_ctrl.scala 220:143]
   wire  _T_413 = 3'h1 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_414 = io_dma_dbg_cmd_done & _T_413; // @[dma_ctrl.scala 220:143]
+  wire  _T_414 = _T_407 & _T_413; // @[dma_ctrl.scala 220:143]
   wire  _T_418 = 3'h2 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_419 = io_dma_dbg_cmd_done & _T_418; // @[dma_ctrl.scala 220:143]
+  wire  _T_419 = _T_407 & _T_418; // @[dma_ctrl.scala 220:143]
   wire  _T_423 = 3'h3 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_424 = io_dma_dbg_cmd_done & _T_423; // @[dma_ctrl.scala 220:143]
+  wire  _T_424 = _T_407 & _T_423; // @[dma_ctrl.scala 220:143]
   wire  _T_428 = 3'h4 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_429 = io_dma_dbg_cmd_done & _T_428; // @[dma_ctrl.scala 220:143]
+  wire  _T_429 = _T_407 & _T_428; // @[dma_ctrl.scala 220:143]
   wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58]
   wire  _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77]
   wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58]
   wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58]
-  wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : 64'h0; // @[dma_ctrl.scala 224:347]
+  reg [63:0] wrbuf_data; // @[lib.scala 374:16]
+  wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347]
   wire  _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77]
   wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58]
   wire  _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77]
@@ -76956,6 +78889,20 @@ module dma_ctrl(
   wire [2:0] _T_944 = RspPtr + 3'h1; // @[dma_ctrl.scala 264:78]
   wire  WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30]
   wire  RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93]
+  wire  RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39]
+  wire [3:0] _T_959 = {3'h0,axi_mstr_prty_en}; // @[Cat.scala 29:58]
+  wire [3:0] _T_961 = {3'h0,bus_rsp_sent}; // @[Cat.scala 29:58]
+  wire [3:0] num_fifo_vld_tmp = _T_959 - _T_961; // @[dma_ctrl.scala 291:62]
+  wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_980 = _T_966 + _T_969; // @[dma_ctrl.scala 293:102]
+  wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102]
+  wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102]
+  wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102]
+  wire [3:0] num_fifo_vld = num_fifo_vld_tmp + num_fifo_vld_tmp2; // @[dma_ctrl.scala 295:45]
   wire  _T_1143 = |fifo_valid; // @[dma_ctrl.scala 338:30]
   wire  fifo_empty = ~_T_1143; // @[dma_ctrl.scala 338:17]
   wire [4:0] _T_1106 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 324:39]
@@ -76998,11 +78945,37 @@ module dma_ctrl(
   wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40]
   wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40]
   reg  dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12]
-  wire  bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60]
-  wire  _T_1215 = bus_rsp_valid | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
+  wire  _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44]
+  wire  _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65]
+  wire  _T_1214 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 387:44]
+  wire  _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
   wire  _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94]
   wire  _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116]
   wire  _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137]
+  wire  wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47]
+  wire  wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46]
+  wire  wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40]
+  wire  _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51]
+  wire  wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49]
+  wire  _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51]
+  wire  wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49]
+  wire  _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63]
+  wire  _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92]
+  wire  _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63]
+  wire  _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102]
+  wire  rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59]
+  wire  _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44]
+  wire  rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42]
+  wire  _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63]
+  wire  rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61]
+  wire  _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51]
+  wire  _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80]
+  wire  _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44]
+  wire  _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42]
+  wire  _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47]
+  wire  _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44]
+  wire  _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42]
+  wire  axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27]
   wire  _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50]
   wire  _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48]
   wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83]
@@ -77118,8 +79091,12 @@ module dma_ctrl(
   assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42]
   assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41]
   assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41]
+  assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27]
+  assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27]
   assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27]
+  assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27]
   assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27]
+  assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43]
   assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41]
   assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40]
   assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40]
@@ -77167,7 +79144,7 @@ module dma_ctrl(
   assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 371:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33]
-  assign dma_buffer_c1cgc_io_en = io_dbg_dma_dbg_ib_dbg_cmd_valid | io_clk_override; // @[dma_ctrl.scala 390:33]
+  assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33]
   assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33]
   assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29]
   assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29]
@@ -77176,13 +79153,13 @@ module dma_ctrl(
   assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28]
   assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 371:17]
+  assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 371:17]
+  assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_12_io_en = 1'h0; // @[lib.scala 371:17]
+  assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
   assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -77232,115 +79209,137 @@ initial begin
   _RAND_5 = {1{`RANDOM}};
   fifo_addr_0 = _RAND_5[31:0];
   _RAND_6 = {1{`RANDOM}};
-  dbg_dma_bubble_bus = _RAND_6[0:0];
+  wrbuf_vld = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  WrPtr = _RAND_7[2:0];
+  wrbuf_data_vld = _RAND_7[0:0];
   _RAND_8 = {1{`RANDOM}};
-  _T_598 = _RAND_8[0:0];
+  rdbuf_vld = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  _T_591 = _RAND_9[0:0];
+  axi_mstr_priority = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  _T_584 = _RAND_10[0:0];
+  wrbuf_addr = _RAND_10[31:0];
   _RAND_11 = {1{`RANDOM}};
-  _T_577 = _RAND_11[0:0];
+  rdbuf_addr = _RAND_11[31:0];
   _RAND_12 = {1{`RANDOM}};
-  _T_570 = _RAND_12[0:0];
+  wrbuf_byteen = _RAND_12[7:0];
   _RAND_13 = {1{`RANDOM}};
-  _T_760 = _RAND_13[0:0];
+  wrbuf_sz = _RAND_13[2:0];
   _RAND_14 = {1{`RANDOM}};
-  _T_753 = _RAND_14[0:0];
+  rdbuf_sz = _RAND_14[2:0];
   _RAND_15 = {1{`RANDOM}};
-  _T_746 = _RAND_15[0:0];
+  fifo_full = _RAND_15[0:0];
   _RAND_16 = {1{`RANDOM}};
-  _T_739 = _RAND_16[0:0];
+  dbg_dma_bubble_bus = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  _T_732 = _RAND_17[0:0];
+  WrPtr = _RAND_17[2:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_886 = _RAND_18[0:0];
+  _T_598 = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  _T_884 = _RAND_19[0:0];
+  _T_591 = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  _T_882 = _RAND_20[0:0];
+  _T_584 = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  _T_880 = _RAND_21[0:0];
+  _T_577 = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
-  _T_878 = _RAND_22[0:0];
+  _T_570 = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  fifo_sz_4 = _RAND_23[2:0];
+  _T_760 = _RAND_23[0:0];
   _RAND_24 = {1{`RANDOM}};
-  fifo_sz_3 = _RAND_24[2:0];
+  _T_753 = _RAND_24[0:0];
   _RAND_25 = {1{`RANDOM}};
-  fifo_sz_2 = _RAND_25[2:0];
+  _T_746 = _RAND_25[0:0];
   _RAND_26 = {1{`RANDOM}};
-  fifo_sz_1 = _RAND_26[2:0];
+  _T_739 = _RAND_26[0:0];
   _RAND_27 = {1{`RANDOM}};
-  fifo_sz_0 = _RAND_27[2:0];
+  _T_732 = _RAND_27[0:0];
   _RAND_28 = {1{`RANDOM}};
-  fifo_byteen_4 = _RAND_28[7:0];
+  _T_886 = _RAND_28[0:0];
   _RAND_29 = {1{`RANDOM}};
-  fifo_byteen_3 = _RAND_29[7:0];
+  _T_884 = _RAND_29[0:0];
   _RAND_30 = {1{`RANDOM}};
-  fifo_byteen_2 = _RAND_30[7:0];
+  _T_882 = _RAND_30[0:0];
   _RAND_31 = {1{`RANDOM}};
-  fifo_byteen_1 = _RAND_31[7:0];
+  _T_880 = _RAND_31[0:0];
   _RAND_32 = {1{`RANDOM}};
-  fifo_byteen_0 = _RAND_32[7:0];
+  _T_878 = _RAND_32[0:0];
   _RAND_33 = {1{`RANDOM}};
-  fifo_error_0 = _RAND_33[1:0];
+  fifo_sz_4 = _RAND_33[2:0];
   _RAND_34 = {1{`RANDOM}};
-  fifo_error_1 = _RAND_34[1:0];
+  fifo_sz_3 = _RAND_34[2:0];
   _RAND_35 = {1{`RANDOM}};
-  fifo_error_2 = _RAND_35[1:0];
+  fifo_sz_2 = _RAND_35[2:0];
   _RAND_36 = {1{`RANDOM}};
-  fifo_error_3 = _RAND_36[1:0];
+  fifo_sz_1 = _RAND_36[2:0];
   _RAND_37 = {1{`RANDOM}};
-  fifo_error_4 = _RAND_37[1:0];
+  fifo_sz_0 = _RAND_37[2:0];
   _RAND_38 = {1{`RANDOM}};
-  RspPtr = _RAND_38[2:0];
+  fifo_byteen_4 = _RAND_38[7:0];
   _RAND_39 = {1{`RANDOM}};
-  _T_721 = _RAND_39[0:0];
+  fifo_byteen_3 = _RAND_39[7:0];
   _RAND_40 = {1{`RANDOM}};
-  _T_714 = _RAND_40[0:0];
+  fifo_byteen_2 = _RAND_40[7:0];
   _RAND_41 = {1{`RANDOM}};
-  _T_707 = _RAND_41[0:0];
+  fifo_byteen_1 = _RAND_41[7:0];
   _RAND_42 = {1{`RANDOM}};
-  _T_700 = _RAND_42[0:0];
+  fifo_byteen_0 = _RAND_42[7:0];
   _RAND_43 = {1{`RANDOM}};
-  _T_693 = _RAND_43[0:0];
+  fifo_error_0 = _RAND_43[1:0];
   _RAND_44 = {1{`RANDOM}};
-  _T_799 = _RAND_44[0:0];
+  fifo_error_1 = _RAND_44[1:0];
   _RAND_45 = {1{`RANDOM}};
-  _T_792 = _RAND_45[0:0];
+  fifo_error_2 = _RAND_45[1:0];
   _RAND_46 = {1{`RANDOM}};
-  _T_785 = _RAND_46[0:0];
+  fifo_error_3 = _RAND_46[1:0];
   _RAND_47 = {1{`RANDOM}};
-  _T_778 = _RAND_47[0:0];
+  fifo_error_4 = _RAND_47[1:0];
   _RAND_48 = {1{`RANDOM}};
-  _T_771 = _RAND_48[0:0];
-  _RAND_49 = {1{`RANDOM}};
-  _T_850 = _RAND_49[0:0];
+  RspPtr = _RAND_48[2:0];
+  _RAND_49 = {2{`RANDOM}};
+  wrbuf_data = _RAND_49[63:0];
   _RAND_50 = {1{`RANDOM}};
-  _T_852 = _RAND_50[0:0];
+  _T_721 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  _T_854 = _RAND_51[0:0];
+  _T_714 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  _T_856 = _RAND_52[0:0];
+  _T_707 = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  _T_858 = _RAND_53[0:0];
-  _RAND_54 = {2{`RANDOM}};
-  fifo_data_0 = _RAND_54[63:0];
-  _RAND_55 = {2{`RANDOM}};
-  fifo_data_1 = _RAND_55[63:0];
-  _RAND_56 = {2{`RANDOM}};
-  fifo_data_2 = _RAND_56[63:0];
-  _RAND_57 = {2{`RANDOM}};
-  fifo_data_3 = _RAND_57[63:0];
-  _RAND_58 = {2{`RANDOM}};
-  fifo_data_4 = _RAND_58[63:0];
+  _T_700 = _RAND_53[0:0];
+  _RAND_54 = {1{`RANDOM}};
+  _T_693 = _RAND_54[0:0];
+  _RAND_55 = {1{`RANDOM}};
+  _T_799 = _RAND_55[0:0];
+  _RAND_56 = {1{`RANDOM}};
+  _T_792 = _RAND_56[0:0];
+  _RAND_57 = {1{`RANDOM}};
+  _T_785 = _RAND_57[0:0];
+  _RAND_58 = {1{`RANDOM}};
+  _T_778 = _RAND_58[0:0];
   _RAND_59 = {1{`RANDOM}};
-  dma_nack_count = _RAND_59[2:0];
+  _T_771 = _RAND_59[0:0];
   _RAND_60 = {1{`RANDOM}};
-  dma_dbg_cmd_done_q = _RAND_60[0:0];
+  _T_850 = _RAND_60[0:0];
+  _RAND_61 = {1{`RANDOM}};
+  _T_852 = _RAND_61[0:0];
+  _RAND_62 = {1{`RANDOM}};
+  _T_854 = _RAND_62[0:0];
+  _RAND_63 = {1{`RANDOM}};
+  _T_856 = _RAND_63[0:0];
+  _RAND_64 = {1{`RANDOM}};
+  _T_858 = _RAND_64[0:0];
+  _RAND_65 = {2{`RANDOM}};
+  fifo_data_0 = _RAND_65[63:0];
+  _RAND_66 = {2{`RANDOM}};
+  fifo_data_1 = _RAND_66[63:0];
+  _RAND_67 = {2{`RANDOM}};
+  fifo_data_2 = _RAND_67[63:0];
+  _RAND_68 = {2{`RANDOM}};
+  fifo_data_3 = _RAND_68[63:0];
+  _RAND_69 = {2{`RANDOM}};
+  fifo_data_4 = _RAND_69[63:0];
+  _RAND_70 = {1{`RANDOM}};
+  dma_nack_count = _RAND_70[2:0];
+  _RAND_71 = {1{`RANDOM}};
+  dma_dbg_cmd_done_q = _RAND_71[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     RdPtr = 3'h0;
@@ -77360,6 +79359,36 @@ initial begin
   if (reset) begin
     fifo_addr_0 = 32'h0;
   end
+  if (reset) begin
+    wrbuf_vld = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_data_vld = 1'h0;
+  end
+  if (reset) begin
+    rdbuf_vld = 1'h0;
+  end
+  if (reset) begin
+    axi_mstr_priority = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    rdbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    wrbuf_byteen = 8'h0;
+  end
+  if (reset) begin
+    wrbuf_sz = 3'h0;
+  end
+  if (reset) begin
+    rdbuf_sz = 3'h0;
+  end
+  if (reset) begin
+    fifo_full = 1'h0;
+  end
   if (reset) begin
     dbg_dma_bubble_bus = 1'h0;
   end
@@ -77459,6 +79488,9 @@ initial begin
   if (reset) begin
     RspPtr = 3'h0;
   end
+  if (reset) begin
+    wrbuf_data = 64'h0;
+  end
   if (reset) begin
     _T_721 = 1'h0;
   end
@@ -77547,8 +79579,10 @@ end // initial
       fifo_addr_4 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_4 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_4 <= wrbuf_addr;
     end else begin
-      fifo_addr_4 <= 32'h0;
+      fifo_addr_4 <= rdbuf_addr;
     end
   end
   always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
@@ -77556,8 +79590,10 @@ end // initial
       fifo_addr_3 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_3 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_3 <= wrbuf_addr;
     end else begin
-      fifo_addr_3 <= 32'h0;
+      fifo_addr_3 <= rdbuf_addr;
     end
   end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
@@ -77565,8 +79601,10 @@ end // initial
       fifo_addr_2 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_2 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_2 <= wrbuf_addr;
     end else begin
-      fifo_addr_2 <= 32'h0;
+      fifo_addr_2 <= rdbuf_addr;
     end
   end
   always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
@@ -77574,8 +79612,10 @@ end // initial
       fifo_addr_1 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_1 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_1 <= wrbuf_addr;
     end else begin
-      fifo_addr_1 <= 32'h0;
+      fifo_addr_1 <= rdbuf_addr;
     end
   end
   always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
@@ -77584,7 +79624,77 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_0 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
     end else begin
-      fifo_addr_0 <= 32'h0;
+      fifo_addr_0 <= bus_cmd_addr;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_vld <= 1'h0;
+    end else begin
+      wrbuf_vld <= _T_1224 & _T_1225;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data_vld <= 1'h0;
+    end else begin
+      wrbuf_data_vld <= _T_1228 & _T_1229;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_vld <= 1'h0;
+    end else begin
+      rdbuf_vld <= _T_1237 & _T_1238;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      axi_mstr_priority <= 1'h0;
+    end else if (axi_mstr_prty_en) begin
+      axi_mstr_priority <= axi_mstr_prty_in;
+    end
+  end
+  always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_addr <= 32'h0;
+    end else begin
+      wrbuf_addr <= io_dma_axi_aw_bits_addr;
+    end
+  end
+  always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_addr <= 32'h0;
+    end else begin
+      rdbuf_addr <= io_dma_axi_ar_bits_addr;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_byteen <= 8'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_byteen <= io_dma_axi_w_bits_strb;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_sz <= 3'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_sz <= io_dma_axi_aw_bits_size;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_sz <= 3'h0;
+    end else if (rdbuf_en) begin
+      rdbuf_sz <= io_dma_axi_ar_bits_size;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      fifo_full <= 1'h0;
+    end else begin
+      fifo_full <= num_fifo_vld >= 4'h5;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
@@ -77716,8 +79826,10 @@ end // initial
     end else if (fifo_cmd_en[4]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_4 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_4 <= wrbuf_sz;
       end else begin
-        fifo_sz_4 <= 3'h0;
+        fifo_sz_4 <= rdbuf_sz;
       end
     end
   end
@@ -77727,8 +79839,10 @@ end // initial
     end else if (fifo_cmd_en[3]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_3 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_3 <= wrbuf_sz;
       end else begin
-        fifo_sz_3 <= 3'h0;
+        fifo_sz_3 <= rdbuf_sz;
       end
     end
   end
@@ -77738,8 +79852,10 @@ end // initial
     end else if (fifo_cmd_en[2]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_2 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_2 <= wrbuf_sz;
       end else begin
-        fifo_sz_2 <= 3'h0;
+        fifo_sz_2 <= rdbuf_sz;
       end
     end
   end
@@ -77749,8 +79865,10 @@ end // initial
     end else if (fifo_cmd_en[1]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_1 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_1 <= wrbuf_sz;
       end else begin
-        fifo_sz_1 <= 3'h0;
+        fifo_sz_1 <= rdbuf_sz;
       end
     end
   end
@@ -77834,7 +79952,7 @@ end // initial
   always @(posedge dma_free_clk or posedge reset) begin
     if (reset) begin
       RspPtr <= 3'h0;
-    end else if (io_dma_dbg_cmd_done) begin
+    end else if (RspPtrEn) begin
       if (_T_941) begin
         RspPtr <= 3'h0;
       end else begin
@@ -77842,6 +79960,13 @@ end // initial
       end
     end
   end
+  always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data <= 64'h0;
+    end else begin
+      wrbuf_data <= io_dma_axi_w_bits_data;
+    end
+  end
   always @(posedge dma_free_clk or posedge reset) begin
     if (reset) begin
       _T_721 <= 1'h0;
@@ -77916,28 +80041,52 @@ end // initial
     if (reset) begin
       _T_850 <= 1'h0;
     end else if (fifo_cmd_en[0]) begin
-      _T_850 <= fifo_write_in;
+      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
+        _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
+      end else if (_T_1261) begin
+        _T_850 <= axi_mstr_priority;
+      end else begin
+        _T_850 <= _T_1260;
+      end
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_852 <= 1'h0;
     end else if (fifo_cmd_en[1]) begin
-      _T_852 <= fifo_write_in;
+      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
+        _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
+      end else if (_T_1261) begin
+        _T_852 <= axi_mstr_priority;
+      end else begin
+        _T_852 <= _T_1260;
+      end
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_854 <= 1'h0;
     end else if (fifo_cmd_en[2]) begin
-      _T_854 <= fifo_write_in;
+      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
+        _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
+      end else if (_T_1261) begin
+        _T_854 <= axi_mstr_priority;
+      end else begin
+        _T_854 <= _T_1260;
+      end
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_856 <= 1'h0;
     end else if (fifo_cmd_en[3]) begin
-      _T_856 <= fifo_write_in;
+      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
+        _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
+      end else if (_T_1261) begin
+        _T_856 <= axi_mstr_priority;
+      end else begin
+        _T_856 <= _T_1260;
+      end
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
@@ -77959,7 +80108,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_0 <= _T_498;
     end else begin
-      fifo_data_0 <= 64'h0;
+      fifo_data_0 <= wrbuf_data;
     end
   end
   always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
@@ -77974,7 +80123,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_1 <= _T_498;
     end else begin
-      fifo_data_1 <= 64'h0;
+      fifo_data_1 <= wrbuf_data;
     end
   end
   always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
@@ -77989,7 +80138,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_2 <= _T_498;
     end else begin
-      fifo_data_2 <= 64'h0;
+      fifo_data_2 <= wrbuf_data;
     end
   end
   always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@@ -78004,7 +80153,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_3 <= _T_498;
     end else begin
-      fifo_data_3 <= 64'h0;
+      fifo_data_3 <= wrbuf_data;
     end
   end
   always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
@@ -78049,19 +80198,34 @@ module axi4_to_ahb(
   input         io_clk_override,
   output        io_axi_aw_ready,
   input         io_axi_aw_valid,
+  input         io_axi_aw_bits_id,
   input  [31:0] io_axi_aw_bits_addr,
   input  [2:0]  io_axi_aw_bits_size,
   output        io_axi_w_ready,
   input         io_axi_w_valid,
+  input  [63:0] io_axi_w_bits_data,
   input  [7:0]  io_axi_w_bits_strb,
   input         io_axi_b_ready,
+  output        io_axi_b_valid,
+  output [1:0]  io_axi_b_bits_resp,
+  output        io_axi_b_bits_id,
+  output        io_axi_ar_ready,
   input         io_axi_ar_valid,
+  input         io_axi_ar_bits_id,
   input  [31:0] io_axi_ar_bits_addr,
   input  [2:0]  io_axi_ar_bits_size,
+  output        io_axi_r_valid,
+  output        io_axi_r_bits_id,
+  output [63:0] io_axi_r_bits_data,
+  output [1:0]  io_axi_r_bits_resp,
+  input  [63:0] io_ahb_in_hrdata,
   input         io_ahb_in_hready,
   input         io_ahb_in_hresp,
+  output [31:0] io_ahb_out_haddr,
+  output [2:0]  io_ahb_out_hsize,
   output [1:0]  io_ahb_out_htrans,
-  output        io_ahb_out_hwrite
+  output        io_ahb_out_hwrite,
+  output [63:0] io_ahb_out_hwdata
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -78076,10 +80240,20 @@ module axi4_to_ahb(
   reg [31:0] _RAND_9;
   reg [31:0] _RAND_10;
   reg [31:0] _RAND_11;
-  reg [31:0] _RAND_12;
+  reg [63:0] _RAND_12;
   reg [31:0] _RAND_13;
   reg [31:0] _RAND_14;
   reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [63:0] _RAND_17;
+  reg [63:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
+  reg [31:0] _RAND_21;
+  reg [31:0] _RAND_22;
+  reg [31:0] _RAND_23;
+  reg [31:0] _RAND_24;
+  reg [31:0] _RAND_25;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -78212,11 +80386,13 @@ module axi4_to_ahb(
   wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67]
   wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58]
+  reg  wrbuf_tag; // @[Reg.scala 27:20]
   reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
   wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 150:21]
   reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
   wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 151:21]
   reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
+  reg [63:0] wrbuf_data; // @[lib.scala 374:16]
   wire  _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55]
   wire  _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39]
   wire  _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67]
@@ -78226,12 +80402,37 @@ module axi4_to_ahb(
   wire  _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67]
   wire  _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
   wire  slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
+  wire  _T_25 = slave_valid_pre & io_axi_b_ready; // @[axi4_to_ahb.scala 156:33]
   wire  buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12]
+  reg  slvbuf_write; // @[Reg.scala 27:20]
+  wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23]
+  reg  slvbuf_error; // @[Reg.scala 27:20]
+  wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 292:88]
+  wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58]
+  wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55]
+  reg  slvbuf_tag; // @[Reg.scala 27:20]
+  wire  _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66]
+  reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
+  wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
+  wire  _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91]
+  reg [63:0] buf_data; // @[lib.scala 374:16]
+  wire  ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 33:27 axi4_to_ahb.scala 342:17]
+  reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 332:57]
+  wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 293:79]
   wire  _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57]
   wire  _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94]
   wire  _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76]
   wire  _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54]
   wire  _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38]
+  wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
+  wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16]
+  wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16]
+  wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16]
+  wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16]
+  wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16]
+  wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16]
+  wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 182:30]
   wire  _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51]
   wire  _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 195:33]
   wire  _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 210:64]
@@ -78251,6 +80452,7 @@ module axi4_to_ahb(
   wire  _T_112 = ~master_valid; // @[axi4_to_ahb.scala 191:34]
   wire  _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 191:32]
   reg [31:0] buf_addr; // @[lib.scala 374:16]
+  wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 196:30]
   wire  _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 197:48]
   wire  _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 197:62]
   wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
@@ -78286,6 +80488,7 @@ module axi4_to_ahb(
   wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16]
   wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16]
   wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16]
+  wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 240:30]
   wire  _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 241:65]
   reg  buf_aligned; // @[Reg.scala 27:20]
   wire  _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 241:44]
@@ -78313,6 +80516,9 @@ module axi4_to_ahb(
   wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 257:75]
   wire  _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 260:40]
+  wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 261:30]
+  wire  _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67]
+  wire  _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67]
   wire  _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67]
   wire  _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
   wire  _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
@@ -78323,29 +80529,42 @@ module axi4_to_ahb(
   wire  _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67]
   wire  _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67]
   wire  _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
   wire  _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67]
+  wire  _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
   wire  _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67]
   wire  _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67]
+  wire  _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67]
   wire  _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67]
   wire  _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67]
   wire  _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67]
   wire  _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67]
+  wire  _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
   wire  _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67]
   wire  _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
+  wire  _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67]
   wire  _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67]
   wire  _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
   wire  _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67]
   wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67]
   wire  _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
+  wire  _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
   wire  _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
   wire  buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58]
   wire  buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58]
+  wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58]
   wire  slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
+  wire  slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
   wire  _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 278:24]
   wire  _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 277:48]
   wire  _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 278:54]
@@ -78379,7 +80598,35 @@ module axi4_to_ahb(
   wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 137:15]
   wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 136:96]
   wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 272:43]
+  wire  _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33]
+  wire  _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 276:38]
+  wire  _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 276:71]
+  wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire  _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 129:55]
+  wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 129:16]
+  wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 128:64]
+  wire  _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 130:60]
+  wire  _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 130:89]
+  wire  _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 130:123]
+  wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 130:21]
+  wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 129:93]
+  wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 276:21]
+  wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 276:15]
+  wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 283:81]
+  wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58]
+  wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  reg [1:0] buf_size; // @[Reg.scala 27:20]
+  wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 283:138]
+  wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
   reg  buf_write; // @[Reg.scala 27:20]
+  wire  _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 296:44]
+  wire  _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 296:56]
+  wire  last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 296:75]
   wire  wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49]
   wire  wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52]
   wire  wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49]
@@ -78390,9 +80637,11 @@ module axi4_to_ahb(
   wire  _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22]
   wire  _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38]
   wire  _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21]
+  wire  _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22]
   wire  _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55]
   wire  _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91]
   wire  _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55]
+  reg  buf_tag; // @[Reg.scala 27:20]
   wire  _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 326:92]
   wire  _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43]
   wire  _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58]
@@ -78462,8 +80711,19 @@ module axi4_to_ahb(
   );
   assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19]
   assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18]
+  assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18]
+  assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22]
+  assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20]
+  assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19]
+  assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18]
+  assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20]
+  assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 163:22]
+  assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22]
+  assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 282:20]
+  assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 283:20]
   assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 197:25 axi4_to_ahb.scala 212:25 axi4_to_ahb.scala 222:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25]
   assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 288:21]
+  assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 289:21]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
@@ -78546,21 +80806,41 @@ initial begin
   _RAND_7 = {1{`RANDOM}};
   cmd_doneQ = _RAND_7[0:0];
   _RAND_8 = {1{`RANDOM}};
-  wrbuf_addr = _RAND_8[31:0];
+  wrbuf_tag = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  wrbuf_size = _RAND_9[2:0];
+  wrbuf_addr = _RAND_9[31:0];
   _RAND_10 = {1{`RANDOM}};
-  wrbuf_byteen = _RAND_10[7:0];
+  wrbuf_size = _RAND_10[2:0];
   _RAND_11 = {1{`RANDOM}};
-  buf_addr = _RAND_11[31:0];
-  _RAND_12 = {1{`RANDOM}};
-  buf_cmd_byte_ptrQ = _RAND_12[2:0];
+  wrbuf_byteen = _RAND_11[7:0];
+  _RAND_12 = {2{`RANDOM}};
+  wrbuf_data = _RAND_12[63:0];
   _RAND_13 = {1{`RANDOM}};
-  buf_byteen = _RAND_13[7:0];
+  slvbuf_write = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  buf_aligned = _RAND_14[0:0];
+  slvbuf_error = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  buf_write = _RAND_15[0:0];
+  slvbuf_tag = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  last_bus_addr = _RAND_16[31:0];
+  _RAND_17 = {2{`RANDOM}};
+  buf_data = _RAND_17[63:0];
+  _RAND_18 = {2{`RANDOM}};
+  ahb_hrdata_q = _RAND_18[63:0];
+  _RAND_19 = {1{`RANDOM}};
+  buf_addr = _RAND_19[31:0];
+  _RAND_20 = {1{`RANDOM}};
+  buf_cmd_byte_ptrQ = _RAND_20[2:0];
+  _RAND_21 = {1{`RANDOM}};
+  buf_byteen = _RAND_21[7:0];
+  _RAND_22 = {1{`RANDOM}};
+  buf_aligned = _RAND_22[0:0];
+  _RAND_23 = {1{`RANDOM}};
+  buf_size = _RAND_23[1:0];
+  _RAND_24 = {1{`RANDOM}};
+  buf_write = _RAND_24[0:0];
+  _RAND_25 = {1{`RANDOM}};
+  buf_tag = _RAND_25[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     buf_state = 3'h0;
@@ -78586,6 +80866,9 @@ initial begin
   if (reset) begin
     cmd_doneQ = 1'h0;
   end
+  if (reset) begin
+    wrbuf_tag = 1'h0;
+  end
   if (reset) begin
     wrbuf_addr = 32'h0;
   end
@@ -78595,6 +80878,27 @@ initial begin
   if (reset) begin
     wrbuf_byteen = 8'h0;
   end
+  if (reset) begin
+    wrbuf_data = 64'h0;
+  end
+  if (reset) begin
+    slvbuf_write = 1'h0;
+  end
+  if (reset) begin
+    slvbuf_error = 1'h0;
+  end
+  if (reset) begin
+    slvbuf_tag = 1'h0;
+  end
+  if (reset) begin
+    last_bus_addr = 32'h0;
+  end
+  if (reset) begin
+    buf_data = 64'h0;
+  end
+  if (reset) begin
+    ahb_hrdata_q = 64'h0;
+  end
   if (reset) begin
     buf_addr = 32'h0;
   end
@@ -78607,9 +80911,15 @@ initial begin
   if (reset) begin
     buf_aligned = 1'h0;
   end
+  if (reset) begin
+    buf_size = 2'h0;
+  end
   if (reset) begin
     buf_write = 1'h0;
   end
+  if (reset) begin
+    buf_tag = 1'h0;
+  end
   `endif // RANDOMIZE
 end // initial
 `ifdef FIRRTL_AFTER_INITIAL
@@ -78712,6 +81022,13 @@ end // initial
       cmd_doneQ <= _T_276 & _T_691;
     end
   end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_tag <= 1'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_tag <= io_axi_aw_bits_id;
+    end
+  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       wrbuf_addr <= 32'h0;
@@ -78733,6 +81050,71 @@ end // initial
       wrbuf_byteen <= io_axi_w_bits_strb;
     end
   end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data <= 64'h0;
+    end else begin
+      wrbuf_data <= io_axi_w_bits_data;
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      slvbuf_write <= 1'h0;
+    end else if (slvbuf_wr_en) begin
+      slvbuf_write <= buf_write;
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      slvbuf_error <= 1'h0;
+    end else if (slvbuf_error_en) begin
+      if (_T_49) begin
+        slvbuf_error <= 1'h0;
+      end else if (_T_101) begin
+        slvbuf_error <= 1'h0;
+      end else if (_T_136) begin
+        slvbuf_error <= ahb_hresp_q;
+      end else if (_T_175) begin
+        slvbuf_error <= 1'h0;
+      end else if (_T_186) begin
+        slvbuf_error <= ahb_hresp_q;
+      end else if (_T_188) begin
+        slvbuf_error <= 1'h0;
+      end else begin
+        slvbuf_error <= _GEN_6;
+      end
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      slvbuf_tag <= 1'h0;
+    end else if (slvbuf_wr_en) begin
+      slvbuf_tag <= buf_tag;
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      last_bus_addr <= 32'h0;
+    end else if (last_addr_en) begin
+      last_bus_addr <= io_ahb_out_haddr;
+    end
+  end
+  always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
+    if (reset) begin
+      buf_data <= 64'h0;
+    end else if (_T_489) begin
+      buf_data <= ahb_hrdata_q;
+    end else begin
+      buf_data <= wrbuf_data;
+    end
+  end
+  always @(posedge ahbm_data_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hrdata_q <= 64'h0;
+    end else begin
+      ahb_hrdata_q <= io_ahb_in_hrdata;
+    end
+  end
   always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
     if (reset) begin
       buf_addr <= 32'h0;
@@ -78859,6 +81241,13 @@ end // initial
       buf_aligned <= buf_aligned_in;
     end
   end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_size <= 2'h0;
+    end else if (buf_wr_en) begin
+      buf_size <= buf_size_in[1:0];
+    end
+  end
   always @(posedge buf_clk or posedge reset) begin
     if (reset) begin
       buf_write <= 1'h0;
@@ -78880,22 +81269,45 @@ end // initial
       end
     end
   end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_tag <= 1'h0;
+    end else if (buf_wr_en) begin
+      if (wr_cmd_vld) begin
+        buf_tag <= wrbuf_tag;
+      end else begin
+        buf_tag <= io_axi_ar_bits_id;
+      end
+    end
+  end
 endmodule
 module ahb_to_axi4(
   input         clock,
   input         reset,
   input         io_scan_mode,
   input         io_bus_clk_en,
+  input         io_axi_aw_ready,
   output        io_axi_aw_valid,
+  output [31:0] io_axi_aw_bits_addr,
+  output [2:0]  io_axi_aw_bits_size,
+  output        io_axi_w_valid,
+  output [63:0] io_axi_w_bits_data,
+  output [7:0]  io_axi_w_bits_strb,
+  input         io_axi_ar_ready,
   output        io_axi_ar_valid,
+  output [31:0] io_axi_ar_bits_addr,
+  output [2:0]  io_axi_ar_bits_size,
   input         io_axi_r_valid,
+  input  [63:0] io_axi_r_bits_data,
   input  [1:0]  io_axi_r_bits_resp,
+  output [63:0] io_ahb_sig_in_hrdata,
   output        io_ahb_sig_in_hready,
   output        io_ahb_sig_in_hresp,
   input  [31:0] io_ahb_sig_out_haddr,
   input  [2:0]  io_ahb_sig_out_hsize,
   input  [1:0]  io_ahb_sig_out_htrans,
   input         io_ahb_sig_out_hwrite,
+  input  [63:0] io_ahb_sig_out_hwdata,
   input         io_ahb_hsel,
   input         io_ahb_hreadyin
 );
@@ -78908,8 +81320,13 @@ module ahb_to_axi4(
   reg [31:0] _RAND_5;
   reg [31:0] _RAND_6;
   reg [31:0] _RAND_7;
-  reg [31:0] _RAND_8;
+  reg [63:0] _RAND_8;
   reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [63:0] _RAND_14;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -78952,7 +81369,9 @@ module ahb_to_axi4(
   wire  _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 80:91]
   wire  bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27]
   reg  cmdbuf_vld; // @[ahb_to_axi4.scala 140:61]
-  wire  _T_153 = io_axi_aw_valid | io_axi_ar_valid; // @[ahb_to_axi4.scala 138:86]
+  wire  _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67]
+  wire  _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105]
+  wire  _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86]
   wire  _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48]
   wire  cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46]
   wire  _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24]
@@ -78984,9 +81403,28 @@ module ahb_to_axi4(
   wire  cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
   wire  buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
   reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 125:65]
+  wire  _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 98:60]
+  wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:78]
+  wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 98:70]
   wire  _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 99:30]
+  wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48]
+  wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 99:40]
+  wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 99:40]
+  wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 98:109]
+  wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 98:109]
   wire  _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 100:30]
+  wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 100:48]
+  wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 100:40]
+  wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 100:40]
+  wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 99:79]
+  wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 99:79]
   wire  _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 101:30]
+  wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 100:79]
+  wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 100:79]
   reg  ahb_hready_q; // @[ahb_to_axi4.scala 123:60]
   wire  _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 104:80]
   reg  ahb_hresp_q; // @[ahb_to_axi4.scala 122:60]
@@ -79002,6 +81440,8 @@ module ahb_to_axi4(
   wire  _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 104:181]
   wire  _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 104:179]
   wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire  buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 46:33 ahb_to_axi4.scala 135:31]
+  reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 118:66]
   reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 124:60]
   wire  _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 108:61]
   wire  _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 108:83]
@@ -79033,6 +81473,12 @@ module ahb_to_axi4(
   wire  cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 137:128]
   wire  _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66]
   wire  _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110]
+  reg [2:0] _T_164; // @[Reg.scala 27:20]
+  reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
+  wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 98:31]
+  reg [31:0] cmdbuf_addr; // @[lib.scala 374:16]
+  reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16]
+  wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 146:31]
   rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -79070,7 +81516,15 @@ module ahb_to_axi4(
     .io_scan_mode(rvclkhdr_5_io_scan_mode)
   );
   assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28]
+  assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33]
+  assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33]
+  assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:28]
+  assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33]
+  assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:33]
   assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28]
+  assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33]
+  assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33]
+  assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 107:38]
   assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 104:38]
   assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 108:38]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
@@ -79142,10 +81596,20 @@ initial begin
   ahb_hresp_q = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
   buf_read_error = _RAND_7[0:0];
-  _RAND_8 = {1{`RANDOM}};
-  ahb_htrans_q = _RAND_8[1:0];
+  _RAND_8 = {2{`RANDOM}};
+  buf_rdata = _RAND_8[63:0];
   _RAND_9 = {1{`RANDOM}};
-  ahb_hwrite_q = _RAND_9[0:0];
+  ahb_htrans_q = _RAND_9[1:0];
+  _RAND_10 = {1{`RANDOM}};
+  ahb_hwrite_q = _RAND_10[0:0];
+  _RAND_11 = {1{`RANDOM}};
+  _T_164 = _RAND_11[2:0];
+  _RAND_12 = {1{`RANDOM}};
+  cmdbuf_wstrb = _RAND_12[7:0];
+  _RAND_13 = {1{`RANDOM}};
+  cmdbuf_addr = _RAND_13[31:0];
+  _RAND_14 = {2{`RANDOM}};
+  cmdbuf_wdata = _RAND_14[63:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     ahb_haddr_q = 32'h0;
@@ -79171,12 +81635,27 @@ initial begin
   if (reset) begin
     buf_read_error = 1'h0;
   end
+  if (reset) begin
+    buf_rdata = 64'h0;
+  end
   if (reset) begin
     ahb_htrans_q = 2'h0;
   end
   if (reset) begin
     ahb_hwrite_q = 1'h0;
   end
+  if (reset) begin
+    _T_164 = 3'h0;
+  end
+  if (reset) begin
+    cmdbuf_wstrb = 8'h0;
+  end
+  if (reset) begin
+    cmdbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    cmdbuf_wdata = 64'h0;
+  end
   `endif // RANDOMIZE
 end // initial
 `ifdef FIRRTL_AFTER_INITIAL
@@ -79267,6 +81746,13 @@ end // initial
       buf_read_error <= _GEN_3;
     end
   end
+  always @(posedge buf_rdata_clk or posedge reset) begin
+    if (reset) begin
+      buf_rdata <= 64'h0;
+    end else begin
+      buf_rdata <= io_axi_r_bits_data;
+    end
+  end
   always @(posedge ahb_clk or posedge reset) begin
     if (reset) begin
       ahb_htrans_q <= 2'h0;
@@ -79281,20 +81767,70 @@ end // initial
       ahb_hwrite_q <= io_ahb_sig_out_hwrite;
     end
   end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      _T_164 <= 3'h0;
+    end else if (cmdbuf_wr_en) begin
+      _T_164 <= ahb_hsize_q;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      cmdbuf_wstrb <= 8'h0;
+    end else if (cmdbuf_wr_en) begin
+      cmdbuf_wstrb <= master_wstrb;
+    end
+  end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+    if (reset) begin
+      cmdbuf_addr <= 32'h0;
+    end else begin
+      cmdbuf_addr <= ahb_haddr_q;
+    end
+  end
+  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+    if (reset) begin
+      cmdbuf_wdata <= 64'h0;
+    end else begin
+      cmdbuf_wdata <= io_ahb_sig_out_hwdata;
+    end
+  end
 endmodule
 module quasar(
   input         clock,
   input         reset,
+  input  [63:0] io_lsu_ahb_in_hrdata,
   input         io_lsu_ahb_in_hready,
   input         io_lsu_ahb_in_hresp,
+  output [31:0] io_lsu_ahb_out_haddr,
+  output [2:0]  io_lsu_ahb_out_hsize,
+  output [1:0]  io_lsu_ahb_out_htrans,
+  output        io_lsu_ahb_out_hwrite,
+  output [63:0] io_lsu_ahb_out_hwdata,
+  input  [63:0] io_ifu_ahb_in_hrdata,
   input         io_ifu_ahb_in_hready,
   input         io_ifu_ahb_in_hresp,
+  output [31:0] io_ifu_ahb_out_haddr,
+  output [2:0]  io_ifu_ahb_out_hsize,
+  output [1:0]  io_ifu_ahb_out_htrans,
+  output        io_ifu_ahb_out_hwrite,
+  output [63:0] io_ifu_ahb_out_hwdata,
+  input  [63:0] io_sb_ahb_in_hrdata,
   input         io_sb_ahb_in_hready,
   input         io_sb_ahb_in_hresp,
+  output [31:0] io_sb_ahb_out_haddr,
+  output [2:0]  io_sb_ahb_out_hsize,
+  output [1:0]  io_sb_ahb_out_htrans,
+  output        io_sb_ahb_out_hwrite,
+  output [63:0] io_sb_ahb_out_hwdata,
+  output [63:0] io_dma_ahb_sig_in_hrdata,
+  output        io_dma_ahb_sig_in_hready,
+  output        io_dma_ahb_sig_in_hresp,
   input  [31:0] io_dma_ahb_sig_out_haddr,
   input  [2:0]  io_dma_ahb_sig_out_hsize,
   input  [1:0]  io_dma_ahb_sig_out_htrans,
   input         io_dma_ahb_sig_out_hwrite,
+  input  [63:0] io_dma_ahb_sig_out_hwdata,
   input         io_dma_ahb_hsel,
   input         io_dma_ahb_hreadyin,
   input         io_dbg_rst_l,
@@ -79341,7 +81877,10 @@ module quasar(
   input  [38:0] io_dccm_rd_data_hi,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
+  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
+  output [70:0] io_ic_wr_data_0,
+  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -79419,6 +81958,7 @@ module quasar(
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 72:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 72:19]
   wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 72:19]
@@ -79462,7 +82002,10 @@ module quasar(
   wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 72:19]
   wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 72:19]
   wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 72:19]
+  wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 72:19]
   wire  ifu_io_ic_rd_en; // @[quasar.scala 72:19]
+  wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 72:19]
+  wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 72:19]
   wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 72:19]
   wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 72:19]
   wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 72:19]
@@ -79477,8 +82020,14 @@ module quasar(
   wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 72:19]
   wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 72:19]
   wire  ifu_io_ic_sel_premux_data; // @[quasar.scala 72:19]
+  wire  ifu_io_ifu_ar_ready; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_ar_valid; // @[quasar.scala 72:19]
+  wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 72:19]
   wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 72:19]
+  wire  ifu_io_ifu_r_valid; // @[quasar.scala 72:19]
+  wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 72:19]
+  wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 72:19]
+  wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_bus_clk_en; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 72:19]
   wire  ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 72:19]
@@ -79635,6 +82184,7 @@ module quasar(
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 73:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 73:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 73:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 73:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 73:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 73:19]
   wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 73:19]
@@ -79727,11 +82277,11 @@ module quasar(
   wire  dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 73:19]
   wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 73:19]
   wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 73:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 73:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 73:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 73:19]
@@ -79782,14 +82332,25 @@ module quasar(
   wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 74:19]
   wire  dbg_io_dmi_reg_wr_en; // @[quasar.scala 74:19]
   wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_aw_ready; // @[quasar.scala 74:19]
   wire  dbg_io_sb_axi_aw_valid; // @[quasar.scala 74:19]
   wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 74:19]
   wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_w_ready; // @[quasar.scala 74:19]
   wire  dbg_io_sb_axi_w_valid; // @[quasar.scala 74:19]
+  wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 74:19]
   wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_b_ready; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_b_valid; // @[quasar.scala 74:19]
+  wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_ar_ready; // @[quasar.scala 74:19]
   wire  dbg_io_sb_axi_ar_valid; // @[quasar.scala 74:19]
   wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 74:19]
   wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_r_ready; // @[quasar.scala 74:19]
+  wire  dbg_io_sb_axi_r_valid; // @[quasar.scala 74:19]
+  wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 74:19]
+  wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 74:19]
   wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 74:19]
   wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 74:19]
   wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 74:19]
@@ -79934,11 +82495,11 @@ module quasar(
   wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 76:19]
   wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 76:19]
   wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 76:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 76:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 76:19]
@@ -79963,14 +82524,27 @@ module quasar(
   wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 76:19]
   wire  lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 76:19]
+  wire  lsu_io_axi_aw_ready; // @[quasar.scala 76:19]
   wire  lsu_io_axi_aw_valid; // @[quasar.scala 76:19]
+  wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 76:19]
   wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 76:19]
   wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 76:19]
+  wire  lsu_io_axi_w_ready; // @[quasar.scala 76:19]
   wire  lsu_io_axi_w_valid; // @[quasar.scala 76:19]
+  wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 76:19]
   wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 76:19]
+  wire  lsu_io_axi_b_valid; // @[quasar.scala 76:19]
+  wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 76:19]
+  wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 76:19]
+  wire  lsu_io_axi_ar_ready; // @[quasar.scala 76:19]
   wire  lsu_io_axi_ar_valid; // @[quasar.scala 76:19]
+  wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 76:19]
   wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 76:19]
   wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 76:19]
+  wire  lsu_io_axi_r_valid; // @[quasar.scala 76:19]
+  wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 76:19]
+  wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 76:19]
+  wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 76:19]
   wire  lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 76:19]
   wire  lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 76:19]
   wire  lsu_io_dec_tlu_force_halt; // @[quasar.scala 76:19]
@@ -80078,8 +82652,21 @@ module quasar(
   wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 78:24]
   wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 78:24]
   wire  dma_ctrl_io_iccm_ready; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 78:24]
+  wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 78:24]
+  wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 78:24]
+  wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 78:24]
+  wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 78:24]
   wire  dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 78:24]
+  wire  dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 78:24]
+  wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 78:24]
+  wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 78:24]
   wire  dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 78:24]
+  wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 78:24]
   wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 78:24]
   wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 78:24]
   wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 78:24]
@@ -80116,19 +82703,34 @@ module quasar(
   wire  axi4_to_ahb_io_clk_override; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_aw_bits_id; // @[quasar.scala 242:32]
   wire [31:0] axi4_to_ahb_io_axi_aw_bits_addr; // @[quasar.scala 242:32]
   wire [2:0] axi4_to_ahb_io_axi_aw_bits_size; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 242:32]
+  wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 242:32]
   wire [7:0] axi4_to_ahb_io_axi_w_bits_strb; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_b_ready; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 242:32]
+  wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_b_bits_id; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_ar_bits_id; // @[quasar.scala 242:32]
   wire [31:0] axi4_to_ahb_io_axi_ar_bits_addr; // @[quasar.scala 242:32]
   wire [2:0] axi4_to_ahb_io_axi_ar_bits_size; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 242:32]
+  wire  axi4_to_ahb_io_axi_r_bits_id; // @[quasar.scala 242:32]
+  wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 242:32]
+  wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 242:32]
+  wire [63:0] axi4_to_ahb_io_ahb_in_hrdata; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 242:32]
+  wire [31:0] axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 242:32]
+  wire [2:0] axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 242:32]
   wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 242:32]
+  wire [63:0] axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 242:32]
   wire  axi4_to_ahb_1_clock; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_reset; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 243:33]
@@ -80136,19 +82738,34 @@ module quasar(
   wire  axi4_to_ahb_1_io_clk_override; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 243:33]
   wire [31:0] axi4_to_ahb_1_io_axi_aw_bits_addr; // @[quasar.scala 243:33]
   wire [2:0] axi4_to_ahb_1_io_axi_aw_bits_size; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 243:33]
+  wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 243:33]
   wire [7:0] axi4_to_ahb_1_io_axi_w_bits_strb; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_b_ready; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 243:33]
+  wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 243:33]
   wire [31:0] axi4_to_ahb_1_io_axi_ar_bits_addr; // @[quasar.scala 243:33]
   wire [2:0] axi4_to_ahb_1_io_axi_ar_bits_size; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 243:33]
+  wire  axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 243:33]
+  wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 243:33]
+  wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 243:33]
+  wire [63:0] axi4_to_ahb_1_io_ahb_in_hrdata; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 243:33]
+  wire [31:0] axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 243:33]
+  wire [2:0] axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 243:33]
   wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 243:33]
+  wire [63:0] axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 243:33]
   wire  axi4_to_ahb_2_clock; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_reset; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 244:33]
@@ -80156,33 +82773,60 @@ module quasar(
   wire  axi4_to_ahb_2_io_clk_override; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 244:33]
   wire [31:0] axi4_to_ahb_2_io_axi_aw_bits_addr; // @[quasar.scala 244:33]
   wire [2:0] axi4_to_ahb_2_io_axi_aw_bits_size; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 244:33]
+  wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 244:33]
   wire [7:0] axi4_to_ahb_2_io_axi_w_bits_strb; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_b_ready; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 244:33]
+  wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 244:33]
   wire [31:0] axi4_to_ahb_2_io_axi_ar_bits_addr; // @[quasar.scala 244:33]
   wire [2:0] axi4_to_ahb_2_io_axi_ar_bits_size; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 244:33]
+  wire  axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 244:33]
+  wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 244:33]
+  wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 244:33]
+  wire [63:0] axi4_to_ahb_2_io_ahb_in_hrdata; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 244:33]
+  wire [31:0] axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 244:33]
+  wire [2:0] axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 244:33]
   wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 244:33]
   wire  axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 244:33]
+  wire [63:0] axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 244:33]
   wire  ahb_to_axi4_clock; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_reset; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_scan_mode; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 245:33]
+  wire  ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 245:33]
+  wire [31:0] ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 245:33]
+  wire [2:0] ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 245:33]
+  wire  ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 245:33]
+  wire [63:0] ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 245:33]
+  wire [7:0] ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 245:33]
+  wire  ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 245:33]
+  wire [31:0] ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 245:33]
+  wire [2:0] ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 245:33]
+  wire [63:0] ahb_to_axi4_io_axi_r_bits_data; // @[quasar.scala 245:33]
   wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 245:33]
+  wire [63:0] ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 245:33]
   wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 245:33]
   wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 245:33]
   wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 245:33]
+  wire [63:0] ahb_to_axi4_io_ahb_sig_out_hwdata; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 245:33]
   wire  ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 245:33]
   wire  _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 80:67]
@@ -80231,6 +82875,7 @@ module quasar(
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
+    .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
     .io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -80274,7 +82919,10 @@ module quasar(
     .io_iccm_rd_data_ecc(ifu_io_iccm_rd_data_ecc),
     .io_ic_rw_addr(ifu_io_ic_rw_addr),
     .io_ic_tag_valid(ifu_io_ic_tag_valid),
+    .io_ic_wr_en(ifu_io_ic_wr_en),
     .io_ic_rd_en(ifu_io_ic_rd_en),
+    .io_ic_wr_data_0(ifu_io_ic_wr_data_0),
+    .io_ic_wr_data_1(ifu_io_ic_wr_data_1),
     .io_ic_debug_wr_data(ifu_io_ic_debug_wr_data),
     .io_ic_debug_addr(ifu_io_ic_debug_addr),
     .io_ic_rd_data(ifu_io_ic_rd_data),
@@ -80289,8 +82937,14 @@ module quasar(
     .io_ic_debug_way(ifu_io_ic_debug_way),
     .io_ic_premux_data(ifu_io_ic_premux_data),
     .io_ic_sel_premux_data(ifu_io_ic_sel_premux_data),
+    .io_ifu_ar_ready(ifu_io_ifu_ar_ready),
     .io_ifu_ar_valid(ifu_io_ifu_ar_valid),
+    .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id),
     .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr),
+    .io_ifu_r_valid(ifu_io_ifu_r_valid),
+    .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id),
+    .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data),
+    .io_ifu_r_bits_resp(ifu_io_ifu_r_bits_resp),
     .io_ifu_bus_clk_en(ifu_io_ifu_bus_clk_en),
     .io_ifu_dma_dma_ifc_dma_iccm_stall_any(ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any),
     .io_ifu_dma_dma_mem_ctl_dma_iccm_req(ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req),
@@ -80449,6 +83103,7 @@ module quasar(
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
+    .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
     .io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -80541,11 +83196,11 @@ module quasar(
     .io_dec_exu_ib_exu_dec_debug_wdata_rs1_d(dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d),
     .io_dec_exu_gpr_exu_gpr_i0_rs1_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d),
     .io_dec_exu_gpr_exu_gpr_i0_rs2_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d),
+    .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
     .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable),
-    .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable),
     .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
     .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any),
     .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any),
@@ -80598,14 +83253,25 @@ module quasar(
     .io_dmi_reg_addr(dbg_io_dmi_reg_addr),
     .io_dmi_reg_wr_en(dbg_io_dmi_reg_wr_en),
     .io_dmi_reg_wdata(dbg_io_dmi_reg_wdata),
+    .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready),
     .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid),
     .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr),
     .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size),
+    .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready),
     .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid),
+    .io_sb_axi_w_bits_data(dbg_io_sb_axi_w_bits_data),
     .io_sb_axi_w_bits_strb(dbg_io_sb_axi_w_bits_strb),
+    .io_sb_axi_b_ready(dbg_io_sb_axi_b_ready),
+    .io_sb_axi_b_valid(dbg_io_sb_axi_b_valid),
+    .io_sb_axi_b_bits_resp(dbg_io_sb_axi_b_bits_resp),
+    .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready),
     .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid),
     .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr),
     .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size),
+    .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready),
+    .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid),
+    .io_sb_axi_r_bits_data(dbg_io_sb_axi_r_bits_data),
+    .io_sb_axi_r_bits_resp(dbg_io_sb_axi_r_bits_resp),
     .io_dbg_dec_dbg_ib_dbg_cmd_valid(dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid),
     .io_dbg_dec_dbg_ib_dbg_cmd_write(dbg_io_dbg_dec_dbg_ib_dbg_cmd_write),
     .io_dbg_dec_dbg_ib_dbg_cmd_type(dbg_io_dbg_dec_dbg_ib_dbg_cmd_type),
@@ -80754,11 +83420,11 @@ module quasar(
     .io_lsu_pic_picm_rd_data(lsu_io_lsu_pic_picm_rd_data),
     .io_lsu_exu_exu_lsu_rs1_d(lsu_io_lsu_exu_exu_lsu_rs1_d),
     .io_lsu_exu_exu_lsu_rs2_d(lsu_io_lsu_exu_exu_lsu_rs2_d),
+    .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
     .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable),
-    .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable),
     .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable),
     .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any),
     .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any),
@@ -80783,14 +83449,27 @@ module quasar(
     .io_dccm_rd_data_hi(lsu_io_dccm_rd_data_hi),
     .io_lsu_tlu_lsu_pmu_load_external_m(lsu_io_lsu_tlu_lsu_pmu_load_external_m),
     .io_lsu_tlu_lsu_pmu_store_external_m(lsu_io_lsu_tlu_lsu_pmu_store_external_m),
+    .io_axi_aw_ready(lsu_io_axi_aw_ready),
     .io_axi_aw_valid(lsu_io_axi_aw_valid),
+    .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr),
     .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size),
+    .io_axi_w_ready(lsu_io_axi_w_ready),
     .io_axi_w_valid(lsu_io_axi_w_valid),
+    .io_axi_w_bits_data(lsu_io_axi_w_bits_data),
     .io_axi_w_bits_strb(lsu_io_axi_w_bits_strb),
+    .io_axi_b_valid(lsu_io_axi_b_valid),
+    .io_axi_b_bits_resp(lsu_io_axi_b_bits_resp),
+    .io_axi_b_bits_id(lsu_io_axi_b_bits_id),
+    .io_axi_ar_ready(lsu_io_axi_ar_ready),
     .io_axi_ar_valid(lsu_io_axi_ar_valid),
+    .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr),
     .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size),
+    .io_axi_r_valid(lsu_io_axi_r_valid),
+    .io_axi_r_bits_id(lsu_io_axi_r_bits_id),
+    .io_axi_r_bits_data(lsu_io_axi_r_bits_data),
+    .io_axi_r_bits_resp(lsu_io_axi_r_bits_resp),
     .io_dec_tlu_flush_lower_r(lsu_io_dec_tlu_flush_lower_r),
     .io_dec_tlu_i0_kill_writeb_r(lsu_io_dec_tlu_i0_kill_writeb_r),
     .io_dec_tlu_force_halt(lsu_io_dec_tlu_force_halt),
@@ -80902,8 +83581,21 @@ module quasar(
     .io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag),
     .io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata),
     .io_iccm_ready(dma_ctrl_io_iccm_ready),
+    .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready),
+    .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid),
+    .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr),
+    .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size),
+    .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready),
+    .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid),
+    .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data),
+    .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb),
     .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid),
+    .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready),
+    .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid),
+    .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr),
+    .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size),
     .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid),
+    .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data),
     .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp),
     .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req),
     .io_lsu_dma_dma_lsc_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr),
@@ -80946,19 +83638,34 @@ module quasar(
     .io_clk_override(axi4_to_ahb_io_clk_override),
     .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready),
     .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid),
+    .io_axi_aw_bits_id(axi4_to_ahb_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(axi4_to_ahb_io_axi_aw_bits_addr),
     .io_axi_aw_bits_size(axi4_to_ahb_io_axi_aw_bits_size),
     .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready),
     .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid),
+    .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data),
     .io_axi_w_bits_strb(axi4_to_ahb_io_axi_w_bits_strb),
     .io_axi_b_ready(axi4_to_ahb_io_axi_b_ready),
+    .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid),
+    .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp),
+    .io_axi_b_bits_id(axi4_to_ahb_io_axi_b_bits_id),
+    .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready),
     .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid),
+    .io_axi_ar_bits_id(axi4_to_ahb_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(axi4_to_ahb_io_axi_ar_bits_addr),
     .io_axi_ar_bits_size(axi4_to_ahb_io_axi_ar_bits_size),
+    .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid),
+    .io_axi_r_bits_id(axi4_to_ahb_io_axi_r_bits_id),
+    .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data),
+    .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp),
+    .io_ahb_in_hrdata(axi4_to_ahb_io_ahb_in_hrdata),
     .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready),
     .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp),
+    .io_ahb_out_haddr(axi4_to_ahb_io_ahb_out_haddr),
+    .io_ahb_out_hsize(axi4_to_ahb_io_ahb_out_hsize),
     .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans),
-    .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite)
+    .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite),
+    .io_ahb_out_hwdata(axi4_to_ahb_io_ahb_out_hwdata)
   );
   axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 243:33]
     .clock(axi4_to_ahb_1_clock),
@@ -80968,19 +83675,34 @@ module quasar(
     .io_clk_override(axi4_to_ahb_1_io_clk_override),
     .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready),
     .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid),
+    .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(axi4_to_ahb_1_io_axi_aw_bits_addr),
     .io_axi_aw_bits_size(axi4_to_ahb_1_io_axi_aw_bits_size),
     .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready),
     .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid),
+    .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data),
     .io_axi_w_bits_strb(axi4_to_ahb_1_io_axi_w_bits_strb),
     .io_axi_b_ready(axi4_to_ahb_1_io_axi_b_ready),
+    .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid),
+    .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp),
+    .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id),
+    .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready),
     .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid),
+    .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(axi4_to_ahb_1_io_axi_ar_bits_addr),
     .io_axi_ar_bits_size(axi4_to_ahb_1_io_axi_ar_bits_size),
+    .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid),
+    .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id),
+    .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data),
+    .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp),
+    .io_ahb_in_hrdata(axi4_to_ahb_1_io_ahb_in_hrdata),
     .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready),
     .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp),
+    .io_ahb_out_haddr(axi4_to_ahb_1_io_ahb_out_haddr),
+    .io_ahb_out_hsize(axi4_to_ahb_1_io_ahb_out_hsize),
     .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans),
-    .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite)
+    .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite),
+    .io_ahb_out_hwdata(axi4_to_ahb_1_io_ahb_out_hwdata)
   );
   axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 244:33]
     .clock(axi4_to_ahb_2_clock),
@@ -80990,38 +83712,83 @@ module quasar(
     .io_clk_override(axi4_to_ahb_2_io_clk_override),
     .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready),
     .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid),
+    .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(axi4_to_ahb_2_io_axi_aw_bits_addr),
     .io_axi_aw_bits_size(axi4_to_ahb_2_io_axi_aw_bits_size),
     .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready),
     .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid),
+    .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data),
     .io_axi_w_bits_strb(axi4_to_ahb_2_io_axi_w_bits_strb),
     .io_axi_b_ready(axi4_to_ahb_2_io_axi_b_ready),
+    .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid),
+    .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp),
+    .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id),
+    .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready),
     .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid),
+    .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(axi4_to_ahb_2_io_axi_ar_bits_addr),
     .io_axi_ar_bits_size(axi4_to_ahb_2_io_axi_ar_bits_size),
+    .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid),
+    .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id),
+    .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data),
+    .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp),
+    .io_ahb_in_hrdata(axi4_to_ahb_2_io_ahb_in_hrdata),
     .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready),
     .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp),
+    .io_ahb_out_haddr(axi4_to_ahb_2_io_ahb_out_haddr),
+    .io_ahb_out_hsize(axi4_to_ahb_2_io_ahb_out_hsize),
     .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans),
-    .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite)
+    .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite),
+    .io_ahb_out_hwdata(axi4_to_ahb_2_io_ahb_out_hwdata)
   );
   ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 245:33]
     .clock(ahb_to_axi4_clock),
     .reset(ahb_to_axi4_reset),
     .io_scan_mode(ahb_to_axi4_io_scan_mode),
     .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en),
+    .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready),
     .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid),
+    .io_axi_aw_bits_addr(ahb_to_axi4_io_axi_aw_bits_addr),
+    .io_axi_aw_bits_size(ahb_to_axi4_io_axi_aw_bits_size),
+    .io_axi_w_valid(ahb_to_axi4_io_axi_w_valid),
+    .io_axi_w_bits_data(ahb_to_axi4_io_axi_w_bits_data),
+    .io_axi_w_bits_strb(ahb_to_axi4_io_axi_w_bits_strb),
+    .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready),
     .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid),
+    .io_axi_ar_bits_addr(ahb_to_axi4_io_axi_ar_bits_addr),
+    .io_axi_ar_bits_size(ahb_to_axi4_io_axi_ar_bits_size),
     .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid),
+    .io_axi_r_bits_data(ahb_to_axi4_io_axi_r_bits_data),
     .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp),
+    .io_ahb_sig_in_hrdata(ahb_to_axi4_io_ahb_sig_in_hrdata),
     .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready),
     .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp),
     .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr),
     .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize),
     .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans),
     .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite),
+    .io_ahb_sig_out_hwdata(ahb_to_axi4_io_ahb_sig_out_hwdata),
     .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel),
     .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin)
   );
+  assign io_lsu_ahb_out_haddr = axi4_to_ahb_2_io_ahb_out_haddr; // @[quasar.scala 251:28 quasar.scala 278:18]
+  assign io_lsu_ahb_out_hsize = axi4_to_ahb_2_io_ahb_out_hsize; // @[quasar.scala 251:28 quasar.scala 278:18]
+  assign io_lsu_ahb_out_htrans = axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 251:28 quasar.scala 278:18]
+  assign io_lsu_ahb_out_hwrite = axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 251:28 quasar.scala 278:18]
+  assign io_lsu_ahb_out_hwdata = axi4_to_ahb_2_io_ahb_out_hwdata; // @[quasar.scala 251:28 quasar.scala 278:18]
+  assign io_ifu_ahb_out_haddr = axi4_to_ahb_1_io_ahb_out_haddr; // @[quasar.scala 258:28 quasar.scala 279:18]
+  assign io_ifu_ahb_out_hsize = axi4_to_ahb_1_io_ahb_out_hsize; // @[quasar.scala 258:28 quasar.scala 279:18]
+  assign io_ifu_ahb_out_htrans = axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 258:28 quasar.scala 279:18]
+  assign io_ifu_ahb_out_hwrite = axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 258:28 quasar.scala 279:18]
+  assign io_ifu_ahb_out_hwdata = axi4_to_ahb_1_io_ahb_out_hwdata; // @[quasar.scala 258:28 quasar.scala 279:18]
+  assign io_sb_ahb_out_haddr = axi4_to_ahb_io_ahb_out_haddr; // @[quasar.scala 264:27 quasar.scala 280:17]
+  assign io_sb_ahb_out_hsize = axi4_to_ahb_io_ahb_out_hsize; // @[quasar.scala 264:27 quasar.scala 280:17]
+  assign io_sb_ahb_out_htrans = axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 264:27 quasar.scala 280:17]
+  assign io_sb_ahb_out_hwrite = axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 264:27 quasar.scala 280:17]
+  assign io_sb_ahb_out_hwdata = axi4_to_ahb_io_ahb_out_hwdata; // @[quasar.scala 264:27 quasar.scala 280:17]
+  assign io_dma_ahb_sig_in_hrdata = ahb_to_axi4_io_ahb_sig_in_hrdata; // @[quasar.scala 270:28 quasar.scala 281:18]
+  assign io_dma_ahb_sig_in_hready = ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 270:28 quasar.scala 281:18]
+  assign io_dma_ahb_sig_in_hresp = ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 270:28 quasar.scala 281:18]
   assign io_core_rst_l = reset & _T_2; // @[quasar.scala 80:17]
   assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 220:19]
   assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 220:19]
@@ -81054,7 +83821,10 @@ module quasar(
   assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 238:11]
   assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 101:13]
   assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 101:13]
+  assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 101:13]
   assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 101:13]
+  assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 101:13]
+  assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 101:13]
   assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 101:13]
   assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 101:13]
   assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 101:13]
@@ -81120,6 +83890,11 @@ module quasar(
   assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 101:13]
   assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 101:13]
   assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 101:13]
+  assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 257:28 quasar.scala 284:27]
+  assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 257:28 quasar.scala 284:27]
+  assign ifu_io_ifu_r_bits_id = {{2'd0}, axi4_to_ahb_1_io_axi_r_bits_id}; // @[quasar.scala 257:28 quasar.scala 284:27]
+  assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 257:28 quasar.scala 284:27]
+  assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 257:28 quasar.scala 284:27]
   assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 99:25]
   assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 100:18]
   assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 100:18]
@@ -81195,6 +83970,7 @@ module quasar(
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 89:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 89:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 89:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 89:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 89:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 89:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 89:18]
@@ -81214,6 +83990,7 @@ module quasar(
   assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 152:18]
   assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 152:18]
   assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 152:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:18]
@@ -81259,6 +84036,14 @@ module quasar(
   assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 186:23]
   assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 187:24]
   assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 188:24]
+  assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 263:27 quasar.scala 283:27]
+  assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27]
   assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 202:26]
   assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 189:25]
   assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 190:20]
@@ -81346,10 +84131,19 @@ module quasar(
   assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 164:18]
   assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 164:18]
   assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:18]
-  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:18]
   assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:18]
   assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11]
   assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11]
+  assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_b_bits_resp = axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_b_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_b_bits_id}; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_r_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_r_bits_id}; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 250:28 quasar.scala 285:27]
+  assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27]
   assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 160:32]
   assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 161:35]
   assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 162:29]
@@ -81424,6 +84218,15 @@ module quasar(
   assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 205:29]
   assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 206:30]
   assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 207:26]
+  assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_aw_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_aw_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_w_valid; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_w_bits_data; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_w_bits_strb; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_ar_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27]
+  assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_ar_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 172:18]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 172:18]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 172:18]
@@ -81441,14 +84244,18 @@ module quasar(
   assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 261:34]
   assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 262:36]
   assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 263:27]
+  assign axi4_to_ahb_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 263:27]
+  assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_b_ready = 1'h1; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 263:27]
+  assign axi4_to_ahb_io_axi_ar_bits_id = 1'h0; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 263:27]
   assign axi4_to_ahb_io_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 263:27]
+  assign axi4_to_ahb_io_ahb_in_hrdata = io_sb_ahb_in_hrdata; // @[quasar.scala 264:27]
   assign axi4_to_ahb_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 264:27]
   assign axi4_to_ahb_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 264:27]
   assign axi4_to_ahb_1_clock = clock;
@@ -81457,14 +84264,18 @@ module quasar(
   assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 255:35]
   assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 256:37]
   assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 257:28]
+  assign axi4_to_ahb_1_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_aw_bits_addr = 32'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_aw_bits_size = 3'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 257:28]
+  assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_w_bits_strb = 8'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_b_ready = 1'h0; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 257:28]
+  assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id[0]; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 257:28]
   assign axi4_to_ahb_1_io_axi_ar_bits_size = 3'h3; // @[quasar.scala 257:28]
+  assign axi4_to_ahb_1_io_ahb_in_hrdata = io_ifu_ahb_in_hrdata; // @[quasar.scala 258:28]
   assign axi4_to_ahb_1_io_ahb_in_hready = io_ifu_ahb_in_hready; // @[quasar.scala 258:28]
   assign axi4_to_ahb_1_io_ahb_in_hresp = io_ifu_ahb_in_hresp; // @[quasar.scala 258:28]
   assign axi4_to_ahb_2_clock = clock;
@@ -81473,26 +84284,34 @@ module quasar(
   assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 248:35]
   assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 249:37]
   assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 250:28]
+  assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id[0]; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 250:28]
+  assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_b_ready = 1'h1; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 250:28]
+  assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id[0]; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 250:28]
   assign axi4_to_ahb_2_io_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 250:28]
+  assign axi4_to_ahb_2_io_ahb_in_hrdata = io_lsu_ahb_in_hrdata; // @[quasar.scala 251:28]
   assign axi4_to_ahb_2_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 251:28]
   assign axi4_to_ahb_2_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 251:28]
   assign ahb_to_axi4_clock = clock;
   assign ahb_to_axi4_reset = reset;
   assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 266:34]
   assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 267:35]
+  assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 269:28]
+  assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 269:28]
   assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 269:28]
+  assign ahb_to_axi4_io_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 269:28]
   assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 269:28]
   assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_sig_out_haddr; // @[quasar.scala 270:28]
   assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_sig_out_hsize; // @[quasar.scala 270:28]
   assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_sig_out_htrans; // @[quasar.scala 270:28]
   assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_sig_out_hwrite; // @[quasar.scala 270:28]
+  assign ahb_to_axi4_io_ahb_sig_out_hwdata = io_dma_ahb_sig_out_hwdata; // @[quasar.scala 270:28]
   assign ahb_to_axi4_io_ahb_hsel = io_dma_ahb_hsel; // @[quasar.scala 270:28]
   assign ahb_to_axi4_io_ahb_hreadyin = io_dma_ahb_hreadyin; // @[quasar.scala 270:28]
 endmodule
@@ -81652,16 +84471,38 @@ module quasar_wrapper(
   wire  dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27]
   wire  core_clock; // @[quasar_wrapper.scala 65:20]
   wire  core_reset; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_lsu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20]
   wire  core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
   wire  core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_ifu_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20]
   wire  core_io_ifu_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
   wire  core_io_ifu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_sb_ahb_in_hrdata; // @[quasar_wrapper.scala 65:20]
   wire  core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
   wire  core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 65:20]
   wire [31:0] core_io_dma_ahb_sig_out_haddr; // @[quasar_wrapper.scala 65:20]
   wire [2:0] core_io_dma_ahb_sig_out_hsize; // @[quasar_wrapper.scala 65:20]
   wire [1:0] core_io_dma_ahb_sig_out_htrans; // @[quasar_wrapper.scala 65:20]
   wire  core_io_dma_ahb_sig_out_hwrite; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_dma_ahb_sig_out_hwdata; // @[quasar_wrapper.scala 65:20]
   wire  core_io_dma_ahb_hsel; // @[quasar_wrapper.scala 65:20]
   wire  core_io_dma_ahb_hreadyin; // @[quasar_wrapper.scala 65:20]
   wire  core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20]
@@ -81708,7 +84549,10 @@ module quasar_wrapper(
   wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 65:20]
   wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 65:20]
   wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ic_wr_en; // @[quasar_wrapper.scala 65:20]
   wire  core_io_ic_rd_en; // @[quasar_wrapper.scala 65:20]
+  wire [70:0] core_io_ic_wr_data_0; // @[quasar_wrapper.scala 65:20]
+  wire [70:0] core_io_ic_wr_data_1; // @[quasar_wrapper.scala 65:20]
   wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 65:20]
   wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 65:20]
   wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 65:20]
@@ -81812,16 +84656,38 @@ module quasar_wrapper(
   quasar core ( // @[quasar_wrapper.scala 65:20]
     .clock(core_clock),
     .reset(core_reset),
+    .io_lsu_ahb_in_hrdata(core_io_lsu_ahb_in_hrdata),
     .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready),
     .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp),
+    .io_lsu_ahb_out_haddr(core_io_lsu_ahb_out_haddr),
+    .io_lsu_ahb_out_hsize(core_io_lsu_ahb_out_hsize),
+    .io_lsu_ahb_out_htrans(core_io_lsu_ahb_out_htrans),
+    .io_lsu_ahb_out_hwrite(core_io_lsu_ahb_out_hwrite),
+    .io_lsu_ahb_out_hwdata(core_io_lsu_ahb_out_hwdata),
+    .io_ifu_ahb_in_hrdata(core_io_ifu_ahb_in_hrdata),
     .io_ifu_ahb_in_hready(core_io_ifu_ahb_in_hready),
     .io_ifu_ahb_in_hresp(core_io_ifu_ahb_in_hresp),
+    .io_ifu_ahb_out_haddr(core_io_ifu_ahb_out_haddr),
+    .io_ifu_ahb_out_hsize(core_io_ifu_ahb_out_hsize),
+    .io_ifu_ahb_out_htrans(core_io_ifu_ahb_out_htrans),
+    .io_ifu_ahb_out_hwrite(core_io_ifu_ahb_out_hwrite),
+    .io_ifu_ahb_out_hwdata(core_io_ifu_ahb_out_hwdata),
+    .io_sb_ahb_in_hrdata(core_io_sb_ahb_in_hrdata),
     .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready),
     .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp),
+    .io_sb_ahb_out_haddr(core_io_sb_ahb_out_haddr),
+    .io_sb_ahb_out_hsize(core_io_sb_ahb_out_hsize),
+    .io_sb_ahb_out_htrans(core_io_sb_ahb_out_htrans),
+    .io_sb_ahb_out_hwrite(core_io_sb_ahb_out_hwrite),
+    .io_sb_ahb_out_hwdata(core_io_sb_ahb_out_hwdata),
+    .io_dma_ahb_sig_in_hrdata(core_io_dma_ahb_sig_in_hrdata),
+    .io_dma_ahb_sig_in_hready(core_io_dma_ahb_sig_in_hready),
+    .io_dma_ahb_sig_in_hresp(core_io_dma_ahb_sig_in_hresp),
     .io_dma_ahb_sig_out_haddr(core_io_dma_ahb_sig_out_haddr),
     .io_dma_ahb_sig_out_hsize(core_io_dma_ahb_sig_out_hsize),
     .io_dma_ahb_sig_out_htrans(core_io_dma_ahb_sig_out_htrans),
     .io_dma_ahb_sig_out_hwrite(core_io_dma_ahb_sig_out_hwrite),
+    .io_dma_ahb_sig_out_hwdata(core_io_dma_ahb_sig_out_hwdata),
     .io_dma_ahb_hsel(core_io_dma_ahb_hsel),
     .io_dma_ahb_hreadyin(core_io_dma_ahb_hreadyin),
     .io_dbg_rst_l(core_io_dbg_rst_l),
@@ -81868,7 +84734,10 @@ module quasar_wrapper(
     .io_dccm_rd_data_hi(core_io_dccm_rd_data_hi),
     .io_ic_rw_addr(core_io_ic_rw_addr),
     .io_ic_tag_valid(core_io_ic_tag_valid),
+    .io_ic_wr_en(core_io_ic_wr_en),
     .io_ic_rd_en(core_io_ic_rd_en),
+    .io_ic_wr_data_0(core_io_ic_wr_data_0),
+    .io_ic_wr_data_1(core_io_ic_wr_data_1),
     .io_ic_debug_wr_data(core_io_ic_debug_wr_data),
     .io_ic_debug_addr(core_io_ic_debug_addr),
     .io_ic_rd_data(core_io_ic_rd_data),
@@ -81905,33 +84774,33 @@ module quasar_wrapper(
     .io_soft_int(core_io_soft_int),
     .io_scan_mode(core_io_scan_mode)
   );
-  assign io_lsu_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 111:21]
+  assign io_lsu_brg_out_haddr = core_io_lsu_ahb_out_haddr; // @[quasar_wrapper.scala 111:21]
   assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 111:21]
   assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_lsu_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_lsu_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_lsu_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_lsu_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_lsu_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 111:21]
-  assign io_ifu_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 110:21]
+  assign io_lsu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 111:21]
+  assign io_lsu_brg_out_hsize = core_io_lsu_ahb_out_hsize; // @[quasar_wrapper.scala 111:21]
+  assign io_lsu_brg_out_htrans = core_io_lsu_ahb_out_htrans; // @[quasar_wrapper.scala 111:21]
+  assign io_lsu_brg_out_hwrite = core_io_lsu_ahb_out_hwrite; // @[quasar_wrapper.scala 111:21]
+  assign io_lsu_brg_out_hwdata = core_io_lsu_ahb_out_hwdata; // @[quasar_wrapper.scala 111:21]
+  assign io_ifu_brg_out_haddr = core_io_ifu_ahb_out_haddr; // @[quasar_wrapper.scala 110:21]
   assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 110:21]
   assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_ifu_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_ifu_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_ifu_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_ifu_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_ifu_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 110:21]
-  assign io_sb_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 112:20]
+  assign io_ifu_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 110:21]
+  assign io_ifu_brg_out_hsize = core_io_ifu_ahb_out_hsize; // @[quasar_wrapper.scala 110:21]
+  assign io_ifu_brg_out_htrans = core_io_ifu_ahb_out_htrans; // @[quasar_wrapper.scala 110:21]
+  assign io_ifu_brg_out_hwrite = core_io_ifu_ahb_out_hwrite; // @[quasar_wrapper.scala 110:21]
+  assign io_ifu_brg_out_hwdata = core_io_ifu_ahb_out_hwdata; // @[quasar_wrapper.scala 110:21]
+  assign io_sb_brg_out_haddr = core_io_sb_ahb_out_haddr; // @[quasar_wrapper.scala 112:20]
   assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 112:20]
   assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_sb_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_sb_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_sb_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_sb_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_sb_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 112:20]
-  assign io_dma_brg_sig_in_hrdata = 64'h0; // @[quasar_wrapper.scala 113:21]
-  assign io_dma_brg_sig_in_hready = 1'h0; // @[quasar_wrapper.scala 113:21]
-  assign io_dma_brg_sig_in_hresp = 1'h0; // @[quasar_wrapper.scala 113:21]
+  assign io_sb_brg_out_hprot = 4'h3; // @[quasar_wrapper.scala 112:20]
+  assign io_sb_brg_out_hsize = core_io_sb_ahb_out_hsize; // @[quasar_wrapper.scala 112:20]
+  assign io_sb_brg_out_htrans = core_io_sb_ahb_out_htrans; // @[quasar_wrapper.scala 112:20]
+  assign io_sb_brg_out_hwrite = core_io_sb_ahb_out_hwrite; // @[quasar_wrapper.scala 112:20]
+  assign io_sb_brg_out_hwdata = core_io_sb_ahb_out_hwdata; // @[quasar_wrapper.scala 112:20]
+  assign io_dma_brg_sig_in_hrdata = core_io_dma_ahb_sig_in_hrdata; // @[quasar_wrapper.scala 113:21]
+  assign io_dma_brg_sig_in_hready = core_io_dma_ahb_sig_in_hready; // @[quasar_wrapper.scala 113:21]
+  assign io_dma_brg_sig_in_hresp = core_io_dma_ahb_sig_in_hresp; // @[quasar_wrapper.scala 113:21]
   assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23]
   assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23]
   assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23]
@@ -81973,10 +84842,10 @@ module quasar_wrapper(
   assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 95:16]
   assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 94:14]
   assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 94:14]
-  assign mem_ic_wr_en = 2'h0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 94:14]
   assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 94:14]
-  assign mem_ic_wr_data_0 = 71'h0; // @[quasar_wrapper.scala 94:14]
-  assign mem_ic_wr_data_1 = 71'h0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 94:14]
   assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 94:14]
   assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 94:14]
   assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 94:14]
@@ -81996,16 +84865,20 @@ module quasar_wrapper(
   assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26]
   assign core_clock = clock;
   assign core_reset = reset;
+  assign core_io_lsu_ahb_in_hrdata = io_lsu_brg_in_hrdata; // @[quasar_wrapper.scala 111:21]
   assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 111:21]
   assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 111:21]
+  assign core_io_ifu_ahb_in_hrdata = io_ifu_brg_in_hrdata; // @[quasar_wrapper.scala 110:21]
   assign core_io_ifu_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 110:21]
   assign core_io_ifu_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 110:21]
+  assign core_io_sb_ahb_in_hrdata = io_sb_brg_in_hrdata; // @[quasar_wrapper.scala 112:20]
   assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 112:20]
   assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 112:20]
   assign core_io_dma_ahb_sig_out_haddr = io_dma_brg_sig_out_haddr; // @[quasar_wrapper.scala 113:21]
   assign core_io_dma_ahb_sig_out_hsize = io_dma_brg_sig_out_hsize; // @[quasar_wrapper.scala 113:21]
   assign core_io_dma_ahb_sig_out_htrans = io_dma_brg_sig_out_htrans; // @[quasar_wrapper.scala 113:21]
   assign core_io_dma_ahb_sig_out_hwrite = io_dma_brg_sig_out_hwrite; // @[quasar_wrapper.scala 113:21]
+  assign core_io_dma_ahb_sig_out_hwdata = io_dma_brg_sig_out_hwdata; // @[quasar_wrapper.scala 113:21]
   assign core_io_dma_ahb_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 113:21]
   assign core_io_dma_ahb_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 113:21]
   assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21]
diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala
index 6571fff2..e9af12d3 100644
--- a/src/main/scala/lib/param.scala
+++ b/src/main/scala/lib/param.scala
@@ -21,7 +21,7 @@ trait param {
   val BTB_INDEX3_HI          = 	0x19
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
-  val BUILD_AHB_LITE         = 	0x0
+  val BUILD_AHB_LITE         = 	0x1
   val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3
diff --git a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar
index fece8274..ce802477 100644
Binary files a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar and b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar differ
diff --git a/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class
index 7cb29a3d..2d41b733 100644
Binary files a/target/scala-2.12/classes/lib/param.class and b/target/scala-2.12/classes/lib/param.class differ
diff --git a/target/streams/_global/_global/checkBuildSources/_global/streams/out b/target/streams/_global/_global/checkBuildSources/_global/streams/out
index 6c981659..24ce6f61 100644
--- a/target/streams/_global/_global/checkBuildSources/_global/streams/out
+++ b/target/streams/_global/_global/checkBuildSources/_global/streams/out
@@ -1 +1 @@
-[debug] Checking for meta build source updates
+[debug] Checking for meta build source updates
diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous
index a343d29d..cd36b640 100644
--- a/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
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diff --git a/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/target/streams/compile/_global/_global/compileSourceFileInputs/previous
index 1dc56a44..63ddbeb1 100644
--- a/target/streams/compile/_global/_global/compileSourceFileInputs/previous
+++ b/target/streams/compile/_global/_global/compileSourceFileInputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala","503f063a2675efdbfb57a502a4fa60dea15b9331"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala","f24faa32ddf3bf63a73061d9d24e5c00058f3d2b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala","f3dd5c2431ee23c1b5b158754bdad765cc909ba9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala","6e8e5a15a1d60123a4f55018ef9caede35deeeb1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala","a2fdfc7178e808f4bbb358784e7aa677d7fde3b6"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala","a66e9f0672f75f5a3288a7362ed7976e9d4048d0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala","aa8a428318dab2b44f123bfe674710f400b73ff9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala","343974417ab69591d12c7d15a8bee798ad82be20"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala","a5028b217bfd6cc6fad3c8388d151e7f8fbcbe77"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala","9923de9bfd2f504ae2bb2b15c42a32ceaa2d5846"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala","0f9289fbd8cba0253e85afd8439b7fad7f368274"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala","d9c545afed0cc63a9ab0b880ec36abca3e7fb61a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala","d9284179851f33d9cd92a94f31bd327c1fdef9ac"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala","415669c1df1dfb3db6b4d92e4010e4ccf4870d7e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala","8d8d0e8ed37d5810d2b47b5762ccdb75afc7fce3"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala","013b036929ed7c9f917ba73eba950f188939743c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala","d343e32edc9108a662b206313eaf1da425813eec"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala","ef5be7fa3e120fc7104f10ab2b519cca0905a566"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala","6c672ea7f0e7f4522288b3fe7f476dad6908ff30"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala","532968a2606c8c841ea8464c48293c06a0e069df"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala","ee1c243afb72958e00597a078bfb318805b9e8bc"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala","99a4c8d332a0802d19c3c31f621b978afaf986ff"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala","03281ac6989dfaf67a9693a253a4aca96e04e5a1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala","6980af1cdf70a73b9d9dc1b6bdd14d50395cc8e0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala","7c91d79f3efef190e30f1ad2346f5113c7a5598a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala","95624005291940cd8a95dba6bc01a44a0fd312f7"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}]
\ No newline at end of file
+["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala","cda24ad15d9de2a10ff5535fa4e6b0acd1245a96"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala","317c73a6f39d63e30b592e7261455062c6f31a0c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala","7de89776d7736202c5586c747a3886f28722a7fe"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala","23d46aa6c2bb3ccea125006655c103c982f1b9b1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala","58feaf508d092ed1910a9d0dfcf34bdd11f3049b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala","c37fe97894075254205a512d25d660b5f15788c0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala","9f207697371dc1f28e50e429fe84ae24b9de4fc3"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala","02c1c840ed0f45ee3b585b8da45554e11766615a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala","f8aa1a99581dafdffe531465f6637f37d9905113"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala","9923de9bfd2f504ae2bb2b15c42a32ceaa2d5846"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala","ab406bf532cd75335375aefb2489072385ebbc7e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala","d9c545afed0cc63a9ab0b880ec36abca3e7fb61a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala","d9284179851f33d9cd92a94f31bd327c1fdef9ac"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala","2f0d8e280d886bc80485e4b0341eeeb04812a552"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala","d7ca34e7d329d7eef0e2506c7a07d6911f2226bf"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala","013b036929ed7c9f917ba73eba950f188939743c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala","369f3ac01e07eb8a2ec97049e878647a148eefef"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala","5ddd0ef60348a8c846f9be03f5672f1e699e4571"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala","6a84cc0a74174fc9ed220355d4e478a8ba85cfcc"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala","7d317f9c4391b9208baad34bef685a94deebda2e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala","86cba6b253cea7c85f14f6816c06ee783c672dd7"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala","0eb6908965b8cb41358107eae90c06a3202bb11c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala","fe3fb275277cd7a9157cb234c209e23c52fe038a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala","cb54784303a8451eea6df9648ea012ad0f2b317e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala","7c91d79f3efef190e30f1ad2346f5113c7a5598a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala","cff6c4a3eecc6b3ec77c870747b620142bd9244c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}]
\ No newline at end of file
diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out
index 2e417dde..0390d08a 100644
--- a/target/streams/compile/compile/_global/streams/out
+++ b/target/streams/compile/compile/_global/streams/out
@@ -1,18 +1,6 @@
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala:502:3: a pure expression does nothing in statement position; multiline expressions may require enclosing parentheses
-[warn]   bus_ifu_bus_clk_en
-[warn]   ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:8:5: match may not be exhaustive.
+[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive.
 [warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)
 [warn]     (ICACHE_WAYPACK, ICACHE_ECC) match{
 [warn]     ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:1751:16: comparing values of types Int and Boolean using `==' will always yield false
-[warn]  if(BUILD_AXI4 == true){
-[warn]                ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2122:17: comparing values of types Int and Boolean using `==' will always yield false
-[warn]  if (ICACHE_ECC == true) {
-[warn]                 ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2155:17: comparing values of types Int and Boolean using `==' will always yield false
-[warn]  if (ICACHE_ECC == true)  io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
-[warn]                 ^
-[warn] there were 3738 feature warnings; re-run with -feature for details
-[warn] 6 warnings found
+[warn] there were 3745 feature warnings; re-run with -feature for details
+[warn] two warnings found
diff --git a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip
index 900f8dc9..594912b2 100644
Binary files a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ
diff --git a/target/streams/compile/compileIncremental/_global/streams/export b/target/streams/compile/compileIncremental/_global/streams/export
index 0e2440a1..927c3fd5 100644
--- a/target/streams/compile/compileIncremental/_global/streams/export
+++ b/target/streams/compile/compileIncremental/_global/streams/export
@@ -1 +1 @@
-scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala
+scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala
diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out
index 576a31c2..1113fefa 100644
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
@@ -1,40 +1,84 @@
 [debug] 
 [debug] Initial source changes: 
-[debug] 	removed:Set(/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_trigger.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dbg/el2_dbg.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/el2_pic_ctrl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/rvjtag_tap.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_jtag_to_core_sync.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lsu/el2_lsu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_decode_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_ib_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu_alu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/ifu/el2_ifu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/beh_lib.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/test.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_tlu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/include/el2_bundle.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_gpr_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/el2_lib.scala)
-[debug] 	added: Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala)
-[debug] 	modified: Set()
-[debug] Invalidated products: Set(/home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/ifu/el2_ifu.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_dest_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_rets_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/ib_gen$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_timer_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/test$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/el2_exu_alu_ctl$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_class_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvbsadder.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_dec_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trig$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/test$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvtwoscomp.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/csr_tlu.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/alu.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdff$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvrangecheck.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lsu/el2_lsu.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_trace_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$gated_latch$$anon$3.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trig$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dmi/rvjtag_tap.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/gpr_gen$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/alu$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_inst_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_encode_64$$anon$14.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvrangecheck$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dbg/el2_dbg.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_decode_64$rvsyncss$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_tlu_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trig.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/CSRs.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvlsadder.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritygen$$anon$10.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_reg_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/pic_main$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdffs$$anon$3.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritygen$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/el2_exu.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_encode$$anon$12.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvtwoscomp$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_trigger_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_br_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvmaskandmatch$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_predict_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_decode_ctl$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_load_cam_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_lsu_error_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvsyncss$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_gpr_ctl_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/test$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_timer_ctl_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_ib_ctl_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/CSR_VAL.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvsyncss$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_main.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvmaskandmatch$$anon$8.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_cache_debug_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/test.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_decode_csr_read.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_gpr_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvdffe$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_div_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritycheck$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvsyncss$$anon$4.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/ib_gen$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_ic_tag_ext_in_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_ic_data_ext_in_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvmaskandmatch.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_mul_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvecc_encode.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_dccm_ext_in_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_CSR_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritygen.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdff$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_tlu_ctl_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvecc_encode_64.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/param.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_encode.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/tlu_gen.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/gpr_gen$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritycheck$$anon$11.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdff.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/ib_gen.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_trap_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_lsu_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvlsadder$$anon$5.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_inst_pkt_t$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_decode_64$$anon$15.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvtwoscomp$$anon$7.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvecc_encode_64$$anon$2.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/el2_exu_alu_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_trigger.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/pic_main$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvclkhdr.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_dec_tlu_csr_pkt.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdffs.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/tlu_gen$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rveven_paritycheck.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdffsc$$anon$2.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_trigger$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/tlu_gen$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$gated_latch.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_decode.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvdffsc.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_encode_64.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_decode_64.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/pic_main.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_alu_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/exu/alu$delayedInit$body.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvecc_encode$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvsyncss.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvbsadder$$anon$6.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_decode_csr_read_IO.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/gpr_gen.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvclkhdr$$anon$4.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/el2_pic_ctrl$$anon$1.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/include/el2_br_tlu_pkt_t.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/el2_lib$rvclkhdr$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvrangecheck$$anon$9.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec_ib_ctl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl$.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/lib/rvecc_decode$$anon$13.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/el2_pic_ctrl.class, /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/classes/dec/el2_dec.class)
+[debug] 	removed:Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala)
+[debug] 	added: Set()
+[debug] 	modified: Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala)
+[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_mem_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_dccm_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dbg_ib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvdffe$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_ifc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/Mem_bundle.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dbg_dctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/csr_tlu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/state_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_ib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_busbuff.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/rets_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trigger_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_div.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dctl_busbuff.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dbg.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSRs.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trace_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_alu_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_alu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/trap_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/param.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_bp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvsyncss$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pic.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dctl_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/predict_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ib_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$2.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dest_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dma_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_bp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pic.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_ifu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/sb_state_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_tlu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/gpr_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/dbg_dma.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_ifc.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/iccm_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_tlu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/blackbox_mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_bundle.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dma_ctrl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper_module.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$4.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/mem_lsu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_aln.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_VAL.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_div_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar$mem.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/alu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu_mul_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/div_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/mul_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/Config.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_dec.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$3.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/mem/quasar.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_mem_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_error_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/br_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_intf.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/class_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/sb_state_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/decode_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/exu/exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/cache_debug_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_exu.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/load_cam_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_IO.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dma_lsc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dbg/state_t$.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_data.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/reg_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp.class, /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/mem_ctl_io.class)
 [debug] External API changes: API Changes: Set()
-[debug] Modified binary dependencies: Set(/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar, /home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-library.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar, /home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar, /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar, /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar, /home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar)
-[debug] Initial directly invalidated classes: Set(dec.el2_dec_decode_csr_read_IO, dec.test, include.el2_reg_pkt_t, dec.el2_dec, dmi.rvjtag_tap, include.el2_cache_debug_pkt_t, dec.el2_dec_ib_ctl, dmi.dmi_jtag_to_core_sync, lib.rvecc_decode_64, include.el2_ccm_ext_in_pkt_t, el2_pic_ctrl, include.el2_dest_pkt_t, dec.el2_dec_gpr_ctl_IO, include.el2_trigger_pkt_t, lib.param, exu.el2_exu_alu_ctl, include.el2_lsu_pkt_t, lib.rvecc_decode, dec.el2_dec_tlu_ctl, dec.el2_dec_tlu_ctl_IO, include.el2_br_tlu_pkt_t, dmi.dmi_wrapper, lib.rvdffs, dec.gpr_gen, lib.el2_lib.rvclkhdr, include.el2_lsu_error_pkt_t, include.el2_class_pkt_t, lib.rvlsadder, exu.alu, lib.el2_lib.rvecc_encode_64, lib.rvsyncss, lib.rvecc_decode_64.rvsyncss, include.el2_ic_tag_ext_in_pkt_t, lib.rvtwoscomp, include.el2_dec_pkt_t, lib.rvdff, dec.csr_tlu, include.el2_rets_pkt_t, dec.el2_CSR_IO, dec.el2_dec_timer_ctl, dec.tlu_gen, dec.CSRs, dec.ib_gen, dec.dec_decode, lsu.el2_lsu, dec.el2_dec_trigger, lib.rvmaskandmatch, dec.dec_main, lib.rveven_paritycheck, dec.dec_trig, dbg.el2_dbg, include.el2_ic_data_ext_in_pkt_t, include.el2_br_pkt_t, exu.el2_exu, include.el2_dccm_ext_in_pkt_t, lib.el2_lib.rvsyncss, lib.el2_lib.rvecc_encode, lib.rvbsadder, lib.el2_lib.gated_latch, include.el2_alu_pkt_t, lib.rvecc_encode_64, include.el2_inst_pkt_t, pic_main, include.el2_load_cam_pkt_t, lib.rvecc_encode, dec.el2_dec_dec_ctl, include.el2_dec_tlu_csr_pkt, lib.el2_lib, dec.el2_dec_IO, dec.CSR_VAL, include.el2_trap_pkt_t, dec.el2_dec_decode_ctl, lib.el2_lib.rvdffe, dec.el2_dec_decode_csr_read, dec.el2_dec_gpr_ctl, dec.el2_dec_ib_ctl_IO, dec.dec_dec_ctl, include.el2_mul_pkt_t, include.el2_trace_pkt_t, include.el2_predict_pkt_t, lib.rvrangecheck, lib.rvdffsc, lib.rveven_paritygen, ifu.el2_ifu, dec.el2_dec_timer_ctl_IO, include.el2_div_pkt_t)
+[debug] Modified binary dependencies: Set()
+[debug] Initial directly invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl)
 [debug] 
 [debug] Sources indirectly invalidated by:
-[debug] 	product: Set(/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_trigger.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dbg/el2_dbg.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/el2_pic_ctrl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/rvjtag_tap.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_jtag_to_core_sync.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lsu/el2_lsu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_decode_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_ib_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu_alu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/ifu/el2_ifu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/beh_lib.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/test.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_tlu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/include/el2_bundle.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_gpr_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/el2_lib.scala)
-[debug] 	binary dep: Set(/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_trigger.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/el2_pic_ctrl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_decode_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_ib_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu_alu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/beh_lib.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/test.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_tlu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/include/el2_bundle.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_gpr_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/el2_lib.scala)
+[debug] 	product: Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala)
+[debug] 	binary dep: Set()
 [debug] 	external source: Set()
-[debug] All initially invalidated classes: Set(dec.el2_dec_decode_csr_read_IO, dec.test, include.el2_reg_pkt_t, dec.el2_dec, dmi.rvjtag_tap, include.el2_cache_debug_pkt_t, dec.el2_dec_ib_ctl, dmi.dmi_jtag_to_core_sync, lib.rvecc_decode_64, include.el2_ccm_ext_in_pkt_t, el2_pic_ctrl, include.el2_dest_pkt_t, dec.el2_dec_gpr_ctl_IO, include.el2_trigger_pkt_t, lib.param, exu.el2_exu_alu_ctl, include.el2_lsu_pkt_t, lib.rvecc_decode, dec.el2_dec_tlu_ctl, dec.el2_dec_tlu_ctl_IO, include.el2_br_tlu_pkt_t, dmi.dmi_wrapper, lib.rvdffs, dec.gpr_gen, lib.el2_lib.rvclkhdr, include.el2_lsu_error_pkt_t, include.el2_class_pkt_t, lib.rvlsadder, exu.alu, lib.el2_lib.rvecc_encode_64, lib.rvsyncss, lib.rvecc_decode_64.rvsyncss, include.el2_ic_tag_ext_in_pkt_t, lib.rvtwoscomp, include.el2_dec_pkt_t, lib.rvdff, dec.csr_tlu, include.el2_rets_pkt_t, dec.el2_CSR_IO, dec.el2_dec_timer_ctl, dec.tlu_gen, dec.CSRs, dec.ib_gen, dec.dec_decode, lsu.el2_lsu, dec.el2_dec_trigger, lib.rvmaskandmatch, dec.dec_main, lib.rveven_paritycheck, dec.dec_trig, dbg.el2_dbg, include.el2_ic_data_ext_in_pkt_t, include.el2_br_pkt_t, exu.el2_exu, include.el2_dccm_ext_in_pkt_t, lib.el2_lib.rvsyncss, lib.el2_lib.rvecc_encode, lib.rvbsadder, lib.el2_lib.gated_latch, include.el2_alu_pkt_t, lib.rvecc_encode_64, include.el2_inst_pkt_t, pic_main, include.el2_load_cam_pkt_t, lib.rvecc_encode, dec.el2_dec_dec_ctl, include.el2_dec_tlu_csr_pkt, lib.el2_lib, dec.el2_dec_IO, dec.CSR_VAL, include.el2_trap_pkt_t, dec.el2_dec_decode_ctl, lib.el2_lib.rvdffe, dec.el2_dec_decode_csr_read, dec.el2_dec_gpr_ctl, dec.el2_dec_ib_ctl_IO, dec.dec_dec_ctl, include.el2_mul_pkt_t, include.el2_trace_pkt_t, include.el2_predict_pkt_t, lib.rvrangecheck, lib.rvdffsc, lib.rveven_paritygen, ifu.el2_ifu, dec.el2_dec_timer_ctl_IO, include.el2_div_pkt_t)
-[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dbg/el2_dbg.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/el2_pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/rvjtag_tap.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_jtag_to_core_sync.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lsu/el2_lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/ifu/el2_ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/beh_lib.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/test.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_tlu_ctl.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/include/el2_bundle.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala, /home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/el2_lib.scala)
-[debug] Initial set of included nodes: dec.el2_dec_decode_csr_read_IO, dec.test, include.el2_reg_pkt_t, dec.el2_dec, dmi.rvjtag_tap, include.el2_cache_debug_pkt_t, dec.el2_dec_ib_ctl, dmi.dmi_jtag_to_core_sync, lib.rvecc_decode_64, include.el2_ccm_ext_in_pkt_t, el2_pic_ctrl, include.el2_dest_pkt_t, dec.el2_dec_gpr_ctl_IO, include.el2_trigger_pkt_t, lib.param, exu.el2_exu_alu_ctl, include.el2_lsu_pkt_t, lib.rvecc_decode, dec.el2_dec_tlu_ctl, dec.el2_dec_tlu_ctl_IO, include.el2_br_tlu_pkt_t, dmi.dmi_wrapper, lib.rvdffs, dec.gpr_gen, lib.el2_lib.rvclkhdr, include.el2_lsu_error_pkt_t, include.el2_class_pkt_t, lib.rvlsadder, exu.alu, lib.el2_lib.rvecc_encode_64, lib.rvsyncss, lib.rvecc_decode_64.rvsyncss, include.el2_ic_tag_ext_in_pkt_t, lib.rvtwoscomp, include.el2_dec_pkt_t, lib.rvdff, dec.csr_tlu, include.el2_rets_pkt_t, dec.el2_CSR_IO, dec.el2_dec_timer_ctl, dec.tlu_gen, dec.CSRs, dec.ib_gen, dec.dec_decode, lsu.el2_lsu, dec.el2_dec_trigger, lib.rvmaskandmatch, dec.dec_main, lib.rveven_paritycheck, dec.dec_trig, dbg.el2_dbg, include.el2_ic_data_ext_in_pkt_t, include.el2_br_pkt_t, exu.el2_exu, include.el2_dccm_ext_in_pkt_t, lib.el2_lib.rvsyncss, lib.el2_lib.rvecc_encode, lib.rvbsadder, lib.el2_lib.gated_latch, include.el2_alu_pkt_t, lib.rvecc_encode_64, include.el2_inst_pkt_t, pic_main, include.el2_load_cam_pkt_t, lib.rvecc_encode, dec.el2_dec_dec_ctl, include.el2_dec_tlu_csr_pkt, lib.el2_lib, dec.el2_dec_IO, dec.CSR_VAL, include.el2_trap_pkt_t, dec.el2_dec_decode_ctl, lib.el2_lib.rvdffe, dec.el2_dec_decode_csr_read, dec.el2_dec_gpr_ctl, dec.el2_dec_ib_ctl_IO, dec.dec_dec_ctl, include.el2_mul_pkt_t, include.el2_trace_pkt_t, include.el2_predict_pkt_t, lib.rvrangecheck, lib.rvdffsc, lib.rveven_paritygen, ifu.el2_ifu, dec.el2_dec_timer_ctl_IO, include.el2_div_pkt_t
-[debug] Including lib.el2_lib by lib.param
-[debug] Including exu.el2_exu_alu_ctl by lib.el2_lib
-[debug] Including dec.el2_dec_tlu_ctl by lib.el2_lib
-[debug] Including dec.el2_dec_tlu_ctl_IO by lib.el2_lib
-[debug] Including lib.rvdffs by lib.el2_lib
-[debug] Including dec.csr_tlu by lib.el2_lib
-[debug] Including dec.el2_CSR_IO by lib.el2_lib
-[debug] Including dec.el2_dec_timer_ctl by lib.el2_lib
-[debug] Including dec.el2_dec_trigger by lib.el2_lib
-[debug] Including dec.el2_dec_dec_ctl by lib.el2_lib
-[debug] Including dec.el2_dec_IO by lib.el2_lib
-[debug] Including dec.el2_dec_decode_ctl by lib.el2_lib
-[debug] Including dec.el2_dec_gpr_ctl by lib.el2_lib
-[debug] Including lib.rvdffsc by lib.el2_lib
-[debug] Including dec.el2_dec_ib_ctl_IO by lib.param
+[debug] All initially invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl)
+[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala)
+[debug] Initial set of included nodes: include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, include.dec_alu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.aln_dec, include.lsu_exu, dbg.state_t, include.lsu_tlu, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lib.Config, lsu.lsu_bus_buffer, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, include.br_pkt_t, dec.CSR_VAL, include.cache_debug_pkt_t, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, snapshot.pt, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl
+[debug] Including dec.dec by lib.param
+[debug] Including dec.dec_ib_ctl_IO by lib.param
+[debug] Including lsu.lsu by lib.param
+[debug] Including dec.dec_ib_ctl by lib.param
+[debug] Including lib.lib by lib.param
+[debug] Including exu.exu by lib.lib
+[debug] Including lsu.lsu_trigger by lib.lib
+[debug] Including dec.dec_gpr_ctl by lib.lib
+[debug] Including lsu.lsu_addrcheck by lib.lib
+[debug] Including mem.quasar by lib.lib
+[debug] Including ifu.ifu by lib.lib
+[debug] Including include.aln_ib by lib.lib
+[debug] Including dec.dec_tlu_ctl_IO by lib.lib
+[debug] Including exu.exu_div_ctl by lib.lib
+[debug] Including dec.dec_tlu_ctl by lib.lib
+[debug] Including lib.ahb_to_axi4 by lib.lib
+[debug] Including lib.axi4_to_ahb by lib.lib
+[debug] Including quasar by lib.lib
+[debug] Including dec.csr_tlu by lib.lib
+[debug] Including lsu.lsu_lsc_ctl by lib.lib
+[debug] Including pic_ctrl by lib.lib
+[debug] Including include.write_data by lib.lib
+[debug] Including exu.exu_alu_ctl by lib.lib
+[debug] Including include.tlu_exu by lib.lib
+[debug] Including dec.dec_IO by lib.lib
+[debug] Including include.iccm_mem by lib.lib
+[debug] Including quasar_bundle by lib.lib
+[debug] Including lsu.lsu_ecc by lib.lib
+[debug] Including mem.blackbox_mem by lib.lib
+[debug] Including include.write_addr by lib.lib
+[debug] Including ifu.mem_ctl_io by lib.lib
+[debug] Including lsu.lsu_bus_buffer by lib.lib
+[debug] Including quasar_wrapper by lib.lib
+[debug] Including include.write_resp by lib.lib
+[debug] Including dec.CSR_IO by lib.lib
+[debug] Including dec.dec_timer_ctl by lib.lib
+[debug] Including include.dec_exu by lib.lib
+[debug] Including include.read_data by lib.lib
+[debug] Including ifu.ifu_aln_ctl by lib.lib
+[debug] Including dbg.dbg by lib.lib
+[debug] Including include.ic_mem by lib.lib
+[debug] Including lsu.lsu_bus_intf by lib.lib
+[debug] Including exu.exu_mul_ctl by lib.lib
+[debug] Including dec.dec_trigger by lib.lib
+[debug] Including lsu.lsu_dccm_ctl by lib.lib
+[debug] Including ifu.ifu_compress_ctl by lib.lib
+[debug] Including ifu.ifu_bp_ctl by lib.lib
+[debug] Including mem.Mem_bundle by lib.lib
+[debug] Including include.dctl_busbuff by lib.lib
+[debug] Including include.read_addr by lib.lib
+[debug] Including include.axi_channels by lib.lib
+[debug] Including dec.dec_dec_ctl by lib.lib
+[debug] Including lsu.lsu_stbuf by lib.lib
+[debug] Including mem.mem_lsu by lib.lib
+[debug] Including include.dec_mem_ctrl by lib.lib
+[debug] Including ifu.ifu_mem_ctl by lib.lib
+[debug] Including ifu.ifu_ifc_ctl by lib.lib
+[debug] Including include.decode_exu by lib.lib
+[debug] Including dma_ctrl by lib.lib
 [debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources
-[info] Compiling 40 Scala sources to /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes ...
+[info] Compiling 39 Scala sources to /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes ...
 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
-[debug] [zinc] Running cached compiler bea4c5c for Scala compiler version 2.12.10
+[debug] [zinc] Running cached compiler 1544a576 for Scala compiler version 2.12.10
 [debug] [zinc] The Scala compiler is invoked with:
 [debug] 	-Xsource:2.11
 [debug] 	-Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar
@@ -42,666 +86,418 @@
 [debug] 	/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar
 [debug] 	-classpath
 [debug] 	/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
-[debug] Scala compilation took 90.990714822 s
+[debug] Scala compilation took 42.644386776 s
 [debug] Done compiling.
-[debug] Invalidating (transitively) by inheritance from include.dma_mem_ctl...
-[debug] Initial set of included nodes: include.dma_mem_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(include.dma_mem_ctl)
-[debug] The following member ref dependencies of include.dma_mem_ctl are invalidated:
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] Change NamesChange(include.dma_mem_ctl,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(dma_mem_ctl,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dma_mem_tag,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(dma_mem_sz,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(include;dma_mem_ctl;init;,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dma_mem_addr,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dma_mem_wdata,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(dma_iccm_req,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(dma_mem_write,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.dma_mem_ctl has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dma_mem_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_mem_ctl, ifu.mem_ctl_io, dma_ctrl, ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from mem.mem_lsu...
-[debug] Initial set of included nodes: mem.mem_lsu
-[debug] Invalidated by transitive inheritance dependency: Set(mem.mem_lsu)
-[debug] The following member ref dependencies of mem.mem_lsu are invalidated:
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_dccm_ctl
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(mem.mem_lsu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(rden,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(rd_addr_hi,[Default]), UsedName(wr_data_lo,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(mem_lsu,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(wren,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(wr_addr_lo,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(rd_data_lo,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(rd_addr_lo,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(rd_data_hi,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(mem;mem_lsu;init;,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(wr_data_hi,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(wr_addr_hi,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The mem.mem_lsu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(mem.mem_lsu)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, quasar, quasar_bundle, quasar_wrapper, lsu.lsu_dccm_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_trigger...
-[debug] Initial set of included nodes: dec.el2_dec_trigger
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_trigger)
-[debug] Change NamesChange(dec.el2_dec_trigger,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(dec;el2_dec_trigger;init;,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(dec_i0_match_data,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(el2_dec_trigger,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_trigger has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_trigger)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_decode...
-[debug] Initial set of included nodes: dec.dec_decode
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode)
-[debug] Change NamesChange(dec.dec_decode,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(dec_decode,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.dec_decode has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(dec_decode,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec_decode)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from pic_ctrl...
-[debug] Initial set of included nodes: pic_ctrl
-[debug] Invalidated by transitive inheritance dependency: Set(pic_ctrl)
-[debug] The following member ref dependencies of pic_ctrl are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(pic_ctrl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_pic,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(EXT_INTR_GW_CLEAR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(picm_rden_ff,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(intpriority_reg_read,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(mhwakeup_in,[Default]), UsedName(free_clk,[Default]), UsedName(l2_intpend_id_ff,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(addr_intpend_base_match,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(intenable_reg_we,[Default]), UsedName(repl,[Default]), UsedName(prithresh_reg_read,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(intpend_reg_extended,[Default]), UsedName(pic_ctrl,[Default]), UsedName(extintsrc_req_sync,[Default]), UsedName(picm_bypass_ff,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(lsu_pic,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(intpriority_reg_we,[Default]), UsedName(picm_wren_ff,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(pic_raddr_c1_clken,[Default]), UsedName(INTPRIORITY_BASE_ADDR,[Default]), UsedName(picm_waddr_ff,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(picm_wr_data_ff,[Default]), UsedName(picm_raddr_ff,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mexintpend_in,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(intpriority_reg_re,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(intpend_reg_read,[Default]), UsedName(getChiselPorts,[Default]), UsedName(meipt_inv,[Default]), UsedName(synchronized,[Default]), UsedName(addr_clear_gw_base_match,[Default]), UsedName(intenable_reg,[Default]), UsedName(getPorts,[Default]), UsedName(INTPEND_BASE_ADDR,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(raddr_config_pic_match,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(pl_in,[Default]), UsedName(INTPEND_SIZE,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(intpriority_reg,[Default]), UsedName(pic_data_c1_clk,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(config_reg_re,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(prithresh_reg_write,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(gw_config_reg,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(levelx_intpend_id,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(gw_config_reg_we,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(levelx_intpend_w_prior_en,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(pic_raddr_c1_clk,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(gw_config_rd_out,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(selected_int_priority,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(waddr_config_pic_match,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(gw_config_reg_re,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(config_reg,[Default]), UsedName(generateComponent,[Default]), UsedName(intpend_w_prior_en,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(meicurpl_inv,[Default]), UsedName(pic_int_c1_clk,[Default]), UsedName(raddr_config_gw_base_match,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(pic_pri_c1_clken,[Default]), UsedName(rvrangecheck,[Default]), UsedName(intenable_reg_read,[Default]), UsedName(finalize,[Default]), UsedName(picm_mken_ff,[Default]), UsedName(gw_config_c1_clk,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(address,[Default]), UsedName(asInstanceOf,[Default]), UsedName(pl_in_q,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(waddr_intenable_base_match,[Default]), UsedName(intenable_rd_out,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(intpriority_rd_out,[Default]), UsedName(intpriority_reg_inv,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(mask,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(intpend_rd_part_out,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(gw_clear_reg_we,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(intenable_reg_re,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(INT_GRPS,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(EXT_INTR_PIC_CONFIG,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(pic_data_c1_clken,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(gw_config_c1_clken,[Default]), UsedName(INTENABLE_BASE_ADDR,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(raddr_intenable_base_match,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(config_reg_in,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(maxint,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(waddr_intpriority_base_match,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ID_BITS,[Default]), UsedName(extintsrc_req,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(GW_CONFIG,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(extintsrc_req_gw,[Default]), UsedName(claimid_in,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(intpriord,[Default]), UsedName(gw_config_reg_read,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(config_reg_we,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(l2_intpend_w_prior_en_ff,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(pic_int_c1_clken,[Default]), UsedName(pic_ctrl;init;,[Default]), UsedName(INTPRIORITY_BITS,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(picm_rd_data_in,[Default]), UsedName(EXT_INTR_GW_CONFIG,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(cmp_and_mux,[Default]), UsedName(intpend_id,[Default]), UsedName(temp_raddr_intenable_base_match,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(pic_pri_c1_clk,[Default]), UsedName(waddr_config_gw_base_match,[Default]), UsedName(raddr_intpriority_base_match,[Default]), UsedName(active_clk,[Default]), UsedName(NUM_LEVELS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(intpend_rd_out,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]))) invalidates 2 classes due to The pic_ctrl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(pic_ctrl)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_cache_debug_pkt_t...
-[debug] Initial set of included nodes: include.el2_cache_debug_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_cache_debug_pkt_t)
-[debug] Change NamesChange(include.el2_cache_debug_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(include;el2_cache_debug_pkt_t;init;,[Default]), UsedName(forceName,[Default]), UsedName(el2_cache_debug_pkt_t,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(icache_dicawics,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(icache_wrdata,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(icache_rd_valid,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(icache_wr_valid,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_cache_debug_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_cache_debug_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.trap_pkt_t...
-[debug] Initial set of included nodes: include.trap_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.trap_pkt_t)
-[debug] The following member ref dependencies of include.trap_pkt_t are invalidated:
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] Change NamesChange(include.trap_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(icaf_type,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(icaf,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(include;trap_pkt_t;init;,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(pmu_divide,[Default]), UsedName($isInstanceOf,[Default]), UsedName(icaf_f1,[Default]), UsedName(i0trigger,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(fence_i,[Default]), UsedName(pmu_i0_br_unpred,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pmu_i0_itype,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(pmu_lsu_misaligned,[Default]), UsedName(_id,[Default]), UsedName(trap_pkt_t,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 7 classes due to The include.trap_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.trap_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_decode_ctl, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, dec.csr_tlu, dec.CSR_IO)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvtwoscomp...
-[debug] Initial set of included nodes: lib.rvtwoscomp
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvtwoscomp)
-[debug] Change NamesChange(lib.rvtwoscomp,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(i,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(lib;rvtwoscomp;init;,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(temp,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvtwoscomp has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(i,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(lib;rvtwoscomp;init;,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(temp,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvtwoscomp)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_tlu_ctl_IO...
-[debug] Initial set of included nodes: dec.el2_dec_tlu_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_tlu_ctl_IO)
-[debug] Change NamesChange(dec.el2_dec_tlu_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(exu_pmu_i0_br_ataken,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_tlu_i0_kill_writeb_wb,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(exu_i0_br_mp_r,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(dec_tlu_meicurpl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(pic_claimid,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(o_cpu_halt_ack,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dec_tlu_presync_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(ifu_pmu_bus_error,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(dec_dbg_cmd_done,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(exu_npc_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(exu_pmu_i0_pc4,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(exu_pmu_i0_br_misp,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(dec_tlu_sideeffect_posted_disable,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(dec_tlu_ic_diag_pkt,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(ifu_ic_error_start,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(dec_pause_state,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ifu_pmu_ic_hit,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(dec_div_active,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(lsu_pmu_bus_busy,[Default]), UsedName(dma_pmu_dccm_read,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(dec_tlu_resume_ack,[Default]), UsedName(ifu_pmu_fetch_stall,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(dec_tlu_flush_leak_one_r,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(exu_i0_br_error_r,[Default]), UsedName(dec_csr_legal_d,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(dec_tlu_debug_stall,[Default]), UsedName(exu_i0_br_start_error_r,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(dec_tlu_dec_clk_override,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(dbg_resume_req,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(dma_pmu_dccm_write,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(lsu_pmu_bus_trxn,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(mhwakeup,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_dma_qos_prty,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(dec_dbg_cmd_fail,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(exu_i0_br_middle_r,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(dec_tlu_external_ldfwd_disable,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(ifu_iccm_rd_ecc_single_err,[Default]), UsedName(exu_i0_br_way_r,[Default]), UsedName(dec_tlu_br0_r_pkt,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(lsu_fastint_stall_any,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(exu_i0_br_hist_r,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(ifu_ic_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(ifu_pmu_bus_trxn,[Default]), UsedName(exu_i0_br_valid_r,[Default]), UsedName(dec_tlu_flush_pause_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(dbg_halt_req,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(dec_tlu_postsync_d,[Default]), UsedName(dec_tlu_i0_commit_cmt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(ifu_ic_debug_rd_data_valid,[Default]), UsedName(compileOptions,[Implicit]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dec_tlu_flush_noredir_r,[Default]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_tlu_wb_coalescing_disable,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(widthOption,[Default]), UsedName(mexintpend,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(el2_dec_tlu_ctl_IO,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(dec_tlu_bpred_disable,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(pic_pl,[Default]), UsedName(lsu_pmu_bus_misaligned,[Default]), UsedName(dma_pmu_any_write,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(dec_tlu_fence_i_r,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(dma_pmu_any_read,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(ifu_miss_state_idle,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(dec_tlu_mpc_halted_only,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(dec_tlu_flush_path_r,[Default]), UsedName(_id,[Default]), UsedName(dec_tlu_flush_err_r,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(dec_tlu_meipt,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(lsu_pmu_bus_error,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(lsu_imprecise_error_store_any,[Default]), UsedName(ifu_pmu_bus_busy,[Default]), UsedName(ifu_pmu_ic_miss,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_imprecise_error_load_any,[Default]), UsedName(lsu_pmu_load_external_m,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(dec_tlu_meihap,[Default]), UsedName(dec;el2_dec_tlu_ctl_IO;init;,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(dec_tlu_debug_mode,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(lsu_imprecise_error_addr_any,[Default]), UsedName(nmi_vec,[Default]), UsedName(dec_tlu_flush_extint,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(lsu_pmu_store_external_m,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_tlu_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_tlu_ctl_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from mem.quasar...
-[debug] Initial set of included nodes: mem.quasar
-[debug] Invalidated by transitive inheritance dependency: Set(mem.quasar)
-[debug] The following member ref dependencies of mem.quasar are invalidated:
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(mem.quasar,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(quasar,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(int2boolean,[Implicit]), UsedName(mem,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(getClass,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The mem.quasar has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(mem.quasar)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar_wrapper)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_IO...
-[debug] Initial set of included nodes: dec.el2_dec_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_IO)
-[debug] Change NamesChange(dec.el2_dec_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(exu_pmu_i0_br_ataken,[Default]), UsedName(rv_trace_pkt,[Default]), UsedName(lsu_nonblock_load_data,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_i0_rs2_bypass_en_d,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(exu_i0_br_mp_r,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(i0_predict_fghr_d,[Default]), UsedName(dbg_cmd_write,[Default]), UsedName(dec_tlu_meicurpl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(i0_predict_index_d,[Default]), UsedName(free_clk,[Default]), UsedName(exu_csr_rs1_x,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(i0_predict_btag_d,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(pic_claimid,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(dec_dbg_rddata,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(dec_i0_select_pc_d,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(o_cpu_halt_ack,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ifu_i0_bp_fghr,[Default]), UsedName(ifu_i0_bp_btag,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(dec_div_cancel,[Default]), UsedName(ifu_pmu_bus_error,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(dec_dbg_cmd_done,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(lsu_nonblock_load_data_error,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(exu_npc_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(dec_csr_ren_d,[Default]), UsedName(isSynthesizable,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(bind,[Default]), UsedName(exu_pmu_i0_pc4,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(exu_pmu_i0_br_misp,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(dec_tlu_sideeffect_posted_disable,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(dec_i0_alu_decode_d,[Default]), UsedName(dec_i0_rs1_bypass_data_d,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(dec_tlu_ic_diag_pkt,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(exu_i0_result_x,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_predict_p_d,[Default]), UsedName(ifu_ic_error_start,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ifu_pmu_ic_hit,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_pause_state_cg,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(i0_brp,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(lsu_nonblock_load_inv_r,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(dec_i0_immed_d,[Default]), UsedName(lsu_nonblock_load_data_tag,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(pred_correct_npc_x,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(lsu_pmu_bus_busy,[Default]), UsedName(dma_pmu_dccm_read,[Default]), UsedName(ifu_i0_pc4,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(dec_tlu_resume_ack,[Default]), UsedName(ifu_pmu_fetch_stall,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(dec_tlu_flush_leak_one_r,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(ifu_i0_icaf_f1,[Default]), UsedName(exu_i0_br_error_r,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(exu_i0_br_start_error_r,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(ifu_i0_icaf_type,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(gpr_i0_rs2_d,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(dbg_resume_req,[Default]), UsedName(el2_dec_IO,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_i0_rs2_en_d,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(dec_i0_rs2_bypass_data_d,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dec_data_en,[Default]), UsedName(exu_i0_pc_x,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(i0_ap,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(dma_pmu_dccm_write,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(lsu_pmu_bus_trxn,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(mhwakeup,[Default]), UsedName(flatten,[Default]), UsedName(exu_div_result,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_dma_qos_prty,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(dec_dbg_cmd_fail,[Default]), UsedName(gpr_i0_rs1_d,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(ifu_i0_cinst,[Default]), UsedName(exu_i0_br_middle_r,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(dec;el2_dec_IO;init;,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(dec_tlu_external_ldfwd_disable,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(dbg_cmd_type,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(ifu_iccm_rd_ecc_single_err,[Default]), UsedName(exu_i0_br_way_r,[Default]), UsedName(dec_tlu_br0_r_pkt,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(lsu_nonblock_load_valid_m,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(lsu_fastint_stall_any,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(exu_i0_br_hist_r,[Default]), UsedName(ifu_i0_dbecc,[Default]), UsedName(direction_=,[Default]), UsedName(dec_ctl_en,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(dec_i0_br_immed_d,[Default]), UsedName(badConnect,[Default]), UsedName(lsu_nonblock_load_inv_tag_r,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(ifu_ic_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(ifu_i0_bp_index,[Default]), UsedName(ifu_pmu_bus_trxn,[Default]), UsedName(exu_i0_br_valid_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ifu_i0_pc,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(dbg_halt_req,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(dec_tlu_i0_commit_cmt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(ifu_ic_debug_rd_data_valid,[Default]), UsedName(lsu_load_stall_any,[Default]), UsedName(compileOptions,[Implicit]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dbg_cmd_valid,[Default]), UsedName(dec_tlu_flush_noredir_r,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(dec_i0_rs1_en_d,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_tlu_wb_coalescing_disable,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(dec_debug_wdata_rs1_d,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(widthOption,[Default]), UsedName(mul_p,[Default]), UsedName(mexintpend,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(dec_tlu_bpred_disable,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(dec_extint_stall,[Default]), UsedName(lsu_nonblock_load_tag_m,[Default]), UsedName(ifu_i0_instr,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(pic_pl,[Default]), UsedName(lsu_pmu_bus_misaligned,[Default]), UsedName(dma_pmu_any_write,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(dec_tlu_fence_i_r,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(dma_pmu_any_read,[Default]), UsedName(suggestName,[Default]), UsedName(lsu_nonblock_load_data_valid,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(ifu_miss_state_idle,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ifu_i0_valid,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(dec_tlu_mpc_halted_only,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(dec_tlu_flush_path_r,[Default]), UsedName(_id,[Default]), UsedName(dec_tlu_flush_err_r,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(dec_i0_rs1_bypass_en_d,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(dec_tlu_meipt,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(lsu_pmu_misaligned_m,[Default]), UsedName(lsu_pmu_bus_error,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(lsu_imprecise_error_store_any,[Default]), UsedName(ifu_pmu_bus_busy,[Default]), UsedName(dbg_cmd_addr,[Default]), UsedName(ifu_pmu_ic_miss,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_imprecise_error_load_any,[Default]), UsedName(lsu_pmu_load_external_m,[Default]), UsedName(active_clk,[Default]), UsedName(dec_tlu_meihap,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(dec_tlu_debug_mode,[Default]), UsedName(suggestedName,[Default]), UsedName(ifu_i0_icaf,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(lsu_imprecise_error_addr_any,[Default]), UsedName(nmi_vec,[Default]), UsedName(dbg_cmd_wrdata,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(div_p,[Default]), UsedName(lsu_pmu_store_external_m,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_IO has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.rvsyncss...
-[debug] Initial set of included nodes: lib.el2_lib.rvsyncss
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.rvsyncss)
-[debug] Change NamesChange(lib.el2_lib.rvsyncss,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.rvsyncss has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.rvsyncss)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu...
-[debug] Initial set of included nodes: lsu.lsu
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu)
-[debug] The following member ref dependencies of lsu.lsu are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(lsu.lsu,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(lsu_lsc_ctl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(ecc,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(lsu_pic,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(dma_dccm_wdata_lo,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_tlu,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(clkdomain,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(dma_dccm_wdata,[Default]), UsedName(IO,[Default]), UsedName(dma_mem_tag_m,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(axi,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(flush_r,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dma_dccm_wdata_hi,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(trigger,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(stbuf,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(lsu_cmpen_m,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(lsu_raw_fwd_hi_r,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(dccm_ctl,[Default]), UsedName(addPostnameHook,[Default]), UsedName(store_stbuf_reqvld_r,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(lsu_raw_fwd_lo_r,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(lsu_raw_fwd_lo_m,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_dec,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu;lsu;init;,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(flush_m_up,[Default]), UsedName(clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dma_mem_tag_d,[Default]), UsedName(bus_intf,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(lsu_fastint_stall_any,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(lsu_load_stall_any,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(lsu_busreq_m,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(lsu_exu,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(lsu_raw_fwd_hi_m,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(dccm,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(dma_pic_wen,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ldst_nodma_mtor,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(isClosed,[Default]), UsedName(lsu_pmu_misaligned_m,[Default]), UsedName(lsu,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_dma,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(dma_dccm_wen,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_ib_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_ib_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_ib_ctl)
-[debug] Change NamesChange(dec.el2_dec_ib_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(ib0_debug_in,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec;el2_dec_ib_ctl;init;,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(el2_dec_ib_ctl,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(debug_read_csr,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(debug_valid,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(debug_write,[Default]), UsedName(dreg,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(debug_read_gpr,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(debug_read,[Default]), UsedName(debug_write_csr,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(debug_write_gpr,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_ib_ctl has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(ib0_debug_in,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec;el2_dec_ib_ctl;init;,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(el2_dec_ib_ctl,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(debug_read_csr,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(debug_valid,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(debug_write,[Default]), UsedName(dreg,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(debug_read_gpr,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(debug_read,[Default]), UsedName(debug_write_csr,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(debug_write_gpr,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_ib_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_trigger...
-[debug] Initial set of included nodes: dec.dec_trigger
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_trigger)
-[debug] The following member ref dependencies of dec.dec_trigger are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_trigger,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(dec_i0_match_data,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec_trigger,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dec;dec_trigger;init;,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dec.dec_trigger has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_trigger)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.ifu_dma...
-[debug] Initial set of included nodes: include.ifu_dma
-[debug] Invalidated by transitive inheritance dependency: Set(include.ifu_dma)
-[debug] The following member ref dependencies of include.ifu_dma are invalidated:
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu
-[debug] 	quasar
-[debug] Change NamesChange(include.ifu_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(include;ifu_dma;init;,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(dma_mem_ctl,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(ifu_dma,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(dma_ifc,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.ifu_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ifu_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(dma_ctrl, ifu.ifu, quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.mem_ctl_io...
-[debug] Initial set of included nodes: ifu.mem_ctl_io
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.mem_ctl_io)
-[debug] The following member ref dependencies of ifu.mem_ctl_io are invalidated:
-[debug] 	ifu.ifu
-[debug] Change NamesChange(ifu.mem_ctl_io,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ic_hit_f,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(iccm_dma_ecc_error,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ifu_fetch_val,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(iccm_dma_rtag,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(mem_ctl_io,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(iccm,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(iccm_ready,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(dma_mem_ctl,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ic_data_f,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(iccm_dma_rdata,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(dec_mem_ctrl,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(ifc_iccm_access_bf,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(ic_dma_active,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(ic_access_fault_f,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ic_fetch_val_f,[Default]), UsedName(iccm_dma_rvalid,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ifu_bp_hit_taken_f,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(ifc_fetch_req_bf,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ifu_bp_inst_mask_f,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ifu_async_error_start,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(ifu_axi,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(ic_write_stall,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(ifc_fetch_addr_bf,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(ic,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(ifu;mem_ctl_io;init;,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(ifc_region_acc_fault_bf,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ifc_dma_access_ok,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(iccm_rd_ecc_double_err,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ifu_ic_mb_empty,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(ic_access_fault_type_f,[Default]), UsedName(ifc_fetch_req_bf_raw,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ifc_fetch_uncacheable_bf,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ifu_bus_clk_en,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(active_clk,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The ifu.mem_ctl_io has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.mem_ctl_io)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_alu_pkt_t...
-[debug] Initial set of included nodes: include.el2_alu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_alu_pkt_t)
-[debug] Change NamesChange(include.el2_alu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(add,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(predict_nt,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(predict_t,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(slt,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(include;el2_alu_pkt_t;init;,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(beq,[Default]), UsedName(lor,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(sll,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(srl,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(sra,[Default]), UsedName(_parent,[Default]), UsedName(jal,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(el2_alu_pkt_t,[Default]), UsedName(land,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(bge,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(blt,[Default]), UsedName(_makeLit,[Default]), UsedName(bne,[Default]), UsedName(notify,[Default]), UsedName(csr_write,[Default]), UsedName(csr_imm,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lxor,[Default]), UsedName(toTarget,[Default]), UsedName(sub,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_alu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_alu_pkt_t)
+[debug] Invalidating (transitively) by inheritance from exu.exu_alu_ctl...
+[debug] Initial set of included nodes: exu.exu_alu_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_alu_ctl)
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(exu.exu_alu_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu_alu_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(exu.exu_alu_ctl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
 [debug] Invalidating (transitively) by inheritance from include.write_resp...
 [debug] Initial set of included nodes: include.write_resp
 [debug] Invalidated by transitive inheritance dependency: Set(include.write_resp)
-[debug] The following member ref dependencies of include.write_resp are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] Change NamesChange(include.write_resp,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(write_resp,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(resp,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(include;write_resp;init;,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(<init>$default$1,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(id,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.write_resp has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
+[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(write_resp,[Default]))
+[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ne,[Default]), UsedName(write_resp,[Default]))
+[debug] Change NamesChange(include.write_resp,ModifiedNames(changes = UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(include;write_resp;init;,[Default]), UsedName(<init>$default$1,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 5 classes due to The include.write_resp has the following regular definitions changed:
+[debug] 	UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(include;write_resp;init;,[Default]), UsedName(<init>$default$1,[Default]), UsedName(write_resp,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]).
 [debug] 	> by transitive inheritance: Set(include.write_resp)
 [debug] 	> 
-[debug] 	> by member reference: Set(dbg.dbg, lsu.lsu_bus_buffer, dma_ctrl, quasar)
+[debug] 	> by member reference: Set(dbg.dbg, lsu.lsu_bus_buffer, lib.axi4_to_ahb, dma_ctrl)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.tlu_busbuff...
-[debug] Initial set of included nodes: include.tlu_busbuff
-[debug] Invalidated by transitive inheritance dependency: Set(include.tlu_busbuff)
-[debug] The following member ref dependencies of include.tlu_busbuff are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] Change NamesChange(include.tlu_busbuff,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(dec_tlu_sideeffect_posted_disable,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(lsu_pmu_bus_busy,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(lsu_pmu_bus_trxn,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dec_tlu_external_ldfwd_disable,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_tlu_wb_coalescing_disable,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(lsu_pmu_bus_misaligned,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(tlu_busbuff,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(lsu_pmu_bus_error,[Default]), UsedName(include;tlu_busbuff;init;,[Default]), UsedName(lsu_imprecise_error_store_any,[Default]), UsedName(lsu_imprecise_error_load_any,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lsu_imprecise_error_addr_any,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 7 classes due to The include.tlu_busbuff has the following implicit definitions changed:
+[debug] Invalidating (transitively) by inheritance from ifu.ifu_mem_ctl...
+[debug] Initial set of included nodes: ifu.ifu_mem_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_mem_ctl)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu_mem_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_mem_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.ifu_mem_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_decode_ctl...
+[debug] Initial set of included nodes: dec.dec_decode_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode_ctl)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_decode_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_decode_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_decode_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.ahb_channel...
+[debug] Initial set of included nodes: include.ahb_channel
+[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_channel)
+[debug] The following member ref dependencies of include.ahb_channel are invalidated:
+[debug] 	lib.ahb_to_axi4
+[debug] 	lib.axi4_to_ahb
+[debug] 	lib.axi4_to_ahb_IO
+[debug] 	lib.lib
+[debug] 	quasar
+[debug] 	quasar_bundle
+[debug] 	quasar_wrapper
+[debug] Change NamesChange(include.ahb_channel,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(out,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(include;ahb_channel;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(ahb_channel,[Default]), UsedName(:=,[Default]), UsedName(in,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(toNamed,[Default]), UsedName(badConnect,[Default]))) invalidates 8 classes due to The include.ahb_channel has the following implicit definitions changed:
 [debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.tlu_busbuff)
+[debug] 	> by transitive inheritance: Set(include.ahb_channel)
 [debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_tlu_ctl_IO, lsu.lsu, dec.dec_tlu_ctl, lsu.lsu_bus_buffer, lsu.lsu_bus_intf)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dctl_dma...
-[debug] Initial set of included nodes: include.dctl_dma
-[debug] Invalidated by transitive inheritance dependency: Set(include.dctl_dma)
-[debug] The following member ref dependencies of include.dctl_dma are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	dma_ctrl
-[debug] Change NamesChange(include.dctl_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(include;dctl_dma;init;,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dctl_dma,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.dctl_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dctl_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(dma_ctrl, dec.dec, dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.predict_pkt_t...
-[debug] Initial set of included nodes: include.predict_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.predict_pkt_t)
-[debug] The following member ref dependencies of include.predict_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] 	exu.exu_alu_ctl
-[debug] 	ifu.ifu_bp_ctl
-[debug] Change NamesChange(include.predict_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(toffset,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(boffset,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(pret,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(predict_pkt_t,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(prett,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(pja,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(ataken,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(pc4,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(include;predict_pkt_t;init;,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(misp,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(pcall,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.predict_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.predict_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_alu_ctl, ifu.ifu_bp_ctl, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_ib_ctl...
-[debug] Initial set of included nodes: dec.dec_ib_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_ib_ctl)
-[debug] The following modified names cause invalidation of dec.dec: Set(UsedName(dec_ib_ctl,[Default]), UsedName(dec;dec_ib_ctl;init;,[Default]), UsedName(IO,[Default]), UsedName(io,[Default]))
-[debug] Change NamesChange(dec.dec_ib_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(ib0_debug_in,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(dec_ib_ctl,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(dec;dec_ib_ctl;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(debug_read_csr,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(debug_valid,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(debug_write,[Default]), UsedName(dreg,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(debug_read_gpr,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(debug_read,[Default]), UsedName(debug_write_csr,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(debug_write_gpr,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dec.dec_ib_ctl has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(ib0_debug_in,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(dec_ib_ctl,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(dec;dec_ib_ctl;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(debug_read_csr,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(debug_valid,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(debug_write,[Default]), UsedName(dreg,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(debug_read_gpr,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(debug_read,[Default]), UsedName(debug_write_csr,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(debug_write_gpr,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec_ib_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
+[debug] 	> by member reference: Set(lib.axi4_to_ahb_IO, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, quasar_bundle, quasar_wrapper, lib.lib)
 [debug]         
 [debug] Invalidating (transitively) by inheritance from include.read_addr...
 [debug] Initial set of included nodes: include.read_addr
 [debug] Invalidated by transitive inheritance dependency: Set(include.read_addr)
-[debug] The following member ref dependencies of include.read_addr are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] Change NamesChange(include.read_addr,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(size,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(qos,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(prot,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(len,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(burst,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(addr,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(include;read_addr;init;,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(lock,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(read_addr,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(<init>$default$1,[Default]), UsedName(cache,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(region,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(id,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.read_addr has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
+[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(read_addr,[Default]))
+[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(read_addr,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(read_addr,[Default]), UsedName(ne,[Default]))
+[debug] Change NamesChange(include.read_addr,ModifiedNames(changes = UsedName(include;read_addr;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(read_addr,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.read_addr has the following regular definitions changed:
+[debug] 	UsedName(include;read_addr;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(read_addr,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]).
 [debug] 	> by transitive inheritance: Set(include.read_addr)
 [debug] 	> 
-[debug] 	> by member reference: Set(quasar, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
+[debug] 	> by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.br_pkt_t...
-[debug] Initial set of included nodes: include.br_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.br_pkt_t)
-[debug] The following member ref dependencies of include.br_pkt_t are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	dec.dec_ib_ctl
-[debug] 	dec.dec_ib_ctl_IO
-[debug] 	ifu.ifu_aln_ctl
-[debug] Change NamesChange(include.br_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(toffset,[Default]), UsedName(ret,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(prett,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(br_pkt_t,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(bank,[Default]), UsedName(include;br_pkt_t;init;,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.br_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.br_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_decode_ctl, dec.dec_ib_ctl_IO, ifu.ifu_aln_ctl, dec.dec_ib_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_decode_csr_read...
-[debug] Initial set of included nodes: dec.dec_decode_csr_read
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode_csr_read)
-[debug] Change NamesChange(dec.dec_decode_csr_read,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(pattern,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(dec_decode_csr_read,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(dec;dec_decode_csr_read;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.dec_decode_csr_read has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(pattern,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(dec_decode_csr_read,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(dec;dec_decode_csr_read;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec_decode_csr_read)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_timer_ctl_IO...
-[debug] Initial set of included nodes: dec.el2_dec_timer_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_timer_ctl_IO)
-[debug] Change NamesChange(dec.el2_dec_timer_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(free_clk,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(internal_dbg_halt_timers,[Default]), UsedName(asUInt,[Default]), UsedName(csr_mitctl1,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dec;el2_dec_timer_ctl_IO;init;,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(bind,[Default]), UsedName(csr_mitb0,[Default]), UsedName(toString,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(dec_pause_state,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(csr_mitcnt0,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(csr_mitctl0,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(pathName,[Default]), UsedName(el2_dec_timer_ctl_IO,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(csr_mitb1,[Default]), UsedName(csr_mitcnt1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_timer_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_timer_ctl_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_lsu_pkt_t...
-[debug] Initial set of included nodes: include.el2_lsu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_lsu_pkt_t)
-[debug] Change NamesChange(include.el2_lsu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(fast_int,[Default]), UsedName(word,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(by,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(load_ldst_bypass_d,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(include;el2_lsu_pkt_t;init;,[Default]), UsedName(store_data_bypass_m,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(half,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(store_data_bypass_d,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(el2_lsu_pkt_t,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(dword,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_lsu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_lsu_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.inst_pkt_t...
-[debug] Initial set of included nodes: include.inst_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.inst_pkt_t)
-[debug] The following modified names cause invalidation of dec.csr_tlu: Set(UsedName(STORE,[Default]), UsedName(CONDBR,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(inst_pkt_t,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(==,[Default]), UsedName(ECALL,[Default]), UsedName(BITMANIPU,[Default]), UsedName(FENCEI,[Default]), UsedName(FENCE,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_tlu_ctl: Set(UsedName(MRET,[Default]), UsedName(inst_pkt_t,[Default]), UsedName(apply,[Default]), UsedName(EBREAK,[Default]), UsedName(==,[Default]), UsedName(ECALL,[Default]))
-[debug] The following modified names cause invalidation of dec.CSR_VAL: Set(UsedName(inst_pkt_t,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_decode_ctl: Set(UsedName(STORE,[Default]), UsedName(CONDBR,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(inst_pkt_t,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(ECALL,[Default]), UsedName(NULL,[Default]), UsedName(FENCEI,[Default]), UsedName(FENCE,[Default]))
-[debug] Change NamesChange(include.inst_pkt_t,ModifiedNames(changes = UsedName(STORE,[Default]), UsedName(ValueSet,[Default]), UsedName(CONDBR,[Default]), UsedName(isInstanceOf,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(synchronized,[Default]), UsedName(inst_pkt_t,[Default]), UsedName(nextId,[Default]), UsedName(ValueOrdering,[Default]), UsedName(toString,[Default]), UsedName(maxId,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(withName,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(Val,[Default]), UsedName(nextName,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(Value,[Default]), UsedName(values,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ECALL,[Default]), UsedName(BITMANIPU,[Default]), UsedName(NULL,[Default]), UsedName(notify,[Default]), UsedName(FENCEI,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(readResolve,[Default]), UsedName(FENCE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 5 classes due to The include.inst_pkt_t has the following regular definitions changed:
-[debug] 	UsedName(STORE,[Default]), UsedName(ValueSet,[Default]), UsedName(CONDBR,[Default]), UsedName(isInstanceOf,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(synchronized,[Default]), UsedName(inst_pkt_t,[Default]), UsedName(nextId,[Default]), UsedName(ValueOrdering,[Default]), UsedName(toString,[Default]), UsedName(maxId,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(withName,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(Val,[Default]), UsedName(nextName,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(Value,[Default]), UsedName(values,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ECALL,[Default]), UsedName(BITMANIPU,[Default]), UsedName(NULL,[Default]), UsedName(notify,[Default]), UsedName(FENCEI,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(readResolve,[Default]), UsedName(FENCE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(include.inst_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.csr_tlu, dec.dec_tlu_ctl, dec.CSR_VAL, dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvdffs...
-[debug] Initial set of included nodes: lib.rvdffs
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvdffs)
-[debug] Change NamesChange(lib.rvdffs,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(clear,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(rvdffs,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(din,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(lib;rvdffs;init;,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvdffs has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lib.rvdffs)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_tlu_csr_pkt...
-[debug] Initial set of included nodes: include.dec_tlu_csr_pkt
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_tlu_csr_pkt)
-[debug] The following member ref dependencies of include.dec_tlu_csr_pkt are invalidated:
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec_decode_csr_read
-[debug] 	dec.dec_decode_csr_read_IO
-[debug] 	dec.dec_tlu_ctl
-[debug] Change NamesChange(include.dec_tlu_csr_pkt,ModifiedNames(changes = UsedName(csr_mcycleh,[Default]), UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(csr_marchid,[Default]), UsedName(csr_mfdc,[Default]), UsedName(csr_dicad1,[Default]), UsedName(ignoreSeq,[Default]), UsedName(presync,[Default]), UsedName(csr_mfdht,[Default]), UsedName(csr_mhartid,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(csr_mtdata1,[Default]), UsedName(asUInt,[Default]), UsedName(csr_mitctl1,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(csr_mdeau,[Default]), UsedName(isInstanceOf,[Default]), UsedName(csr_miccmect,[Default]), UsedName(csr_mtsel,[Default]), UsedName(csr_mtval,[Default]), UsedName(:=,[Default]), UsedName(csr_meivt,[Default]), UsedName(csr_micect,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(csr_mvendorid,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(csr_mip,[Default]), UsedName(csr_mhpmc3,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(csr_mitb0,[Default]), UsedName(csr_minstreth,[Default]), UsedName(csr_mhpmc6h,[Default]), UsedName(csr_mhpmc4h,[Default]), UsedName(toString,[Default]), UsedName(csr_dmst,[Default]), UsedName(csr_dicago,[Default]), UsedName(csr_mtdata2,[Default]), UsedName(litArg,[Default]), UsedName(csr_meihap,[Default]), UsedName(csr_mhpmc5h,[Default]), UsedName(csr_mhpmc4,[Default]), UsedName(getElements,[Default]), UsedName(csr_mcountinhibit,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(csr_mhpmc5,[Default]), UsedName(csr_mhpme3,[Default]), UsedName(csr_mpmc,[Default]), UsedName(csr_meicpct,[Default]), UsedName(ref,[Default]), UsedName(csr_meipt,[Default]), UsedName(do_asUInt,[Default]), UsedName(csr_mstatus,[Default]), UsedName(csr_mrac,[Default]), UsedName(csr_mtvec,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(csr_mdseac,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(csr_dpc,[Default]), UsedName(setRef,[Default]), UsedName(csr_mitcnt0,[Default]), UsedName(csr_dicad0h,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(csr_mepc,[Default]), UsedName(dec_tlu_csr_pkt,[Default]), UsedName(csr_mhpme5,[Default]), UsedName(csr_dicad0,[Default]), UsedName(csr_meicurpl,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(csr_mhpmc3h,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(csr_mie,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(csr_mscratch,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(csr_mcyclel,[Default]), UsedName(csr_dicawics,[Default]), UsedName(notify,[Default]), UsedName(csr_mitctl0,[Default]), UsedName(postsync,[Default]), UsedName(include;dec_tlu_csr_pkt;init;,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(csr_mcgc,[Default]), UsedName(csr_mcause,[Default]), UsedName(suggestName,[Default]), UsedName(csr_mcpc,[Default]), UsedName(eq,[Default]), UsedName(csr_mscause,[Default]), UsedName(pathName,[Default]), UsedName(csr_meicidpl,[Default]), UsedName(<>,[Default]), UsedName(csr_mimpid,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(csr_dcsr,[Default]), UsedName(csr_mhpme4,[Default]), UsedName(csr_mhpme6,[Default]), UsedName(csr_mfdhs,[Default]), UsedName(csr_mitb1,[Default]), UsedName(csr_mitcnt1,[Default]), UsedName(csr_mdccmect,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(csr_mhpmc6,[Default]), UsedName(binding,[Default]), UsedName(csr_minstretl,[Default]), UsedName(getOptionRef,[Default]), UsedName(csr_misa,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dec_tlu_csr_pkt has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_tlu_csr_pkt)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, dec.csr_tlu, dec.CSR_IO, dec.dec_decode_csr_read)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dma_lsc_ctl...
-[debug] Initial set of included nodes: include.dma_lsc_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(include.dma_lsc_ctl)
-[debug] The following member ref dependencies of include.dma_lsc_ctl are invalidated:
-[debug] 	dma_ctrl
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_lsc_ctl
-[debug] Change NamesChange(include.dma_lsc_ctl,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(dma_lsc_ctl,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(dma_mem_sz,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(dma_dccm_req,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(include;dma_lsc_ctl;init;,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dma_mem_addr,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dma_mem_wdata,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(dma_mem_write,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.dma_lsc_ctl has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dma_lsc_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, dma_ctrl, lsu.lsu_lsc_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dest_pkt_t...
-[debug] Initial set of included nodes: include.dest_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.dest_pkt_t)
-[debug] The following member ref dependencies of include.dest_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(include.dest_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(i0v,[Default]), UsedName(ignoreSeq,[Default]), UsedName(csrwaddr,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(csrwen,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(i0store,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(i0div,[Default]), UsedName(i0load,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(dest_pkt_t,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(include;dest_pkt_t;init;,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(csrwonly,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(i0rd,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The include.dest_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dest_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_gpr_ctl_IO...
-[debug] Initial set of included nodes: dec.dec_gpr_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_gpr_ctl_IO)
-[debug] The following member ref dependencies of dec.dec_gpr_ctl_IO are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_gpr_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(wen0,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(raddr0,[Default]), UsedName(wd1,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(waddr1,[Default]), UsedName(bind,[Default]), UsedName(wd0,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(waddr0,[Default]), UsedName(dec_gpr_ctl_IO,[Default]), UsedName(ref,[Default]), UsedName(wen2,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(raddr1,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(gpr_exu,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(waddr2,[Default]), UsedName(dec;dec_gpr_ctl_IO;init;,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(wd2,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(wen1,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The dec.dec_gpr_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_gpr_ctl_IO)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_ib_ctl_IO...
-[debug] Initial set of included nodes: dec.dec_ib_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_ib_ctl_IO)
-[debug] The following member ref dependencies of dec.dec_ib_ctl_IO are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_ib_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_ib0_valid_d,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(dec_i0_pc4_d,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(dec_i0_dbecc_d,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(dbg_ib,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_i0_icaf_type_d,[Default]), UsedName(dec_debug_fence_d,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_brp,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(dec_i0_bp_index,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_i0_bp_fghr,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ifu_ib,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(dec_i0_instr_d,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(dec_ib_ctl_IO,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dec_i0_icaf_d,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(dec;dec_ib_ctl_IO;init;,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_i0_bp_btag,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_icaf_f1_d,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(ib_exu,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The dec.dec_ib_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_ib_ctl_IO)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dmi.dmi_wrapper...
-[debug] Initial set of included nodes: dmi.dmi_wrapper
-[debug] Invalidated by transitive inheritance dependency: Set(dmi.dmi_wrapper)
-[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(jtag_id,[Default]), UsedName(reg_wr_en,[Default]), UsedName(IO,[Default]), UsedName(trst_n,[Default]), UsedName(tdo,[Default]), UsedName(core_clk,[Default]), UsedName(reg_wr_data,[Default]), UsedName(tck,[Default]), UsedName(reg_en,[Default]), UsedName(io,[Default]), UsedName(dmi_wrapper,[Default]), UsedName(rd_data,[Default]), UsedName(tms,[Default]), UsedName(tdi,[Default]), UsedName(reg_wr_addr,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName(core_rst_n,[Default]))
-[debug] Change NamesChange(dmi.dmi_wrapper,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(tdoEnable,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(jtag_id,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(reg_wr_en,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(trst_n,[Default]), UsedName(tdo,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(core_clk,[Default]), UsedName(reg_wr_data,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(setRef,[Default]), UsedName(tck,[Default]), UsedName(_parent,[Default]), UsedName(reg_en,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(dmi_wrapper,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(params,[Default]), UsedName(rd_data,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(tms,[Default]), UsedName(suggestName,[Default]), UsedName(tdi,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(_id,[Default]), UsedName(reg_wr_addr,[Default]), UsedName(isClosed,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(core_rst_n,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dmi.dmi_wrapper has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(tdoEnable,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(jtag_id,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(reg_wr_en,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(trst_n,[Default]), UsedName(tdo,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(core_clk,[Default]), UsedName(reg_wr_data,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(setRef,[Default]), UsedName(tck,[Default]), UsedName(_parent,[Default]), UsedName(reg_en,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(dmi_wrapper,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(params,[Default]), UsedName(rd_data,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(tms,[Default]), UsedName(suggestName,[Default]), UsedName(tdi,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(_id,[Default]), UsedName(reg_wr_addr,[Default]), UsedName(isClosed,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(core_rst_n,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dmi.dmi_wrapper)
+[debug] Invalidating (transitively) by inheritance from include.iccm_mem...
+[debug] Initial set of included nodes: include.iccm_mem
+[debug] Invalidated by transitive inheritance dependency: Set(include.iccm_mem)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.iccm_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The include.iccm_mem has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(include.iccm_mem)
 [debug] 	> 
 [debug] 	> by member reference: Set(quasar_wrapper)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_div...
-[debug] Initial set of included nodes: include.dec_div
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_div)
-[debug] The following member ref dependencies of include.dec_div are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] 	exu.exu_div_ctl
-[debug] Change NamesChange(include.dec_div,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dec_div_cancel,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dec_div,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(include;dec_div;init;,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(div_p,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.dec_div has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_div)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_div_ctl, dec.dec, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_decode_csr_read...
-[debug] Initial set of included nodes: dec.el2_dec_decode_csr_read
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_decode_csr_read)
-[debug] Change NamesChange(dec.el2_dec_decode_csr_read,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec;el2_dec_decode_csr_read;init;,[Default]), UsedName(forceName,[Default]), UsedName(el2_dec_decode_csr_read,[Default]), UsedName(pattern,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_decode_csr_read has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec;el2_dec_decode_csr_read;init;,[Default]), UsedName(forceName,[Default]), UsedName(el2_dec_decode_csr_read,[Default]), UsedName(pattern,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_decode_csr_read)
+[debug] Invalidating (transitively) by inheritance from ifu.mem_ctl_io...
+[debug] Initial set of included nodes: ifu.mem_ctl_io
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.mem_ctl_io)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.mem_ctl_io,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The ifu.mem_ctl_io has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.mem_ctl_io)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.ic_mem...
-[debug] Initial set of included nodes: include.ic_mem
-[debug] Invalidated by transitive inheritance dependency: Set(include.ic_mem)
-[debug] The following member ref dependencies of include.ic_mem are invalidated:
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	mem.Mem_bundle
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(include.ic_mem,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(debug_rd_data,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(tag_perr,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(include;ic_mem;init;,[Default]), UsedName(debug_wr_data,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(ic_mem,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(sel_premux_data,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(debug_tag_array,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(debug_wr_en,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(tag_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(eccerr,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(rw_addr,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(rd_hit,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(premux_data,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(wr_en,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rd_en,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(debug_rd_en,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(debug_addr,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(rd_data,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(debug_way,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(wr_data,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(parerr,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(tag_valid,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 8 classes due to The include.ic_mem has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ic_mem)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu, quasar, quasar_bundle, ifu.mem_ctl_io, quasar_wrapper, mem.Mem_bundle, ifu.ifu_mem_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.tlu_dma...
-[debug] Initial set of included nodes: include.tlu_dma
-[debug] Invalidated by transitive inheritance dependency: Set(include.tlu_dma)
-[debug] The following member ref dependencies of include.tlu_dma are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	dma_ctrl
-[debug] Change NamesChange(include.tlu_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(include;tlu_dma;init;,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(dma_pmu_dccm_read,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(dma_pmu_dccm_write,[Default]), UsedName(tlu_dma,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(dec_tlu_dma_qos_prty,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(dma_pmu_any_write,[Default]), UsedName(dma_pmu_any_read,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.tlu_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.tlu_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_tlu_ctl, dec.dec_tlu_ctl_IO, dma_ctrl, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_exu...
-[debug] Initial set of included nodes: include.lsu_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_exu)
-[debug] The following member ref dependencies of include.lsu_exu are invalidated:
-[debug] 	exu.exu
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_lsc_ctl
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(exu_lsu_rs2_d,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(include;lsu_exu;init;,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(exu_lsu_rs1_d,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(lsu_exu,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.lsu_exu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, quasar, lsu.lsu_lsc_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_mem_ctrl...
-[debug] Initial set of included nodes: include.dec_mem_ctrl
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_mem_ctrl)
-[debug] The following member ref dependencies of include.dec_mem_ctrl are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_mem_ctrl,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(dec_tlu_fence_i_wb,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ifu_pmu_bus_error,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(dec_mem_ctrl,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(dec_tlu_ic_diag_pkt,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(ifu_ic_error_start,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ifu_pmu_ic_hit,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(ifu_iccm_rd_ecc_single_err,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(ifu_ic_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(ifu_pmu_bus_trxn,[Default]), UsedName(dec_tlu_flush_err_wb,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(dec_tlu_i0_commit_cmt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(ifu_ic_debug_rd_data_valid,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(include;dec_mem_ctrl;init;,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(ifu_miss_state_idle,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(ifu_pmu_bus_busy,[Default]), UsedName(ifu_pmu_ic_miss,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 8 classes due to The include.dec_mem_ctrl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_mem_ctrl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, ifu.ifu, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, quasar, ifu.mem_ctl_io, ifu.ifu_mem_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_ifc...
-[debug] Initial set of included nodes: include.dec_ifc
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_ifc)
-[debug] The following member ref dependencies of include.dec_ifc are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_ifc_ctl
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_ifc,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(dec_ifc,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(ifu_pmu_fetch_stall,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_flush_noredir_wb,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(include;dec_ifc;init;,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 7 classes due to The include.dec_ifc has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_ifc)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, ifu.ifu, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, quasar, ifu.ifu_ifc_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvrangecheck...
-[debug] Initial set of included nodes: lib.rvrangecheck
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvrangecheck)
-[debug] Change NamesChange(lib.rvrangecheck,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(in_region,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(start_addr,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(addr,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(in_range,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName(MASK_BITS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(REGION_BITS,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName(lib;rvrangecheck;init;,[Default]), UsedName(region,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvrangecheck has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(in_region,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(start_addr,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(addr,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(in_range,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName(MASK_BITS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(REGION_BITS,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName(lib;rvrangecheck;init;,[Default]), UsedName(region,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvrangecheck)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_predict_pkt_t...
-[debug] Initial set of included nodes: include.el2_predict_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_predict_pkt_t)
-[debug] Change NamesChange(include.el2_predict_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(toffset,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(boffset,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(pret,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(prett,[Default]), UsedName(el2_predict_pkt_t,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(pja,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(ataken,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(pc4,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(misp,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(include;el2_predict_pkt_t;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(pcall,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_predict_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_predict_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.rvecc_encode_64...
-[debug] Initial set of included nodes: lib.lib.rvecc_encode_64
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.rvecc_encode_64)
-[debug] Change NamesChange(lib.lib.rvecc_encode_64,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(lib;lib;rvecc_encode_64;init;,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.lib.rvecc_encode_64 has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(lib;lib;rvecc_encode_64;init;,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.rvecc_encode_64)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_decode_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_decode_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_decode_ctl)
-[debug] Change NamesChange(dec.el2_dec_decode_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(nonblock_load_rd,[Default]), UsedName(i0_instr_error,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(lsu_nonblock_load_data,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_i0_rs2_bypass_en_d,[Default]), UsedName(dec_tlu_i0_kill_writeb_wb,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(i0_wb_ctl_en,[Default]), UsedName(dec_ib0_valid_d,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(i0_br_unpred,[Default]), UsedName(MEM_CAL,[Default]), UsedName(i0_br_error_all,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(i0_br_error,[Default]), UsedName(cam_wen,[Default]), UsedName(i0_nonblock_load_stall,[Default]), UsedName(cam_in,[Default]), UsedName(i0_predict_fghr_d,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(flush_final_r,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(prior_inflight_eff,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(i0_result_r,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(i0_rs2_nonblock_load_bypass_en_d,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(i0_predict_index_d,[Default]), UsedName(free_clk,[Default]), UsedName(exu_csr_rs1_x,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(dec;el2_dec_decode_ctl;init;,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(i0_predict_btag_d,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(csr_clr_d,[Default]), UsedName(x_d_in,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(i0_load_block_d,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(i0_rd_en_d,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(dec_i0_select_pc_d,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(i0_rs1_class_d,[Default]), UsedName(i0_predict_br,[Default]), UsedName(nonblock_load_cancel,[Default]), UsedName(dec_i0_pc4_d,[Default]), UsedName(div_active_in,[Default]), UsedName(rvecc_encode,[Default]), UsedName(i0_nonblock_boundary_stall,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(dec_i0_dbecc_d,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(tlu_wr_pause_r2,[Default]), UsedName(pause_state_in,[Default]), UsedName(dec_tlu_presync_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_i0_icaf_type_d,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(csr_data_wen,[Default]), UsedName(dec_debug_fence_d,[Default]), UsedName(csr_imm_x,[Default]), UsedName(i0_store_stall_d,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(illegal_lockout,[Default]), UsedName(r_d_in,[Default]), UsedName(dec_div_cancel,[Default]), UsedName(i0_inst_wb,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(lsu_nonblock_load_data_error,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(clear_pause,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(lsu_idle,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(lsu_trigger_match_r,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(pause_state,[Default]), UsedName(div_e1_to_r,[Default]), UsedName(i0_rs2bypass,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(i0_exublock_d,[Default]), UsedName(i0_x_data_en,[Default]), UsedName(i0_notbr_error,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(csr_read_x,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(dec_csr_ren_d,[Default]), UsedName(i0_wen_r,[Default]), UsedName(load_ldst_bypass_d,[Default]), UsedName(getPorts,[Default]), UsedName(div_flush,[Default]), UsedName(i0_r_data_en,[Default]), UsedName(i0_br_toffset_error,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(i0_wb_data_en,[Default]), UsedName(x_t,[Default]), UsedName(i0_brp_valid,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(dec_i0_wen_r,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(r_t,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(_namespace,[Default]), UsedName(illegal_inst_en,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(csr_set_d,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(cam_write,[Default]), UsedName(Tag_Word,[Default]), UsedName(i0_pret_case,[Default]), UsedName(ld_stall_2,[Default]), UsedName(LSU2DMA,[Default]), UsedName(leak1_mode,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(i0_pja,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(lsu_decode_d,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(dec_i0_alu_decode_d,[Default]), UsedName(dec_i0_rs1_bypass_data_d,[Default]), UsedName(i0_x_c,[Default]), UsedName(i0_pret_raw,[Default]), UsedName(i0_result_x,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(r_d,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(exu_i0_result_x,[Default]), UsedName(ld_stall_1,[Default]), UsedName(cam_inv_reset_tag,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_predict_p_d,[Default]), UsedName(dec_i0_brp,[Default]), UsedName(i0_exudecode_d,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dec_pause_state,[Default]), UsedName(store_data_bypass_m,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(i0_exulegal_decode_d,[Default]), UsedName(forceName,[Default]), UsedName(prior_inflight_x,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(csr_mask_x,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(i0_legal,[Default]), UsedName(dec_pause_state_cg,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(i0_icaf_d,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(i0_dec,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(i0_postsync,[Default]), UsedName(postsync_stall,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(el2_dec_decode_ctl,[Default]), UsedName(dec_div_active,[Default]), UsedName(lsu_nonblock_load_inv_r,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(debug_fence_raw,[Default]), UsedName(dec_i0_immed_d,[Default]), UsedName(d_t,[Default]), UsedName(lsu_nonblock_load_data_tag,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(i0_r_ctl_en,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(pred_correct_npc_x,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(dec_i0_rs1_d,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(dec_i0_rs2_d,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(i0_wb1_data_en,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(i0_pcall_raw,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(div_decode_d,[Default]), UsedName(i0_dp_raw,[Default]), UsedName(i0_result_corr_r,[Default]), UsedName(i0_wb_en,[Default]), UsedName(dec_tlu_flush_leak_one_r,[Default]), UsedName(i0_predict_t,[Default]), UsedName(dec_csr_legal_d,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(dec_tlu_debug_stall,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(cam_inv_reset_val,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(load_data_tag,[Default]), UsedName(csr_ren_qual_d,[Default]), UsedName(csr_write_d,[Default]), UsedName(finalize,[Default]), UsedName(i0_pc_wb,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(i0_rs2_depth_d,[Default]), UsedName(dec_i0_rs2_en_d,[Default]), UsedName(i0,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(i0_pja_case,[Default]), UsedName(i0_result_r_raw,[Default]), UsedName(dec_i0_rs2_bypass_data_d,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(dec_i0_bp_index,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(i0_immed_d,[Default]), UsedName(dec_data_en,[Default]), UsedName(ps_stall_in,[Default]), UsedName(exu_i0_pc_x,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(i0_pcall_imm,[Default]), UsedName(i0_pcall_12b_offset,[Default]), UsedName(i0_ap,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(debug_fence_i,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(waddr,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(i0_wb1_en,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(i0_uiimm20,[Default]), UsedName(i0_pcall,[Default]), UsedName(i0_csr_write_only_d,[Default]), UsedName(dec_i0_bp_fghr,[Default]), UsedName(i0_block_d,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(leak1_i0_stall,[Default]), UsedName(store_data_bypass_d,[Default]), UsedName(cam_data_reset,[Default]), UsedName(i0_pja_raw,[Default]), UsedName(rvclkhdr,[Default]), UsedName(i0_inst_x,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(i0_rs2_class_d,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(i0_d_c,[Default]), UsedName(illegal_lockout_in,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(i0_ret_error,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(r_t_in,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(ifu_i0_cinst,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(prior_csr_write,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(data_gate_en,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(nonblock_load_write,[Default]), UsedName(clk_override,[Default]), UsedName(write_csr_data,[Default]), UsedName(leak1_i1_stall_in,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(div_inst,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(lsu_nonblock_load_valid_m,[Default]), UsedName(i0_rs1_depend_i0_r,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(data_gate_clk,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(i0_rs2_depend_i0_r,[Default]), UsedName(dec_ctl_en,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(dec_i0_br_immed_d,[Default]), UsedName(i0_pret,[Default]), UsedName(i0_csr_write,[Default]), UsedName(lsu_nonblock_load_inv_tag_r,[Default]), UsedName(_onModuleClose,[Default]), UsedName(i0_predict_nt,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(dec_i0_instr_d,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_i0_wdata_r,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(csr_write_x,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(dec_i0_pc_r,[Default]), UsedName(last_br_immed_d,[Default]), UsedName(cam_write_tag,[Default]), UsedName(dec_tlu_flush_pause_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(csr_read,[Default]), UsedName(i0_rs2_depend_i0_x,[Default]), UsedName(debug_fence,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(dec_tlu_postsync_d,[Default]), UsedName(io,[Default]), UsedName(dec_i0_waddr_r,[Default]), UsedName(clone,[Default]), UsedName(cam,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(cam_raw,[Default]), UsedName(lsu_load_stall_any,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(i0_legal_decode_d,[Default]), UsedName(leak1_i0_stall_in,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(write_csr_data_in,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(i0_ap_pc4,[Default]), UsedName(i0_div_decode_d,[Default]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(i0_nonblock_div_stall,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(temp_pred_correct_npc_x,[Default]), UsedName(dec_i0_icaf_d,[Default]), UsedName(i0_rs1_depth_d,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(prior_inflight,[Default]), UsedName(dec_i0_rs1_en_d,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(presync_stall,[Default]), UsedName(i0r,[Default]), UsedName($isInstanceOf,[Default]), UsedName(i0_jalimm20,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mul_p,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(cal_temp,[Default]), UsedName(i0_pcall_case,[Default]), UsedName(lsu_pmu_misaligned_r,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(csrimm_x,[Default]), UsedName(i0_div_prior_div_stall,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(any_csr_d,[Default]), UsedName(i0_inst_wb_in,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(i0_ap_pc2,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(i0_jal,[Default]), UsedName(csr_write,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(mul_decode_d,[Default]), UsedName(dec_i0_bp_btag,[Default]), UsedName(i0_r_c,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(i0_dp,[Default]), UsedName(dec_extint_stall,[Default]), UsedName(lsu_nonblock_load_tag_m,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(i0_block_raw_d,[Default]), UsedName(csr_set_x,[Default]), UsedName(i0_rs1_nonblock_load_bypass_en_d,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(i0_x_ctl_en,[Default]), UsedName(nonblock_div_cancel,[Default]), UsedName(tlu_wr_pause_r1,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(cam_data_reset_tag,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(lsu_nonblock_load_data_valid,[Default]), UsedName(nonblock_load_valid_m_delay,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(i0_pipe_en,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(dec_nonblock_load_waddr,[Default]), UsedName(write_csr_data_x,[Default]), UsedName(i0_load_kill_wen_r,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(wbd,[Default]), UsedName(addCommand,[Default]), UsedName(cam_data_reset_val,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(div_waddr_wb,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(dec_i0_icaf_f1_d,[Default]), UsedName(parentModName,[Default]), UsedName(i0_rs1bypass,[Default]), UsedName(getClass,[Default]), UsedName(i0_inst_d,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(x_d,[Default]), UsedName(dec_i0_rs1_bypass_en_d,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(i0_presync,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(i0_rs1_depend_i0_x,[Default]), UsedName(dec_nonblock_load_wen,[Default]), UsedName(isClosed,[Default]), UsedName(lsu_pmu_misaligned_m,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(leak1_i1_stall,[Default]), UsedName(x_t_in,[Default]), UsedName(csr_rddata_x,[Default]), UsedName(pause_stall,[Default]), UsedName(i0_br_offset,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(cam_inv_reset,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(shift_illegal,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(d_d,[Default]), UsedName(dec_tlu_flush_extint,[Default]), UsedName(dbg_cmd_wrdata,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(i0_load_stall_d,[Default]), UsedName(div_p,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(i0_inst_r,[Default]), UsedName(prior_inflight_wb,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(csr_clr_x,[Default]), UsedName(last_br_immed_x,[Default]))) invalidates 1 classes due to The dec.el2_dec_decode_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_decode_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.ic_tag_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.ic_tag_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.ic_tag_ext_in_pkt_t)
-[debug] Change NamesChange(include.ic_tag_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(include;ic_tag_ext_in_pkt_t;init;,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ic_tag_ext_in_pkt_t,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.ic_tag_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ic_tag_ext_in_pkt_t)
+[debug] Invalidating (transitively) by inheritance from include.aln_ib...
+[debug] Initial set of included nodes: include.aln_ib
+[debug] Invalidated by transitive inheritance dependency: Set(include.aln_ib)
+[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.aln_ib,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.aln_ib has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.aln_ib)
 [debug] 	> 
 [debug] 	> 
 [debug]         
 [debug] Invalidating (transitively) by inheritance from lib.axi4_to_ahb_IO...
 [debug] Initial set of included nodes: lib.axi4_to_ahb_IO
 [debug] Invalidated by transitive inheritance dependency: Set(lib.axi4_to_ahb_IO)
-[debug] The following member ref dependencies of lib.axi4_to_ahb_IO are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(lib.axi4_to_ahb_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(axi_rready,[Default]), UsedName(axi_bresp,[Default]), UsedName(ignoreSeq,[Default]), UsedName(axi_awready,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lib;axi4_to_ahb_IO;init;,[Default]), UsedName(direction,[Default]), UsedName(ahb_haddr,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(axi_wvalid,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(axi_awid,[Default]), UsedName(toNamed,[Default]), UsedName(axi_wready,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(bind,[Default]), UsedName(bus_clk_en,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(axi_bready,[Default]), UsedName(ahb_hprot,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(axi_arvalid,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_wstrb,[Default]), UsedName(ahb_htrans,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(axi_awsize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arready,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(axi_araddr,[Default]), UsedName(axi_bvalid,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(scan_mode,[Default]), UsedName(axi_wlast,[Default]), UsedName(_parent,[Default]), UsedName(axi_bid,[Default]), UsedName(clk_override,[Default]), UsedName(axi_awaddr,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(TAG,[Default]), UsedName(topBindingOpt,[Default]), UsedName(axi_rresp,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(axi_arid,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(axi_arsize,[Default]), UsedName(!=,[Default]), UsedName(axi_arprot,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(axi4_to_ahb_IO,[Default]), UsedName(_makeLit,[Default]), UsedName(ahb_hmastlock,[Default]), UsedName(notify,[Default]), UsedName(axi_rlast,[Default]), UsedName(ahb_hready,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(axi_awvalid,[Default]), UsedName(ahb_hburst,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(axi_rid,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_awprot,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(axi_wdata,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The lib.axi4_to_ahb_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
+[debug] The following modified names cause invalidation of quasar: Set(UsedName(ahb,[Default]), UsedName(axi,[Default]))
+[debug] Change NamesChange(lib.axi4_to_ahb_IO,ModifiedNames(changes = UsedName(axi_wlast,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(axi_rlast,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi,[Default]), UsedName(ahb_hready,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hmastlock,[Default]))) invalidates 2 classes due to The lib.axi4_to_ahb_IO has the following regular definitions changed:
+[debug] 	UsedName(axi_wlast,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(axi_rlast,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi,[Default]), UsedName(ahb_hready,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hmastlock,[Default]).
 [debug] 	> by transitive inheritance: Set(lib.axi4_to_ahb_IO)
 [debug] 	> 
 [debug] 	> by member reference: Set(quasar)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvecc_decode_64.rvsyncss...
-[debug] Initial set of included nodes: lib.rvecc_decode_64.rvsyncss
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvecc_decode_64.rvsyncss)
-[debug] Change NamesChange(lib.rvecc_decode_64.rvsyncss,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvecc_decode_64.rvsyncss has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvecc_decode_64.rvsyncss)
+[debug] Invalidating (transitively) by inheritance from dec.CSR_IO...
+[debug] Initial set of included nodes: dec.CSR_IO
+[debug] Invalidated by transitive inheritance dependency: Set(dec.CSR_IO)
+[debug] Change NamesChange(dec.CSR_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.CSR_IO has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.CSR_IO)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from snapshot.pt...
+[debug] Initial set of included nodes: snapshot.pt
+[debug] Invalidated by transitive inheritance dependency: Set(snapshot.pt)
+[debug] Change NamesChange(snapshot.pt,ModifiedNames(changes = UsedName(BTB_ADDR_HI,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(notify,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(notifyAll,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(synchronized,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(wait,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(##,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ne,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(equals,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(==,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(hashCode,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(PIC_REGION,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(eq,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(clone,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(getClass,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName($asInstanceOf,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(pt,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]))) invalidates 1 classes due to The snapshot.pt has the following regular definitions changed:
+[debug] 	UsedName(BTB_ADDR_HI,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(notify,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(notifyAll,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(synchronized,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(wait,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(##,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ne,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(equals,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(==,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(hashCode,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(PIC_REGION,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(eq,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(clone,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(getClass,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName($asInstanceOf,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(pt,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]).
+[debug] 	> by transitive inheritance: Set(snapshot.pt)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_addrcheck...
+[debug] Initial set of included nodes: lsu.lsu_addrcheck
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_addrcheck)
+[debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_addrcheck,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_addrcheck has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_addrcheck)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lib.ahb_to_axi4...
+[debug] Initial set of included nodes: lib.ahb_to_axi4
+[debug] Invalidated by transitive inheritance dependency: Set(lib.ahb_to_axi4)
+[debug] The following modified names cause invalidation of quasar: Set(UsedName(hreadyin,[Default]), UsedName(hsel,[Default]), UsedName(ahb,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi,[Default]))
+[debug] Change NamesChange(lib.ahb_to_axi4,ModifiedNames(changes = UsedName(hreadyin,[Default]), UsedName(axi_wlast,[Default]), UsedName(axi_awburst,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_awlen,[Default]), UsedName(hsel,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(ahb_hreadyin,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_hsel,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(flip,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(axi_arburst,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi_arlen,[Default]), UsedName(axi,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hreadyout,[Default]), UsedName(ahb_hmastlock,[Default]))) invalidates 2 classes due to The lib.ahb_to_axi4 has the following regular definitions changed:
+[debug] 	UsedName(hreadyin,[Default]), UsedName(axi_wlast,[Default]), UsedName(axi_awburst,[Default]), UsedName(axi_bid,[Default]), UsedName(axi_arready,[Default]), UsedName(axi_awaddr,[Default]), UsedName(axi_awlen,[Default]), UsedName(hsel,[Default]), UsedName(axi_rresp,[Default]), UsedName(axi_rready,[Default]), UsedName(ahb_hreadyin,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_hsel,[Default]), UsedName(axi_wdata,[Default]), UsedName(axi_rvalid,[Default]), UsedName(axi_bready,[Default]), UsedName(axi_arid,[Default]), UsedName(axi_araddr,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_htrans,[Default]), UsedName(axi_wvalid,[Default]), UsedName(ahb_hresp,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(axi_arprot,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(axi_arvalid,[Default]), UsedName(axi_wstrb,[Default]), UsedName(flip,[Default]), UsedName(axi_awready,[Default]), UsedName(axi_awid,[Default]), UsedName(ahb,[Default]), UsedName(axi_awsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(axi_awvalid,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(io,[Default]), UsedName(sig,[Default]), UsedName(axi_bresp,[Default]), UsedName(ahb_hburst,[Default]), UsedName(axi_rdata,[Default]), UsedName(axi_awprot,[Default]), UsedName(axi_bvalid,[Default]), UsedName(axi_wready,[Default]), UsedName(axi_arburst,[Default]), UsedName(ahb_haddr,[Default]), UsedName(axi_arlen,[Default]), UsedName(axi,[Default]), UsedName(axi_rid,[Default]), UsedName(ahb_hprot,[Default]), UsedName(axi_arsize,[Default]), UsedName(ahb_hreadyout,[Default]), UsedName(ahb_hmastlock,[Default]).
+[debug] 	> by transitive inheritance: Set(lib.ahb_to_axi4)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lib.axi4_to_ahb...
+[debug] Initial set of included nodes: lib.axi4_to_ahb
+[debug] Invalidated by transitive inheritance dependency: Set(lib.axi4_to_ahb)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lib.axi4_to_ahb,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lib.axi4_to_ahb has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lib.axi4_to_ahb)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_trigger...
+[debug] Initial set of included nodes: dec.dec_trigger
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_trigger)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_trigger,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_trigger has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_trigger)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dma_ctrl...
+[debug] Initial set of included nodes: dma_ctrl
+[debug] Invalidated by transitive inheritance dependency: Set(dma_ctrl)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dma_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dma_ctrl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(dma_ctrl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.ic_mem...
+[debug] Initial set of included nodes: include.ic_mem
+[debug] Invalidated by transitive inheritance dependency: Set(include.ic_mem)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.ic_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The include.ic_mem has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.ic_mem)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_buffer...
+[debug] Initial set of included nodes: lsu.lsu_bus_buffer
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_buffer)
+[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_bus_buffer,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_bus_buffer has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_bus_buffer)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_gpr_ctl...
+[debug] Initial set of included nodes: dec.dec_gpr_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_gpr_ctl)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_gpr_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.dec_gpr_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_gpr_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_IO...
+[debug] Initial set of included nodes: dec.dec_IO
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_IO)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_IO has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_IO)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_dec_ctl...
+[debug] Initial set of included nodes: dec.dec_dec_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_dec_ctl)
+[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_dec_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_dec_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_dec_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from ifu.ifu...
+[debug] Initial set of included nodes: ifu.ifu
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The ifu.ifu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.ifu)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from quasar_bundle...
+[debug] Initial set of included nodes: quasar_bundle
+[debug] Invalidated by transitive inheritance dependency: Set(quasar_bundle)
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(hreadyin,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_ahb,[Default]), UsedName(lsu_ahb,[Default]), UsedName(sig,[Default]))
+[debug] Change NamesChange(quasar_bundle,ModifiedNames(changes = UsedName(dma_hsize,[Default]), UsedName(lsu_hresp,[Default]), UsedName(hreadyin,[Default]), UsedName(hresp,[Default]), UsedName(lsu_hburst,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(hmastlock,[Default]), UsedName(lsu_hsize,[Default]), UsedName(dma_htrans,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(hready,[Default]), UsedName(sb_hwdata,[Default]), UsedName(lsu_hwrite,[Default]), UsedName(sb_hwrite,[Default]), UsedName(hrdata,[Default]), UsedName(hsize,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_hburst,[Default]), UsedName(htrans,[Default]), UsedName(sb_ahb,[Default]), UsedName(sb_hprot,[Default]), UsedName(hburst,[Default]), UsedName(lsu_hready,[Default]), UsedName(lsu_ahb,[Default]), UsedName(lsu_hmastlock,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_hsize,[Default]), UsedName(lsu_haddr,[Default]), UsedName(sb_htrans,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(sb_hready,[Default]), UsedName(hprot,[Default]), UsedName(dma_hburst,[Default]), UsedName(lsu_htrans,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(lsu_hrdata,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_hprot,[Default]), UsedName(sb_hrdata,[Default]), UsedName(sb_hmastlock,[Default]), UsedName(dma_hrdata,[Default]), UsedName(sb_haddr,[Default]), UsedName(sig,[Default]), UsedName(dma_hwrite,[Default]), UsedName(sb_hresp,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]), UsedName(lsu_hwdata,[Default]), UsedName(haddr,[Default]), UsedName(hwrite,[Default]))) invalidates 2 classes due to The quasar_bundle has the following regular definitions changed:
+[debug] 	UsedName(dma_hsize,[Default]), UsedName(lsu_hresp,[Default]), UsedName(hreadyin,[Default]), UsedName(hresp,[Default]), UsedName(lsu_hburst,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(hmastlock,[Default]), UsedName(lsu_hsize,[Default]), UsedName(dma_htrans,[Default]), UsedName(hsel,[Default]), UsedName(dma_ahb,[Default]), UsedName(hready,[Default]), UsedName(sb_hwdata,[Default]), UsedName(lsu_hwrite,[Default]), UsedName(sb_hwrite,[Default]), UsedName(hrdata,[Default]), UsedName(hsize,[Default]), UsedName(ifu_ahb,[Default]), UsedName(bridge_gen,[Default]), UsedName(sb_hburst,[Default]), UsedName(htrans,[Default]), UsedName(sb_ahb,[Default]), UsedName(sb_hprot,[Default]), UsedName(hburst,[Default]), UsedName(lsu_hready,[Default]), UsedName(lsu_ahb,[Default]), UsedName(lsu_hmastlock,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_hsize,[Default]), UsedName(lsu_haddr,[Default]), UsedName(sb_htrans,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(sb_hready,[Default]), UsedName(hprot,[Default]), UsedName(dma_hburst,[Default]), UsedName(lsu_htrans,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(lsu_hrdata,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_hprot,[Default]), UsedName(sb_hrdata,[Default]), UsedName(sb_hmastlock,[Default]), UsedName(dma_hrdata,[Default]), UsedName(sb_haddr,[Default]), UsedName(sig,[Default]), UsedName(dma_hwrite,[Default]), UsedName(sb_hresp,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]), UsedName(lsu_hwdata,[Default]), UsedName(haddr,[Default]), UsedName(hwrite,[Default]).
+[debug] 	> by transitive inheritance: Set(quasar_bundle)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from mem.quasar...
+[debug] Initial set of included nodes: mem.quasar
+[debug] Invalidated by transitive inheritance dependency: Set(mem.quasar)
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] Change NamesChange(mem.quasar,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The mem.quasar has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(mem.quasar)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.decode_exu...
+[debug] Initial set of included nodes: include.decode_exu
+[debug] Invalidated by transitive inheritance dependency: Set(include.decode_exu)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.decode_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.decode_exu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(include.decode_exu)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from pic_ctrl...
+[debug] Initial set of included nodes: pic_ctrl
+[debug] Invalidated by transitive inheritance dependency: Set(pic_ctrl)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(pic_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The pic_ctrl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(pic_ctrl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
 [debug] Invalidating (transitively) by inheritance from lsu.lsu_ecc...
 [debug] Initial set of included nodes: lsu.lsu_ecc
 [debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_ecc)
-[debug] The following member ref dependencies of lsu.lsu_ecc are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_ecc,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(dccm_wdata_ecc_hi_any,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ecc_out_lo_nc,[Default]), UsedName(single_ecc_error_hi_r,[Default]), UsedName(single_ecc_error_lo_r,[Default]), UsedName(sec_data_ecc_lo_r_ff,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(is_ldst_lo_r,[Default]), UsedName(double_ecc_error_hi_any,[Default]), UsedName(desiredName,[Default]), UsedName(stbuf_data_any,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(dccm_rdata_lo_r,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_dccm_m,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(is_ldst_hi_r,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(dma_dccm_wdata_lo,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dccm_rdata_hi_any,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(end_addr_r,[Default]), UsedName(is_ldst_r,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(dccm_data_ecc_lo_r,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(lsu_single_ecc_error_m,[Default]), UsedName(lsu_double_ecc_error_r,[Default]), UsedName(dccm_rdata_lo_any,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(lsu_single_ecc_error_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dma_dccm_wdata_hi,[Default]), UsedName(dccm_rdata_lo_m,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(dccm_rdata_hi_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dccm_wdata_hi_any,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(sec_data_hi_r_ff,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(double_ecc_error_hi_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(dma_dccm_wdata_ecc_lo,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(is_ldst_hi_m,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(sec_data_hi_m,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(sec_data_lo_r_ff,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(ld_single_ecc_error_r_ff,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(is_ldst_m,[Default]), UsedName(lsu_dccm_rden_r,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(dma_dccm_wdata_ecc_hi,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(double_ecc_error_lo_any,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(lsu_dccm_rden_m,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(dccm_data_ecc_hi_m,[Default]), UsedName(lsu_ecc,[Default]), UsedName(is_ldst_lo_any,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(is_ldst_lo_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(is_ldst_hi_any,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(double_ecc_error_lo_m,[Default]), UsedName(sec_data_lo_m,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(addr_in_dccm_r,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(dccm_data_ecc_hi_any,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(sec_data_hi_r,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ldst_dual_r,[Default]), UsedName(single_ecc_error_hi_any,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(lsu_double_ecc_error_m,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(dccm_data_ecc_lo_any,[Default]), UsedName(sec_data_hi_any,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(double_ecc_error_lo_r,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(stbuf_ecc_any,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(ld_single_ecc_error_r,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(dccm_wdata_ecc_lo_any,[Default]), UsedName(dccm_rdata_hi_r,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(ldst_dual_m,[Default]), UsedName(parentModName,[Default]), UsedName(dccm_wdata_lo_any,[Default]), UsedName(getClass,[Default]), UsedName(ecc_out_hi_nc,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(dccm_data_ecc_hi_r,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(dccm_data_ecc_lo_m,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(namingContext$macro$4,[Default]), UsedName(sec_data_ecc_hi_r_ff,[Default]), UsedName(sec_data_lo_r,[Default]), UsedName(double_ecc_error_hi_m,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(lsu;lsu_ecc;init;,[Default]), UsedName(single_ecc_error_lo_any,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(sec_data_lo_any,[Default]), UsedName(dma_dccm_wen,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(end_addr_m,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_ecc has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_ecc,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_ecc has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
 [debug] 	> by transitive inheritance: Set(lsu.lsu_ecc)
 [debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
+[debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.dma_ifc...
-[debug] Initial set of included nodes: include.dma_ifc
-[debug] Invalidated by transitive inheritance dependency: Set(include.dma_ifc)
-[debug] The following member ref dependencies of include.dma_ifc are invalidated:
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_ifc_ctl
-[debug] Change NamesChange(include.dma_ifc,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(include;dma_ifc;init;,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(dma_ifc,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.dma_ifc has the following implicit definitions changed:
+[debug] Invalidating (transitively) by inheritance from include.ahb_out_dma...
+[debug] Initial set of included nodes: include.ahb_out_dma
+[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_out_dma)
+[debug] Change NamesChange(include.ahb_out_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(hmastlock,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(hsize,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(htrans,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(hburst,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(hprot,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(include;ahb_out_dma;init;,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(:=,[Default]), UsedName(ahb_out_dma,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(hwdata,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(haddr,[Default]), UsedName(toNamed,[Default]), UsedName(hwrite,[Default]), UsedName(badConnect,[Default]))) invalidates 1 classes due to The include.ahb_out_dma has the following implicit definitions changed:
 [debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dma_ifc)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_ifc_ctl, dma_ctrl, ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rveven_paritygen...
-[debug] Initial set of included nodes: lib.rveven_paritygen
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rveven_paritygen)
-[debug] Change NamesChange(lib.rveven_paritygen,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(data_in,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(lib;rveven_paritygen;init;,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(parity_out,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rveven_paritygen has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(data_in,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(lib;rveven_paritygen;init;,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(parity_out,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rveven_paritygen)
+[debug] 	> by transitive inheritance: Set(include.ahb_out_dma)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.dctl_busbuff...
-[debug] Initial set of included nodes: include.dctl_busbuff
-[debug] Invalidated by transitive inheritance dependency: Set(include.dctl_busbuff)
-[debug] The following member ref dependencies of include.dctl_busbuff are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] Change NamesChange(include.dctl_busbuff,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(lsu_nonblock_load_data,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(lsu_nonblock_load_data_error,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(dctl_busbuff,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(lsu_nonblock_load_inv_r,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(lsu_nonblock_load_data_tag,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(include;dctl_busbuff;init;,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(lsu_nonblock_load_valid_m,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(lsu_nonblock_load_inv_tag_r,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(lsu_nonblock_load_tag_m,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(lsu_nonblock_load_data_valid,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dctl_busbuff has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dctl_busbuff)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_decode_ctl, lsu.lsu, lsu.lsu_bus_buffer, lsu.lsu_bus_intf)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_lsu_error_pkt_t...
-[debug] Initial set of included nodes: include.el2_lsu_error_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_lsu_error_pkt_t)
-[debug] Change NamesChange(include.el2_lsu_error_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(el2_lsu_error_pkt_t,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(inst_type,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(mscause,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(include;el2_lsu_error_pkt_t;init;,[Default]), UsedName(exc_type,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(single_ecc_error,[Default]), UsedName(bind,[Default]), UsedName(addr,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(exc_valid,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_lsu_error_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_lsu_error_pkt_t)
+[debug] Invalidating (transitively) by inheritance from exu.exu_mul_ctl...
+[debug] Initial set of included nodes: exu.exu_mul_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_mul_ctl)
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(exu.exu_mul_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The exu.exu_mul_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(exu.exu_mul_ctl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_ic_data_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.el2_ic_data_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_ic_data_ext_in_pkt_t)
-[debug] Change NamesChange(include.el2_ic_data_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(include;el2_ic_data_ext_in_pkt_t;init;,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(el2_ic_data_ext_in_pkt_t,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_ic_data_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_ic_data_ext_in_pkt_t)
+[debug] Invalidating (transitively) by inheritance from ifu.ifu_aln_ctl...
+[debug] Initial set of included nodes: ifu.ifu_aln_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_aln_ctl)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu_aln_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_aln_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.ifu_aln_ctl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from dec.CSR_IO...
-[debug] Initial set of included nodes: dec.CSR_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.CSR_IO)
-[debug] Change NamesChange(dec.CSR_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(exu_pmu_i0_br_ataken,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(dec_tlu_meicurpl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(soft_int_sync,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(request_debug_mode_r,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(illegal_r,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(pic_claimid,[Default]), UsedName(mdseac_locked_f,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(update_hit_bit_r,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ext_int_freeze_d1,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(dcsr_single_step_done_f,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(tlu_flush_lower_r_d1,[Default]), UsedName(lsu_pmu_load_external_r,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(trigger_hit_dmode_r_d1,[Default]), UsedName(ebreak_r,[Default]), UsedName(ifu_pmu_bus_error,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(dec_tlu_br0_error_r,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(tlu_flush_path_r_d1,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(internal_dbg_halt_mode_f,[Default]), UsedName(dec;CSR_IO;init;,[Default]), UsedName(rfpc_i0_r,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(inst_acc_second_r,[Default]), UsedName(mie_ns,[Default]), UsedName(dbg_tlu_halted_f,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(iccm_sbecc_r_d1,[Default]), UsedName(exu_npc_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(lsu_pmu_store_external_r,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(dec_tlu_br0_start_error_r,[Default]), UsedName(exu_pmu_i0_pc4,[Default]), UsedName(npc_r_d1,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(exu_pmu_i0_br_misp,[Default]), UsedName(ebreak_to_debug_mode_r_d1,[Default]), UsedName(take_int_timer1_int,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(dcsr,[Default]), UsedName(i0_exception_valid_r,[Default]), UsedName(lsu_i0_exc_r,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(dec_tlu_sideeffect_posted_disable,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(lsu_error_pkt_addr_r,[Default]), UsedName(mstatus_mie_ns,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(exc_or_int_valid_r_d1,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(take_int_timer0_int,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(trigger_hit_r_d1,[Default]), UsedName(inst_acc_r,[Default]), UsedName(nmi_lsu_load_type,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(dec_tlu_ic_diag_pkt,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(timer_int_sync,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dbg_tlu_halted,[Default]), UsedName(ic_perr_r_d1,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ifu_pmu_ic_hit,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(ebreak_to_debug_mode_r,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(lsu_pmu_bus_busy,[Default]), UsedName(dma_pmu_dccm_read,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(mstatus,[Default]), UsedName(ifu_pmu_fetch_stall,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(i0_valid_wb,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(dec_tlu_dec_clk_override,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(mdseac_locked_ns,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(debug_halt_req_f,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(dma_pmu_dccm_write,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(lsu_pmu_bus_trxn,[Default]), UsedName(enter_debug_halt_req,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(lsu_i0_exc_r_d1,[Default]), UsedName(rvclkhdr,[Default]), UsedName(lsu_idle_any_f,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_dma_qos_prty,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dpc,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(force_halt,[Default]), UsedName(take_timer_int,[Default]), UsedName(lsu_single_ecc_error_r_d1,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mtvec,[Default]), UsedName(dcsr_single_step_running_f,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(i0_exception_valid_r_d1,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(dec_tlu_external_ldfwd_disable,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(i0_trigger_hit_r,[Default]), UsedName(exc_or_int_valid_r,[Default]), UsedName(take_ext_int,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(take_nmi,[Default]), UsedName(npc_r,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(tlu_flush_lower_r,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(ifu_ic_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(ifu_pmu_bus_trxn,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(csr_wr_clk,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(ecall_r,[Default]), UsedName(==,[Default]), UsedName(ifu_ic_debug_rd_data_valid,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(nmi_lsu_store_type,[Default]), UsedName(CSR_IO,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(internal_dbg_halt_mode,[Default]), UsedName(csr_pkt,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_tlu_wb_coalescing_disable,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mret_r,[Default]), UsedName(widthOption,[Default]), UsedName(mexintpend,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(allow_dbg_halt_csr_write,[Default]), UsedName(dec_tlu_bpred_disable,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(reset_delayed,[Default]), UsedName(tlu_i0_commit_cmt,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(pic_pl,[Default]), UsedName(lsu_pmu_bus_misaligned,[Default]), UsedName(fw_halt_req,[Default]), UsedName(dma_pmu_any_write,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(lsu_exc_valid_r,[Default]), UsedName(mepc_trigger_hit_sel_pc_r,[Default]), UsedName(e4e5_int_clk,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(interrupt_valid_r_d1,[Default]), UsedName(dma_pmu_any_read,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(request_debug_mode_done,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(mtdata1_t,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(internal_dbg_halt_mode_f2,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(dec_tlu_meipt,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(take_ext_int_start,[Default]), UsedName(lsu_pmu_bus_error,[Default]), UsedName(nmi_int_detected_f,[Default]), UsedName(lsu_imprecise_error_store_any,[Default]), UsedName(ifu_pmu_bus_busy,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(ifu_pmu_ic_miss,[Default]), UsedName(ifu_miss_state_idle_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_imprecise_error_load_any,[Default]), UsedName(mepc,[Default]), UsedName(debug_halt_req,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(dec_tlu_meihap,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(exc_cause_wb,[Default]), UsedName($asInstanceOf,[Default]), UsedName(mip,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(dec_tlu_flush_noredir_r_d1,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(lsu_imprecise_error_addr_any,[Default]), UsedName(interrupt_valid_r,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(exc_cause_r,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.CSR_IO has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.CSR_IO)
+[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl_IO...
+[debug] Initial set of included nodes: dec.dec_tlu_ctl_IO
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl_IO)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_tlu_ctl_IO,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_tlu_ctl_IO has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_tlu_ctl_IO)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_decode_csr_read_IO...
-[debug] Initial set of included nodes: dec.el2_dec_decode_csr_read_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_decode_csr_read_IO)
-[debug] Change NamesChange(dec.el2_dec_decode_csr_read_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(dec;el2_dec_decode_csr_read_IO;init;,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(csr_pkt,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(el2_dec_decode_csr_read_IO,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_decode_csr_read_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_decode_csr_read_IO)
+[debug] Invalidating (transitively) by inheritance from dec.dec_timer_ctl...
+[debug] Initial set of included nodes: dec.dec_timer_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_timer_ctl)
+[debug] Change NamesChange(dec.dec_timer_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_timer_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_timer_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from exu.exu_div_ctl...
+[debug] Initial set of included nodes: exu.exu_div_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_div_ctl)
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(exu.exu_div_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu_div_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(exu.exu_div_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.write_addr...
+[debug] Initial set of included nodes: include.write_addr
+[debug] Invalidated by transitive inheritance dependency: Set(include.write_addr)
+[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default]))
+[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default]))
+[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default]))
+[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(write_addr,[Default]))
+[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]), UsedName(write_addr,[Default]))
+[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ne,[Default]), UsedName(write_addr,[Default]))
+[debug] Change NamesChange(include.write_addr,ModifiedNames(changes = UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(write_addr,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName(include;write_addr;init;,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.write_addr has the following regular definitions changed:
+[debug] 	UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(write_addr,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName(include;write_addr;init;,[Default]), UsedName($asInstanceOf,[Default]).
+[debug] 	> by transitive inheritance: Set(include.write_addr)
+[debug] 	> 
+[debug] 	> by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl...
+[debug] Initial set of included nodes: dec.dec_tlu_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dec.dec_tlu_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The dec.dec_tlu_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.dec_tlu_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_stbuf...
+[debug] Initial set of included nodes: lsu.lsu_stbuf
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_stbuf)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_stbuf,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The lsu.lsu_stbuf has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_stbuf)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu...
+[debug] Initial set of included nodes: lsu.lsu
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu)
 [debug] 	> 
 [debug] 	> 
 [debug]         
@@ -767,1872 +563,134 @@
 [debug] Including include.decode_exu by lib.lib
 [debug] Including dma_ctrl by lib.lib
 [debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl)
-[debug] The following member ref dependencies of lsu.lsu_clkdomain are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of exu.exu are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of dec.dec_decode_ctl are invalidated:
-[debug] 	dec.dec
-[debug] The following member ref dependencies of lsu.lsu_trigger are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of include.exu_bp are invalidated:
-[debug] 	exu.exu
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_bp_ctl
-[debug] 	quasar
-[debug] The following member ref dependencies of dec.dec_gpr_ctl are invalidated:
-[debug] 	dec.dec
-[debug] The following member ref dependencies of lsu.lsu_addrcheck are invalidated:
-[debug] 	lsu.lsu_lsc_ctl
-[debug] The following member ref dependencies of mem.quasar are invalidated:
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of include.dec_aln are invalidated:
-[debug] 	dec.dec
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_aln_ctl
-[debug] The following member ref dependencies of ifu.ifu are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of include.aln_ib are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_ib_ctl
-[debug] 	dec.dec_ib_ctl_IO
-[debug] 	ifu.ifu_aln_ctl
-[debug] The following member ref dependencies of dec.dec_tlu_ctl_IO are invalidated:
-[debug] 	dec.dec
-[debug] The following member ref dependencies of exu.exu_div_ctl are invalidated:
-[debug] 	exu.exu
-[debug] The following member ref dependencies of lsu.lsu are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of dec.dec_tlu_ctl are invalidated:
-[debug] 	dec.dec
-[debug] The following member ref dependencies of lib.ahb_to_axi4 are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of lib.axi4_to_ahb are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of quasar are invalidated:
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of lsu.lsu_lsc_ctl are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of pic_ctrl are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of include.write_data are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] The following member ref dependencies of exu.exu_alu_ctl are invalidated:
-[debug] 	exu.exu
-[debug] The following member ref dependencies of include.tlu_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	exu.exu
-[debug] 	quasar
-[debug] The following member ref dependencies of dec.dec_IO are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of include.iccm_mem are invalidated:
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	mem.Mem_bundle
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of quasar_bundle are invalidated:
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of lsu.lsu_ecc are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of include.write_addr are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] The following member ref dependencies of ifu.mem_ctl_io are invalidated:
-[debug] 	ifu.ifu
-[debug] The following member ref dependencies of lsu.lsu_bus_buffer are invalidated:
-[debug] 	lsu.lsu_bus_intf
-[debug] The following member ref dependencies of include.write_resp are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] The following member ref dependencies of include.dec_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	exu.exu
-[debug] 	quasar
-[debug] The following member ref dependencies of include.read_data are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] The following member ref dependencies of ifu.ifu_aln_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] The following member ref dependencies of dbg.dbg are invalidated:
-[debug] 	quasar
-[debug] The following member ref dependencies of include.ic_mem are invalidated:
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	mem.Mem_bundle
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of lsu.lsu_bus_intf are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of exu.exu_mul_ctl are invalidated:
-[debug] 	exu.exu
-[debug] The following member ref dependencies of dec.dec_trigger are invalidated:
-[debug] 	dec.dec
-[debug] The following member ref dependencies of lsu.lsu_dccm_ctl are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of ifu.ifu_compress_ctl are invalidated:
-[debug] 	ifu.ifu_aln_ctl
-[debug] The following member ref dependencies of ifu.ifu_bp_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] The following member ref dependencies of mem.Mem_bundle are invalidated:
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of include.dctl_busbuff are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] The following member ref dependencies of include.read_addr are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] The following member ref dependencies of include.axi_channels are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of dec.dec_dec_ctl are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] The following member ref dependencies of lsu.lsu_stbuf are invalidated:
-[debug] 	lsu.lsu
-[debug] The following member ref dependencies of mem.mem_lsu are invalidated:
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_dccm_ctl
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of include.dec_mem_ctrl are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	quasar
-[debug] The following member ref dependencies of ifu.ifu_mem_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] The following member ref dependencies of ifu.ifu_ifc_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] The following member ref dependencies of include.decode_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] The following member ref dependencies of lib.lib are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_dec_ctl
-[debug] 	dec.dec_decode_ctl
-[debug] 	dec.dec_gpr_ctl
-[debug] 	dec.dec_timer_ctl
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	dec.dec_trigger
-[debug] 	dma_ctrl
-[debug] 	exu.exu
-[debug] 	exu.exu_alu_ctl
-[debug] 	exu.exu_div_ctl
-[debug] 	exu.exu_mul_ctl
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_aln_ctl
-[debug] 	ifu.ifu_bp_ctl
-[debug] 	ifu.ifu_compress_ctl
-[debug] 	ifu.ifu_ifc_ctl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	include.aln_ib
-[debug] 	include.axi_channels
-[debug] 	include.dctl_busbuff
-[debug] 	include.dec_aln
-[debug] 	include.dec_exu
-[debug] 	include.dec_mem_ctrl
-[debug] 	include.decode_exu
-[debug] 	include.exu_bp
-[debug] 	include.ic_mem
-[debug] 	include.iccm_mem
-[debug] 	include.read_addr
-[debug] 	include.read_data
-[debug] 	include.tlu_exu
-[debug] 	include.write_addr
-[debug] 	include.write_data
-[debug] 	include.write_resp
-[debug] 	lib.ahb_to_axi4
-[debug] 	lib.axi4_to_ahb
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_addrcheck
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] 	lsu.lsu_clkdomain
-[debug] 	lsu.lsu_dccm_ctl
-[debug] 	lsu.lsu_ecc
-[debug] 	lsu.lsu_lsc_ctl
-[debug] 	lsu.lsu_stbuf
-[debug] 	lsu.lsu_trigger
-[debug] 	mem.Mem_bundle
-[debug] 	mem.blackbox_mem
-[debug] 	mem.mem_lsu
-[debug] 	mem.quasar
-[debug] 	pic_ctrl
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] The following member ref dependencies of dma_ctrl are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(lib.lib,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lib,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(getClass,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 63 classes due to The lib.lib has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_clkdomain, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_clkdomain, dec.dec, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, dec.dec_ib_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.test...
-[debug] Initial set of included nodes: dec.test
-[debug] Invalidated by transitive inheritance dependency: Set(dec.test)
-[debug] Change NamesChange(dec.test,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(dec;test;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(main,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(in,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(test,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(args,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.test has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(dec;test;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(main,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(in,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(test,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(args,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.test)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dbg_dctl...
-[debug] Initial set of included nodes: include.dbg_dctl
-[debug] Invalidated by transitive inheritance dependency: Set(include.dbg_dctl)
-[debug] The following member ref dependencies of include.dbg_dctl are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	dma_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(include.dbg_dctl,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(include;dbg_dctl;init;,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dbg_dctl,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(dbg_cmd_wrdata,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dbg_dctl has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dbg_dctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_decode_ctl, quasar, dbg.dbg, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.br_tlu_pkt_t...
-[debug] Initial set of included nodes: include.br_tlu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.br_tlu_pkt_t)
-[debug] The following member ref dependencies of include.br_tlu_pkt_t are invalidated:
-[debug] 	dec.dec_tlu_ctl
-[debug] 	ifu.ifu_bp_ctl
-[debug] Change NamesChange(include.br_tlu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(br_tlu_pkt_t,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(middle,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(include;br_tlu_pkt_t;init;,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 3 classes due to The include.br_tlu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.br_tlu_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_tlu_ctl, ifu.ifu_bp_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.gpr_exu...
-[debug] Initial set of included nodes: include.gpr_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.gpr_exu)
-[debug] The following member ref dependencies of include.gpr_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_gpr_ctl
-[debug] 	dec.dec_gpr_ctl_IO
-[debug] 	exu.exu
-[debug] Change NamesChange(include.gpr_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(include;gpr_exu;init;,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(gpr_i0_rs2_d,[Default]), UsedName(gpr_exu,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(gpr_i0_rs1_d,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.gpr_exu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.gpr_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_gpr_ctl_IO, dec.dec_gpr_ctl, dec.dec, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvecc_decode_64...
-[debug] Initial set of included nodes: lib.rvecc_decode_64
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvecc_decode_64)
-[debug] Change NamesChange(lib.rvecc_decode_64,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(ecc_in,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvsyncss,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(ecc_error,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName(lib;rvecc_decode_64;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(ecc_check,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvecc_decode_64 has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(ecc_in,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvsyncss,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(ecc_error,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName(lib;rvecc_decode_64;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(ecc_check,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvecc_decode_64)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.axi_channels...
-[debug] Initial set of included nodes: include.axi_channels
-[debug] Invalidated by transitive inheritance dependency: Set(include.axi_channels)
-[debug] The following member ref dependencies of include.axi_channels are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(include.axi_channels,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUS_TAG,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(include;axi_channels;init;,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(axi_channels,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(r,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(aw,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ar,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(w,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(b,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(<init>$default$1,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 12 classes due to The include.axi_channels has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.axi_channels)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu, lsu.lsu, quasar, quasar_bundle, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, dbg.dbg, lsu.lsu_bus_intf, ifu.ifu_mem_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rveven_paritycheck...
-[debug] Initial set of included nodes: lib.rveven_paritycheck
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rveven_paritycheck)
-[debug] Change NamesChange(lib.rveven_paritycheck,ModifiedNames(changes = UsedName(parity_in,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(data_in,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(parity_err,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName(lib;rveven_paritycheck;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rveven_paritycheck has the following regular definitions changed:
-[debug] 	UsedName(parity_in,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(data_in,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(parity_err,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName(lib;rveven_paritycheck;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rveven_paritycheck)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.iccm_mem...
-[debug] Initial set of included nodes: include.iccm_mem
-[debug] Invalidated by transitive inheritance dependency: Set(include.iccm_mem)
-[debug] The following member ref dependencies of include.iccm_mem are invalidated:
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	ifu.mem_ctl_io
-[debug] 	mem.Mem_bundle
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(include.iccm_mem,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(rden,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(buf_correct_ecc,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(rd_data_ecc,[Default]), UsedName(iccm_mem,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(rw_addr,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(wren,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(correction_state,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(wr_size,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(rd_data,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(wr_data,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(include;iccm_mem;init;,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 8 classes due to The include.iccm_mem has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.iccm_mem)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu, quasar, quasar_bundle, ifu.mem_ctl_io, quasar_wrapper, mem.Mem_bundle, ifu.ifu_mem_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_clkdomain...
-[debug] Initial set of included nodes: lsu.lsu_clkdomain
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain)
-[debug] The following member ref dependencies of lsu.lsu_clkdomain are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_clkdomain,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(lsu_c1_d_clken_q,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(lsu_free_c1_clken,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(lsu_free_c2_clk,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(stbuf_reqvld_any,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(lsu_bus_buffer_empty_any,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(lsu;lsu_clkdomain;init;,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(lsu_bus_obuf_c1_clken,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_dccm_m,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_bus_buf_c1_clk,[Default]), UsedName(lsu_pkt_d,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(lsu_busm_clk,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(lsu_stbuf_empty_any,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(lsu_c1_r_clk,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(lsu_stbuf_c1_clk,[Default]), UsedName(lsu_c1_m_clken,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(namingContext$macro$5,[Default]), UsedName(lsu_store_c1_m_clken,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(lsu_busreq_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(dma_dccm_req,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(lsu_store_c1_r_clk,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_c2_r_clken,[Default]), UsedName(lsu_c1_m_clken_q,[Default]), UsedName(lsu_store_c1_r_clken,[Default]), UsedName(hashCode,[Default]), UsedName(lsu_stbuf_c1_clken,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(lsu_bus_ibuf_c1_clken,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(lsu_c2_m_clk,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(lsu_c2_m_clken,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(lsu_free_c2_clken,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(lsu_bus_buffer_pend_any,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(lsu_clkdomain,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(lsu_c1_r_clken,[Default]), UsedName(lsu_c1_m_clk,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(lsu_store_c1_m_clk,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(lsu_c1_r_clken_q,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(lsu_free_c1_clken_q,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(lsu_bus_buf_c1_clken,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(lsu_bus_obuf_c1_clk,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(stbuf_reqvld_flushed_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(lsu_bus_ibuf_c1_clk,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(ldst_stbuf_reqvld_r,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(lsu_c1_d_clken,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_clkdomain has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_clkdomain)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_pkt_t...
-[debug] Initial set of included nodes: include.dec_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_pkt_t)
-[debug] The following member ref dependencies of include.dec_pkt_t are invalidated:
-[debug] 	dec.dec_dec_ctl
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(include.dec_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(imm12,[Default]), UsedName(pc,[Default]), UsedName(ignoreSeq,[Default]), UsedName(presync,[Default]), UsedName(word,[Default]), UsedName(add,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(rs1_sign,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(imm20,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(mret,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(by,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(dec_pkt_t,[Default]), UsedName(pm_alu,[Default]), UsedName(isSynthesizable,[Default]), UsedName(ebreak,[Default]), UsedName(alu,[Default]), UsedName(bind,[Default]), UsedName(rs1,[Default]), UsedName(csr_set,[Default]), UsedName(rem,[Default]), UsedName(rs2_sign,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(slt,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(beq,[Default]), UsedName(lor,[Default]), UsedName(ref,[Default]), UsedName(half,[Default]), UsedName(do_asUInt,[Default]), UsedName(sll,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(shimm5,[Default]), UsedName(rs2,[Default]), UsedName(mul,[Default]), UsedName(srl,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(low,[Default]), UsedName(ecall,[Default]), UsedName(csr_clr,[Default]), UsedName(sra,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(jal,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(land,[Default]), UsedName(topBindingOpt,[Default]), UsedName(csr_read,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(fence,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(bge,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(div,[Default]), UsedName(blt,[Default]), UsedName(_makeLit,[Default]), UsedName(bne,[Default]), UsedName(notify,[Default]), UsedName(postsync,[Default]), UsedName(csr_write,[Default]), UsedName(csr_imm,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(fence_i,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(include;dec_pkt_t;init;,[Default]), UsedName(lsu,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(condbr,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lxor,[Default]), UsedName(toTarget,[Default]), UsedName(sub,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 3 classes due to The include.dec_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_dec_ctl, dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_ccm_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.el2_ccm_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_ccm_ext_in_pkt_t)
-[debug] Change NamesChange(include.el2_ccm_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(include;el2_ccm_ext_in_pkt_t;init;,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(el2_ccm_ext_in_pkt_t,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_ccm_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_ccm_ext_in_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.cache_debug_pkt_t...
-[debug] Initial set of included nodes: include.cache_debug_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.cache_debug_pkt_t)
-[debug] The following member ref dependencies of include.cache_debug_pkt_t are invalidated:
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec_tlu_ctl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	quasar
-[debug] Change NamesChange(include.cache_debug_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(include;cache_debug_pkt_t;init;,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(cache_debug_pkt_t,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(icache_dicawics,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(icache_wrdata,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(icache_rd_valid,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(icache_wr_valid,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.cache_debug_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.cache_debug_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_tlu_ctl, quasar, dec.csr_tlu, dec.CSR_IO, ifu.ifu_mem_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.el2_ifu...
-[debug] Initial set of included nodes: ifu.el2_ifu
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.el2_ifu)
-[debug] Change NamesChange(ifu.el2_ifu,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ifu;el2_ifu;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(el2_ifu,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The ifu.el2_ifu has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ifu;el2_ifu;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(el2_ifu,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(ifu.el2_ifu)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.ifu_ifc_ctl...
-[debug] Initial set of included nodes: ifu.ifu_ifc_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_ifc_ctl)
-[debug] The following member ref dependencies of ifu.ifu_ifc_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] Change NamesChange(ifu.ifu_ifc_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(sel_btb_addr_bf,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(goto_idle,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ic_hit_f,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(line_wrap,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ifu_bp_btb_target_f,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(fb_left,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_ifc,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dma_iccm_stall_any_f,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(flush_fb,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(wfm,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(wfm_E,[Default]), UsedName(rvbradder,[Default]), UsedName(exu_flush_path_final,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(fb_write_f,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(fb_right2,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(fb_write_ns,[Default]), UsedName(getPorts,[Default]), UsedName(ifc_iccm_access_bf,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(fetch_addr_next,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(ic_dma_active,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(fetch_bf_en,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ifu_fb_consume2,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(fetch_E,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ifu_bp_hit_taken_f,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(next_state_0,[Default]), UsedName(idle,[Default]), UsedName(hashCode,[Default]), UsedName(address_upper,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(fetch_addr_next_0,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(ifc_fetch_req_bf,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ifu;ifu_ifc_ctl;init;,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(state,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(next_state_1,[Default]), UsedName(fb_full_f,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(ic_write_stall,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(idle_E,[Default]), UsedName(gated_latch,[Default]), UsedName(ifu_ifc_ctl,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(ifc_fetch_addr_bf,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(ifu_fb_consume1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(dma_stall,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(sel_last_addr_bf,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(fb_right,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(ifc_region_acc_fault_bf,[Default]), UsedName(fetch_addr_bf,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(iccm_acc_in_range_bf,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(ifc_dma_access_ok,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(leave_idle,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ifc_fetch_addr_f,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(dma_ifc,[Default]), UsedName(ifu_ic_mb_empty,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ifc_fetch_req_bf_raw,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ifc_fetch_uncacheable_bf,[Default]), UsedName(mb_empty_mod,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(sel_next_addr_bf,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(miss_f,[Default]), UsedName(ifc_fetch_req_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(fb_full_f_ns,[Default]), UsedName(active_clk,[Default]), UsedName(stall_E,[Default]), UsedName(miss_a,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(iccm_acc_in_region_bf,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The ifu.ifu_ifc_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.ifu_ifc_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl...
-[debug] Initial set of included nodes: dec.dec_tlu_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl)
-[debug] The following member ref dependencies of dec.dec_tlu_ctl are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_tlu_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(i_cpu_run_req_sync,[Default]), UsedName(take_nmi_r_d1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ext_int_ready,[Default]), UsedName(lsu_i0_exc_r_raw,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(lsu_exc_acc_r,[Default]), UsedName(MIP_MEIP,[Default]), UsedName(MIE_MTIE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(iccm_repair_state_d1,[Default]), UsedName(MEM_CAL,[Default]), UsedName(e4_valid,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(e5_valid,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(soft_int_sync,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(ic_perr_r,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(resume_ack_ns,[Default]), UsedName(request_debug_mode_r,[Default]), UsedName(MIP_MITIP1,[Default]), UsedName(illegal_r,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(reset_detected,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(iccm_repair_state_rfnpc,[Default]), UsedName(i0_trigger_hit_raw_r,[Default]), UsedName(mdseac_locked_f,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(request_debug_mode_done_f,[Default]), UsedName(internal_pmu_fw_halt_mode,[Default]), UsedName(dbg_run_state_ns,[Default]), UsedName(debug_halt_req_d1,[Default]), UsedName(debug_brkpt_status_ns,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(nmi_int_detected,[Default]), UsedName(internal_dbg_halt_timers,[Default]), UsedName(e4e5_valid,[Default]), UsedName(reset_detect,[Default]), UsedName(update_hit_bit_r,[Default]), UsedName(ext_int_freeze,[Default]), UsedName(rvecc_encode,[Default]), UsedName(enter_pmu_fw_halt_req,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ce_int_ready,[Default]), UsedName(ext_int_freeze_d1,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(dbg_cmd_done_ns,[Default]), UsedName(MIP_MITIP0,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(dcsr_single_step_done_f,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(tlu_flush_lower_r_d1,[Default]), UsedName(lsu_pmu_load_external_r,[Default]), UsedName(ignore_ext_int_due_to_lsu_stall,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(synchronous_flush_r,[Default]), UsedName(trigger_hit_dmode_r_d1,[Default]), UsedName(ebreak_r,[Default]), UsedName(rvlsadder,[Default]), UsedName(take_ext_int_start_d2,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(dec_tlu_br0_error_r,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(trigger_execute,[Default]), UsedName(tlu_flush_path_r_d1,[Default]), UsedName(mpc_debug_halt_req_sync_raw,[Default]), UsedName(vectored_path,[Default]), UsedName(lsu_exc_st_r,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(dec_pause_state_f,[Default]), UsedName(MTDATA1_MATCH,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(internal_dbg_halt_mode_f,[Default]), UsedName(rfpc_i0_r,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(inst_acc_second_r,[Default]), UsedName(mie_ns,[Default]), UsedName(dbg_tlu_halted_f,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(iccm_repair_state_ns,[Default]), UsedName(iccm_sbecc_r_d1,[Default]), UsedName(lsu_single_ecc_error_r,[Default]), UsedName(circuitName,[Default]), UsedName(i0_iside_trigger_has_pri_r,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(MIP_MSIP,[Default]), UsedName(int_timer0_int_possible,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(int_timer1_int_hold,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(nmi_lsu_detected,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(mpc_debug_run_ack_ns,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_pmu_store_external_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(debug_brkpt_status_f,[Default]), UsedName(take_ce_int,[Default]), UsedName(dec_tlu_br0_start_error_r,[Default]), UsedName(npc_r_d1,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(i_cpu_halt_req_sync,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(int_timer0_int_ready,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(block_interrupts,[Default]), UsedName(ebreak_to_debug_mode_r_d1,[Default]), UsedName(take_int_timer1_int,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(dcsr_single_step_done,[Default]), UsedName(i0_exception_valid_r,[Default]), UsedName(lsu_i0_exc_r,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(dbg_halt_req_held,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(MTDATA1_ACTION,[Default]), UsedName(lsu_error_pkt_addr_r,[Default]), UsedName(mstatus_mie_ns,[Default]), UsedName(dec_tlu_flush_pause_r_d1,[Default]), UsedName(pmu_fw_tlu_halted_f,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(exc_or_int_valid_r_d1,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(dbg_halt_req_held_ns,[Default]), UsedName(take_int_timer0_int,[Default]), UsedName(MTDATA1_DMODE,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(tlu_flush_path_r,[Default]), UsedName(trigger_hit_r_d1,[Default]), UsedName(inst_acc_r,[Default]), UsedName(nmi_lsu_load_type,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(mpc_debug_run_req_sync,[Default]), UsedName(timer_int_sync,[Default]), UsedName(dec_tlu_mpc_halted_only_ns,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dbg_tlu_halted,[Default]), UsedName(ic_perr_r_d1,[Default]), UsedName(mpc_debug_run_req_sync_pulse,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(sel_npc_resume,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec;dec_tlu_ctl;init;,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(trigger_action,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(MTDATA1_ST,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(MCPC,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(MTDATA1_SEL,[Default]), UsedName(sel_fir_addr,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(iccm_sbecc_r,[Default]), UsedName(timer_int_ready,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(ebreak_to_debug_mode_r,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(trigger_data,[Default]), UsedName(i_cpu_run_req_d1_raw,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(mstatus,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(dec_tlu_ctl,[Default]), UsedName(nameIds,[Default]), UsedName(dbg_halt_state_f,[Default]), UsedName(mpc_debug_halt_req_sync,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(i0_valid_wb,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(debug_mode_status,[Default]), UsedName(finalize,[Default]), UsedName(pmu_fw_halt_req_ns,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(mpc_debug_run_ack_f,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(request_debug_mode_r_d1,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(mdseac_locked_ns,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(trigger_enabled,[Default]), UsedName(debug_resume_req,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(debug_halt_req_f,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(pause_expired_wb,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(MTDATA1_LD,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(inst_acc_r_raw,[Default]), UsedName(enter_debug_halt_req,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(halt_taken,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(lsu_i0_exc_r_d1,[Default]), UsedName(rvclkhdr,[Default]), UsedName(lsu_idle_any_f,[Default]), UsedName(mpc_debug_halt_ack_f,[Default]), UsedName(valid_csr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(i0trigger_qual_r,[Default]), UsedName(dpc,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(conditionally_illegal,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(force_halt,[Default]), UsedName(take_timer_int,[Default]), UsedName(lsu_single_ecc_error_r_d1,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(csr,[Default]), UsedName(dec_tlu_br0_v_r,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mtvec,[Default]), UsedName(dcsr_single_step_running_f,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(i0_exception_valid_r_d1,[Default]), UsedName(lsu_exc_valid_r_raw,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(i0_trigger_action_r,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(internal_pmu_fw_halt_mode_f,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(nmi_lsu_load_type_f,[Default]), UsedName(clk_override,[Default]), UsedName(MIE_MITIE1,[Default]), UsedName(take_ext_int_start_d3,[Default]), UsedName(MSTATUS_MIE,[Default]), UsedName(i0_trigger_hit_r,[Default]), UsedName(exc_or_int_valid_r,[Default]), UsedName(take_ext_int,[Default]), UsedName(core_empty,[Default]), UsedName(gated_latch,[Default]), UsedName(take_nmi,[Default]), UsedName(npc_r,[Default]), UsedName(dec_tlu_wr_pause_r_d1,[Default]), UsedName(int_timer0_int_hold,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(int_timer_stalled,[Default]), UsedName(mpc_debug_halt_req_sync_f,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(trigger_store,[Default]), UsedName(syncro_ff,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(MIP_MCEIP,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(MIE_MCEIE,[Default]), UsedName(dcsr_single_step_running,[Default]), UsedName(MIE_MSIE,[Default]), UsedName(tlu_flush_lower_r,[Default]), UsedName(int_timer0_int_hold_f,[Default]), UsedName(_onModuleClose,[Default]), UsedName(soft_int_ready,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(DCSR_STOPC,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(csr_read,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(pause_expired_r,[Default]), UsedName(csr_wr_clk,[Default]), UsedName(PIC_BITS,[Default]), UsedName(nmi_int_delayed,[Default]), UsedName(mpc_run_state_f,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(i0_trigger_eval_r,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(ecall_r,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(flush_clkvalid,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(nmi_lsu_store_type,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(internal_dbg_halt_mode,[Default]), UsedName(csr_pkt,[Default]), UsedName(getModulePorts,[Default]), UsedName(cpu_halt_ack,[Default]), UsedName(MTDATA1_M_ENABLED,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(pmu_fw_tlu_halted,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(mhwakeup_ready,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(i_cpu_run_req_d1,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(MIP_MTIP,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(i0_lsu_trigger_has_pri_r,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mret_r,[Default]), UsedName(mpc_halt_state_f,[Default]), UsedName(nmi_lsu_store_type_f,[Default]), UsedName(dbg_halt_req_final,[Default]), UsedName(cpu_run_ack,[Default]), UsedName(i_cpu_run_req_sync_qual,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(e4e5_clk,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(interrupt_path,[Default]), UsedName(debug_resume_req_f,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(lsu_exc_ma_r,[Default]), UsedName(pmu_fw_halt_req_f,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(lsu_i0_rfnpc_r,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(fence_i_r,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(take_ext_int_start_d1,[Default]), UsedName(getRef,[Default]), UsedName(allow_dbg_halt_csr_write,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ext_halt_pulse,[Default]), UsedName(reset_delayed,[Default]), UsedName(tlu_i0_commit_cmt,[Default]), UsedName(i_cpu_halt_req_sync_qual,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(fw_halt_req,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(nmi_int_sync,[Default]), UsedName(mpc_run_state_ns,[Default]), UsedName(lsu_exc_valid_r,[Default]), UsedName(mepc_trigger_hit_sel_pc_r,[Default]), UsedName(mpc_debug_halt_ack_ns,[Default]), UsedName(e4e5_int_clk,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(interrupt_valid_r_d1,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(take_reset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(request_debug_mode_done,[Default]), UsedName(compileOptions,[Default]), UsedName(i0_trigger_r,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(mtdata1_t,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(cpu_halt_status,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(internal_dbg_halt_mode_f2,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(lsu_r_wb_clk,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(take_ext_int_start,[Default]), UsedName(nmi_int_detected_f,[Default]), UsedName(DCSR_EBREAKM,[Default]), UsedName(debug_brkpt_valid,[Default]), UsedName(take_soft_int,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(ifu_miss_state_idle_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_exc_valid_r_d1,[Default]), UsedName(halt_taken_f,[Default]), UsedName(int_timer1_int_hold_f,[Default]), UsedName(mepc,[Default]), UsedName(debug_halt_req,[Default]), UsedName(mpc_halt_state_ns,[Default]), UsedName(fast_int_meicpct,[Default]), UsedName(mpc_debug_halt_req_sync_pulse,[Default]), UsedName(MIE_MITIE0,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(exc_cause_wb,[Default]), UsedName(dbg_run_state_f,[Default]), UsedName(int_timer1_int_possible,[Default]), UsedName($asInstanceOf,[Default]), UsedName(int_timer1_int_ready,[Default]), UsedName(mip,[Default]), UsedName(wait,[Default]), UsedName(i_cpu_halt_req_d1,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(dec_tlu_flush_noredir_r_d1,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(int_timers,[Default]), UsedName(take_halt,[Default]), UsedName(debug_halt_req_ns,[Default]), UsedName(i0_trigger_chain_masked_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(trigger_hit_dmode_r,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(dbg_halt_state_ns,[Default]), UsedName(MTDATA1_CHAIN,[Default]), UsedName(interrupt_valid_r,[Default]), UsedName(DCSR_STEP,[Default]), UsedName(tlu_i0_kill_writeb_r,[Default]), UsedName(sel_npc_r,[Default]), UsedName(mpc_debug_run_req_sync_f,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(exc_cause_r,[Default]), UsedName(DCSR_STEPIE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(MTDATA1_EXE,[Default]), UsedName(MIE_MEIE,[Default]))) invalidates 2 classes due to The dec.dec_tlu_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_tlu_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from mem.blackbox_mem...
-[debug] Initial set of included nodes: mem.blackbox_mem
-[debug] Invalidated by transitive inheritance dependency: Set(mem.blackbox_mem)
-[debug] Change NamesChange(mem.blackbox_mem,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(blackbox_mem,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(mem;blackbox_mem;init;,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(it,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The mem.blackbox_mem has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(mem.blackbox_mem)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvecc_encode_64...
-[debug] Initial set of included nodes: lib.rvecc_encode_64
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvecc_encode_64)
-[debug] Change NamesChange(lib.rvecc_encode_64,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(lib;rvecc_encode_64;init;,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvecc_encode_64 has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(lib;rvecc_encode_64;init;,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvecc_encode_64)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_rets_pkt_t...
-[debug] Initial set of included nodes: include.el2_rets_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_rets_pkt_t)
-[debug] Change NamesChange(include.el2_rets_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(include;el2_rets_pkt_t;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(pc0_ret,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(pc0_call,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(pc0_pc4,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(el2_rets_pkt_t,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_rets_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_rets_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_gpr_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_gpr_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_gpr_ctl)
-[debug] Change NamesChange(dec.el2_dec_gpr_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(w0v,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(w2v,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(dec;el2_dec_gpr_ctl;init;,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(gpr_wr_en,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(w1v,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(gpr_out,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(el2_dec_gpr_ctl,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(gpr_in,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_gpr_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_gpr_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_CSR_IO...
-[debug] Initial set of included nodes: dec.el2_CSR_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_CSR_IO)
-[debug] Change NamesChange(dec.el2_CSR_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(exu_pmu_i0_br_ataken,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(el2_CSR_IO,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(dec_tlu_meicurpl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(soft_int_sync,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(request_debug_mode_r,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(illegal_r,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(pic_claimid,[Default]), UsedName(mdseac_locked_f,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(update_hit_bit_r,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ext_int_freeze_d1,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(dcsr_single_step_done_f,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(tlu_flush_lower_r_d1,[Default]), UsedName(lsu_pmu_load_external_r,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(trigger_hit_dmode_r_d1,[Default]), UsedName(ebreak_r,[Default]), UsedName(ifu_pmu_bus_error,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(dec_tlu_br0_error_r,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(tlu_flush_path_r_d1,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(internal_dbg_halt_mode_f,[Default]), UsedName(rfpc_i0_r,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(inst_acc_second_r,[Default]), UsedName(mie_ns,[Default]), UsedName(dbg_tlu_halted_f,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(dec;el2_CSR_IO;init;,[Default]), UsedName(parentPathName,[Default]), UsedName(iccm_sbecc_r_d1,[Default]), UsedName(exu_npc_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(lsu_pmu_store_external_r,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(dec_tlu_br0_start_error_r,[Default]), UsedName(exu_pmu_i0_pc4,[Default]), UsedName(npc_r_d1,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(exu_pmu_i0_br_misp,[Default]), UsedName(ebreak_to_debug_mode_r_d1,[Default]), UsedName(take_int_timer1_int,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(i0_exception_valid_r,[Default]), UsedName(lsu_i0_exc_r,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(dec_tlu_sideeffect_posted_disable,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(lsu_error_pkt_addr_r,[Default]), UsedName(mstatus_mie_ns,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(exc_or_int_valid_r_d1,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(take_int_timer0_int,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(trigger_hit_r_d1,[Default]), UsedName(inst_acc_r,[Default]), UsedName(nmi_lsu_load_type,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(dec_tlu_ic_diag_pkt,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(timer_int_sync,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dbg_tlu_halted,[Default]), UsedName(ic_perr_r_d1,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ifu_pmu_ic_hit,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma_dccm_stall_any,[Default]), UsedName(ebreak_to_debug_mode_r,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(lsu_pmu_bus_busy,[Default]), UsedName(dma_pmu_dccm_read,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(mstatus,[Default]), UsedName(ifu_pmu_fetch_stall,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(dma_iccm_stall_any,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(i0_valid_wb,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(dec_tlu_dec_clk_override,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(mdseac_locked_ns,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(debug_halt_req_f,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(dma_pmu_dccm_write,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(lsu_pmu_bus_trxn,[Default]), UsedName(enter_debug_halt_req,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(lsu_i0_exc_r_d1,[Default]), UsedName(rvclkhdr,[Default]), UsedName(lsu_idle_any_f,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_dma_qos_prty,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dpc,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(force_halt,[Default]), UsedName(take_timer_int,[Default]), UsedName(lsu_single_ecc_error_r_d1,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mtvec,[Default]), UsedName(dcsr_single_step_running_f,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(i0_exception_valid_r_d1,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(dec_tlu_external_ldfwd_disable,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(i0_trigger_hit_r,[Default]), UsedName(exc_or_int_valid_r,[Default]), UsedName(take_ext_int,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(take_nmi,[Default]), UsedName(npc_r,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(tlu_flush_lower_r,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(ifu_ic_debug_rd_data,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(ifu_pmu_bus_trxn,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(csr_wr_clk,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(ecall_r,[Default]), UsedName(==,[Default]), UsedName(ifu_ic_debug_rd_data_valid,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(nmi_lsu_store_type,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(internal_dbg_halt_mode,[Default]), UsedName(csr_pkt,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_tlu_wb_coalescing_disable,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mret_r,[Default]), UsedName(widthOption,[Default]), UsedName(mexintpend,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(allow_dbg_halt_csr_write,[Default]), UsedName(dec_tlu_bpred_disable,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(reset_delayed,[Default]), UsedName(tlu_i0_commit_cmt,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(pic_pl,[Default]), UsedName(lsu_pmu_bus_misaligned,[Default]), UsedName(fw_halt_req,[Default]), UsedName(dma_pmu_any_write,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(lsu_exc_valid_r,[Default]), UsedName(mepc_trigger_hit_sel_pc_r,[Default]), UsedName(e4e5_int_clk,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(interrupt_valid_r_d1,[Default]), UsedName(dma_pmu_any_read,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(request_debug_mode_done,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(mtdata1_t,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(internal_dbg_halt_mode_f2,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(dec_tlu_meipt,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(take_ext_int_start,[Default]), UsedName(lsu_pmu_bus_error,[Default]), UsedName(nmi_int_detected_f,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(lsu_imprecise_error_store_any,[Default]), UsedName(ifu_pmu_bus_busy,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(ifu_pmu_ic_miss,[Default]), UsedName(ifu_miss_state_idle_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_imprecise_error_load_any,[Default]), UsedName(mepc,[Default]), UsedName(debug_halt_req,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(dec_tlu_meihap,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(exc_cause_wb,[Default]), UsedName($asInstanceOf,[Default]), UsedName(mip,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(dec_tlu_flush_noredir_r_d1,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(lsu_imprecise_error_addr_any,[Default]), UsedName(interrupt_valid_r,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(exc_cause_r,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_CSR_IO has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_CSR_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dmi.rvjtag_tap...
-[debug] Initial set of included nodes: dmi.rvjtag_tap
-[debug] Invalidated by transitive inheritance dependency: Set(dmi.rvjtag_tap)
-[debug] Change NamesChange(dmi.rvjtag_tap,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(rvjtag_tap,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dmi;rvjtag_tap;init;,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dmi.rvjtag_tap has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(rvjtag_tap,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dmi;rvjtag_tap;init;,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dmi.rvjtag_tap)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.exu...
-[debug] Initial set of included nodes: exu.exu
-[debug] Invalidated by transitive inheritance dependency: Set(exu.exu)
-[debug] The following member ref dependencies of exu.exu are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(exu.exu,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(r_ctl_en,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(i0_flush_path_d,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(i0_flush_path_x,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(i0_rs2_bypass_data_d,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(PREDPIPESIZE,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(i0_flush_upper_x,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(predpipe_x,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(flush_lower_ff,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(r_data_en,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(i0_valid_d,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(exu_flush_path_final,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(i_mul,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(i0_pred_correct_upper_r,[Default]), UsedName(i0_rs2_d,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(i0_rs1_bypass_en_d,[Default]), UsedName(exu,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(exu_bp,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(exu;exu;init;,[Default]), UsedName(final_predict_mp,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(x_ctl_en,[Default]), UsedName(i0_rs2_bypass_en_d,[Default]), UsedName(i0_rs1_bypass_data_d,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(i0_pred_correct_upper_x,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(csr_rs1_in_d,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(pred_temp1,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(i0_flush_path_upper_r,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(ghr_d,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(i0_pp_r,[Default]), UsedName(i0_rs1_d,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(exu_div_result,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(muldiv_rs2_d,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(i0_predict_p_d,[Default]), UsedName(data_gate_en,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(pred_temp2,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(muldiv_rs1_d,[Default]), UsedName(mul_result_x,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(pred_correct_npc_r,[Default]), UsedName(after_flush_eghr,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(i0_predict_newp_d,[Default]), UsedName(predpipe_d,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(ghr_x_ns,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(i0_pred_correct_upper_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dec_exu,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(lsu_exu,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(alu_result_x,[Default]), UsedName(x_data_en,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(i0_valid_x,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(i0_flush_upper_d,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(i0_taken_d,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(mul_valid_x,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(i0_predict_p_x,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(i0_taken_x,[Default]), UsedName(predpipe_r,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(ghr_x,[Default]), UsedName(i_div,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(i_alu,[Default]), UsedName(ghr_d_ns,[Default]), UsedName(dbg_cmd_wrdata,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(final_predpipe_mp,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]))) invalidates 2 classes due to The exu.exu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(exu.exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.Config...
-[debug] Initial set of included nodes: lib.Config
-[debug] Including lib.axi4_to_ahb_IO by lib.Config
-[debug] Including lib.axi4_to_ahb by lib.Config
-[debug] Invalidated by transitive inheritance dependency: Set(lib.Config, lib.axi4_to_ahb_IO, lib.axi4_to_ahb)
-[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
-[debug] Change NamesChange(lib.Config,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(TAG,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(Config,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 3 classes due to The lib.Config has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(TAG,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(Config,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.Config, lib.axi4_to_ahb_IO, lib.axi4_to_ahb)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.rets_pkt_t...
-[debug] Initial set of included nodes: include.rets_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.rets_pkt_t)
-[debug] Change NamesChange(include.rets_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(rets_pkt_t,[Default]), UsedName(ignoreSeq,[Default]), UsedName(pc0_ret,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(pc0_call,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(include;rets_pkt_t;init;,[Default]), UsedName(setRef,[Default]), UsedName(pc0_pc4,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.rets_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.rets_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from mem.quasar.mem...
-[debug] Initial set of included nodes: mem.quasar.mem
-[debug] Invalidated by transitive inheritance dependency: Set(mem.quasar.mem)
-[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(IO,[Default]), UsedName(io,[Default]), UsedName(mem,[Default]), UsedName(mem;quasar;mem;init;,[Default]))
-[debug] Change NamesChange(mem.quasar.mem,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mem,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(mem;quasar;mem;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The mem.quasar.mem has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mem,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(mem;quasar;mem;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(mem.quasar.mem)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar_wrapper)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.tlu_gen...
-[debug] Initial set of included nodes: dec.tlu_gen
-[debug] Invalidated by transitive inheritance dependency: Set(dec.tlu_gen)
-[debug] Change NamesChange(dec.tlu_gen,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(tlu_gen,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.tlu_gen has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(tlu_gen,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.tlu_gen)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_dec...
-[debug] Initial set of included nodes: include.lsu_dec
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_dec)
-[debug] The following member ref dependencies of include.lsu_dec are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	lsu.lsu
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_dec,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(dctl_busbuff,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(lsu_dec,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(tlu_busbuff,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(include;lsu_dec;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.lsu_dec has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_dec)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, quasar, dec.dec_IO, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.rvecc_encode...
-[debug] Initial set of included nodes: lib.el2_lib.rvecc_encode
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.rvecc_encode)
-[debug] Change NamesChange(lib.el2_lib.rvecc_encode,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(lib;el2_lib;rvecc_encode;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.rvecc_encode has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(lib;el2_lib;rvecc_encode;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.rvecc_encode)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dmi.dmi_wrapper_module...
-[debug] Initial set of included nodes: dmi.dmi_wrapper_module
-[debug] Invalidated by transitive inheritance dependency: Set(dmi.dmi_wrapper_module)
-[debug] Change NamesChange(dmi.dmi_wrapper_module,ModifiedNames(changes = UsedName(dmi;dmi_wrapper_module;init;,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(tdoEnable,[Default]), UsedName(getIds,[Default]), UsedName(jtag_id,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(reg_wr_en,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(trst_n,[Default]), UsedName(tdo,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(core_clk,[Default]), UsedName(finalize,[Default]), UsedName(reg_wr_data,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(tck,[Default]), UsedName(_parent,[Default]), UsedName(dmi_wrapper_module,[Default]), UsedName(reg_en,[Default]), UsedName(dwrap,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(rd_data,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(tms,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(tdi,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(reg_wr_addr,[Default]), UsedName(isClosed,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(core_rst_n,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dmi.dmi_wrapper_module has the following regular definitions changed:
-[debug] 	UsedName(dmi;dmi_wrapper_module;init;,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(tdoEnable,[Default]), UsedName(getIds,[Default]), UsedName(jtag_id,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(reg_wr_en,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(trst_n,[Default]), UsedName(tdo,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(core_clk,[Default]), UsedName(finalize,[Default]), UsedName(reg_wr_data,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(tck,[Default]), UsedName(_parent,[Default]), UsedName(dmi_wrapper_module,[Default]), UsedName(reg_en,[Default]), UsedName(dwrap,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(rd_data,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(tms,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(tdi,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(reg_wr_addr,[Default]), UsedName(isClosed,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(core_rst_n,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dmi.dmi_wrapper_module)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.ifu...
-[debug] Initial set of included nodes: ifu.ifu
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu)
-[debug] The following member ref dependencies of ifu.ifu are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(ifu.ifu,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(iccm_dma_ecc_error,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(iccm_dma_rtag,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(ifu_dec,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(mem_ctl,[Default]), UsedName(rvecc_encode,[Default]), UsedName(iccm,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(iccm_ready,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(ifu;ifu;init;,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(iccm_dma_rdata,[Default]), UsedName(rvbradder,[Default]), UsedName(exu_flush_path_final,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(exu_ifu,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ifu,[Default]), UsedName(iccm_dma_rvalid,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(ifu_dma,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(bp_ctl,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(ic,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(aln_ctl,[Default]), UsedName(ifc_ctl,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ifu_bus_clk_en,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(active_clk,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]))) invalidates 2 classes due to The ifu.ifu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.ifu)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.rvecc_encode...
-[debug] Initial set of included nodes: lib.lib.rvecc_encode
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.rvecc_encode)
-[debug] Change NamesChange(lib.lib.rvecc_encode,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(lib;lib;rvecc_encode;init;,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.lib.rvecc_encode has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(lib;lib;rvecc_encode;init;,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.rvecc_encode)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from quasar...
-[debug] Initial set of included nodes: quasar
-[debug] Invalidated by transitive inheritance dependency: Set(quasar)
-[debug] The following member ref dependencies of quasar are invalidated:
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(quasar,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(exu,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(dma_ctrl,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dec,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ifu,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(pic_ctrl_inst,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(core_dbg_cmd_fail,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(core_dbg_rddata,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dbg,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(core_dbg_cmd_done,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(quasar;init;,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(quasar,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(active_state,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(lsu,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(active_clk,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The quasar has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(quasar)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar_wrapper)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_IO...
-[debug] Initial set of included nodes: dec.dec_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_IO)
-[debug] The following member ref dependencies of dec.dec_IO are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(dec.dec_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(dec_pic,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(rv_trace_pkt,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(dec_dma,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(ifu_dec,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(dec_dbg_rddata,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(o_cpu_halt_ack,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_tlu,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(dec_dbg_cmd_done,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(dec_IO,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_pause_state_cg,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(dec;dec_IO;init;,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(dec_tlu_resume_ack,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(lsu_dec,[Default]), UsedName(dbg_resume_req,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(dec_dbg,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(exu_div_result,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(dec_dbg_cmd_fail,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(exu_i0_br_way_r,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(lsu_fastint_stall_any,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(dbg_halt_req,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(lsu_load_stall_any,[Default]), UsedName(compileOptions,[Implicit]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_exu,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_tlu_mpc_halted_only,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(lsu_pmu_misaligned_m,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(active_clk,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(dec_tlu_debug_mode,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(nmi_vec,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The dec.dec_IO has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_IO)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dma_ctrl...
-[debug] Initial set of included nodes: dma_ctrl
-[debug] Invalidated by transitive inheritance dependency: Set(dma_ctrl)
-[debug] The following member ref dependencies of dma_ctrl are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(dma_ctrl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(wrbuf_en,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dma_bus_cgc,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dma_dbg_cmd_done_q,[Default]), UsedName(dma_axi,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(wrbuf_rst,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(bus_cmd_mid,[Default]), UsedName(MEM_CAL,[Default]), UsedName(dma_bus_clk_en,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(wrbuf_data_vld,[Default]), UsedName(rdbuf_addr,[Default]), UsedName(bus_cmd_posted_write,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(wrbuf_addr,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dma_free_clk,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(iccm_dma_ecc_error,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(dec_dma,[Default]), UsedName(dbg_dma,[Default]), UsedName(fifo_byteen_in,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(iccm_dma_rtag,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(bus_cmd_valid,[Default]), UsedName(bus_cmd_byteen,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(fifo_rpend,[Default]), UsedName(bus_cmd_sz,[Default]), UsedName(fifo_full,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(dma_mem_sz_int,[Default]), UsedName(bus_posted_write_done,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(iccm_ready,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dma_buffer_c1cgc,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(dma_mem_addr_in_pic_region_nc,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rdbuf_rst,[Default]), UsedName(rvlsadder,[Default]), UsedName(RspPtrEn,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(WrPtr,[Default]), UsedName(dma_address_error,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(dma_mem_addr_int,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(NxtRdPtr,[Default]), UsedName(iccm_dma_rdata,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(dma_fifo_ready,[Default]), UsedName(WrPtrEn,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(fifo_error_en,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dbg_cmd_size,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(dma_dbg_cmd_error,[Default]), UsedName(synchronized,[Default]), UsedName(dma_ctrl;init;,[Default]), UsedName(getPorts,[Default]), UsedName(rdbuf_en,[Default]), UsedName(wrbuf_cmd_sent,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(axi_mstr_priority,[Default]), UsedName(fifo_error,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(fifo_done_bus,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(fifo_valid,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(dma_ctrl,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(fifo_empty,[Default]), UsedName(fifo_sz_in,[Default]), UsedName(NxtWrPtr,[Default]), UsedName(fifo_prty,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(axi_mstr_prty_in,[Default]), UsedName(fifo_posted_write_in,[Default]), UsedName(forceName,[Default]), UsedName(fifo_reset,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(RdPtr,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(dma_mem_addr_in_dccm,[Default]), UsedName(fifo_full_spec,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(fifo_data,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(axi_rsp_sent,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dma_free_cgc,[Default]), UsedName(wrbuf_byteen,[Default]), UsedName(dma_mem_addr_in_iccm_region_nc,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(dbg_dma_bubble_bus,[Default]), UsedName(iccm_dma_rvalid,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(dma_dbg_cmd_done,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(dma_nack_count_csr,[Default]), UsedName(wrbuf_vld,[Default]), UsedName(hashCode,[Default]), UsedName(ifu_dma,[Default]), UsedName(instanceName,[Default]), UsedName(fifo_data_en,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(axi_rsp_write,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(wrbuf_sz,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(wrbuf_data,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(num_fifo_vld_tmp,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dma_mem_addr_in_pic,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(fifo_write_in,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(NxtRspPtr,[Default]), UsedName(bus_cmd_addr,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(dma_mem_byteen,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(fifo_done_en,[Default]), UsedName(bus_cmd_sent,[Default]), UsedName(gated_latch,[Default]), UsedName(axi_rsp_tag,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(fifo_pend_en,[Default]), UsedName(fifo_posted_write,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dma_buffer_c1_clk,[Default]), UsedName(fifo_sz,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(wrbuf_tag,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(axi_mstr_prty_en,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dma_bus_clk,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(axi_rsp_error,[Default]), UsedName(num_fifo_vld,[Default]), UsedName(fifo_dbg,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(bus_rsp_sent,[Default]), UsedName(wrbuf_data_en,[Default]), UsedName(DEPTH_PTR,[Default]), UsedName(fifo_dbg_in,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(dma_mem_addr_in_dccm_region_nc,[Default]), UsedName(axi_rsp_rdata,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(fifo_error_in,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(bus_cmd_prty,[Default]), UsedName(axi_rsp_valid,[Default]), UsedName(fifo_addr_in,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(fifo_full_spec_bus,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(RspPtr,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(fifo_error_bus,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(dma_mem_addr_in_iccm,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(rdbuf_tag,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(rdbuf_cmd_sent,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(wrbuf_data_rst,[Default]), UsedName(bus_cmd_tag,[Default]), UsedName(fifo_error_bus_en,[Default]), UsedName(dma_dbg_cmd_fail,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(dma_free_clken,[Default]), UsedName(dma_dbg_rddata,[Default]), UsedName(dma_mem_req,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(fifo_write,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(bus_cmd_wdata,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(num_fifo_vld_tmp2,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(RdPtrEn,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(fifo_addr,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(fifo_cmd_en,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(dma_nack_count,[Default]), UsedName(isClosed,[Default]), UsedName(rdbuf_sz,[Default]), UsedName(dma_nack_count_d,[Default]), UsedName(fifo_done_bus_en,[Default]), UsedName(bus_cmd_write,[Default]), UsedName(fifo_tag,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(fifo_done,[Default]), UsedName(lsu_dma,[Default]), UsedName(fifo_byteen,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(dbg_dma_io,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(dma_alignment_error,[Default]), UsedName(clock,[Default]), UsedName(dma_buffer_c1_clken,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(fifo_mid,[Default]), UsedName(fifo_data_in,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(rdbuf_vld,[Default]), UsedName(addId,[Default]), UsedName(bus_rsp_valid,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(axi_mstr_sel,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dma_ctrl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dma_ctrl)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_dccm_ctl...
-[debug] Initial set of included nodes: lsu.lsu_dccm_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_dccm_ctl)
-[debug] The following member ref dependencies of lsu.lsu_dccm_ctl are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_dccm_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(ld_single_ecc_error_hi_r_ff,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(single_ecc_error_hi_r,[Default]), UsedName(single_ecc_error_lo_r,[Default]), UsedName(sec_data_ecc_lo_r_ff,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(store_data_pre_m,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(lsu_free_c2_clk,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(stbuf_reqvld_any,[Default]), UsedName(desiredName,[Default]), UsedName(stbuf_data_any,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(dccm_rdata_lo_r,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(lsu_pic,[Default]), UsedName(end_addr_d,[Default]), UsedName(rvecc_encode,[Default]), UsedName(store_data_pre_hi_r,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_pic_d,[Default]), UsedName(lsu_rdata_corr_m,[Default]), UsedName(addr_in_dccm_m,[Default]), UsedName(addr_in_dccm_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_pkt_d,[Default]), UsedName(getIds,[Default]), UsedName(kill_ecc_corr_hi_r,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(dma_dccm_wdata_lo,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(store_data_hi_m,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dma_mem_tag_m,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(picm_mask_data_m,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(lsu_c1_r_clk,[Default]), UsedName(end_addr_r,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dccm_rdata_r,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(dccm_data_ecc_lo_r,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(lsu_double_ecc_error_r,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(stbuf_fwddata_r,[Default]), UsedName(circuitName,[Default]), UsedName(ld_single_ecc_error_lo_r_ns,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(lsu_addr_d,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dma_dccm_wdata_hi,[Default]), UsedName(dccm_rdata_lo_m,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(lsu_ld_data_corr_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(picm_rd_data_m,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(dccm_rdata_hi_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(ld_sec_addr_lo_r_ff,[Default]), UsedName(ld_sec_addr_hi_r_ff,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(lsu_dccm_wren_d,[Default]), UsedName(sec_data_hi_r_ff,[Default]), UsedName(Tag_Word,[Default]), UsedName(lsu_rdata_r,[Default]), UsedName(stbuf_addr_any,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(store_byteen_m,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(lsu_raw_fwd_hi_r,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(store_data_hi_r,[Default]), UsedName(dccm_rdata_corr_r,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(ld_single_ecc_error_lo_r_ff,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(lsu;lsu_dccm_ctl;init;,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(lsu_rdata_m,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(dma_dccm_wdata_ecc_lo,[Default]), UsedName(lsu_double_ecc_error_r_ff,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(dccm_wr_bypass_d_m_lo_Q,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(dccm_rdata_m,[Default]), UsedName(lsu_raw_fwd_lo_r,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(store_datafn_lo_r,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(lsu_store_c1_r_clk,[Default]), UsedName(dccm_wren_Q,[Default]), UsedName(dccm_wr_bypass_d_r_lo,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(stbuf_fwddata_lo_m,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_commit_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dccm_wr_data_Q,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(sec_data_hi_m,[Default]), UsedName(lsu_c2_m_clk,[Default]), UsedName(store_data_lo_r,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(sec_data_lo_r_ff,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(ld_single_ecc_error_r_ff,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(lsu_dccm_rden_r,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ld_single_ecc_error_hi_r_ns,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(kill_ecc_corr_lo_r,[Default]), UsedName(dma_dccm_wdata_ecc_hi,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(store_datafn_hi_r,[Default]), UsedName(dccm_wr_bypass_d_m_hi,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(lsu_dccm_rden_m,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(addr_in_pic_m,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(dccm_data_ecc_hi_m,[Default]), UsedName(store_data_r,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(dccm_wr_bypass_d_m_lo,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(lsu_dccm_ctl,[Default]), UsedName(stbuf_fwdbyteen_lo_m,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(stbuf_fwdbyteen_hi_m,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(sec_data_lo_m,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(addr_in_dccm_r,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(store_data_pre_lo_r,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(dma_dccm_ctl,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(sec_data_hi_r,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(lsu_rdata_corr_r,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(lsu_double_ecc_error_m,[Default]), UsedName(dccm_rdata_corr_m,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(lsu_stbuf_commit_any,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(store_byteen_ext_m,[Default]), UsedName(lsu_ld_data_corr_m,[Default]), UsedName(dccm,[Default]), UsedName(stbuf_ecc_any,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(picm_rd_data_r,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(ld_single_ecc_error_r,[Default]), UsedName(dma_pic_wen,[Default]), UsedName(lsu_ld_data_r,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(lsu_dccm_rden_d,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(namingContext$macro$2,[Default]), UsedName(store_data_pre_r,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(dccm_rdata_hi_r,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(stbuf_fwdbyteen_r,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(store_byteen_r,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(dccm_data_ecc_hi_r,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(addr_in_pic_r,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(dccm_data_ecc_lo_m,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(picm_rd_data_r_32,[Default]), UsedName(store_data_m,[Default]), UsedName(dccm_wr_bypass_d_r_hi,[Default]), UsedName(sec_data_ecc_hi_r_ff,[Default]), UsedName(stbuf_fwddata_hi_m,[Default]), UsedName(sec_data_lo_r,[Default]), UsedName(lsu_ld_data_m,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(ld_single_ecc_error_hi_r,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(store_data_lo_m,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(store_byteen_ext_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(ld_single_ecc_error_lo_r,[Default]), UsedName(dccm_wr_bypass_d_m_hi_Q,[Default]), UsedName(dma_dccm_wen,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(end_addr_m,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_dccm_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_dccm_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dbg.dbg_dma...
-[debug] Initial set of included nodes: dbg.dbg_dma
-[debug] Invalidated by transitive inheritance dependency: Set(dbg.dbg_dma)
-[debug] The following member ref dependencies of dbg.dbg_dma are invalidated:
-[debug] 	dma_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(dbg.dbg_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dbg_dma,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(dbg_dma_bubble,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(dma_dbg_ready,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dbg;dbg_dma;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 3 classes due to The dbg.dbg_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dbg.dbg_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(dma_ctrl, quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.write_data...
-[debug] Initial set of included nodes: include.write_data
-[debug] Invalidated by transitive inheritance dependency: Set(include.write_data)
-[debug] The following member ref dependencies of include.write_data are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] Change NamesChange(include.write_data,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(data,[Default]), UsedName(last,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(strb,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(write_data,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(include;write_data;init;,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.write_data has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.write_data)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_trigger_pkt_t...
-[debug] Initial set of included nodes: include.el2_trigger_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_trigger_pkt_t)
-[debug] Change NamesChange(include.el2_trigger_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(select,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(tdata2,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(m,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(execute,[Default]), UsedName(_parent,[Default]), UsedName(el2_trigger_pkt_t,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(match_,[Default]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(include;el2_trigger_pkt_t;init;,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_trigger_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_trigger_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_gpr_ctl_IO...
-[debug] Initial set of included nodes: dec.el2_dec_gpr_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_gpr_ctl_IO)
-[debug] Change NamesChange(dec.el2_dec_gpr_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(wen0,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(raddr0,[Default]), UsedName(wd1,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(waddr1,[Default]), UsedName(bind,[Default]), UsedName(wd0,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(rd0,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(waddr0,[Default]), UsedName(rd1,[Default]), UsedName(ref,[Default]), UsedName(wen2,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(raddr1,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(waddr2,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(el2_dec_gpr_ctl_IO,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(dec;el2_dec_gpr_ctl_IO;init;,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(wd2,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(wen1,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_gpr_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_gpr_ctl_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dmi.dmi_jtag_to_core_sync...
-[debug] Initial set of included nodes: dmi.dmi_jtag_to_core_sync
-[debug] Invalidated by transitive inheritance dependency: Set(dmi.dmi_jtag_to_core_sync)
-[debug] Change NamesChange(dmi.dmi_jtag_to_core_sync,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(dmi_jtag_to_core_sync,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(dmi;dmi_jtag_to_core_sync;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dmi.dmi_jtag_to_core_sync has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(dmi_jtag_to_core_sync,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(dmi;dmi_jtag_to_core_sync;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dmi.dmi_jtag_to_core_sync)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.write_addr...
-[debug] Initial set of included nodes: include.write_addr
-[debug] Invalidated by transitive inheritance dependency: Set(include.write_addr)
-[debug] The following member ref dependencies of include.write_addr are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] Change NamesChange(include.write_addr,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(size,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(qos,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(prot,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(len,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(burst,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(addr,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(include;write_addr;init;,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(lock,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(write_addr,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(<init>$default$1,[Default]), UsedName(cache,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(region,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(id,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.write_addr has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.write_addr)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dbg.dbg...
-[debug] Initial set of included nodes: dbg.dbg
-[debug] Invalidated by transitive inheritance dependency: Set(dbg.dbg)
-[debug] The following member ref dependencies of dbg.dbg are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(dbg.dbg,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(abstractcs_reg,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(sbdata1_din,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(dm_temp_0,[Default]), UsedName(dmcontrol_wren_Q,[Default]), UsedName(sbcs_unaligned,[Default]), UsedName(sbcs_sbbusyerror_din,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(abstractcs_busy_din,[Default]), UsedName(dbg_dma,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(dmi_reg_en,[Default]), UsedName(desiredName,[Default]), UsedName(abs_temp_10_8,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(sb_free_clken,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(abstractcs_error_sel1,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(sbdata0_reg_wren1,[Default]), UsedName(sbaddress0_reg_wren0,[Default]), UsedName(abstractcs_error_selor,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(dmstatus_reg,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(sbdata1_reg_wren1,[Default]), UsedName(sbdata1_reg,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dmstatus_running,[Default]), UsedName(sb_nxtstate,[Default]), UsedName(data1_reg_wren,[Default]), UsedName(sbaddress0_reg_din,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(sb_bus_rsp_error,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(temp_sbcs_22,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(sbaddress0_reg_wren1,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(abstractcs_busy_wren,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(sb_bus_cmd_write_data,[Default]), UsedName(sb_state,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dbg_cmd_size,[Default]), UsedName(sbaddress0_reg,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(dbg_state_en,[Default]), UsedName(getChiselPorts,[Default]), UsedName(sbaddress0_reg_wren,[Default]), UsedName(synchronized,[Default]), UsedName(sbcs_sberror_din,[Default]), UsedName(sbcs_sberror_wren,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(sbreadondata_access,[Default]), UsedName(dbg_core_rst_l,[Default]), UsedName(sbcs_sbbusyerror_wren,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(dbg_rst_l,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(dmcontrol_reg,[Default]), UsedName(Tag_Word,[Default]), UsedName(dmstatus_resumeack_wren,[Default]), UsedName(dbg_state,[Default]), UsedName(sb_bus_rdata,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(temp_sbcs_20,[Default]), UsedName(sb_bus_cmd_read,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(dmstatus_havereset_rst,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(sb_state_en,[Default]), UsedName(sb_axi,[Default]), UsedName(data1_reg,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(command_reg,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(sb_bus_rsp_write,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(haltsum0_reg,[Default]), UsedName(addPostnameHook,[Default]), UsedName(temp_sbcs_19_15,[Default]), UsedName(dmi_reg_wr_en,[Default]), UsedName(forceName,[Default]), UsedName(sbdata1_reg_wren,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(abstractcs_error_sel3,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(dmstatus_unavail,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(data0_reg_wren1,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(sbaddress0_incr,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(dbg_free_clk,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(command_din,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(dec_tlu_resume_ack,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(data1_din,[Default]), UsedName(sbcs_illegal_size,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(dbg_resume_req,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(abs_temp_12,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(sb_free_clk,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dbg_bus_clk_en,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(sbdata0_reg_wren,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(core_dbg_cmd_fail,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(core_dbg_rddata,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dmcontrol_wren,[Default]), UsedName(rvclkhdr,[Default]), UsedName(sbcs_sbbusy_din,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(sbcs_reg,[Default]), UsedName(temp_sbcs_21,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dbg,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(data0_reg_wren0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(temp_sbcs_14_12,[Default]), UsedName(clk_override,[Default]), UsedName(dmstatus_resumeack,[Default]), UsedName(sb_bus_cmd_write_addr,[Default]), UsedName(core_dbg_cmd_done,[Default]), UsedName(dbg_dec,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(dmstatus_havereset_wren,[Default]), UsedName(_onModuleClose,[Default]), UsedName(temp,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dmstatus_havereset,[Default]), UsedName(temp_rst,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(dbg_halt_req,[Default]), UsedName(abstractcs_error_sel0,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(dbg;dbg;init;,[Default]), UsedName(sbdata0_din,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(abstractcs_error_sel5,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(sbcs_sbbusy_wren,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(sb_bus_rsp_read,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(abstractcs_error_sel4,[Default]), UsedName(dmi_reg_rdata,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(abstractcs_error_din,[Default]), UsedName(command_wren,[Default]), UsedName(sbreadonaddr_access,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(data0_reg_wren,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(dmstatus_halted,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(data0_reg,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(sbcs_wren,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(sbdata1_reg_wren0,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(sbdata0_reg_wren0,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(sbdata0wr_access,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(dmi_reg_addr,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(dec_tlu_mpc_halted_only,[Default]), UsedName(dbg_dm_rst_l,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(data0_din,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(abstractcs_error_sel2,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(dm_temp,[Default]), UsedName(dbg_free_clken,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(sbdata0_reg,[Default]), UsedName(dmstatus_resumeack_din,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(dbg_dma_io,[Default]), UsedName(wait,[Default]), UsedName(dec_tlu_debug_mode,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(dmi_reg_rdata_din,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(dbg_nxtstate,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(dmi_reg_wdata,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dbg.dbg has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dbg.dbg)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.exu_bp...
-[debug] Initial set of included nodes: include.exu_bp
-[debug] Invalidated by transitive inheritance dependency: Set(include.exu_bp)
-[debug] The following member ref dependencies of include.exu_bp are invalidated:
-[debug] 	exu.exu
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_bp_ctl
-[debug] 	quasar
-[debug] Change NamesChange(include.exu_bp,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(exu_mp_pkt,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(exu_mp_btag,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(exu_bp,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(exu_mp_fghr,[Default]), UsedName(include;exu_bp;init;,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(exu_i0_br_index_r,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(exu_i0_br_fghr_r,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(exu_i0_br_way_r,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(exu_mp_eghr,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(exu_mp_index,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.exu_bp has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.exu_bp)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_bp_ctl, ifu.ifu, quasar, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.gpr_gen...
-[debug] Initial set of included nodes: dec.gpr_gen
-[debug] Invalidated by transitive inheritance dependency: Set(dec.gpr_gen)
-[debug] Change NamesChange(dec.gpr_gen,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(gpr_gen,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.gpr_gen has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(gpr_gen,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.gpr_gen)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.aln_dec...
-[debug] Initial set of included nodes: include.aln_dec
-[debug] Invalidated by transitive inheritance dependency: Set(include.aln_dec)
-[debug] The following member ref dependencies of include.aln_dec are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	ifu.ifu_aln_ctl
-[debug] Change NamesChange(include.aln_dec,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(include;aln_dec;init;,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ifu_i0_cinst,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(aln_dec,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.aln_dec has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.aln_dec)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_aln_ctl, dec.dec, dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.alu_pkt_t...
-[debug] Initial set of included nodes: include.alu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.alu_pkt_t)
-[debug] The following member ref dependencies of include.alu_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] 	exu.exu_alu_ctl
-[debug] Change NamesChange(include.alu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(add,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(predict_nt,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(predict_t,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(alu_pkt_t,[Default]), UsedName(toString,[Default]), UsedName(slt,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(beq,[Default]), UsedName(include;alu_pkt_t;init;,[Default]), UsedName(lor,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(sll,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(srl,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(sra,[Default]), UsedName(_parent,[Default]), UsedName(jal,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(land,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(bge,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(blt,[Default]), UsedName(_makeLit,[Default]), UsedName(bne,[Default]), UsedName(notify,[Default]), UsedName(csr_write,[Default]), UsedName(csr_imm,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lxor,[Default]), UsedName(toTarget,[Default]), UsedName(sub,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.alu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.alu_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_alu_ctl, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvmaskandmatch...
-[debug] Initial set of included nodes: lib.rvmaskandmatch
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvmaskandmatch)
-[debug] Change NamesChange(lib.rvmaskandmatch,ModifiedNames(changes = UsedName(data,[Default]), UsedName(_closed,[Default]), UsedName(masken_or_fullmask,[Default]), UsedName(desiredName,[Default]), UsedName(match_out,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(matchvec,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(mask,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(masken,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(lib;rvmaskandmatch;init;,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvmaskandmatch has the following regular definitions changed:
-[debug] 	UsedName(data,[Default]), UsedName(_closed,[Default]), UsedName(masken_or_fullmask,[Default]), UsedName(desiredName,[Default]), UsedName(match_out,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(matchvec,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(mask,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(masken,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(lib;rvmaskandmatch;init;,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvmaskandmatch)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dbg_ib...
-[debug] Initial set of included nodes: include.dbg_ib
-[debug] Invalidated by transitive inheritance dependency: Set(include.dbg_ib)
-[debug] The following member ref dependencies of include.dbg_ib are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dec.dec
-[debug] 	dec.dec_ib_ctl
-[debug] 	dec.dec_ib_ctl_IO
-[debug] 	dma_ctrl
-[debug] Change NamesChange(include.dbg_ib,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(dbg_cmd_write,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dbg_ib,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(include;dbg_ib;init;,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(dbg_cmd_type,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dbg_cmd_valid,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dbg_cmd_addr,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dbg_ib has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dbg_ib)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_ib_ctl_IO, dbg.dbg, dec.dec_ib_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_alu...
-[debug] Initial set of included nodes: include.dec_alu
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_alu)
-[debug] The following member ref dependencies of include.dec_alu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] 	exu.exu_alu_ctl
-[debug] Change NamesChange(include.dec_alu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(dec_alu,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(dec_csr_ren_d,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(dec_i0_alu_decode_d,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(include;dec_alu;init;,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(exu_i0_pc_x,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(dec_i0_br_immed_d,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.dec_alu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_alu)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_alu_ctl, dec.dec, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_pic...
-[debug] Initial set of included nodes: include.lsu_pic
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_pic)
-[debug] The following member ref dependencies of include.lsu_pic are invalidated:
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_dccm_ctl
-[debug] 	pic_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_pic,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(lsu_pic,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(picm_wraddr,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(picm_rden,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(picm_mken,[Default]), UsedName(do_asUInt,[Default]), UsedName(picm_wren,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(picm_rdaddr,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(picm_wr_data,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(picm_rd_data,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(include;lsu_pic;init;,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.lsu_pic has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_pic)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, lsu.lsu_dccm_ctl, quasar, pic_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dbg.sb_state_t...
-[debug] Initial set of included nodes: dbg.sb_state_t
-[debug] Invalidated by transitive inheritance dependency: Set(dbg.sb_state_t)
-[debug] Change NamesChange(dbg.sb_state_t,ModifiedNames(changes = UsedName(rsp_rd,[Default]), UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(wait_rd,[Default]), UsedName(toString,[Default]), UsedName(cmd_rd,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(cmd_wr,[Default]), UsedName(cmd_wr_data,[Default]), UsedName(cmd_wr_addr,[Default]), UsedName(ne,[Default]), UsedName(rsp_wr,[Default]), UsedName(sbidle,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(wait_wr,[Default]), UsedName(getClass,[Default]), UsedName(done,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(sb_state_t,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dbg.sb_state_t has the following regular definitions changed:
-[debug] 	UsedName(rsp_rd,[Default]), UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(wait_rd,[Default]), UsedName(toString,[Default]), UsedName(cmd_rd,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(cmd_wr,[Default]), UsedName(cmd_wr_data,[Default]), UsedName(cmd_wr_addr,[Default]), UsedName(ne,[Default]), UsedName(rsp_wr,[Default]), UsedName(sbidle,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(wait_wr,[Default]), UsedName(getClass,[Default]), UsedName(done,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(sb_state_t,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dbg.sb_state_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_tlu_ctl_IO...
-[debug] Initial set of included nodes: dec.dec_tlu_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_tlu_ctl_IO)
-[debug] The following member ref dependencies of dec.dec_tlu_ctl_IO are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_tlu_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(dec_pic,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_tlu_i0_kill_writeb_wb,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(dec_tlu_ifu_clk_override,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(o_cpu_halt_ack,[Default]), UsedName(dec_tlu_pic_clk_override,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_icm_clk_override,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dec_tlu_presync_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(dec_tlu_misc_clk_override,[Default]), UsedName(dec_tlu_lsu_clk_override,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_tlu,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(tlu_ifc,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(dec_dbg_cmd_done,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(dec_tlu_ctl_IO,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(dec_tlu_dccm_clk_override,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(iccm_dma_sb_error,[Default]), UsedName(isSynthesizable,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(tlu_bp,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(dec_pause_state,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(dec_i0_decode_d,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(dec_div_active,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(dec_tlu_resume_ack,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(tlu_mem,[Default]), UsedName(dec_csr_legal_d,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(dec_tlu_debug_stall,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(dec_tlu_dec_clk_override,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(dbg_resume_req,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(tlu_dma,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(dec_tlu_dbg_halted,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(dec_dbg_cmd_fail,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(exu_i0_br_way_r,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(lsu_fastint_stall_any,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(tlu_exu,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dec_tlu_bus_clk_override,[Default]), UsedName(dec_tlu_flush_pause_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(dec;dec_tlu_ctl_IO;init;,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(dbg_halt_req,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_postsync_d,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(tlu_busbuff,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_tlu_mpc_halted_only,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(dec_tlu_debug_mode,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(nmi_vec,[Default]), UsedName(dec_tlu_flush_extint,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The dec.dec_tlu_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_tlu_ctl_IO)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_dma...
-[debug] Initial set of included nodes: include.dec_dma
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_dma)
-[debug] The following member ref dependencies of include.dec_dma are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dma_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dec_dma,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(include;dec_dma;init;,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(tlu_dma,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dctl_dma,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.dec_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(dma_ctrl, quasar, dec.dec_IO, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_exu...
-[debug] Initial set of included nodes: include.dec_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_exu)
-[debug] The following member ref dependencies of include.dec_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	exu.exu
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_alu,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(include;dec_exu;init;,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(decode_exu,[Default]), UsedName(dec_div,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(gpr_exu,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(tlu_exu,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_exu,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(ib_exu,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.dec_exu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar, dec.dec_IO, dec.dec, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.rvsyncss...
-[debug] Initial set of included nodes: lib.lib.rvsyncss
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.rvsyncss)
-[debug] The following modified names cause invalidation of dec.dec_tlu_ctl: Set(UsedName(apply,[Default]), UsedName(rvsyncss,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of pic_ctrl: Set(UsedName(apply,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]))
-[debug] Change NamesChange(lib.lib.rvsyncss,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 3 classes due to The lib.lib.rvsyncss has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvsyncss,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.rvsyncss)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_tlu_ctl, pic_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.csr_tlu...
-[debug] Initial set of included nodes: dec.csr_tlu
-[debug] Invalidated by transitive inheritance dependency: Set(dec.csr_tlu)
-[debug] Change NamesChange(dec.csr_tlu,ModifiedNames(changes = UsedName(ICACHE_ENABLE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(configurable_gw,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(rvrangecheck,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(io,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(int2boolean,[Implicit]), UsedName(ICCM_ICACHE,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(csr_tlu,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(uint2bool,[Implicit]))) invalidates 1 classes due to The dec.csr_tlu has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.csr_tlu)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dbg.el2_dbg...
-[debug] Initial set of included nodes: dbg.el2_dbg
-[debug] Invalidated by transitive inheritance dependency: Set(dbg.el2_dbg)
-[debug] Change NamesChange(dbg.el2_dbg,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(el2_dbg,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(dbg;el2_dbg;init;,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dbg.el2_dbg has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(el2_dbg,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(dbg;el2_dbg;init;,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dbg.el2_dbg)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_mul_pkt_t...
-[debug] Initial set of included nodes: include.el2_mul_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_mul_pkt_t)
-[debug] Change NamesChange(include.el2_mul_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(crc32c_h,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(rs1_sign,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(clmulh,[Default]), UsedName(rs2_sign,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(crc32_h,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(include;el2_mul_pkt_t;init;,[Default]), UsedName(ref,[Default]), UsedName(crc32c_b,[Default]), UsedName(do_asUInt,[Default]), UsedName(clmulr,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(bdep,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(bext,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(low,[Default]), UsedName(grev,[Default]), UsedName(crc32_w,[Default]), UsedName(unshfl,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(crc32_b,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(bfp,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(crc32c_w,[Default]), UsedName(clmul,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(shfl,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(el2_mul_pkt_t,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_mul_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_mul_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.trigger_pkt_t...
-[debug] Initial set of included nodes: include.trigger_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.trigger_pkt_t)
-[debug] The following member ref dependencies of include.trigger_pkt_t are invalidated:
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	dec.dec_trigger
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_trigger
-[debug] 	quasar
-[debug] Change NamesChange(include.trigger_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(match_pkt,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(select,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(trigger_pkt_t,[Default]), UsedName(bind,[Default]), UsedName(include;trigger_pkt_t;init;,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(tdata2,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(m,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(execute,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 11 classes due to The include.trigger_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.trigger_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, lsu.lsu_trigger, dec.dec_tlu_ctl_IO, lsu.lsu, dec.dec_tlu_ctl, quasar, dec.csr_tlu, dec.dec_IO, dec.CSR_IO, dec.dec_trigger)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from quasar_bundle...
-[debug] Initial set of included nodes: quasar_bundle
-[debug] Invalidated by transitive inheritance dependency: Set(quasar_bundle)
-[debug] The following member ref dependencies of quasar_bundle are invalidated:
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(quasar_bundle,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(dma_hwdata,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(rv_trace_pkt,[Default]), UsedName(htrans,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dma_axi,[Default]), UsedName(lsu_haddr,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(dma_bus_clk_en,[Default]), UsedName(dccm_clk_override,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(dma_hburst,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(dmi_reg_en,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(direction,[Default]), UsedName(lsu_hprot,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(o_cpu_halt_ack,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(iccm,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(hsize,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(hrdata,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(dma_hrdata,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(sb_haddr,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(hburst,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(hresp,[Default]), UsedName(circuitName,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(lsu_hwdata,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dma_haddr,[Default]), UsedName(sb_hwdata,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(sb_hprot,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dbg_rst_l,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(dma_hsel,[Default]), UsedName(lsu_hresp,[Default]), UsedName(lsu_hsize,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(sb_hsize,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(lsu_hrdata,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(sb_axi,[Default]), UsedName(lsu_axi,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(sb_hburst,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(lsu_hwrite,[Default]), UsedName(dma_hwrite,[Default]), UsedName(core_rst_l,[Default]), UsedName(dmi_reg_wr_en,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(hready,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(sb_hready,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(sb_hmastlock,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(lsu_hready,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hmastlock,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dbg_bus_clk_en,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(dma_hresp,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(hprot,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(isWidthKnown,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(sb_hwrite,[Default]), UsedName(quasar_bundle,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dma_htrans,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(ifu_axi,[Default]), UsedName(lsu_hburst,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(icm_clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(lsu_htrans,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(ic,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(quasar_bundle;init;,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(lsu_hmastlock,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(haddr,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(rst_vec,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(sb_hrdata,[Default]), UsedName(dmi_reg_rdata,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(extintsrc_req,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(sb_htrans,[Default]), UsedName(dccm,[Default]), UsedName(dma_hsize,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(dmi_reg_addr,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ifu_bus_clk_en,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(sb_hresp,[Default]), UsedName(hwrite,[Default]), UsedName(dma_hprot,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(dmi_hard_reset,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(nmi_vec,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(dmi_reg_wdata,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The quasar_bundle has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(quasar_bundle)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar_wrapper)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_intf...
-[debug] Initial set of included nodes: lsu.lsu_bus_intf
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_intf)
-[debug] The following member ref dependencies of lsu.lsu_bus_intf are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_bus_intf,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ldst_byteen_m,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ldst_byteen_ext_r,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ld_byte_hit_buf_lo,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(lsu_free_c2_clk,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(lsu_bus_buffer_empty_any,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ldst_byteen_ext_m,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(end_addr_d,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_bus_buf_c1_clk,[Default]), UsedName(ld_addr_rhit_lo_lo,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(ld_byte_rhit_lo,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(lsu_busm_clk,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_bus_clk_en_q,[Default]), UsedName(is_sideeffects_m,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(lsu_c1_r_clk,[Default]), UsedName(end_addr_r,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(ld_addr_rhit_hi_lo,[Default]), UsedName(ldst_dual_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ld_fwddata_m,[Default]), UsedName(toNamed,[Default]), UsedName(axi,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(ld_byte_rhit_hi,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(lsu_addr_d,[Default]), UsedName(flush_r,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(addr_match_word_lo_r_m,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ld_byte_rhit_lo_lo,[Default]), UsedName(dctl_busbuff,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(ld_byte_rhit_hi_hi,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(ld_fwddata_buf_hi,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(store_data_hi_r,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(lsu_busreq_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(ld_full_hit_hi_m,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(lsu_bus_buffer_full_any,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ld_fwddata_rpipe_lo,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(ldst_byteen_hi_r,[Default]), UsedName(bus_buffer,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(ld_byte_hit_buf_hi,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_commit_r,[Default]), UsedName(ldst_byteen_r,[Default]), UsedName(no_word_merge_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(ld_byte_rhit_lo_hi,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(store_data_lo_r,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(ldst_byteen_lo_m,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(ld_full_hit_m,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(lsu;lsu_bus_intf;init;,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(ld_addr_rhit_hi_hi,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(lsu_bus_buffer_pend_any,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(store_data_r,[Default]), UsedName(ld_full_hit_lo_m,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(bus_read_data_m,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(flush_m_up,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(addr_match_dw_lo_r_m,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(lsu_c1_m_clk,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(lsu_busreq_m,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ldst_dual_r,[Default]), UsedName(lsu_bus_obuf_c1_clk,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(no_dword_merge_r,[Default]), UsedName(notify,[Default]), UsedName(lsu_bus_ibuf_c1_clk,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(ld_fwddata_buf_lo,[Default]), UsedName(store_data_ext_r,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(is_sideeffects_r,[Default]), UsedName(ldst_byteen_lo_r,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ld_fwddata_rpipe_hi,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ld_byte_hit_hi,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(tlu_busbuff,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(ldst_dual_m,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(ld_byte_hit_lo,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ld_fwddata_hi,[Default]), UsedName(ld_addr_rhit_lo_hi,[Default]), UsedName(ld_byte_rhit_hi_lo,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(lsu_bus_idle_any,[Default]), UsedName(ld_fwddata_lo,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(ldst_byteen_hi_m,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(end_addr_m,[Default]), UsedName(lsu_bus_intf,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_bus_intf has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_bus_intf)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_timer_ctl...
-[debug] Initial set of included nodes: dec.dec_timer_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_timer_ctl)
-[debug] Change NamesChange(dec.dec_timer_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(MITB1,[Default]), UsedName(mitctl1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(mitcnt0_inc_ok,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(MITB0,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(mitctl0,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(mitcnt0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(mitctl0_ns,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(mit0_match_ns,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(MITCTL0,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(wr_mitb0_r,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(mitb0_b,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(dec_timer_ctl,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(dec;dec_timer_ctl;init;,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(MITCTL_ENABLE_HALTED,[Default]), UsedName(MITCTL1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(MITCNT0,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(MITCNT1,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(wr_mitcnt0_r,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(mitctl1_0_b,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(mitcnt1_ns,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(mitcnt1,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mitctl0_0_b_ns,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(mitctl0_0_b,[Default]), UsedName(mitcnt1_inc_ok,[Default]), UsedName(mitctl1_ns,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(wr_mitctl1_r,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(wr_mitcnt1_r,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(mitb1_b,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(mit1_match_ns,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(MITCTL_ENABLE_PAUSED,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(mitcnt0_ns,[Default]), UsedName(mitctl1_0_b_ns,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(wr_mitb1_r,[Default]), UsedName(parentModName,[Default]), UsedName(wr_mitctl0_r,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(mitcnt1_inc,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(mitb1,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(mitcnt0_inc,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(MITCTL_ENABLE,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(mitb0,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.dec_timer_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_timer_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from snapshot.pt...
-[debug] Initial set of included nodes: snapshot.pt
-[debug] Invalidated by transitive inheritance dependency: Set(snapshot.pt)
-[debug] Change NamesChange(snapshot.pt,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(pt,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(getClass,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The snapshot.pt has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(pt,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(getClass,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(snapshot.pt)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_tlu_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_tlu_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_tlu_ctl)
-[debug] Change NamesChange(dec.el2_dec_tlu_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(i_cpu_run_req_sync,[Default]), UsedName(take_nmi_r_d1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ext_int_ready,[Default]), UsedName(lsu_i0_exc_r_raw,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(lsu_exc_acc_r,[Default]), UsedName(MIP_MEIP,[Default]), UsedName(MIE_MTIE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(iccm_repair_state_d1,[Default]), UsedName(MEM_CAL,[Default]), UsedName(e4_valid,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(e5_valid,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(soft_int_sync,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(ic_perr_r,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(resume_ack_ns,[Default]), UsedName(request_debug_mode_r,[Default]), UsedName(MIP_MITIP1,[Default]), UsedName(illegal_r,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(reset_detected,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(iccm_repair_state_rfnpc,[Default]), UsedName(i0_trigger_hit_raw_r,[Default]), UsedName(mdseac_locked_f,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(dec;el2_dec_tlu_ctl;init;,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(request_debug_mode_done_f,[Default]), UsedName(internal_pmu_fw_halt_mode,[Default]), UsedName(dbg_run_state_ns,[Default]), UsedName(debug_halt_req_d1,[Default]), UsedName(debug_brkpt_status_ns,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(nmi_int_detected,[Default]), UsedName(internal_dbg_halt_timers,[Default]), UsedName(e4e5_valid,[Default]), UsedName(reset_detect,[Default]), UsedName(update_hit_bit_r,[Default]), UsedName(ext_int_freeze,[Default]), UsedName(rvecc_encode,[Default]), UsedName(enter_pmu_fw_halt_req,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ce_int_ready,[Default]), UsedName(ext_int_freeze_d1,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(dbg_cmd_done_ns,[Default]), UsedName(MIP_MITIP0,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(dcsr_single_step_done_f,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(tlu_flush_lower_r_d1,[Default]), UsedName(lsu_pmu_load_external_r,[Default]), UsedName(ignore_ext_int_due_to_lsu_stall,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(synchronous_flush_r,[Default]), UsedName(trigger_hit_dmode_r_d1,[Default]), UsedName(ebreak_r,[Default]), UsedName(rvlsadder,[Default]), UsedName(take_ext_int_start_d2,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(dec_tlu_br0_error_r,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(trigger_execute,[Default]), UsedName(tlu_flush_path_r_d1,[Default]), UsedName(mpc_debug_halt_req_sync_raw,[Default]), UsedName(vectored_path,[Default]), UsedName(lsu_exc_st_r,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(dec_pause_state_f,[Default]), UsedName(MTDATA1_MATCH,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(internal_dbg_halt_mode_f,[Default]), UsedName(rfpc_i0_r,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(inst_acc_second_r,[Default]), UsedName(mie_ns,[Default]), UsedName(dbg_tlu_halted_f,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(iccm_repair_state_ns,[Default]), UsedName(iccm_sbecc_r_d1,[Default]), UsedName(lsu_single_ecc_error_r,[Default]), UsedName(circuitName,[Default]), UsedName(i0_iside_trigger_has_pri_r,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(MIP_MSIP,[Default]), UsedName(int_timer0_int_possible,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(int_timer1_int_hold,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(nmi_lsu_detected,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(mpc_debug_run_ack_ns,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_pmu_store_external_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(debug_brkpt_status_f,[Default]), UsedName(take_ce_int,[Default]), UsedName(dec_tlu_br0_start_error_r,[Default]), UsedName(npc_r_d1,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(i_cpu_halt_req_sync,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(int_timer0_int_ready,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(block_interrupts,[Default]), UsedName(ebreak_to_debug_mode_r_d1,[Default]), UsedName(take_int_timer1_int,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(dcsr,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(dcsr_single_step_done,[Default]), UsedName(i0_exception_valid_r,[Default]), UsedName(lsu_i0_exc_r,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(dbg_halt_req_held,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(MTDATA1_ACTION,[Default]), UsedName(lsu_error_pkt_addr_r,[Default]), UsedName(mstatus_mie_ns,[Default]), UsedName(dec_tlu_flush_pause_r_d1,[Default]), UsedName(pmu_fw_tlu_halted_f,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(exc_or_int_valid_r_d1,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(dbg_halt_req_held_ns,[Default]), UsedName(take_int_timer0_int,[Default]), UsedName(MTDATA1_DMODE,[Default]), UsedName(tlu_flush_path_r,[Default]), UsedName(trigger_hit_r_d1,[Default]), UsedName(inst_acc_r,[Default]), UsedName(nmi_lsu_load_type,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(mpc_debug_run_req_sync,[Default]), UsedName(timer_int_sync,[Default]), UsedName(dec_tlu_mpc_halted_only_ns,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dbg_tlu_halted,[Default]), UsedName(ic_perr_r_d1,[Default]), UsedName(mpc_debug_run_req_sync_pulse,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(sel_npc_resume,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(trigger_action,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(MTDATA1_ST,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(MCPC,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(MTDATA1_SEL,[Default]), UsedName(sel_fir_addr,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(iccm_sbecc_r,[Default]), UsedName(timer_int_ready,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(ebreak_to_debug_mode_r,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(trigger_data,[Default]), UsedName(i_cpu_run_req_d1_raw,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(mstatus,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dbg_halt_state_f,[Default]), UsedName(mpc_debug_halt_req_sync,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(i0_valid_wb,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(debug_mode_status,[Default]), UsedName(finalize,[Default]), UsedName(pmu_fw_halt_req_ns,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(mpc_debug_run_ack_f,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(request_debug_mode_r_d1,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(mdseac_locked_ns,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(trigger_enabled,[Default]), UsedName(debug_resume_req,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(debug_halt_req_f,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(pause_expired_wb,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(MTDATA1_LD,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(inst_acc_r_raw,[Default]), UsedName(enter_debug_halt_req,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(halt_taken,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(lsu_i0_exc_r_d1,[Default]), UsedName(rvclkhdr,[Default]), UsedName(lsu_idle_any_f,[Default]), UsedName(mpc_debug_halt_ack_f,[Default]), UsedName(valid_csr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(i0trigger_qual_r,[Default]), UsedName(dpc,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(conditionally_illegal,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(force_halt,[Default]), UsedName(take_timer_int,[Default]), UsedName(lsu_single_ecc_error_r_d1,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(csr,[Default]), UsedName(dec_tlu_br0_v_r,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mtvec,[Default]), UsedName(dcsr_single_step_running_f,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(i0_exception_valid_r_d1,[Default]), UsedName(lsu_exc_valid_r_raw,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(i0_trigger_action_r,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(internal_pmu_fw_halt_mode_f,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(nmi_lsu_load_type_f,[Default]), UsedName(clk_override,[Default]), UsedName(MIE_MITIE1,[Default]), UsedName(take_ext_int_start_d3,[Default]), UsedName(MSTATUS_MIE,[Default]), UsedName(i0_trigger_hit_r,[Default]), UsedName(exc_or_int_valid_r,[Default]), UsedName(take_ext_int,[Default]), UsedName(core_empty,[Default]), UsedName(gated_latch,[Default]), UsedName(take_nmi,[Default]), UsedName(npc_r,[Default]), UsedName(dec_tlu_wr_pause_r_d1,[Default]), UsedName(int_timer0_int_hold,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(int_timer_stalled,[Default]), UsedName(mpc_debug_halt_req_sync_f,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(trigger_store,[Default]), UsedName(syncro_ff,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(MIP_MCEIP,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(MIE_MCEIE,[Default]), UsedName(dcsr_single_step_running,[Default]), UsedName(MIE_MSIE,[Default]), UsedName(tlu_flush_lower_r,[Default]), UsedName(int_timer0_int_hold_f,[Default]), UsedName(_onModuleClose,[Default]), UsedName(soft_int_ready,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(DCSR_STOPC,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(csr_read,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(pause_expired_r,[Default]), UsedName(csr_wr_clk,[Default]), UsedName(PIC_BITS,[Default]), UsedName(nmi_int_delayed,[Default]), UsedName(mpc_run_state_f,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(i0_trigger_eval_r,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(ecall_r,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(flush_clkvalid,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(nmi_lsu_store_type,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(internal_dbg_halt_mode,[Default]), UsedName(csr_pkt,[Default]), UsedName(getModulePorts,[Default]), UsedName(cpu_halt_ack,[Default]), UsedName(MTDATA1_M_ENABLED,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(pmu_fw_tlu_halted,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(mhwakeup_ready,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(i_cpu_run_req_d1,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(MIP_MTIP,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(i0_lsu_trigger_has_pri_r,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mret_r,[Default]), UsedName(mpc_halt_state_f,[Default]), UsedName(nmi_lsu_store_type_f,[Default]), UsedName(dbg_halt_req_final,[Default]), UsedName(cpu_run_ack,[Default]), UsedName(i_cpu_run_req_sync_qual,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(e4e5_clk,[Default]), UsedName(el2_dec_tlu_ctl,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(interrupt_path,[Default]), UsedName(debug_resume_req_f,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(lsu_exc_ma_r,[Default]), UsedName(pmu_fw_halt_req_f,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(lsu_i0_rfnpc_r,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(fence_i_r,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(take_ext_int_start_d1,[Default]), UsedName(getRef,[Default]), UsedName(allow_dbg_halt_csr_write,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ext_halt_pulse,[Default]), UsedName(reset_delayed,[Default]), UsedName(tlu_i0_commit_cmt,[Default]), UsedName(i_cpu_halt_req_sync_qual,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(fw_halt_req,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(nmi_int_sync,[Default]), UsedName(mpc_run_state_ns,[Default]), UsedName(lsu_exc_valid_r,[Default]), UsedName(mepc_trigger_hit_sel_pc_r,[Default]), UsedName(mpc_debug_halt_ack_ns,[Default]), UsedName(e4e5_int_clk,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(interrupt_valid_r_d1,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(take_reset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(request_debug_mode_done,[Default]), UsedName(compileOptions,[Default]), UsedName(i0_trigger_r,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(mtdata1_t,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(cpu_halt_status,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(internal_dbg_halt_mode_f2,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(lsu_r_wb_clk,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(take_ext_int_start,[Default]), UsedName(nmi_int_detected_f,[Default]), UsedName(DCSR_EBREAKM,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(debug_brkpt_valid,[Default]), UsedName(take_soft_int,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(ifu_miss_state_idle_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu_exc_valid_r_d1,[Default]), UsedName(halt_taken_f,[Default]), UsedName(int_timer1_int_hold_f,[Default]), UsedName(mepc,[Default]), UsedName(debug_halt_req,[Default]), UsedName(mpc_halt_state_ns,[Default]), UsedName(fast_int_meicpct,[Default]), UsedName(mpc_debug_halt_req_sync_pulse,[Default]), UsedName(MIE_MITIE0,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(exc_cause_wb,[Default]), UsedName(dbg_run_state_f,[Default]), UsedName(int_timer1_int_possible,[Default]), UsedName($asInstanceOf,[Default]), UsedName(int_timer1_int_ready,[Default]), UsedName(mip,[Default]), UsedName(wait,[Default]), UsedName(i_cpu_halt_req_d1,[Default]), UsedName(suggestedName,[Default]), UsedName(dec_tlu_flush_noredir_r_d1,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(int_timers,[Default]), UsedName(take_halt,[Default]), UsedName(debug_halt_req_ns,[Default]), UsedName(i0_trigger_chain_masked_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(trigger_hit_dmode_r,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(dbg_halt_state_ns,[Default]), UsedName(MTDATA1_CHAIN,[Default]), UsedName(interrupt_valid_r,[Default]), UsedName(DCSR_STEP,[Default]), UsedName(tlu_i0_kill_writeb_r,[Default]), UsedName(sel_npc_r,[Default]), UsedName(mpc_debug_run_req_sync_f,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(exc_cause_r,[Default]), UsedName(DCSR_STEPIE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(MTDATA1_EXE,[Default]), UsedName(MIE_MEIE,[Default]))) invalidates 1 classes due to The dec.el2_dec_tlu_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_tlu_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_decode_ctl...
-[debug] Initial set of included nodes: dec.dec_decode_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode_ctl)
-[debug] The following member ref dependencies of dec.dec_decode_ctl are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_decode_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(nonblock_load_rd,[Default]), UsedName(dec_alu,[Default]), UsedName(i0_instr_error,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_tlu_i0_kill_writeb_wb,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(i0_wb_ctl_en,[Default]), UsedName(dec_ib0_valid_d,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(i0_br_unpred,[Default]), UsedName(MEM_CAL,[Default]), UsedName(i0_br_error_all,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(i0_br_error,[Default]), UsedName(cam_wen,[Default]), UsedName(i0_nonblock_load_stall,[Default]), UsedName(cam_in,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(flush_final_r,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(prior_inflight_eff,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(i0_result_r,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(i0_rs2_nonblock_load_bypass_en_d,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(free_clk,[Default]), UsedName(dec_pmu_postsync_stall,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(csr_clr_d,[Default]), UsedName(x_d_in,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(i0_load_block_d,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(i0_rd_en_d,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(dec_pmu_presync_stall,[Default]), UsedName(dec_pmu_decode_stall,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(i0_rs1_class_d,[Default]), UsedName(i0_predict_br,[Default]), UsedName(nonblock_load_cancel,[Default]), UsedName(dec_i0_pc4_d,[Default]), UsedName(div_active_in,[Default]), UsedName(rvecc_encode,[Default]), UsedName(i0_nonblock_boundary_stall,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(dec_i0_dbecc_d,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(tlu_wr_pause_r2,[Default]), UsedName(pause_state_in,[Default]), UsedName(dec_tlu_presync_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec_i0_icaf_type_d,[Default]), UsedName(dec_pmu_instr_decoded,[Default]), UsedName(csr_data_wen,[Default]), UsedName(dec_debug_fence_d,[Default]), UsedName(csr_imm_x,[Default]), UsedName(i0_store_stall_d,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(illegal_lockout,[Default]), UsedName(r_d_in,[Default]), UsedName(i0_inst_wb,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(dec_csr_wen_unq_d,[Default]), UsedName(clear_pause,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(lsu_idle,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(lsu_trigger_match_r,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(pause_state,[Default]), UsedName(div_e1_to_r,[Default]), UsedName(i0_rs2bypass,[Default]), UsedName(lsu_store_stall_any,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(i0_exublock_d,[Default]), UsedName(i0_x_data_en,[Default]), UsedName(i0_notbr_error,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(csr_read_x,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(i0_wen_r,[Default]), UsedName(decode_exu,[Default]), UsedName(load_ldst_bypass_d,[Default]), UsedName(getPorts,[Default]), UsedName(dec_div,[Default]), UsedName(div_flush,[Default]), UsedName(i0_r_data_en,[Default]), UsedName(i0_br_toffset_error,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(i0_wb_data_en,[Default]), UsedName(x_t,[Default]), UsedName(i0_brp_valid,[Default]), UsedName(dctl_busbuff,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(dec_i0_wen_r,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(r_t,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(dec_csr_stall_int_ff,[Default]), UsedName(_namespace,[Default]), UsedName(illegal_inst_en,[Default]), UsedName(dec_csr_rddata_d,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(csr_set_d,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(cam_write,[Default]), UsedName(Tag_Word,[Default]), UsedName(i0_pret_case,[Default]), UsedName(ld_stall_2,[Default]), UsedName(LSU2DMA,[Default]), UsedName(leak1_mode,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(i0_pja,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(lsu_decode_d,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(i0_x_c,[Default]), UsedName(i0_pret_raw,[Default]), UsedName(i0_result_x,[Default]), UsedName(dec_tlu_pipelining_disable,[Default]), UsedName(r_d,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(ld_stall_1,[Default]), UsedName(cam_inv_reset_tag,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_brp,[Default]), UsedName(i0_exudecode_d,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(dec_pause_state,[Default]), UsedName(store_data_bypass_m,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(i0_exulegal_decode_d,[Default]), UsedName(forceName,[Default]), UsedName(prior_inflight_x,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(csr_mask_x,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(i0_legal,[Default]), UsedName(dec_pause_state_cg,[Default]), UsedName(dec_tlu_wr_pause_r,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(i0_icaf_d,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(i0_dec,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(i0_postsync,[Default]), UsedName(postsync_stall,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(dec_div_active,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(debug_fence_raw,[Default]), UsedName(d_t,[Default]), UsedName(i0_r_ctl_en,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(dec_i0_rs1_d,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(dec_i0_rs2_d,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(i0_wb1_data_en,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(i0_pcall_raw,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(div_decode_d,[Default]), UsedName(i0_dp_raw,[Default]), UsedName(i0_result_corr_r,[Default]), UsedName(i0_wb_en,[Default]), UsedName(dec_tlu_flush_leak_one_r,[Default]), UsedName(i0_predict_t,[Default]), UsedName(dec_csr_legal_d,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(dec_tlu_debug_stall,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(cam_inv_reset_val,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(load_data_tag,[Default]), UsedName(csr_ren_qual_d,[Default]), UsedName(csr_write_d,[Default]), UsedName(finalize,[Default]), UsedName(i0_pc_wb,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(i0_rs2_depth_d,[Default]), UsedName(i0,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(i0_pja_case,[Default]), UsedName(i0_result_r_raw,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(dec_i0_bp_index,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(i0_immed_d,[Default]), UsedName(ps_stall_in,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(i0_pcall_imm,[Default]), UsedName(i0_pcall_12b_offset,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(debug_fence_i,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(waddr,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(i0_wb1_en,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_i0_valid_r,[Default]), UsedName(rvdffe,[Default]), UsedName(i0_uiimm20,[Default]), UsedName(i0_pcall,[Default]), UsedName(i0_csr_write_only_d,[Default]), UsedName(dec_i0_bp_fghr,[Default]), UsedName(i0_block_d,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(leak1_i0_stall,[Default]), UsedName(store_data_bypass_d,[Default]), UsedName(cam_data_reset,[Default]), UsedName(i0_pja_raw,[Default]), UsedName(rvclkhdr,[Default]), UsedName(i0_inst_x,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dctl_dma,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(i0_rs2_class_d,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(i0_d_c,[Default]), UsedName(illegal_lockout_in,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(i0_ret_error,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(r_t_in,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(prior_csr_write,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(data_gate_en,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(nonblock_load_write,[Default]), UsedName(clk_override,[Default]), UsedName(write_csr_data,[Default]), UsedName(leak1_i1_stall_in,[Default]), UsedName(gated_latch,[Default]), UsedName(dec_csr_wen_r,[Default]), UsedName(div_inst,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(dec_tlu_packet_r,[Default]), UsedName(i0_rs1_depend_i0_r,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(data_gate_clk,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(i0_rs2_depend_i0_r,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(i0_pret,[Default]), UsedName(i0_csr_write,[Default]), UsedName(_onModuleClose,[Default]), UsedName(i0_predict_nt,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(dec_i0_instr_d,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_i0_wdata_r,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(csr_write_x,[Default]), UsedName(dec_tlu_i0_kill_writeb_r,[Default]), UsedName(dec_i0_pc_r,[Default]), UsedName(last_br_immed_d,[Default]), UsedName(cam_write_tag,[Default]), UsedName(dec_tlu_flush_pause_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(csr_read,[Default]), UsedName(i0_rs2_depend_i0_x,[Default]), UsedName(debug_fence,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(dec_tlu_postsync_d,[Default]), UsedName(io,[Default]), UsedName(dec_i0_waddr_r,[Default]), UsedName(clone,[Default]), UsedName(cam,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(cam_raw,[Default]), UsedName(lsu_load_stall_any,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(i0_legal_decode_d,[Default]), UsedName(leak1_i0_stall_in,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(write_csr_data_in,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(i0_ap_pc4,[Default]), UsedName(i0_div_decode_d,[Default]), UsedName(dec_csr_any_unq_d,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(i0_nonblock_div_stall,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(temp_pred_correct_npc_x,[Default]), UsedName(dec_i0_icaf_d,[Default]), UsedName(i0_rs1_depth_d,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(prior_inflight,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(presync_stall,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(i0r,[Default]), UsedName($isInstanceOf,[Default]), UsedName(i0_jalimm20,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(dbg_dctl,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(cal_temp,[Default]), UsedName(i0_pcall_case,[Default]), UsedName(lsu_pmu_misaligned_r,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(csrimm_x,[Default]), UsedName(i0_div_prior_div_stall,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(any_csr_d,[Default]), UsedName(i0_inst_wb_in,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(i0_ap_pc2,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(i0_jal,[Default]), UsedName(csr_write,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(mul_decode_d,[Default]), UsedName(dec_i0_bp_btag,[Default]), UsedName(i0_r_c,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(i0_dp,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(i0_block_raw_d,[Default]), UsedName(csr_set_x,[Default]), UsedName(dec;dec_decode_ctl;init;,[Default]), UsedName(i0_rs1_nonblock_load_bypass_en_d,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(i0_x_ctl_en,[Default]), UsedName(nonblock_div_cancel,[Default]), UsedName(tlu_wr_pause_r1,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(cam_data_reset_tag,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(nonblock_load_valid_m_delay,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(i0_pipe_en,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(dec_nonblock_load_waddr,[Default]), UsedName(write_csr_data_x,[Default]), UsedName(i0_load_kill_wen_r,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(wbd,[Default]), UsedName(addCommand,[Default]), UsedName(cam_data_reset_val,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(div_waddr_wb,[Default]), UsedName(dec_i0_icaf_f1_d,[Default]), UsedName(parentModName,[Default]), UsedName(i0_rs1bypass,[Default]), UsedName(getClass,[Default]), UsedName(i0_inst_d,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(x_d,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(i0_presync,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(lsu_idle_any,[Default]), UsedName(i0_rs1_depend_i0_x,[Default]), UsedName(dec_nonblock_load_wen,[Default]), UsedName(isClosed,[Default]), UsedName(lsu_pmu_misaligned_m,[Default]), UsedName(leak1_i1_stall,[Default]), UsedName(x_t_in,[Default]), UsedName(csr_rddata_x,[Default]), UsedName(pause_stall,[Default]), UsedName(i0_br_offset,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(dec_decode_ctl,[Default]), UsedName(cam_inv_reset,[Default]), UsedName(active_clk,[Default]), UsedName(dec_illegal_inst,[Default]), UsedName(dec_aln,[Default]), UsedName(shift_illegal,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(dec_tlu_i0_pc_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(d_d,[Default]), UsedName(dec_tlu_flush_extint,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(i0_load_stall_d,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(i0_inst_r,[Default]), UsedName(prior_inflight_wb,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(csr_clr_x,[Default]), UsedName(last_br_immed_x,[Default]))) invalidates 2 classes due to The dec.dec_decode_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_decode_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.rvdffe...
-[debug] Initial set of included nodes: lib.lib.rvdffe
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.rvdffe)
-[debug] The following modified names cause invalidation of exu.exu: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_decode_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_gpr_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]))
-[debug] The following modified names cause invalidation of exu.exu_div_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(isInstanceOf,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(isInstanceOf,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of dec.csr_tlu: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of exu.exu_alu_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(eq,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_ecc: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(isInstanceOf,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_timer_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]))
-[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]))
-[debug] The following modified names cause invalidation of exu.exu_mul_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_dccm_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_bp_ctl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_stbuf: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_ifc_ctl: Set(UsedName(isInstanceOf,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(apply,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]))
-[debug] Change NamesChange(lib.lib.rvdffe,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 20 classes due to The lib.lib.rvdffe has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.rvdffe)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu, dec.dec_decode_ctl, dec.dec_gpr_ctl, exu.exu_div_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, dec.csr_tlu, exu.exu_alu_ctl, lsu.lsu_ecc, lsu.lsu_bus_buffer, dec.dec_timer_ctl, ifu.ifu_aln_ctl, dbg.dbg, exu.exu_mul_ctl, lsu.lsu_dccm_ctl, ifu.ifu_bp_ctl, lsu.lsu_stbuf, ifu.ifu_ifc_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.tlu_exu...
-[debug] Initial set of included nodes: include.tlu_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.tlu_exu)
-[debug] The following member ref dependencies of include.tlu_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	exu.exu
-[debug] 	quasar
-[debug] Change NamesChange(include.tlu_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(exu_pmu_i0_br_ataken,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(exu_i0_br_mp_r,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(exu_npc_r,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(exu_pmu_i0_pc4,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(exu_pmu_i0_br_misp,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(include;tlu_exu;init;,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(exu_i0_br_index_r,[Default]), UsedName(exu_i0_br_error_r,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(exu_i0_br_start_error_r,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(exu_i0_br_middle_r,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(tlu_exu,[Default]), UsedName(exu_i0_br_hist_r,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(exu_i0_br_valid_r,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(dec_tlu_flush_path_r,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(dec_tlu_meihap,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.tlu_exu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.tlu_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, exu.exu, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_dec_ctl...
-[debug] Initial set of included nodes: dec.dec_dec_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_dec_ctl)
-[debug] The following member ref dependencies of dec.dec_dec_ctl are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(dec.dec_dec_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(main,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(dec;dec_dec_ctl;init;,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(pattern,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ins,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(executionStart,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(delayedInit,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(dec_dec_ctl,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(args,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dec.dec_dec_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_dec_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from QUASAR_Wrp...
-[debug] Initial set of included nodes: QUASAR_Wrp
-[debug] Invalidated by transitive inheritance dependency: Set(QUASAR_Wrp)
-[debug] Change NamesChange(QUASAR_Wrp,ModifiedNames(changes = UsedName(QUASAR_Wrp,[Default]), UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The QUASAR_Wrp has the following regular definitions changed:
-[debug] 	UsedName(QUASAR_Wrp,[Default]), UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(QUASAR_Wrp)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvsyncss...
-[debug] Initial set of included nodes: lib.rvsyncss
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvsyncss)
-[debug] Change NamesChange(lib.rvsyncss,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(sync_ff1,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(lib;rvsyncss;init;,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rvsyncss,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(sync_ff2,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvsyncss has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(sync_ff1,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(lib;rvsyncss;init;,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rvsyncss,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(sync_ff2,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvsyncss)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_inst_pkt_t...
-[debug] Initial set of included nodes: include.el2_inst_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_inst_pkt_t)
-[debug] Change NamesChange(include.el2_inst_pkt_t,ModifiedNames(changes = UsedName(STORE,[Default]), UsedName(ValueSet,[Default]), UsedName(CONDBR,[Default]), UsedName(isInstanceOf,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(synchronized,[Default]), UsedName(nextId,[Default]), UsedName(ValueOrdering,[Default]), UsedName(toString,[Default]), UsedName(maxId,[Default]), UsedName(el2_inst_pkt_t,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(withName,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(Val,[Default]), UsedName(nextName,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(Value,[Default]), UsedName(values,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ECALL,[Default]), UsedName(BITMANIPU,[Default]), UsedName(NULL,[Default]), UsedName(notify,[Default]), UsedName(FENCEI,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(readResolve,[Default]), UsedName(FENCE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The include.el2_inst_pkt_t has the following regular definitions changed:
-[debug] 	UsedName(STORE,[Default]), UsedName(ValueSet,[Default]), UsedName(CONDBR,[Default]), UsedName(isInstanceOf,[Default]), UsedName(CSRWRITE,[Default]), UsedName(MRET,[Default]), UsedName(synchronized,[Default]), UsedName(nextId,[Default]), UsedName(ValueOrdering,[Default]), UsedName(toString,[Default]), UsedName(maxId,[Default]), UsedName(el2_inst_pkt_t,[Default]), UsedName(apply,[Default]), UsedName(MUL,[Default]), UsedName(CSRRW,[Default]), UsedName(LOAD,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(withName,[Default]), UsedName(ALU,[Default]), UsedName(CSRREAD,[Default]), UsedName(Val,[Default]), UsedName(nextName,[Default]), UsedName(JAL,[Default]), UsedName(EBREAK,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(Value,[Default]), UsedName(values,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ECALL,[Default]), UsedName(BITMANIPU,[Default]), UsedName(NULL,[Default]), UsedName(notify,[Default]), UsedName(FENCEI,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(readResolve,[Default]), UsedName(FENCE,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(include.el2_inst_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_bp...
-[debug] Initial set of included nodes: include.dec_bp
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_bp)
-[debug] The following member ref dependencies of include.dec_bp are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_bp_ctl
-[debug] Change NamesChange(include.dec_bp,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(include;dec_bp;init;,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(dec_bp,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(dec_tlu_br0_r_pkt,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(dec_tlu_bpred_disable,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(dec_tlu_flush_leak_one_wb,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dec_bp has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_bp)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, ifu.ifu, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, ifu.ifu_bp_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_trap_pkt_t...
-[debug] Initial set of included nodes: include.el2_trap_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_trap_pkt_t)
-[debug] Change NamesChange(include.el2_trap_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(icaf_type,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(include;el2_trap_pkt_t;init;,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(icaf,[Default]), UsedName(do_asUInt,[Default]), UsedName(el2_trap_pkt_t,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(pmu_divide,[Default]), UsedName($isInstanceOf,[Default]), UsedName(icaf_f1,[Default]), UsedName(i0trigger,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(fence_i,[Default]), UsedName(pmu_i0_br_unpred,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pmu_i0_itype,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(pmu_lsu_misaligned,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_trap_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_trap_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_br_tlu_pkt_t...
-[debug] Initial set of included nodes: include.el2_br_tlu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_br_tlu_pkt_t)
-[debug] Change NamesChange(include.el2_br_tlu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(include;el2_br_tlu_pkt_t;init;,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(middle,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(el2_br_tlu_pkt_t,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_br_tlu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_br_tlu_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.gated_latch...
-[debug] Initial set of included nodes: lib.el2_lib.gated_latch
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.gated_latch)
-[debug] Change NamesChange(lib.el2_lib.gated_latch,ModifiedNames(changes = UsedName(SE,[Default]), UsedName(_closed,[Default]), UsedName(CK,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Q,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(gated_latch,[Default]), UsedName(EN,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(lib;el2_lib;gated_latch;init;,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.gated_latch has the following regular definitions changed:
-[debug] 	UsedName(SE,[Default]), UsedName(_closed,[Default]), UsedName(CK,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Q,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(gated_latch,[Default]), UsedName(EN,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(lib;el2_lib;gated_latch;init;,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.gated_latch)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_ic_tag_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.el2_ic_tag_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_ic_tag_ext_in_pkt_t)
-[debug] Change NamesChange(include.el2_ic_tag_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(el2_ic_tag_ext_in_pkt_t,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(include;el2_ic_tag_ext_in_pkt_t;init;,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_ic_tag_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_ic_tag_ext_in_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_div_pkt_t...
-[debug] Initial set of included nodes: include.el2_div_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_div_pkt_t)
-[debug] Change NamesChange(include.el2_div_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(include;el2_div_pkt_t;init;,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(el2_div_pkt_t,[Default]), UsedName(rem,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_div_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_div_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dma_dccm_ctl...
-[debug] Initial set of included nodes: include.dma_dccm_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(include.dma_dccm_ctl)
-[debug] The following member ref dependencies of include.dma_dccm_ctl are invalidated:
-[debug] 	dma_ctrl
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_dccm_ctl
-[debug] Change NamesChange(include.dma_dccm_ctl,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(dccm_dma_rtag,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(dccm_dma_rdata,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dccm_dma_ecc_error,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(dma_mem_addr,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(dccm_dma_rvalid,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(include;dma_dccm_ctl;init;,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(dma_dccm_ctl,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dma_mem_wdata,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.dma_dccm_ctl has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dma_dccm_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, lsu.lsu_dccm_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_dccm_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.el2_dccm_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_dccm_ext_in_pkt_t)
-[debug] Change NamesChange(include.el2_dccm_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(el2_dccm_ext_in_pkt_t,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(include;el2_dccm_ext_in_pkt_t;init;,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_dccm_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_dccm_ext_in_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.read_data...
-[debug] Initial set of included nodes: include.read_data
-[debug] Invalidated by transitive inheritance dependency: Set(include.read_data)
-[debug] The following member ref dependencies of include.read_data are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dma_ctrl
-[debug] 	ifu.ifu_mem_ctl
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	quasar
-[debug] Change NamesChange(include.read_data,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(data,[Default]), UsedName(last,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(include;read_data;init;,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(resp,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(<init>$default$1,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(read_data,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(id,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.read_data has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.read_data)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_br_pkt_t...
-[debug] Initial set of included nodes: include.el2_br_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_br_pkt_t)
-[debug] Change NamesChange(include.el2_br_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(toffset,[Default]), UsedName(ret,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(include;el2_br_pkt_t;init;,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(br_error,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(prett,[Default]), UsedName(el2_br_pkt_t,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(br_start_error,[Default]), UsedName(bank,[Default]), UsedName(_parent,[Default]), UsedName(way,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(hist,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_br_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_br_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.gated_latch...
-[debug] Initial set of included nodes: lib.lib.gated_latch
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.gated_latch)
-[debug] Change NamesChange(lib.lib.gated_latch,ModifiedNames(changes = UsedName(SE,[Default]), UsedName(lib;lib;gated_latch;init;,[Default]), UsedName(_closed,[Default]), UsedName(CK,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Q,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(gated_latch,[Default]), UsedName(EN,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.lib.gated_latch has the following regular definitions changed:
-[debug] 	UsedName(SE,[Default]), UsedName(lib;lib;gated_latch;init;,[Default]), UsedName(_closed,[Default]), UsedName(CK,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(setResource,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Q,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(gated_latch,[Default]), UsedName(EN,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(params,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(addResource,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.gated_latch)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_dest_pkt_t...
-[debug] Initial set of included nodes: include.el2_dest_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_dest_pkt_t)
-[debug] Change NamesChange(include.el2_dest_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(i0v,[Default]), UsedName(ignoreSeq,[Default]), UsedName(csrwaddr,[Default]), UsedName(include;el2_dest_pkt_t;init;,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(csrwen,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(i0store,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(i0valid,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(i0div,[Default]), UsedName(i0load,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(el2_dest_pkt_t,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(csrwonly,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(i0rd,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_dest_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_dest_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_class_pkt_t...
-[debug] Initial set of included nodes: include.el2_class_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_class_pkt_t)
-[debug] Change NamesChange(include.el2_class_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(el2_class_pkt_t,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(alu,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(mul,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(include;el2_class_pkt_t;init;,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_class_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_class_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.el2_lsu...
-[debug] Initial set of included nodes: lsu.el2_lsu
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.el2_lsu)
-[debug] Change NamesChange(lsu.el2_lsu,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(lsu;el2_lsu;init;,[Default]), UsedName(el2_lsu,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lsu.el2_lsu has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(lsu;el2_lsu;init;,[Default]), UsedName(el2_lsu,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lsu.el2_lsu)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.rvclkhdr...
-[debug] Initial set of included nodes: lib.el2_lib.rvclkhdr
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.rvclkhdr)
-[debug] Change NamesChange(lib.el2_lib.rvclkhdr,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(clkhdr,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(apply,[Default]), UsedName(lib;el2_lib;rvclkhdr;init;,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(l1clk,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(clk,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.rvclkhdr has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(clkhdr,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(apply,[Default]), UsedName(lib;el2_lib;rvclkhdr;init;,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(l1clk,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(clk,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.rvclkhdr)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_dec_tlu_csr_pkt...
-[debug] Initial set of included nodes: include.el2_dec_tlu_csr_pkt
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_dec_tlu_csr_pkt)
-[debug] Change NamesChange(include.el2_dec_tlu_csr_pkt,ModifiedNames(changes = UsedName(csr_mcycleh,[Default]), UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(csr_marchid,[Default]), UsedName(csr_mfdc,[Default]), UsedName(csr_dicad1,[Default]), UsedName(ignoreSeq,[Default]), UsedName(presync,[Default]), UsedName(csr_mfdht,[Default]), UsedName(csr_mhartid,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(csr_mtdata1,[Default]), UsedName(asUInt,[Default]), UsedName(csr_mitctl1,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(csr_mdeau,[Default]), UsedName(isInstanceOf,[Default]), UsedName(csr_miccmect,[Default]), UsedName(csr_mtsel,[Default]), UsedName(csr_mtval,[Default]), UsedName(:=,[Default]), UsedName(csr_meivt,[Default]), UsedName(csr_micect,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(csr_mvendorid,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(csr_mip,[Default]), UsedName(csr_mhpmc3,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(csr_mitb0,[Default]), UsedName(csr_minstreth,[Default]), UsedName(csr_mhpmc6h,[Default]), UsedName(csr_mhpmc4h,[Default]), UsedName(toString,[Default]), UsedName(csr_dmst,[Default]), UsedName(csr_dicago,[Default]), UsedName(csr_mtdata2,[Default]), UsedName(litArg,[Default]), UsedName(csr_meihap,[Default]), UsedName(csr_mhpmc5h,[Default]), UsedName(csr_mhpmc4,[Default]), UsedName(getElements,[Default]), UsedName(csr_mcountinhibit,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(csr_mhpmc5,[Default]), UsedName(csr_mhpme3,[Default]), UsedName(csr_mpmc,[Default]), UsedName(csr_meicpct,[Default]), UsedName(ref,[Default]), UsedName(csr_meipt,[Default]), UsedName(do_asUInt,[Default]), UsedName(csr_mstatus,[Default]), UsedName(csr_mrac,[Default]), UsedName(csr_mtvec,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(csr_mdseac,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(csr_dpc,[Default]), UsedName(setRef,[Default]), UsedName(csr_mitcnt0,[Default]), UsedName(csr_dicad0h,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(csr_mepc,[Default]), UsedName(csr_mhpme5,[Default]), UsedName(csr_dicad0,[Default]), UsedName(csr_meicurpl,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(csr_mhpmc3h,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(csr_mie,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(include;el2_dec_tlu_csr_pkt;init;,[Default]), UsedName(csr_mscratch,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(csr_mcyclel,[Default]), UsedName(csr_dicawics,[Default]), UsedName(notify,[Default]), UsedName(csr_mitctl0,[Default]), UsedName(postsync,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(csr_mcgc,[Default]), UsedName(csr_mcause,[Default]), UsedName(suggestName,[Default]), UsedName(csr_mcpc,[Default]), UsedName(eq,[Default]), UsedName(csr_mscause,[Default]), UsedName(pathName,[Default]), UsedName(csr_meicidpl,[Default]), UsedName(<>,[Default]), UsedName(csr_mimpid,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(csr_dcsr,[Default]), UsedName(csr_mhpme4,[Default]), UsedName(csr_mhpme6,[Default]), UsedName(csr_mfdhs,[Default]), UsedName(csr_mitb1,[Default]), UsedName(el2_dec_tlu_csr_pkt,[Default]), UsedName(csr_mitcnt1,[Default]), UsedName(csr_mdccmect,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(csr_mhpmc6,[Default]), UsedName(binding,[Default]), UsedName(csr_minstretl,[Default]), UsedName(getOptionRef,[Default]), UsedName(csr_misa,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_dec_tlu_csr_pkt has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_dec_tlu_csr_pkt)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_timer_ctl_IO...
-[debug] Initial set of included nodes: dec.dec_timer_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_timer_ctl_IO)
-[debug] Change NamesChange(dec.dec_timer_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dec_timer_t0_pulse,[Default]), UsedName(free_clk,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(dec_csr_wraddr_r,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(internal_dbg_halt_timers,[Default]), UsedName(asUInt,[Default]), UsedName(csr_mitctl1,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(dec_timer_rddata_d,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(dec;dec_timer_ctl_IO;init;,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dec_tlu_pmu_fw_halted,[Default]), UsedName(bind,[Default]), UsedName(csr_mitb0,[Default]), UsedName(toString,[Default]), UsedName(dec_csr_wrdata_r,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(dec_pause_state,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName(dec_timer_ctl_IO,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(csr_mitcnt0,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(csr_mitctl0,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(dec_timer_t1_pulse,[Default]), UsedName(pathName,[Default]), UsedName(dec_csr_wen_r_mod,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dec_timer_read_d,[Default]), UsedName(csr_mitb1,[Default]), UsedName(csr_mitcnt1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.dec_timer_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_timer_ctl_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.rvecc_encode_64...
-[debug] Initial set of included nodes: lib.el2_lib.rvecc_encode_64
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.rvecc_encode_64)
-[debug] Change NamesChange(lib.el2_lib.rvecc_encode_64,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName(lib;el2_lib;rvecc_encode_64;init;,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.rvecc_encode_64 has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(mask6,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName(lib;el2_lib;rvecc_encode_64;init;,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.rvecc_encode_64)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from el2_pic_ctrl...
-[debug] Initial set of included nodes: el2_pic_ctrl
-[debug] Invalidated by transitive inheritance dependency: Set(el2_pic_ctrl)
-[debug] Change NamesChange(el2_pic_ctrl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(EXT_INTR_GW_CLEAR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(picm_rden_ff,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(intpriority_reg_read,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(mhwakeup_in,[Default]), UsedName(free_clk,[Default]), UsedName(l2_intpend_id_ff,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(addr_intpend_base_match,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(intenable_reg_we,[Default]), UsedName(repl,[Default]), UsedName(prithresh_reg_read,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(el2_pic_ctrl;init;,[Default]), UsedName(intpend_reg_extended,[Default]), UsedName(pl,[Default]), UsedName(extintsrc_req_sync,[Default]), UsedName(picm_bypass_ff,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(intpriority_reg_we,[Default]), UsedName(picm_wren_ff,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(pic_raddr_c1_clken,[Default]), UsedName(INTPRIORITY_BASE_ADDR,[Default]), UsedName(picm_waddr_ff,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(picm_wraddr,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(picm_wr_data_ff,[Default]), UsedName(picm_raddr_ff,[Default]), UsedName(el2_cmp_and_mux,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mexintpend_in,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(intpriority_reg_re,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(intpend_reg_read,[Default]), UsedName(getChiselPorts,[Default]), UsedName(meipt_inv,[Default]), UsedName(synchronized,[Default]), UsedName(addr_clear_gw_base_match,[Default]), UsedName(intenable_reg,[Default]), UsedName(getPorts,[Default]), UsedName(INTPEND_BASE_ADDR,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(raddr_config_pic_match,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(pl_in,[Default]), UsedName(INTPEND_SIZE,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(intpriority_reg,[Default]), UsedName(pic_data_c1_clk,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(config_reg_re,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(prithresh_reg_write,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(gw_config_reg,[Default]), UsedName(Tag_Word,[Default]), UsedName(picm_rden,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(levelx_intpend_id,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(gw_config_reg_we,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(levelx_intpend_w_prior_en,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(pic_raddr_c1_clk,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(gw_config_rd_out,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(selected_int_priority,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(waddr_config_pic_match,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(meicurpl,[Default]), UsedName(gw_config_reg_re,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(picm_mken,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(config_reg,[Default]), UsedName(generateComponent,[Default]), UsedName(intpend_w_prior_en,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(meicurpl_inv,[Default]), UsedName(pic_int_c1_clk,[Default]), UsedName(picm_wren,[Default]), UsedName(raddr_config_gw_base_match,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(pic_pri_c1_clken,[Default]), UsedName(rvrangecheck,[Default]), UsedName(intenable_reg_read,[Default]), UsedName(finalize,[Default]), UsedName(picm_mken_ff,[Default]), UsedName(gw_config_c1_clk,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(address,[Default]), UsedName(asInstanceOf,[Default]), UsedName(pl_in_q,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(waddr_intenable_base_match,[Default]), UsedName(intenable_rd_out,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(mhwakeup,[Default]), UsedName(intpriority_rd_out,[Default]), UsedName(intpriority_reg_inv,[Default]), UsedName(picm_rdaddr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(mask,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(intpend_rd_part_out,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(gw_clear_reg_we,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(intenable_reg_re,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(INT_GRPS,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(EXT_INTR_PIC_CONFIG,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(pic_data_c1_clken,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(gw_config_c1_clken,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INTENABLE_BASE_ADDR,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(raddr_intenable_base_match,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(picm_wr_data,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(config_reg_in,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(maxint,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mexintpend,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(waddr_intpriority_base_match,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ID_BITS,[Default]), UsedName(extintsrc_req,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(GW_CONFIG,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(extintsrc_req_gw,[Default]), UsedName(picm_rd_data,[Default]), UsedName(claimid_in,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(intpriord,[Default]), UsedName(gw_config_reg_read,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(config_reg_we,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(claimid,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(l2_intpend_w_prior_en_ff,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(pic_int_c1_clken,[Default]), UsedName(INTPRIORITY_BITS,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(picm_rd_data_in,[Default]), UsedName(EXT_INTR_GW_CONFIG,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(intpend_id,[Default]), UsedName(temp_raddr_intenable_base_match,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(pic_pri_c1_clk,[Default]), UsedName(waddr_config_gw_base_match,[Default]), UsedName(raddr_intpriority_base_match,[Default]), UsedName(active_clk,[Default]), UsedName(NUM_LEVELS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(meipt,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(intpend_rd_out,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(el2_pic_ctrl,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]))) invalidates 1 classes due to The el2_pic_ctrl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(el2_pic_ctrl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.mul_pkt_t...
-[debug] Initial set of included nodes: include.mul_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.mul_pkt_t)
-[debug] The following member ref dependencies of include.mul_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] 	exu.exu_mul_ctl
-[debug] Change NamesChange(include.mul_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(crc32c_h,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(rs1_sign,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(clmulh,[Default]), UsedName(rs2_sign,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(crc32_h,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(crc32c_b,[Default]), UsedName(do_asUInt,[Default]), UsedName(clmulr,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(bdep,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(bext,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(low,[Default]), UsedName(grev,[Default]), UsedName(crc32_w,[Default]), UsedName(unshfl,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(crc32_b,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(bfp,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(crc32c_w,[Default]), UsedName(clmul,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(mul_pkt_t,[Default]), UsedName(shfl,[Default]), UsedName(include;mul_pkt_t;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.mul_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.mul_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_mul_ctl, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_main...
-[debug] Initial set of included nodes: dec.dec_main
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_main)
-[debug] Change NamesChange(dec.dec_main,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(dec_main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.dec_main has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(dec_main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec_main)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.alu...
-[debug] Initial set of included nodes: exu.alu
-[debug] Invalidated by transitive inheritance dependency: Set(exu.alu)
-[debug] Change NamesChange(exu.alu,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(alu,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The exu.alu has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(alu,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(exu.alu)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_reg_pkt_t...
-[debug] Initial set of included nodes: include.el2_reg_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_reg_pkt_t)
-[debug] Change NamesChange(include.el2_reg_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(rs1,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(rs2,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(el2_reg_pkt_t,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(include;el2_reg_pkt_t;init;,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_reg_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_reg_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.ifu_mem_ctl...
-[debug] Initial set of included nodes: ifu.ifu_mem_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_mem_ctl)
-[debug] The following member ref dependencies of ifu.ifu_mem_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] Change NamesChange(ifu.ifu_mem_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(final_data_out1,[Default]), UsedName(reset_beat_cnt,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(stream_eol_f,[Default]), UsedName(iccm_dma_rden,[Default]), UsedName(iccm_rd_ecc_single_err_ff,[Default]), UsedName(write_ic_16_bytes,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(fetch_req_f_qual,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(scnd_miss_req_ff2,[Default]), UsedName(iccm_dma_rdata_1_muxed,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ic_byp_data_only_new,[Default]), UsedName(ic_debug_tag_wr_en,[Default]), UsedName(way_status_wr_en_w_debug,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ic_iccm_hit_f,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(iccm_dma_ecc_error,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(bus_inc_data_beat_cnt,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ifu_bus_arready_ff,[Default]), UsedName(bus_rd_addr_count,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(miss_wrap_f,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ic_miss_buff_half,[Default]), UsedName(desiredName,[Default]), UsedName(ic_valid,[Default]), UsedName(repl,[Default]), UsedName(ic_miss_buff_data_valid,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(ifu_bus_rsp_rdata,[Default]), UsedName(busclk_reset,[Default]), UsedName(ifu_bus_cmd_ready,[Default]), UsedName(ifu_wr_cumulative_err_data,[Default]), UsedName(ifc_dma_access_ok_d,[Default]), UsedName(perr_nxtstate,[Default]), UsedName(ic_act_miss_f,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ecc_wff_C,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(err_stop_nxtstate,[Default]), UsedName(bus_ifu_wr_data_error,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ic_byp_hit_f,[Default]), UsedName(bus_ifu_wr_en,[Default]), UsedName(getIds,[Default]), UsedName(ifu_tag_wren_ff,[Default]), UsedName(ifu_status_wr_addr,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(scnd_miss_req,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bus_reset_cmd_beat_cnt_secondlast,[Default]), UsedName(ic_final_data,[Default]), UsedName(imb_scnd_in,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(fetch_uncacheable_ff,[Default]), UsedName(IO,[Default]), UsedName(ifu_wr_data_comb_err,[Default]), UsedName(bus_new_rd_addr_count,[Default]), UsedName(rvlsadder,[Default]), UsedName(miss_addr_in,[Default]), UsedName(err_idle_C,[Default]), UsedName(iccm_dma_ecc_error_in,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ifu_bus_rvalid_unq_ff,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(bus_ifu_bus_clk_en_ff,[Default]), UsedName(iccm_dma_rvalid_temp,[Default]), UsedName(ifu_wr_cumulative_err,[Default]), UsedName(ifc_region_acc_okay,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(debug_c1_clk,[Default]), UsedName(bus_hold_cmd_beat_cnt,[Default]), UsedName(ifu_bus_arvalid,[Default]), UsedName(dma_mem_addr_ff,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(way_status_new,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(ic_rd_parity_final_err,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(ic_wr_parity,[Default]), UsedName(circuitName,[Default]), UsedName(ic_debug_ict_array_sel_ff,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(crit_wd_byp_ok_ff,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(bus_inc_cmd_beat_cnt,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(bypass_index_5_3_inc,[Default]), UsedName(bus_last_data_beat,[Default]), UsedName(ic_valid_ff,[Default]), UsedName(last_beat,[Default]), UsedName(ic_miss_buff_data,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(hit_u_miss_C,[Default]), UsedName(way_status_mb_ff,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(ic_ignore_2nd_miss_f,[Default]), UsedName(sel_hold_imb,[Default]), UsedName(ic_crit_wd_rdy_new_in,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(miss_state,[Default]), UsedName(ifu_bus_rsp_ready,[Default]), UsedName(scnd_miss_index_match,[Default]), UsedName(iccm_rd_ecc_single_err_hold_in,[Default]), UsedName(debug_c1_clken,[Default]), UsedName(bus_ifu_wr_en_ff,[Default]), UsedName(ifc_bus_acc_fault_f,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(ic_miss_buff_data_in,[Default]), UsedName(bus_cmd_beat_count,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(err_fetch1_C,[Default]), UsedName(ifu_status_wr_addr_w_debug,[Default]), UsedName(iccm_rdmux_data,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(ic_tag_valid_unq,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ifu_bus_rdata_ff,[Default]), UsedName(Tag_Word,[Default]), UsedName(iccm_ecc_word_enable,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(uncacheable_miss_in,[Default]), UsedName(reset_tag_valid_for_miss,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(ic_miss_buff_data_error_bypass,[Default]), UsedName(tag_valid_clken,[Default]), UsedName(ic_miss_buff_ecc,[Default]), UsedName(byp_fetch_index_inc_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ic_act_hit_f,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(bus_new_data_beat_count,[Default]), UsedName(ifc_region_acc_fault_final_f,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(tagv_mb_ff,[Default]), UsedName(miss_wait_C,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(way_status_clk,[Default]), UsedName(ic_byp_data_only_pre_new,[Default]), UsedName(bus_ifu_bus_clk_en,[Default]), UsedName(dma_iccm_req_f,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(sel_hold_imb_scnd,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(ic_valid_w_debug,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(fetch_bf_f_c1_clk,[Default]), UsedName(dma_mem_tag_ff,[Default]), UsedName(forceName,[Default]), UsedName(ifc_fetch_req_f_raw,[Default]), UsedName(final_data_out2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(fetch_req_icache_f,[Default]), UsedName(ifu_status_wr_addr_ff,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(sel_mb_addr_ff,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(perr_state,[Default]), UsedName(byp_fetch_index,[Default]), UsedName(bus_cmd_req_hold,[Default]), UsedName(stall_scnd_miss_C,[Default]), UsedName(ifc_iccm_access_f,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(bus_reset_data_beat_cnt,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(crit_byp_ok_C,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(ifc_dma_access_q_ok,[Default]), UsedName(ifu;ifu_mem_ctl;init;,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(ifu_bus_rvalid_unq,[Default]), UsedName(ic_fetch_val_shift_right,[Default]), UsedName(iccm_corrected_data_f_mux,[Default]), UsedName(initializeInParent,[Default]), UsedName(way_status_new_w_debug,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(last_data_recieved_in,[Default]), UsedName(generateComponent,[Default]), UsedName(tagv_mb_scnd_ff,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ic_wff_C,[Default]), UsedName(replace_way_mb_any,[Default]), UsedName(nameIds,[Default]), UsedName(ic_debug_tag_val_rd_out,[Default]), UsedName(iccm_corrected_ecc_f_mux,[Default]), UsedName(ic_debug_rd_en_ff,[Default]), UsedName(imb_in,[Default]), UsedName(ifc_fetch_req_qual_bf,[Default]), UsedName(scnd_miss_req_q,[Default]), UsedName(uncacheable_miss_ff,[Default]), UsedName(sel_ic_data,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(iccm_dma_rdata_in,[Default]), UsedName(way_status_new_ff,[Default]), UsedName(ifu_bus_rresp_ff,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(vaddr_f,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(ifu_mem_ctl,[Default]), UsedName(way_status_mb_scnd_ff,[Default]), UsedName(rvrangecheck,[Default]), UsedName(ifc_bus_ic_req_ff_in,[Default]), UsedName(err_fetch2_C,[Default]), UsedName(ifc_region_acc_fault_final_bf,[Default]), UsedName(finalize,[Default]), UsedName(way_status,[Default]), UsedName(ic_miss_buff_data_error_bypass_inc,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(way_status_rep_new,[Default]), UsedName(ic_act_miss_f_delayed,[Default]), UsedName(asInstanceOf,[Default]), UsedName(miss_buff_hit_unq_f,[Default]), UsedName(way_status_wr_en,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(bus_data_beat_count,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(way_status_mb_scnd_in,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(bus_wren_last,[Default]), UsedName(setRef,[Default]), UsedName(bus_new_cmd_beat_count,[Default]), UsedName(rvdffe,[Default]), UsedName(ifu_bp_hit_taken_q_f,[Default]), UsedName(ifu_byp_data_err_new,[Default]), UsedName(bus_ic_wr_en,[Default]), UsedName(sel_mb_status_addr,[Default]), UsedName(ic_miss_buff_data_error_in,[Default]), UsedName(err_stop_state_en,[Default]), UsedName(ifc_region_acc_fault_memory_f,[Default]), UsedName(iccm_rw_addr_f,[Default]), UsedName(byp_fetch_index_inc,[Default]), UsedName(iccm_ecc_corr_index_ff,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(ifc_region_acc_fault_f,[Default]), UsedName(byp_fetch_index_inc_0,[Default]), UsedName(ifu_bus_arvalid_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(byp_fetch_index_1,[Default]), UsedName(iccm_dma_rdata_temp,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(reset_all_tags,[Default]), UsedName(bus_cmd_req_in,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dma_sb_err_state_ff,[Default]), UsedName(ecc_cor_C,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(tag_valid_clk,[Default]), UsedName(stream_C,[Default]), UsedName(bypass_index,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(ifu_ic_rw_int_addr_ff,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(iccm_corrected_data,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(bypass_data_ready_in,[Default]), UsedName(_parent,[Default]), UsedName(ic_miss_buff_parity,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(miss_pending,[Default]), UsedName(ecc_decoded,[Default]), UsedName(bus_cmd_sent,[Default]), UsedName(ifu_bus_rsp_valid,[Default]), UsedName(fetch_req_iccm_f,[Default]), UsedName(iccm_ecc_write_status,[Default]), UsedName(gated_latch,[Default]), UsedName(test_way_status_clken,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(ifu_bus_arready,[Default]), UsedName(wren_reset_miss,[Default]), UsedName(bus_hold_data_beat_cnt,[Default]), UsedName(sel_iccm_data,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(iccm_double_ecc_error,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(iccm_ecc_corr_data_ff,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(second_half_available,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(way_status_hit_new,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(ifu_tag_wren_w_debug,[Default]), UsedName(iccm_corrected_ecc,[Default]), UsedName(crit_wrd_rdy_C,[Default]), UsedName(ic_tag_valid_out,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(final_data_sel2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ifu_bus_cmd_valid,[Default]), UsedName(iccm_ecc_corr_index_in,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(test_way_status_out,[Default]), UsedName(io,[Default]), UsedName(ic_debug_ict_array_sel_in,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(perr_sel_invalidate,[Default]), UsedName(ifc_dma_access_ok_prev,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(miss_state_en,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(ic_wr_ecc,[Default]), UsedName(err_stop_idle_C,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(final_data_sel1,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(busclk_force,[Default]), UsedName(err_stop_fetch_C,[Default]), UsedName(iccm_correct_ecc,[Default]), UsedName(ifu_bus_rsp_opc,[Default]), UsedName(ifu_bus_rvalid_ff,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(ic_premux_data_temp,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ic_req_addr_bits_hi_3,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ic_miss_under_miss_f,[Default]), UsedName(ifc_region_acc_fault_memory_bf,[Default]), UsedName(ic_sel_premux_data_temp,[Default]), UsedName(fetch_bf_f_c1_clken,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(last_data_recieved_ff,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(ic_fetch_val_int_f,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(perr_err_inv_way,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ic_miss_buff_data_valid_bypass_index,[Default]), UsedName(way_status_mb_in,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(iccm_dma_rvalid_in,[Default]), UsedName(perr_sb_write_status,[Default]), UsedName(bus_ifu_wr_data_error_ff,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(crit_byp_hit_f,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(reset_ic_ff,[Default]), UsedName(sel_byp_data,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(ifu_bus_arready_unq,[Default]), UsedName(stream_miss_f,[Default]), UsedName(tagv_mb_scnd_in,[Default]), UsedName(ic_crit_wd_rdy_new_ff,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ifu_fetch_addr_int_f,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(ifu_bus_rvalid,[Default]), UsedName(scnd_miss_req_in,[Default]), UsedName(bus_wren,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ifu_ic_rw_int_addr_w_debug,[Default]), UsedName(iccm_error_start,[Default]), UsedName(dma_mem_ecc,[Default]), UsedName(bus_cmd_beat_en,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ifu_ic_debug_rd_data_in,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(scnd_miss_C,[Default]), UsedName(way_status_out,[Default]), UsedName(iccm_dma_rtag_temp,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(ic_miss_buff_data_valid_in,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(byp_fetch_index_0,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(reset_ic_in,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(perr_ic_index_ff,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ic_miss_buff_data_valid_inc_bypass_index,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(ifu_ic_rw_int_addr,[Default]), UsedName(bus_ifu_wr_en_ff_wo_err,[Default]), UsedName(idle_C,[Default]), UsedName(other_tag,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(ic_debug_way_ff,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(ifu_ic_req_addr_f,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ic_wr_16bytes_data,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(dma_sb_err_C,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(write_fill_data,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(ic_miss_buff_data_error,[Default]), UsedName(isClosed,[Default]), UsedName(tagv_mb_in,[Default]), UsedName(ifu_wr_data_comb_err_ff,[Default]), UsedName(bus_reset_cmd_beat_cnt_0,[Default]), UsedName(ifc_fetch_req_f,[Default]), UsedName(flush_final_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(way_status_clken,[Default]), UsedName(ifu_bus_rid_ff,[Default]), UsedName(perr_state_en,[Default]), UsedName(ic_wr_addr_bits_hi_3,[Default]), UsedName(debug_data_clk,[Default]), UsedName(two_byte_instr,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(miss_nxtstate,[Default]), UsedName(iccm_single_ecc_error,[Default]), UsedName($asInstanceOf,[Default]), UsedName(ifu_tag_wren,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(imb_scnd_ff,[Default]), UsedName(dma_sb_err_state,[Default]), UsedName(err_stop_fetch,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(uncacheable_miss_scnd_ff,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(uncacheable_miss_scnd_in,[Default]), UsedName(busclk,[Default]), UsedName(err_stop_state,[Default]), UsedName(way_status_wr_en_ff,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(ifu_bus_arready_unq_ff,[Default]), UsedName(addId,[Default]), UsedName(imb_ff,[Default]), UsedName(toTarget,[Default]), UsedName(bus_ifu_wr_en_ff_q,[Default]), UsedName(stream_hit_f,[Default]), UsedName(sel_mb_addr,[Default]), UsedName(ic_crit_wd_rdy,[Default]), UsedName(bypass_valid_value_check,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(ifu_bus_rsp_tag,[Default]), UsedName(miss_addr,[Default]))) invalidates 2 classes due to The ifu.ifu_mem_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.ifu_mem_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_buffer...
-[debug] Initial set of included nodes: lsu.lsu_bus_buffer
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_buffer)
-[debug] The following member ref dependencies of lsu.lsu_bus_buffer are invalidated:
-[debug] 	lsu.lsu_bus_intf
-[debug] Change NamesChange(lsu.lsu_bus_buffer,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(buf_state_en,[Default]), UsedName(buf_addr_in,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(buf_dual,[Default]), UsedName(obuf_rdrsp_tag,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(buf_dual_in,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(ld_addr_hitvec_hi,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(CmdPtr0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(obuf_data_done,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(ibuf_valid,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(buf_ldfwdtag_in,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(ibuf_timer,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ld_byte_hit_buf_lo,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(ibuf_byteen_in,[Default]), UsedName(obuf_data_done_in,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(lsu_nonblock_load_data_hi,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(buf_write_in,[Default]), UsedName(lsu_free_c2_clk,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(ld_addr_hitvec_lo,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(buf_dualhi,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(lsu_bus_buffer_empty_any,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(lsu_nonblock_load_valid_r,[Default]), UsedName(obuf_rdrsp_pend_in,[Default]), UsedName(ldst_byteen_ext_m,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(buf_sideeffect,[Default]), UsedName(rvecc_encode,[Default]), UsedName(buf_ldfwd_in,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(bus_addr_match_pending,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(buf_data,[Default]), UsedName(WrPtr0_m,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_bus_buf_c1_clk,[Default]), UsedName(buf_nomerge,[Default]), UsedName(buf_samedw,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(buf_wr_en,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(lsu_busm_clk,[Default]), UsedName(bus_rsp_read,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_bus_clk_en_q,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(obuf_rst,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(end_addr_r,[Default]), UsedName(obuf_addr_in,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(lsu_nonblock_data_unalgn,[Default]), UsedName(TIMER_LOG2,[Default]), UsedName(buf_ldfwdtag,[Default]), UsedName(ldst_dual_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(buf_cmd_state_bus_en,[Default]), UsedName(obuf_wr_wait,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(obuf_wr_timer,[Default]), UsedName(rvbradder,[Default]), UsedName(bus_rsp_write,[Default]), UsedName(buf_ageQ,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(ibuf_merge_en,[Default]), UsedName(cmd_C,[Default]), UsedName(ibuf_rst,[Default]), UsedName(ld_addr_ibuf_hit_hi,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(ibuf_sz_in,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(flush_r,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(obuf_byteen_in,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(obuf_nosend_in,[Default]), UsedName(indexing,[Default]), UsedName(getPorts,[Default]), UsedName(obuf_nosend,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(is_aligned_r,[Default]), UsedName(bus_wcmd_sent,[Default]), UsedName(ibuf_dual,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(obuf_addr,[Default]), UsedName(obuf_write_in,[Default]), UsedName(dctl_busbuff,[Default]), UsedName(ld_byte_hitvec_hi,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(obuf_merge_en,[Default]), UsedName(ibuf_merge_in,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(ibuf_nomerge,[Default]), UsedName(toString,[Default]), UsedName(obuf_sz,[Default]), UsedName(bus_cmd_ready,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(ibuf_addr_in,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(buf_age_younger,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ibuf_write,[Default]), UsedName(Tag_Word,[Default]), UsedName(ibuf_drain_vld,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(lsu_nonblock_load_data_lo,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(buf_data_in,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(buf_dualhi_in,[Default]), UsedName(bus_rsp_read_error,[Default]), UsedName(obuf_tag0,[Default]), UsedName(ld_fwddata_buf_hi,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(ld_addr_ibuf_hit_lo,[Default]), UsedName(ibuf_sz,[Default]), UsedName(store_data_hi_r,[Default]), UsedName(lsu_axi,[Default]), UsedName(obuf_wr_timer_in,[Default]), UsedName(buf_ldfwd,[Default]), UsedName(buf_rspage_in,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(obuf_rdrsp_tag_in,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ld_fwddata_buf_hi_initial,[Default]), UsedName(forceName,[Default]), UsedName(TIMER_MAX,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(lsu_busreq_r,[Default]), UsedName(obuf_valid,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(TIMER,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(lsu_bus_buffer_full_any,[Default]), UsedName(obuf_data,[Default]), UsedName(obuf_tag0_in,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(fwd_data,[Default]), UsedName(ibuf_data,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(obuf_data_in,[Default]), UsedName(ibuf_dualtag,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ld_byte_hitvecfn_hi,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(done_partial_C,[Default]), UsedName(name,[Default]), UsedName(ldst_byteen_hi_r,[Default]), UsedName(buf_byteen,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(lsu_bus_buffer,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(CmdPtr0Dec,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(bus_wdata_sent,[Default]), UsedName(nameIds,[Default]), UsedName(ld_byte_hitvec_lo,[Default]), UsedName(ibuf_sideeffect,[Default]), UsedName(buf_numvld_pend_any,[Default]), UsedName(ibuf_timer_in,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ibuf_tag,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(ld_byte_hit_buf_hi,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_commit_r,[Default]), UsedName(ibuf_byp,[Default]), UsedName(ldst_byteen_r,[Default]), UsedName(no_word_merge_r,[Default]), UsedName(ibuf_byteen,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(lsu_nonblock_unsign,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(ibuf_unsign,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(obuf_tag1,[Default]), UsedName(WrPtr1_m,[Default]), UsedName(lsu_nonblock_addr_offset,[Default]), UsedName(store_data_lo_r,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(bus_rsp_rdata,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(ldst_byteen_lo_m,[Default]), UsedName(lsu_bus_cntr_overflow,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(buf_rspageQ,[Default]), UsedName(rvclkhdr,[Default]), UsedName(ibuf_data_out,[Default]), UsedName(ld_full_hit_m,[Default]), UsedName(ibuf_data_in,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(buf_resp_state_bus_en,[Default]), UsedName(buf_error_en,[Default]), UsedName(found_cmdptr0,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ibuf_tag_in,[Default]), UsedName(ibuf_dualtag_in,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(ibuf_force_drain,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(bus_sideeffect_pend,[Default]), UsedName(bus_rsp_write_tag,[Default]), UsedName(CmdPtr1Dec,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(lsu_bus_buffer_pend_any,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(store_data_r,[Default]), UsedName(buf_addr,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(buf_byteen_in,[Default]), UsedName(buf_dualtag,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(ibuf_drainvec_vld,[Default]), UsedName(ibuf_wr_en,[Default]), UsedName(buf_rspage,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(flush_m_up,[Default]), UsedName(obuf_wr_enQ,[Default]), UsedName(lsu_nonblock_dual,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(obuf_sideeffect,[Default]), UsedName(obuf_data1_in,[Default]), UsedName(buf_age_in,[Default]), UsedName(buf_state_bus_en,[Default]), UsedName(bus_cmd_sent,[Default]), UsedName(gated_latch,[Default]), UsedName(any_done_wait_state,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(bus_rsp_write_error,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(ld_byte_ibuf_hit_hi,[Default]), UsedName(obuf_merge_in,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(obuf_aligned_in,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(obuf_data0_in,[Default]), UsedName(buf_samedw_in,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(buf_age,[Default]), UsedName(buf_nxtstate,[Default]), UsedName(resp_C,[Default]), UsedName(lsu_imprecise_error_store_tag,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ld_byte_hitvecfn_lo,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(dec_tlu_force_halt,[Default]), UsedName(obuf_sz_in,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(buf_dualtag_in,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(CmdPtr1,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(buf_sz_in,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(obuf_force_wr_en,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(obuf_byteen0_in,[Default]), UsedName(lsu_busreq_m,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(obuf_write,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(ibuf_byteen_out,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ldst_dual_r,[Default]), UsedName(lsu_bus_obuf_c1_clk,[Default]), UsedName(found_cmdptr1,[Default]), UsedName(ibuf_buf_byp,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(buf_write,[Default]), UsedName(wait_C,[Default]), UsedName(buf_numvld_any,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(RspPtr,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(ld_byte_ibuf_hit_lo,[Default]), UsedName(no_dword_merge_r,[Default]), UsedName(notify,[Default]), UsedName(lsu_bus_ibuf_c1_clk,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(ld_fwddata_buf_lo,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(buf_error,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(is_sideeffects_r,[Default]), UsedName(ldst_byteen_lo_r,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(buf_unsign_in,[Default]), UsedName(obuf_byteen1_in,[Default]), UsedName(obuf_rdrsp_pend,[Default]), UsedName(obuf_tag1_in,[Default]), UsedName(obuf_sideeffect_in,[Default]), UsedName(obuf_byteen,[Default]), UsedName(buf_sz,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(obuf_merge,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(buf_sideeffect_in,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(tlu_busbuff,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(buf_rsp_pickage,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(bus_rsp_read_tag,[Default]), UsedName(idle_C,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(buf_nomerge_in,[Default]), UsedName(done_wait_C,[Default]), UsedName(obuf_cmd_done,[Default]), UsedName(ldst_dual_m,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(DEPTH,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(buf_rspage_set,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(buf_data_en,[Default]), UsedName(RspPtrDec,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(WrPtr0_r,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ldst_samedw_r,[Default]), UsedName(lsu_nonblock_sz,[Default]), UsedName(DEPTH_LOG2,[Default]), UsedName(buf_numvld_wrcmd_any,[Default]), UsedName(obuf_cmd_done_in,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(ld_fwddata_buf_lo_initial,[Default]), UsedName(Enc8x3,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(buf_unsign,[Default]), UsedName(namingContext$macro$7,[Default]), UsedName(buf_ldfwd_en,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(obuf_wr_en,[Default]), UsedName(done_C,[Default]), UsedName(lsu_nonblock_load_data_ready,[Default]), UsedName(lsu_bus_idle_any,[Default]), UsedName(bus_coalescing_disable,[Default]), UsedName(ibuf_addr,[Default]), UsedName(lsu;lsu_bus_buffer;init;,[Default]), UsedName(WrPtr1_r,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(ldst_byteen_hi_m,[Default]), UsedName(buf_numvld_cmd_any,[Default]), UsedName(addId,[Default]), UsedName(buf_state,[Default]), UsedName(toTarget,[Default]), UsedName(buf_rst,[Default]), UsedName(end_addr_m,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(ibuf_samedw,[Default]))) invalidates 2 classes due to The lsu.lsu_bus_buffer has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_bus_buffer)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_bus_intf)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_dma...
-[debug] Initial set of included nodes: include.lsu_dma
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_dma)
-[debug] The following member ref dependencies of include.lsu_dma are invalidated:
-[debug] 	dma_ctrl
-[debug] 	lsu.lsu
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_dma,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(dma_lsc_ctl,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(dma_mem_tag,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dccm_ready,[Default]), UsedName(include;lsu_dma;init;,[Default]), UsedName(!=,[Default]), UsedName(dma_dccm_ctl,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(lsu_dma,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.lsu_dma has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_dma)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu, dma_ctrl, quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.exu_ifu...
-[debug] Initial set of included nodes: include.exu_ifu
-[debug] Invalidated by transitive inheritance dependency: Set(include.exu_ifu)
-[debug] The following member ref dependencies of include.exu_ifu are invalidated:
-[debug] 	ifu.ifu
-[debug] 	quasar
-[debug] Change NamesChange(include.exu_ifu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(include;exu_ifu;init;,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(exu_bp,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(exu_ifu,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 3 classes due to The include.exu_ifu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.exu_ifu)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu, quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_lsc_ctl...
-[debug] Initial set of included nodes: lsu.lsu_lsc_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_lsc_ctl)
-[debug] The following member ref dependencies of lsu.lsu_lsc_ctl are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_lsc_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(lsu_ld_datafn_corr_r,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(offset_d,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(misaligned_fault_r,[Default]), UsedName(lsu_lsc_ctl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(store_data_pre_m,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(addr_offset_d,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(lsu_ld_datafn_m,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(access_fault_r,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(end_addr_offset_d,[Default]), UsedName(full_end_addr_d,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(end_addr_d,[Default]), UsedName(dma_lsc_ctl,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(rs1_d,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(fir_dccm_access_error_m,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_pic_d,[Default]), UsedName(addr_in_dccm_m,[Default]), UsedName(addr_in_dccm_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_pkt_d,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(lsu_result_m,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(access_fault_d,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(store_data_d,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(lsu_fir_error,[Default]), UsedName(picm_mask_data_m,[Default]), UsedName(is_sideeffects_m,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(lsu_c1_r_clk,[Default]), UsedName(end_addr_r,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(addr_external_m,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(lsu_single_ecc_error_m,[Default]), UsedName(lsu_double_ecc_error_r,[Default]), UsedName(fir_nondccm_access_error_m,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(lsu_single_ecc_error_r,[Default]), UsedName(lsu_offset_d,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(lsu_addr_d,[Default]), UsedName(flush_r,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(lsu_fir_error_m,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(lsu_ld_data_corr_r,[Default]), UsedName(lsu_error_pkt_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(fir_nondccm_access_error_d,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(misaligned_fault_d,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(lsu_error_pkt_m,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(fir_dccm_access_error_r,[Default]), UsedName(addr_external_r,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(addr_external_d,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(lsu_rs1_d,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(fir_dccm_access_error_d,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(lsu_fir_addr,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_commit_r,[Default]), UsedName(lsu_result_corr_r,[Default]), UsedName(lsu_exc_m,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(bus_read_data_r,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(lsu_p,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(lsu_c2_m_clk,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(dec_lsu_offset_d,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(lsu_ld_datafn_r,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(exc_mscause_r,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(addr_in_pic_m,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(lsu_single_ecc_error_incr,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(bus_read_data_m,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(flush_m_up,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(dma_mem_wdata_shifted,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(lsu_c1_m_clk,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(full_addr_d,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(lsu_store_c1_m_clk,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(addr_in_dccm_r,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(access_fault_m,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(addrcheck,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(lsu_c2_r_clk,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(rs1_d_raw,[Default]), UsedName(lsu_exu,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(lsu_double_ecc_error_m,[Default]), UsedName(lsu_pkt_m_in,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(store_data_m_in,[Default]), UsedName(exc_mscause_m,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(dma_pkt_d,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(lsu_ld_data_r,[Default]), UsedName(fir_nondccm_access_error_r,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(exc_mscause_d,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(addr_in_pic_r,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(lsu;lsu_lsc_ctl;init;,[Default]), UsedName(store_data_m,[Default]), UsedName(lsu_ld_data_m,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(end_addr_m,[Default]), UsedName(lsu_pkt_r_in,[Default]), UsedName(misaligned_fault_m,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]))) invalidates 2 classes due to The lsu.lsu_lsc_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_lsc_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_trigger...
-[debug] Initial set of included nodes: lsu.lsu_trigger
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_trigger)
-[debug] The following member ref dependencies of lsu.lsu_trigger are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_trigger,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(lsu_trigger,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(lsu_trigger_match_m,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(lsu;lsu_trigger;init;,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(lsu_match_data,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(trigger_pkt_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(store_data_m,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(store_data_trigger_m,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_trigger has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_trigger)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.exu_div_ctl...
-[debug] Initial set of included nodes: exu.exu_div_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_div_ctl)
-[debug] The following member ref dependencies of exu.exu_div_ctl are invalidated:
-[debug] 	exu.exu
-[debug] Change NamesChange(exu.exu_div_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(dividend_neg_ff,[Default]), UsedName(short_dividend,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(exu_div_ctl,[Default]), UsedName(valid_ff_x,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(exu_div_cgc,[Default]), UsedName(add,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(dividend_eff,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(smallnum_case_ff,[Default]), UsedName(b_cls,[Default]), UsedName(a_shift,[Default]), UsedName(valid_x,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(shortq_enable_ff,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(smallnum_ff,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(dec_div,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_div_wren,[Default]), UsedName(run_in,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(finish_ff,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(sign_ff,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(rem_correct,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(divisor_neg_ff,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(q_in,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(rem_ff,[Default]), UsedName(m_already_comp,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(a_ff_comp,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(finish,[Default]), UsedName(override_reset,[Default]), UsedName(smallnum,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(aff_enable,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(shortq_shift_ff,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(m_ff,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(pat,[Default]), UsedName(setRef,[Default]), UsedName(qff_enable,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(exu_div_result,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(divisor,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(shortq_enable,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(a_eff,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(q_ff_eff,[Default]), UsedName(rvecc_decode,[Default]), UsedName(q_ff,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(shortq_shift,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(a_ff,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(a_ff_eff,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dividend,[Default]), UsedName(a_eff_shift,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(m_eff,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(exu;exu_div_ctl;init;,[Default]), UsedName(q_ff_comp,[Default]), UsedName(count,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(smallnum_case,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(namingContext$macro$2,[Default]), UsedName(pathName,[Default]), UsedName(a_cls,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(a_in,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(dividend_comp,[Default]), UsedName(shortq_raw,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(shortq_shift_xx,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(count_in,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(div_clken,[Default]), UsedName(run_state,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(sign_eff,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The exu.exu_div_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(exu.exu_div_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_stbuf...
-[debug] Initial set of included nodes: lsu.lsu_stbuf
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_stbuf)
-[debug] The following member ref dependencies of lsu.lsu_stbuf are invalidated:
-[debug] 	lsu.lsu
-[debug] Change NamesChange(lsu.lsu_stbuf,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(stbuf_fwdbyteenvec_lo,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(stbuf_fwdpipe2_lo,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(store_matchvec_hi_r,[Default]), UsedName(stbuf_specvld_any,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(stbuf_match_lo,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(isdccmst_m,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ldst_byteen_ext_r,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(lsu_free_c2_clk,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(stbuf_reqvld_any,[Default]), UsedName(desiredName,[Default]), UsedName(stbuf_data_any,[Default]), UsedName(stbuf_specvld_r,[Default]), UsedName(repl,[Default]), UsedName(stbuf_fwddata_lo_pre_m,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(end_addr_d,[Default]), UsedName(rvecc_encode,[Default]), UsedName(lsu_stbuf_full_any,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_dccm_m,[Default]), UsedName(WrPtrPlus2,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ld_addr_rhit_lo_lo,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(ld_byte_rhit_lo,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(fwdpipe1_lo,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(stbuf_numvld_any,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(lsu_stbuf_empty_any,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(fwdpipe2_lo,[Default]), UsedName(WrPtr,[Default]), UsedName(RdPtrPlus1,[Default]), UsedName(lsu_c1_r_clk,[Default]), UsedName(end_addr_r,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(ld_addr_rhit_hi_lo,[Default]), UsedName(ldst_dual_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(namingContext$macro$3,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(NxtRdPtr,[Default]), UsedName(rvbradder,[Default]), UsedName(stbuf_fwddata_hi_pre_m,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(lsu_stbuf_c1_clk,[Default]), UsedName(WrPtrEn,[Default]), UsedName(circuitName,[Default]), UsedName(stbuf_fwdbyteen_lo_pre_m,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(ld_byte_rhit_hi,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(lsu_addr_d,[Default]), UsedName(stbuf_fwdpipe1_hi,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(datain3,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(lsu_addr_r,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ld_byte_rhit_lo_lo,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(sel_lo,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(stbuf_fwdpipe3_hi,[Default]), UsedName(Tag_Word,[Default]), UsedName(stbuf_addr_any,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(store_matchvec_lo_r,[Default]), UsedName(lsu_cmpen_m,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(ld_byte_rhit_hi_hi,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(stbuf_byteen,[Default]), UsedName(store_data_hi_r,[Default]), UsedName(NxtWrPtr,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(stbuf_fwdata_hi_pre_m,[Default]), UsedName(datain2,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(store_stbuf_reqvld_r,[Default]), UsedName(forceName,[Default]), UsedName(fwdpipe3_lo,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(RdPtr,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu;lsu_stbuf;init;,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(isdccmst_r,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ld_fwddata_rpipe_lo,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(ldst_byteen_hi_r,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(stbuf_fwdpipe2_hi,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(store_datafn_lo_r,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(stbuf_fwdbyteenvec_hi,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(stbuf_fwdpipe1_lo,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(stbuf_fwddata_lo_m,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(cmpaddr_lo_m,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(lsu_commit_r,[Default]), UsedName(stbuf_fwdbyteen_hi_pre_m,[Default]), UsedName(ldst_byteen_r,[Default]), UsedName(hashCode,[Default]), UsedName(stbuf_match_hi,[Default]), UsedName(instanceName,[Default]), UsedName(stbuf_vld,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(ld_byte_rhit_lo_hi,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(fwdpipe2_hi,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(store_data_lo_r,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(stbuf_fwdata_lo_pre_m,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(store_coalesce_hi_r,[Default]), UsedName(stbuf_reset,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(store_byteen_hi_r,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(lsu_pkt_r,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(store_datafn_hi_r,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(ld_addr_rhit_hi_hi,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(fwdpipe4_hi,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(stbuf_byteenin,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(lsu_addr_m,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(stbuf_dma_kill,[Default]), UsedName(stbuf_fwdbyteen_lo_m,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(fwdpipe1_hi,[Default]), UsedName(stbuf_addr,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(stbuf_fwdbyteen_hi_m,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(stbuf_addrin,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(stbuf_dma_kill_en,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(lsu_c1_m_clk,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(stbuf_fwdpipe3_lo,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(addr_in_dccm_r,[Default]), UsedName(cmpaddr_hi_m,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(datain4,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(stbuf_fwdpipe4_hi,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(store_byteen_lo_r,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(fwdpipe3_hi,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ldst_dual_r,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(cmpen_lo_m,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(stbuf_datain,[Default]), UsedName(stbuf_fwdpipe4_lo,[Default]), UsedName(stbuf_reqvld_flushed_any,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(WrPtrPlus1,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(lsu_stbuf_commit_any,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(datain1,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_lsu_valid_raw_d,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(cmpen_hi_m,[Default]), UsedName(store_coalesce_lo_r,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(ldst_byteen_lo_r,[Default]), UsedName(ldst_stbuf_reqvld_r,[Default]), UsedName(lsu_pkt_m,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ld_fwddata_rpipe_hi,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(ld_byte_hit_hi,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(RdPtrEn,[Default]), UsedName(ldst_dual_m,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(stbuf_wr_en,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(stbuf_data,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(fwdpipe4_lo,[Default]), UsedName(ld_byte_hit_lo,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ld_addr_rhit_lo_hi,[Default]), UsedName(lsu_stbuf,[Default]), UsedName(stbuf_fwddata_hi_m,[Default]), UsedName(ld_byte_rhit_hi_lo,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(store_byteen_ext_r,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(end_addr_m,[Default]), UsedName(stbuf_specvld_m,[Default]), UsedName(dual_stbuf_write_r,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_stbuf has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_stbuf)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_trace_pkt_t...
-[debug] Initial set of included nodes: include.el2_trace_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_trace_pkt_t)
-[debug] Change NamesChange(include.el2_trace_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(rv_i_valid_ip,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(rv_i_insn_ip,[Default]), UsedName(litArg,[Default]), UsedName(rv_i_exception_ip,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(el2_trace_pkt_t,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(rv_i_address_ip,[Default]), UsedName(flatten,[Default]), UsedName(rv_i_ecause_ip,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(rv_i_interrupt_ip,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(rv_i_tval_ip,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(include;el2_trace_pkt_t;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_trace_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_trace_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dccm_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.dccm_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.dccm_ext_in_pkt_t)
-[debug] Change NamesChange(include.dccm_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(include;dccm_ext_in_pkt_t;init;,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(dccm_ext_in_pkt_t,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.dccm_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dccm_ext_in_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.ib_gen...
-[debug] Initial set of included nodes: dec.ib_gen
-[debug] Invalidated by transitive inheritance dependency: Set(dec.ib_gen)
-[debug] Change NamesChange(dec.ib_gen,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(ib_gen,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.ib_gen has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(ib_gen,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.ib_gen)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_tlu...
-[debug] Initial set of included nodes: include.lsu_tlu
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_tlu)
-[debug] The following member ref dependencies of include.lsu_tlu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	lsu.lsu
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_tlu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(lsu_tlu,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(include;lsu_tlu;init;,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(lsu_pmu_load_external_m,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lsu_pmu_store_external_m,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 7 classes due to The include.lsu_tlu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_tlu)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_tlu_ctl_IO, lsu.lsu, dec.dec_tlu_ctl, quasar, dec.dec_IO)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_aln...
-[debug] Initial set of included nodes: include.dec_aln
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_aln)
-[debug] The following member ref dependencies of include.dec_aln are invalidated:
-[debug] 	dec.dec
-[debug] 	ifu.ifu
-[debug] 	ifu.ifu_aln_ctl
-[debug] Change NamesChange(include.dec_aln,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(aln_ib,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(include;dec_aln;init;,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(ifu_pmu_instr_aligned,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(dec_aln,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(aln_dec,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.dec_aln has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_aln)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_aln_ctl, ifu.ifu, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.decode_exu...
-[debug] Initial set of included nodes: include.decode_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.decode_exu)
-[debug] The following member ref dependencies of include.decode_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu
-[debug] Change NamesChange(include.decode_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_i0_rs2_bypass_en_d,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(i0_predict_fghr_d,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(include;decode_exu;init;,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(i0_predict_index_d,[Default]), UsedName(exu_csr_rs1_x,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(i0_predict_btag_d,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(dec_i0_select_pc_d,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(decode_exu,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(dec_i0_rs1_bypass_data_d,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(exu_i0_result_x,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_predict_p_d,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(dec_i0_immed_d,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(pred_correct_npc_x,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_i0_rs2_en_d,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(dec_i0_rs2_bypass_data_d,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dec_data_en,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(i0_ap,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(dec_ctl_en,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(dec_i0_rs1_en_d,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(mul_p,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(dec_extint_stall,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(dec_i0_rs1_bypass_en_d,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 4 classes due to The include.decode_exu has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.decode_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_decode_ctl, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_error_pkt_t...
-[debug] Initial set of included nodes: include.lsu_error_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_error_pkt_t)
-[debug] The following member ref dependencies of include.lsu_error_pkt_t are invalidated:
-[debug] 	dec.CSR_IO
-[debug] 	dec.csr_tlu
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_lsc_ctl
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_error_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(inst_type,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(mscause,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(exc_type,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(include;lsu_error_pkt_t;init;,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(single_ecc_error,[Default]), UsedName(bind,[Default]), UsedName(addr,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(lsu_error_pkt_t,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 10 classes due to The include.lsu_error_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_error_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_tlu_ctl_IO, lsu.lsu, dec.dec_tlu_ctl, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, dec.dec_IO, dec.CSR_IO)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.el2_exu...
-[debug] Initial set of included nodes: exu.el2_exu
-[debug] Invalidated by transitive inheritance dependency: Set(exu.el2_exu)
-[debug] Change NamesChange(exu.el2_exu,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(el2_exu,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(exu;el2_exu;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The exu.el2_exu has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(el2_exu,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(exu;el2_exu;init;,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(exu.el2_exu)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.axi4_to_ahb...
-[debug] Initial set of included nodes: lib.axi4_to_ahb
-[debug] Invalidated by transitive inheritance dependency: Set(lib.axi4_to_ahb)
-[debug] The following member ref dependencies of lib.axi4_to_ahb are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(lib.axi4_to_ahb,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(wrbuf_en,[Default]), UsedName(buf_state_en,[Default]), UsedName(buf_addr_in,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(buf_aligned_in,[Default]), UsedName(wrbuf_rst,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(wrbuf_data_vld,[Default]), UsedName(data_rd,[Default]), UsedName(buf_data_wr_en,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(wrbuf_addr,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(buf_cmd_byte_ptrQ,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(rd_bypass_idle,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(buf_write_in,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(lib;axi4_to_ahb;init;,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(stream_rd,[Default]), UsedName(master_valid,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(slave_valid_pre,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(buf_data,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(master_size,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(buf_wr_en,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(ahb_htrans_q,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(cmd_done_rst,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(master_addr,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(buf_cmd_nxtbyte_ptr,[Default]), UsedName(cmd_doneQ,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bus_clk,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(data_wr,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(slvbuf_write,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(get_nxtbyte_ptr,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(ahb_hwrite_q,[Default]), UsedName(bus_write_clk_en,[Default]), UsedName(getPorts,[Default]), UsedName(wrbuf_cmd_sent,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(wrbuf_size,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(bypass_en,[Default]), UsedName(cmd_rd,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(buf_tag_in,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(ahbm_addr_clken,[Default]), UsedName(last_bus_addr,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(buf_data_in,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(slvbuf_tag,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(buf_size,[Default]), UsedName(slvbuf_clken,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(ahb_hresp_q,[Default]), UsedName(slvbuf_wr_en,[Default]), UsedName(forceName,[Default]), UsedName(ahb_hrdata_q,[Default]), UsedName(master_byteen,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(slvbuf_error_in,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(get_write_addr,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(cmd_done,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(buf_byteen,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(buf_clken,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(wrbuf_byteen,[Default]), UsedName(master_opc,[Default]), UsedName(bus_write_clk,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(slave_rdata,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(last_addr_en,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(master_wdata,[Default]), UsedName(wrbuf_vld,[Default]), UsedName(slave_opc,[Default]), UsedName(idle,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(buf_aligned,[Default]), UsedName(cmd_wr,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(wrbuf_data,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(master_ready,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ahbm_clk,[Default]), UsedName(ahbm_data_clk,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(buf_addr,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(buf_byteen_in,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(ahbm_addr_clk,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(wrbuf_tag,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(buf_nxtstate,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(ahbm_data_clken,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(ahb_hready_q,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(trxn_done,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(wrbuf_data_en,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(master_tag,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(buf_tag,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(buf_write,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(slave_valid,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(buf_cmd_byte_ptr_en,[Default]), UsedName(slave_ready,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(buf_clk,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(slvbuf_error_en,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(buf_cmd_byte_ptr,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(slvbuf_error,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(get_write_size,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(buf_size_in,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(wr_cmd_vld,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(done,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(slave_tag,[Default]), UsedName(stream_err_rd,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(buf_state,[Default]), UsedName(toTarget,[Default]), UsedName(buf_rst,[Default]), UsedName(notifyAll,[Default]), UsedName(found,[Default]), UsedName(equals,[Default]), UsedName(axi4_to_ahb,[Default]))) invalidates 2 classes due to The lib.axi4_to_ahb has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lib.axi4_to_ahb)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.div_pkt_t...
-[debug] Initial set of included nodes: include.div_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.div_pkt_t)
-[debug] The following member ref dependencies of include.div_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] 	exu.exu_div_ctl
-[debug] Change NamesChange(include.div_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(rem,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(div_pkt_t,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(include;div_pkt_t;init;,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 3 classes due to The include.div_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.div_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu_div_ctl, dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dbg.state_t...
-[debug] Initial set of included nodes: dbg.state_t
-[debug] Invalidated by transitive inheritance dependency: Set(dbg.state_t)
-[debug] Change NamesChange(dbg.state_t,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(state_t,[Default]), UsedName(synchronized,[Default]), UsedName(halted,[Default]), UsedName(toString,[Default]), UsedName(cmd_wait,[Default]), UsedName(cmd_done,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(idle,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(halting,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(resuming,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName(cmd_start,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dbg.state_t has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(state_t,[Default]), UsedName(synchronized,[Default]), UsedName(halted,[Default]), UsedName(toString,[Default]), UsedName(cmd_wait,[Default]), UsedName(cmd_done,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(idle,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(halting,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(resuming,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName(cmd_start,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dbg.state_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.ifu_aln_ctl...
-[debug] Initial set of included nodes: ifu.ifu_aln_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_aln_ctl)
-[debug] The following member ref dependencies of ifu.ifu_aln_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] Change NamesChange(ifu.ifu_aln_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(qwen,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(misc2,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(q0off_in,[Default]), UsedName(sf1val,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(f0_shift_2B,[Default]), UsedName(f2pc,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(f2_wr_en,[Default]), UsedName(f0val,[Default]), UsedName(f0way,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(f1ictype,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(rdptr,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(f0prett,[Default]), UsedName(ifu_fetch_val,[Default]), UsedName(secondbrtag_hash,[Default]), UsedName(secondpc,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(f1ret,[Default]), UsedName(f1val,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ifu_bp_btb_target_f,[Default]), UsedName(firstpc,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(aligndbecc,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(misc1eff,[Default]), UsedName(ifu_bp_hist1_f,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(wrptr,[Default]), UsedName(f1icaf,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(f1_shift_wr_en,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(ifu_fetch_data_f,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(f0pc_in,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(shift_2B,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(first4B,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(f0hist0,[Default]), UsedName(ifu_bp_valid_f,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(q0ptr,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(alignway,[Default]), UsedName(alignret,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(aligndata,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(fetch_to_f0,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(brdata1eff,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(f1pc4,[Default]), UsedName(q0off,[Default]), UsedName(ifvalid,[Default]), UsedName(f1brend,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(fetch_to_f1,[Default]), UsedName(i0_shift,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(shift_f1_f0,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(f2val,[Default]), UsedName(brdata0eff,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(q0final,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(f1dbecc,[Default]), UsedName(misceff,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(f1val_in,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(error_stall_in,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(consume_fb0,[Default]), UsedName(sf1_valid,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(consume_fb1,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(f1pc_in,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(ifu_fb_consume2,[Default]), UsedName(ifu_aln_ctl,[Default]), UsedName(f0_shift_wr_en,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(f0icaf,[Default]), UsedName(ic_access_fault_f,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ifu_bp_hist0_f,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(f0pc,[Default]), UsedName(misc_data_in,[Default]), UsedName(f0val_in,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(ifu_bp_poffset_f,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ifu_bp_fghr_f,[Default]), UsedName(q2,[Default]), UsedName(f0poffset,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ifu_bp_pc4_f,[Default]), UsedName(f1fghr,[Default]), UsedName(q0,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(q1sel,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(f2_valid,[Default]), UsedName(icaf_eff,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(i0_brp_pc4,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(rdptr_in,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(alignhist0,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(brdata0final,[Default]), UsedName(rvdffe,[Default]), UsedName(f1hist1,[Default]), UsedName(f0hist1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(alignicaf,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(f0dbecc,[Default]), UsedName(shift_f2_f1,[Default]), UsedName(rvclkhdr,[Default]), UsedName(f2val_in,[Default]), UsedName(misc0eff,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(wrptr_in,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(ifu_bp_ret_f,[Default]), UsedName(ifu_async_error_start,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(sf1pc,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(brdata2,[Default]), UsedName(f0ictype,[Default]), UsedName(MHI,[Default]), UsedName(firstbrtag_hash,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(error_stall,[Default]), UsedName(f0ret,[Default]), UsedName(f0brend,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(alignbrend,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(q1final,[Default]), UsedName(misc1,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(f1way,[Default]), UsedName(misc0,[Default]), UsedName(qren,[Default]), UsedName(fetch_to_f2,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(q2off,[Default]), UsedName(brdata_in,[Default]), UsedName(ifu_fb_consume1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(alignhist1,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(brdataeff,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(q1ptr,[Default]), UsedName(f0pc4,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(f1prett,[Default]), UsedName(secondpc_hash,[Default]), UsedName(PIC_BITS,[Default]), UsedName(f0pc_plus1,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(ifu;ifu_aln_ctl;init;,[Default]), UsedName(f1poffset,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(brdata1,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(f1hist0,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(ifu_bp_way_f,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(first2B,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(qeff,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(ifu_fetch_pc,[Default]), UsedName(i0_ends_f1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(q1eff,[Default]), UsedName(f1pc_plus1,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(iccm_rd_ecc_double_err,[Default]), UsedName(q2off_in,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(sf0val,[Default]), UsedName(q1off_in,[Default]), UsedName(brdata0,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(decompressed,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(ic_access_fault_type_f,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(alignfromf1,[Default]), UsedName(shift_4B,[Default]), UsedName(firstpc_hash,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(alignpc4,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(f0fghr,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(f1_shift_2B,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(brdata1final,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(ifirst,[Default]), UsedName(q1,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(q0sel,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(q1off,[Default]), UsedName(active_clk,[Default]), UsedName(dec_aln,[Default]), UsedName(f1pc,[Default]), UsedName(shift_f2_f0,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(BRDATA_SIZE,[Default]), UsedName(wait,[Default]), UsedName(alignval,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(q0eff,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(sf0_valid,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(MSIZE,[Default]))) invalidates 2 classes due to The ifu.ifu_aln_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.ifu_aln_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lsu.lsu_addrcheck...
-[debug] Initial set of included nodes: lsu.lsu_addrcheck
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_addrcheck)
-[debug] The following member ref dependencies of lsu.lsu_addrcheck are invalidated:
-[debug] 	lsu.lsu_lsc_ctl
-[debug] Change NamesChange(lsu.lsu_addrcheck,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(end_addr_in_dccm_d,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(end_addr_d,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(rs1_d,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(addr_in_pic_d,[Default]), UsedName(addr_in_dccm_d,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(misaligned_fault_mscause_d,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(lsu_pkt_d,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(access_fault_d,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(is_sideeffects_m,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(end_addr_in_dccm_region_d,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(start_addr_in_dccm_region_d,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(unmapped_access_fault_d,[Default]), UsedName(is_sideeffects_d,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(picm_access_fault_d,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(fir_nondccm_access_error_d,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(misaligned_fault_d,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(addr_in_iccm,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(start_addr_in_pic_d,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(start_addr_in_pic_region_d,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(start_addr_dccm_or_pic,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(addr_external_d,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(rs1_region_d,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(fir_dccm_access_error_d,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(is_aligned_d,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(start_addr_in_dccm_d,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(lsu_addrcheck,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(lsu_c2_m_clk,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(dec_tlu_mrac_ff,[Default]), UsedName(rvclkhdr,[Default]), UsedName(access_fault_mscause_d,[Default]), UsedName(lsu;lsu_addrcheck;init;,[Default]), UsedName(csr_idx,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(namingContext$macro$6,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(end_addr_in_pic_d,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(start_addr_d,[Default]), UsedName(mpu_access_fault_d,[Default]), UsedName(regpred_access_fault_d,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(end_addr_in_pic_region_d,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(sideeffect_misaligned_fault_d,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(non_dccm_access_ok,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(regcross_misaligned_fault_d,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(base_reg_dccm_or_pic,[Default]), UsedName(_id,[Default]), UsedName(exc_mscause_d,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The lsu.lsu_addrcheck has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_addrcheck)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_lsc_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_pic...
-[debug] Initial set of included nodes: include.dec_pic
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_pic)
-[debug] The following member ref dependencies of include.dec_pic are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_tlu_ctl
-[debug] 	dec.dec_tlu_ctl_IO
-[debug] 	pic_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_pic,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(dec_pic,[Default]), UsedName(dec_tlu_meicurpl,[Default]), UsedName(ignoreSeq,[Default]), UsedName(pic_claimid,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(include;dec_pic;init;,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(mhwakeup,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(mexintpend,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(pic_pl,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dec_tlu_meipt,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 7 classes due to The include.dec_pic has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_pic)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, dec.dec_tlu_ctl_IO, dec.dec_tlu_ctl, quasar, pic_ctrl, dec.dec_IO)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.ccm_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.ccm_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.ccm_ext_in_pkt_t)
-[debug] Change NamesChange(include.ccm_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName(ccm_ext_in_pkt_t,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(include;ccm_ext_in_pkt_t;init;,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.ccm_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ccm_ext_in_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_dec_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_dec_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_dec_ctl)
-[debug] Change NamesChange(dec.el2_dec_dec_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(el2_dec_dec_ctl,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(pattern,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(ins,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(dec;el2_dec_dec_ctl;init;,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_dec_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_dec_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.el2_exu_alu_ctl...
-[debug] Initial set of included nodes: exu.el2_exu_alu_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(exu.el2_exu_alu_ctl)
-[debug] Change NamesChange(exu.el2_exu_alu_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(result_ff,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ov,[Default]), UsedName(actual_taken,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(enable,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(bm,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(any_jal,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(flush_upper_out,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(cout,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(newhist,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(predict_p_out,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(shift_amount,[Default]), UsedName(sel_shift,[Default]), UsedName(sout,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(sel_adder,[Default]), UsedName(pc_in,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(shift_long,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(sel_pc,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(slt_one,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(csr_ren_in,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(flush_upper_x,[Default]), UsedName(exu;el2_exu_alu_ctl;init;,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(flush_path_out,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(shift_extend,[Default]), UsedName(brimm_in,[Default]), UsedName(pp_in,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(flush_lower_r,[Default]), UsedName(b_in,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(pred_correct_out,[Default]), UsedName(gated_latch,[Default]), UsedName(pc_ff,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(el2_exu_alu_ctl,[Default]), UsedName(lt,[Default]), UsedName(ge,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(pcout,[Default]), UsedName(csr_write_data,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(valid_in,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(shift_mask,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(lout,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(cond_mispredict,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(target_mispredict,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(ap,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(a_in,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(flush_final_out,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(aout,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(neg,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(result,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The exu.el2_exu_alu_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(exu.el2_exu_alu_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_gpr_ctl...
-[debug] Initial set of included nodes: dec.dec_gpr_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_gpr_ctl)
-[debug] The following member ref dependencies of dec.dec_gpr_ctl are invalidated:
-[debug] 	dec.dec
-[debug] Change NamesChange(dec.dec_gpr_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(dec_gpr_ctl,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(w0v,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(w2v,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(gpr_wr_en,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(w1v,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(dec;dec_gpr_ctl;init;,[Default]), UsedName(gpr_out,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(gpr_in,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dec.dec_gpr_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_gpr_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_dec_pkt_t...
-[debug] Initial set of included nodes: include.el2_dec_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_dec_pkt_t)
-[debug] Change NamesChange(include.el2_dec_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(imm12,[Default]), UsedName(pc,[Default]), UsedName(ignoreSeq,[Default]), UsedName(presync,[Default]), UsedName(word,[Default]), UsedName(add,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(rs1_sign,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(imm20,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(el2_dec_pkt_t,[Default]), UsedName(toNamed,[Default]), UsedName(mret,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(by,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(pm_alu,[Default]), UsedName(isSynthesizable,[Default]), UsedName(ebreak,[Default]), UsedName(alu,[Default]), UsedName(bind,[Default]), UsedName(rs1,[Default]), UsedName(csr_set,[Default]), UsedName(rem,[Default]), UsedName(rs2_sign,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(slt,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(beq,[Default]), UsedName(lor,[Default]), UsedName(ref,[Default]), UsedName(half,[Default]), UsedName(do_asUInt,[Default]), UsedName(sll,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(shimm5,[Default]), UsedName(rs2,[Default]), UsedName(mul,[Default]), UsedName(srl,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(include;el2_dec_pkt_t;init;,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(low,[Default]), UsedName(ecall,[Default]), UsedName(csr_clr,[Default]), UsedName(sra,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(jal,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(land,[Default]), UsedName(topBindingOpt,[Default]), UsedName(csr_read,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(fence,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(bge,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(div,[Default]), UsedName(blt,[Default]), UsedName(_makeLit,[Default]), UsedName(bne,[Default]), UsedName(notify,[Default]), UsedName(postsync,[Default]), UsedName(csr_write,[Default]), UsedName(csr_imm,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(fence_i,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(lsu,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(condbr,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(lxor,[Default]), UsedName(toTarget,[Default]), UsedName(sub,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_dec_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_dec_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_timer_ctl...
-[debug] Initial set of included nodes: dec.el2_dec_timer_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_timer_ctl)
-[debug] Change NamesChange(dec.el2_dec_timer_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(MITB1,[Default]), UsedName(mitctl1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(mitcnt0_inc_ok,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(dec;el2_dec_timer_ctl;init;,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(MITB0,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(mitctl0,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(mitcnt0,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(mitctl0_ns,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(mit0_match_ns,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(MITCTL0,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(wr_mitb0_r,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(mitb0_b,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(MITCTL_ENABLE_HALTED,[Default]), UsedName(MITCTL1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(MITCNT0,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(MITCNT1,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(wr_mitcnt0_r,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(mitctl1_0_b,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(mitcnt1_ns,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(mitcnt1,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(mitctl0_0_b_ns,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(mitctl0_0_b,[Default]), UsedName(mitcnt1_inc_ok,[Default]), UsedName(mitctl1_ns,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(wr_mitctl1_r,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(wr_mitcnt1_r,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(mitb1_b,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mit1_match_ns,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(el2_dec_timer_ctl,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(MITCTL_ENABLE_PAUSED,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(mitcnt0_ns,[Default]), UsedName(mitctl1_0_b_ns,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(wr_mitb1_r,[Default]), UsedName(parentModName,[Default]), UsedName(wr_mitctl0_r,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(mitcnt1_inc,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(mitb1,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(mitcnt0_inc,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(MITCTL_ENABLE,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(mitb0,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.el2_dec_timer_ctl has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_timer_ctl)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.ifu_dec...
-[debug] Initial set of included nodes: include.ifu_dec
-[debug] Invalidated by transitive inheritance dependency: Set(include.ifu_dec)
-[debug] The following member ref dependencies of include.ifu_dec are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	ifu.ifu
-[debug] 	quasar
-[debug] Change NamesChange(include.ifu_dec,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(ifu_dec,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(dec_ifc,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(dec_mem_ctrl,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(dec_bp,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(include;ifu_dec;init;,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dec_aln,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.ifu_dec has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ifu_dec)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu, quasar, dec.dec_IO, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.dec_dbg...
-[debug] Initial set of included nodes: include.dec_dbg
-[debug] Invalidated by transitive inheritance dependency: Set(include.dec_dbg)
-[debug] The following member ref dependencies of include.dec_dbg are invalidated:
-[debug] 	dbg.dbg
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dma_ctrl
-[debug] 	quasar
-[debug] Change NamesChange(include.dec_dbg,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(dbg_ib,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(dec_dbg,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dbg_dctl,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(include;dec_dbg;init;,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.dec_dbg has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.dec_dbg)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, quasar, dec.dec_IO, dbg.dbg, dma_ctrl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.el2_load_cam_pkt_t...
-[debug] Initial set of included nodes: include.el2_load_cam_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.el2_load_cam_pkt_t)
-[debug] Change NamesChange(include.el2_load_cam_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(include;el2_load_cam_pkt_t;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(wb,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(valid,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(tag,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(el2_load_cam_pkt_t,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.el2_load_cam_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.el2_load_cam_pkt_t)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.param...
-[debug] Initial set of included nodes: lib.param
-[debug] Including dec.dec by lib.param
-[debug] Including dec.dec_ib_ctl_IO by lib.param
-[debug] Including lsu.lsu by lib.param
-[debug] Including dec.dec_ib_ctl by lib.param
-[debug] Including lib.lib by lib.param
-[debug] Including lsu.lsu_clkdomain by lib.lib
-[debug] Including exu.exu by lib.lib
-[debug] Including dec.dec_decode_ctl by lib.lib
-[debug] Including lsu.lsu_trigger by lib.lib
-[debug] Including include.exu_bp by lib.lib
-[debug] Including dec.dec_gpr_ctl by lib.lib
-[debug] Including lsu.lsu_addrcheck by lib.lib
-[debug] Including mem.quasar by lib.lib
-[debug] Including include.dec_aln by lib.lib
-[debug] Including ifu.ifu by lib.lib
-[debug] Including include.aln_ib by lib.lib
-[debug] Including dec.dec_tlu_ctl_IO by lib.lib
-[debug] Including exu.exu_div_ctl by lib.lib
-[debug] Including dec.dec_tlu_ctl by lib.lib
-[debug] Including lib.ahb_to_axi4 by lib.lib
-[debug] Including lib.axi4_to_ahb by lib.lib
-[debug] Including quasar by lib.lib
-[debug] Including dec.csr_tlu by lib.lib
-[debug] Including lsu.lsu_lsc_ctl by lib.lib
-[debug] Including pic_ctrl by lib.lib
-[debug] Including include.write_data by lib.lib
-[debug] Including exu.exu_alu_ctl by lib.lib
-[debug] Including include.tlu_exu by lib.lib
-[debug] Including dec.dec_IO by lib.lib
-[debug] Including include.iccm_mem by lib.lib
-[debug] Including quasar_bundle by lib.lib
-[debug] Including lsu.lsu_ecc by lib.lib
-[debug] Including mem.blackbox_mem by lib.lib
-[debug] Including include.write_addr by lib.lib
-[debug] Including ifu.mem_ctl_io by lib.lib
-[debug] Including lsu.lsu_bus_buffer by lib.lib
-[debug] Including quasar_wrapper by lib.lib
-[debug] Including include.write_resp by lib.lib
-[debug] Including dec.CSR_IO by lib.lib
-[debug] Including dec.dec_timer_ctl by lib.lib
-[debug] Including include.dec_exu by lib.lib
-[debug] Including include.read_data by lib.lib
-[debug] Including ifu.ifu_aln_ctl by lib.lib
-[debug] Including dbg.dbg by lib.lib
-[debug] Including include.ic_mem by lib.lib
-[debug] Including lsu.lsu_bus_intf by lib.lib
-[debug] Including exu.exu_mul_ctl by lib.lib
-[debug] Including dec.dec_trigger by lib.lib
-[debug] Including lsu.lsu_dccm_ctl by lib.lib
-[debug] Including ifu.ifu_compress_ctl by lib.lib
-[debug] Including ifu.ifu_bp_ctl by lib.lib
-[debug] Including mem.Mem_bundle by lib.lib
-[debug] Including include.dctl_busbuff by lib.lib
-[debug] Including include.read_addr by lib.lib
-[debug] Including include.axi_channels by lib.lib
-[debug] Including dec.dec_dec_ctl by lib.lib
-[debug] Including lsu.lsu_stbuf by lib.lib
-[debug] Including mem.mem_lsu by lib.lib
-[debug] Including include.dec_mem_ctrl by lib.lib
-[debug] Including ifu.ifu_mem_ctl by lib.lib
-[debug] Including ifu.ifu_ifc_ctl by lib.lib
-[debug] Including include.decode_exu by lib.lib
-[debug] Including dma_ctrl by lib.lib
-[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain, dec.dec, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, dec.dec_ib_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl)
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_bp_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of include.exu_bp. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_addrcheck: Set(UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]))
-[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of include.aln_ib. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of mem.quasar.mem: Set(UsedName(ICACHE_WAYPACK,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(DCCM_ENABLE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(ICCM_ENABLE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of dec.csr_tlu: Set(UsedName(BUILD_AXI4,[Default]), UsedName(ICACHE_ECC,[Default]))
-[debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of pic_ctrl. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of include.tlu_exu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of include.iccm_mem. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_ecc: Set(UsedName(DCCM_ENABLE,[Default]))
-[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of include.ic_mem. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_dccm_ctl: Set(UsedName(DCCM_ENABLE,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_bp_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
-[debug] None of the modified names appears in source file of include.dctl_busbuff. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of lsu.lsu_stbuf. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of mem.mem_lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_ifc_ctl: Set(UsedName(ICCM_ENABLE,[Default]))
-[debug] None of the modified names appears in source file of include.decode_exu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lib.lib: Set(UsedName(ICACHE_WAYPACK,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICACHE_ECC,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of dec.dec_ib_ctl. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec_ib_ctl_IO. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
-[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of lib.lib: Set(UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]))
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_dccm_ctl: Set(UsedName(DCCM_ENABLE,[Default]))
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
@@ -2644,7 +702,7 @@
 [debug] None of the modified names appears in source file of lsu.lsu_trigger. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.exu_bp. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_gpr_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_addrcheck: Set(UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_addrcheck. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of mem.quasar. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.dec_aln. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
@@ -2653,10 +711,10 @@
 [debug] None of the modified names appears in source file of exu.exu_div_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(ICCM_ENABLE,[Default]))
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] The following modified names cause invalidation of dec.csr_tlu: Set(UsedName(BUILD_AXI4,[Default]), UsedName(ICACHE_ECC,[Default]))
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.csr_tlu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_lsc_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of pic_ctrl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.write_data. This dependency is not being considered for invalidation.
@@ -2665,26 +723,26 @@
 [debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.iccm_mem. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_ecc: Set(UsedName(DCCM_ENABLE,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_ecc. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of mem.blackbox_mem. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.write_addr. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(BUILD_AHB_LITE,[Default]))
-[debug] None of the modified names appears in source file of quasar_wrapper. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
 [debug] None of the modified names appears in source file of include.write_resp. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.CSR_IO. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_timer_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.dec_exu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.read_data. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_aln_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.ic_mem. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of exu.exu_mul_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of dec.dec_trigger. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of lsu.lsu_dccm_ctl: Set(UsedName(DCCM_ENABLE,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of ifu.ifu_compress_ctl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_bp_ctl: Set(UsedName(BTB_BTAG_FOLD,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of mem.Mem_bundle. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.dctl_busbuff. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.read_addr. This dependency is not being considered for invalidation.
@@ -2693,353 +751,341 @@
 [debug] None of the modified names appears in source file of lsu.lsu_stbuf. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of mem.mem_lsu. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.dec_mem_ctrl. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(ICACHE_ENABLE,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_ifc_ctl: Set(UsedName(ICCM_ENABLE,[Default]))
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_ifc_ctl. This dependency is not being considered for invalidation.
 [debug] None of the modified names appears in source file of include.decode_exu. This dependency is not being considered for invalidation.
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(ICCM_ENABLE,[Default]), UsedName(DMA_BUS_ID,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(BUILD_AHB_LITE,[Default]))
-[debug] Change NamesChange(lib.param,ModifiedNames(changes = UsedName(ICACHE_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]))) invalidates 65 classes due to The lib.param has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]).
-[debug] 	> by transitive inheritance: Set(lsu.lsu_clkdomain, dec.dec, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, dec.dec_ib_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl)
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lib.lib,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 60 classes due to The lib.lib has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_clkdomain, exu.exu, dec.dec_decode_ctl, lsu.lsu_trigger, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, ifu.ifu, include.aln_ib, dec.dec_tlu_ctl_IO, exu.exu_div_ctl, lsu.lsu, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, lsu.lsu_lsc_ctl, pic_ctrl, include.write_data, exu.exu_alu_ctl, include.tlu_exu, dec.dec_IO, include.iccm_mem, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.write_addr, ifu.mem_ctl_io, lsu.lsu_bus_buffer, quasar_wrapper, include.write_resp, dec.CSR_IO, dec.dec_timer_ctl, include.dec_exu, include.read_data, ifu.ifu_aln_ctl, dbg.dbg, include.ic_mem, lsu.lsu_bus_intf, exu.exu_mul_ctl, dec.dec_trigger, lsu.lsu_dccm_ctl, ifu.ifu_compress_ctl, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.decode_exu, lib.lib, dma_ctrl)
 [debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_addrcheck, mem.quasar.mem, lib.ahb_to_axi4, quasar, dec.csr_tlu, lsu.lsu_ecc, lsu.lsu_bus_buffer, ifu.ifu_aln_ctl, lsu.lsu_dccm_ctl, ifu.ifu_bp_ctl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, lib.lib, dma_ctrl)
+[debug] 	> by member reference: Set(quasar_wrapper, lib.lib)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvbsadder...
-[debug] Initial set of included nodes: lib.rvbsadder
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvbsadder)
-[debug] Change NamesChange(lib.rvbsadder,ModifiedNames(changes = UsedName(dout_upper,[Default]), UsedName(pc,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(lib;rvbsadder;init;,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rvbsadder,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(offset,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvbsadder has the following regular definitions changed:
-[debug] 	UsedName(dout_upper,[Default]), UsedName(pc,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(lib;rvbsadder;init;,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(rvbsadder,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(offset,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvbsadder)
+[debug] Invalidating (transitively) by inheritance from include.tlu_exu...
+[debug] Initial set of included nodes: include.tlu_exu
+[debug] Invalidated by transitive inheritance dependency: Set(include.tlu_exu)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.tlu_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.tlu_exu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.tlu_exu)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.ic_data_ext_in_pkt_t...
-[debug] Initial set of included nodes: include.ic_data_ext_in_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.ic_data_ext_in_pkt_t)
-[debug] Change NamesChange(include.ic_data_ext_in_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(RM,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(SD,[Default]), UsedName(BC2,[Default]), UsedName(bind,[Default]), UsedName(RME,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ic_data_ext_in_pkt_t,[Default]), UsedName(ref,[Default]), UsedName(BC1,[Default]), UsedName(do_asUInt,[Default]), UsedName(DS,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(LS,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(TEST1,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(TEST_RNM,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(include;ic_data_ext_in_pkt_t;init;,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The include.ic_data_ext_in_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ic_data_ext_in_pkt_t)
+[debug] Invalidating (transitively) by inheritance from include.dec_mem_ctrl...
+[debug] Initial set of included nodes: include.dec_mem_ctrl
+[debug] Invalidated by transitive inheritance dependency: Set(include.dec_mem_ctrl)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_tlu_ctl_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_tlu_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.dec_mem_ctrl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.dec_mem_ctrl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(include.dec_mem_ctrl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec...
-[debug] Initial set of included nodes: dec.el2_dec
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec)
-[debug] Change NamesChange(dec.el2_dec,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(gpr,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(instbuff,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(decode,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec_trigger,[Default]), UsedName(forceName,[Default]), UsedName(tlu,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dec;el2_dec;init;,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(el2_dec,[Default]))) invalidates 1 classes due to The dec.el2_dec has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(gpr,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(instbuff,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(decode,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec_trigger,[Default]), UsedName(forceName,[Default]), UsedName(tlu,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(dec;el2_dec;init;,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(el2_dec,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec)
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_dccm_ctl...
+[debug] Initial set of included nodes: lsu.lsu_dccm_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_dccm_ctl)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_dccm_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_dccm_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_dccm_ctl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.lsu_pkt_t...
-[debug] Initial set of included nodes: include.lsu_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.lsu_pkt_t)
-[debug] The following member ref dependencies of include.lsu_pkt_t are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	dec.dec_decode_ctl
-[debug] 	lsu.lsu
-[debug] 	lsu.lsu_addrcheck
-[debug] 	lsu.lsu_bus_buffer
-[debug] 	lsu.lsu_bus_intf
-[debug] 	lsu.lsu_clkdomain
-[debug] 	lsu.lsu_dccm_ctl
-[debug] 	lsu.lsu_ecc
-[debug] 	lsu.lsu_lsc_ctl
-[debug] 	lsu.lsu_stbuf
-[debug] 	lsu.lsu_trigger
-[debug] 	quasar
-[debug] Change NamesChange(include.lsu_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(fast_int,[Default]), UsedName(word,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(store,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(by,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(load_ldst_bypass_d,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(store_data_bypass_m,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(half,[Default]), UsedName(do_asUInt,[Default]), UsedName(dma,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(lsu_pkt_t,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(store_data_bypass_d,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(include;lsu_pkt_t;init;,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(unsign,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(dword,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 15 classes due to The include.lsu_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.lsu_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_clkdomain, dec.dec, dec.dec_decode_ctl, lsu.lsu_trigger, lsu.lsu_addrcheck, lsu.lsu, quasar, lsu.lsu_lsc_ctl, dec.dec_IO, lsu.lsu_ecc, lsu.lsu_bus_buffer, lsu.lsu_bus_intf, lsu.lsu_dccm_ctl, lsu.lsu_stbuf)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.load_cam_pkt_t...
-[debug] Initial set of included nodes: include.load_cam_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.load_cam_pkt_t)
-[debug] The following member ref dependencies of include.load_cam_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(include.load_cam_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(include;load_cam_pkt_t;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(wb,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(tag,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(load_cam_pkt_t,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The include.load_cam_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.load_cam_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvdffsc...
-[debug] Initial set of included nodes: lib.rvdffsc
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvdffsc)
-[debug] Change NamesChange(lib.rvdffsc,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(clear,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(din,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(rvdffsc,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(lib;rvdffsc;init;,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvdffsc has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lib.rvdffsc)
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_lsc_ctl...
+[debug] Initial set of included nodes: lsu.lsu_lsc_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_lsc_ctl)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_lsc_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_lsc_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_lsc_ctl)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.ib_exu...
-[debug] Initial set of included nodes: include.ib_exu
-[debug] Invalidated by transitive inheritance dependency: Set(include.ib_exu)
-[debug] The following member ref dependencies of include.ib_exu are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_ib_ctl
-[debug] 	dec.dec_ib_ctl_IO
-[debug] 	exu.exu
-[debug] Change NamesChange(include.ib_exu,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(include;ib_exu;init;,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(dec_debug_wdata_rs1_d,[Default]), UsedName(widthOption,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ib_exu,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.ib_exu has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.ib_exu)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_ib_ctl_IO, dec.dec_ib_ctl, dec.dec, exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib.rvdffe...
-[debug] Initial set of included nodes: lib.el2_lib.rvdffe
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib.rvdffe)
-[debug] Change NamesChange(lib.el2_lib.rvdffe,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib.rvdffe has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(apply,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvdffe,[Default]), UsedName(ne,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib.rvdffe)
+[debug] Invalidating (transitively) by inheritance from dec.csr_tlu...
+[debug] Initial set of included nodes: dec.csr_tlu
+[debug] Invalidated by transitive inheritance dependency: Set(dec.csr_tlu)
+[debug] Change NamesChange(dec.csr_tlu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The dec.csr_tlu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(dec.csr_tlu)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.aln_ib...
-[debug] Initial set of included nodes: include.aln_ib
-[debug] Invalidated by transitive inheritance dependency: Set(include.aln_ib)
-[debug] The following member ref dependencies of include.aln_ib are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_ib_ctl
-[debug] 	dec.dec_ib_ctl_IO
-[debug] 	ifu.ifu_aln_ctl
-[debug] Change NamesChange(include.aln_ib,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(aln_ib,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ifu_i0_bp_fghr,[Default]), UsedName(ifu_i0_bp_btag,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(include;aln_ib;init;,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(i0_brp,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(ifu_i0_pc4,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ifu_i0_icaf_f1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(ifu_i0_icaf_type,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(ifu_i0_dbecc,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(ifu_i0_bp_index,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ifu_i0_pc,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(ifu_i0_instr,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ifu_i0_valid,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(ifu_i0_icaf,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 5 classes due to The include.aln_ib has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.aln_ib)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_ib_ctl, dec.dec_ib_ctl_IO, ifu.ifu_aln_ctl, dec.dec)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from include.class_pkt_t...
-[debug] Initial set of included nodes: include.class_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.class_pkt_t)
-[debug] The following member ref dependencies of include.class_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(include.class_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(load,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(alu,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(mul,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(class_pkt_t,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(include;class_pkt_t;init;,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The include.class_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.class_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from quasar_wrapper...
-[debug] Initial set of included nodes: quasar_wrapper
-[debug] Invalidated by transitive inheritance dependency: Set(quasar_wrapper)
-[debug] Change NamesChange(quasar_wrapper,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(jtag_trst_n,[Default]), UsedName(dma_hwdata,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(rv_trace_pkt,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dma_axi,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(debug_brkpt_status,[Default]), UsedName(quasar_wrapper,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(dma_bus_clk_en,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(core_id,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(dma_hburst,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(core,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(mpc_reset_run_req,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(o_cpu_halt_ack,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(jtag_id,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dec_tlu_perfcnt2,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(dma_hrdata,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(dma_haddr,[Default]), UsedName(jtag_tck,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(dbg_rst_l,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(dma_hsel,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(jtag_tdo,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(sb_axi,[Default]), UsedName(lsu_axi,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(i_cpu_run_req,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dma_hwrite,[Default]), UsedName(core_rst_l,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(lsu_bus_clk_en,[Default]), UsedName(mbist_mode,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(soft_int,[Default]), UsedName(mpc_debug_run_ack,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(o_debug_mode_status,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dec_tlu_perfcnt1,[Default]), UsedName(i_cpu_halt_req,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(jtag_tdi,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(dbg_bus_clk_en,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(dma_hresp,[Default]), UsedName(o_cpu_halt_status,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(o_cpu_run_ack,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(dec_tlu_perfcnt3,[Default]), UsedName(mpc_debug_halt_req,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(dma_htrans,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(ifu_axi,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(mpc_debug_halt_ack,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(dmi_wrapper,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(mem,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mpc_debug_run_req,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(rst_vec,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dec_tlu_perfcnt0,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(nmi_int,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(quasar_wrapper;init;,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(extintsrc_req,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(jtag_tms,[Default]), UsedName(dma_hsize,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ifu_bus_clk_en,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(dma_hprot,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(timer_int,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(nmi_vec,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The quasar_wrapper has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(quasar_wrapper)
+[debug] Invalidating (transitively) by inheritance from exu.exu...
+[debug] Initial set of included nodes: exu.exu
+[debug] Invalidated by transitive inheritance dependency: Set(exu.exu)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(exu.exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The exu.exu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(exu.exu)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.ahb_to_axi4...
-[debug] Initial set of included nodes: lib.ahb_to_axi4
-[debug] Invalidated by transitive inheritance dependency: Set(lib.ahb_to_axi4)
-[debug] The following member ref dependencies of lib.ahb_to_axi4 are invalidated:
-[debug] 	quasar
-[debug] Change NamesChange(lib.ahb_to_axi4,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(buf_state_en,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(axi_rready,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(axi_bresp,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(cmdbuf_rst,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(buf_rdata,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ahb_htrans_in,[Default]), UsedName(axi_awready,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(ahb_hsel,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(ahb_haddr,[Default]), UsedName(rvecc_encode,[Default]), UsedName(buf_read_error_in,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(axi_wvalid,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(ahb_hsize_q,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ahb_bus_addr_clk_en,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(ahb_htrans_q,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(ahb_addr_in_dccm_region_nc,[Default]), UsedName(axi_awid,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(axi_wready,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bus_clk,[Default]), UsedName(ahb_hwdata,[Default]), UsedName(rvbradder,[Default]), UsedName(axi_arburst,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(ahb_addr_in_pic,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(buf_rdata_en,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(ahb_hwrite_q,[Default]), UsedName(getPorts,[Default]), UsedName(ahb_hrdata,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(ahb_hreadyin,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(bus_clk_en,[Default]), UsedName(rd,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(pend,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(axi_bready,[Default]), UsedName(ahb_hprot,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(ahb_haddr_q,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(axi_awburst,[Default]), UsedName(ahb_hresp_q,[Default]), UsedName(wr,[Default]), UsedName(buf_rdata_clk_en,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(axi_arvalid,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(axi_rdata,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(axi_wstrb,[Default]), UsedName(ahb_htrans,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ahb_addr_in_iccm_region_nc,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(ahb_hreadyout,[Default]), UsedName(ahb_hsize,[Default]), UsedName(ahb_hwrite,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(axi_awsize,[Default]), UsedName(idle,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(ahb_hresp,[Default]), UsedName(axi_arready,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(ahb_to_axi4,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(axi_araddr,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(axi_bvalid,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(ahb_clk,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(cmdbuf_wdata,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(axi_wlast,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(axi_bid,[Default]), UsedName(clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(axi_awaddr,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(ahb_addr_in_iccm,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ahb_addr_in_pic_region_nc,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(TAG,[Default]), UsedName(buf_nxtstate,[Default]), UsedName(master_wstrb,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(axi_rresp,[Default]), UsedName(io,[Default]), UsedName(ahb_hready_q,[Default]), UsedName(buf_read_error,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(axi_arid,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(cmdbuf_wr_en,[Default]), UsedName(axi_arsize,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(axi_arprot,[Default]), UsedName(cmdbuf_write,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(ahb_hmastlock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(cmdbuf_full,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ahb_hready,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(buf_rdata_clk,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(axi_awvalid,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(ahb_hburst,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(axi_rid,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(cmdbuf_size,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(cmdbuf_addr,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(ahb_addr_in_dccm,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(axi_rvalid,[Default]), UsedName(ahb_hwdata_q,[Default]), UsedName(axi_awlen,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(cmdbuf_wstrb,[Default]), UsedName(axi_awprot,[Default]), UsedName(ahb_addr_clk,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(cmdbuf_vld,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(buf_state,[Default]), UsedName(axi_wdata,[Default]), UsedName(toTarget,[Default]), UsedName(axi_arlen,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(namingContext$macro$1,[Default]), UsedName(lib;ahb_to_axi4;init;,[Default]))) invalidates 2 classes due to The lib.ahb_to_axi4 has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lib.ahb_to_axi4)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvecc_decode...
-[debug] Initial set of included nodes: lib.rvecc_decode
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvecc_decode)
-[debug] Change NamesChange(lib.rvecc_decode,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(din_plus_parity,[Default]), UsedName(ecc_in,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(dout_plus_parity,[Default]), UsedName(lib;rvecc_decode;init;,[Default]), UsedName(sed_ded,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(single_ecc_error,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(double_ecc_error,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(error_mask,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(ecc_check,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvecc_decode has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(din_plus_parity,[Default]), UsedName(ecc_in,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(mask0,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(dout_plus_parity,[Default]), UsedName(lib;rvecc_decode;init;,[Default]), UsedName(sed_ded,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(single_ecc_error,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(double_ecc_error,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(n,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(error_mask,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(ecc_check,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvecc_decode)
+[debug] Invalidating (transitively) by inheritance from include.dec_aln...
+[debug] Initial set of included nodes: include.dec_aln
+[debug] Invalidated by transitive inheritance dependency: Set(include.dec_aln)
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.dec_aln,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dec_aln has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.dec_aln)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.trace_pkt_t...
-[debug] Initial set of included nodes: include.trace_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.trace_pkt_t)
-[debug] The following member ref dependencies of include.trace_pkt_t are invalidated:
-[debug] 	dec.dec
-[debug] 	dec.dec_IO
-[debug] 	quasar
-[debug] 	quasar_bundle
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(include.trace_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(rv_i_valid_ip,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(rv_i_insn_ip,[Default]), UsedName(litArg,[Default]), UsedName(rv_i_exception_ip,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(rv_i_address_ip,[Default]), UsedName(flatten,[Default]), UsedName(rv_i_ecause_ip,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(rv_i_interrupt_ip,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(trace_pkt_t,[Default]), UsedName(include;trace_pkt_t;init;,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(rv_i_tval_ip,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 6 classes due to The include.trace_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.trace_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec, quasar, dec.dec_IO, quasar_bundle, quasar_wrapper)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.el2_lib...
-[debug] Initial set of included nodes: lib.el2_lib
-[debug] Invalidated by transitive inheritance dependency: Set(lib.el2_lib)
-[debug] Change NamesChange(lib.el2_lib,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(el2_btb_tag_hash,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bool2int,[Implicit]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(el2_lib,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(el2_configurable_gw,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(el2_btb_ghr_hash,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(el2_btb_addr_hash,[Default]), UsedName(getClass,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(el2_btb_tag_hash_fold,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.el2_lib has the following implicit definitions changed:
-[debug] 	UsedName(bool2int,[Implicit]), UsedName(aslong,[Implicit]).
-[debug] 	> by transitive inheritance: Set(lib.el2_lib)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.el2_dec_ib_ctl_IO...
-[debug] Initial set of included nodes: dec.el2_dec_ib_ctl_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.el2_dec_ib_ctl_IO)
-[debug] Change NamesChange(dec.el2_dec_ib_ctl_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(dec_ib0_valid_d,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(dbg_cmd_write,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(dec_i0_pc4_d,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(dec_i0_dbecc_d,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(ifu_i0_bp_fghr,[Default]), UsedName(dec_i0_icaf_type_d,[Default]), UsedName(ifu_i0_bp_btag,[Default]), UsedName(dec_debug_fence_d,[Default]), UsedName(dec;el2_dec_ib_ctl_IO;init;,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(dec_i0_brp,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(i0_brp,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(ifu_i0_pc4,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ifu_i0_icaf_f1,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(ifu_i0_icaf_type,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(dec_i0_bp_index,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_i0_bp_fghr,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(dbg_cmd_type,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(ifu_i0_dbecc,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(dec_i0_instr_d,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(ifu_i0_bp_index,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ifu_i0_pc,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(dbg_cmd_valid,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dec_i0_icaf_d,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(dec_debug_wdata_rs1_d,[Default]), UsedName(widthOption,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(dec_i0_bp_btag,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(ifu_i0_instr,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(el2_dec_ib_ctl_IO,[Default]), UsedName(ifu_i0_valid,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_icaf_f1_d,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(dbg_cmd_addr,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(ifu_i0_icaf,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.el2_dec_ib_ctl_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.el2_dec_ib_ctl_IO)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvlsadder...
-[debug] Initial set of included nodes: lib.rvlsadder
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvlsadder)
-[debug] Change NamesChange(lib.rvlsadder,ModifiedNames(changes = UsedName(dout_upper,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(rs1,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(lib;rvlsadder;init;,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(offset,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvlsadder has the following regular definitions changed:
-[debug] 	UsedName(dout_upper,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(rs1,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(lib;rvlsadder;init;,[Default]), UsedName(setRef,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(offset,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvlsadder)
-[debug] 	> 
-[debug] 	> 
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec...
-[debug] Initial set of included nodes: dec.dec
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec)
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(IO,[Default]), UsedName(dec;dec;init;,[Default]), UsedName(dec,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(io,[Default]), UsedName(clock,[Default]))
-[debug] Change NamesChange(dec.dec,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(gpr,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(instbuff,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(decode,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(dec;dec;init;,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec_trigger,[Default]), UsedName(forceName,[Default]), UsedName(tlu,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dec,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The dec.dec has the following regular definitions changed:
-[debug] 	UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_i0_pc_wb1,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(dec_i0_trigger_match_d,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(gpr,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(instbuff,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(decode,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(dec;dec;init;,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(dec_trigger,[Default]), UsedName(forceName,[Default]), UsedName(tlu,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(dec,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(dec_tlu_exc_cause_wb1,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(dec_tlu_i0_valid_wb1,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(dec_tlu_mtval_wb1,[Default]), UsedName(reset,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(dec_tlu_i0_exc_valid_wb1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(dec_tlu_int_valid_wb1,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(dec_i0_inst_wb1,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec)
-[debug] 	> 
-[debug] 	> by member reference: Set(quasar)
-[debug]         
 [debug] Invalidating (transitively) by inheritance from ifu.ifu_compress_ctl...
 [debug] Initial set of included nodes: ifu.ifu_compress_ctl
 [debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_compress_ctl)
-[debug] The following member ref dependencies of ifu.ifu_compress_ctl are invalidated:
-[debug] 	ifu.ifu_aln_ctl
-[debug] Change NamesChange(ifu.ifu_compress_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(rdrd,[Default]), UsedName(l1_31,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(rs2pd,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(l1_11,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(l2_31,[Default]), UsedName(ifu_compress_ctl,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(sjald_12,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(sjald_1,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(l2,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(uswspimm7d,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(uimm5d,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rs2prd,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(l3_11,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(dout,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(sluimm17_12,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ulwimm6d,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(rdeq1,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(simm9d,[Default]), UsedName(uswimm6d,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(ifu;ifu_compress_ctl;init;,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(rs2d,[Default]), UsedName(ulwimm6_2,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(din,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(rdprs1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(l3_31,[Default]), UsedName(ulwspimm7_2,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName(uswspimm7_2,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(sjald,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(rdpd,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(pat,[Default]), UsedName(sbroffset8_1,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(l1_19,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(rs2rs2,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(uimm9d,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(l1_24,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(legal,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(sluimmd,[Default]), UsedName(sjaloffset11_1,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(l1_14,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(uimm5_0,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName(simm5d,[Default]), UsedName($isInstanceOf,[Default]), UsedName(rs2prs2,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(simm5_0,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(l3_24,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(l1_6,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(uswimm6_2,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(l3,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ulwspimm7d,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(rs1eq2,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(l1,[Default]), UsedName(rdprd,[Default]), UsedName(simm9_4,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(l2_19,[Default]), UsedName(rdd,[Default]), UsedName(rdeq2,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(sbr8d,[Default]), UsedName(uimm9_2,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(rdrs1,[Default]), UsedName(out,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The ifu.ifu_compress_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
+[debug] None of the modified names appears in source file of ifu.ifu_aln_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu_compress_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_compress_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
 [debug] 	> by transitive inheritance: Set(ifu.ifu_compress_ctl)
 [debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu_aln_ctl)
+[debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_trig...
-[debug] Initial set of included nodes: dec.dec_trig
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_trig)
-[debug] Change NamesChange(dec.dec_trig,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(dec_trig,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The dec.dec_trig has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName(dec_trig,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(dec.dec_trig)
+[debug] Invalidating (transitively) by inheritance from mem.mem_lsu...
+[debug] Initial set of included nodes: mem.mem_lsu
+[debug] Invalidated by transitive inheritance dependency: Set(mem.mem_lsu)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of lsu.lsu_dccm_ctl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(mem.mem_lsu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The mem.mem_lsu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(mem.mem_lsu)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.exu_bp...
+[debug] Initial set of included nodes: include.exu_bp
+[debug] Invalidated by transitive inheritance dependency: Set(include.exu_bp)
+[debug] None of the modified names appears in source file of ifu.ifu_bp_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.exu_bp,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.exu_bp has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.exu_bp)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from ifu.ifu_bp_ctl...
-[debug] Initial set of included nodes: ifu.ifu_bp_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_bp_ctl)
-[debug] The following member ref dependencies of ifu.ifu_bp_ctl are invalidated:
-[debug] 	ifu.ifu
-[debug] Change NamesChange(ifu.ifu_bp_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(hist0_raw,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(tag_match_way1_f,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(bht_bank1_rd_data_f,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(leak_one_f_d1,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(tag_match_way0_f,[Default]), UsedName(tag_match_vway1_expanded_f,[Default]), UsedName(ic_hit_f,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(bht_rd_addr_hashed_p1_f,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(tag_match_way1_expanded_p1_f,[Default]), UsedName(exu_mp_way_f,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ifu_bp_btb_target_f,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(btb_rd_ret_f,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ifu_bp_hist1_f,[Default]), UsedName(btb_lru_b0_f,[Default]), UsedName(fetch_start_f,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(bht_dir_f,[Default]), UsedName(btb_vlru_rd_f,[Default]), UsedName(btb_bank0_rd_data_way0_out,[Default]), UsedName(rvecc_encode,[Default]), UsedName(dec_tlu_flush_lower_wb,[Default]), UsedName(btb_valid,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(TAG_START,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(exu_mp_valid,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(exu_flush_final,[Default]), UsedName(isInstanceOf,[Default]), UsedName(branch_error_bank_conflict_f,[Default]), UsedName(exu_flush_ghr,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(vwayhit_f,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(btb_rd_pc4_f,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(btb_lru_b0_ns,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(fetch_wrindex_p1_dec,[Default]), UsedName(branch_error_bank_conflict_p1_f,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(btb_rd_addr_f,[Default]), UsedName(ifu_bp_valid_f,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(btb_wr_en_way0,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(bht_vbank0_rd_data_f,[Default]), UsedName(toNamed,[Default]), UsedName(branch_error_collision_p1_f,[Default]), UsedName(getCommands,[Default]), UsedName(leak_one_f,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(btb_rd_tgt_f,[Default]), UsedName(bht_rd_addr_f,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(btb_wr_en_way1,[Default]), UsedName(btb_rd_addr_p1_f,[Default]), UsedName(ifu;ifu_bp_ctl;init;,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(bloc_f,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(btb_wr_tag,[Default]), UsedName(btb_bank0e_rd_data_p1_f,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(use_mp_way_p1,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(fetch_mp_collision_f,[Default]), UsedName(hist1_raw,[Default]), UsedName(middle_of_bank,[Default]), UsedName(rs_hold,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(bht_wr_data2,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(PC4,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(exu_mp_call,[Default]), UsedName(btb_bank0o_rd_data_f,[Default]), UsedName(configurable_gw,[Default]), UsedName(exu_bp,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(mp_hashed,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(fetch_mp_collision_p1_f,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(fghr,[Default]), UsedName(bht_bank0_rd_data_p1_f,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(dec_tlu_br0_start_error_wb,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(exu_mp_ret,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(wayhit_p1_f,[Default]), UsedName(btb_wr_data,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(tag_match_way0_expanded_p1_f,[Default]), UsedName(use_mp_way,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(bht_bank_clk,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(bht_bank0_rd_data_f,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(exu_i0_br_fghr_wb,[Default]), UsedName(forceName,[Default]), UsedName(BV,[Default]), UsedName(bht_wr_data0,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(LRU_SIZE,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(rets_in,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ifu_bp_hist0_f,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(bht_wr_en2,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(merged_ghr,[Default]), UsedName(bht_vbank1_rd_data_f,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(ifu_bp_poffset_f,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(exu_mp_tgt,[Default]), UsedName(override_reset,[Default]), UsedName(dec_tlu_br0_hist_wb,[Default]), UsedName(initializeInParent,[Default]), UsedName(btb_vbank0_rd_data_f,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ifu_bp_fghr_f,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(bht_wr_addr0,[Default]), UsedName(rsenable,[Default]), UsedName(ifu_bp_pc4_f,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(exu_mp_hist,[Default]), UsedName(ifu_bp_hit_taken_f,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(fetch_rd_tag_p1_f,[Default]), UsedName(btb_bank0_rd_data_way1_p1_f,[Default]), UsedName(fetch_wrindex_dec,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(pc4_raw,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(final_h,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(dec_bp,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(pret_raw,[Default]), UsedName(btb_fg_crossing_f,[Default]), UsedName(setRef,[Default]), UsedName(rs_push,[Default]), UsedName(rvdffe,[Default]), UsedName(fetch_addr_p1_f,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(fetch_rd_tag_f,[Default]), UsedName(ifu_bp_ctl,[Default]), UsedName(rvclkhdr,[Default]), UsedName(RET,[Default]), UsedName(lru_update_valid_f,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ifu_bp_inst_mask_f,[Default]), UsedName(eoc_near,[Default]), UsedName(bp_rs_call_target_f,[Default]), UsedName(exu_mp_ja,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(btb_lru_b0_hold,[Default]), UsedName(ifu_bp_ret_f,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(tag_match_way1_expanded_f,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(dec_tlu_br0_v_wb,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(btb_lru_rd_p1_f,[Default]), UsedName(wayhit_f,[Default]), UsedName(bht_bank_rd_data_out,[Default]), UsedName(gated_latch,[Default]), UsedName(btb_error_addr_wb,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(btb_bank0e_rd_data_f,[Default]), UsedName(dec_tlu_br0_error_wb,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(bp_btb_target_adder_f,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(CALL,[Default]), UsedName(btb_bank0_rd_data_way0_f,[Default]), UsedName(ifc_fetch_adder_prior,[Default]), UsedName(tag_match_way0_p1_f,[Default]), UsedName(_onModuleClose,[Default]), UsedName(dec_tlu_error_wb,[Default]), UsedName(bht_valid_f,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(bp_total_branch_offset_f,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(tag_match_way1_p1_f,[Default]), UsedName(btb_wr_addr,[Default]), UsedName(bht_bank_sel,[Default]), UsedName(btb_bank0_rd_data_way0_p1_f,[Default]), UsedName(bht_wr_addr2,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(exu_mp_way,[Default]), UsedName(bht_bank_clken,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(btb_bank0_rd_data_way1_out,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(btb_sel_f,[Default]), UsedName(NUM_BHT_LOOP,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(dec_tlu_way_wb_f,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(adder_pc_in_f,[Default]), UsedName(ifu_bp_way_f,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(dec_tlu_br0_way_wb,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(BHT_NO_ADDR_MATCH,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(mp_wrlru_b0,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(exu_mp_ataken,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(exu_mp_valid_write,[Default]), UsedName(dec_tlu_br0_addr_wb,[Default]), UsedName(notify,[Default]), UsedName(ifc_fetch_addr_f,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(exu_mp_boffset,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(btb_vbank1_rd_data_f,[Default]), UsedName(getRef,[Default]), UsedName(branch_error_collision_f,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(exu_mp_addr,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(br0_hashed_wb,[Default]), UsedName(NUM_BHT_LOOP_INNER_HI,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(num_valids,[Default]), UsedName(rs_pop,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(namingContext$macro$2,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(tag_match_way0_expanded_f,[Default]), UsedName(bht_rd_addr_p1_f,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(btb_sel_data_f,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(rets_out,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(exu_flush_final_d1,[Default]), UsedName(bht_force_taken_f,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(btb_rd_call_f,[Default]), UsedName(ifc_fetch_req_f,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(use_fa_plus,[Default]), UsedName(btb_lru_rd_f,[Default]), UsedName(BOFF,[Default]), UsedName(active_clk,[Default]), UsedName(bht_rd_addr_hashed_f,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(bht_wr_en0,[Default]), UsedName(fetch_wrlru_b0,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(NUM_BHT_LOOP_OUTER_LO,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(eoc_mask,[Default]), UsedName(dec_tlu_way_wb,[Default]), UsedName(mp_wrindex_dec,[Default]), UsedName(fetch_wrlru_p1_b0,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(bht_bank_wr_data,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(fghr_ns,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(btb_bank0_rd_data_way1_f,[Default]), UsedName(dec_tlu_br0_middle_wb,[Default]), UsedName(exu_mp_pc4,[Default]))) invalidates 2 classes due to The ifu.ifu_bp_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(ifu.ifu_bp_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(ifu.ifu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.exu_alu_ctl...
-[debug] Initial set of included nodes: exu.exu_alu_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_alu_ctl)
-[debug] The following member ref dependencies of exu.exu_alu_ctl are invalidated:
-[debug] 	exu.exu
-[debug] Change NamesChange(exu.exu_alu_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(dec_alu,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(result_ff,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ov,[Default]), UsedName(actual_taken,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(enable,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(exu;exu_alu_ctl;init;,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(bm,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(any_jal,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(flush_upper_out,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(cout,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(newhist,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(predict_p_out,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(shift_amount,[Default]), UsedName(sel_shift,[Default]), UsedName(sout,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(sel_adder,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(shift_long,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(sel_pc,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(slt_one,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(flush_upper_x,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(exu_alu_ctl,[Default]), UsedName(i0_ap,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(flush_path_out,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(shift_extend,[Default]), UsedName(pp_in,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(b_in,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(pred_correct_out,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(lt,[Default]), UsedName(ge,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(pcout,[Default]), UsedName(csr_write_data,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(shift_mask,[Default]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(lout,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(dec_tlu_flush_lower_r,[Default]), UsedName(cond_mispredict,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(dec_i0_pc_d,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(target_mispredict,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(a_in,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(flush_final_out,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName(aout,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(neg,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(result,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The exu.exu_alu_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(exu.exu_alu_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from exu.exu_mul_ctl...
-[debug] Initial set of included nodes: exu.exu_mul_ctl
-[debug] Invalidated by transitive inheritance dependency: Set(exu.exu_mul_ctl)
-[debug] The following member ref dependencies of exu.exu_mul_ctl are invalidated:
-[debug] 	exu.exu
-[debug] Change NamesChange(exu.exu_mul_ctl,ModifiedNames(changes = UsedName(ICACHE_2BANKS,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(_closed,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(rs2_x,[Default]), UsedName(desiredName,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(rvecc_encode,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(getIds,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(rvbradder,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(portsContains,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(exu_mul_ctl,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(_namespace,[Default]), UsedName(mul_x_enable,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(low_x,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(rs1_ext_in,[Default]), UsedName(result_x,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(name,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(generateComponent,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(nameIds,[Default]), UsedName(exu;exu_mul_ctl;init;,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(rs1_in,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(prod_x,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(gated_latch,[Default]), UsedName(rs2_in,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(reset,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(rvecc_decode,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(getModulePorts,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(mul_p,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(PIC_REGION,[Default]), UsedName(override_clock,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(rs1_x,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(addCommand,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(isClosed,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(rs2_ext_in,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 2 classes due to The exu.exu_mul_ctl has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
-[debug] 	> by transitive inheritance: Set(exu.exu_mul_ctl)
-[debug] 	> 
-[debug] 	> by member reference: Set(exu.exu)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from dec.dec_decode_csr_read_IO...
-[debug] Initial set of included nodes: dec.dec_decode_csr_read_IO
-[debug] Invalidated by transitive inheritance dependency: Set(dec.dec_decode_csr_read_IO)
-[debug] Change NamesChange(dec.dec_decode_csr_read_IO,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(dec_csr_rdaddr_d,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(dec_decode_csr_read_IO,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(csr_pkt,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(dec;dec_decode_csr_read_IO;init;,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 1 classes due to The dec.dec_decode_csr_read_IO has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(dec.dec_decode_csr_read_IO)
+[debug] Invalidating (transitively) by inheritance from mem.blackbox_mem...
+[debug] Initial set of included nodes: mem.blackbox_mem
+[debug] Invalidated by transitive inheritance dependency: Set(mem.blackbox_mem)
+[debug] Change NamesChange(mem.blackbox_mem,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The mem.blackbox_mem has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(mem.blackbox_mem)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from include.reg_pkt_t...
-[debug] Initial set of included nodes: include.reg_pkt_t
-[debug] Invalidated by transitive inheritance dependency: Set(include.reg_pkt_t)
-[debug] The following member ref dependencies of include.reg_pkt_t are invalidated:
-[debug] 	dec.dec_decode_ctl
-[debug] Change NamesChange(include.reg_pkt_t,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(ignoreSeq,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(direction,[Default]), UsedName(asUInt,[Default]), UsedName(binding_=,[Default]), UsedName(allElements,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(:=,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(getWidth,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(bind,[Default]), UsedName(rs1,[Default]), UsedName(rd,[Default]), UsedName(toString,[Default]), UsedName(litArg,[Default]), UsedName(getElements,[Default]), UsedName(addPostnameHook,[Default]), UsedName(include;reg_pkt_t;init;,[Default]), UsedName(forceName,[Default]), UsedName(ref,[Default]), UsedName(do_asUInt,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(rs2,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(setRef,[Default]), UsedName(flatten,[Default]), UsedName(isWidthKnown,[Default]), UsedName(_parent,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(toPrintable,[Default]), UsedName(direction_=,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(topBindingOpt,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(isLit,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName($isInstanceOf,[Default]), UsedName(widthOption,[Default]), UsedName(_makeLit,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(suggestName,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(<>,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(binding,[Default]), UsedName(getOptionRef,[Default]), UsedName(reg_pkt_t,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The include.reg_pkt_t has the following implicit definitions changed:
-[debug] 	UsedName(compileOptions,[Implicit]).
-[debug] 	> by transitive inheritance: Set(include.reg_pkt_t)
-[debug] 	> 
-[debug] 	> by member reference: Set(dec.dec_decode_ctl)
-[debug]         
-[debug] Invalidating (transitively) by inheritance from pic_main...
-[debug] Initial set of included nodes: pic_main
-[debug] Invalidated by transitive inheritance dependency: Set(pic_main)
-[debug] Change NamesChange(pic_main,ModifiedNames(changes = UsedName(isInstanceOf,[Default]), UsedName(pic_main,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The pic_main has the following regular definitions changed:
-[debug] 	UsedName(isInstanceOf,[Default]), UsedName(pic_main,[Default]), UsedName(main,[Default]), UsedName(synchronized,[Default]), UsedName(toString,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(asInstanceOf,[Default]), UsedName(ne,[Default]), UsedName(executionStart,[Default]), UsedName(delayedInit,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(notify,[Default]), UsedName(eq,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(args,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(pic_main)
-[debug] 	> 
+[debug] Invalidating (transitively) by inheritance from quasar...
+[debug] Initial set of included nodes: quasar
+[debug] Invalidated by transitive inheritance dependency: Set(quasar)
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] Change NamesChange(quasar,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 2 classes due to The quasar has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(quasar)
 [debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper)
 [debug]         
 [debug] Invalidating (transitively) by inheritance from mem.Mem_bundle...
 [debug] Initial set of included nodes: mem.Mem_bundle
 [debug] Invalidated by transitive inheritance dependency: Set(mem.Mem_bundle)
-[debug] The following member ref dependencies of mem.Mem_bundle are invalidated:
-[debug] 	quasar_wrapper
-[debug] Change NamesChange(mem.Mem_bundle,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(ICACHE_2BANKS,[Default]), UsedName(legacyConnect,[Default]), UsedName(ICACHE_ENABLE,[Default]), UsedName(INST_ACCESS_ENABLE7,[Default]), UsedName(DATA_MEM_LINE,[Default]), UsedName(ICCM_SADR,[Default]), UsedName(DATA_ACCESS_MASK0,[Default]), UsedName(BTB_INDEX3_LO,[Default]), UsedName(MEM_CAL,[Default]), UsedName(dccm_clk_override,[Default]), UsedName(PIC_BASE_ADDR,[Default]), UsedName(DATA_ACCESS_ENABLE6,[Default]), UsedName(PIC_2CYCLE,[Default]), UsedName(ignoreSeq,[Default]), UsedName(INST_ACCESS_ENABLE1,[Default]), UsedName(BTB_ADDR_HI,[Default]), UsedName(BHT_ADDR_HI,[Default]), UsedName(ICACHE_BANK_HI,[Default]), UsedName(BTB_ARRAY_DEPTH,[Default]), UsedName(ICACHE_STATUS_BITS,[Default]), UsedName(ICACHE_WAYPACK,[Default]), UsedName(INST_ACCESS_MASK7,[Default]), UsedName(ICACHE_BANK_LO,[Default]), UsedName(ICACHE_FDATA_WIDTH,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(repl,[Default]), UsedName(SB_BUS_PRTY,[Default]), UsedName(BTB_BTAG_FOLD,[Default]), UsedName(direction,[Default]), UsedName(ICCM_ENABLE,[Default]), UsedName(asUInt,[Default]), UsedName(rvecc_encode,[Default]), UsedName(iccm,[Default]), UsedName(binding_=,[Default]), UsedName(LSU_BUS_ID,[Default]), UsedName(rvecc_decode_64,[Default]), UsedName(allElements,[Default]), UsedName(ICACHE_DATA_INDEX_LO,[Default]), UsedName(getPublicFields,[Default]), UsedName(ICACHE_NUM_WAYS,[Default]), UsedName(isInstanceOf,[Default]), UsedName(DATA_ACCESS_ADDR6,[Default]), UsedName(rvrangecheck_ch,[Default]), UsedName(ICACHE_BANK_BITS,[Default]), UsedName(SB_BUS_TAG,[Default]), UsedName(Mem_bundle,[Default]), UsedName(DATA_ACCESS_ENABLE0,[Default]), UsedName(rvlsadder,[Default]), UsedName(PIC_TOTAL_INT,[Default]), UsedName(:=,[Default]), UsedName(DCCM_DATA_WIDTH,[Default]), UsedName(ICCM_BANK_BITS,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(DCCM_SIZE,[Default]), UsedName(INST_ACCESS_ADDR7,[Default]), UsedName(toNamed,[Default]), UsedName(litValue,[Default]), UsedName(ICACHE_DATA_WIDTH,[Default]), UsedName(bulkConnect,[Default]), UsedName(typeEquivalent,[Default]), UsedName(rvbradder,[Default]), UsedName(getWidth,[Default]), UsedName(BHT_ADDR_LO,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(ICACHE_BANKS_WAY,[Default]), UsedName(DATA_ACCESS_MASK3,[Default]), UsedName(btb_tag_hash,[Default]), UsedName(PIC_TOTAL_INT_PLUS1,[Default]), UsedName(INST_ACCESS_ENABLE6,[Default]), UsedName(NO_ICCM_NO_ICACHE,[Default]), UsedName(INST_ACCESS_MASK2,[Default]), UsedName(synchronized,[Default]), UsedName(isSynthesizable,[Default]), UsedName(aslong,[Implicit]), UsedName(DCCM_BANK_BITS,[Default]), UsedName(bind,[Default]), UsedName(LSU_SB_BITS,[Default]), UsedName(LSU_BUS_TAG,[Default]), UsedName(toString,[Default]), UsedName(DATA_ACCESS_MASK5,[Default]), UsedName(INST_ACCESS_ADDR5,[Default]), UsedName(configurable_gw,[Default]), UsedName(Tag_Word,[Default]), UsedName(LSU2DMA,[Default]), UsedName(INST_ACCESS_MASK1,[Default]), UsedName(BHT_GHR_HASH_1,[Default]), UsedName(DATA_ACCESS_ENABLE3,[Default]), UsedName(litArg,[Default]), UsedName(ICCM_BITS,[Default]), UsedName(btb_ghr_hash,[Default]), UsedName(rvmaskandmatch,[Default]), UsedName(INST_ACCESS_ADDR4,[Default]), UsedName(getElements,[Default]), UsedName(DCCM_BITS,[Default]), UsedName(LSU_STBUF_DEPTH,[Default]), UsedName(ICCM_REGION,[Default]), UsedName(DATA_ACCESS_ADDR2,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(DMA_BUF_DEPTH,[Default]), UsedName(ICACHE_DATA_DEPTH,[Default]), UsedName(BUILD_AXI_NATIVE,[Default]), UsedName(DATA_ACCESS_ENABLE1,[Default]), UsedName(DATA_ACCESS_MASK7,[Default]), UsedName(DATA_ACCESS_ADDR4,[Default]), UsedName(DATA_ACCESS_ENABLE5,[Default]), UsedName(DATA_ACCESS_ADDR3,[Default]), UsedName(ref,[Default]), UsedName(BUS_PRTY_DEFAULT,[Default]), UsedName(ICACHE_BANK_WIDTH,[Default]), UsedName(LOAD_TO_USE_PLUS1,[Default]), UsedName(rst_l,[Default]), UsedName(ICACHE_INDEX_HI,[Default]), UsedName(do_asUInt,[Default]), UsedName(INST_ACCESS_MASK3,[Default]), UsedName(INST_ACCESS_ADDR0,[Default]), UsedName(INST_ACCESS_ADDR1,[Default]), UsedName(DCCM_SADR,[Default]), UsedName(ICACHE_TAG_INDEX_LO,[Default]), UsedName(LSU_NUM_NBLOAD_WIDTH,[Default]), UsedName($init$,[Default]), UsedName(DCCM_NUM_BANKS,[Default]), UsedName(##,[Default]), UsedName(INST_ACCESS_MASK4,[Default]), UsedName(rvrangecheck,[Default]), UsedName(finalize,[Default]), UsedName(bindingToString,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(dec_tlu_core_ecc_disable,[Default]), UsedName(asInstanceOf,[Default]), UsedName(topBinding,[Default]), UsedName(ICACHE_LN_SZ,[Default]), UsedName(DCCM_BYTE_WIDTH,[Default]), UsedName(IFU_BUS_PRTY,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(BTB_ADDR_LO,[Default]), UsedName(DMA_BUS_ID,[Default]), UsedName(ICACHE_SIZE,[Default]), UsedName(LSU_BUS_PRTY,[Default]), UsedName(IFU_BUS_ID,[Default]), UsedName(setRef,[Default]), UsedName(rvdffe,[Default]), UsedName(DCCM_FDATA_WIDTH,[Default]), UsedName(rvsyncss,[Default]), UsedName(DATA_ACCESS_ENABLE4,[Default]), UsedName(rveven_paritycheck,[Default]), UsedName(rvclkhdr,[Default]), UsedName(flatten,[Default]), UsedName(IFU_BUS_TAG,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ICACHE_ONLY,[Default]), UsedName(DMA_BUS_PRTY,[Default]), UsedName(scan_mode,[Default]), UsedName(BTB_INDEX1_HI,[Default]), UsedName(DCCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_MASK1,[Default]), UsedName(ICACHE_TAG_LO,[Default]), UsedName(BHT_SIZE,[Default]), UsedName(BHT_GHR_SIZE,[Default]), UsedName(DATA_ACCESS_ENABLE7,[Default]), UsedName(BTB_FOLD2_INDEX_HASH,[Default]), UsedName(ICCM_BANK_INDEX_LO,[Default]), UsedName(BTB_INDEX1_LO,[Default]), UsedName(_parent,[Default]), UsedName(INST_ACCESS_ENABLE0,[Default]), UsedName(rvecc_encode_64,[Default]), UsedName(icm_clk_override,[Default]), UsedName(gated_latch,[Default]), UsedName(SB_BUS_ID,[Default]), UsedName(litOption,[Default]), UsedName(lref,[Default]), UsedName(className,[Default]), UsedName(BUILD_AHB_LITE,[Default]), UsedName(toPrintable,[Default]), UsedName(rvtwoscomp,[Default]), UsedName(direction_=,[Default]), UsedName(RET_STACK_SIZE,[Default]), UsedName(ne,[Default]), UsedName(specifiedDirection,[Default]), UsedName(rvecc_decode,[Default]), UsedName(ic,[Default]), UsedName(badConnect,[Default]), UsedName(_onModuleClose,[Default]), UsedName(DMA_BUS_TAG,[Default]), UsedName(BUILD_AXI4,[Default]), UsedName(INST_ACCESS_MASK5,[Default]), UsedName(topBindingOpt,[Default]), UsedName(INST_ACCESS_ENABLE2,[Default]), UsedName(ICACHE_ECC,[Default]), UsedName(PIC_BITS,[Default]), UsedName(DATA_ACCESS_MASK2,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(compileOptions,[Implicit]), UsedName(connectFromBits,[Default]), UsedName(INST_ACCESS_MASK6,[Default]), UsedName(clk,[Default]), UsedName(DCCM_ENABLE,[Default]), UsedName(isLit,[Default]), UsedName(INST_ACCESS_ENABLE5,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(int2boolean,[Implicit]), UsedName(BTB_SIZE,[Default]), UsedName(INST_ACCESS_MASK0,[Default]), UsedName(!=,[Default]), UsedName(TIMER_LEGAL_EN,[Default]), UsedName(ICCM_ICACHE,[Default]), UsedName(elements,[Default]), UsedName(width,[Default]), UsedName(ICACHE_BEAT_ADDR_HI,[Default]), UsedName(btb_addr_hash,[Default]), UsedName($isInstanceOf,[Default]), UsedName(BTB_INDEX2_HI,[Default]), UsedName(DATA_ACCESS_ADDR1,[Default]), UsedName(rveven_paritygen,[Default]), UsedName(widthOption,[Default]), UsedName(INST_ACCESS_ADDR2,[Default]), UsedName(mem;Mem_bundle;init;,[Default]), UsedName(_makeLit,[Default]), UsedName(PIC_REGION,[Default]), UsedName(BTB_INDEX2_LO,[Default]), UsedName(notify,[Default]), UsedName(ICCM_INDEX_BITS,[Default]), UsedName(DATA_ACCESS_ADDR0,[Default]), UsedName(PIC_INT_WORDS,[Default]), UsedName(INST_ACCESS_ENABLE3,[Default]), UsedName(getRef,[Default]), UsedName(ICCM_BANK_HI,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(BTB_BTAG_SIZE,[Default]), UsedName(DCCM_ECC_WIDTH,[Default]), UsedName(ICCM_ONLY,[Default]), UsedName(dccm,[Default]), UsedName(LSU_NUM_NBLOAD,[Default]), UsedName(INST_ACCESS_ADDR6,[Default]), UsedName(suggestName,[Default]), UsedName(DATA_ACCESS_ENABLE2,[Default]), UsedName(eq,[Default]), UsedName(FAST_INTERRUPT_REDIRECT,[Default]), UsedName(INST_ACCESS_ADDR3,[Default]), UsedName(pathName,[Default]), UsedName(DATA_ACCESS_MASK4,[Default]), UsedName(ICACHE_BEAT_BITS,[Default]), UsedName(ICCM_NUM_BANKS,[Default]), UsedName(<>,[Default]), UsedName(DCCM_REGION,[Default]), UsedName(PIC_SIZE,[Default]), UsedName(parentModName,[Default]), UsedName(bind$default$2,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(btb_tag_hash_fold,[Default]), UsedName(ICACHE_NUM_BEATS,[Default]), UsedName(INST_ACCESS_ENABLE4,[Default]), UsedName(DATA_ACCESS_ADDR5,[Default]), UsedName(ICACHE_SCND_LAST,[Default]), UsedName(BTB_INDEX3_HI,[Default]), UsedName(DCCM_WIDTH_BITS,[Default]), UsedName(ICCM_SIZE,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(uint2bool,[Implicit]), UsedName(rvrangecheck_ch$default$3,[Default]), UsedName(binding,[Default]), UsedName(DATA_ACCESS_MASK6,[Default]), UsedName(getOptionRef,[Default]), UsedName(DATA_ACCESS_ADDR7,[Default]), UsedName(ICACHE_TAG_DEPTH,[Default]), UsedName(BHT_ARRAY_DEPTH,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]), UsedName(connect,[Default]), UsedName(cloneType,[Default]))) invalidates 2 classes due to The mem.Mem_bundle has the following implicit definitions changed:
-[debug] 	UsedName(aslong,[Implicit]), UsedName(compileOptions,[Implicit]), UsedName(int2boolean,[Implicit]), UsedName(uint2bool,[Implicit]).
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] Change NamesChange(mem.Mem_bundle,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 2 classes due to The mem.Mem_bundle has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
 [debug] 	> by transitive inheritance: Set(mem.Mem_bundle)
 [debug] 	> 
 [debug] 	> by member reference: Set(quasar_wrapper)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvdff...
-[debug] Initial set of included nodes: lib.rvdff
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvdff)
-[debug] Change NamesChange(lib.rvdff,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(rvdff,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(flop,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(lib;rvdff;init;,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvdff has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(dout,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(rvdff,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(<init>$default$2,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(flop,[Default]), UsedName(_parent,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(lib;rvdff;init;,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName(<init>$default$1,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvdff)
+[debug] Invalidating (transitively) by inheritance from include.ahb_out...
+[debug] Initial set of included nodes: include.ahb_out
+[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_out)
+[debug] The following member ref dependencies of include.ahb_out are invalidated:
+[debug] 	lib.ahb_to_axi4
+[debug] 	lib.axi4_to_ahb
+[debug] Change NamesChange(include.ahb_out,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(hmastlock,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(include;ahb_out;init;,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(hsize,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(htrans,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(hburst,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(hprot,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(ahb_out,[Default]), UsedName(:=,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(hwdata,[Default]), UsedName(isWidthKnown,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(haddr,[Default]), UsedName(toNamed,[Default]), UsedName(hwrite,[Default]), UsedName(badConnect,[Default]))) invalidates 3 classes due to The include.ahb_out has the following implicit definitions changed:
+[debug] 	UsedName(compileOptions,[Implicit]).
+[debug] 	> by transitive inheritance: Set(include.ahb_out)
+[debug] 	> 
+[debug] 	> by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.ahb_in...
+[debug] Initial set of included nodes: include.ahb_in
+[debug] Invalidated by transitive inheritance dependency: Set(include.ahb_in)
+[debug] The following member ref dependencies of include.ahb_in are invalidated:
+[debug] 	lib.ahb_to_axi4
+[debug] 	lib.axi4_to_ahb
+[debug] Change NamesChange(include.ahb_in,ModifiedNames(changes = UsedName(asTypeOf,[Default]), UsedName(do_asUInt,[Default]), UsedName(hresp,[Default]), UsedName(instanceName,[Default]), UsedName(toTarget,[Default]), UsedName(suggestedName,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(setRef,[Default]), UsedName(topBindingOpt,[Default]), UsedName(asInstanceOf,[Default]), UsedName(isLit,[Default]), UsedName(typeEquivalent,[Default]), UsedName(toString,[Default]), UsedName(direction_=,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(isSynthesizable,[Default]), UsedName(synchronized,[Default]), UsedName(topBinding,[Default]), UsedName(asUInt,[Default]), UsedName(pathName,[Default]), UsedName(specifiedDirection,[Default]), UsedName(wait,[Default]), UsedName(hready,[Default]), UsedName(include;ahb_in;init;,[Default]), UsedName(getPublicFields,[Default]), UsedName(##,[Default]), UsedName(toPrintableHelper,[Default]), UsedName(width,[Default]), UsedName(ne,[Default]), UsedName(hrdata,[Default]), UsedName(ref,[Default]), UsedName(elements,[Default]), UsedName(equals,[Default]), UsedName(bulkConnect,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(==,[Default]), UsedName(suggestName,[Default]), UsedName(parentModName,[Default]), UsedName(flatten,[Default]), UsedName(binding_=,[Default]), UsedName(_makeLit,[Default]), UsedName(bind$default$2,[Default]), UsedName(parentPathName,[Default]), UsedName(isInstanceOf,[Default]), UsedName(compileOptions,[Implicit]), UsedName($isInstanceOf,[Default]), UsedName(getOptionRef,[Default]), UsedName(className,[Default]), UsedName(widthOption,[Default]), UsedName($init$,[Default]), UsedName(getElements,[Default]), UsedName(connectFromBits,[Default]), UsedName(cloneTypeFull,[Default]), UsedName(ignoreSeq,[Default]), UsedName(circuitName,[Default]), UsedName(binding,[Default]), UsedName(<>,[Default]), UsedName(litArg,[Default]), UsedName(_onModuleClose,[Default]), UsedName(specifiedDirection_=,[Default]), UsedName(lref,[Default]), UsedName(litOption,[Default]), UsedName(allElements,[Default]), UsedName(connect,[Default]), UsedName(bind,[Default]), UsedName(getRef,[Default]), UsedName(getWidth,[Default]), UsedName(addPostnameHook,[Default]), UsedName(litValue,[Default]), UsedName(hashCode,[Default]), UsedName(cloneType,[Default]), UsedName(_parent,[Default]), UsedName(eq,[Default]), UsedName(:=,[Default]), UsedName(bindingToString,[Default]), UsedName(clone,[Default]), UsedName(_id,[Default]), UsedName(isWidthKnown,[Default]), UsedName(ahb_in,[Default]), UsedName(getClass,[Default]), UsedName(do_asTypeOf,[Default]), UsedName(toPrintable,[Default]), UsedName(forceName,[Default]), UsedName(_assignCompatibilityExplicitDirection,[Default]), UsedName(direction,[Default]), UsedName($asInstanceOf,[Default]), UsedName(legacyConnect,[Default]), UsedName(toNamed,[Default]), UsedName(badConnect,[Default]))) invalidates 3 classes due to The include.ahb_in has the following implicit definitions changed:
+[debug] 	UsedName(compileOptions,[Implicit]).
+[debug] 	> by transitive inheritance: Set(include.ahb_in)
+[debug] 	> 
+[debug] 	> by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_bus_intf...
+[debug] Initial set of included nodes: lsu.lsu_bus_intf
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_bus_intf)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_bus_intf,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_bus_intf has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_bus_intf)
 [debug] 	> 
 [debug] 	> 
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.lib.rvclkhdr...
-[debug] Initial set of included nodes: lib.lib.rvclkhdr
-[debug] Invalidated by transitive inheritance dependency: Set(lib.lib.rvclkhdr)
-[debug] The following modified names cause invalidation of lsu.lsu_clkdomain: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(name,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_decode_ctl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(ne,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of exu.exu_div_ctl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(name,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of dec.dec_tlu_ctl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(isInstanceOf,[Default]), UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(name,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(ne,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(isInstanceOf,[Default]), UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of quasar: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(reset,[Default]), UsedName(io,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of dec.csr_tlu: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of pic_ctrl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(name,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(ne,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clk,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(reset,[Default]), UsedName(io,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_bp_ctl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(name,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(isInstanceOf,[Default]), UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(asInstanceOf,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(io,[Default]), UsedName(==,[Default]), UsedName(clock,[Default]))
-[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(IO,[Default]), UsedName(apply,[Default]), UsedName(en,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(lib;lib;rvclkhdr;init;,[Default]), UsedName(l1clk,[Default]), UsedName(ne,[Default]), UsedName(io,[Default]), UsedName(clk,[Default]), UsedName(clock,[Default]))
-[debug] Change NamesChange(lib.lib.rvclkhdr,ModifiedNames(changes = UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(clkhdr,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(apply,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(lib;lib;rvclkhdr;init;,[Default]), UsedName(l1clk,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(clk,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 14 classes due to The lib.lib.rvclkhdr has the following regular definitions changed:
-[debug] 	UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(clkhdr,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(getPorts,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(apply,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(name,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(en,[Default]), UsedName(setRef,[Default]), UsedName(rvclkhdr,[Default]), UsedName(scan_mode,[Default]), UsedName(_parent,[Default]), UsedName(lib;lib;rvclkhdr;init;,[Default]), UsedName(l1clk,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(clk,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.lib.rvclkhdr)
+[debug] Invalidating (transitively) by inheritance from include.dctl_busbuff...
+[debug] Initial set of included nodes: include.dctl_busbuff
+[debug] Invalidated by transitive inheritance dependency: Set(include.dctl_busbuff)
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_decode_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.dctl_busbuff,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dctl_busbuff has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.dctl_busbuff)
+[debug] 	> 
 [debug] 	> 
-[debug] 	> by member reference: Set(lsu.lsu_clkdomain, dec.dec_decode_ctl, exu.exu_div_ctl, dec.dec_tlu_ctl, lib.ahb_to_axi4, lib.axi4_to_ahb, quasar, dec.csr_tlu, pic_ctrl, dbg.dbg, ifu.ifu_bp_ctl, ifu.ifu_mem_ctl, dma_ctrl)
 [debug]         
-[debug] Invalidating (transitively) by inheritance from lib.rvecc_encode...
-[debug] Initial set of included nodes: lib.rvecc_encode
-[debug] Invalidated by transitive inheritance dependency: Set(lib.rvecc_encode)
-[debug] Change NamesChange(lib.rvecc_encode,ModifiedNames(changes = UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(lib;rvecc_encode;init;,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]))) invalidates 1 classes due to The lib.rvecc_encode has the following regular definitions changed:
-[debug] 	UsedName(w0,[Default]), UsedName(mask2,[Default]), UsedName(mask3,[Default]), UsedName(y,[Default]), UsedName(_closed,[Default]), UsedName(desiredName,[Default]), UsedName(mask1,[Default]), UsedName(k,[Default]), UsedName(rvecc_encode,[Default]), UsedName(getPublicFields,[Default]), UsedName(isInstanceOf,[Default]), UsedName(getIds,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(IO,[Default]), UsedName(mask0,[Default]), UsedName(lib;rvecc_encode;init;,[Default]), UsedName(toNamed,[Default]), UsedName(getCommands,[Default]), UsedName(parentPathName,[Default]), UsedName(circuitName,[Default]), UsedName(portsContains,[Default]), UsedName(getChiselPorts,[Default]), UsedName(synchronized,[Default]), UsedName(w3,[Default]), UsedName(getPorts,[Default]), UsedName(w1,[Default]), UsedName(toString,[Default]), UsedName(_namespace,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(ecc_out,[Default]), UsedName(w6,[Default]), UsedName(din,[Default]), UsedName(namePorts,[Default]), UsedName(addPostnameHook,[Default]), UsedName(forceName,[Default]), UsedName(x,[Default]), UsedName(name,[Default]), UsedName(m,[Default]), UsedName(override_reset,[Default]), UsedName(initializeInParent,[Default]), UsedName(generateComponent,[Default]), UsedName(nameIds,[Default]), UsedName($init$,[Default]), UsedName(##,[Default]), UsedName(finalize,[Default]), UsedName(hashCode,[Default]), UsedName(instanceName,[Default]), UsedName(asInstanceOf,[Default]), UsedName(setRef,[Default]), UsedName(z,[Default]), UsedName(_parent,[Default]), UsedName(w2,[Default]), UsedName(reset,[Default]), UsedName(ne,[Default]), UsedName(_onModuleClose,[Default]), UsedName(io,[Default]), UsedName(clone,[Default]), UsedName(==,[Default]), UsedName(_component,[Default]), UsedName(_compatAutoWrapPorts,[Default]), UsedName(portsSize,[Default]), UsedName(getModulePorts,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(mask4,[Default]), UsedName(!=,[Default]), UsedName($isInstanceOf,[Default]), UsedName(override_clock,[Default]), UsedName(notify,[Default]), UsedName(getRef,[Default]), UsedName(suggestName,[Default]), UsedName(mkReset,[Default]), UsedName(eq,[Default]), UsedName(pathName,[Default]), UsedName(compileOptions,[Default]), UsedName(addCommand,[Default]), UsedName(_compatIoPortBound,[Default]), UsedName(parentModName,[Default]), UsedName(getClass,[Default]), UsedName(_id,[Default]), UsedName(w4,[Default]), UsedName(mask5,[Default]), UsedName(isClosed,[Default]), UsedName($asInstanceOf,[Default]), UsedName(wait,[Default]), UsedName(suggestedName,[Default]), UsedName(getOptionRef,[Default]), UsedName(clock,[Default]), UsedName(j,[Default]), UsedName(w5,[Default]), UsedName(addId,[Default]), UsedName(toTarget,[Default]), UsedName(notifyAll,[Default]), UsedName(equals,[Default]).
-[debug] 	> by transitive inheritance: Set(lib.rvecc_encode)
+[debug] Invalidating (transitively) by inheritance from quasar_wrapper...
+[debug] Initial set of included nodes: quasar_wrapper
+[debug] Invalidated by transitive inheritance dependency: Set(quasar_wrapper)
+[debug] Change NamesChange(quasar_wrapper,ModifiedNames(changes = UsedName(dma_hsize,[Default]), UsedName(dma_axi,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(ifu_brg,[Default]), UsedName(dma_htrans,[Default]), UsedName(bridge_gen,[Default]), UsedName(lsu_axi,[Default]), UsedName(sb_brg,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_axi,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(dma_hburst,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(ifu_axi,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_brg,[Default]), UsedName(dma_hrdata,[Default]), UsedName(io,[Default]), UsedName(dma_hwrite,[Default]), UsedName(dma_brg,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]))) invalidates 1 classes due to The quasar_wrapper has the following regular definitions changed:
+[debug] 	UsedName(dma_hsize,[Default]), UsedName(dma_axi,[Default]), UsedName(dma_hreadyout,[Default]), UsedName(dma_hresp,[Default]), UsedName(ifu_brg,[Default]), UsedName(dma_htrans,[Default]), UsedName(bridge_gen,[Default]), UsedName(lsu_axi,[Default]), UsedName(sb_brg,[Default]), UsedName(dma_hsel,[Default]), UsedName(sb_axi,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(dma_hburst,[Default]), UsedName(flip,[Default]), UsedName(dma_haddr,[Default]), UsedName(ifu_axi,[Default]), UsedName(dma_hmastlock,[Default]), UsedName(lsu_brg,[Default]), UsedName(dma_hrdata,[Default]), UsedName(io,[Default]), UsedName(dma_hwrite,[Default]), UsedName(dma_brg,[Default]), UsedName(dma_hwdata,[Default]), UsedName(dma_hreadyin,[Default]), UsedName(dma_hprot,[Default]).
+[debug] 	> by transitive inheritance: Set(quasar_wrapper)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_clkdomain...
+[debug] Initial set of included nodes: lsu.lsu_clkdomain
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_clkdomain)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_clkdomain,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The lsu.lsu_clkdomain has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_clkdomain)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.read_data...
+[debug] Initial set of included nodes: include.read_data
+[debug] Invalidated by transitive inheritance dependency: Set(include.read_data)
+[debug] The following modified names cause invalidation of lib.ahb_to_axi4: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(ne,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of lib.axi4_to_ahb: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of lsu.lsu_bus_buffer: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of dbg.dbg: Set(UsedName(read_data,[Default]))
+[debug] The following modified names cause invalidation of ifu.ifu_mem_ctl: Set(UsedName(asInstanceOf,[Default]), UsedName(read_data,[Default]), UsedName(==,[Default]), UsedName(isInstanceOf,[Default]))
+[debug] The following modified names cause invalidation of dma_ctrl: Set(UsedName(read_data,[Default]), UsedName(ne,[Default]))
+[debug] Change NamesChange(include.read_data,ModifiedNames(changes = UsedName(include;read_data;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(read_data,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]))) invalidates 7 classes due to The include.read_data has the following regular definitions changed:
+[debug] 	UsedName(include;read_data;init;,[Default]), UsedName(notify,[Default]), UsedName(notifyAll,[Default]), UsedName(asInstanceOf,[Default]), UsedName(toString,[Default]), UsedName(finalize,[Default]), UsedName(!=,[Default]), UsedName(synchronized,[Default]), UsedName(wait,[Default]), UsedName(read_data,[Default]), UsedName(##,[Default]), UsedName(ne,[Default]), UsedName(equals,[Default]), UsedName(bridge_gen,[Default]), UsedName(==,[Default]), UsedName(<init>$default$1,[Default]), UsedName(isInstanceOf,[Default]), UsedName($isInstanceOf,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(hashCode,[Default]), UsedName(eq,[Default]), UsedName(clone,[Default]), UsedName(getClass,[Default]), UsedName($asInstanceOf,[Default]).
+[debug] 	> by transitive inheritance: Set(include.read_data)
+[debug] 	> 
+[debug] 	> by member reference: Set(lib.ahb_to_axi4, lib.axi4_to_ahb, lsu.lsu_bus_buffer, dbg.dbg, ifu.ifu_mem_ctl, dma_ctrl)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.write_data...
+[debug] Initial set of included nodes: include.write_data
+[debug] Invalidated by transitive inheritance dependency: Set(include.write_data)
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.write_data,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]))) invalidates 1 classes due to The include.write_data has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(bridge_gen,[Default]), UsedName(flip,[Default]).
+[debug] 	> by transitive inheritance: Set(include.write_data)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.dec_exu...
+[debug] Initial set of included nodes: include.dec_exu
+[debug] Invalidated by transitive inheritance dependency: Set(include.dec_exu)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of dec.dec. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of exu.exu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.dec_exu,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The include.dec_exu has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.dec_exu)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from ifu.ifu_ifc_ctl...
+[debug] Initial set of included nodes: ifu.ifu_ifc_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_ifc_ctl)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu_ifc_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_ifc_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.ifu_ifc_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from include.axi_channels...
+[debug] Initial set of included nodes: include.axi_channels
+[debug] Invalidated by transitive inheritance dependency: Set(include.axi_channels)
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb_IO. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.ahb_to_axi4. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lib.axi4_to_ahb. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of quasar_bundle. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.mem_ctl_io. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_buffer. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of quasar_wrapper: Set(UsedName(bridge_gen,[Default]))
+[debug] None of the modified names appears in source file of dbg.dbg. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of lsu.lsu_bus_intf. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of ifu.ifu_mem_ctl. This dependency is not being considered for invalidation.
+[debug] The following modified names cause invalidation of lib.lib: Set(UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]))
+[debug] None of the modified names appears in source file of dma_ctrl. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(include.axi_channels,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 3 classes due to The include.axi_channels has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(include.axi_channels)
+[debug] 	> 
+[debug] 	> by member reference: Set(quasar_wrapper, lib.lib)
+[debug]         
+[debug] Invalidating (transitively) by inheritance from ifu.ifu_bp_ctl...
+[debug] Initial set of included nodes: ifu.ifu_bp_ctl
+[debug] Invalidated by transitive inheritance dependency: Set(ifu.ifu_bp_ctl)
+[debug] None of the modified names appears in source file of ifu.ifu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(ifu.ifu_bp_ctl,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The ifu.ifu_bp_ctl has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(ifu.ifu_bp_ctl)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from lsu.lsu_trigger...
+[debug] Initial set of included nodes: lsu.lsu_trigger
+[debug] Invalidated by transitive inheritance dependency: Set(lsu.lsu_trigger)
+[debug] None of the modified names appears in source file of lsu.lsu. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(lsu.lsu_trigger,ModifiedNames(changes = UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]))) invalidates 1 classes due to The lsu.lsu_trigger has the following regular definitions changed:
+[debug] 	UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(bridge_gen,[Default]).
+[debug] 	> by transitive inheritance: Set(lsu.lsu_trigger)
+[debug] 	> 
+[debug] 	> 
+[debug]         
+[debug] Invalidating (transitively) by inheritance from dbg.dbg...
+[debug] Initial set of included nodes: dbg.dbg
+[debug] Invalidated by transitive inheritance dependency: Set(dbg.dbg)
+[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(dbg.dbg,ModifiedNames(changes = UsedName(dbg_dm_rst_l,[Default]), UsedName(rst_not,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(rst_temp,[Default]))) invalidates 1 classes due to The dbg.dbg has the following regular definitions changed:
+[debug] 	UsedName(dbg_dm_rst_l,[Default]), UsedName(rst_not,[Default]), UsedName(bridge_gen,[Default]), UsedName(ahb_bridge_gen,[Default]), UsedName(flip,[Default]), UsedName(rst_temp,[Default]).
+[debug] 	> by transitive inheritance: Set(dbg.dbg)
 [debug] 	> 
 [debug] 	> 
 [debug]         
 [debug] New invalidations:
-[debug] 	Set(dec.CSR_VAL)
-[debug] Initial set of included nodes: dec.CSR_VAL
+[debug] 	Set()
+[debug] Initial set of included nodes: 
 [debug] Previously invalidated, but (transitively) depend on new invalidations:
 [debug] 	Set()
 [debug] No classes were invalidated.
diff --git a/target/streams/compile/copyResources/_global/streams/copy-resources b/target/streams/compile/copyResources/_global/streams/copy-resources
index e3dbd2b7..1d20d3ea 100644
--- a/target/streams/compile/copyResources/_global/streams/copy-resources
+++ b/target/streams/compile/copyResources/_global/streams/copy-resources
@@ -1 +1 @@
-[[{"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv"]},{"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv"]}],{"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1607581553111},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv","lastModified":1607581553111}}]
\ No newline at end of file
+[[{"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv"]},{"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv"]}],{"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv","lastModified":1607928118381},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv","lastModified":1607928118381},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v","lastModified":1607928118381},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1607928118385},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1607928118381},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1607928118381},"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv","lastModified":1607928118385}}]
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs
index 45f56934..a7c00c6a 100644
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@@ -1 +1 @@
--1947755211
\ No newline at end of file
+793527455
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out
index 6243345b..2047205e 100644
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@@ -32,14 +32,10 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl.class
 [debug] 	QUASAR_Wrp$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$.class
-[debug] 	snapshot
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot
-[debug] 	snapshot/pt$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt$.class
-[debug] 	snapshot/pt.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt.class
 [debug] 	quasar_wrapper.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper.class
+[debug] 	quasar_bundle$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_bundle$$anon$1.class
 [debug] 	vsrc
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc
 [debug] 	vsrc/ifu_iccm_mem.sv
@@ -160,30 +156,34 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr.class
 [debug] 	lib/lib$rvecc_encode.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode.class
+[debug] 	lib/lib$gated_latch$$anon$4.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class
 [debug] 	lib/Config.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/Config.class
 [debug] 	lib/axi4_to_ahb_IO.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class
-[debug] 	lib/lib$gated_latch$$anon$3.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$3.class
 [debug] 	lib/lib.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib.class
+[debug] 	lib/lib$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$$anon$1.class
 [debug] 	lib/lib$rvecc_encode_64.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class
 [debug] 	lib/ahb_to_axi4.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4.class
-[debug] 	lib/lib$rvecc_encode_64$$anon$2.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$2.class
+[debug] 	lib/lib$rvecc_encode_64$$anon$3.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class
 [debug] 	lib/ahb_to_axi4$$anon$1.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class
 [debug] 	lib/lib$rvsyncss$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvsyncss$.class
 [debug] 	lib/lib$gated_latch.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch.class
-[debug] 	lib/lib$rvclkhdr$$anon$4.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$4.class
-[debug] 	lib/lib$rvecc_encode$$anon$1.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$1.class
+[debug] 	lib/ahb_to_axi4$$anon$1$$anon$2.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class
+[debug] 	lib/lib$rvclkhdr$$anon$5.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class
+[debug] 	lib/lib$rvecc_encode$$anon$2.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class
 [debug] 	lib/axi4_to_ahb.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb.class
 [debug] 	lib/param.class
@@ -242,6 +242,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_error_pkt_t.class
 [debug] 	include/read_addr.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr.class
+[debug] 	include/ahb_out_dma.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_out_dma.class
 [debug] 	include/dest_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dest_pkt_t.class
 [debug] 	include/dbg_ib.class
@@ -254,12 +256,10 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t$.class
 [debug] 	include/tlu_dma.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_dma.class
-[debug] 	include/write_addr$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr$.class
-[debug] 	include/write_resp$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp$.class
 [debug] 	include/axi_channels.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels.class
+[debug] 	include/ahb_out.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_out.class
 [debug] 	include/ic_mem.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_mem.class
 [debug] 	include/write_addr.class
@@ -296,6 +296,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_ifc.class
 [debug] 	include/ifu_dec.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dec.class
+[debug] 	include/ahb_channel.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_channel.class
 [debug] 	include/lsu_pic.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pic.class
 [debug] 	include/dctl_busbuff.class
@@ -316,14 +318,14 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pkt_t.class
 [debug] 	include/aln_ib.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_ib.class
-[debug] 	include/read_data$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data$.class
 [debug] 	include/cache_debug_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/cache_debug_pkt_t.class
 [debug] 	include/load_cam_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/load_cam_pkt_t.class
 [debug] 	include/dec_mem_ctrl.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class
+[debug] 	include/ahb_in.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_in.class
 [debug] 	include/axi_channels$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels$.class
 [debug] 	include/ic_tag_ext_in_pkt_t.class
@@ -370,8 +372,6 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/alu_pkt_t.class
 [debug] 	include/rets_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/rets_pkt_t.class
-[debug] 	include/read_addr$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr$.class
 [debug] 	dec
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec
 [debug] 	dec/dec_trigger$$anon$1.class