diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir
index 2804117d..101fc57b 100644
--- a/axi4_to_ahb.fir
+++ b/axi4_to_ahb.fir
@@ -1241,7 +1241,7 @@ circuit axi4_to_ahb :
     inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18]
     rvclkhdr_2.io.en <= _T_650 @[el2_lib.scala 511:17]
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
     reg _T_651 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
@@ -1251,7 +1251,7 @@ circuit axi4_to_ahb :
     inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18]
     rvclkhdr_3.io.en <= _T_652 @[el2_lib.scala 511:17]
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
     reg _T_653 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v
index 810dab44..1a48fee3 100644
--- a/axi4_to_ahb.v
+++ b/axi4_to_ahb.v
@@ -558,10 +558,10 @@ module axi4_to_ahb(
   assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
   assign rvclkhdr_1_io_en = io_bus_clk_en & _T_44; // @[el2_lib.scala 485:16]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
-  assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[el2_lib.scala 510:18]
   assign rvclkhdr_2_io_en = _T_42 & master_ready; // @[el2_lib.scala 511:17]
   assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
-  assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[el2_lib.scala 510:18]
   assign rvclkhdr_3_io_en = _T_43 & master_ready; // @[el2_lib.scala 511:17]
   assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
   assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala
index 3bd41ff1..efdfaa97 100644
--- a/src/main/scala/lib/axi4_to_ahb.scala
+++ b/src/main/scala/lib/axi4_to_ahb.scala
@@ -385,8 +385,8 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
   wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())}
   wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())}
   //rvdffe
-  wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,clock,io.scan_mode)
-  wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,clock,io.scan_mode)
+  wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,bus_clk,io.scan_mode)
+  wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,bus_clk,io.scan_mode)
   //rvdffs
   wrbuf_byteen := withClock(bus_clk) {
     RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())
diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class
index a8e9bd07..b5fa9cc6 100644
Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb.class and b/target/scala-2.12/classes/lib/axi4_to_ahb.class differ