From 5862a40dcdcb94bd0df67584928e7e21b609fc19 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 8 Oct 2020 12:38:19 +0500 Subject: [PATCH] Write fixed --- el2_ifu_iccm_mem.fir | 984 +++++++++--------- el2_ifu_iccm_mem.v | 770 +++++++------- src/main/scala/ifu/el2_ifu_iccm_mem.scala | 8 +- .../classes/ifu/el2_ifu_iccm_mem.class | Bin 93360 -> 94300 bytes target/scala-2.12/classes/ifu/ifu_iccm$.class | Bin 3883 -> 3884 bytes .../ifu/ifu_iccm$delayedInit$body.class | Bin 743 -> 743 bytes 6 files changed, 866 insertions(+), 896 deletions(-) diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir index 08ba1903..0dc01fc2 100644 --- a/el2_ifu_iccm_mem.fir +++ b/el2_ifu_iccm_mem.fir @@ -47,38 +47,38 @@ circuit el2_ifu_iccm_mem : node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140] node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107] node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64] - node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] - node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:99] - node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 36:64] - node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:139] - node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 36:106] - node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:99] - node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 36:64] - node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] - node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:139] - node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 36:106] - node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] - node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:99] - node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 36:64] - node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] - node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:139] - node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 36:106] - node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] - node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:99] - node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 36:64] - node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] - node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:139] - node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 36:106] - node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 37:72] - node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] - node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 37:72] - node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] - node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 37:72] - node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] - node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 37:72] - node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] + node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99] + node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64] + node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139] + node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106] + node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99] + node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64] + node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] + node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139] + node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106] + node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] + node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99] + node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64] + node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] + node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139] + node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106] + node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] + node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99] + node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64] + node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] + node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139] + node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106] + node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72] + node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] + node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72] + node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] + node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72] + node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] + node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72] + node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] @@ -136,498 +136,466 @@ circuit el2_ifu_iccm_mem : read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53] wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28] wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19] - write mport _T_93 = iccm_mem[addr_bank_0], clock - when write_vec[0] : - _T_93[0] <= iccm_bank_wr_data[0] - skip - when write_vec[1] : - _T_93[1] <= iccm_bank_wr_data[1] - skip - when write_vec[2] : - _T_93[2] <= iccm_bank_wr_data[2] - skip - when write_vec[3] : - _T_93[3] <= iccm_bank_wr_data[3] - skip - write mport _T_94 = iccm_mem[addr_bank_1], clock - when write_vec[0] : - _T_94[0] <= iccm_bank_wr_data[0] - skip - when write_vec[1] : - _T_94[1] <= iccm_bank_wr_data[1] - skip - when write_vec[2] : - _T_94[2] <= iccm_bank_wr_data[2] - skip - when write_vec[3] : - _T_94[3] <= iccm_bank_wr_data[3] - skip - write mport _T_95 = iccm_mem[addr_bank_2], clock - when write_vec[0] : - _T_95[0] <= iccm_bank_wr_data[0] - skip - when write_vec[1] : - _T_95[1] <= iccm_bank_wr_data[1] - skip - when write_vec[2] : - _T_95[2] <= iccm_bank_wr_data[2] - skip - when write_vec[3] : - _T_95[3] <= iccm_bank_wr_data[3] - skip - write mport _T_96 = iccm_mem[addr_bank_3], clock - when write_vec[0] : - _T_96[0] <= iccm_bank_wr_data[0] - skip - when write_vec[1] : - _T_96[1] <= iccm_bank_wr_data[1] - skip - when write_vec[2] : - _T_96[2] <= iccm_bank_wr_data[2] - skip - when write_vec[3] : - _T_96[3] <= iccm_bank_wr_data[3] - skip - node _T_97 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15] - node _T_98 = mux(_T_97, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] - infer mport _T_99 = iccm_mem[UInt<1>("h00")], clock @[el2_ifu_iccm_mem.scala 49:77] - node _T_100 = bits(addr_bank_0, 1, 0) - node _T_101 = and(_T_98, _T_99[_T_100]) @[el2_ifu_iccm_mem.scala 49:67] - node _T_102 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15] - node _T_103 = mux(_T_102, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] - infer mport _T_104 = iccm_mem[UInt<1>("h01")], clock @[el2_ifu_iccm_mem.scala 49:77] - node _T_105 = bits(addr_bank_1, 1, 0) - node _T_106 = and(_T_103, _T_104[_T_105]) @[el2_ifu_iccm_mem.scala 49:67] - node _T_107 = bits(read_enable[2], 0, 0) @[Bitwise.scala 72:15] - node _T_108 = mux(_T_107, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] - infer mport _T_109 = iccm_mem[UInt<2>("h02")], clock @[el2_ifu_iccm_mem.scala 49:77] - node _T_110 = bits(addr_bank_2, 1, 0) - node _T_111 = and(_T_108, _T_109[_T_110]) @[el2_ifu_iccm_mem.scala 49:67] - node _T_112 = bits(read_enable[3], 0, 0) @[Bitwise.scala 72:15] - node _T_113 = mux(_T_112, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] - infer mport _T_114 = iccm_mem[UInt<2>("h03")], clock @[el2_ifu_iccm_mem.scala 49:77] - node _T_115 = bits(addr_bank_3, 1, 0) - node _T_116 = and(_T_113, _T_114[_T_115]) @[el2_ifu_iccm_mem.scala 49:67] - inter[0] <= _T_101 @[el2_ifu_iccm_mem.scala 49:9] - inter[1] <= _T_106 @[el2_ifu_iccm_mem.scala 49:9] - inter[2] <= _T_111 @[el2_ifu_iccm_mem.scala 49:9] - inter[3] <= _T_116 @[el2_ifu_iccm_mem.scala 49:9] - reg _T_117 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] - _T_117 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62] - iccm_bank_dout[0] <= _T_117 @[el2_ifu_iccm_mem.scala 50:52] - reg _T_118 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] - _T_118 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62] - iccm_bank_dout[1] <= _T_118 @[el2_ifu_iccm_mem.scala 50:52] - reg _T_119 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] - _T_119 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62] - iccm_bank_dout[2] <= _T_119 @[el2_ifu_iccm_mem.scala 50:52] - reg _T_120 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] - _T_120 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62] - iccm_bank_dout[3] <= _T_120 @[el2_ifu_iccm_mem.scala 50:52] - io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 52:21] - io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 52:21] - io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 52:21] - io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 52:21] + node _T_93 = bits(write_vec[0], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] + when _T_93 : @[el2_ifu_iccm_mem.scala 49:60] + infer mport _T_94 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:69] + _T_94[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 49:87] + skip @[el2_ifu_iccm_mem.scala 49:60] + node _T_95 = bits(write_vec[1], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] + when _T_95 : @[el2_ifu_iccm_mem.scala 49:60] + infer mport _T_96 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 49:69] + _T_96[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 49:87] + skip @[el2_ifu_iccm_mem.scala 49:60] + node _T_97 = bits(write_vec[2], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] + when _T_97 : @[el2_ifu_iccm_mem.scala 49:60] + infer mport _T_98 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 49:69] + _T_98[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 49:87] + skip @[el2_ifu_iccm_mem.scala 49:60] + node _T_99 = bits(write_vec[3], 0, 0) @[el2_ifu_iccm_mem.scala 49:53] + when _T_99 : @[el2_ifu_iccm_mem.scala 49:60] + infer mport _T_100 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 49:69] + _T_100[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 49:87] + skip @[el2_ifu_iccm_mem.scala 49:60] + node _T_101 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15] + node _T_102 = mux(_T_101, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] + infer mport _T_103 = iccm_mem[UInt<1>("h00")], clock @[el2_ifu_iccm_mem.scala 51:77] + node _T_104 = bits(addr_bank_0, 1, 0) + node _T_105 = and(_T_102, _T_103[_T_104]) @[el2_ifu_iccm_mem.scala 51:67] + node _T_106 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15] + node _T_107 = mux(_T_106, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] + infer mport _T_108 = iccm_mem[UInt<1>("h01")], clock @[el2_ifu_iccm_mem.scala 51:77] + node _T_109 = bits(addr_bank_1, 1, 0) + node _T_110 = and(_T_107, _T_108[_T_109]) @[el2_ifu_iccm_mem.scala 51:67] + node _T_111 = bits(read_enable[2], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] + infer mport _T_113 = iccm_mem[UInt<2>("h02")], clock @[el2_ifu_iccm_mem.scala 51:77] + node _T_114 = bits(addr_bank_2, 1, 0) + node _T_115 = and(_T_112, _T_113[_T_114]) @[el2_ifu_iccm_mem.scala 51:67] + node _T_116 = bits(read_enable[3], 0, 0) @[Bitwise.scala 72:15] + node _T_117 = mux(_T_116, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12] + infer mport _T_118 = iccm_mem[UInt<2>("h03")], clock @[el2_ifu_iccm_mem.scala 51:77] + node _T_119 = bits(addr_bank_3, 1, 0) + node _T_120 = and(_T_117, _T_118[_T_119]) @[el2_ifu_iccm_mem.scala 51:67] + inter[0] <= _T_105 @[el2_ifu_iccm_mem.scala 51:9] + inter[1] <= _T_110 @[el2_ifu_iccm_mem.scala 51:9] + inter[2] <= _T_115 @[el2_ifu_iccm_mem.scala 51:9] + inter[3] <= _T_120 @[el2_ifu_iccm_mem.scala 51:9] + reg _T_121 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62] + _T_121 <= inter[0] @[el2_ifu_iccm_mem.scala 52:62] + iccm_bank_dout[0] <= _T_121 @[el2_ifu_iccm_mem.scala 52:52] + reg _T_122 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62] + _T_122 <= inter[1] @[el2_ifu_iccm_mem.scala 52:62] + iccm_bank_dout[1] <= _T_122 @[el2_ifu_iccm_mem.scala 52:52] + reg _T_123 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62] + _T_123 <= inter[2] @[el2_ifu_iccm_mem.scala 52:62] + iccm_bank_dout[2] <= _T_123 @[el2_ifu_iccm_mem.scala 52:52] + reg _T_124 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62] + _T_124 <= inter[3] @[el2_ifu_iccm_mem.scala 52:62] + iccm_bank_dout[3] <= _T_124 @[el2_ifu_iccm_mem.scala 52:52] + io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 54:21] + io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 54:21] + io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 54:21] + io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 54:21] wire redundant_valid : UInt<2> redundant_valid <= UInt<1>("h00") - wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 58:31] - redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 59:21] - redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 59:21] - node _T_121 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67] - node _T_122 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90] - node _T_123 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128] - node _T_124 = eq(_T_122, _T_123) @[el2_ifu_iccm_mem.scala 61:105] - node _T_125 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 61:169] - node _T_127 = and(_T_124, _T_126) @[el2_ifu_iccm_mem.scala 61:145] - node _T_128 = and(_T_121, _T_127) @[el2_ifu_iccm_mem.scala 61:71] - node _T_129 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22] - node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60] - node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 62:37] - node _T_132 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93] - node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 62:99] - node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 62:77] - node _T_135 = or(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 61:179] - node _T_136 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67] - node _T_137 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90] - node _T_138 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128] - node _T_139 = eq(_T_137, _T_138) @[el2_ifu_iccm_mem.scala 61:105] - node _T_140 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163] - node _T_141 = eq(_T_140, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 61:169] - node _T_142 = and(_T_139, _T_141) @[el2_ifu_iccm_mem.scala 61:145] - node _T_143 = and(_T_136, _T_142) @[el2_ifu_iccm_mem.scala 61:71] - node _T_144 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22] - node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60] - node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 62:37] - node _T_147 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93] - node _T_148 = eq(_T_147, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 62:99] - node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 62:77] - node _T_150 = or(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 61:179] - node _T_151 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67] - node _T_152 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90] - node _T_153 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128] - node _T_154 = eq(_T_152, _T_153) @[el2_ifu_iccm_mem.scala 61:105] - node _T_155 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163] - node _T_156 = eq(_T_155, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 61:169] - node _T_157 = and(_T_154, _T_156) @[el2_ifu_iccm_mem.scala 61:145] - node _T_158 = and(_T_151, _T_157) @[el2_ifu_iccm_mem.scala 61:71] - node _T_159 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22] - node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60] - node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 62:37] - node _T_162 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93] - node _T_163 = eq(_T_162, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 62:99] - node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 62:77] - node _T_165 = or(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 61:179] - node _T_166 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67] - node _T_167 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90] - node _T_168 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128] - node _T_169 = eq(_T_167, _T_168) @[el2_ifu_iccm_mem.scala 61:105] - node _T_170 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163] - node _T_171 = eq(_T_170, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 61:169] - node _T_172 = and(_T_169, _T_171) @[el2_ifu_iccm_mem.scala 61:145] - node _T_173 = and(_T_166, _T_172) @[el2_ifu_iccm_mem.scala 61:71] - node _T_174 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22] - node _T_175 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60] - node _T_176 = eq(_T_174, _T_175) @[el2_ifu_iccm_mem.scala 62:37] - node _T_177 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93] - node _T_178 = eq(_T_177, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 62:99] - node _T_179 = and(_T_176, _T_178) @[el2_ifu_iccm_mem.scala 62:77] - node _T_180 = or(_T_173, _T_179) @[el2_ifu_iccm_mem.scala 61:179] - node _T_181 = cat(_T_180, _T_165) @[Cat.scala 29:58] - node _T_182 = cat(_T_181, _T_150) @[Cat.scala 29:58] - node sel_red1 = cat(_T_182, _T_135) @[Cat.scala 29:58] - node _T_183 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67] - node _T_184 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] - node _T_185 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] - node _T_186 = eq(_T_184, _T_185) @[el2_ifu_iccm_mem.scala 63:105] - node _T_187 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] - node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 63:169] - node _T_189 = and(_T_186, _T_188) @[el2_ifu_iccm_mem.scala 63:145] - node _T_190 = and(_T_183, _T_189) @[el2_ifu_iccm_mem.scala 63:71] - node _T_191 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] - node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] - node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 64:37] - node _T_194 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] - node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 64:99] - node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 64:77] - node _T_197 = or(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 63:179] - node _T_198 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67] - node _T_199 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] - node _T_200 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] - node _T_201 = eq(_T_199, _T_200) @[el2_ifu_iccm_mem.scala 63:105] - node _T_202 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] - node _T_203 = eq(_T_202, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 63:169] - node _T_204 = and(_T_201, _T_203) @[el2_ifu_iccm_mem.scala 63:145] - node _T_205 = and(_T_198, _T_204) @[el2_ifu_iccm_mem.scala 63:71] - node _T_206 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] - node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] - node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 64:37] - node _T_209 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] - node _T_210 = eq(_T_209, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 64:99] - node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 64:77] - node _T_212 = or(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 63:179] - node _T_213 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67] - node _T_214 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] - node _T_215 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] - node _T_216 = eq(_T_214, _T_215) @[el2_ifu_iccm_mem.scala 63:105] - node _T_217 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] - node _T_218 = eq(_T_217, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 63:169] - node _T_219 = and(_T_216, _T_218) @[el2_ifu_iccm_mem.scala 63:145] - node _T_220 = and(_T_213, _T_219) @[el2_ifu_iccm_mem.scala 63:71] - node _T_221 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] - node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] - node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 64:37] - node _T_224 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] - node _T_225 = eq(_T_224, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 64:99] - node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 64:77] - node _T_227 = or(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 63:179] - node _T_228 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67] - node _T_229 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] - node _T_230 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] - node _T_231 = eq(_T_229, _T_230) @[el2_ifu_iccm_mem.scala 63:105] - node _T_232 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] - node _T_233 = eq(_T_232, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 63:169] - node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 63:145] - node _T_235 = and(_T_228, _T_234) @[el2_ifu_iccm_mem.scala 63:71] - node _T_236 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] - node _T_237 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] - node _T_238 = eq(_T_236, _T_237) @[el2_ifu_iccm_mem.scala 64:37] - node _T_239 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] - node _T_240 = eq(_T_239, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 64:99] - node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 64:77] - node _T_242 = or(_T_235, _T_241) @[el2_ifu_iccm_mem.scala 63:179] - node _T_243 = cat(_T_242, _T_227) @[Cat.scala 29:58] - node _T_244 = cat(_T_243, _T_212) @[Cat.scala 29:58] - node sel_red0 = cat(_T_244, _T_197) @[Cat.scala 29:58] - reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 66:27] - sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 66:27] - reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 67:27] - sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 67:27] - wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 68:28] - redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 69:18] - redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 69:18] - node _T_245 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 71:47] - node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 71:51] - node _T_247 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 72:47] - node _T_248 = bits(_T_247, 0, 0) @[el2_ifu_iccm_mem.scala 72:51] - node _T_249 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:47] - node _T_250 = not(_T_249) @[el2_ifu_iccm_mem.scala 73:36] - node _T_251 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:64] - node _T_252 = not(_T_251) @[el2_ifu_iccm_mem.scala 73:53] - node _T_253 = and(_T_250, _T_252) @[el2_ifu_iccm_mem.scala 73:51] - node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_iccm_mem.scala 73:69] - node _T_255 = mux(_T_246, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_256 = mux(_T_248, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_257 = mux(_T_254, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72] - node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72] + wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 60:31] + redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21] + redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21] + node _T_125 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67] + node _T_126 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] + node _T_127 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] + node _T_128 = eq(_T_126, _T_127) @[el2_ifu_iccm_mem.scala 63:105] + node _T_129 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 63:169] + node _T_131 = and(_T_128, _T_130) @[el2_ifu_iccm_mem.scala 63:145] + node _T_132 = and(_T_125, _T_131) @[el2_ifu_iccm_mem.scala 63:71] + node _T_133 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] + node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] + node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 64:37] + node _T_136 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 64:99] + node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 64:77] + node _T_139 = or(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 63:179] + node _T_140 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67] + node _T_141 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] + node _T_142 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] + node _T_143 = eq(_T_141, _T_142) @[el2_ifu_iccm_mem.scala 63:105] + node _T_144 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] + node _T_145 = eq(_T_144, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 63:169] + node _T_146 = and(_T_143, _T_145) @[el2_ifu_iccm_mem.scala 63:145] + node _T_147 = and(_T_140, _T_146) @[el2_ifu_iccm_mem.scala 63:71] + node _T_148 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] + node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] + node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 64:37] + node _T_151 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] + node _T_152 = eq(_T_151, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 64:99] + node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 64:77] + node _T_154 = or(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 63:179] + node _T_155 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67] + node _T_156 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] + node _T_157 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] + node _T_158 = eq(_T_156, _T_157) @[el2_ifu_iccm_mem.scala 63:105] + node _T_159 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] + node _T_160 = eq(_T_159, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 63:169] + node _T_161 = and(_T_158, _T_160) @[el2_ifu_iccm_mem.scala 63:145] + node _T_162 = and(_T_155, _T_161) @[el2_ifu_iccm_mem.scala 63:71] + node _T_163 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] + node _T_164 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] + node _T_165 = eq(_T_163, _T_164) @[el2_ifu_iccm_mem.scala 64:37] + node _T_166 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] + node _T_167 = eq(_T_166, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 64:99] + node _T_168 = and(_T_165, _T_167) @[el2_ifu_iccm_mem.scala 64:77] + node _T_169 = or(_T_162, _T_168) @[el2_ifu_iccm_mem.scala 63:179] + node _T_170 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67] + node _T_171 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90] + node _T_172 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128] + node _T_173 = eq(_T_171, _T_172) @[el2_ifu_iccm_mem.scala 63:105] + node _T_174 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163] + node _T_175 = eq(_T_174, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 63:169] + node _T_176 = and(_T_173, _T_175) @[el2_ifu_iccm_mem.scala 63:145] + node _T_177 = and(_T_170, _T_176) @[el2_ifu_iccm_mem.scala 63:71] + node _T_178 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22] + node _T_179 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60] + node _T_180 = eq(_T_178, _T_179) @[el2_ifu_iccm_mem.scala 64:37] + node _T_181 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93] + node _T_182 = eq(_T_181, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 64:99] + node _T_183 = and(_T_180, _T_182) @[el2_ifu_iccm_mem.scala 64:77] + node _T_184 = or(_T_177, _T_183) @[el2_ifu_iccm_mem.scala 63:179] + node _T_185 = cat(_T_184, _T_169) @[Cat.scala 29:58] + node _T_186 = cat(_T_185, _T_154) @[Cat.scala 29:58] + node sel_red1 = cat(_T_186, _T_139) @[Cat.scala 29:58] + node _T_187 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67] + node _T_188 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] + node _T_189 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] + node _T_190 = eq(_T_188, _T_189) @[el2_ifu_iccm_mem.scala 65:105] + node _T_191 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169] + node _T_193 = and(_T_190, _T_192) @[el2_ifu_iccm_mem.scala 65:145] + node _T_194 = and(_T_187, _T_193) @[el2_ifu_iccm_mem.scala 65:71] + node _T_195 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] + node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] + node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 66:37] + node _T_198 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99] + node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 66:77] + node _T_201 = or(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 65:179] + node _T_202 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67] + node _T_203 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] + node _T_204 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] + node _T_205 = eq(_T_203, _T_204) @[el2_ifu_iccm_mem.scala 65:105] + node _T_206 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] + node _T_207 = eq(_T_206, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169] + node _T_208 = and(_T_205, _T_207) @[el2_ifu_iccm_mem.scala 65:145] + node _T_209 = and(_T_202, _T_208) @[el2_ifu_iccm_mem.scala 65:71] + node _T_210 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] + node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] + node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 66:37] + node _T_213 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] + node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99] + node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 66:77] + node _T_216 = or(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 65:179] + node _T_217 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67] + node _T_218 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] + node _T_219 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] + node _T_220 = eq(_T_218, _T_219) @[el2_ifu_iccm_mem.scala 65:105] + node _T_221 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] + node _T_222 = eq(_T_221, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169] + node _T_223 = and(_T_220, _T_222) @[el2_ifu_iccm_mem.scala 65:145] + node _T_224 = and(_T_217, _T_223) @[el2_ifu_iccm_mem.scala 65:71] + node _T_225 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] + node _T_226 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] + node _T_227 = eq(_T_225, _T_226) @[el2_ifu_iccm_mem.scala 66:37] + node _T_228 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] + node _T_229 = eq(_T_228, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99] + node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 66:77] + node _T_231 = or(_T_224, _T_230) @[el2_ifu_iccm_mem.scala 65:179] + node _T_232 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67] + node _T_233 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90] + node _T_234 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128] + node _T_235 = eq(_T_233, _T_234) @[el2_ifu_iccm_mem.scala 65:105] + node _T_236 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163] + node _T_237 = eq(_T_236, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169] + node _T_238 = and(_T_235, _T_237) @[el2_ifu_iccm_mem.scala 65:145] + node _T_239 = and(_T_232, _T_238) @[el2_ifu_iccm_mem.scala 65:71] + node _T_240 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22] + node _T_241 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60] + node _T_242 = eq(_T_240, _T_241) @[el2_ifu_iccm_mem.scala 66:37] + node _T_243 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93] + node _T_244 = eq(_T_243, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99] + node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 66:77] + node _T_246 = or(_T_239, _T_245) @[el2_ifu_iccm_mem.scala 65:179] + node _T_247 = cat(_T_246, _T_231) @[Cat.scala 29:58] + node _T_248 = cat(_T_247, _T_216) @[Cat.scala 29:58] + node sel_red0 = cat(_T_248, _T_201) @[Cat.scala 29:58] + reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 68:27] + sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 68:27] + reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 69:27] + sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 69:27] + wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 70:28] + redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18] + redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18] + node _T_249 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:47] + node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 73:51] + node _T_251 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 74:47] + node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_iccm_mem.scala 74:51] + node _T_253 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47] + node _T_254 = not(_T_253) @[el2_ifu_iccm_mem.scala 75:36] + node _T_255 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:64] + node _T_256 = not(_T_255) @[el2_ifu_iccm_mem.scala 75:53] + node _T_257 = and(_T_254, _T_256) @[el2_ifu_iccm_mem.scala 75:51] + node _T_258 = bits(_T_257, 0, 0) @[el2_ifu_iccm_mem.scala 75:69] + node _T_259 = mux(_T_250, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_260 = mux(_T_252, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72] wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_0 <= _T_259 @[Mux.scala 27:72] - node _T_260 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 71:47] - node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 71:51] - node _T_262 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 72:47] - node _T_263 = bits(_T_262, 0, 0) @[el2_ifu_iccm_mem.scala 72:51] - node _T_264 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:47] - node _T_265 = not(_T_264) @[el2_ifu_iccm_mem.scala 73:36] - node _T_266 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:64] - node _T_267 = not(_T_266) @[el2_ifu_iccm_mem.scala 73:53] - node _T_268 = and(_T_265, _T_267) @[el2_ifu_iccm_mem.scala 73:51] - node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_iccm_mem.scala 73:69] - node _T_270 = mux(_T_261, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_271 = mux(_T_263, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_272 = mux(_T_269, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_273 = or(_T_270, _T_271) @[Mux.scala 27:72] - node _T_274 = or(_T_273, _T_272) @[Mux.scala 27:72] + iccm_bank_dout_fn_0 <= _T_263 @[Mux.scala 27:72] + node _T_264 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:47] + node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 73:51] + node _T_266 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 74:47] + node _T_267 = bits(_T_266, 0, 0) @[el2_ifu_iccm_mem.scala 74:51] + node _T_268 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47] + node _T_269 = not(_T_268) @[el2_ifu_iccm_mem.scala 75:36] + node _T_270 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:64] + node _T_271 = not(_T_270) @[el2_ifu_iccm_mem.scala 75:53] + node _T_272 = and(_T_269, _T_271) @[el2_ifu_iccm_mem.scala 75:51] + node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_iccm_mem.scala 75:69] + node _T_274 = mux(_T_265, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_275 = mux(_T_267, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_276 = mux(_T_273, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = or(_T_274, _T_275) @[Mux.scala 27:72] + node _T_278 = or(_T_277, _T_276) @[Mux.scala 27:72] wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_1 <= _T_274 @[Mux.scala 27:72] - node _T_275 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 71:47] - node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 71:51] - node _T_277 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 72:47] - node _T_278 = bits(_T_277, 0, 0) @[el2_ifu_iccm_mem.scala 72:51] - node _T_279 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:47] - node _T_280 = not(_T_279) @[el2_ifu_iccm_mem.scala 73:36] - node _T_281 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:64] - node _T_282 = not(_T_281) @[el2_ifu_iccm_mem.scala 73:53] - node _T_283 = and(_T_280, _T_282) @[el2_ifu_iccm_mem.scala 73:51] - node _T_284 = bits(_T_283, 0, 0) @[el2_ifu_iccm_mem.scala 73:69] - node _T_285 = mux(_T_276, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_286 = mux(_T_278, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_287 = mux(_T_284, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_288 = or(_T_285, _T_286) @[Mux.scala 27:72] - node _T_289 = or(_T_288, _T_287) @[Mux.scala 27:72] + iccm_bank_dout_fn_1 <= _T_278 @[Mux.scala 27:72] + node _T_279 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:47] + node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 73:51] + node _T_281 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 74:47] + node _T_282 = bits(_T_281, 0, 0) @[el2_ifu_iccm_mem.scala 74:51] + node _T_283 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47] + node _T_284 = not(_T_283) @[el2_ifu_iccm_mem.scala 75:36] + node _T_285 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:64] + node _T_286 = not(_T_285) @[el2_ifu_iccm_mem.scala 75:53] + node _T_287 = and(_T_284, _T_286) @[el2_ifu_iccm_mem.scala 75:51] + node _T_288 = bits(_T_287, 0, 0) @[el2_ifu_iccm_mem.scala 75:69] + node _T_289 = mux(_T_280, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_290 = mux(_T_282, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_291 = mux(_T_288, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_292 = or(_T_289, _T_290) @[Mux.scala 27:72] + node _T_293 = or(_T_292, _T_291) @[Mux.scala 27:72] wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_2 <= _T_289 @[Mux.scala 27:72] - node _T_290 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 71:47] - node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 71:51] - node _T_292 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 72:47] - node _T_293 = bits(_T_292, 0, 0) @[el2_ifu_iccm_mem.scala 72:51] - node _T_294 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:47] - node _T_295 = not(_T_294) @[el2_ifu_iccm_mem.scala 73:36] - node _T_296 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:64] - node _T_297 = not(_T_296) @[el2_ifu_iccm_mem.scala 73:53] - node _T_298 = and(_T_295, _T_297) @[el2_ifu_iccm_mem.scala 73:51] - node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_iccm_mem.scala 73:69] - node _T_300 = mux(_T_291, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_301 = mux(_T_293, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_302 = mux(_T_299, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_303 = or(_T_300, _T_301) @[Mux.scala 27:72] - node _T_304 = or(_T_303, _T_302) @[Mux.scala 27:72] + iccm_bank_dout_fn_2 <= _T_293 @[Mux.scala 27:72] + node _T_294 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:47] + node _T_295 = bits(_T_294, 0, 0) @[el2_ifu_iccm_mem.scala 73:51] + node _T_296 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 74:47] + node _T_297 = bits(_T_296, 0, 0) @[el2_ifu_iccm_mem.scala 74:51] + node _T_298 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47] + node _T_299 = not(_T_298) @[el2_ifu_iccm_mem.scala 75:36] + node _T_300 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:64] + node _T_301 = not(_T_300) @[el2_ifu_iccm_mem.scala 75:53] + node _T_302 = and(_T_299, _T_301) @[el2_ifu_iccm_mem.scala 75:51] + node _T_303 = bits(_T_302, 0, 0) @[el2_ifu_iccm_mem.scala 75:69] + node _T_304 = mux(_T_295, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_305 = mux(_T_297, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_306 = mux(_T_303, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_307 = or(_T_304, _T_305) @[Mux.scala 27:72] + node _T_308 = or(_T_307, _T_306) @[Mux.scala 27:72] wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_3 <= _T_304 @[Mux.scala 27:72] + iccm_bank_dout_fn_3 <= _T_308 @[Mux.scala 27:72] wire redundant_lru : UInt<1> redundant_lru <= UInt<1>("h00") - node _T_305 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 75:20] - node r0_addr_en = and(_T_305, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 75:35] - node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 76:35] - node _T_306 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 77:63] - node _T_307 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 77:78] - node _T_308 = or(_T_306, _T_307) @[el2_ifu_iccm_mem.scala 77:67] - node _T_309 = and(_T_308, io.iccm_rden) @[el2_ifu_iccm_mem.scala 77:83] - node _T_310 = and(_T_309, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 77:98] - node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_310) @[el2_ifu_iccm_mem.scala 77:50] - node _T_311 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:55] - node _T_312 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 78:84] - node _T_313 = mux(_T_312, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:74] - node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_311, _T_313) @[el2_ifu_iccm_mem.scala 78:29] - reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_309 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 77:20] + node r0_addr_en = and(_T_309, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 77:35] + node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:35] + node _T_310 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 79:63] + node _T_311 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 79:78] + node _T_312 = or(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 79:67] + node _T_313 = and(_T_312, io.iccm_rden) @[el2_ifu_iccm_mem.scala 79:83] + node _T_314 = and(_T_313, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 79:98] + node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_314) @[el2_ifu_iccm_mem.scala 79:50] + node _T_315 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:55] + node _T_316 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 80:84] + node _T_317 = mux(_T_316, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:74] + node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_315, _T_317) @[el2_ifu_iccm_mem.scala 80:29] + reg _T_318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when redundant_lru_en : @[Reg.scala 28:19] - _T_314 <= redundant_lru_in @[Reg.scala 28:23] + _T_318 <= redundant_lru_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_lru <= _T_314 @[el2_ifu_iccm_mem.scala 79:17] - node _T_315 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 80:52] - reg _T_316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + redundant_lru <= _T_318 @[el2_ifu_iccm_mem.scala 81:17] + node _T_319 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 82:52] + reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_316 <= _T_315 @[Reg.scala 28:23] + _T_320 <= _T_319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[0] <= _T_316 @[el2_ifu_iccm_mem.scala 80:24] - node _T_317 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 81:52] - node _T_318 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 81:85] - reg _T_319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_318 : @[Reg.scala 28:19] - _T_319 <= _T_317 @[Reg.scala 28:23] + redundant_address[0] <= _T_320 @[el2_ifu_iccm_mem.scala 82:24] + node _T_321 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 83:52] + node _T_322 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 83:85] + reg _T_323 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_322 : @[Reg.scala 28:19] + _T_323 <= _T_321 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[1] <= _T_319 @[el2_ifu_iccm_mem.scala 81:24] - node _T_320 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 82:57] - reg _T_321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_320 : @[Reg.scala 28:19] - _T_321 <= UInt<1>("h01") @[Reg.scala 28:23] + redundant_address[1] <= _T_323 @[el2_ifu_iccm_mem.scala 83:24] + node _T_324 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:57] + reg _T_325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_324 : @[Reg.scala 28:19] + _T_325 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg _T_322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_326 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_322 <= UInt<1>("h01") @[Reg.scala 28:23] + _T_326 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_323 = cat(_T_321, _T_322) @[Cat.scala 29:58] - redundant_valid <= _T_323 @[el2_ifu_iccm_mem.scala 82:19] - node _T_324 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 84:45] - node _T_325 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 84:85] - node _T_326 = eq(_T_324, _T_325) @[el2_ifu_iccm_mem.scala 84:61] - node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 85:22] - node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 85:48] - node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 85:26] - node _T_330 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 85:70] - node _T_331 = eq(_T_330, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 85:75] - node _T_332 = or(_T_329, _T_331) @[el2_ifu_iccm_mem.scala 85:52] - node _T_333 = and(_T_326, _T_332) @[el2_ifu_iccm_mem.scala 84:102] - node _T_334 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 85:101] - node _T_335 = and(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 85:84] - node _T_336 = and(_T_335, io.iccm_wren) @[el2_ifu_iccm_mem.scala 85:105] - node _T_337 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 86:6] - node _T_338 = and(_T_337, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 86:21] - node redundant_data0_en = or(_T_336, _T_338) @[el2_ifu_iccm_mem.scala 85:121] - node _T_339 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:49] - node _T_340 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:73] - node _T_341 = and(_T_339, _T_340) @[el2_ifu_iccm_mem.scala 87:52] - node _T_342 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:100] - node _T_343 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:122] - node _T_344 = eq(_T_343, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:127] - node _T_345 = and(_T_342, _T_344) @[el2_ifu_iccm_mem.scala 87:104] - node _T_346 = or(_T_341, _T_345) @[el2_ifu_iccm_mem.scala 87:78] - node _T_347 = bits(_T_346, 0, 0) @[el2_ifu_iccm_mem.scala 87:137] - node _T_348 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 88:20] - node _T_349 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 88:44] - node redundant_data0_in = mux(_T_347, _T_348, _T_349) @[el2_ifu_iccm_mem.scala 87:31] - node _T_350 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 89:78] - reg _T_351 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_350 : @[Reg.scala 28:19] - _T_351 <= redundant_data0_in @[Reg.scala 28:23] + node _T_327 = cat(_T_325, _T_326) @[Cat.scala 29:58] + redundant_valid <= _T_327 @[el2_ifu_iccm_mem.scala 84:19] + node _T_328 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45] + node _T_329 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 86:85] + node _T_330 = eq(_T_328, _T_329) @[el2_ifu_iccm_mem.scala 86:61] + node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22] + node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:48] + node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 87:26] + node _T_334 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70] + node _T_335 = eq(_T_334, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75] + node _T_336 = or(_T_333, _T_335) @[el2_ifu_iccm_mem.scala 87:52] + node _T_337 = and(_T_330, _T_336) @[el2_ifu_iccm_mem.scala 86:102] + node _T_338 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 87:101] + node _T_339 = and(_T_337, _T_338) @[el2_ifu_iccm_mem.scala 87:84] + node _T_340 = and(_T_339, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105] + node _T_341 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6] + node _T_342 = and(_T_341, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21] + node redundant_data0_en = or(_T_340, _T_342) @[el2_ifu_iccm_mem.scala 87:121] + node _T_343 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49] + node _T_344 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:73] + node _T_345 = and(_T_343, _T_344) @[el2_ifu_iccm_mem.scala 89:52] + node _T_346 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:100] + node _T_347 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122] + node _T_348 = eq(_T_347, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127] + node _T_349 = and(_T_346, _T_348) @[el2_ifu_iccm_mem.scala 89:104] + node _T_350 = or(_T_345, _T_349) @[el2_ifu_iccm_mem.scala 89:78] + node _T_351 = bits(_T_350, 0, 0) @[el2_ifu_iccm_mem.scala 89:137] + node _T_352 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20] + node _T_353 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44] + node redundant_data0_in = mux(_T_351, _T_352, _T_353) @[el2_ifu_iccm_mem.scala 89:31] + node _T_354 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78] + reg _T_355 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_354 : @[Reg.scala 28:19] + _T_355 <= redundant_data0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[0] <= _T_351 @[el2_ifu_iccm_mem.scala 89:21] - node _T_352 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 91:45] - node _T_353 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 91:85] - node _T_354 = eq(_T_352, _T_353) @[el2_ifu_iccm_mem.scala 91:61] - node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 92:22] - node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 92:48] - node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 92:26] - node _T_358 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 92:70] - node _T_359 = eq(_T_358, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 92:75] - node _T_360 = or(_T_357, _T_359) @[el2_ifu_iccm_mem.scala 92:52] - node _T_361 = and(_T_354, _T_360) @[el2_ifu_iccm_mem.scala 91:102] - node _T_362 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 92:101] - node _T_363 = and(_T_361, _T_362) @[el2_ifu_iccm_mem.scala 92:84] - node _T_364 = and(_T_363, io.iccm_wren) @[el2_ifu_iccm_mem.scala 92:105] - node _T_365 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 93:6] - node _T_366 = and(_T_365, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 93:21] - node redundant_data1_en = or(_T_364, _T_366) @[el2_ifu_iccm_mem.scala 92:121] - node _T_367 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:49] - node _T_368 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:73] - node _T_369 = and(_T_367, _T_368) @[el2_ifu_iccm_mem.scala 94:52] - node _T_370 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:100] - node _T_371 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:122] - node _T_372 = eq(_T_371, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:127] - node _T_373 = and(_T_370, _T_372) @[el2_ifu_iccm_mem.scala 94:104] - node _T_374 = or(_T_369, _T_373) @[el2_ifu_iccm_mem.scala 94:78] - node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_iccm_mem.scala 94:137] - node _T_376 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 95:20] - node _T_377 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 95:44] - node redundant_data1_in = mux(_T_375, _T_376, _T_377) @[el2_ifu_iccm_mem.scala 94:31] - node _T_378 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 96:78] - reg _T_379 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_378 : @[Reg.scala 28:19] - _T_379 <= redundant_data1_in @[Reg.scala 28:23] + redundant_data[0] <= _T_355 @[el2_ifu_iccm_mem.scala 91:21] + node _T_356 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45] + node _T_357 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 93:85] + node _T_358 = eq(_T_356, _T_357) @[el2_ifu_iccm_mem.scala 93:61] + node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22] + node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:48] + node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 94:26] + node _T_362 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70] + node _T_363 = eq(_T_362, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75] + node _T_364 = or(_T_361, _T_363) @[el2_ifu_iccm_mem.scala 94:52] + node _T_365 = and(_T_358, _T_364) @[el2_ifu_iccm_mem.scala 93:102] + node _T_366 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 94:101] + node _T_367 = and(_T_365, _T_366) @[el2_ifu_iccm_mem.scala 94:84] + node _T_368 = and(_T_367, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105] + node _T_369 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6] + node _T_370 = and(_T_369, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21] + node redundant_data1_en = or(_T_368, _T_370) @[el2_ifu_iccm_mem.scala 94:121] + node _T_371 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49] + node _T_372 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:73] + node _T_373 = and(_T_371, _T_372) @[el2_ifu_iccm_mem.scala 96:52] + node _T_374 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:100] + node _T_375 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122] + node _T_376 = eq(_T_375, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127] + node _T_377 = and(_T_374, _T_376) @[el2_ifu_iccm_mem.scala 96:104] + node _T_378 = or(_T_373, _T_377) @[el2_ifu_iccm_mem.scala 96:78] + node _T_379 = bits(_T_378, 0, 0) @[el2_ifu_iccm_mem.scala 96:137] + node _T_380 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20] + node _T_381 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44] + node redundant_data1_in = mux(_T_379, _T_380, _T_381) @[el2_ifu_iccm_mem.scala 96:31] + node _T_382 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78] + reg _T_383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_382 : @[Reg.scala 28:19] + _T_383 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[1] <= _T_379 @[el2_ifu_iccm_mem.scala 96:21] - node _T_380 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 98:50] - reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 98:34] - iccm_rd_addr_lo_q <= _T_380 @[el2_ifu_iccm_mem.scala 98:34] - node _T_381 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 99:48] - reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 99:34] - iccm_rd_addr_hi_q <= _T_381 @[el2_ifu_iccm_mem.scala 99:34] - node _T_382 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 101:86] - node _T_383 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 101:115] - node _T_384 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 101:86] - node _T_385 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 101:115] - node _T_386 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 101:86] - node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 101:115] - node _T_388 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:86] - node _T_389 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 101:115] - node _T_390 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_391 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_392 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_393 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72] - node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72] - node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72] - wire _T_397 : UInt<32> @[Mux.scala 27:72] - _T_397 <= _T_396 @[Mux.scala 27:72] - node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59] - node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:77] - node _T_400 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 102:106] - node _T_401 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59] - node _T_402 = eq(_T_401, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 102:77] - node _T_403 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 102:106] - node _T_404 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59] - node _T_405 = eq(_T_404, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 102:77] - node _T_406 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 102:106] - node _T_407 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59] - node _T_408 = eq(_T_407, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 102:77] - node _T_409 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 102:106] - node _T_410 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_411 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_412 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_413 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_414 = or(_T_410, _T_411) @[Mux.scala 27:72] - node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72] - node _T_416 = or(_T_415, _T_413) @[Mux.scala 27:72] - wire _T_417 : UInt<32> @[Mux.scala 27:72] - _T_417 <= _T_416 @[Mux.scala 27:72] - node iccm_rd_data_pre = cat(_T_397, _T_417) @[Cat.scala 29:58] - node _T_418 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 103:43] - node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_iccm_mem.scala 103:53] - node _T_420 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_421 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 103:89] - node _T_422 = cat(_T_420, _T_421) @[Cat.scala 29:58] - node _T_423 = mux(_T_419, _T_422, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 103:25] - io.iccm_rd_data <= _T_423 @[el2_ifu_iccm_mem.scala 103:19] - node _T_424 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 104:85] - node _T_425 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 104:85] - node _T_426 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 104:85] - node _T_427 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 104:85] - node _T_428 = mux(_T_424, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_429 = mux(_T_425, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_430 = mux(_T_426, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_431 = mux(_T_427, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_432 = or(_T_428, _T_429) @[Mux.scala 27:72] - node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72] - node _T_434 = or(_T_433, _T_431) @[Mux.scala 27:72] - wire _T_435 : UInt<39> @[Mux.scala 27:72] - _T_435 <= _T_434 @[Mux.scala 27:72] - node _T_436 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:79] - node _T_438 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61] - node _T_439 = eq(_T_438, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:79] - node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61] - node _T_441 = eq(_T_440, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:79] - node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61] - node _T_443 = eq(_T_442, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:79] - node _T_444 = mux(_T_437, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_445 = mux(_T_439, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_446 = mux(_T_441, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_447 = mux(_T_443, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_448 = or(_T_444, _T_445) @[Mux.scala 27:72] - node _T_449 = or(_T_448, _T_446) @[Mux.scala 27:72] - node _T_450 = or(_T_449, _T_447) @[Mux.scala 27:72] - wire _T_451 : UInt<39> @[Mux.scala 27:72] - _T_451 <= _T_450 @[Mux.scala 27:72] - node _T_452 = cat(_T_435, _T_451) @[Cat.scala 29:58] - io.iccm_rd_data_ecc <= _T_452 @[el2_ifu_iccm_mem.scala 104:23] + redundant_data[1] <= _T_383 @[el2_ifu_iccm_mem.scala 98:21] + node _T_384 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 100:50] + reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 100:34] + iccm_rd_addr_lo_q <= _T_384 @[el2_ifu_iccm_mem.scala 100:34] + node _T_385 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 101:48] + reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 101:34] + iccm_rd_addr_hi_q <= _T_385 @[el2_ifu_iccm_mem.scala 101:34] + node _T_386 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 103:86] + node _T_387 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 103:115] + node _T_388 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 103:86] + node _T_389 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 103:115] + node _T_390 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 103:86] + node _T_391 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 103:115] + node _T_392 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:86] + node _T_393 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 103:115] + node _T_394 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_395 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_396 = mux(_T_390, _T_391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_397 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_398 = or(_T_394, _T_395) @[Mux.scala 27:72] + node _T_399 = or(_T_398, _T_396) @[Mux.scala 27:72] + node _T_400 = or(_T_399, _T_397) @[Mux.scala 27:72] + wire _T_401 : UInt<32> @[Mux.scala 27:72] + _T_401 <= _T_400 @[Mux.scala 27:72] + node _T_402 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 104:77] + node _T_404 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 104:106] + node _T_405 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59] + node _T_406 = eq(_T_405, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 104:77] + node _T_407 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 104:106] + node _T_408 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59] + node _T_409 = eq(_T_408, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 104:77] + node _T_410 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 104:106] + node _T_411 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59] + node _T_412 = eq(_T_411, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 104:77] + node _T_413 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 104:106] + node _T_414 = mux(_T_403, _T_404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_415 = mux(_T_406, _T_407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_416 = mux(_T_409, _T_410, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_417 = mux(_T_412, _T_413, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_418 = or(_T_414, _T_415) @[Mux.scala 27:72] + node _T_419 = or(_T_418, _T_416) @[Mux.scala 27:72] + node _T_420 = or(_T_419, _T_417) @[Mux.scala 27:72] + wire _T_421 : UInt<32> @[Mux.scala 27:72] + _T_421 <= _T_420 @[Mux.scala 27:72] + node iccm_rd_data_pre = cat(_T_401, _T_421) @[Cat.scala 29:58] + node _T_422 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 105:43] + node _T_423 = bits(_T_422, 0, 0) @[el2_ifu_iccm_mem.scala 105:53] + node _T_424 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_425 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 105:89] + node _T_426 = cat(_T_424, _T_425) @[Cat.scala 29:58] + node _T_427 = mux(_T_423, _T_426, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 105:25] + io.iccm_rd_data <= _T_427 @[el2_ifu_iccm_mem.scala 105:19] + node _T_428 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:85] + node _T_429 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:85] + node _T_430 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:85] + node _T_431 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:85] + node _T_432 = mux(_T_428, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_433 = mux(_T_429, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_434 = mux(_T_430, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_435 = mux(_T_431, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_436 = or(_T_432, _T_433) @[Mux.scala 27:72] + node _T_437 = or(_T_436, _T_434) @[Mux.scala 27:72] + node _T_438 = or(_T_437, _T_435) @[Mux.scala 27:72] + wire _T_439 : UInt<39> @[Mux.scala 27:72] + _T_439 <= _T_438 @[Mux.scala 27:72] + node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 107:79] + node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 107:79] + node _T_444 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61] + node _T_445 = eq(_T_444, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 107:79] + node _T_446 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61] + node _T_447 = eq(_T_446, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 107:79] + node _T_448 = mux(_T_441, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_449 = mux(_T_443, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_450 = mux(_T_445, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_451 = mux(_T_447, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_452 = or(_T_448, _T_449) @[Mux.scala 27:72] + node _T_453 = or(_T_452, _T_450) @[Mux.scala 27:72] + node _T_454 = or(_T_453, _T_451) @[Mux.scala 27:72] + wire _T_455 : UInt<39> @[Mux.scala 27:72] + _T_455 <= _T_454 @[Mux.scala 27:72] + node _T_456 = cat(_T_439, _T_455) @[Cat.scala 29:58] + io.iccm_rd_data_ecc <= _T_456 @[el2_ifu_iccm_mem.scala 106:23] diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v index c3246672..6b667fd0 100644 --- a/el2_ifu_iccm_mem.v +++ b/el2_ifu_iccm_mem.v @@ -41,109 +41,109 @@ module el2_ifu_iccm_mem( reg [31:0] _RAND_18; `endif // RANDOMIZE_REG_INIT reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_0__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_0__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_0__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_0__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21] reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_1__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_1__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_1__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_1__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21] reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_2__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_2__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_2__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_2__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21] reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_3__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] - wire [38:0] iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - wire [11:0] iccm_mem_3__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_3__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] - wire iccm_mem_3__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] wire iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21] wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43] wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21] - wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54] - wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54] + wire [14:0] _GEN_47 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54] + wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_47; // @[el2_ifu_iccm_mem.scala 25:54] wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50] wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54] wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100] @@ -162,22 +162,22 @@ module el2_ifu_iccm_mem( wire _T_27 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:140] wire _T_28 = _T_25 | _T_27; // @[el2_ifu_iccm_mem.scala 33:107] wire wren_bank_3 = io_iccm_wren & _T_28; // @[el2_ifu_iccm_mem.scala 33:64] - wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 36:64] - wire rden_bank_0 = _T_31 | _T_12; // @[el2_ifu_iccm_mem.scala 36:106] - wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 36:64] - wire rden_bank_1 = _T_36 | _T_17; // @[el2_ifu_iccm_mem.scala 36:106] - wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 36:64] - wire rden_bank_2 = _T_41 | _T_22; // @[el2_ifu_iccm_mem.scala 36:106] - wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 36:64] - wire rden_bank_3 = _T_46 | _T_27; // @[el2_ifu_iccm_mem.scala 36:106] - wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 37:72] - wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] - wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 37:72] - wire iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] - wire _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 37:72] - wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] - wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72] - wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] + wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 35:64] + wire rden_bank_0 = _T_31 | _T_12; // @[el2_ifu_iccm_mem.scala 35:106] + wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 35:64] + wire rden_bank_1 = _T_36 | _T_17; // @[el2_ifu_iccm_mem.scala 35:106] + wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 35:64] + wire rden_bank_2 = _T_41 | _T_22; // @[el2_ifu_iccm_mem.scala 35:106] + wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 35:64] + wire rden_bank_3 = _T_46 | _T_27; // @[el2_ifu_iccm_mem.scala 35:106] + wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 36:72] + wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] + wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 36:72] + wire iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] + wire _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 36:72] + wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] + wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 36:72] + wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] wire [11:0] _T_59 = _T_12 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] wire [11:0] addr_bank_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 38:55] wire [11:0] _T_66 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] @@ -194,281 +194,281 @@ module el2_ifu_iccm_mem( wire read_enable_2 = iccm_clken_2 & _T_89; // @[el2_ifu_iccm_mem.scala 44:70] wire _T_91 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 44:72] wire read_enable_3 = iccm_clken_3 & _T_91; // @[el2_ifu_iccm_mem.scala 44:70] - wire [38:0] _T_98 = read_enable_0 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] - wire [38:0] _GEN_8 = iccm_mem_0__T_99_data; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_9 = 2'h1 == addr_bank_0[1:0] ? iccm_mem_1__T_99_data : _GEN_8; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_10 = 2'h2 == addr_bank_0[1:0] ? iccm_mem_2__T_99_data : _GEN_9; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_11 = 2'h3 == addr_bank_0[1:0] ? iccm_mem_3__T_99_data : _GEN_10; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _T_103 = read_enable_1 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] - wire [38:0] _GEN_12 = iccm_mem_0__T_104_data; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_13 = 2'h1 == addr_bank_1[1:0] ? iccm_mem_1__T_104_data : _GEN_12; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_14 = 2'h2 == addr_bank_1[1:0] ? iccm_mem_2__T_104_data : _GEN_13; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_15 = 2'h3 == addr_bank_1[1:0] ? iccm_mem_3__T_104_data : _GEN_14; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _T_108 = read_enable_2 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] - wire [38:0] _GEN_16 = iccm_mem_0__T_109_data; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_17 = 2'h1 == addr_bank_2[1:0] ? iccm_mem_1__T_109_data : _GEN_16; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_18 = 2'h2 == addr_bank_2[1:0] ? iccm_mem_2__T_109_data : _GEN_17; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_19 = 2'h3 == addr_bank_2[1:0] ? iccm_mem_3__T_109_data : _GEN_18; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _T_113 = read_enable_3 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] - wire [38:0] _GEN_20 = iccm_mem_0__T_114_data; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_21 = 2'h1 == addr_bank_3[1:0] ? iccm_mem_1__T_114_data : _GEN_20; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_22 = 2'h2 == addr_bank_3[1:0] ? iccm_mem_2__T_114_data : _GEN_21; // @[el2_ifu_iccm_mem.scala 49:67] - wire [38:0] _GEN_23 = 2'h3 == addr_bank_3[1:0] ? iccm_mem_3__T_114_data : _GEN_22; // @[el2_ifu_iccm_mem.scala 49:67] - reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62] - reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62] - reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62] - reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 50:62] - reg _T_321; // @[Reg.scala 27:20] - reg _T_322; // @[Reg.scala 27:20] - wire [1:0] redundant_valid = {_T_321,_T_322}; // @[Cat.scala 29:58] + wire [38:0] _T_102 = read_enable_0 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] + wire [38:0] _GEN_24 = iccm_mem_0__T_103_data; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_25 = 2'h1 == addr_bank_0[1:0] ? iccm_mem_1__T_103_data : _GEN_24; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_26 = 2'h2 == addr_bank_0[1:0] ? iccm_mem_2__T_103_data : _GEN_25; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_27 = 2'h3 == addr_bank_0[1:0] ? iccm_mem_3__T_103_data : _GEN_26; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _T_107 = read_enable_1 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] + wire [38:0] _GEN_28 = iccm_mem_0__T_108_data; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_29 = 2'h1 == addr_bank_1[1:0] ? iccm_mem_1__T_108_data : _GEN_28; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_30 = 2'h2 == addr_bank_1[1:0] ? iccm_mem_2__T_108_data : _GEN_29; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_31 = 2'h3 == addr_bank_1[1:0] ? iccm_mem_3__T_108_data : _GEN_30; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _T_112 = read_enable_2 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] + wire [38:0] _GEN_32 = iccm_mem_0__T_113_data; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_33 = 2'h1 == addr_bank_2[1:0] ? iccm_mem_1__T_113_data : _GEN_32; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_34 = 2'h2 == addr_bank_2[1:0] ? iccm_mem_2__T_113_data : _GEN_33; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_35 = 2'h3 == addr_bank_2[1:0] ? iccm_mem_3__T_113_data : _GEN_34; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _T_117 = read_enable_3 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12] + wire [38:0] _GEN_36 = iccm_mem_0__T_118_data; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_37 = 2'h1 == addr_bank_3[1:0] ? iccm_mem_1__T_118_data : _GEN_36; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_38 = 2'h2 == addr_bank_3[1:0] ? iccm_mem_2__T_118_data : _GEN_37; // @[el2_ifu_iccm_mem.scala 51:67] + wire [38:0] _GEN_39 = 2'h3 == addr_bank_3[1:0] ? iccm_mem_3__T_118_data : _GEN_38; // @[el2_ifu_iccm_mem.scala 51:67] + reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 52:62] + reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 52:62] + reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 52:62] + reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 52:62] + reg _T_325; // @[Reg.scala 27:20] + reg _T_326; // @[Reg.scala 27:20] + wire [1:0] redundant_valid = {_T_325,_T_326}; // @[Cat.scala 29:58] reg [13:0] redundant_address_1; // @[Reg.scala 27:20] - wire _T_124 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 61:105] - wire _T_127 = _T_124 & _T_10; // @[el2_ifu_iccm_mem.scala 61:145] - wire _T_128 = redundant_valid[1] & _T_127; // @[el2_ifu_iccm_mem.scala 61:71] - wire _T_131 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 62:37] - wire _T_134 = _T_131 & _T_12; // @[el2_ifu_iccm_mem.scala 62:77] - wire _T_135 = _T_128 | _T_134; // @[el2_ifu_iccm_mem.scala 61:179] - wire _T_142 = _T_124 & _T_15; // @[el2_ifu_iccm_mem.scala 61:145] - wire _T_143 = redundant_valid[1] & _T_142; // @[el2_ifu_iccm_mem.scala 61:71] - wire _T_149 = _T_131 & _T_17; // @[el2_ifu_iccm_mem.scala 62:77] - wire _T_150 = _T_143 | _T_149; // @[el2_ifu_iccm_mem.scala 61:179] - wire _T_157 = _T_124 & _T_20; // @[el2_ifu_iccm_mem.scala 61:145] - wire _T_158 = redundant_valid[1] & _T_157; // @[el2_ifu_iccm_mem.scala 61:71] - wire _T_164 = _T_131 & _T_22; // @[el2_ifu_iccm_mem.scala 62:77] - wire _T_165 = _T_158 | _T_164; // @[el2_ifu_iccm_mem.scala 61:179] - wire _T_172 = _T_124 & _T_25; // @[el2_ifu_iccm_mem.scala 61:145] - wire _T_173 = redundant_valid[1] & _T_172; // @[el2_ifu_iccm_mem.scala 61:71] - wire _T_179 = _T_131 & _T_27; // @[el2_ifu_iccm_mem.scala 62:77] - wire _T_180 = _T_173 | _T_179; // @[el2_ifu_iccm_mem.scala 61:179] - wire [3:0] sel_red1 = {_T_180,_T_165,_T_150,_T_135}; // @[Cat.scala 29:58] + wire _T_128 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 63:105] + wire _T_131 = _T_128 & _T_10; // @[el2_ifu_iccm_mem.scala 63:145] + wire _T_132 = redundant_valid[1] & _T_131; // @[el2_ifu_iccm_mem.scala 63:71] + wire _T_135 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 64:37] + wire _T_138 = _T_135 & _T_12; // @[el2_ifu_iccm_mem.scala 64:77] + wire _T_139 = _T_132 | _T_138; // @[el2_ifu_iccm_mem.scala 63:179] + wire _T_146 = _T_128 & _T_15; // @[el2_ifu_iccm_mem.scala 63:145] + wire _T_147 = redundant_valid[1] & _T_146; // @[el2_ifu_iccm_mem.scala 63:71] + wire _T_153 = _T_135 & _T_17; // @[el2_ifu_iccm_mem.scala 64:77] + wire _T_154 = _T_147 | _T_153; // @[el2_ifu_iccm_mem.scala 63:179] + wire _T_161 = _T_128 & _T_20; // @[el2_ifu_iccm_mem.scala 63:145] + wire _T_162 = redundant_valid[1] & _T_161; // @[el2_ifu_iccm_mem.scala 63:71] + wire _T_168 = _T_135 & _T_22; // @[el2_ifu_iccm_mem.scala 64:77] + wire _T_169 = _T_162 | _T_168; // @[el2_ifu_iccm_mem.scala 63:179] + wire _T_176 = _T_128 & _T_25; // @[el2_ifu_iccm_mem.scala 63:145] + wire _T_177 = redundant_valid[1] & _T_176; // @[el2_ifu_iccm_mem.scala 63:71] + wire _T_183 = _T_135 & _T_27; // @[el2_ifu_iccm_mem.scala 64:77] + wire _T_184 = _T_177 | _T_183; // @[el2_ifu_iccm_mem.scala 63:179] + wire [3:0] sel_red1 = {_T_184,_T_169,_T_154,_T_139}; // @[Cat.scala 29:58] reg [13:0] redundant_address_0; // @[Reg.scala 27:20] - wire _T_186 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 63:105] - wire _T_189 = _T_186 & _T_10; // @[el2_ifu_iccm_mem.scala 63:145] - wire _T_190 = redundant_valid[0] & _T_189; // @[el2_ifu_iccm_mem.scala 63:71] - wire _T_193 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 64:37] - wire _T_196 = _T_193 & _T_12; // @[el2_ifu_iccm_mem.scala 64:77] - wire _T_197 = _T_190 | _T_196; // @[el2_ifu_iccm_mem.scala 63:179] - wire _T_204 = _T_186 & _T_15; // @[el2_ifu_iccm_mem.scala 63:145] - wire _T_205 = redundant_valid[0] & _T_204; // @[el2_ifu_iccm_mem.scala 63:71] - wire _T_211 = _T_193 & _T_17; // @[el2_ifu_iccm_mem.scala 64:77] - wire _T_212 = _T_205 | _T_211; // @[el2_ifu_iccm_mem.scala 63:179] - wire _T_219 = _T_186 & _T_20; // @[el2_ifu_iccm_mem.scala 63:145] - wire _T_220 = redundant_valid[0] & _T_219; // @[el2_ifu_iccm_mem.scala 63:71] - wire _T_226 = _T_193 & _T_22; // @[el2_ifu_iccm_mem.scala 64:77] - wire _T_227 = _T_220 | _T_226; // @[el2_ifu_iccm_mem.scala 63:179] - wire _T_234 = _T_186 & _T_25; // @[el2_ifu_iccm_mem.scala 63:145] - wire _T_235 = redundant_valid[0] & _T_234; // @[el2_ifu_iccm_mem.scala 63:71] - wire _T_241 = _T_193 & _T_27; // @[el2_ifu_iccm_mem.scala 64:77] - wire _T_242 = _T_235 | _T_241; // @[el2_ifu_iccm_mem.scala 63:179] - wire [3:0] sel_red0 = {_T_242,_T_227,_T_212,_T_197}; // @[Cat.scala 29:58] - reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 66:27] - reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 67:27] - wire _T_250 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 73:36] - wire _T_252 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 73:53] - wire _T_253 = _T_250 & _T_252; // @[el2_ifu_iccm_mem.scala 73:51] + wire _T_190 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 65:105] + wire _T_193 = _T_190 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145] + wire _T_194 = redundant_valid[0] & _T_193; // @[el2_ifu_iccm_mem.scala 65:71] + wire _T_197 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 66:37] + wire _T_200 = _T_197 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77] + wire _T_201 = _T_194 | _T_200; // @[el2_ifu_iccm_mem.scala 65:179] + wire _T_208 = _T_190 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145] + wire _T_209 = redundant_valid[0] & _T_208; // @[el2_ifu_iccm_mem.scala 65:71] + wire _T_215 = _T_197 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77] + wire _T_216 = _T_209 | _T_215; // @[el2_ifu_iccm_mem.scala 65:179] + wire _T_223 = _T_190 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145] + wire _T_224 = redundant_valid[0] & _T_223; // @[el2_ifu_iccm_mem.scala 65:71] + wire _T_230 = _T_197 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77] + wire _T_231 = _T_224 | _T_230; // @[el2_ifu_iccm_mem.scala 65:179] + wire _T_238 = _T_190 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145] + wire _T_239 = redundant_valid[0] & _T_238; // @[el2_ifu_iccm_mem.scala 65:71] + wire _T_245 = _T_197 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77] + wire _T_246 = _T_239 | _T_245; // @[el2_ifu_iccm_mem.scala 65:179] + wire [3:0] sel_red0 = {_T_246,_T_231,_T_216,_T_201}; // @[Cat.scala 29:58] + reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 68:27] + reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 69:27] + wire _T_254 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 75:36] + wire _T_256 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 75:53] + wire _T_257 = _T_254 & _T_256; // @[el2_ifu_iccm_mem.scala 75:51] reg [38:0] redundant_data_1; // @[Reg.scala 27:20] - wire [38:0] _T_255 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_259 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] reg [38:0] redundant_data_0; // @[Reg.scala 27:20] - wire [38:0] _T_256 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_257 = _T_253 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_0 = _T_258 | _T_257; // @[Mux.scala 27:72] - wire _T_265 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 73:36] - wire _T_267 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 73:53] - wire _T_268 = _T_265 & _T_267; // @[el2_ifu_iccm_mem.scala 73:51] - wire [38:0] _T_270 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_271 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_272 = _T_268 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_273 = _T_270 | _T_271; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_1 = _T_273 | _T_272; // @[Mux.scala 27:72] - wire _T_280 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 73:36] - wire _T_282 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 73:53] - wire _T_283 = _T_280 & _T_282; // @[el2_ifu_iccm_mem.scala 73:51] - wire [38:0] _T_285 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_286 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_287 = _T_283 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_288 = _T_285 | _T_286; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_2 = _T_288 | _T_287; // @[Mux.scala 27:72] - wire _T_295 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 73:36] - wire _T_297 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 73:53] - wire _T_298 = _T_295 & _T_297; // @[el2_ifu_iccm_mem.scala 73:51] - wire [38:0] _T_300 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_301 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_302 = _T_298 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_303 = _T_300 | _T_301; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_3 = _T_303 | _T_302; // @[Mux.scala 27:72] + wire [38:0] _T_260 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_261 = _T_257 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_0 = _T_262 | _T_261; // @[Mux.scala 27:72] + wire _T_269 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 75:36] + wire _T_271 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 75:53] + wire _T_272 = _T_269 & _T_271; // @[el2_ifu_iccm_mem.scala 75:51] + wire [38:0] _T_274 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_275 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_276 = _T_272 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_277 = _T_274 | _T_275; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_1 = _T_277 | _T_276; // @[Mux.scala 27:72] + wire _T_284 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 75:36] + wire _T_286 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 75:53] + wire _T_287 = _T_284 & _T_286; // @[el2_ifu_iccm_mem.scala 75:51] + wire [38:0] _T_289 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_290 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_291 = _T_287 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_292 = _T_289 | _T_290; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_2 = _T_292 | _T_291; // @[Mux.scala 27:72] + wire _T_299 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 75:36] + wire _T_301 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 75:53] + wire _T_302 = _T_299 & _T_301; // @[el2_ifu_iccm_mem.scala 75:51] + wire [38:0] _T_304 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_305 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_306 = _T_302 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_307 = _T_304 | _T_305; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_3 = _T_307 | _T_306; // @[Mux.scala 27:72] reg redundant_lru; // @[Reg.scala 27:20] - wire _T_305 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 75:20] - wire r0_addr_en = _T_305 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 75:35] - wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 76:35] - wire _T_306 = |sel_red0; // @[el2_ifu_iccm_mem.scala 77:63] - wire _T_307 = |sel_red1; // @[el2_ifu_iccm_mem.scala 77:78] - wire _T_308 = _T_306 | _T_307; // @[el2_ifu_iccm_mem.scala 77:67] - wire _T_309 = _T_308 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 77:83] - wire _T_310 = _T_309 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 77:98] - wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_310; // @[el2_ifu_iccm_mem.scala 77:50] - wire _GEN_27 = r1_addr_en | _T_321; // @[Reg.scala 28:19] - wire _GEN_28 = r0_addr_en | _T_322; // @[Reg.scala 28:19] - wire _T_326 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 84:61] - wire _T_329 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 85:26] - wire _T_332 = _T_329 | _T_1; // @[el2_ifu_iccm_mem.scala 85:52] - wire _T_333 = _T_326 & _T_332; // @[el2_ifu_iccm_mem.scala 84:102] - wire _T_335 = _T_333 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 85:84] - wire _T_336 = _T_335 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 85:105] - wire redundant_data0_en = _T_336 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 85:121] - wire _T_345 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 87:104] - wire _T_346 = _T_329 | _T_345; // @[el2_ifu_iccm_mem.scala 87:78] - wire _T_354 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 91:61] - wire _T_357 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 92:26] - wire _T_360 = _T_357 | _T_1; // @[el2_ifu_iccm_mem.scala 92:52] - wire _T_361 = _T_354 & _T_360; // @[el2_ifu_iccm_mem.scala 91:102] - wire _T_363 = _T_361 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 92:84] - wire _T_364 = _T_363 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 92:105] - wire redundant_data1_en = _T_364 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 92:121] - wire _T_373 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 94:104] - wire _T_374 = _T_357 | _T_373; // @[el2_ifu_iccm_mem.scala 94:78] - reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 98:34] - reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 99:34] - wire _T_382 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 101:86] - wire _T_384 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 101:86] - wire _T_386 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 101:86] - wire _T_388 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 101:86] - wire [31:0] _T_390 = _T_382 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_391 = _T_384 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_392 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_393 = _T_388 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72] - wire [31:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72] - wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72] - wire _T_399 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 102:77] - wire _T_402 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 102:77] - wire _T_405 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 102:77] - wire _T_408 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 102:77] - wire [31:0] _T_410 = _T_399 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_411 = _T_402 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_412 = _T_405 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_413 = _T_408 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_414 = _T_410 | _T_411; // @[Mux.scala 27:72] - wire [31:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72] - wire [31:0] _T_416 = _T_415 | _T_413; // @[Mux.scala 27:72] - wire [63:0] iccm_rd_data_pre = {_T_396,_T_416}; // @[Cat.scala 29:58] - wire [63:0] _T_422 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] - wire [38:0] _T_428 = _T_382 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_429 = _T_384 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_430 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_431 = _T_388 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_432 = _T_428 | _T_429; // @[Mux.scala 27:72] - wire [38:0] _T_433 = _T_432 | _T_430; // @[Mux.scala 27:72] - wire [38:0] _T_434 = _T_433 | _T_431; // @[Mux.scala 27:72] - wire [38:0] _T_444 = _T_399 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_445 = _T_402 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_446 = _T_405 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_447 = _T_408 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_448 = _T_444 | _T_445; // @[Mux.scala 27:72] - wire [38:0] _T_449 = _T_448 | _T_446; // @[Mux.scala 27:72] - wire [38:0] _T_450 = _T_449 | _T_447; // @[Mux.scala 27:72] - assign iccm_mem_0__T_99_addr = 12'h0; - assign iccm_mem_0__T_99_data = iccm_mem_0[iccm_mem_0__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_0__T_104_addr = 12'h1; - assign iccm_mem_0__T_104_data = iccm_mem_0[iccm_mem_0__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_0__T_109_addr = 12'h2; - assign iccm_mem_0__T_109_data = iccm_mem_0[iccm_mem_0__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_0__T_114_addr = 12'h3; - assign iccm_mem_0__T_114_data = iccm_mem_0[iccm_mem_0__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_0__T_93_data = io_iccm_wr_data[38:0]; - assign iccm_mem_0__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_0__T_93_mask = iccm_clken_0 & wren_bank_0; - assign iccm_mem_0__T_93_en = 1'h1; + wire _T_309 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 77:20] + wire r0_addr_en = _T_309 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 77:35] + wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 78:35] + wire _T_310 = |sel_red0; // @[el2_ifu_iccm_mem.scala 79:63] + wire _T_311 = |sel_red1; // @[el2_ifu_iccm_mem.scala 79:78] + wire _T_312 = _T_310 | _T_311; // @[el2_ifu_iccm_mem.scala 79:67] + wire _T_313 = _T_312 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 79:83] + wire _T_314 = _T_313 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 79:98] + wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_314; // @[el2_ifu_iccm_mem.scala 79:50] + wire _GEN_43 = r1_addr_en | _T_325; // @[Reg.scala 28:19] + wire _GEN_44 = r0_addr_en | _T_326; // @[Reg.scala 28:19] + wire _T_330 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 86:61] + wire _T_333 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 87:26] + wire _T_336 = _T_333 | _T_1; // @[el2_ifu_iccm_mem.scala 87:52] + wire _T_337 = _T_330 & _T_336; // @[el2_ifu_iccm_mem.scala 86:102] + wire _T_339 = _T_337 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 87:84] + wire _T_340 = _T_339 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 87:105] + wire redundant_data0_en = _T_340 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 87:121] + wire _T_349 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 89:104] + wire _T_350 = _T_333 | _T_349; // @[el2_ifu_iccm_mem.scala 89:78] + wire _T_358 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 93:61] + wire _T_361 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 94:26] + wire _T_364 = _T_361 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52] + wire _T_365 = _T_358 & _T_364; // @[el2_ifu_iccm_mem.scala 93:102] + wire _T_367 = _T_365 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 94:84] + wire _T_368 = _T_367 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105] + wire redundant_data1_en = _T_368 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121] + wire _T_377 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104] + wire _T_378 = _T_361 | _T_377; // @[el2_ifu_iccm_mem.scala 96:78] + reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 100:34] + reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 101:34] + wire _T_386 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 103:86] + wire _T_388 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 103:86] + wire _T_390 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 103:86] + wire _T_392 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 103:86] + wire [31:0] _T_394 = _T_386 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_395 = _T_388 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_396 = _T_390 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_397 = _T_392 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_398 = _T_394 | _T_395; // @[Mux.scala 27:72] + wire [31:0] _T_399 = _T_398 | _T_396; // @[Mux.scala 27:72] + wire [31:0] _T_400 = _T_399 | _T_397; // @[Mux.scala 27:72] + wire _T_403 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 104:77] + wire _T_406 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 104:77] + wire _T_409 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 104:77] + wire _T_412 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 104:77] + wire [31:0] _T_414 = _T_403 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_415 = _T_406 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_416 = _T_409 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_417 = _T_412 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_418 = _T_414 | _T_415; // @[Mux.scala 27:72] + wire [31:0] _T_419 = _T_418 | _T_416; // @[Mux.scala 27:72] + wire [31:0] _T_420 = _T_419 | _T_417; // @[Mux.scala 27:72] + wire [63:0] iccm_rd_data_pre = {_T_400,_T_420}; // @[Cat.scala 29:58] + wire [63:0] _T_426 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] + wire [38:0] _T_432 = _T_386 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_433 = _T_388 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_434 = _T_390 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_435 = _T_392 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_436 = _T_432 | _T_433; // @[Mux.scala 27:72] + wire [38:0] _T_437 = _T_436 | _T_434; // @[Mux.scala 27:72] + wire [38:0] _T_438 = _T_437 | _T_435; // @[Mux.scala 27:72] + wire [38:0] _T_448 = _T_403 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_449 = _T_406 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_450 = _T_409 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_451 = _T_412 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_452 = _T_448 | _T_449; // @[Mux.scala 27:72] + wire [38:0] _T_453 = _T_452 | _T_450; // @[Mux.scala 27:72] + wire [38:0] _T_454 = _T_453 | _T_451; // @[Mux.scala 27:72] + assign iccm_mem_0__T_103_addr = 12'h0; + assign iccm_mem_0__T_103_data = iccm_mem_0[iccm_mem_0__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_0__T_108_addr = 12'h1; + assign iccm_mem_0__T_108_data = iccm_mem_0[iccm_mem_0__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_0__T_113_addr = 12'h2; + assign iccm_mem_0__T_113_data = iccm_mem_0[iccm_mem_0__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_0__T_118_addr = 12'h3; + assign iccm_mem_0__T_118_data = iccm_mem_0[iccm_mem_0__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21] assign iccm_mem_0__T_94_data = io_iccm_wr_data[38:0]; - assign iccm_mem_0__T_94_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; - assign iccm_mem_0__T_94_mask = iccm_clken_0 & wren_bank_0; - assign iccm_mem_0__T_94_en = 1'h1; - assign iccm_mem_0__T_95_data = io_iccm_wr_data[38:0]; - assign iccm_mem_0__T_95_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; - assign iccm_mem_0__T_95_mask = iccm_clken_0 & wren_bank_0; - assign iccm_mem_0__T_95_en = 1'h1; - assign iccm_mem_0__T_96_data = io_iccm_wr_data[38:0]; - assign iccm_mem_0__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; - assign iccm_mem_0__T_96_mask = iccm_clken_0 & wren_bank_0; - assign iccm_mem_0__T_96_en = 1'h1; - assign iccm_mem_1__T_99_addr = 12'h0; - assign iccm_mem_1__T_99_data = iccm_mem_1[iccm_mem_1__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_1__T_104_addr = 12'h1; - assign iccm_mem_1__T_104_data = iccm_mem_1[iccm_mem_1__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_1__T_109_addr = 12'h2; - assign iccm_mem_1__T_109_data = iccm_mem_1[iccm_mem_1__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_1__T_114_addr = 12'h3; - assign iccm_mem_1__T_114_data = iccm_mem_1[iccm_mem_1__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_1__T_93_data = io_iccm_wr_data[77:39]; - assign iccm_mem_1__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_1__T_93_mask = iccm_clken_1 & wren_bank_1; - assign iccm_mem_1__T_93_en = 1'h1; - assign iccm_mem_1__T_94_data = io_iccm_wr_data[77:39]; - assign iccm_mem_1__T_94_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; - assign iccm_mem_1__T_94_mask = iccm_clken_1 & wren_bank_1; - assign iccm_mem_1__T_94_en = 1'h1; - assign iccm_mem_1__T_95_data = io_iccm_wr_data[77:39]; - assign iccm_mem_1__T_95_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; - assign iccm_mem_1__T_95_mask = iccm_clken_1 & wren_bank_1; - assign iccm_mem_1__T_95_en = 1'h1; + assign iccm_mem_0__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; + assign iccm_mem_0__T_94_mask = 1'h1; + assign iccm_mem_0__T_94_en = iccm_clken_0 & wren_bank_0; + assign iccm_mem_0__T_96_data = 39'h0; + assign iccm_mem_0__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; + assign iccm_mem_0__T_96_mask = 1'h0; + assign iccm_mem_0__T_96_en = iccm_clken_1 & wren_bank_1; + assign iccm_mem_0__T_98_data = 39'h0; + assign iccm_mem_0__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; + assign iccm_mem_0__T_98_mask = 1'h0; + assign iccm_mem_0__T_98_en = iccm_clken_2 & wren_bank_2; + assign iccm_mem_0__T_100_data = 39'h0; + assign iccm_mem_0__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; + assign iccm_mem_0__T_100_mask = 1'h0; + assign iccm_mem_0__T_100_en = iccm_clken_3 & wren_bank_3; + assign iccm_mem_1__T_103_addr = 12'h0; + assign iccm_mem_1__T_103_data = iccm_mem_1[iccm_mem_1__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_1__T_108_addr = 12'h1; + assign iccm_mem_1__T_108_data = iccm_mem_1[iccm_mem_1__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_1__T_113_addr = 12'h2; + assign iccm_mem_1__T_113_data = iccm_mem_1[iccm_mem_1__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_1__T_118_addr = 12'h3; + assign iccm_mem_1__T_118_data = iccm_mem_1[iccm_mem_1__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_1__T_94_data = 39'h0; + assign iccm_mem_1__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; + assign iccm_mem_1__T_94_mask = 1'h0; + assign iccm_mem_1__T_94_en = iccm_clken_0 & wren_bank_0; assign iccm_mem_1__T_96_data = io_iccm_wr_data[77:39]; - assign iccm_mem_1__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; - assign iccm_mem_1__T_96_mask = iccm_clken_1 & wren_bank_1; - assign iccm_mem_1__T_96_en = 1'h1; - assign iccm_mem_2__T_99_addr = 12'h0; - assign iccm_mem_2__T_99_data = iccm_mem_2[iccm_mem_2__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_2__T_104_addr = 12'h1; - assign iccm_mem_2__T_104_data = iccm_mem_2[iccm_mem_2__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_2__T_109_addr = 12'h2; - assign iccm_mem_2__T_109_data = iccm_mem_2[iccm_mem_2__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_2__T_114_addr = 12'h3; - assign iccm_mem_2__T_114_data = iccm_mem_2[iccm_mem_2__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_2__T_93_data = io_iccm_wr_data[38:0]; - assign iccm_mem_2__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_2__T_93_mask = iccm_clken_2 & wren_bank_2; - assign iccm_mem_2__T_93_en = 1'h1; - assign iccm_mem_2__T_94_data = io_iccm_wr_data[38:0]; - assign iccm_mem_2__T_94_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; - assign iccm_mem_2__T_94_mask = iccm_clken_2 & wren_bank_2; - assign iccm_mem_2__T_94_en = 1'h1; - assign iccm_mem_2__T_95_data = io_iccm_wr_data[38:0]; - assign iccm_mem_2__T_95_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; - assign iccm_mem_2__T_95_mask = iccm_clken_2 & wren_bank_2; - assign iccm_mem_2__T_95_en = 1'h1; - assign iccm_mem_2__T_96_data = io_iccm_wr_data[38:0]; - assign iccm_mem_2__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; - assign iccm_mem_2__T_96_mask = iccm_clken_2 & wren_bank_2; - assign iccm_mem_2__T_96_en = 1'h1; - assign iccm_mem_3__T_99_addr = 12'h0; - assign iccm_mem_3__T_99_data = iccm_mem_3[iccm_mem_3__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_3__T_104_addr = 12'h1; - assign iccm_mem_3__T_104_data = iccm_mem_3[iccm_mem_3__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_3__T_109_addr = 12'h2; - assign iccm_mem_3__T_109_data = iccm_mem_3[iccm_mem_3__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_3__T_114_addr = 12'h3; - assign iccm_mem_3__T_114_data = iccm_mem_3[iccm_mem_3__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21] - assign iccm_mem_3__T_93_data = io_iccm_wr_data[77:39]; - assign iccm_mem_3__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_3__T_93_mask = iccm_clken_3 & wren_bank_3; - assign iccm_mem_3__T_93_en = 1'h1; - assign iccm_mem_3__T_94_data = io_iccm_wr_data[77:39]; - assign iccm_mem_3__T_94_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; - assign iccm_mem_3__T_94_mask = iccm_clken_3 & wren_bank_3; - assign iccm_mem_3__T_94_en = 1'h1; - assign iccm_mem_3__T_95_data = io_iccm_wr_data[77:39]; - assign iccm_mem_3__T_95_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; - assign iccm_mem_3__T_95_mask = iccm_clken_3 & wren_bank_3; - assign iccm_mem_3__T_95_en = 1'h1; - assign iccm_mem_3__T_96_data = io_iccm_wr_data[77:39]; - assign iccm_mem_3__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; - assign iccm_mem_3__T_96_mask = iccm_clken_3 & wren_bank_3; - assign iccm_mem_3__T_96_en = 1'h1; - assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_422 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 103:19] - assign io_iccm_rd_data_ecc = {_T_434,_T_450}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 104:23] - assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 52:21] - assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 52:21] - assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 52:21] - assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 52:21] + assign iccm_mem_1__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; + assign iccm_mem_1__T_96_mask = 1'h1; + assign iccm_mem_1__T_96_en = iccm_clken_1 & wren_bank_1; + assign iccm_mem_1__T_98_data = 39'h0; + assign iccm_mem_1__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; + assign iccm_mem_1__T_98_mask = 1'h0; + assign iccm_mem_1__T_98_en = iccm_clken_2 & wren_bank_2; + assign iccm_mem_1__T_100_data = 39'h0; + assign iccm_mem_1__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; + assign iccm_mem_1__T_100_mask = 1'h0; + assign iccm_mem_1__T_100_en = iccm_clken_3 & wren_bank_3; + assign iccm_mem_2__T_103_addr = 12'h0; + assign iccm_mem_2__T_103_data = iccm_mem_2[iccm_mem_2__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_2__T_108_addr = 12'h1; + assign iccm_mem_2__T_108_data = iccm_mem_2[iccm_mem_2__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_2__T_113_addr = 12'h2; + assign iccm_mem_2__T_113_data = iccm_mem_2[iccm_mem_2__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_2__T_118_addr = 12'h3; + assign iccm_mem_2__T_118_data = iccm_mem_2[iccm_mem_2__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_2__T_94_data = 39'h0; + assign iccm_mem_2__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; + assign iccm_mem_2__T_94_mask = 1'h0; + assign iccm_mem_2__T_94_en = iccm_clken_0 & wren_bank_0; + assign iccm_mem_2__T_96_data = 39'h0; + assign iccm_mem_2__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; + assign iccm_mem_2__T_96_mask = 1'h0; + assign iccm_mem_2__T_96_en = iccm_clken_1 & wren_bank_1; + assign iccm_mem_2__T_98_data = io_iccm_wr_data[38:0]; + assign iccm_mem_2__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; + assign iccm_mem_2__T_98_mask = 1'h1; + assign iccm_mem_2__T_98_en = iccm_clken_2 & wren_bank_2; + assign iccm_mem_2__T_100_data = 39'h0; + assign iccm_mem_2__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; + assign iccm_mem_2__T_100_mask = 1'h0; + assign iccm_mem_2__T_100_en = iccm_clken_3 & wren_bank_3; + assign iccm_mem_3__T_103_addr = 12'h0; + assign iccm_mem_3__T_103_data = iccm_mem_3[iccm_mem_3__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_3__T_108_addr = 12'h1; + assign iccm_mem_3__T_108_data = iccm_mem_3[iccm_mem_3__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_3__T_113_addr = 12'h2; + assign iccm_mem_3__T_113_data = iccm_mem_3[iccm_mem_3__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_3__T_118_addr = 12'h3; + assign iccm_mem_3__T_118_data = iccm_mem_3[iccm_mem_3__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21] + assign iccm_mem_3__T_94_data = 39'h0; + assign iccm_mem_3__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; + assign iccm_mem_3__T_94_mask = 1'h0; + assign iccm_mem_3__T_94_en = iccm_clken_0 & wren_bank_0; + assign iccm_mem_3__T_96_data = 39'h0; + assign iccm_mem_3__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; + assign iccm_mem_3__T_96_mask = 1'h0; + assign iccm_mem_3__T_96_en = iccm_clken_1 & wren_bank_1; + assign iccm_mem_3__T_98_data = 39'h0; + assign iccm_mem_3__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; + assign iccm_mem_3__T_98_mask = 1'h0; + assign iccm_mem_3__T_98_en = iccm_clken_2 & wren_bank_2; + assign iccm_mem_3__T_100_data = io_iccm_wr_data[77:39]; + assign iccm_mem_3__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; + assign iccm_mem_3__T_100_mask = 1'h1; + assign iccm_mem_3__T_100_en = iccm_clken_3 & wren_bank_3; + assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_426 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 105:19] + assign io_iccm_rd_data_ecc = {_T_438,_T_454}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 106:23] + assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 54:21] + assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 54:21] + assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 54:21] + assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 54:21] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -527,9 +527,9 @@ initial begin _RAND_7 = {2{`RANDOM}}; iccm_bank_dout_3 = _RAND_7[38:0]; _RAND_8 = {1{`RANDOM}}; - _T_321 = _RAND_8[0:0]; + _T_325 = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_322 = _RAND_9[0:0]; + _T_326 = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; redundant_address_1 = _RAND_10[13:0]; _RAND_11 = {1{`RANDOM}}; @@ -556,67 +556,67 @@ end // initial `endif `endif // SYNTHESIS always @(posedge clock) begin - if(iccm_mem_0__T_93_en & iccm_mem_0__T_93_mask) begin - iccm_mem_0[iccm_mem_0__T_93_addr] <= iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] - end if(iccm_mem_0__T_94_en & iccm_mem_0__T_94_mask) begin iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_0__T_95_en & iccm_mem_0__T_95_mask) begin - iccm_mem_0[iccm_mem_0__T_95_addr] <= iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - end if(iccm_mem_0__T_96_en & iccm_mem_0__T_96_mask) begin iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_1__T_93_en & iccm_mem_1__T_93_mask) begin - iccm_mem_1[iccm_mem_1__T_93_addr] <= iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + if(iccm_mem_0__T_98_en & iccm_mem_0__T_98_mask) begin + iccm_mem_0[iccm_mem_0__T_98_addr] <= iccm_mem_0__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + if(iccm_mem_0__T_100_en & iccm_mem_0__T_100_mask) begin + iccm_mem_0[iccm_mem_0__T_100_addr] <= iccm_mem_0__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_1__T_94_en & iccm_mem_1__T_94_mask) begin iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_1__T_95_en & iccm_mem_1__T_95_mask) begin - iccm_mem_1[iccm_mem_1__T_95_addr] <= iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - end if(iccm_mem_1__T_96_en & iccm_mem_1__T_96_mask) begin iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_2__T_93_en & iccm_mem_2__T_93_mask) begin - iccm_mem_2[iccm_mem_2__T_93_addr] <= iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + if(iccm_mem_1__T_98_en & iccm_mem_1__T_98_mask) begin + iccm_mem_1[iccm_mem_1__T_98_addr] <= iccm_mem_1__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + if(iccm_mem_1__T_100_en & iccm_mem_1__T_100_mask) begin + iccm_mem_1[iccm_mem_1__T_100_addr] <= iccm_mem_1__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_2__T_94_en & iccm_mem_2__T_94_mask) begin iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_2__T_95_en & iccm_mem_2__T_95_mask) begin - iccm_mem_2[iccm_mem_2__T_95_addr] <= iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - end if(iccm_mem_2__T_96_en & iccm_mem_2__T_96_mask) begin iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_3__T_93_en & iccm_mem_3__T_93_mask) begin - iccm_mem_3[iccm_mem_3__T_93_addr] <= iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + if(iccm_mem_2__T_98_en & iccm_mem_2__T_98_mask) begin + iccm_mem_2[iccm_mem_2__T_98_addr] <= iccm_mem_2__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + if(iccm_mem_2__T_100_en & iccm_mem_2__T_100_mask) begin + iccm_mem_2[iccm_mem_2__T_100_addr] <= iccm_mem_2__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_3__T_94_en & iccm_mem_3__T_94_mask) begin iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end - if(iccm_mem_3__T_95_en & iccm_mem_3__T_95_mask) begin - iccm_mem_3[iccm_mem_3__T_95_addr] <= iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] - end if(iccm_mem_3__T_96_en & iccm_mem_3__T_96_mask) begin iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end - iccm_bank_dout_0 <= _T_98 & _GEN_11; - iccm_bank_dout_1 <= _T_103 & _GEN_15; - iccm_bank_dout_2 <= _T_108 & _GEN_19; - iccm_bank_dout_3 <= _T_113 & _GEN_23; + if(iccm_mem_3__T_98_en & iccm_mem_3__T_98_mask) begin + iccm_mem_3[iccm_mem_3__T_98_addr] <= iccm_mem_3__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + if(iccm_mem_3__T_100_en & iccm_mem_3__T_100_mask) begin + iccm_mem_3[iccm_mem_3__T_100_addr] <= iccm_mem_3__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + iccm_bank_dout_0 <= _T_102 & _GEN_27; + iccm_bank_dout_1 <= _T_107 & _GEN_31; + iccm_bank_dout_2 <= _T_112 & _GEN_35; + iccm_bank_dout_3 <= _T_117 & _GEN_39; if (reset) begin - _T_321 <= 1'h0; + _T_325 <= 1'h0; end else begin - _T_321 <= _GEN_27; + _T_325 <= _GEN_43; end if (reset) begin - _T_322 <= 1'h0; + _T_326 <= 1'h0; end else begin - _T_322 <= _GEN_28; + _T_326 <= _GEN_44; end if (reset) begin redundant_address_1 <= 14'h0; @@ -641,7 +641,7 @@ end // initial if (reset) begin redundant_data_1 <= 39'h0; end else if (redundant_data1_en) begin - if (_T_374) begin + if (_T_378) begin redundant_data_1 <= iccm_bank_wr_data_1; end else begin redundant_data_1 <= iccm_bank_wr_data_0; @@ -650,7 +650,7 @@ end // initial if (reset) begin redundant_data_0 <= 39'h0; end else if (redundant_data0_en) begin - if (_T_346) begin + if (_T_350) begin redundant_data_0 <= iccm_bank_wr_data_1; end else begin redundant_data_0 <= iccm_bank_wr_data_0; @@ -660,9 +660,9 @@ end // initial redundant_lru <= 1'h0; end else if (redundant_lru_en) begin if (io_iccm_buf_correct_ecc) begin - redundant_lru <= _T_305; + redundant_lru <= _T_309; end else begin - redundant_lru <= _T_306; + redundant_lru <= _T_310; end end if (reset) begin diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala index 72e3bff1..fc320560 100644 --- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -32,9 +32,9 @@ class el2_ifu_iccm_mem extends Module with el2_lib { val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&((io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))) val iccm_bank_wr_data = iccm_bank_wr_data_vec - //io.iccm_bank_wr_data := iccm_bank_wr_data val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield wren_bank(i) | rden_bank(i) | io.clk_override + val addr_bank = (0 until ICCM_NUM_BANKS).map(i=> Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1), Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1)))) @@ -42,10 +42,12 @@ class el2_ifu_iccm_mem extends Module with el2_lib { val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i)) val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i))) - //io.test := addr_bank + val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) - for(i<-0 until ICCM_NUM_BANKS) iccm_mem.write(addr_bank(i), iccm_bank_wr_data, write_vec) + + for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i).asBool){iccm_mem(addr_bank(i))(i) :=iccm_bank_wr_data(i)} + inter := (0 until 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