diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir
index b1beb419..2f19aacc 100644
--- a/quasar_wrapper.fir
+++ b/quasar_wrapper.fir
@@ -73424,983 +73424,973 @@ circuit quasar_wrapper :
     reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     _T_339 <= mfdc_ns @[lib.scala 374:16]
     mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1748:11]
-    node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1753:40]
-    node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1753:20]
-    node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1753:67]
-    node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1753:95]
-    node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1753:75]
-    node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1753:119]
-    node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58]
-    node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58]
+    node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1757:39]
+    node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1757:19]
+    node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1757:66]
+    node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58]
+    mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1757:12]
+    node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1758:28]
+    node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1758:19]
+    node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1758:54]
+    node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58]
     node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58]
-    mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1753:13]
-    node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1754:29]
-    node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1754:20]
-    node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1754:55]
-    node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1754:72]
-    node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1754:63]
-    node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1754:85]
-    node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58]
-    node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58]
-    node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58]
-    node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58]
-    mfdc <= _T_358 @[dec_tlu_ctl.scala 1754:13]
-    node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46]
-    io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1762:39]
-    node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46]
-    io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1763:39]
-    node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46]
-    io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1764:39]
-    node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46]
-    io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1765:39]
-    node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46]
-    io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1766:39]
-    node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46]
-    io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1767:39]
-    node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46]
-    io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1768:39]
-    node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70]
-    node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77]
-    node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1777:48]
-    node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89]
-    node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1777:87]
-    node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113]
-    node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1777:111]
-    io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1777:24]
-    node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61]
-    node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68]
-    node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1784:39]
-    node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39]
-    node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64]
-    node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91]
-    node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1787:71]
-    node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1787:69]
-    node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41]
-    node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66]
-    node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93]
-    node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1788:73]
-    node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1788:71]
-    node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41]
-    node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66]
-    node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93]
-    node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1789:73]
-    node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1789:71]
-    node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41]
-    node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66]
-    node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93]
-    node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1790:73]
-    node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1790:71]
-    node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41]
-    node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66]
-    node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93]
-    node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1791:73]
-    node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1791:71]
-    node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41]
-    node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66]
-    node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93]
-    node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1792:73]
-    node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1792:71]
-    node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41]
-    node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66]
-    node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93]
-    node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1793:73]
-    node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1793:71]
-    node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41]
-    node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66]
-    node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93]
-    node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1794:73]
-    node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1794:71]
-    node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41]
-    node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66]
-    node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93]
-    node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1795:73]
-    node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1795:71]
-    node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41]
-    node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66]
-    node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93]
-    node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1796:73]
-    node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1796:71]
-    node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41]
-    node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66]
-    node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93]
-    node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1797:73]
-    node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1797:71]
-    node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41]
-    node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66]
-    node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93]
-    node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1798:73]
-    node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1798:70]
-    node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41]
-    node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66]
-    node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93]
-    node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1799:73]
-    node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1799:70]
-    node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41]
-    node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66]
-    node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93]
-    node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1800:73]
-    node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1800:70]
-    node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41]
-    node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66]
-    node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93]
-    node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1801:73]
-    node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1801:70]
-    node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41]
-    node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66]
-    node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93]
-    node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1802:73]
-    node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1802:70]
-    node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58]
-    node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58]
+    mfdc <= _T_348 @[dec_tlu_ctl.scala 1758:12]
+    node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46]
+    io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1762:39]
+    node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46]
+    io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1763:39]
+    node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46]
+    io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1764:39]
+    node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46]
+    io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1765:39]
+    node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46]
+    io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1766:39]
+    node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46]
+    io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1767:39]
+    node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46]
+    io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1768:39]
+    node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70]
+    node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77]
+    node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1777:48]
+    node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89]
+    node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1777:87]
+    node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113]
+    node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1777:111]
+    io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1777:24]
+    node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61]
+    node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68]
+    node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1784:39]
+    node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39]
+    node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64]
+    node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91]
+    node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1787:71]
+    node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1787:69]
+    node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41]
+    node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66]
+    node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93]
+    node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1788:73]
+    node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1788:71]
+    node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41]
+    node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66]
+    node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93]
+    node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1789:73]
+    node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1789:71]
+    node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41]
+    node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66]
+    node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93]
+    node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1790:73]
+    node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1790:71]
+    node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41]
+    node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66]
+    node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93]
+    node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1791:73]
+    node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1791:71]
+    node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41]
+    node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66]
+    node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93]
+    node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1792:73]
+    node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1792:71]
+    node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41]
+    node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66]
+    node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93]
+    node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1793:73]
+    node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1793:71]
+    node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41]
+    node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66]
+    node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93]
+    node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1794:73]
+    node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1794:71]
+    node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41]
+    node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66]
+    node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93]
+    node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1795:73]
+    node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1795:71]
+    node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41]
+    node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66]
+    node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93]
+    node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1796:73]
+    node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1796:71]
+    node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41]
+    node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66]
+    node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93]
+    node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1797:73]
+    node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1797:71]
+    node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41]
+    node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66]
+    node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93]
+    node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1798:73]
+    node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1798:70]
+    node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41]
+    node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66]
+    node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93]
+    node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1799:73]
+    node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1799:70]
+    node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41]
+    node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66]
+    node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93]
+    node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1800:73]
+    node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1800:70]
+    node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41]
+    node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66]
+    node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93]
+    node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1801:73]
+    node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1801:70]
+    node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41]
+    node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66]
+    node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93]
+    node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1802:73]
+    node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1802:70]
+    node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58]
+    node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58]
+    node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58]
+    node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58]
+    node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58]
+    node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58]
+    node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58]
+    node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58]
+    node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58]
+    node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58]
+    node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58]
+    node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58]
     node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58]
-    node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58]
-    node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58]
-    node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58]
-    node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58]
-    node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58]
-    node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58]
-    node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58]
-    node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58]
-    node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58]
-    node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58]
-    node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58]
-    node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58]
-    node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58]
-    node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58]
+    node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58]
+    node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58]
+    node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58]
+    node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58]
+    node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58]
+    node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58]
+    node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58]
+    node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58]
+    node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58]
+    node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58]
+    node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58]
+    node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58]
+    node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58]
+    node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58]
     node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58]
-    node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58]
-    node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58]
-    node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58]
-    node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58]
-    node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58]
-    node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58]
-    node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58]
-    node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58]
-    node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58]
-    node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58]
-    node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58]
-    node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58]
-    node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58]
-    node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38]
+    node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58]
+    node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58]
+    node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58]
+    node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38]
     inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17]
+    rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17]
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     mrac <= mrac_in @[lib.scala 374:16]
     io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1807:21]
-    node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62]
-    node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69]
-    node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1815:40]
-    node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59]
-    node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1825:57]
-    node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1825:35]
-    io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1825:22]
-    node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49]
-    node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86]
-    node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1827:84]
-    node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111]
-    node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1827:109]
-    mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1827:12]
-    node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64]
+    node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62]
+    node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69]
+    node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1815:40]
+    node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59]
+    node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1825:57]
+    node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1825:35]
+    io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1825:22]
+    node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49]
+    node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86]
+    node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1827:84]
+    node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111]
+    node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1827:109]
+    mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1827:12]
+    node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64]
     inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17]
+    rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17]
     rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16]
-    node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61]
-    node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68]
-    node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1838:39]
-    node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51]
-    node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1842:30]
-    node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57]
-    node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1842:55]
-    node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89]
-    node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1842:87]
-    io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1842:17]
+    node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61]
+    node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68]
+    node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1838:39]
+    node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51]
+    node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1842:30]
+    node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57]
+    node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1842:55]
+    node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89]
+    node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1842:87]
+    io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1842:17]
     wire fw_halted_ns : UInt<1>
     fw_halted_ns <= UInt<1>("h00")
     reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1844:48]
     fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1844:48]
-    node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34]
-    node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49]
-    node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1845:47]
-    fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1845:15]
-    node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29]
-    node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57]
-    node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1846:37]
-    node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1846:62]
-    node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1846:18]
-    mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1846:12]
-    reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44]
-    _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44]
-    mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1848:9]
-    node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10]
-    mpmc <= _T_514 @[dec_tlu_ctl.scala 1851:7]
-    node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40]
-    node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48]
-    node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92]
-    node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1860:19]
-    node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63]
-    node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70]
-    node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1862:41]
-    node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58]
-    node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1863:23]
-    node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1863:23]
-    micect_inc <= _T_522 @[dec_tlu_ctl.scala 1863:13]
-    node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35]
-    node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75]
-    node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58]
-    node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95]
-    node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58]
-    node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1864:22]
-    node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42]
-    node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1866:61]
+    node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34]
+    node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49]
+    node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1845:47]
+    fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1845:15]
+    node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29]
+    node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57]
+    node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1846:37]
+    node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1846:62]
+    node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1846:18]
+    mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1846:12]
+    reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44]
+    _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44]
+    mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1848:9]
+    node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10]
+    mpmc <= _T_504 @[dec_tlu_ctl.scala 1851:7]
+    node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40]
+    node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48]
+    node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92]
+    node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1860:19]
+    node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63]
+    node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70]
+    node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1862:41]
+    node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58]
+    node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1863:23]
+    node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1863:23]
+    micect_inc <= _T_512 @[dec_tlu_ctl.scala 1863:13]
+    node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35]
+    node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75]
+    node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58]
+    node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95]
+    node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58]
+    node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1864:22]
+    node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42]
+    node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1866:61]
     inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23]
     rvclkhdr_12.clock <= clock
     rvclkhdr_12.reset <= reset
     rvclkhdr_12.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17]
+    rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17]
     rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_530 <= micect_ns @[lib.scala 374:16]
-    micect <= _T_530 @[dec_tlu_ctl.scala 1866:9]
-    node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48]
-    node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1868:39]
-    node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79]
-    node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58]
-    node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1868:57]
-    node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1868:88]
-    mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1868:14]
-    node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69]
-    node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76]
-    node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1877:47]
-    node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26]
-    node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70]
-    node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58]
-    node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1878:33]
-    node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1878:33]
-    miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1878:15]
-    node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45]
-    node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85]
-    node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58]
-    node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107]
-    node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58]
-    node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1879:30]
-    node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48]
-    node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69]
-    node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1881:93]
+    reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_520 <= micect_ns @[lib.scala 374:16]
+    micect <= _T_520 @[dec_tlu_ctl.scala 1866:9]
+    node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48]
+    node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1868:39]
+    node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79]
+    node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58]
+    node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1868:57]
+    node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1868:88]
+    mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1868:14]
+    node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69]
+    node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76]
+    node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1877:47]
+    node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26]
+    node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70]
+    node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58]
+    node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1878:33]
+    node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1878:33]
+    miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1878:15]
+    node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45]
+    node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85]
+    node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58]
+    node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107]
+    node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58]
+    node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1879:30]
+    node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48]
+    node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69]
+    node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1881:93]
     inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23]
     rvclkhdr_13.clock <= clock
     rvclkhdr_13.reset <= reset
     rvclkhdr_13.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17]
+    rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17]
     rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_552 <= miccmect_ns @[lib.scala 374:16]
-    miccmect <= _T_552 @[dec_tlu_ctl.scala 1881:11]
-    node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51]
-    node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1883:40]
-    node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84]
-    node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58]
-    node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1883:60]
-    node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1883:93]
-    miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1883:15]
-    node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69]
-    node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76]
-    node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1892:47]
-    node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26]
-    node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
-    node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1893:33]
-    node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1893:33]
-    mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1893:15]
-    node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45]
-    node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85]
-    node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58]
-    node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107]
-    node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58]
-    node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1894:30]
-    node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49]
-    node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1896:81]
+    reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_542 <= miccmect_ns @[lib.scala 374:16]
+    miccmect <= _T_542 @[dec_tlu_ctl.scala 1881:11]
+    node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51]
+    node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1883:40]
+    node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84]
+    node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58]
+    node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1883:60]
+    node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1883:93]
+    miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1883:15]
+    node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69]
+    node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76]
+    node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1892:47]
+    node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26]
+    node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
+    node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1893:33]
+    node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1893:33]
+    mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1893:15]
+    node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45]
+    node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85]
+    node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58]
+    node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107]
+    node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58]
+    node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1894:30]
+    node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49]
+    node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1896:81]
     inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23]
     rvclkhdr_14.clock <= clock
     rvclkhdr_14.reset <= reset
     rvclkhdr_14.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17]
+    rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17]
     rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_572 <= mdccmect_ns @[lib.scala 374:16]
-    mdccmect <= _T_572 @[dec_tlu_ctl.scala 1896:11]
-    node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52]
-    node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1898:41]
-    node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85]
-    node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58]
-    node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1898:61]
-    node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1898:94]
-    mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1898:16]
-    node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62]
-    node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69]
-    node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1908:40]
-    node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32]
-    node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59]
-    node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1910:20]
-    reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43]
-    _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43]
-    mfdht <= _T_583 @[dec_tlu_ctl.scala 1912:8]
-    node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62]
-    node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69]
-    node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1921:40]
-    node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32]
-    node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60]
-    node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43]
-    node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1924:41]
-    node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1924:65]
-    node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78]
-    node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98]
-    node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58]
-    node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1924:21]
-    node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1923:20]
-    node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71]
-    node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1926:92]
-    reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_596 : @[Reg.scala 28:19]
-      _T_597 <= mfdhs_ns @[Reg.scala 28:23]
+    reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_562 <= mdccmect_ns @[lib.scala 374:16]
+    mdccmect <= _T_562 @[dec_tlu_ctl.scala 1896:11]
+    node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52]
+    node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1898:41]
+    node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85]
+    node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58]
+    node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1898:61]
+    node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1898:94]
+    mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1898:16]
+    node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62]
+    node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69]
+    node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1908:40]
+    node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32]
+    node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59]
+    node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1910:20]
+    reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43]
+    _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43]
+    mfdht <= _T_573 @[dec_tlu_ctl.scala 1912:8]
+    node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62]
+    node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69]
+    node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1921:40]
+    node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32]
+    node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60]
+    node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43]
+    node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1924:41]
+    node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1924:65]
+    node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78]
+    node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98]
+    node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58]
+    node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1924:21]
+    node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1923:20]
+    node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71]
+    node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1926:92]
+    reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_586 : @[Reg.scala 28:19]
+      _T_587 <= mfdhs_ns @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    mfdhs <= _T_597 @[dec_tlu_ctl.scala 1926:8]
-    node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47]
-    node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74]
-    node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1928:74]
-    node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48]
-    node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27]
-    node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1928:26]
-    node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81]
-    reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_603 : @[Reg.scala 28:19]
-      _T_604 <= force_halt_ctr @[Reg.scala 28:23]
+    mfdhs <= _T_587 @[dec_tlu_ctl.scala 1926:8]
+    node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47]
+    node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74]
+    node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1928:74]
+    node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48]
+    node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27]
+    node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1928:26]
+    node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81]
+    reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_593 : @[Reg.scala 28:19]
+      _T_594 <= force_halt_ctr @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1931:19]
-    node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24]
-    node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79]
-    node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1933:71]
-    node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1933:48]
-    node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1933:87]
-    node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1933:28]
-    io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1933:16]
-    node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62]
-    node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69]
-    node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1941:40]
-    node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40]
-    node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59]
+    force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1931:19]
+    node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24]
+    node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79]
+    node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1933:71]
+    node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1933:48]
+    node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1933:87]
+    node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1933:28]
+    io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1933:16]
+    node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62]
+    node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69]
+    node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1941:40]
+    node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40]
+    node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59]
     inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23]
     rvclkhdr_15.clock <= clock
     rvclkhdr_15.reset <= reset
     rvclkhdr_15.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17]
+    rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17]
     rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    meivt <= _T_613 @[lib.scala 374:16]
-    node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49]
+    meivt <= _T_603 @[lib.scala 374:16]
+    node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49]
     inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23]
     rvclkhdr_16.clock <= clock
     rvclkhdr_16.reset <= reset
     rvclkhdr_16.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17]
+    rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17]
     rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     meihap <= io.pic_claimid @[lib.scala 374:16]
-    node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58]
-    io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1956:20]
-    node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65]
-    node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72]
-    node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1965:43]
-    node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38]
-    node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65]
-    node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1966:23]
-    reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46]
-    _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46]
-    meicurpl <= _T_621 @[dec_tlu_ctl.scala 1968:11]
+    node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58]
+    io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1956:20]
+    node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65]
+    node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72]
+    node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1965:43]
+    node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38]
+    node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65]
+    node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1966:23]
+    reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46]
+    _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46]
+    meicurpl <= _T_611 @[dec_tlu_ctl.scala 1968:11]
     io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1970:22]
-    node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66]
-    node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73]
-    node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1980:44]
-    node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88]
-    node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37]
-    node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38]
-    node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65]
-    node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1983:23]
-    node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1982:23]
-    reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44]
-    _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44]
-    meicidpl <= _T_629 @[dec_tlu_ctl.scala 1985:11]
-    node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62]
-    node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69]
-    node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1992:40]
-    node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83]
-    wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1992:15]
-    node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62]
-    node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69]
-    node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 2001:40]
-    node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32]
-    node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59]
-    node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2002:20]
-    reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43]
-    _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2004:43]
-    meipt <= _T_638 @[dec_tlu_ctl.scala 2004:8]
+    node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66]
+    node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73]
+    node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1980:44]
+    node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88]
+    node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37]
+    node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38]
+    node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65]
+    node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1983:23]
+    node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1982:23]
+    reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44]
+    _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44]
+    meicidpl <= _T_619 @[dec_tlu_ctl.scala 1985:11]
+    node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62]
+    node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69]
+    node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1992:40]
+    node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83]
+    wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1992:15]
+    node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62]
+    node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69]
+    node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2001:40]
+    node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32]
+    node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59]
+    node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2002:20]
+    reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43]
+    _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2004:43]
+    meipt <= _T_628 @[dec_tlu_ctl.scala 2004:8]
     io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2006:19]
-    node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89]
-    node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2032:66]
-    node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31]
-    node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2035:29]
-    node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63]
-    node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2035:61]
-    node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98]
-    node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2035:96]
-    node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2035:118]
-    node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48]
-    node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2036:46]
-    node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80]
-    node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2036:78]
-    node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2036:114]
-    node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77]
-    node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2037:75]
-    node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2037:111]
-    node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108]
-    node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72]
-    node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72]
-    node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72]
+    node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89]
+    node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2032:66]
+    node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31]
+    node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2035:29]
+    node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63]
+    node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2035:61]
+    node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98]
+    node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2035:96]
+    node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2035:118]
+    node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48]
+    node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2036:46]
+    node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80]
+    node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2036:78]
+    node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2036:114]
+    node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77]
+    node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2037:75]
+    node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2037:111]
+    node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108]
+    node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72]
+    node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72]
+    node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72]
     wire dcsr_cause : UInt<3> @[Mux.scala 27:72]
-    dcsr_cause <= _T_662 @[Mux.scala 27:72]
-    node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46]
-    node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91]
-    node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98]
-    node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2040:69]
-    node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69]
-    node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75]
-    node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2046:59]
-    node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59]
-    node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78]
-    node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2047:56]
+    dcsr_cause <= _T_652 @[Mux.scala 27:72]
+    node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46]
+    node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91]
+    node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98]
+    node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2040:69]
+    node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69]
+    node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75]
+    node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2046:59]
+    node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59]
+    node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78]
+    node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2047:56]
     node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2049:48]
-    node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44]
-    node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64]
-    node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91]
+    node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44]
+    node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64]
+    node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91]
+    node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58]
+    node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58]
+    node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58]
+    node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18]
+    node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49]
+    node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84]
+    node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110]
+    node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154]
+    node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2051:145]
+    node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178]
     node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58]
-    node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58]
+    node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58]
     node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58]
-    node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18]
-    node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49]
-    node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84]
-    node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110]
-    node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154]
-    node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2051:145]
-    node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178]
+    node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58]
+    node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58]
+    node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58]
+    node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58]
+    node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211]
+    node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245]
     node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58]
-    node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58]
+    node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58]
     node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58]
-    node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58]
-    node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58]
-    node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58]
-    node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58]
-    node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211]
-    node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245]
-    node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58]
-    node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58]
-    node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58]
-    node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2051:7]
-    node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2050:19]
-    node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54]
-    node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66]
-    node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2053:94]
-    node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2053:109]
+    node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2051:7]
+    node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2050:19]
+    node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54]
+    node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66]
+    node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2053:94]
+    node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2053:109]
     inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23]
     rvclkhdr_17.clock <= clock
     rvclkhdr_17.reset <= reset
     rvclkhdr_17.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17]
+    rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17]
     rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_701 <= dcsr_ns @[lib.scala 374:16]
-    io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2053:10]
-    node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45]
-    node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90]
-    node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97]
-    node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2061:68]
-    node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44]
-    node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2062:42]
-    node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67]
-    node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2062:65]
-    node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21]
-    node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39]
-    node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2066:37]
-    node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56]
-    node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2066:68]
-    node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97]
-    node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68]
-    node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33]
-    node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49]
-    node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2068:68]
-    node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72]
-    node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72]
+    reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_691 <= dcsr_ns @[lib.scala 374:16]
+    io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2053:10]
+    node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45]
+    node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90]
+    node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97]
+    node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2061:68]
+    node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44]
+    node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2062:42]
+    node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67]
+    node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2062:65]
+    node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21]
+    node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39]
+    node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2066:37]
+    node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56]
+    node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2066:68]
+    node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97]
+    node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68]
+    node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33]
+    node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49]
+    node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2068:68]
+    node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72]
+    node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72]
     wire dpc_ns : UInt<31> @[Mux.scala 27:72]
-    dpc_ns <= _T_722 @[Mux.scala 27:72]
-    node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36]
-    node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53]
-    node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2070:72]
+    dpc_ns <= _T_712 @[Mux.scala 27:72]
+    node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36]
+    node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53]
+    node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2070:72]
     inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23]
     rvclkhdr_18.clock <= clock
     rvclkhdr_18.reset <= reset
     rvclkhdr_18.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17]
+    rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17]
     rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_726 <= dpc_ns @[lib.scala 374:16]
-    io.dpc <= _T_726 @[dec_tlu_ctl.scala 2070:9]
-    node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43]
-    node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68]
-    node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96]
-    node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58]
-    node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58]
-    node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50]
-    node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95]
-    node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102]
-    node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2085:73]
-    node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50]
+    reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_716 <= dpc_ns @[lib.scala 374:16]
+    io.dpc <= _T_716 @[dec_tlu_ctl.scala 2070:9]
+    node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43]
+    node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68]
+    node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96]
+    node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58]
+    node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58]
+    node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50]
+    node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95]
+    node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102]
+    node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2085:73]
+    node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50]
     inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23]
     rvclkhdr_19.clock <= clock
     rvclkhdr_19.reset <= reset
     rvclkhdr_19.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17]
+    rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17]
     rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     dicawics <= dicawics_ns @[lib.scala 374:16]
-    node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48]
-    node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93]
-    node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100]
-    node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2103:71]
-    node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34]
-    node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21]
-    node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46]
-    node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2106:79]
+    node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48]
+    node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93]
+    node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100]
+    node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2103:71]
+    node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34]
+    node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21]
+    node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46]
+    node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2106:79]
     inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23]
     rvclkhdr_20.clock <= clock
     rvclkhdr_20.reset <= reset
     rvclkhdr_20.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17]
+    rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17]
     rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     dicad0 <= dicad0_ns @[lib.scala 374:16]
-    node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49]
-    node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94]
-    node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101]
-    node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2116:72]
-    node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36]
-    node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88]
-    node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2118:22]
-    node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48]
-    node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2120:81]
+    node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49]
+    node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94]
+    node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101]
+    node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2116:72]
+    node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36]
+    node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88]
+    node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2118:22]
+    node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48]
+    node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2120:81]
     inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23]
     rvclkhdr_21.clock <= clock
     rvclkhdr_21.reset <= reset
     rvclkhdr_21.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17]
+    rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17]
     rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
     reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
     dicad0h <= dicad0h_ns @[lib.scala 374:16]
-    wire _T_748 : UInt<7>
-    _T_748 <= UInt<1>("h00")
-    node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2128:48]
-    node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2128:93]
-    node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100]
-    node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2128:71]
-    node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2130:34]
-    node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61]
-    node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91]
-    node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2130:21]
-    node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78]
-    node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2132:111]
-    reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_758 : @[Reg.scala 28:19]
-      _T_759 <= _T_756 @[Reg.scala 28:23]
+    wire _T_738 : UInt<7>
+    _T_738 <= UInt<1>("h00")
+    node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2128:48]
+    node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2128:93]
+    node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100]
+    node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2128:71]
+    node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2130:34]
+    node _T_744 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61]
+    node _T_745 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91]
+    node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2130:21]
+    node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78]
+    node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2132:111]
+    reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_748 : @[Reg.scala 28:19]
+      _T_749 <= _T_746 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    _T_748 <= _T_759 @[dec_tlu_ctl.scala 2132:13]
-    node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58]
-    dicad1 <= _T_760 @[dec_tlu_ctl.scala 2133:9]
-    node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69]
-    node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83]
-    node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97]
-    node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58]
-    node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58]
-    io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2155:56]
+    _T_738 <= _T_749 @[dec_tlu_ctl.scala 2132:13]
+    node _T_750 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58]
+    dicad1 <= _T_750 @[dec_tlu_ctl.scala 2133:9]
+    node _T_751 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69]
+    node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83]
+    node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97]
+    node _T_754 = cat(_T_751, _T_752) @[Cat.scala 29:58]
+    node _T_755 = cat(_T_754, _T_753) @[Cat.scala 29:58]
+    io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_755 @[dec_tlu_ctl.scala 2155:56]
     io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2158:41]
-    node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52]
-    node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75]
-    node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98]
-    node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2160:96]
-    node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142]
-    node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149]
-    node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2160:120]
-    node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52]
-    node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97]
-    node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104]
-    node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2161:75]
+    node _T_756 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52]
+    node _T_757 = and(_T_756, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75]
+    node _T_758 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98]
+    node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2160:96]
+    node _T_760 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142]
+    node _T_761 = eq(_T_760, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149]
+    node icache_rd_valid = and(_T_759, _T_761) @[dec_tlu_ctl.scala 2160:120]
+    node _T_762 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52]
+    node _T_763 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97]
+    node _T_764 = eq(_T_763, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104]
+    node icache_wr_valid = and(_T_762, _T_764) @[dec_tlu_ctl.scala 2161:75]
     reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58]
     icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2163:58]
     reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2164:58]
     icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2164:58]
     io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2166:41]
     io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2167:41]
-    node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62]
-    node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69]
-    node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2175:40]
-    node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32]
-    node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59]
-    node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2176:20]
-    reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43]
-    _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43]
-    mtsel <= _T_779 @[dec_tlu_ctl.scala 2178:8]
-    node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38]
-    node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64]
-    node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2213:44]
-    node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2213:42]
-    node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40]
-    node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66]
-    node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2215:46]
-    node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2215:44]
-    node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41]
-    node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46]
-    node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90]
-    node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2217:69]
-    node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47]
-    node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52]
-    node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94]
-    node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136]
-    node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43]
-    node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83]
-    node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58]
-    node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58]
-    node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58]
-    node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58]
-    node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58]
-    node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58]
-    node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58]
-    node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
-    node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
-    node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2223:70]
-    node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121]
-    node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2223:112]
-    node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154]
-    node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2223:138]
-    node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
-    node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2223:135]
-    node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
-    node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
-    node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2223:70]
-    node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121]
-    node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2223:112]
-    node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154]
-    node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2223:138]
-    node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
-    node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2223:135]
-    node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
-    node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
-    node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2223:70]
-    node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121]
-    node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2223:112]
-    node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154]
-    node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2223:138]
-    node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
-    node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2223:135]
-    node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
-    node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
-    node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2223:70]
-    node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121]
-    node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2223:112]
-    node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154]
-    node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2223:138]
-    node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
-    node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2223:135]
+    node _T_765 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62]
+    node _T_766 = eq(_T_765, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69]
+    node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_766) @[dec_tlu_ctl.scala 2175:40]
+    node _T_767 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32]
+    node _T_768 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59]
+    node mtsel_ns = mux(_T_767, _T_768, mtsel) @[dec_tlu_ctl.scala 2176:20]
+    reg _T_769 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43]
+    _T_769 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43]
+    mtsel <= _T_769 @[dec_tlu_ctl.scala 2178:8]
+    node _T_770 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38]
+    node _T_771 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64]
+    node _T_772 = not(_T_771) @[dec_tlu_ctl.scala 2213:44]
+    node tdata_load = and(_T_770, _T_772) @[dec_tlu_ctl.scala 2213:42]
+    node _T_773 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40]
+    node _T_774 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66]
+    node _T_775 = not(_T_774) @[dec_tlu_ctl.scala 2215:46]
+    node tdata_opcode = and(_T_773, _T_775) @[dec_tlu_ctl.scala 2215:44]
+    node _T_776 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41]
+    node _T_777 = and(_T_776, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46]
+    node _T_778 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90]
+    node tdata_action = and(_T_777, _T_778) @[dec_tlu_ctl.scala 2217:69]
+    node _T_779 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47]
+    node _T_780 = and(_T_779, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52]
+    node _T_781 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94]
+    node _T_782 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136]
+    node _T_783 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43]
+    node _T_784 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83]
+    node _T_785 = cat(_T_784, tdata_load) @[Cat.scala 29:58]
+    node _T_786 = cat(_T_783, tdata_opcode) @[Cat.scala 29:58]
+    node _T_787 = cat(_T_786, _T_785) @[Cat.scala 29:58]
+    node _T_788 = cat(tdata_action, _T_782) @[Cat.scala 29:58]
+    node _T_789 = cat(_T_780, _T_781) @[Cat.scala 29:58]
+    node _T_790 = cat(_T_789, _T_788) @[Cat.scala 29:58]
+    node tdata_wrdata_r = cat(_T_790, _T_787) @[Cat.scala 29:58]
+    node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
+    node _T_792 = eq(_T_791, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
+    node _T_793 = and(io.dec_csr_wen_r_mod, _T_792) @[dec_tlu_ctl.scala 2223:70]
+    node _T_794 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121]
+    node _T_795 = and(_T_793, _T_794) @[dec_tlu_ctl.scala 2223:112]
+    node _T_796 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154]
+    node _T_797 = not(_T_796) @[dec_tlu_ctl.scala 2223:138]
+    node _T_798 = or(_T_797, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
+    node _T_799 = and(_T_795, _T_798) @[dec_tlu_ctl.scala 2223:135]
+    node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
+    node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
+    node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2223:70]
+    node _T_803 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121]
+    node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2223:112]
+    node _T_805 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154]
+    node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2223:138]
+    node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
+    node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2223:135]
+    node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
+    node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
+    node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2223:70]
+    node _T_812 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121]
+    node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2223:112]
+    node _T_814 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154]
+    node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2223:138]
+    node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
+    node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2223:135]
+    node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92]
+    node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99]
+    node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2223:70]
+    node _T_821 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121]
+    node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2223:112]
+    node _T_823 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154]
+    node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2223:138]
+    node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170]
+    node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2223:135]
     wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2223:42]
-    wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2223:42]
-    wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2223:42]
-    wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2223:42]
-    wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2223:42]
-    node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68]
-    node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111]
-    node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135]
-    node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156]
-    node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2224:139]
-    node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176]
-    node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58]
-    node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58]
-    node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2224:49]
-    node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68]
-    node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111]
-    node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135]
-    node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156]
-    node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2224:139]
-    node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176]
-    node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58]
-    node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58]
-    node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2224:49]
-    node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68]
-    node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111]
-    node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135]
-    node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156]
-    node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2224:139]
-    node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176]
-    node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58]
-    node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58]
-    node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2224:49]
-    node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68]
-    node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111]
-    node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135]
-    node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156]
-    node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2224:139]
-    node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176]
-    node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58]
-    node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58]
-    node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2224:49]
+    wr_mtdata1_t_r[0] <= _T_799 @[dec_tlu_ctl.scala 2223:42]
+    wr_mtdata1_t_r[1] <= _T_808 @[dec_tlu_ctl.scala 2223:42]
+    wr_mtdata1_t_r[2] <= _T_817 @[dec_tlu_ctl.scala 2223:42]
+    wr_mtdata1_t_r[3] <= _T_826 @[dec_tlu_ctl.scala 2223:42]
+    node _T_827 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68]
+    node _T_828 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111]
+    node _T_829 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135]
+    node _T_830 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156]
+    node _T_831 = or(_T_829, _T_830) @[dec_tlu_ctl.scala 2224:139]
+    node _T_832 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176]
+    node _T_833 = cat(_T_828, _T_831) @[Cat.scala 29:58]
+    node _T_834 = cat(_T_833, _T_832) @[Cat.scala 29:58]
+    node _T_835 = mux(_T_827, tdata_wrdata_r, _T_834) @[dec_tlu_ctl.scala 2224:49]
+    node _T_836 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68]
+    node _T_837 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111]
+    node _T_838 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135]
+    node _T_839 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156]
+    node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2224:139]
+    node _T_841 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176]
+    node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58]
+    node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58]
+    node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2224:49]
+    node _T_845 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68]
+    node _T_846 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111]
+    node _T_847 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135]
+    node _T_848 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156]
+    node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2224:139]
+    node _T_850 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176]
+    node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58]
+    node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58]
+    node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2224:49]
+    node _T_854 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68]
+    node _T_855 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111]
+    node _T_856 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135]
+    node _T_857 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156]
+    node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2224:139]
+    node _T_859 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176]
+    node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58]
+    node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58]
+    node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2224:49]
     wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2224:40]
-    mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2224:40]
-    mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2224:40]
-    mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2224:40]
-    mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2224:40]
-    reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
-    _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74]
-    io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2226:39]
-    reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
-    _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74]
-    io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2226:39]
-    reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
-    _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74]
-    io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2226:39]
-    reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
-    _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74]
-    io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2226:39]
-    node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58]
-    node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104]
-    node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142]
-    node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174]
-    node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206]
-    node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238]
-    node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58]
-    node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58]
-    node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58]
-    node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58]
-    node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58]
-    node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58]
-    node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58]
-    node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58]
-    node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58]
-    node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104]
-    node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142]
-    node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174]
-    node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206]
-    node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238]
-    node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58]
-    node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58]
-    node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58]
-    node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58]
-    node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58]
-    node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58]
-    node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58]
-    node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58]
-    node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58]
-    node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104]
-    node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142]
-    node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174]
-    node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206]
-    node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238]
-    node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58]
-    node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58]
-    node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58]
-    node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58]
-    node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58]
-    node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58]
-    node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58]
-    node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58]
-    node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58]
-    node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104]
-    node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142]
-    node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174]
-    node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206]
-    node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238]
-    node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58]
-    node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58]
-    node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58]
-    node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58]
-    node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58]
-    node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58]
-    node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58]
-    node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58]
-    node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72]
-    node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72]
-    node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72]
+    mtdata1_t_ns[0] <= _T_835 @[dec_tlu_ctl.scala 2224:40]
+    mtdata1_t_ns[1] <= _T_844 @[dec_tlu_ctl.scala 2224:40]
+    mtdata1_t_ns[2] <= _T_853 @[dec_tlu_ctl.scala 2224:40]
+    mtdata1_t_ns[3] <= _T_862 @[dec_tlu_ctl.scala 2224:40]
+    reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
+    _T_863 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74]
+    io.mtdata1_t[0] <= _T_863 @[dec_tlu_ctl.scala 2226:39]
+    reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
+    _T_864 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74]
+    io.mtdata1_t[1] <= _T_864 @[dec_tlu_ctl.scala 2226:39]
+    reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
+    _T_865 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74]
+    io.mtdata1_t[2] <= _T_865 @[dec_tlu_ctl.scala 2226:39]
+    reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74]
+    _T_866 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74]
+    io.mtdata1_t[3] <= _T_866 @[dec_tlu_ctl.scala 2226:39]
+    node _T_867 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58]
+    node _T_868 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104]
+    node _T_869 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142]
+    node _T_870 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174]
+    node _T_871 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206]
+    node _T_872 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238]
+    node _T_873 = cat(UInt<3>("h00"), _T_872) @[Cat.scala 29:58]
+    node _T_874 = cat(_T_870, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_875 = cat(_T_874, _T_871) @[Cat.scala 29:58]
+    node _T_876 = cat(_T_875, _T_873) @[Cat.scala 29:58]
+    node _T_877 = cat(_T_869, UInt<6>("h00")) @[Cat.scala 29:58]
+    node _T_878 = cat(UInt<4>("h02"), _T_868) @[Cat.scala 29:58]
+    node _T_879 = cat(_T_878, UInt<6>("h01f")) @[Cat.scala 29:58]
+    node _T_880 = cat(_T_879, _T_877) @[Cat.scala 29:58]
+    node _T_881 = cat(_T_880, _T_876) @[Cat.scala 29:58]
+    node _T_882 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58]
+    node _T_883 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104]
+    node _T_884 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142]
+    node _T_885 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174]
+    node _T_886 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206]
+    node _T_887 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238]
+    node _T_888 = cat(UInt<3>("h00"), _T_887) @[Cat.scala 29:58]
+    node _T_889 = cat(_T_885, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_890 = cat(_T_889, _T_886) @[Cat.scala 29:58]
+    node _T_891 = cat(_T_890, _T_888) @[Cat.scala 29:58]
+    node _T_892 = cat(_T_884, UInt<6>("h00")) @[Cat.scala 29:58]
+    node _T_893 = cat(UInt<4>("h02"), _T_883) @[Cat.scala 29:58]
+    node _T_894 = cat(_T_893, UInt<6>("h01f")) @[Cat.scala 29:58]
+    node _T_895 = cat(_T_894, _T_892) @[Cat.scala 29:58]
+    node _T_896 = cat(_T_895, _T_891) @[Cat.scala 29:58]
+    node _T_897 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58]
+    node _T_898 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104]
+    node _T_899 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142]
+    node _T_900 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174]
+    node _T_901 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206]
+    node _T_902 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238]
+    node _T_903 = cat(UInt<3>("h00"), _T_902) @[Cat.scala 29:58]
+    node _T_904 = cat(_T_900, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_905 = cat(_T_904, _T_901) @[Cat.scala 29:58]
+    node _T_906 = cat(_T_905, _T_903) @[Cat.scala 29:58]
+    node _T_907 = cat(_T_899, UInt<6>("h00")) @[Cat.scala 29:58]
+    node _T_908 = cat(UInt<4>("h02"), _T_898) @[Cat.scala 29:58]
+    node _T_909 = cat(_T_908, UInt<6>("h01f")) @[Cat.scala 29:58]
+    node _T_910 = cat(_T_909, _T_907) @[Cat.scala 29:58]
+    node _T_911 = cat(_T_910, _T_906) @[Cat.scala 29:58]
+    node _T_912 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58]
+    node _T_913 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104]
+    node _T_914 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142]
+    node _T_915 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174]
+    node _T_916 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206]
+    node _T_917 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238]
+    node _T_918 = cat(UInt<3>("h00"), _T_917) @[Cat.scala 29:58]
+    node _T_919 = cat(_T_915, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_920 = cat(_T_919, _T_916) @[Cat.scala 29:58]
+    node _T_921 = cat(_T_920, _T_918) @[Cat.scala 29:58]
+    node _T_922 = cat(_T_914, UInt<6>("h00")) @[Cat.scala 29:58]
+    node _T_923 = cat(UInt<4>("h02"), _T_913) @[Cat.scala 29:58]
+    node _T_924 = cat(_T_923, UInt<6>("h01f")) @[Cat.scala 29:58]
+    node _T_925 = cat(_T_924, _T_922) @[Cat.scala 29:58]
+    node _T_926 = cat(_T_925, _T_921) @[Cat.scala 29:58]
+    node _T_927 = mux(_T_867, _T_881, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_928 = mux(_T_882, _T_896, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_929 = mux(_T_897, _T_911, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_930 = mux(_T_912, _T_926, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_931 = or(_T_927, _T_928) @[Mux.scala 27:72]
+    node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72]
+    node _T_933 = or(_T_932, _T_930) @[Mux.scala 27:72]
     wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72]
-    mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72]
-    node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58]
-    io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2231:40]
-    node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61]
-    io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2232:43]
-    node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58]
-    io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2233:40]
-    node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58]
-    io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2234:40]
-    node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58]
-    io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2235:40]
-    node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58]
-    io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2236:40]
-    node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58]
-    io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2231:40]
-    node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61]
-    io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2232:43]
-    node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58]
-    io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2233:40]
-    node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58]
-    io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2234:40]
-    node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58]
-    io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2235:40]
-    node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58]
-    io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2236:40]
-    node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58]
-    io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2231:40]
-    node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61]
-    io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2232:43]
-    node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58]
-    io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2233:40]
-    node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58]
-    io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2234:40]
-    node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58]
-    io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2235:40]
-    node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58]
-    io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2236:40]
-    node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58]
-    io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2231:40]
-    node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61]
-    io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2232:43]
-    node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58]
-    io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2233:40]
-    node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58]
-    io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2234:40]
-    node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58]
-    io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2235:40]
-    node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58]
-    io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2236:40]
-    node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
-    node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
-    node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2243:69]
-    node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120]
-    node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2243:111]
-    node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153]
-    node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2243:137]
-    node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
-    node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2243:134]
-    node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
-    node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
-    node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2243:69]
-    node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120]
-    node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2243:111]
-    node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153]
-    node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2243:137]
-    node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
-    node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2243:134]
-    node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
-    node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
-    node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2243:69]
-    node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120]
-    node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2243:111]
-    node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153]
-    node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2243:137]
-    node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
-    node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2243:134]
-    node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
-    node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
-    node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2243:69]
-    node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120]
-    node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2243:111]
-    node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153]
-    node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2243:137]
-    node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
-    node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2243:134]
+    mtdata1_tsel_out <= _T_933 @[Mux.scala 27:72]
+    node _T_934 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58]
+    io.trigger_pkt_any[0].select <= _T_934 @[dec_tlu_ctl.scala 2231:40]
+    node _T_935 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61]
+    io.trigger_pkt_any[0].match_pkt <= _T_935 @[dec_tlu_ctl.scala 2232:43]
+    node _T_936 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58]
+    io.trigger_pkt_any[0].store <= _T_936 @[dec_tlu_ctl.scala 2233:40]
+    node _T_937 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58]
+    io.trigger_pkt_any[0].load <= _T_937 @[dec_tlu_ctl.scala 2234:40]
+    node _T_938 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58]
+    io.trigger_pkt_any[0].execute <= _T_938 @[dec_tlu_ctl.scala 2235:40]
+    node _T_939 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58]
+    io.trigger_pkt_any[0].m <= _T_939 @[dec_tlu_ctl.scala 2236:40]
+    node _T_940 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58]
+    io.trigger_pkt_any[1].select <= _T_940 @[dec_tlu_ctl.scala 2231:40]
+    node _T_941 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61]
+    io.trigger_pkt_any[1].match_pkt <= _T_941 @[dec_tlu_ctl.scala 2232:43]
+    node _T_942 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58]
+    io.trigger_pkt_any[1].store <= _T_942 @[dec_tlu_ctl.scala 2233:40]
+    node _T_943 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58]
+    io.trigger_pkt_any[1].load <= _T_943 @[dec_tlu_ctl.scala 2234:40]
+    node _T_944 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58]
+    io.trigger_pkt_any[1].execute <= _T_944 @[dec_tlu_ctl.scala 2235:40]
+    node _T_945 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58]
+    io.trigger_pkt_any[1].m <= _T_945 @[dec_tlu_ctl.scala 2236:40]
+    node _T_946 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58]
+    io.trigger_pkt_any[2].select <= _T_946 @[dec_tlu_ctl.scala 2231:40]
+    node _T_947 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61]
+    io.trigger_pkt_any[2].match_pkt <= _T_947 @[dec_tlu_ctl.scala 2232:43]
+    node _T_948 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58]
+    io.trigger_pkt_any[2].store <= _T_948 @[dec_tlu_ctl.scala 2233:40]
+    node _T_949 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58]
+    io.trigger_pkt_any[2].load <= _T_949 @[dec_tlu_ctl.scala 2234:40]
+    node _T_950 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58]
+    io.trigger_pkt_any[2].execute <= _T_950 @[dec_tlu_ctl.scala 2235:40]
+    node _T_951 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58]
+    io.trigger_pkt_any[2].m <= _T_951 @[dec_tlu_ctl.scala 2236:40]
+    node _T_952 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58]
+    io.trigger_pkt_any[3].select <= _T_952 @[dec_tlu_ctl.scala 2231:40]
+    node _T_953 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61]
+    io.trigger_pkt_any[3].match_pkt <= _T_953 @[dec_tlu_ctl.scala 2232:43]
+    node _T_954 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58]
+    io.trigger_pkt_any[3].store <= _T_954 @[dec_tlu_ctl.scala 2233:40]
+    node _T_955 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58]
+    io.trigger_pkt_any[3].load <= _T_955 @[dec_tlu_ctl.scala 2234:40]
+    node _T_956 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58]
+    io.trigger_pkt_any[3].execute <= _T_956 @[dec_tlu_ctl.scala 2235:40]
+    node _T_957 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58]
+    io.trigger_pkt_any[3].m <= _T_957 @[dec_tlu_ctl.scala 2236:40]
+    node _T_958 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
+    node _T_959 = eq(_T_958, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
+    node _T_960 = and(io.dec_csr_wen_r_mod, _T_959) @[dec_tlu_ctl.scala 2243:69]
+    node _T_961 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120]
+    node _T_962 = and(_T_960, _T_961) @[dec_tlu_ctl.scala 2243:111]
+    node _T_963 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153]
+    node _T_964 = not(_T_963) @[dec_tlu_ctl.scala 2243:137]
+    node _T_965 = or(_T_964, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
+    node _T_966 = and(_T_962, _T_965) @[dec_tlu_ctl.scala 2243:134]
+    node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
+    node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
+    node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2243:69]
+    node _T_970 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120]
+    node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2243:111]
+    node _T_972 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153]
+    node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2243:137]
+    node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
+    node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2243:134]
+    node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
+    node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
+    node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2243:69]
+    node _T_979 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120]
+    node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2243:111]
+    node _T_981 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153]
+    node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2243:137]
+    node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
+    node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2243:134]
+    node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91]
+    node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98]
+    node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2243:69]
+    node _T_988 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120]
+    node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2243:111]
+    node _T_990 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153]
+    node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2243:137]
+    node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169]
+    node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2243:134]
     wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2243:42]
-    wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2243:42]
-    wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2243:42]
-    wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2243:42]
-    wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2243:42]
-    node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84]
+    wr_mtdata2_t_r[0] <= _T_966 @[dec_tlu_ctl.scala 2243:42]
+    wr_mtdata2_t_r[1] <= _T_975 @[dec_tlu_ctl.scala 2243:42]
+    wr_mtdata2_t_r[2] <= _T_984 @[dec_tlu_ctl.scala 2243:42]
+    wr_mtdata2_t_r[3] <= _T_993 @[dec_tlu_ctl.scala 2243:42]
+    node _T_994 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84]
     inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23]
     rvclkhdr_22.clock <= clock
     rvclkhdr_22.reset <= reset
     rvclkhdr_22.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17]
+    rvclkhdr_22.io.en <= _T_994 @[lib.scala 371:17]
     rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
-    mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2244:36]
-    node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84]
+    reg _T_995 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_995 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
+    mtdata2_t[0] <= _T_995 @[dec_tlu_ctl.scala 2244:36]
+    node _T_996 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84]
     inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23]
     rvclkhdr_23.clock <= clock
     rvclkhdr_23.reset <= reset
     rvclkhdr_23.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17]
+    rvclkhdr_23.io.en <= _T_996 @[lib.scala 371:17]
     rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
-    mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2244:36]
-    node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84]
+    reg _T_997 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_997 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
+    mtdata2_t[1] <= _T_997 @[dec_tlu_ctl.scala 2244:36]
+    node _T_998 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84]
     inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23]
     rvclkhdr_24.clock <= clock
     rvclkhdr_24.reset <= reset
     rvclkhdr_24.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17]
+    rvclkhdr_24.io.en <= _T_998 @[lib.scala 371:17]
     rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
-    mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2244:36]
-    node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84]
+    reg _T_999 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_999 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
+    mtdata2_t[2] <= _T_999 @[dec_tlu_ctl.scala 2244:36]
+    node _T_1000 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84]
     inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23]
     rvclkhdr_25.clock <= clock
     rvclkhdr_25.reset <= reset
     rvclkhdr_25.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17]
+    rvclkhdr_25.io.en <= _T_1000 @[lib.scala 371:17]
     rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
-    mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2244:36]
-    node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57]
-    node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57]
-    node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57]
-    node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57]
-    node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72]
-    node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72]
-    node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72]
+    reg _T_1001 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_1001 <= io.dec_csr_wrdata_r @[lib.scala 374:16]
+    mtdata2_t[3] <= _T_1001 @[dec_tlu_ctl.scala 2244:36]
+    node _T_1002 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57]
+    node _T_1003 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57]
+    node _T_1004 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57]
+    node _T_1005 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57]
+    node _T_1006 = mux(_T_1002, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1007 = mux(_T_1003, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1008 = mux(_T_1004, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1009 = mux(_T_1005, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1010 = or(_T_1006, _T_1007) @[Mux.scala 27:72]
+    node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72]
+    node _T_1012 = or(_T_1011, _T_1009) @[Mux.scala 27:72]
     wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72]
-    mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72]
+    mtdata2_tsel_out <= _T_1012 @[Mux.scala 27:72]
     io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2249:51]
     io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2249:51]
     io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2249:51]
@@ -74409,238 +74399,248 @@ circuit quasar_wrapper :
     mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2260:15]
     mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2261:15]
     mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2262:15]
-    node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2268:59]
+    node _T_1013 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
+    node _T_1014 = mux(_T_1013, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1014) @[dec_tlu_ctl.scala 2268:59]
     wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2269:24]
     wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2270:27]
-    node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38]
-    node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2274:24]
-    node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
-    node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2275:62]
-    node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
-    node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2276:62]
-    node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
-    node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2277:62]
-    node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
-    node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2278:62]
-    node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
-    node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2278:94]
-    node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
-    node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2279:62]
-    node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
-    node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2279:94]
-    node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
-    node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2279:115]
-    node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
-    node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2280:62]
-    node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
-    node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
-    node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2280:115]
-    node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
-    node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2281:62]
-    node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
-    node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2282:62]
-    node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
-    node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2283:62]
-    node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
-    node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2284:62]
-    node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
-    node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
-    node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2285:62]
-    node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
-    node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
-    node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2286:62]
-    node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
-    node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
-    node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2287:62]
-    node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
-    node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
-    node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2288:62]
-    node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
-    node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
-    node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
-    node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2289:62]
-    node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
-    node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
-    node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2289:101]
-    node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
-    node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2290:59]
-    node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
-    node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
-    node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2291:59]
-    node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
-    node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
-    node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2292:59]
-    node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
-    node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
-    node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2293:59]
-    node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
-    node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
-    node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2294:59]
-    node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
-    node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
-    node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2295:59]
-    node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
-    node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
-    node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2296:59]
-    node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
-    node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
-    node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2297:59]
-    node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
-    node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
-    node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2298:59]
-    node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
-    node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
-    node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2299:59]
-    node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
-    node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
-    node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2299:101]
-    node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
-    node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2300:62]
-    node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
-    node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
-    node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2301:62]
-    node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
-    node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
-    node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2302:62]
-    node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
-    node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
-    node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2303:62]
-    node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
-    node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2304:62]
-    node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
-    node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2305:62]
-    node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
-    node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2306:62]
-    node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
-    node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2307:62]
-    node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
-    node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2308:62]
-    node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
-    node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2309:62]
-    node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
-    node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2310:62]
-    node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
-    node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
-    node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
-    node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2311:62]
-    node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
-    node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
-    node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
-    node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2312:62]
-    node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
-    node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2313:62]
-    node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
-    node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2314:62]
-    node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
-    node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
-    node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
-    node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2315:62]
-    node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
-    node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2316:62]
-    node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
-    node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2317:62]
-    node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
-    node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2318:62]
-    node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
-    node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2319:62]
-    node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
-    node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2320:62]
-    node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
-    node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2321:62]
-    node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
-    node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2322:62]
-    node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2322:73]
-    node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
-    node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2323:62]
-    node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2323:73]
-    node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
-    node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
-    node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2323:113]
-    node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2323:125]
-    node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2323:98]
-    node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
-    node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2324:62]
-    node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
-    node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
-    node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2325:62]
-    node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
-    node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
-    node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2326:62]
-    node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
-    node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
-    node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2328:62]
-    node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
-    node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2329:62]
-    node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
-    node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2330:62]
-    node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
-    node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2331:62]
-    node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
-    node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2332:62]
-    node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72]
+    node _T_1015 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38]
+    node _T_1016 = not(_T_1015) @[dec_tlu_ctl.scala 2274:24]
+    node _T_1017 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
+    node _T_1018 = bits(_T_1017, 0, 0) @[dec_tlu_ctl.scala 2275:62]
+    node _T_1019 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
+    node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2276:62]
+    node _T_1021 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
+    node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2277:62]
+    node _T_1023 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
+    node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2278:62]
+    node _T_1025 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
+    node _T_1026 = and(io.tlu_i0_commit_cmt, _T_1025) @[dec_tlu_ctl.scala 2278:94]
+    node _T_1027 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
+    node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2279:62]
+    node _T_1029 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
+    node _T_1030 = and(io.tlu_i0_commit_cmt, _T_1029) @[dec_tlu_ctl.scala 2279:94]
+    node _T_1031 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
+    node _T_1032 = and(_T_1030, _T_1031) @[dec_tlu_ctl.scala 2279:115]
+    node _T_1033 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
+    node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2280:62]
+    node _T_1035 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
+    node _T_1036 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
+    node _T_1037 = and(_T_1035, _T_1036) @[dec_tlu_ctl.scala 2280:115]
+    node _T_1038 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
+    node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2281:62]
+    node _T_1040 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
+    node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2282:62]
+    node _T_1042 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
+    node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2283:62]
+    node _T_1044 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
+    node _T_1045 = bits(_T_1044, 0, 0) @[dec_tlu_ctl.scala 2284:62]
+    node _T_1046 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
+    node _T_1047 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
+    node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2285:62]
+    node _T_1049 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
+    node _T_1050 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
+    node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2286:62]
+    node _T_1052 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
+    node _T_1053 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
+    node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2287:62]
+    node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
+    node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
+    node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2288:62]
+    node _T_1058 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
+    node _T_1059 = and(_T_1058, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
+    node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
+    node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2289:62]
+    node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
+    node _T_1063 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
+    node _T_1064 = and(_T_1062, _T_1063) @[dec_tlu_ctl.scala 2289:101]
+    node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
+    node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2290:59]
+    node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
+    node _T_1068 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
+    node _T_1069 = bits(_T_1068, 0, 0) @[dec_tlu_ctl.scala 2291:59]
+    node _T_1070 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
+    node _T_1071 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
+    node _T_1072 = bits(_T_1071, 0, 0) @[dec_tlu_ctl.scala 2292:59]
+    node _T_1073 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
+    node _T_1074 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
+    node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2293:59]
+    node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
+    node _T_1077 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
+    node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2294:59]
+    node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
+    node _T_1080 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
+    node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2295:59]
+    node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
+    node _T_1083 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
+    node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2296:59]
+    node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
+    node _T_1086 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
+    node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2297:59]
+    node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
+    node _T_1089 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
+    node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2298:59]
+    node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
+    node _T_1092 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
+    node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2299:59]
+    node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
+    node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
+    node _T_1096 = or(_T_1094, _T_1095) @[dec_tlu_ctl.scala 2299:101]
+    node _T_1097 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
+    node _T_1098 = bits(_T_1097, 0, 0) @[dec_tlu_ctl.scala 2300:62]
+    node _T_1099 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
+    node _T_1100 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
+    node _T_1101 = bits(_T_1100, 0, 0) @[dec_tlu_ctl.scala 2301:62]
+    node _T_1102 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
+    node _T_1103 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
+    node _T_1104 = bits(_T_1103, 0, 0) @[dec_tlu_ctl.scala 2302:62]
+    node _T_1105 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
+    node _T_1106 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
+    node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2303:62]
+    node _T_1108 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
+    node _T_1109 = bits(_T_1108, 0, 0) @[dec_tlu_ctl.scala 2304:62]
+    node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
+    node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2305:62]
+    node _T_1112 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
+    node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2306:62]
+    node _T_1114 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
+    node _T_1115 = bits(_T_1114, 0, 0) @[dec_tlu_ctl.scala 2307:62]
+    node _T_1116 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
+    node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2308:62]
+    node _T_1118 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
+    node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2309:62]
+    node _T_1120 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
+    node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2310:62]
+    node _T_1122 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
+    node _T_1123 = or(_T_1122, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
+    node _T_1124 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
+    node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2311:62]
+    node _T_1126 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
+    node _T_1127 = or(_T_1126, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
+    node _T_1128 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
+    node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2312:62]
+    node _T_1130 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
+    node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2313:62]
+    node _T_1132 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
+    node _T_1133 = bits(_T_1132, 0, 0) @[dec_tlu_ctl.scala 2314:62]
+    node _T_1134 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
+    node _T_1135 = and(_T_1134, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
+    node _T_1136 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
+    node _T_1137 = bits(_T_1136, 0, 0) @[dec_tlu_ctl.scala 2315:62]
+    node _T_1138 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
+    node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2316:62]
+    node _T_1140 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
+    node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2317:62]
+    node _T_1142 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
+    node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2318:62]
+    node _T_1144 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
+    node _T_1145 = bits(_T_1144, 0, 0) @[dec_tlu_ctl.scala 2319:62]
+    node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
+    node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2320:62]
+    node _T_1148 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
+    node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2321:62]
+    node _T_1150 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
+    node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2322:62]
+    node _T_1152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1154 = not(_T_1153) @[dec_tlu_ctl.scala 2322:73]
+    node _T_1155 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
+    node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2323:62]
+    node _T_1157 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1159 = not(_T_1158) @[dec_tlu_ctl.scala 2323:73]
+    node _T_1160 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
+    node _T_1161 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
+    node _T_1162 = and(_T_1160, _T_1161) @[dec_tlu_ctl.scala 2323:113]
+    node _T_1163 = orr(_T_1162) @[dec_tlu_ctl.scala 2323:125]
+    node _T_1164 = and(_T_1159, _T_1163) @[dec_tlu_ctl.scala 2323:98]
+    node _T_1165 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
+    node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2324:62]
+    node _T_1167 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
+    node _T_1168 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
+    node _T_1169 = bits(_T_1168, 0, 0) @[dec_tlu_ctl.scala 2325:62]
+    node _T_1170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
+    node _T_1171 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
+    node _T_1172 = bits(_T_1171, 0, 0) @[dec_tlu_ctl.scala 2326:62]
+    node _T_1173 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
+    node _T_1174 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
+    node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2328:62]
+    node _T_1176 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
+    node _T_1177 = bits(_T_1176, 0, 0) @[dec_tlu_ctl.scala 2329:62]
+    node _T_1178 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
+    node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2330:62]
+    node _T_1180 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
+    node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2331:62]
+    node _T_1182 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
+    node _T_1183 = bits(_T_1182, 0, 0) @[dec_tlu_ctl.scala 2332:62]
+    node _T_1184 = mux(_T_1018, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1185 = mux(_T_1020, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1186 = mux(_T_1022, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1187 = mux(_T_1024, _T_1026, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1188 = mux(_T_1028, _T_1032, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1189 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1190 = mux(_T_1039, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1191 = mux(_T_1041, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1192 = mux(_T_1043, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1193 = mux(_T_1045, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1194 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1195 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1196 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1197 = mux(_T_1057, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1198 = mux(_T_1061, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1199 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1200 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1201 = mux(_T_1072, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1202 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1203 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1204 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1205 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1206 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1207 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1208 = mux(_T_1093, _T_1096, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1209 = mux(_T_1098, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1210 = mux(_T_1101, _T_1102, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1211 = mux(_T_1104, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1212 = mux(_T_1107, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1213 = mux(_T_1109, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1214 = mux(_T_1111, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1215 = mux(_T_1113, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1216 = mux(_T_1115, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1217 = mux(_T_1117, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1218 = mux(_T_1119, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1219 = mux(_T_1121, _T_1123, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1220 = mux(_T_1125, _T_1127, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1221 = mux(_T_1129, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1222 = mux(_T_1131, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1223 = mux(_T_1133, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1224 = mux(_T_1137, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1225 = mux(_T_1139, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1226 = mux(_T_1141, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1227 = mux(_T_1143, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1228 = mux(_T_1145, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1229 = mux(_T_1147, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1230 = mux(_T_1149, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1231 = mux(_T_1151, _T_1154, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1232 = mux(_T_1156, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1233 = mux(_T_1166, _T_1167, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1234 = mux(_T_1169, _T_1170, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1235 = mux(_T_1172, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1236 = mux(_T_1175, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1237 = mux(_T_1177, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1238 = mux(_T_1179, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1239 = mux(_T_1181, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1240 = mux(_T_1183, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1241 = or(_T_1184, _T_1185) @[Mux.scala 27:72]
+    node _T_1242 = or(_T_1241, _T_1186) @[Mux.scala 27:72]
+    node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72]
+    node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72]
+    node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72]
+    node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72]
+    node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72]
+    node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72]
+    node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72]
+    node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72]
+    node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72]
     node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72]
     node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72]
     node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72]
@@ -74686,247 +74686,247 @@ circuit quasar_wrapper :
     node _T_1294 = or(_T_1293, _T_1238) @[Mux.scala 27:72]
     node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72]
     node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72]
-    node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72]
-    node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72]
-    node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72]
-    node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72]
-    node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72]
-    node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72]
-    node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72]
-    node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72]
-    node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72]
-    node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72]
-    wire _T_1307 : UInt<1> @[Mux.scala 27:72]
-    _T_1307 <= _T_1306 @[Mux.scala 27:72]
-    node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2274:44]
-    mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2274:19]
-    node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38]
-    node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2274:24]
-    node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
-    node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2275:62]
-    node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
-    node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2276:62]
-    node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
-    node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2277:62]
-    node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
-    node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2278:62]
-    node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
-    node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2278:94]
-    node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
-    node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2279:62]
-    node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
-    node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2279:94]
-    node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
-    node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2279:115]
-    node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
-    node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2280:62]
-    node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
-    node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
-    node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2280:115]
-    node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
-    node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2281:62]
-    node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
-    node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2282:62]
-    node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
-    node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2283:62]
-    node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
-    node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2284:62]
-    node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
-    node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
-    node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2285:62]
-    node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
-    node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
-    node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2286:62]
-    node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
-    node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
-    node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2287:62]
-    node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
-    node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
-    node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2288:62]
-    node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
-    node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
-    node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
-    node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2289:62]
-    node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
-    node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
-    node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2289:101]
-    node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
-    node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2290:59]
-    node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
-    node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
-    node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2291:59]
-    node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
-    node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
-    node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2292:59]
-    node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
-    node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
-    node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2293:59]
-    node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
-    node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
-    node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2294:59]
-    node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
-    node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
-    node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2295:59]
-    node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
-    node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
-    node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2296:59]
-    node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
-    node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
-    node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2297:59]
-    node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
-    node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
-    node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2298:59]
-    node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
-    node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
-    node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2299:59]
-    node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
-    node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
-    node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2299:101]
-    node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
-    node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2300:62]
-    node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
-    node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
-    node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2301:62]
-    node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
-    node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
-    node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2302:62]
-    node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
-    node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
-    node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2303:62]
-    node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
-    node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2304:62]
-    node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
-    node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2305:62]
-    node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
-    node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2306:62]
-    node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
-    node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2307:62]
-    node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
-    node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2308:62]
-    node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
-    node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2309:62]
-    node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
-    node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2310:62]
-    node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
-    node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
-    node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
-    node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2311:62]
-    node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
-    node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
-    node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
-    node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2312:62]
-    node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
-    node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2313:62]
-    node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
-    node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2314:62]
-    node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
-    node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
-    node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
-    node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2315:62]
-    node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
-    node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2316:62]
-    node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
-    node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2317:62]
-    node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
-    node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2318:62]
-    node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
-    node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2319:62]
-    node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
-    node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2320:62]
-    node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
-    node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2321:62]
-    node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
-    node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2322:62]
-    node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2322:73]
-    node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
-    node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2323:62]
-    node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2323:73]
-    node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
-    node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
-    node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2323:113]
-    node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2323:125]
-    node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2323:98]
-    node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
-    node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2324:62]
-    node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
-    node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
-    node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2325:62]
-    node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
-    node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
-    node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2326:62]
-    node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
-    node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
-    node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2328:62]
-    node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
-    node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2329:62]
-    node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
-    node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2330:62]
-    node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
-    node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2331:62]
-    node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
-    node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2332:62]
-    node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72]
+    wire _T_1297 : UInt<1> @[Mux.scala 27:72]
+    _T_1297 <= _T_1296 @[Mux.scala 27:72]
+    node _T_1298 = and(_T_1016, _T_1297) @[dec_tlu_ctl.scala 2274:44]
+    mhpmc_inc_r[0] <= _T_1298 @[dec_tlu_ctl.scala 2274:19]
+    node _T_1299 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38]
+    node _T_1300 = not(_T_1299) @[dec_tlu_ctl.scala 2274:24]
+    node _T_1301 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
+    node _T_1302 = bits(_T_1301, 0, 0) @[dec_tlu_ctl.scala 2275:62]
+    node _T_1303 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
+    node _T_1304 = bits(_T_1303, 0, 0) @[dec_tlu_ctl.scala 2276:62]
+    node _T_1305 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
+    node _T_1306 = bits(_T_1305, 0, 0) @[dec_tlu_ctl.scala 2277:62]
+    node _T_1307 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
+    node _T_1308 = bits(_T_1307, 0, 0) @[dec_tlu_ctl.scala 2278:62]
+    node _T_1309 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
+    node _T_1310 = and(io.tlu_i0_commit_cmt, _T_1309) @[dec_tlu_ctl.scala 2278:94]
+    node _T_1311 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
+    node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2279:62]
+    node _T_1313 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
+    node _T_1314 = and(io.tlu_i0_commit_cmt, _T_1313) @[dec_tlu_ctl.scala 2279:94]
+    node _T_1315 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
+    node _T_1316 = and(_T_1314, _T_1315) @[dec_tlu_ctl.scala 2279:115]
+    node _T_1317 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
+    node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2280:62]
+    node _T_1319 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
+    node _T_1320 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
+    node _T_1321 = and(_T_1319, _T_1320) @[dec_tlu_ctl.scala 2280:115]
+    node _T_1322 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
+    node _T_1323 = bits(_T_1322, 0, 0) @[dec_tlu_ctl.scala 2281:62]
+    node _T_1324 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
+    node _T_1325 = bits(_T_1324, 0, 0) @[dec_tlu_ctl.scala 2282:62]
+    node _T_1326 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
+    node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2283:62]
+    node _T_1328 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
+    node _T_1329 = bits(_T_1328, 0, 0) @[dec_tlu_ctl.scala 2284:62]
+    node _T_1330 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
+    node _T_1331 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
+    node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2285:62]
+    node _T_1333 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
+    node _T_1334 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
+    node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2286:62]
+    node _T_1336 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
+    node _T_1337 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
+    node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2287:62]
+    node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
+    node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
+    node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2288:62]
+    node _T_1342 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
+    node _T_1343 = and(_T_1342, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
+    node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
+    node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2289:62]
+    node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
+    node _T_1347 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
+    node _T_1348 = and(_T_1346, _T_1347) @[dec_tlu_ctl.scala 2289:101]
+    node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
+    node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2290:59]
+    node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
+    node _T_1352 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
+    node _T_1353 = bits(_T_1352, 0, 0) @[dec_tlu_ctl.scala 2291:59]
+    node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
+    node _T_1355 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
+    node _T_1356 = bits(_T_1355, 0, 0) @[dec_tlu_ctl.scala 2292:59]
+    node _T_1357 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
+    node _T_1358 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
+    node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2293:59]
+    node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
+    node _T_1361 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
+    node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2294:59]
+    node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
+    node _T_1364 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
+    node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2295:59]
+    node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
+    node _T_1367 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
+    node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2296:59]
+    node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
+    node _T_1370 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
+    node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2297:59]
+    node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
+    node _T_1373 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
+    node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2298:59]
+    node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
+    node _T_1376 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
+    node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2299:59]
+    node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
+    node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
+    node _T_1380 = or(_T_1378, _T_1379) @[dec_tlu_ctl.scala 2299:101]
+    node _T_1381 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
+    node _T_1382 = bits(_T_1381, 0, 0) @[dec_tlu_ctl.scala 2300:62]
+    node _T_1383 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
+    node _T_1384 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
+    node _T_1385 = bits(_T_1384, 0, 0) @[dec_tlu_ctl.scala 2301:62]
+    node _T_1386 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
+    node _T_1387 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
+    node _T_1388 = bits(_T_1387, 0, 0) @[dec_tlu_ctl.scala 2302:62]
+    node _T_1389 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
+    node _T_1390 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
+    node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2303:62]
+    node _T_1392 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
+    node _T_1393 = bits(_T_1392, 0, 0) @[dec_tlu_ctl.scala 2304:62]
+    node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
+    node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2305:62]
+    node _T_1396 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
+    node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2306:62]
+    node _T_1398 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
+    node _T_1399 = bits(_T_1398, 0, 0) @[dec_tlu_ctl.scala 2307:62]
+    node _T_1400 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
+    node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2308:62]
+    node _T_1402 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
+    node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2309:62]
+    node _T_1404 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
+    node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2310:62]
+    node _T_1406 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
+    node _T_1407 = or(_T_1406, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
+    node _T_1408 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
+    node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2311:62]
+    node _T_1410 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
+    node _T_1411 = or(_T_1410, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
+    node _T_1412 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
+    node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2312:62]
+    node _T_1414 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
+    node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2313:62]
+    node _T_1416 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
+    node _T_1417 = bits(_T_1416, 0, 0) @[dec_tlu_ctl.scala 2314:62]
+    node _T_1418 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
+    node _T_1419 = and(_T_1418, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
+    node _T_1420 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
+    node _T_1421 = bits(_T_1420, 0, 0) @[dec_tlu_ctl.scala 2315:62]
+    node _T_1422 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
+    node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2316:62]
+    node _T_1424 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
+    node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2317:62]
+    node _T_1426 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
+    node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2318:62]
+    node _T_1428 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
+    node _T_1429 = bits(_T_1428, 0, 0) @[dec_tlu_ctl.scala 2319:62]
+    node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
+    node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2320:62]
+    node _T_1432 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
+    node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2321:62]
+    node _T_1434 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
+    node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2322:62]
+    node _T_1436 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1438 = not(_T_1437) @[dec_tlu_ctl.scala 2322:73]
+    node _T_1439 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
+    node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2323:62]
+    node _T_1441 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1443 = not(_T_1442) @[dec_tlu_ctl.scala 2323:73]
+    node _T_1444 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
+    node _T_1445 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
+    node _T_1446 = and(_T_1444, _T_1445) @[dec_tlu_ctl.scala 2323:113]
+    node _T_1447 = orr(_T_1446) @[dec_tlu_ctl.scala 2323:125]
+    node _T_1448 = and(_T_1443, _T_1447) @[dec_tlu_ctl.scala 2323:98]
+    node _T_1449 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
+    node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2324:62]
+    node _T_1451 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
+    node _T_1452 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
+    node _T_1453 = bits(_T_1452, 0, 0) @[dec_tlu_ctl.scala 2325:62]
+    node _T_1454 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
+    node _T_1455 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
+    node _T_1456 = bits(_T_1455, 0, 0) @[dec_tlu_ctl.scala 2326:62]
+    node _T_1457 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
+    node _T_1458 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
+    node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2328:62]
+    node _T_1460 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
+    node _T_1461 = bits(_T_1460, 0, 0) @[dec_tlu_ctl.scala 2329:62]
+    node _T_1462 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
+    node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2330:62]
+    node _T_1464 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
+    node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2331:62]
+    node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
+    node _T_1467 = bits(_T_1466, 0, 0) @[dec_tlu_ctl.scala 2332:62]
+    node _T_1468 = mux(_T_1302, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1469 = mux(_T_1304, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1470 = mux(_T_1306, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1471 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1472 = mux(_T_1312, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1473 = mux(_T_1318, _T_1321, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1474 = mux(_T_1323, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1475 = mux(_T_1325, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1476 = mux(_T_1327, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1477 = mux(_T_1329, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1478 = mux(_T_1332, _T_1333, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1479 = mux(_T_1335, _T_1336, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1480 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1481 = mux(_T_1341, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1482 = mux(_T_1345, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1483 = mux(_T_1350, _T_1351, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1484 = mux(_T_1353, _T_1354, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1485 = mux(_T_1356, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1486 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1487 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1488 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1489 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1490 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1491 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1492 = mux(_T_1377, _T_1380, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1493 = mux(_T_1382, _T_1383, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1494 = mux(_T_1385, _T_1386, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1495 = mux(_T_1388, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1496 = mux(_T_1391, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1497 = mux(_T_1393, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1498 = mux(_T_1395, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1499 = mux(_T_1397, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1500 = mux(_T_1399, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1501 = mux(_T_1401, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1502 = mux(_T_1403, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1503 = mux(_T_1405, _T_1407, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1504 = mux(_T_1409, _T_1411, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1505 = mux(_T_1413, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1506 = mux(_T_1415, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1507 = mux(_T_1417, _T_1419, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1508 = mux(_T_1421, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1509 = mux(_T_1423, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1510 = mux(_T_1425, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1511 = mux(_T_1427, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1512 = mux(_T_1429, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1513 = mux(_T_1431, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1514 = mux(_T_1433, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1515 = mux(_T_1435, _T_1438, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1516 = mux(_T_1440, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1517 = mux(_T_1450, _T_1451, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1518 = mux(_T_1453, _T_1454, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1519 = mux(_T_1456, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1520 = mux(_T_1459, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1521 = mux(_T_1461, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1522 = mux(_T_1463, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1523 = mux(_T_1465, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1524 = mux(_T_1467, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1525 = or(_T_1468, _T_1469) @[Mux.scala 27:72]
+    node _T_1526 = or(_T_1525, _T_1470) @[Mux.scala 27:72]
+    node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72]
+    node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72]
+    node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72]
+    node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72]
+    node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72]
+    node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72]
+    node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72]
+    node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72]
+    node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72]
     node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72]
     node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72]
     node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72]
@@ -74972,247 +74972,247 @@ circuit quasar_wrapper :
     node _T_1578 = or(_T_1577, _T_1522) @[Mux.scala 27:72]
     node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72]
     node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72]
-    node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72]
-    node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72]
-    node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72]
-    node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72]
-    node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72]
-    node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72]
-    node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72]
-    node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72]
-    node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72]
-    node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72]
-    wire _T_1591 : UInt<1> @[Mux.scala 27:72]
-    _T_1591 <= _T_1590 @[Mux.scala 27:72]
-    node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2274:44]
-    mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2274:19]
-    node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38]
-    node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2274:24]
-    node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
-    node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2275:62]
-    node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
-    node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2276:62]
-    node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
-    node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2277:62]
-    node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
-    node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2278:62]
-    node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
-    node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2278:94]
-    node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
-    node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2279:62]
-    node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
-    node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2279:94]
-    node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
-    node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2279:115]
-    node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
-    node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2280:62]
-    node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
-    node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
-    node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2280:115]
-    node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
-    node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2281:62]
-    node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
-    node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2282:62]
-    node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
-    node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2283:62]
-    node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
-    node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2284:62]
-    node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
-    node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
-    node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2285:62]
-    node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
-    node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
-    node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2286:62]
-    node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
-    node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
-    node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2287:62]
-    node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
-    node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
-    node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2288:62]
-    node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
-    node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
-    node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
-    node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2289:62]
-    node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
-    node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
-    node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2289:101]
-    node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
-    node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2290:59]
-    node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
-    node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
-    node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2291:59]
-    node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
-    node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
-    node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2292:59]
-    node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
-    node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
-    node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2293:59]
-    node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
-    node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
-    node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2294:59]
-    node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
-    node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
-    node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2295:59]
-    node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
-    node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
-    node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2296:59]
-    node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
-    node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
-    node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2297:59]
-    node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
-    node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
-    node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2298:59]
-    node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
-    node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
-    node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2299:59]
-    node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
-    node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
-    node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2299:101]
-    node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
-    node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2300:62]
-    node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
-    node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
-    node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2301:62]
-    node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
-    node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
-    node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2302:62]
-    node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
-    node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
-    node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2303:62]
-    node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
-    node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2304:62]
-    node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
-    node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2305:62]
-    node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
-    node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2306:62]
-    node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
-    node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2307:62]
-    node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
-    node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2308:62]
-    node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
-    node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2309:62]
-    node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
-    node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2310:62]
-    node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
-    node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
-    node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
-    node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2311:62]
-    node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
-    node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
-    node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
-    node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2312:62]
-    node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
-    node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2313:62]
-    node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
-    node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2314:62]
-    node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
-    node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
-    node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
-    node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2315:62]
-    node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
-    node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2316:62]
-    node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
-    node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2317:62]
-    node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
-    node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2318:62]
-    node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
-    node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2319:62]
-    node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
-    node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2320:62]
-    node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
-    node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2321:62]
-    node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
-    node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2322:62]
-    node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2322:84]
-    node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2322:73]
-    node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
-    node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2323:62]
-    node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2323:84]
-    node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2323:73]
-    node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
-    node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
-    node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2323:113]
-    node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2323:125]
-    node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2323:98]
-    node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
-    node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2324:62]
-    node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
-    node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
-    node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2325:62]
-    node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
-    node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
-    node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2326:62]
-    node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
-    node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
-    node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2328:62]
-    node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
-    node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2329:62]
-    node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
-    node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2330:62]
-    node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
-    node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2331:62]
-    node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
-    node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2332:62]
-    node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72]
+    wire _T_1581 : UInt<1> @[Mux.scala 27:72]
+    _T_1581 <= _T_1580 @[Mux.scala 27:72]
+    node _T_1582 = and(_T_1300, _T_1581) @[dec_tlu_ctl.scala 2274:44]
+    mhpmc_inc_r[1] <= _T_1582 @[dec_tlu_ctl.scala 2274:19]
+    node _T_1583 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38]
+    node _T_1584 = not(_T_1583) @[dec_tlu_ctl.scala 2274:24]
+    node _T_1585 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
+    node _T_1586 = bits(_T_1585, 0, 0) @[dec_tlu_ctl.scala 2275:62]
+    node _T_1587 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
+    node _T_1588 = bits(_T_1587, 0, 0) @[dec_tlu_ctl.scala 2276:62]
+    node _T_1589 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
+    node _T_1590 = bits(_T_1589, 0, 0) @[dec_tlu_ctl.scala 2277:62]
+    node _T_1591 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
+    node _T_1592 = bits(_T_1591, 0, 0) @[dec_tlu_ctl.scala 2278:62]
+    node _T_1593 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
+    node _T_1594 = and(io.tlu_i0_commit_cmt, _T_1593) @[dec_tlu_ctl.scala 2278:94]
+    node _T_1595 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
+    node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2279:62]
+    node _T_1597 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
+    node _T_1598 = and(io.tlu_i0_commit_cmt, _T_1597) @[dec_tlu_ctl.scala 2279:94]
+    node _T_1599 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
+    node _T_1600 = and(_T_1598, _T_1599) @[dec_tlu_ctl.scala 2279:115]
+    node _T_1601 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
+    node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2280:62]
+    node _T_1603 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
+    node _T_1604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
+    node _T_1605 = and(_T_1603, _T_1604) @[dec_tlu_ctl.scala 2280:115]
+    node _T_1606 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
+    node _T_1607 = bits(_T_1606, 0, 0) @[dec_tlu_ctl.scala 2281:62]
+    node _T_1608 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
+    node _T_1609 = bits(_T_1608, 0, 0) @[dec_tlu_ctl.scala 2282:62]
+    node _T_1610 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
+    node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2283:62]
+    node _T_1612 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
+    node _T_1613 = bits(_T_1612, 0, 0) @[dec_tlu_ctl.scala 2284:62]
+    node _T_1614 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
+    node _T_1615 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
+    node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2285:62]
+    node _T_1617 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
+    node _T_1618 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
+    node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2286:62]
+    node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
+    node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
+    node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2287:62]
+    node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
+    node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
+    node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2288:62]
+    node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
+    node _T_1627 = and(_T_1626, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
+    node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
+    node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2289:62]
+    node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
+    node _T_1631 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
+    node _T_1632 = and(_T_1630, _T_1631) @[dec_tlu_ctl.scala 2289:101]
+    node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
+    node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2290:59]
+    node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
+    node _T_1636 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
+    node _T_1637 = bits(_T_1636, 0, 0) @[dec_tlu_ctl.scala 2291:59]
+    node _T_1638 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
+    node _T_1639 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
+    node _T_1640 = bits(_T_1639, 0, 0) @[dec_tlu_ctl.scala 2292:59]
+    node _T_1641 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
+    node _T_1642 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
+    node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2293:59]
+    node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
+    node _T_1645 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
+    node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2294:59]
+    node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
+    node _T_1648 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
+    node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2295:59]
+    node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
+    node _T_1651 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
+    node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2296:59]
+    node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
+    node _T_1654 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
+    node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2297:59]
+    node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
+    node _T_1657 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
+    node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2298:59]
+    node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
+    node _T_1660 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
+    node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2299:59]
+    node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
+    node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
+    node _T_1664 = or(_T_1662, _T_1663) @[dec_tlu_ctl.scala 2299:101]
+    node _T_1665 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
+    node _T_1666 = bits(_T_1665, 0, 0) @[dec_tlu_ctl.scala 2300:62]
+    node _T_1667 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
+    node _T_1668 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
+    node _T_1669 = bits(_T_1668, 0, 0) @[dec_tlu_ctl.scala 2301:62]
+    node _T_1670 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
+    node _T_1671 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
+    node _T_1672 = bits(_T_1671, 0, 0) @[dec_tlu_ctl.scala 2302:62]
+    node _T_1673 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
+    node _T_1674 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
+    node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2303:62]
+    node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
+    node _T_1677 = bits(_T_1676, 0, 0) @[dec_tlu_ctl.scala 2304:62]
+    node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
+    node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2305:62]
+    node _T_1680 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
+    node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2306:62]
+    node _T_1682 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
+    node _T_1683 = bits(_T_1682, 0, 0) @[dec_tlu_ctl.scala 2307:62]
+    node _T_1684 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
+    node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2308:62]
+    node _T_1686 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
+    node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2309:62]
+    node _T_1688 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
+    node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2310:62]
+    node _T_1690 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
+    node _T_1691 = or(_T_1690, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
+    node _T_1692 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
+    node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2311:62]
+    node _T_1694 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
+    node _T_1695 = or(_T_1694, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
+    node _T_1696 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
+    node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2312:62]
+    node _T_1698 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
+    node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2313:62]
+    node _T_1700 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
+    node _T_1701 = bits(_T_1700, 0, 0) @[dec_tlu_ctl.scala 2314:62]
+    node _T_1702 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
+    node _T_1703 = and(_T_1702, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
+    node _T_1704 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
+    node _T_1705 = bits(_T_1704, 0, 0) @[dec_tlu_ctl.scala 2315:62]
+    node _T_1706 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
+    node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2316:62]
+    node _T_1708 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
+    node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2317:62]
+    node _T_1710 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
+    node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2318:62]
+    node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
+    node _T_1713 = bits(_T_1712, 0, 0) @[dec_tlu_ctl.scala 2319:62]
+    node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
+    node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2320:62]
+    node _T_1716 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
+    node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2321:62]
+    node _T_1718 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
+    node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2322:62]
+    node _T_1720 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2322:84]
+    node _T_1722 = not(_T_1721) @[dec_tlu_ctl.scala 2322:73]
+    node _T_1723 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
+    node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2323:62]
+    node _T_1725 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2323:84]
+    node _T_1727 = not(_T_1726) @[dec_tlu_ctl.scala 2323:73]
+    node _T_1728 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
+    node _T_1729 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
+    node _T_1730 = and(_T_1728, _T_1729) @[dec_tlu_ctl.scala 2323:113]
+    node _T_1731 = orr(_T_1730) @[dec_tlu_ctl.scala 2323:125]
+    node _T_1732 = and(_T_1727, _T_1731) @[dec_tlu_ctl.scala 2323:98]
+    node _T_1733 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
+    node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2324:62]
+    node _T_1735 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
+    node _T_1736 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
+    node _T_1737 = bits(_T_1736, 0, 0) @[dec_tlu_ctl.scala 2325:62]
+    node _T_1738 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
+    node _T_1739 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
+    node _T_1740 = bits(_T_1739, 0, 0) @[dec_tlu_ctl.scala 2326:62]
+    node _T_1741 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
+    node _T_1742 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
+    node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2328:62]
+    node _T_1744 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
+    node _T_1745 = bits(_T_1744, 0, 0) @[dec_tlu_ctl.scala 2329:62]
+    node _T_1746 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
+    node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2330:62]
+    node _T_1748 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
+    node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2331:62]
+    node _T_1750 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
+    node _T_1751 = bits(_T_1750, 0, 0) @[dec_tlu_ctl.scala 2332:62]
+    node _T_1752 = mux(_T_1586, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1753 = mux(_T_1588, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1754 = mux(_T_1590, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1755 = mux(_T_1592, _T_1594, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1756 = mux(_T_1596, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1757 = mux(_T_1602, _T_1605, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1758 = mux(_T_1607, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1759 = mux(_T_1609, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1760 = mux(_T_1611, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1761 = mux(_T_1613, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1762 = mux(_T_1616, _T_1617, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1763 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1764 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1765 = mux(_T_1625, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1766 = mux(_T_1629, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1767 = mux(_T_1634, _T_1635, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1768 = mux(_T_1637, _T_1638, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1769 = mux(_T_1640, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1770 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1771 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1772 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1773 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1774 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1775 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1776 = mux(_T_1661, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1777 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1778 = mux(_T_1669, _T_1670, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1779 = mux(_T_1672, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1780 = mux(_T_1675, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1781 = mux(_T_1677, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1782 = mux(_T_1679, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1783 = mux(_T_1681, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1784 = mux(_T_1683, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1785 = mux(_T_1685, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1786 = mux(_T_1687, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1787 = mux(_T_1689, _T_1691, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1788 = mux(_T_1693, _T_1695, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1789 = mux(_T_1697, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1790 = mux(_T_1699, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1791 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1792 = mux(_T_1705, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1793 = mux(_T_1707, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1794 = mux(_T_1709, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1795 = mux(_T_1711, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1796 = mux(_T_1713, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1797 = mux(_T_1715, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1798 = mux(_T_1717, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1799 = mux(_T_1719, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1800 = mux(_T_1724, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1801 = mux(_T_1734, _T_1735, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1802 = mux(_T_1737, _T_1738, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1803 = mux(_T_1740, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1804 = mux(_T_1743, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1805 = mux(_T_1745, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1806 = mux(_T_1747, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1807 = mux(_T_1749, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1808 = mux(_T_1751, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1809 = or(_T_1752, _T_1753) @[Mux.scala 27:72]
+    node _T_1810 = or(_T_1809, _T_1754) @[Mux.scala 27:72]
+    node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72]
+    node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72]
+    node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72]
+    node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72]
+    node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72]
+    node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72]
+    node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72]
+    node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72]
+    node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72]
     node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72]
     node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72]
     node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72]
@@ -75258,247 +75258,247 @@ circuit quasar_wrapper :
     node _T_1862 = or(_T_1861, _T_1806) @[Mux.scala 27:72]
     node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72]
     node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72]
-    node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72]
-    node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72]
-    node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72]
-    node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72]
-    node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72]
-    node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72]
-    node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72]
-    node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72]
-    node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72]
-    node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72]
-    wire _T_1875 : UInt<1> @[Mux.scala 27:72]
-    _T_1875 <= _T_1874 @[Mux.scala 27:72]
-    node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2274:44]
-    mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2274:19]
-    node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38]
-    node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2274:24]
-    node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
-    node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2275:62]
-    node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
-    node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2276:62]
-    node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
-    node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2277:62]
-    node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
-    node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2278:62]
-    node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
-    node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2278:94]
-    node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
-    node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2279:62]
-    node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
-    node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2279:94]
-    node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
-    node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2279:115]
-    node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
-    node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2280:62]
-    node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
-    node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
-    node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2280:115]
-    node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
-    node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2281:62]
-    node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
-    node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2282:62]
-    node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
-    node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2283:62]
-    node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
-    node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2284:62]
-    node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
-    node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
-    node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2285:62]
-    node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
-    node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
-    node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2286:62]
-    node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
-    node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
-    node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2287:62]
-    node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
-    node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
-    node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2288:62]
-    node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
-    node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
-    node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
-    node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2289:62]
-    node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
-    node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
-    node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2289:101]
-    node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
-    node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2290:59]
-    node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
-    node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
-    node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2291:59]
-    node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
-    node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
-    node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2292:59]
-    node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
-    node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
-    node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2293:59]
-    node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
-    node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
-    node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2294:59]
-    node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
-    node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
-    node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2295:59]
-    node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
-    node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
-    node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2296:59]
-    node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
-    node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
-    node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2297:59]
-    node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
-    node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
-    node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2298:59]
-    node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
-    node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
-    node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2299:59]
-    node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
-    node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
-    node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2299:101]
-    node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
-    node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2300:62]
-    node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
-    node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
-    node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2301:62]
-    node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
-    node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
-    node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2302:62]
-    node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
-    node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
-    node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2303:62]
-    node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
-    node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2304:62]
-    node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
-    node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2305:62]
-    node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
-    node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2306:62]
-    node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
-    node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2307:62]
-    node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
-    node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2308:62]
-    node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
-    node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2309:62]
-    node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
-    node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2310:62]
-    node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
-    node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
-    node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
-    node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2311:62]
-    node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
-    node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
-    node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
-    node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2312:62]
-    node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
-    node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2313:62]
-    node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
-    node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2314:62]
-    node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
-    node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
-    node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
-    node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2315:62]
-    node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
-    node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2316:62]
-    node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
-    node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2317:62]
-    node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
-    node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2318:62]
-    node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
-    node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2319:62]
-    node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
-    node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2320:62]
-    node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
-    node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2321:62]
-    node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
-    node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2322:62]
-    node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
-    node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2322:84]
-    node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2322:73]
-    node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
-    node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2323:62]
-    node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
-    node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2323:84]
-    node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2323:73]
-    node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
-    node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
-    node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2323:113]
-    node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2323:125]
-    node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2323:98]
-    node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
-    node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2324:62]
-    node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
-    node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
-    node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2325:62]
-    node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
-    node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
-    node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2326:62]
-    node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
-    node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
-    node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2328:62]
-    node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
-    node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2329:62]
-    node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
-    node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2330:62]
-    node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
-    node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2331:62]
-    node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
-    node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2332:62]
-    node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72]
+    wire _T_1865 : UInt<1> @[Mux.scala 27:72]
+    _T_1865 <= _T_1864 @[Mux.scala 27:72]
+    node _T_1866 = and(_T_1584, _T_1865) @[dec_tlu_ctl.scala 2274:44]
+    mhpmc_inc_r[2] <= _T_1866 @[dec_tlu_ctl.scala 2274:19]
+    node _T_1867 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38]
+    node _T_1868 = not(_T_1867) @[dec_tlu_ctl.scala 2274:24]
+    node _T_1869 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34]
+    node _T_1870 = bits(_T_1869, 0, 0) @[dec_tlu_ctl.scala 2275:62]
+    node _T_1871 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34]
+    node _T_1872 = bits(_T_1871, 0, 0) @[dec_tlu_ctl.scala 2276:62]
+    node _T_1873 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34]
+    node _T_1874 = bits(_T_1873, 0, 0) @[dec_tlu_ctl.scala 2277:62]
+    node _T_1875 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34]
+    node _T_1876 = bits(_T_1875, 0, 0) @[dec_tlu_ctl.scala 2278:62]
+    node _T_1877 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96]
+    node _T_1878 = and(io.tlu_i0_commit_cmt, _T_1877) @[dec_tlu_ctl.scala 2278:94]
+    node _T_1879 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34]
+    node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2279:62]
+    node _T_1881 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96]
+    node _T_1882 = and(io.tlu_i0_commit_cmt, _T_1881) @[dec_tlu_ctl.scala 2279:94]
+    node _T_1883 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117]
+    node _T_1884 = and(_T_1882, _T_1883) @[dec_tlu_ctl.scala 2279:115]
+    node _T_1885 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34]
+    node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2280:62]
+    node _T_1887 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94]
+    node _T_1888 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117]
+    node _T_1889 = and(_T_1887, _T_1888) @[dec_tlu_ctl.scala 2280:115]
+    node _T_1890 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34]
+    node _T_1891 = bits(_T_1890, 0, 0) @[dec_tlu_ctl.scala 2281:62]
+    node _T_1892 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34]
+    node _T_1893 = bits(_T_1892, 0, 0) @[dec_tlu_ctl.scala 2282:62]
+    node _T_1894 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34]
+    node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2283:62]
+    node _T_1896 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34]
+    node _T_1897 = bits(_T_1896, 0, 0) @[dec_tlu_ctl.scala 2284:62]
+    node _T_1898 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91]
+    node _T_1899 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34]
+    node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2285:62]
+    node _T_1901 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105]
+    node _T_1902 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34]
+    node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2286:62]
+    node _T_1904 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91]
+    node _T_1905 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34]
+    node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2287:62]
+    node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91]
+    node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34]
+    node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2288:62]
+    node _T_1910 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91]
+    node _T_1911 = and(_T_1910, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100]
+    node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34]
+    node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2289:62]
+    node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91]
+    node _T_1915 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142]
+    node _T_1916 = and(_T_1914, _T_1915) @[dec_tlu_ctl.scala 2289:101]
+    node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34]
+    node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2290:59]
+    node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89]
+    node _T_1920 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34]
+    node _T_1921 = bits(_T_1920, 0, 0) @[dec_tlu_ctl.scala 2291:59]
+    node _T_1922 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89]
+    node _T_1923 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34]
+    node _T_1924 = bits(_T_1923, 0, 0) @[dec_tlu_ctl.scala 2292:59]
+    node _T_1925 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89]
+    node _T_1926 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34]
+    node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2293:59]
+    node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89]
+    node _T_1929 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34]
+    node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2294:59]
+    node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89]
+    node _T_1932 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34]
+    node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2295:59]
+    node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89]
+    node _T_1935 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34]
+    node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2296:59]
+    node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89]
+    node _T_1938 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34]
+    node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2297:59]
+    node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89]
+    node _T_1941 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34]
+    node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2298:59]
+    node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89]
+    node _T_1944 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34]
+    node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2299:59]
+    node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89]
+    node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122]
+    node _T_1948 = or(_T_1946, _T_1947) @[dec_tlu_ctl.scala 2299:101]
+    node _T_1949 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34]
+    node _T_1950 = bits(_T_1949, 0, 0) @[dec_tlu_ctl.scala 2300:62]
+    node _T_1951 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95]
+    node _T_1952 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34]
+    node _T_1953 = bits(_T_1952, 0, 0) @[dec_tlu_ctl.scala 2301:62]
+    node _T_1954 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97]
+    node _T_1955 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34]
+    node _T_1956 = bits(_T_1955, 0, 0) @[dec_tlu_ctl.scala 2302:62]
+    node _T_1957 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110]
+    node _T_1958 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34]
+    node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2303:62]
+    node _T_1960 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34]
+    node _T_1961 = bits(_T_1960, 0, 0) @[dec_tlu_ctl.scala 2304:62]
+    node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34]
+    node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2305:62]
+    node _T_1964 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34]
+    node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2306:62]
+    node _T_1966 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34]
+    node _T_1967 = bits(_T_1966, 0, 0) @[dec_tlu_ctl.scala 2307:62]
+    node _T_1968 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34]
+    node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2308:62]
+    node _T_1970 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34]
+    node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2309:62]
+    node _T_1972 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34]
+    node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2310:62]
+    node _T_1974 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98]
+    node _T_1975 = or(_T_1974, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120]
+    node _T_1976 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34]
+    node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2311:62]
+    node _T_1978 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92]
+    node _T_1979 = or(_T_1978, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117]
+    node _T_1980 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34]
+    node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2312:62]
+    node _T_1982 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34]
+    node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2313:62]
+    node _T_1984 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34]
+    node _T_1985 = bits(_T_1984, 0, 0) @[dec_tlu_ctl.scala 2314:62]
+    node _T_1986 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97]
+    node _T_1987 = and(_T_1986, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129]
+    node _T_1988 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34]
+    node _T_1989 = bits(_T_1988, 0, 0) @[dec_tlu_ctl.scala 2315:62]
+    node _T_1990 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34]
+    node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2316:62]
+    node _T_1992 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34]
+    node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2317:62]
+    node _T_1994 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34]
+    node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2318:62]
+    node _T_1996 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34]
+    node _T_1997 = bits(_T_1996, 0, 0) @[dec_tlu_ctl.scala 2319:62]
+    node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34]
+    node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2320:62]
+    node _T_2000 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34]
+    node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2321:62]
+    node _T_2002 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34]
+    node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2322:62]
+    node _T_2004 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84]
+    node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2322:84]
+    node _T_2006 = not(_T_2005) @[dec_tlu_ctl.scala 2322:73]
+    node _T_2007 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34]
+    node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2323:62]
+    node _T_2009 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84]
+    node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2323:84]
+    node _T_2011 = not(_T_2010) @[dec_tlu_ctl.scala 2323:73]
+    node _T_2012 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107]
+    node _T_2013 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118]
+    node _T_2014 = and(_T_2012, _T_2013) @[dec_tlu_ctl.scala 2323:113]
+    node _T_2015 = orr(_T_2014) @[dec_tlu_ctl.scala 2323:125]
+    node _T_2016 = and(_T_2011, _T_2015) @[dec_tlu_ctl.scala 2323:98]
+    node _T_2017 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34]
+    node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2324:62]
+    node _T_2019 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91]
+    node _T_2020 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34]
+    node _T_2021 = bits(_T_2020, 0, 0) @[dec_tlu_ctl.scala 2325:62]
+    node _T_2022 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94]
+    node _T_2023 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34]
+    node _T_2024 = bits(_T_2023, 0, 0) @[dec_tlu_ctl.scala 2326:62]
+    node _T_2025 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94]
+    node _T_2026 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34]
+    node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2328:62]
+    node _T_2028 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34]
+    node _T_2029 = bits(_T_2028, 0, 0) @[dec_tlu_ctl.scala 2329:62]
+    node _T_2030 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34]
+    node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2330:62]
+    node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34]
+    node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2331:62]
+    node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34]
+    node _T_2035 = bits(_T_2034, 0, 0) @[dec_tlu_ctl.scala 2332:62]
+    node _T_2036 = mux(_T_1870, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2037 = mux(_T_1872, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2038 = mux(_T_1874, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2039 = mux(_T_1876, _T_1878, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2040 = mux(_T_1880, _T_1884, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2041 = mux(_T_1886, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2042 = mux(_T_1891, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2043 = mux(_T_1893, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2044 = mux(_T_1895, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2045 = mux(_T_1897, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2046 = mux(_T_1900, _T_1901, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2047 = mux(_T_1903, _T_1904, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2048 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2049 = mux(_T_1909, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2050 = mux(_T_1913, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2051 = mux(_T_1918, _T_1919, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2052 = mux(_T_1921, _T_1922, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2053 = mux(_T_1924, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2054 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2055 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2056 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2057 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2058 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2059 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2060 = mux(_T_1945, _T_1948, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2061 = mux(_T_1950, _T_1951, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2062 = mux(_T_1953, _T_1954, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2063 = mux(_T_1956, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2064 = mux(_T_1959, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2065 = mux(_T_1961, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2066 = mux(_T_1963, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2067 = mux(_T_1965, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2068 = mux(_T_1967, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2069 = mux(_T_1969, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2070 = mux(_T_1971, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2071 = mux(_T_1973, _T_1975, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2072 = mux(_T_1977, _T_1979, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2073 = mux(_T_1981, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2074 = mux(_T_1983, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2075 = mux(_T_1985, _T_1987, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2076 = mux(_T_1989, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2077 = mux(_T_1991, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2078 = mux(_T_1993, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2079 = mux(_T_1995, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2080 = mux(_T_1997, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2081 = mux(_T_1999, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2082 = mux(_T_2001, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2083 = mux(_T_2003, _T_2006, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2084 = mux(_T_2008, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2085 = mux(_T_2018, _T_2019, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2086 = mux(_T_2021, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2087 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2088 = mux(_T_2027, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2089 = mux(_T_2029, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2090 = mux(_T_2031, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2091 = mux(_T_2033, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2092 = mux(_T_2035, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2093 = or(_T_2036, _T_2037) @[Mux.scala 27:72]
+    node _T_2094 = or(_T_2093, _T_2038) @[Mux.scala 27:72]
+    node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72]
+    node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72]
+    node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72]
+    node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72]
+    node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72]
+    node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72]
+    node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72]
+    node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72]
+    node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72]
     node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72]
     node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72]
     node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72]
@@ -75544,585 +75544,585 @@ circuit quasar_wrapper :
     node _T_2146 = or(_T_2145, _T_2090) @[Mux.scala 27:72]
     node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72]
     node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72]
-    node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72]
-    node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72]
-    node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72]
-    node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72]
-    node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72]
-    node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72]
-    node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72]
-    node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72]
-    node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72]
-    node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72]
-    wire _T_2159 : UInt<1> @[Mux.scala 27:72]
-    _T_2159 <= _T_2158 @[Mux.scala 27:72]
-    node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2274:44]
-    mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2274:19]
-    reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53]
-    _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53]
-    mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2335:20]
-    reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53]
-    _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53]
-    mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2336:20]
-    reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53]
-    _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53]
-    mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2337:20]
-    reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53]
-    _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53]
-    mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2338:20]
+    wire _T_2149 : UInt<1> @[Mux.scala 27:72]
+    _T_2149 <= _T_2148 @[Mux.scala 27:72]
+    node _T_2150 = and(_T_1868, _T_2149) @[dec_tlu_ctl.scala 2274:44]
+    mhpmc_inc_r[3] <= _T_2150 @[dec_tlu_ctl.scala 2274:19]
+    reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53]
+    _T_2151 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53]
+    mhpmc_inc_r_d1[0] <= _T_2151 @[dec_tlu_ctl.scala 2335:20]
+    reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53]
+    _T_2152 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53]
+    mhpmc_inc_r_d1[1] <= _T_2152 @[dec_tlu_ctl.scala 2336:20]
+    reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53]
+    _T_2153 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53]
+    mhpmc_inc_r_d1[2] <= _T_2153 @[dec_tlu_ctl.scala 2337:20]
+    reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53]
+    _T_2154 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53]
+    mhpmc_inc_r_d1[3] <= _T_2154 @[dec_tlu_ctl.scala 2338:20]
     reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:56]
     perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2339:56]
-    node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53]
-    node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2342:44]
-    node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67]
-    perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2342:17]
-    node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70]
-    node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2343:61]
-    node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2343:37]
-    node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15]
-    node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104]
-    node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120]
-    node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136]
-    node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152]
-    node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58]
-    node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58]
-    node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58]
-    node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2343:86]
-    node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88]
-    node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2345:67]
-    node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2345:65]
-    node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2345:45]
-    node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2345:43]
-    io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2345:22]
-    node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88]
-    node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2346:67]
-    node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2346:65]
-    node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2346:45]
-    node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2346:43]
-    io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2346:22]
-    node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88]
-    node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2347:67]
-    node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2347:65]
-    node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2347:45]
-    node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2347:43]
-    io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2347:22]
-    node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88]
-    node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2348:67]
-    node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2348:65]
-    node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2348:45]
-    node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2348:43]
-    io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2348:22]
-    node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65]
-    node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72]
-    node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2354:43]
-    node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23]
-    node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61]
-    node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2355:39]
-    node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86]
-    node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2355:66]
+    node _T_2155 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53]
+    node _T_2156 = and(io.dec_tlu_dbg_halted, _T_2155) @[dec_tlu_ctl.scala 2342:44]
+    node _T_2157 = or(_T_2156, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67]
+    perfcnt_halted <= _T_2157 @[dec_tlu_ctl.scala 2342:17]
+    node _T_2158 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70]
+    node _T_2159 = and(io.dec_tlu_dbg_halted, _T_2158) @[dec_tlu_ctl.scala 2343:61]
+    node _T_2160 = not(_T_2159) @[dec_tlu_ctl.scala 2343:37]
+    node _T_2161 = bits(_T_2160, 0, 0) @[Bitwise.scala 72:15]
+    node _T_2162 = mux(_T_2161, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_2163 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104]
+    node _T_2164 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120]
+    node _T_2165 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136]
+    node _T_2166 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152]
+    node _T_2167 = cat(_T_2165, _T_2166) @[Cat.scala 29:58]
+    node _T_2168 = cat(_T_2163, _T_2164) @[Cat.scala 29:58]
+    node _T_2169 = cat(_T_2168, _T_2167) @[Cat.scala 29:58]
+    node perfcnt_during_sleep = and(_T_2162, _T_2169) @[dec_tlu_ctl.scala 2343:86]
+    node _T_2170 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88]
+    node _T_2171 = not(_T_2170) @[dec_tlu_ctl.scala 2345:67]
+    node _T_2172 = and(perfcnt_halted_d1, _T_2171) @[dec_tlu_ctl.scala 2345:65]
+    node _T_2173 = not(_T_2172) @[dec_tlu_ctl.scala 2345:45]
+    node _T_2174 = and(mhpmc_inc_r_d1[0], _T_2173) @[dec_tlu_ctl.scala 2345:43]
+    io.dec_tlu_perfcnt0 <= _T_2174 @[dec_tlu_ctl.scala 2345:22]
+    node _T_2175 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88]
+    node _T_2176 = not(_T_2175) @[dec_tlu_ctl.scala 2346:67]
+    node _T_2177 = and(perfcnt_halted_d1, _T_2176) @[dec_tlu_ctl.scala 2346:65]
+    node _T_2178 = not(_T_2177) @[dec_tlu_ctl.scala 2346:45]
+    node _T_2179 = and(mhpmc_inc_r_d1[1], _T_2178) @[dec_tlu_ctl.scala 2346:43]
+    io.dec_tlu_perfcnt1 <= _T_2179 @[dec_tlu_ctl.scala 2346:22]
+    node _T_2180 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88]
+    node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2347:67]
+    node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2347:65]
+    node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2347:45]
+    node _T_2184 = and(mhpmc_inc_r_d1[2], _T_2183) @[dec_tlu_ctl.scala 2347:43]
+    io.dec_tlu_perfcnt2 <= _T_2184 @[dec_tlu_ctl.scala 2347:22]
+    node _T_2185 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88]
+    node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2348:67]
+    node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2348:65]
+    node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2348:45]
+    node _T_2189 = and(mhpmc_inc_r_d1[3], _T_2188) @[dec_tlu_ctl.scala 2348:43]
+    io.dec_tlu_perfcnt3 <= _T_2189 @[dec_tlu_ctl.scala 2348:22]
+    node _T_2190 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65]
+    node _T_2191 = eq(_T_2190, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72]
+    node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2191) @[dec_tlu_ctl.scala 2354:43]
+    node _T_2192 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23]
+    node _T_2193 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61]
+    node _T_2194 = or(_T_2192, _T_2193) @[dec_tlu_ctl.scala 2355:39]
+    node _T_2195 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86]
+    node mhpmc3_wr_en1 = and(_T_2194, _T_2195) @[dec_tlu_ctl.scala 2355:66]
     node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2356:36]
-    node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28]
-    node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41]
-    node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58]
-    node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58]
-    node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2359:49]
-    node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2359:49]
-    mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2359:14]
-    node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36]
-    node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76]
-    node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2360:21]
-    node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42]
+    node _T_2196 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28]
+    node _T_2197 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41]
+    node _T_2198 = cat(_T_2196, _T_2197) @[Cat.scala 29:58]
+    node _T_2199 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58]
+    node _T_2200 = add(_T_2198, _T_2199) @[dec_tlu_ctl.scala 2359:49]
+    node _T_2201 = tail(_T_2200, 1) @[dec_tlu_ctl.scala 2359:49]
+    mhpmc3_incr <= _T_2201 @[dec_tlu_ctl.scala 2359:14]
+    node _T_2202 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36]
+    node _T_2203 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76]
+    node mhpmc3_ns = mux(_T_2202, io.dec_csr_wrdata_r, _T_2203) @[dec_tlu_ctl.scala 2360:21]
+    node _T_2204 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42]
     inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23]
     rvclkhdr_26.clock <= clock
     rvclkhdr_26.reset <= reset
     rvclkhdr_26.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17]
+    rvclkhdr_26.io.en <= _T_2204 @[lib.scala 371:17]
     rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2215 <= mhpmc3_ns @[lib.scala 374:16]
-    mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2362:9]
-    node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66]
-    node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73]
-    node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2364:44]
+    reg _T_2205 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2205 <= mhpmc3_ns @[lib.scala 374:16]
+    mhpmc3 <= _T_2205 @[dec_tlu_ctl.scala 2362:9]
+    node _T_2206 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66]
+    node _T_2207 = eq(_T_2206, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73]
+    node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2207) @[dec_tlu_ctl.scala 2364:44]
     node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2365:38]
-    node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38]
-    node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78]
-    node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2366:22]
-    node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46]
+    node _T_2208 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38]
+    node _T_2209 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78]
+    node mhpmc3h_ns = mux(_T_2208, io.dec_csr_wrdata_r, _T_2209) @[dec_tlu_ctl.scala 2366:22]
+    node _T_2210 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46]
     inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23]
     rvclkhdr_27.clock <= clock
     rvclkhdr_27.reset <= reset
     rvclkhdr_27.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17]
+    rvclkhdr_27.io.en <= _T_2210 @[lib.scala 371:17]
     rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2221 <= mhpmc3h_ns @[lib.scala 374:16]
-    mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2368:10]
-    node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65]
-    node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72]
-    node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2373:43]
-    node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23]
-    node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61]
-    node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2374:39]
-    node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86]
-    node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2374:66]
+    reg _T_2211 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2211 <= mhpmc3h_ns @[lib.scala 374:16]
+    mhpmc3h <= _T_2211 @[dec_tlu_ctl.scala 2368:10]
+    node _T_2212 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65]
+    node _T_2213 = eq(_T_2212, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72]
+    node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2213) @[dec_tlu_ctl.scala 2373:43]
+    node _T_2214 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23]
+    node _T_2215 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61]
+    node _T_2216 = or(_T_2214, _T_2215) @[dec_tlu_ctl.scala 2374:39]
+    node _T_2217 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86]
+    node mhpmc4_wr_en1 = and(_T_2216, _T_2217) @[dec_tlu_ctl.scala 2374:66]
     node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2375:36]
-    node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28]
-    node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41]
-    node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58]
-    node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58]
-    node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2379:49]
-    node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2379:49]
-    mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2379:14]
-    node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36]
-    node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63]
-    node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82]
-    node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2380:21]
-    node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43]
+    node _T_2218 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28]
+    node _T_2219 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41]
+    node _T_2220 = cat(_T_2218, _T_2219) @[Cat.scala 29:58]
+    node _T_2221 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58]
+    node _T_2222 = add(_T_2220, _T_2221) @[dec_tlu_ctl.scala 2379:49]
+    node _T_2223 = tail(_T_2222, 1) @[dec_tlu_ctl.scala 2379:49]
+    mhpmc4_incr <= _T_2223 @[dec_tlu_ctl.scala 2379:14]
+    node _T_2224 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36]
+    node _T_2225 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63]
+    node _T_2226 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82]
+    node mhpmc4_ns = mux(_T_2224, _T_2225, _T_2226) @[dec_tlu_ctl.scala 2380:21]
+    node _T_2227 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43]
     inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23]
     rvclkhdr_28.clock <= clock
     rvclkhdr_28.reset <= reset
     rvclkhdr_28.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17]
+    rvclkhdr_28.io.en <= _T_2227 @[lib.scala 371:17]
     rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2238 <= mhpmc4_ns @[lib.scala 374:16]
-    mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2381:9]
-    node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66]
-    node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73]
-    node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2383:44]
+    reg _T_2228 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2228 <= mhpmc4_ns @[lib.scala 374:16]
+    mhpmc4 <= _T_2228 @[dec_tlu_ctl.scala 2381:9]
+    node _T_2229 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66]
+    node _T_2230 = eq(_T_2229, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73]
+    node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2230) @[dec_tlu_ctl.scala 2383:44]
     node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2384:38]
-    node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38]
-    node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78]
-    node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2385:22]
-    node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46]
+    node _T_2231 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38]
+    node _T_2232 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78]
+    node mhpmc4h_ns = mux(_T_2231, io.dec_csr_wrdata_r, _T_2232) @[dec_tlu_ctl.scala 2385:22]
+    node _T_2233 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46]
     inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23]
     rvclkhdr_29.clock <= clock
     rvclkhdr_29.reset <= reset
     rvclkhdr_29.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17]
+    rvclkhdr_29.io.en <= _T_2233 @[lib.scala 371:17]
     rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2244 <= mhpmc4h_ns @[lib.scala 374:16]
-    mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2386:10]
-    node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65]
-    node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72]
-    node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2392:43]
-    node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23]
-    node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61]
-    node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2393:39]
-    node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86]
-    node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2393:66]
+    reg _T_2234 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2234 <= mhpmc4h_ns @[lib.scala 374:16]
+    mhpmc4h <= _T_2234 @[dec_tlu_ctl.scala 2386:10]
+    node _T_2235 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65]
+    node _T_2236 = eq(_T_2235, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72]
+    node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2236) @[dec_tlu_ctl.scala 2392:43]
+    node _T_2237 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23]
+    node _T_2238 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61]
+    node _T_2239 = or(_T_2237, _T_2238) @[dec_tlu_ctl.scala 2393:39]
+    node _T_2240 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86]
+    node mhpmc5_wr_en1 = and(_T_2239, _T_2240) @[dec_tlu_ctl.scala 2393:66]
     node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2394:36]
-    node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28]
-    node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41]
-    node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58]
-    node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58]
-    node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2396:49]
-    node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2396:49]
-    mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2396:14]
-    node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36]
-    node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76]
-    node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2397:21]
-    node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43]
+    node _T_2241 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28]
+    node _T_2242 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41]
+    node _T_2243 = cat(_T_2241, _T_2242) @[Cat.scala 29:58]
+    node _T_2244 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58]
+    node _T_2245 = add(_T_2243, _T_2244) @[dec_tlu_ctl.scala 2396:49]
+    node _T_2246 = tail(_T_2245, 1) @[dec_tlu_ctl.scala 2396:49]
+    mhpmc5_incr <= _T_2246 @[dec_tlu_ctl.scala 2396:14]
+    node _T_2247 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36]
+    node _T_2248 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76]
+    node mhpmc5_ns = mux(_T_2247, io.dec_csr_wrdata_r, _T_2248) @[dec_tlu_ctl.scala 2397:21]
+    node _T_2249 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43]
     inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23]
     rvclkhdr_30.clock <= clock
     rvclkhdr_30.reset <= reset
     rvclkhdr_30.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17]
+    rvclkhdr_30.io.en <= _T_2249 @[lib.scala 371:17]
     rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2260 <= mhpmc5_ns @[lib.scala 374:16]
-    mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2399:9]
-    node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66]
-    node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73]
-    node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2401:44]
+    reg _T_2250 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2250 <= mhpmc5_ns @[lib.scala 374:16]
+    mhpmc5 <= _T_2250 @[dec_tlu_ctl.scala 2399:9]
+    node _T_2251 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66]
+    node _T_2252 = eq(_T_2251, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73]
+    node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2252) @[dec_tlu_ctl.scala 2401:44]
     node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2402:38]
-    node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38]
-    node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78]
-    node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2403:22]
-    node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46]
+    node _T_2253 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38]
+    node _T_2254 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78]
+    node mhpmc5h_ns = mux(_T_2253, io.dec_csr_wrdata_r, _T_2254) @[dec_tlu_ctl.scala 2403:22]
+    node _T_2255 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46]
     inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23]
     rvclkhdr_31.clock <= clock
     rvclkhdr_31.reset <= reset
     rvclkhdr_31.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17]
+    rvclkhdr_31.io.en <= _T_2255 @[lib.scala 371:17]
     rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2266 <= mhpmc5h_ns @[lib.scala 374:16]
-    mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2405:10]
-    node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65]
-    node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72]
-    node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2410:43]
-    node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23]
-    node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61]
-    node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2411:39]
-    node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86]
-    node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2411:66]
+    reg _T_2256 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2256 <= mhpmc5h_ns @[lib.scala 374:16]
+    mhpmc5h <= _T_2256 @[dec_tlu_ctl.scala 2405:10]
+    node _T_2257 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65]
+    node _T_2258 = eq(_T_2257, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72]
+    node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2258) @[dec_tlu_ctl.scala 2410:43]
+    node _T_2259 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23]
+    node _T_2260 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61]
+    node _T_2261 = or(_T_2259, _T_2260) @[dec_tlu_ctl.scala 2411:39]
+    node _T_2262 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86]
+    node mhpmc6_wr_en1 = and(_T_2261, _T_2262) @[dec_tlu_ctl.scala 2411:66]
     node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2412:36]
-    node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28]
-    node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41]
-    node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58]
-    node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58]
-    node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2414:49]
-    node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2414:49]
-    mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2414:14]
-    node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36]
-    node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76]
-    node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2415:21]
-    node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43]
+    node _T_2263 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28]
+    node _T_2264 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41]
+    node _T_2265 = cat(_T_2263, _T_2264) @[Cat.scala 29:58]
+    node _T_2266 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58]
+    node _T_2267 = add(_T_2265, _T_2266) @[dec_tlu_ctl.scala 2414:49]
+    node _T_2268 = tail(_T_2267, 1) @[dec_tlu_ctl.scala 2414:49]
+    mhpmc6_incr <= _T_2268 @[dec_tlu_ctl.scala 2414:14]
+    node _T_2269 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36]
+    node _T_2270 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76]
+    node mhpmc6_ns = mux(_T_2269, io.dec_csr_wrdata_r, _T_2270) @[dec_tlu_ctl.scala 2415:21]
+    node _T_2271 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43]
     inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23]
     rvclkhdr_32.clock <= clock
     rvclkhdr_32.reset <= reset
     rvclkhdr_32.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17]
+    rvclkhdr_32.io.en <= _T_2271 @[lib.scala 371:17]
     rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2282 <= mhpmc6_ns @[lib.scala 374:16]
-    mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2417:9]
-    node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66]
-    node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73]
-    node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2419:44]
+    reg _T_2272 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2272 <= mhpmc6_ns @[lib.scala 374:16]
+    mhpmc6 <= _T_2272 @[dec_tlu_ctl.scala 2417:9]
+    node _T_2273 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66]
+    node _T_2274 = eq(_T_2273, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73]
+    node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2274) @[dec_tlu_ctl.scala 2419:44]
     node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2420:38]
-    node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38]
-    node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78]
-    node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2421:22]
-    node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46]
+    node _T_2275 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38]
+    node _T_2276 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78]
+    node mhpmc6h_ns = mux(_T_2275, io.dec_csr_wrdata_r, _T_2276) @[dec_tlu_ctl.scala 2421:22]
+    node _T_2277 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46]
     inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23]
     rvclkhdr_33.clock <= clock
     rvclkhdr_33.reset <= reset
     rvclkhdr_33.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17]
+    rvclkhdr_33.io.en <= _T_2277 @[lib.scala 371:17]
     rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_2288 <= mhpmc6h_ns @[lib.scala 374:16]
-    mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2423:10]
-    node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50]
-    node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56]
-    node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93]
-    node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2430:102]
-    node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2430:71]
-    node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141]
-    node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2430:28]
-    node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63]
-    node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70]
-    node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2432:41]
-    node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80]
-    reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2297 : @[Reg.scala 28:19]
-      _T_2298 <= event_saturate_r @[Reg.scala 28:23]
+    reg _T_2278 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_2278 <= mhpmc6h_ns @[lib.scala 374:16]
+    mhpmc6h <= _T_2278 @[dec_tlu_ctl.scala 2423:10]
+    node _T_2279 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50]
+    node _T_2280 = gt(_T_2279, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56]
+    node _T_2281 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93]
+    node _T_2282 = orr(_T_2281) @[dec_tlu_ctl.scala 2430:102]
+    node _T_2283 = or(_T_2280, _T_2282) @[dec_tlu_ctl.scala 2430:71]
+    node _T_2284 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141]
+    node event_saturate_r = mux(_T_2283, UInt<10>("h0204"), _T_2284) @[dec_tlu_ctl.scala 2430:28]
+    node _T_2285 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63]
+    node _T_2286 = eq(_T_2285, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70]
+    node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2286) @[dec_tlu_ctl.scala 2432:41]
+    node _T_2287 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80]
+    reg _T_2288 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2287 : @[Reg.scala 28:19]
+      _T_2288 <= event_saturate_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2434:9]
-    node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63]
-    node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70]
-    node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2439:41]
-    node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80]
-    reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2301 : @[Reg.scala 28:19]
-      _T_2302 <= event_saturate_r @[Reg.scala 28:23]
+    mhpme3 <= _T_2288 @[dec_tlu_ctl.scala 2434:9]
+    node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63]
+    node _T_2290 = eq(_T_2289, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70]
+    node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2290) @[dec_tlu_ctl.scala 2439:41]
+    node _T_2291 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80]
+    reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2291 : @[Reg.scala 28:19]
+      _T_2292 <= event_saturate_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2440:9]
-    node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63]
-    node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70]
-    node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2446:41]
-    node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80]
-    reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2305 : @[Reg.scala 28:19]
-      _T_2306 <= event_saturate_r @[Reg.scala 28:23]
+    mhpme4 <= _T_2292 @[dec_tlu_ctl.scala 2440:9]
+    node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63]
+    node _T_2294 = eq(_T_2293, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70]
+    node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2294) @[dec_tlu_ctl.scala 2446:41]
+    node _T_2295 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80]
+    reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2295 : @[Reg.scala 28:19]
+      _T_2296 <= event_saturate_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2447:9]
-    node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63]
-    node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70]
-    node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2453:41]
-    node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80]
-    reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2309 : @[Reg.scala 28:19]
-      _T_2310 <= event_saturate_r @[Reg.scala 28:23]
+    mhpme5 <= _T_2296 @[dec_tlu_ctl.scala 2447:9]
+    node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63]
+    node _T_2298 = eq(_T_2297, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70]
+    node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2298) @[dec_tlu_ctl.scala 2453:41]
+    node _T_2299 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80]
+    reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2299 : @[Reg.scala 28:19]
+      _T_2300 <= event_saturate_r @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2454:9]
-    node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70]
-    node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77]
-    node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2470:48]
-    node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54]
+    mhpme6 <= _T_2300 @[dec_tlu_ctl.scala 2454:9]
+    node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70]
+    node _T_2302 = eq(_T_2301, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77]
+    node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2302) @[dec_tlu_ctl.scala 2470:48]
+    node _T_2303 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54]
     wire temp_ncount0 : UInt<1>
-    temp_ncount0 <= _T_2313
-    node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54]
+    temp_ncount0 <= _T_2303
+    node _T_2304 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54]
     wire temp_ncount1 : UInt<1>
-    temp_ncount1 <= _T_2314
-    node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55]
+    temp_ncount1 <= _T_2304
+    node _T_2305 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55]
     wire temp_ncount6_2 : UInt<5>
-    temp_ncount6_2 <= _T_2315
-    node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74]
-    node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103]
-    reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2317 : @[Reg.scala 28:19]
-      _T_2318 <= _T_2316 @[Reg.scala 28:23]
+    temp_ncount6_2 <= _T_2305
+    node _T_2306 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74]
+    node _T_2307 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103]
+    reg _T_2308 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2307 : @[Reg.scala 28:19]
+      _T_2308 <= _T_2306 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2475:17]
-    node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72]
-    node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99]
-    reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_2320 : @[Reg.scala 28:19]
-      _T_2321 <= _T_2319 @[Reg.scala 28:23]
+    temp_ncount6_2 <= _T_2308 @[dec_tlu_ctl.scala 2475:17]
+    node _T_2309 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72]
+    node _T_2310 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99]
+    reg _T_2311 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_2310 : @[Reg.scala 28:19]
+      _T_2311 <= _T_2309 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2477:15]
-    node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58]
-    mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2478:16]
-    node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51]
-    node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78]
-    node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104]
-    node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130]
-    node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32]
-    node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2486:59]
-    node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2486:78]
+    temp_ncount0 <= _T_2311 @[dec_tlu_ctl.scala 2477:15]
+    node _T_2312 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_2313 = cat(_T_2312, temp_ncount0) @[Cat.scala 29:58]
+    mcountinhibit <= _T_2313 @[dec_tlu_ctl.scala 2478:16]
+    node _T_2314 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51]
+    node _T_2315 = or(_T_2314, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78]
+    node _T_2316 = or(_T_2315, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104]
+    node _T_2317 = or(_T_2316, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130]
+    node _T_2318 = or(_T_2317, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32]
+    node _T_2319 = or(_T_2318, io.clk_override) @[dec_tlu_ctl.scala 2486:59]
+    node _T_2320 = bits(_T_2319, 0, 0) @[dec_tlu_ctl.scala 2486:78]
     inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22]
     rvclkhdr_34.clock <= clock
     rvclkhdr_34.reset <= reset
     rvclkhdr_34.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16]
+    rvclkhdr_34.io.en <= _T_2320 @[lib.scala 345:16]
     rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62]
-    _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62]
-    io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2488:30]
-    node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91]
-    node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137]
-    node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2489:135]
-    node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2489:112]
-    reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62]
-    _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2489:62]
-    io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30]
-    reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62]
-    _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62]
-    io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30]
-    reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62]
-    _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62]
-    io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2491:30]
+    reg _T_2321 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62]
+    _T_2321 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62]
+    io.dec_tlu_i0_valid_wb1 <= _T_2321 @[dec_tlu_ctl.scala 2488:30]
+    node _T_2322 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91]
+    node _T_2323 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137]
+    node _T_2324 = and(io.trigger_hit_r_d1, _T_2323) @[dec_tlu_ctl.scala 2489:135]
+    node _T_2325 = or(_T_2322, _T_2324) @[dec_tlu_ctl.scala 2489:112]
+    reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62]
+    _T_2326 <= _T_2325 @[dec_tlu_ctl.scala 2489:62]
+    io.dec_tlu_i0_exc_valid_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2489:30]
+    reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62]
+    _T_2327 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62]
+    io.dec_tlu_exc_cause_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2490:30]
+    reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62]
+    _T_2328 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62]
+    io.dec_tlu_int_valid_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2491:30]
     io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2493:24]
-    node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61]
-    node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42]
-    node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40]
-    node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39]
-    node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40]
-    node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
-    node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40]
-    node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103]
-    node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128]
-    node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58]
-    node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58]
-    node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
-    node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58]
-    node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58]
-    node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38]
-    node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70]
-    node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96]
-    node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58]
-    node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36]
-    node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78]
-    node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102]
-    node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123]
-    node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144]
-    node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58]
-    node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58]
-    node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58]
-    node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58]
-    node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58]
-    node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36]
-    node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75]
-    node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96]
-    node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114]
-    node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132]
-    node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58]
-    node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58]
-    node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58]
-    node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58]
-    node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58]
-    node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40]
-    node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65]
-    node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40]
-    node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69]
-    node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42]
-    node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72]
-    node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42]
-    node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72]
-    node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41]
-    node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66]
-    node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37]
-    node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39]
-    node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64]
-    node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40]
-    node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80]
-    node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58]
-    node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38]
-    node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63]
-    node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37]
-    node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62]
-    node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39]
-    node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64]
-    node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38]
-    node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
-    node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39]
-    node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58]
-    node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58]
-    node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41]
-    node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81]
-    node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58]
-    node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41]
-    node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81]
-    node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58]
-    node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38]
-    node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78]
-    node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58]
-    node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37]
-    node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77]
-    node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58]
-    node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37]
-    node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77]
-    node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58]
-    node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37]
-    node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85]
-    node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58]
-    node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58]
-    node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36]
-    node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39]
-    node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64]
-    node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40]
-    node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65]
-    node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39]
-    node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64]
-    node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41]
-    node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80]
-    node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104]
-    node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131]
-    node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58]
-    node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58]
-    node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58]
-    node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58]
-    node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58]
-    node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38]
-    node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78]
-    node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58]
-    node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40]
-    node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74]
-    node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40]
-    node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74]
-    node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39]
-    node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64]
-    node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41]
-    node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66]
-    node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41]
-    node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66]
-    node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39]
-    node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64]
-    node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39]
-    node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64]
-    node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39]
-    node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64]
-    node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39]
-    node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64]
-    node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40]
-    node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65]
-    node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40]
-    node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65]
-    node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40]
-    node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65]
-    node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40]
-    node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65]
-    node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38]
-    node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78]
-    node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58]
-    node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38]
-    node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78]
-    node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58]
-    node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39]
-    node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79]
-    node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58]
-    node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39]
-    node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79]
-    node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58]
-    node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39]
-    node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78]
-    node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58]
-    node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39]
-    node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78]
-    node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58]
-    node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46]
-    node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86]
-    node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58]
-    node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37]
-    node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
-    node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37]
-    node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76]
-    node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72]
+    node _T_2329 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61]
+    node _T_2330 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42]
+    node _T_2331 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40]
+    node _T_2332 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39]
+    node _T_2333 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40]
+    node _T_2334 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
+    node _T_2335 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40]
+    node _T_2336 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103]
+    node _T_2337 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128]
+    node _T_2338 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58]
+    node _T_2339 = cat(_T_2338, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2340 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58]
+    node _T_2341 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
+    node _T_2342 = cat(_T_2341, _T_2340) @[Cat.scala 29:58]
+    node _T_2343 = cat(_T_2342, _T_2339) @[Cat.scala 29:58]
+    node _T_2344 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38]
+    node _T_2345 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70]
+    node _T_2346 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96]
+    node _T_2347 = cat(_T_2345, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_2348 = cat(_T_2347, _T_2346) @[Cat.scala 29:58]
+    node _T_2349 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36]
+    node _T_2350 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78]
+    node _T_2351 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102]
+    node _T_2352 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123]
+    node _T_2353 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144]
+    node _T_2354 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2355 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2356 = cat(_T_2355, _T_2354) @[Cat.scala 29:58]
+    node _T_2357 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2358 = cat(UInt<1>("h00"), _T_2350) @[Cat.scala 29:58]
+    node _T_2359 = cat(_T_2358, UInt<16>("h00")) @[Cat.scala 29:58]
+    node _T_2360 = cat(_T_2359, _T_2357) @[Cat.scala 29:58]
+    node _T_2361 = cat(_T_2360, _T_2356) @[Cat.scala 29:58]
+    node _T_2362 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36]
+    node _T_2363 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75]
+    node _T_2364 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96]
+    node _T_2365 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114]
+    node _T_2366 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132]
+    node _T_2367 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2368 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2369 = cat(_T_2368, _T_2367) @[Cat.scala 29:58]
+    node _T_2370 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2371 = cat(UInt<1>("h00"), _T_2363) @[Cat.scala 29:58]
+    node _T_2372 = cat(_T_2371, UInt<16>("h00")) @[Cat.scala 29:58]
+    node _T_2373 = cat(_T_2372, _T_2370) @[Cat.scala 29:58]
+    node _T_2374 = cat(_T_2373, _T_2369) @[Cat.scala 29:58]
+    node _T_2375 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40]
+    node _T_2376 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65]
+    node _T_2377 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40]
+    node _T_2378 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69]
+    node _T_2379 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42]
+    node _T_2380 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72]
+    node _T_2381 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42]
+    node _T_2382 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72]
+    node _T_2383 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41]
+    node _T_2384 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66]
+    node _T_2385 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37]
+    node _T_2386 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_2387 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39]
+    node _T_2388 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64]
+    node _T_2389 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40]
+    node _T_2390 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80]
+    node _T_2391 = cat(UInt<28>("h00"), _T_2390) @[Cat.scala 29:58]
+    node _T_2392 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38]
+    node _T_2393 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63]
+    node _T_2394 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37]
+    node _T_2395 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62]
+    node _T_2396 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39]
+    node _T_2397 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64]
+    node _T_2398 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38]
+    node _T_2399 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
+    node _T_2400 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39]
+    node _T_2401 = cat(meivt, meihap) @[Cat.scala 29:58]
+    node _T_2402 = cat(_T_2401, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_2403 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41]
+    node _T_2404 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81]
+    node _T_2405 = cat(UInt<28>("h00"), _T_2404) @[Cat.scala 29:58]
+    node _T_2406 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41]
+    node _T_2407 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81]
+    node _T_2408 = cat(UInt<28>("h00"), _T_2407) @[Cat.scala 29:58]
+    node _T_2409 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38]
+    node _T_2410 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78]
+    node _T_2411 = cat(UInt<28>("h00"), _T_2410) @[Cat.scala 29:58]
+    node _T_2412 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37]
+    node _T_2413 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77]
+    node _T_2414 = cat(UInt<23>("h00"), _T_2413) @[Cat.scala 29:58]
+    node _T_2415 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37]
+    node _T_2416 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77]
+    node _T_2417 = cat(UInt<13>("h00"), _T_2416) @[Cat.scala 29:58]
+    node _T_2418 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37]
+    node _T_2419 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85]
+    node _T_2420 = cat(UInt<16>("h04000"), _T_2419) @[Cat.scala 29:58]
+    node _T_2421 = cat(_T_2420, UInt<2>("h03")) @[Cat.scala 29:58]
+    node _T_2422 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36]
+    node _T_2423 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_2424 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39]
+    node _T_2425 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64]
+    node _T_2426 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40]
+    node _T_2427 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65]
+    node _T_2428 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39]
+    node _T_2429 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64]
+    node _T_2430 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41]
+    node _T_2431 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80]
+    node _T_2432 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104]
+    node _T_2433 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131]
+    node _T_2434 = cat(UInt<3>("h00"), _T_2433) @[Cat.scala 29:58]
+    node _T_2435 = cat(_T_2434, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_2436 = cat(UInt<2>("h00"), _T_2432) @[Cat.scala 29:58]
+    node _T_2437 = cat(UInt<7>("h00"), _T_2431) @[Cat.scala 29:58]
+    node _T_2438 = cat(_T_2437, _T_2436) @[Cat.scala 29:58]
+    node _T_2439 = cat(_T_2438, _T_2435) @[Cat.scala 29:58]
+    node _T_2440 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38]
+    node _T_2441 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78]
+    node _T_2442 = cat(UInt<30>("h00"), _T_2441) @[Cat.scala 29:58]
+    node _T_2443 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40]
+    node _T_2444 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74]
+    node _T_2445 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40]
+    node _T_2446 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74]
+    node _T_2447 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39]
+    node _T_2448 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64]
+    node _T_2449 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41]
+    node _T_2450 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66]
+    node _T_2451 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41]
+    node _T_2452 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66]
+    node _T_2453 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39]
+    node _T_2454 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64]
+    node _T_2455 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39]
+    node _T_2456 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64]
+    node _T_2457 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39]
+    node _T_2458 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64]
+    node _T_2459 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39]
+    node _T_2460 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64]
+    node _T_2461 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40]
+    node _T_2462 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65]
+    node _T_2463 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40]
+    node _T_2464 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65]
+    node _T_2465 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40]
+    node _T_2466 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65]
+    node _T_2467 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40]
+    node _T_2468 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65]
+    node _T_2469 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38]
+    node _T_2470 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78]
+    node _T_2471 = cat(UInt<26>("h00"), _T_2470) @[Cat.scala 29:58]
+    node _T_2472 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38]
+    node _T_2473 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78]
+    node _T_2474 = cat(UInt<30>("h00"), _T_2473) @[Cat.scala 29:58]
+    node _T_2475 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39]
+    node _T_2476 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79]
+    node _T_2477 = cat(UInt<22>("h00"), _T_2476) @[Cat.scala 29:58]
+    node _T_2478 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39]
+    node _T_2479 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79]
+    node _T_2480 = cat(UInt<22>("h00"), _T_2479) @[Cat.scala 29:58]
+    node _T_2481 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39]
+    node _T_2482 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78]
+    node _T_2483 = cat(UInt<22>("h00"), _T_2482) @[Cat.scala 29:58]
+    node _T_2484 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39]
+    node _T_2485 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78]
+    node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58]
+    node _T_2487 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46]
+    node _T_2488 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86]
+    node _T_2489 = cat(UInt<25>("h00"), _T_2488) @[Cat.scala 29:58]
+    node _T_2490 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37]
+    node _T_2491 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
+    node _T_2492 = cat(_T_2491, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_2493 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37]
+    node _T_2494 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76]
+    node _T_2495 = mux(_T_2329, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2496 = mux(_T_2330, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2497 = mux(_T_2331, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2498 = mux(_T_2332, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2499 = mux(_T_2333, _T_2334, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2500 = mux(_T_2335, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2501 = mux(_T_2344, _T_2348, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2502 = mux(_T_2349, _T_2361, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2503 = mux(_T_2362, _T_2374, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2504 = mux(_T_2375, _T_2376, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2505 = mux(_T_2377, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2506 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2507 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2508 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2509 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2510 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2511 = mux(_T_2389, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2512 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2513 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2514 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2515 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2516 = mux(_T_2400, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2517 = mux(_T_2403, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2518 = mux(_T_2406, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2519 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2520 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2521 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2522 = mux(_T_2418, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2523 = mux(_T_2422, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2524 = mux(_T_2424, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2525 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2526 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2527 = mux(_T_2430, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2528 = mux(_T_2440, _T_2442, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2529 = mux(_T_2443, _T_2444, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2530 = mux(_T_2445, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2531 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2532 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2533 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2534 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2535 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2536 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2537 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2538 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2539 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2540 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2541 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2542 = mux(_T_2469, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2543 = mux(_T_2472, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2544 = mux(_T_2475, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2545 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2546 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2547 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2548 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2549 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2550 = mux(_T_2493, _T_2494, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_2551 = or(_T_2495, _T_2496) @[Mux.scala 27:72]
+    node _T_2552 = or(_T_2551, _T_2497) @[Mux.scala 27:72]
+    node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72]
+    node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72]
+    node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72]
+    node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72]
+    node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72]
+    node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72]
+    node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72]
+    node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72]
+    node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72]
     node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72]
     node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72]
     node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72]
@@ -76167,19 +76167,9 @@ circuit quasar_wrapper :
     node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72]
     node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72]
     node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72]
-    node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72]
-    node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72]
-    node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72]
-    node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72]
-    node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72]
-    node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72]
-    node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72]
-    node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72]
-    node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72]
-    node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72]
-    wire _T_2616 : UInt @[Mux.scala 27:72]
-    _T_2616 <= _T_2615 @[Mux.scala 27:72]
-    io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2498:21]
+    wire _T_2606 : UInt @[Mux.scala 27:72]
+    _T_2606 <= _T_2605 @[Mux.scala 27:72]
+    io.dec_csr_rddata_d <= _T_2606 @[dec_tlu_ctl.scala 2498:21]
     
   module dec_decode_csr_read : 
     input clock : Clock
@@ -114799,7 +114789,7 @@ circuit quasar_wrapper :
   module quasar_wrapper : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_brg : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>}
+    output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_brg : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_brg : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>}
     
     inst mem of mem @[quasar_wrapper.scala 63:19]
     mem.scan_mode is invalid
@@ -114827,354 +114817,466 @@ circuit quasar_wrapper :
     dmi_wrapper.tms is invalid
     dmi_wrapper.tck is invalid
     dmi_wrapper.trst_n is invalid
-    inst swerv of quasar @[quasar_wrapper.scala 65:21]
-    swerv.clock <= clock
-    swerv.reset <= reset
-    swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 66:22]
+    inst core of quasar @[quasar_wrapper.scala 65:20]
+    core.clock <= clock
+    core.reset <= reset
+    core.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 66:21]
     dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 67:25]
     dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 68:22]
     dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 69:22]
     dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 70:22]
     dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 71:27]
     dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 72:26]
-    dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 73:26]
+    dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 73:26]
     dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 76:29]
-    swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 77:26]
-    swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 78:25]
-    swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 79:23]
-    swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 80:26]
-    swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 81:27]
+    core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 77:25]
+    core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 78:24]
+    core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 79:22]
+    core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 80:25]
+    core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 81:26]
     io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 82:15]
-    mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 85:28]
-    mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 86:27]
-    mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 87:35]
-    swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 88:15]
-    swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 88:15]
-    mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 88:15]
-    mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 88:15]
-    mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 88:15]
-    mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 88:15]
-    mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 88:15]
-    mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 88:15]
-    mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 88:15]
-    mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 88:15]
+    mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 85:28]
+    mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 86:27]
+    mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 87:35]
+    core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 88:15]
+    core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 88:15]
+    mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 88:15]
+    mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 88:15]
+    mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 88:15]
+    mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 88:15]
+    mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 88:15]
+    mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 88:15]
+    mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 88:15]
+    mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 88:15]
     mem.rst_l <= reset @[quasar_wrapper.scala 89:16]
     mem.clk <= clock @[quasar_wrapper.scala 90:14]
     mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 91:20]
-    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 93:22]
-    mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 94:15]
-    mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 94:15]
-    swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 94:15]
-    mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 94:15]
-    mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 94:15]
-    mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 94:15]
-    mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 94:15]
-    mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 94:15]
-    mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 94:15]
-    mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 94:15]
-    swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 95:17]
-    swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 95:17]
-    mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 95:17]
-    mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 95:17]
-    mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 95:17]
-    mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 95:17]
-    mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 95:17]
-    mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:17]
-    mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 95:17]
-    wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:33]
-    _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:33]
-    _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
-    _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:33]
-    _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33]
-    _T.out.hwdata <= swerv.io.ahb.out.hwdata @[quasar_wrapper.scala 99:18]
-    _T.out.hwrite <= swerv.io.ahb.out.hwrite @[quasar_wrapper.scala 99:18]
-    _T.out.htrans <= swerv.io.ahb.out.htrans @[quasar_wrapper.scala 99:18]
-    _T.out.hsize <= swerv.io.ahb.out.hsize @[quasar_wrapper.scala 99:18]
-    _T.out.hprot <= swerv.io.ahb.out.hprot @[quasar_wrapper.scala 99:18]
-    _T.out.hmastlock <= swerv.io.ahb.out.hmastlock @[quasar_wrapper.scala 99:18]
-    _T.out.hburst <= swerv.io.ahb.out.hburst @[quasar_wrapper.scala 99:18]
-    _T.out.haddr <= swerv.io.ahb.out.haddr @[quasar_wrapper.scala 99:18]
-    swerv.io.ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 99:18]
-    swerv.io.ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 99:18]
-    swerv.io.ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 99:18]
-    wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:37]
-    _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:37]
-    _T_1.out.hwdata <= swerv.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 100:22]
-    _T_1.out.hwrite <= swerv.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 100:22]
-    _T_1.out.htrans <= swerv.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 100:22]
-    _T_1.out.hsize <= swerv.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 100:22]
-    _T_1.out.hprot <= swerv.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 100:22]
-    _T_1.out.hmastlock <= swerv.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 100:22]
-    _T_1.out.hburst <= swerv.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 100:22]
-    _T_1.out.haddr <= swerv.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 100:22]
-    swerv.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 100:22]
-    swerv.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 100:22]
-    swerv.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 100:22]
-    wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 101:36]
-    _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36]
-    _T_2.out.hwdata <= swerv.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 101:21]
-    _T_2.out.hwrite <= swerv.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 101:21]
-    _T_2.out.htrans <= swerv.io.sb_ahb.out.htrans @[quasar_wrapper.scala 101:21]
-    _T_2.out.hsize <= swerv.io.sb_ahb.out.hsize @[quasar_wrapper.scala 101:21]
-    _T_2.out.hprot <= swerv.io.sb_ahb.out.hprot @[quasar_wrapper.scala 101:21]
-    _T_2.out.hmastlock <= swerv.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 101:21]
-    _T_2.out.hburst <= swerv.io.sb_ahb.out.hburst @[quasar_wrapper.scala 101:21]
-    _T_2.out.haddr <= swerv.io.sb_ahb.out.haddr @[quasar_wrapper.scala 101:21]
-    swerv.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 101:21]
-    swerv.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 101:21]
-    swerv.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 101:21]
-    wire _T_3 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 102:37]
-    _T_3.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 102:37]
-    _T_3.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:37]
-    swerv.io.dma.ahb.out.hwdata <= _T_3.out.hwdata @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.hwrite <= _T_3.out.hwrite @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.htrans <= _T_3.out.htrans @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.hsize <= _T_3.out.hsize @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.hprot <= _T_3.out.hprot @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.hmastlock <= _T_3.out.hmastlock @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.hburst <= _T_3.out.hburst @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.ahb.out.haddr <= _T_3.out.haddr @[quasar_wrapper.scala 102:22]
-    _T_3.in.hresp <= swerv.io.dma.ahb.in.hresp @[quasar_wrapper.scala 102:22]
-    _T_3.in.hready <= swerv.io.dma.ahb.in.hready @[quasar_wrapper.scala 102:22]
-    _T_3.in.hrdata <= swerv.io.dma.ahb.in.hrdata @[quasar_wrapper.scala 102:22]
-    swerv.io.dma.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 103:23]
-    swerv.io.dma.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 104:27]
-    swerv.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 105:22]
-    io.lsu_brg.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 105:22]
-    swerv.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 105:22]
-    swerv.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 106:22]
-    io.ifu_brg.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 106:22]
-    swerv.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 106:22]
-    swerv.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 107:21]
-    io.sb_brg.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 107:21]
-    io.sb_brg.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 107:21]
-    io.sb_brg.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 107:21]
-    io.sb_brg.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 107:21]
-    io.sb_brg.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 107:21]
-    io.sb_brg.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 107:21]
-    io.sb_brg.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 107:21]
-    io.sb_brg.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 107:21]
-    swerv.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 107:21]
-    io.dma_brg.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 108:22]
-    io.dma_brg.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 108:22]
-    io.dma_brg.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 108:22]
-    io.dma_brg.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 108:22]
-    io.dma_brg.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 108:22]
-    io.dma_brg.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 108:22]
-    io.dma_brg.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 108:22]
-    io.dma_brg.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 108:22]
-    io.dma_brg.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 108:22]
-    io.dma_brg.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 108:22]
-    swerv.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 108:22]
-    io.dma_brg.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 108:22]
-    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 122:22]
-    swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 123:20]
-    swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 124:20]
-    swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 125:20]
-    swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 128:27]
-    swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 129:26]
-    swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 130:20]
-    swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 133:31]
-    swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 134:30]
-    swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 135:30]
-    swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 137:27]
-    swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 138:27]
-    swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 139:27]
-    swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 140:27]
-    swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 142:22]
-    swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 143:21]
-    swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 144:26]
-    io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 148:19]
-    io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 148:19]
-    io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 151:21]
-    io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 152:24]
-    io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 153:20]
-    io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 154:26]
-    io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 156:25]
-    io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 157:24]
-    io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 158:25]
-    io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 160:23]
-    io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 161:23]
-    io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 162:23]
-    io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 163:23]
+    core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 93:21]
+    mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 94:14]
+    mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 94:14]
+    core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 94:14]
+    core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 94:14]
+    core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 94:14]
+    core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 94:14]
+    core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 94:14]
+    core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 94:14]
+    core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 94:14]
+    mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 94:14]
+    mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 94:14]
+    mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 94:14]
+    mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 94:14]
+    mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 94:14]
+    mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 94:14]
+    mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 94:14]
+    core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 95:16]
+    core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 95:16]
+    mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 95:16]
+    mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 95:16]
+    mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 95:16]
+    mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 95:16]
+    mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 95:16]
+    mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:16]
+    mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 95:16]
+    io.ifu_brg.out.hwdata <= core.io.ahb.out.hwdata @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.hwrite <= core.io.ahb.out.hwrite @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.htrans <= core.io.ahb.out.htrans @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.hsize <= core.io.ahb.out.hsize @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.hprot <= core.io.ahb.out.hprot @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.hmastlock <= core.io.ahb.out.hmastlock @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.hburst <= core.io.ahb.out.hburst @[quasar_wrapper.scala 111:17]
+    io.ifu_brg.out.haddr <= core.io.ahb.out.haddr @[quasar_wrapper.scala 111:17]
+    core.io.ahb.in.hresp <= io.ifu_brg.in.hresp @[quasar_wrapper.scala 111:17]
+    core.io.ahb.in.hready <= io.ifu_brg.in.hready @[quasar_wrapper.scala 111:17]
+    core.io.ahb.in.hrdata <= io.ifu_brg.in.hrdata @[quasar_wrapper.scala 111:17]
+    io.lsu_brg.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 112:21]
+    io.lsu_brg.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 112:21]
+    core.io.lsu_ahb.in.hresp <= io.lsu_brg.in.hresp @[quasar_wrapper.scala 112:21]
+    core.io.lsu_ahb.in.hready <= io.lsu_brg.in.hready @[quasar_wrapper.scala 112:21]
+    core.io.lsu_ahb.in.hrdata <= io.lsu_brg.in.hrdata @[quasar_wrapper.scala 112:21]
+    io.sb_brg.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 113:20]
+    io.sb_brg.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 113:20]
+    core.io.sb_ahb.in.hresp <= io.sb_brg.in.hresp @[quasar_wrapper.scala 113:20]
+    core.io.sb_ahb.in.hready <= io.sb_brg.in.hready @[quasar_wrapper.scala 113:20]
+    core.io.sb_ahb.in.hrdata <= io.sb_brg.in.hrdata @[quasar_wrapper.scala 113:20]
+    core.io.dma.hreadyin <= io.dma_brg.hreadyin @[quasar_wrapper.scala 114:17]
+    core.io.dma.hsel <= io.dma_brg.hsel @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hwdata <= io.dma_brg.ahb.out.hwdata @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hwrite <= io.dma_brg.ahb.out.hwrite @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.htrans <= io.dma_brg.ahb.out.htrans @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hsize <= io.dma_brg.ahb.out.hsize @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hprot <= io.dma_brg.ahb.out.hprot @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hmastlock <= io.dma_brg.ahb.out.hmastlock @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.hburst <= io.dma_brg.ahb.out.hburst @[quasar_wrapper.scala 114:17]
+    core.io.dma.ahb.out.haddr <= io.dma_brg.ahb.out.haddr @[quasar_wrapper.scala 114:17]
+    io.dma_brg.ahb.in.hresp <= core.io.dma.ahb.in.hresp @[quasar_wrapper.scala 114:17]
+    io.dma_brg.ahb.in.hready <= core.io.dma.ahb.in.hready @[quasar_wrapper.scala 114:17]
+    io.dma_brg.ahb.in.hrdata <= core.io.dma.ahb.in.hrdata @[quasar_wrapper.scala 114:17]
+    wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 116:36]
+    _T.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36]
+    _T.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36]
+    _T.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 116:36]
+    _T.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 116:36]
+    _T.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 116:36]
+    _T.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    _T.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 116:36]
+    core.io.lsu_axi.r.bits.last <= _T.r.bits.last @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.r.bits.resp <= _T.r.bits.resp @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.r.bits.data <= _T.r.bits.data @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.r.bits.id <= _T.r.bits.id @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.r.valid <= _T.r.valid @[quasar_wrapper.scala 116:21]
+    _T.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 116:21]
+    _T.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 116:21]
+    _T.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.ar.ready <= _T.ar.ready @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.b.bits.id <= _T.b.bits.id @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.b.bits.resp <= _T.b.bits.resp @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.b.valid <= _T.b.valid @[quasar_wrapper.scala 116:21]
+    _T.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 116:21]
+    _T.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 116:21]
+    _T.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 116:21]
+    _T.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 116:21]
+    _T.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.w.ready <= _T.w.ready @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 116:21]
+    _T.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 116:21]
+    _T.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 116:21]
+    core.io.lsu_axi.aw.ready <= _T.aw.ready @[quasar_wrapper.scala 116:21]
+    wire _T_1 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 117:36]
+    _T_1.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    _T_1.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 117:36]
+    core.io.ifu_axi.r.bits.last <= _T_1.r.bits.last @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.r.bits.resp <= _T_1.r.bits.resp @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.r.bits.data <= _T_1.r.bits.data @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.r.bits.id <= _T_1.r.bits.id @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.r.valid <= _T_1.r.valid @[quasar_wrapper.scala 117:21]
+    _T_1.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 117:21]
+    _T_1.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 117:21]
+    _T_1.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.ar.ready <= _T_1.ar.ready @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.b.bits.id <= _T_1.b.bits.id @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.b.bits.resp <= _T_1.b.bits.resp @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.b.valid <= _T_1.b.valid @[quasar_wrapper.scala 117:21]
+    _T_1.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 117:21]
+    _T_1.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 117:21]
+    _T_1.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 117:21]
+    _T_1.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 117:21]
+    _T_1.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.w.ready <= _T_1.w.ready @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 117:21]
+    _T_1.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 117:21]
+    _T_1.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 117:21]
+    core.io.ifu_axi.aw.ready <= _T_1.aw.ready @[quasar_wrapper.scala 117:21]
+    wire _T_2 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 118:35]
+    _T_2.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.r.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.b.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.bits.id <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    _T_2.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 118:35]
+    core.io.sb_axi.r.bits.last <= _T_2.r.bits.last @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.r.bits.resp <= _T_2.r.bits.resp @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.r.bits.data <= _T_2.r.bits.data @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.r.bits.id <= _T_2.r.bits.id @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.r.valid <= _T_2.r.valid @[quasar_wrapper.scala 118:20]
+    _T_2.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 118:20]
+    _T_2.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 118:20]
+    _T_2.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.ar.ready <= _T_2.ar.ready @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.b.bits.id <= _T_2.b.bits.id @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.b.bits.resp <= _T_2.b.bits.resp @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.b.valid <= _T_2.b.valid @[quasar_wrapper.scala 118:20]
+    _T_2.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 118:20]
+    _T_2.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 118:20]
+    _T_2.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 118:20]
+    _T_2.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 118:20]
+    _T_2.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.w.ready <= _T_2.w.ready @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 118:20]
+    _T_2.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 118:20]
+    _T_2.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 118:20]
+    core.io.sb_axi.aw.ready <= _T_2.aw.ready @[quasar_wrapper.scala 118:20]
+    wire _T_3 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar_wrapper.scala 119:36]
+    _T_3.r.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.valid <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.ready <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.valid <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.ar.ready <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.b.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.b.bits.resp <= UInt<2>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.b.valid <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.b.ready <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.w.bits.last <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.w.bits.strb <= UInt<8>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.w.bits.data <= UInt<64>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.w.valid <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.w.ready <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.qos <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.prot <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.cache <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.lock <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.burst <= UInt<2>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.size <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.len <= UInt<8>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.region <= UInt<4>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.addr <= UInt<32>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.bits.id <= UInt<3>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.valid <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.aw.ready <= UInt<1>("h00") @[quasar_wrapper.scala 119:36]
+    _T_3.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 119:21]
+    _T_3.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 119:21]
+    _T_3.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 119:21]
+    _T_3.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 119:21]
+    _T_3.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.r.ready <= _T_3.r.ready @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.qos <= _T_3.ar.bits.qos @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.prot <= _T_3.ar.bits.prot @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.cache <= _T_3.ar.bits.cache @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.lock <= _T_3.ar.bits.lock @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.burst <= _T_3.ar.bits.burst @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.size <= _T_3.ar.bits.size @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.len <= _T_3.ar.bits.len @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.region <= _T_3.ar.bits.region @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.addr <= _T_3.ar.bits.addr @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.bits.id <= _T_3.ar.bits.id @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.ar.valid <= _T_3.ar.valid @[quasar_wrapper.scala 119:21]
+    _T_3.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 119:21]
+    _T_3.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 119:21]
+    _T_3.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 119:21]
+    _T_3.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.b.ready <= _T_3.b.ready @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.w.bits.last <= _T_3.w.bits.last @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.w.bits.strb <= _T_3.w.bits.strb @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.w.bits.data <= _T_3.w.bits.data @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.w.valid <= _T_3.w.valid @[quasar_wrapper.scala 119:21]
+    _T_3.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.qos <= _T_3.aw.bits.qos @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.prot <= _T_3.aw.bits.prot @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.cache <= _T_3.aw.bits.cache @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.lock <= _T_3.aw.bits.lock @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.burst <= _T_3.aw.bits.burst @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.size <= _T_3.aw.bits.size @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.len <= _T_3.aw.bits.len @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.region <= _T_3.aw.bits.region @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.addr <= _T_3.aw.bits.addr @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.bits.id <= _T_3.aw.bits.id @[quasar_wrapper.scala 119:21]
+    core.io.dma_axi.aw.valid <= _T_3.aw.valid @[quasar_wrapper.scala 119:21]
+    _T_3.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 119:21]
+    core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 122:21]
+    core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 123:19]
+    core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 124:19]
+    core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 125:19]
+    core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 128:26]
+    core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 129:25]
+    core.io.core_id <= io.core_id @[quasar_wrapper.scala 130:19]
+    core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 133:30]
+    core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 134:29]
+    core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 135:29]
+    core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 137:26]
+    core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 138:26]
+    core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 139:26]
+    core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 140:26]
+    core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 142:21]
+    core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 143:20]
+    core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 144:25]
+    io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 148:19]
+    io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 148:19]
+    io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 151:21]
+    io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 152:24]
+    io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 153:20]
+    io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 154:26]
+    io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 156:25]
+    io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 157:24]
+    io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 158:25]
+    io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 160:23]
+    io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 161:23]
+    io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 162:23]
+    io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 163:23]
     
diff --git a/quasar_wrapper.v b/quasar_wrapper.v
index 1f1d739b..2e6fcce9 100644
--- a/quasar_wrapper.v
+++ b/quasar_wrapper.v
@@ -38,7 +38,6 @@ module ifu_mem_ctl(
   output        io_dec_mem_ctrl_ifu_pmu_ic_hit,
   output        io_dec_mem_ctrl_ifu_pmu_bus_error,
   output        io_dec_mem_ctrl_ifu_pmu_bus_busy,
-  output        io_dec_mem_ctrl_ifu_pmu_bus_trxn,
   output        io_dec_mem_ctrl_ifu_ic_error_start,
   output        io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   output [70:0] io_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -53,16 +52,8 @@ module ifu_mem_ctl(
   input         io_ifc_dma_access_ok,
   input         io_ifu_bp_hit_taken_f,
   input         io_ifu_bp_inst_mask_f,
-  input         io_ifu_axi_ar_ready,
   output        io_ifu_axi_ar_valid,
-  output [2:0]  io_ifu_axi_ar_bits_id,
   output [31:0] io_ifu_axi_ar_bits_addr,
-  output [3:0]  io_ifu_axi_ar_bits_region,
-  output        io_ifu_axi_r_ready,
-  input         io_ifu_axi_r_valid,
-  input  [2:0]  io_ifu_axi_r_bits_id,
-  input  [63:0] io_ifu_axi_r_bits_data,
-  input  [1:0]  io_ifu_axi_r_bits_resp,
   input         io_ifu_bus_clk_en,
   input         io_dma_mem_ctl_dma_iccm_req,
   input  [31:0] io_dma_mem_ctl_dma_mem_addr,
@@ -81,10 +72,7 @@ module ifu_mem_ctl(
   input  [77:0] io_iccm_rd_data_ecc,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
-  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
-  output [70:0] io_ic_wr_data_0,
-  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -102,7 +90,6 @@ module ifu_mem_ctl(
   input  [1:0]  io_ifu_fetch_val,
   output        io_ifu_ic_mb_empty,
   output        io_ic_dma_active,
-  output        io_ic_write_stall,
   output        io_iccm_dma_ecc_error,
   output        io_iccm_dma_rvalid,
   output [63:0] io_iccm_dma_rdata,
@@ -284,7 +271,7 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_161;
   reg [31:0] _RAND_162;
   reg [31:0] _RAND_163;
-  reg [63:0] _RAND_164;
+  reg [31:0] _RAND_164;
   reg [31:0] _RAND_165;
   reg [31:0] _RAND_166;
   reg [31:0] _RAND_167;
@@ -533,7 +520,7 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_410;
   reg [31:0] _RAND_411;
   reg [31:0] _RAND_412;
-  reg [31:0] _RAND_413;
+  reg [95:0] _RAND_413;
   reg [31:0] _RAND_414;
   reg [31:0] _RAND_415;
   reg [31:0] _RAND_416;
@@ -541,13 +528,13 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_418;
   reg [31:0] _RAND_419;
   reg [31:0] _RAND_420;
-  reg [31:0] _RAND_421;
+  reg [63:0] _RAND_421;
   reg [31:0] _RAND_422;
   reg [31:0] _RAND_423;
   reg [31:0] _RAND_424;
   reg [31:0] _RAND_425;
   reg [31:0] _RAND_426;
-  reg [31:0] _RAND_427;
+  reg [63:0] _RAND_427;
   reg [31:0] _RAND_428;
   reg [31:0] _RAND_429;
   reg [31:0] _RAND_430;
@@ -561,38 +548,6 @@ module ifu_mem_ctl(
   reg [31:0] _RAND_438;
   reg [31:0] _RAND_439;
   reg [31:0] _RAND_440;
-  reg [31:0] _RAND_441;
-  reg [95:0] _RAND_442;
-  reg [31:0] _RAND_443;
-  reg [31:0] _RAND_444;
-  reg [31:0] _RAND_445;
-  reg [31:0] _RAND_446;
-  reg [31:0] _RAND_447;
-  reg [31:0] _RAND_448;
-  reg [31:0] _RAND_449;
-  reg [31:0] _RAND_450;
-  reg [31:0] _RAND_451;
-  reg [63:0] _RAND_452;
-  reg [31:0] _RAND_453;
-  reg [31:0] _RAND_454;
-  reg [31:0] _RAND_455;
-  reg [31:0] _RAND_456;
-  reg [31:0] _RAND_457;
-  reg [63:0] _RAND_458;
-  reg [31:0] _RAND_459;
-  reg [31:0] _RAND_460;
-  reg [31:0] _RAND_461;
-  reg [31:0] _RAND_462;
-  reg [31:0] _RAND_463;
-  reg [31:0] _RAND_464;
-  reg [31:0] _RAND_465;
-  reg [31:0] _RAND_466;
-  reg [31:0] _RAND_467;
-  reg [31:0] _RAND_468;
-  reg [31:0] _RAND_469;
-  reg [31:0] _RAND_470;
-  reg [31:0] _RAND_471;
-  reg [31:0] _RAND_472;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -978,9 +933,6 @@ module ifu_mem_ctl(
   reg [2:0] miss_state; // @[Reg.scala 27:20]
   wire  miss_pending = miss_state != 3'h0; // @[ifu_mem_ctl.scala 159:30]
   wire  _T_1 = _T | miss_pending; // @[ifu_mem_ctl.scala 91:71]
-  wire  _T_2 = _T_1 | io_exu_flush_final; // @[ifu_mem_ctl.scala 91:86]
-  reg  scnd_miss_req_q; // @[ifu_mem_ctl.scala 464:52]
-  wire  scnd_miss_req = scnd_miss_req_q & _T_319; // @[ifu_mem_ctl.scala 466:36]
   wire  debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 92:42]
   wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
   reg [30:0] ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 214:63]
@@ -1090,8 +1042,6 @@ module ifu_mem_ctl(
   wire  _GEN_41 = _T_2531 ? _T_2557 : _GEN_37; // @[Conditional.scala 39:67]
   wire  err_stop_fetch = _T_2526 ? 1'h0 : _GEN_41; // @[Conditional.scala 40:58]
   wire  _T_11 = _T_10 | err_stop_fetch; // @[ifu_mem_ctl.scala 97:112]
-  wire  _T_13 = io_ifu_axi_r_valid & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 99:44]
-  wire  _T_14 = _T_13 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 99:65]
   wire  _T_227 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 189:37]
   wire  _T_228 = ~_T_227; // @[ifu_mem_ctl.scala 189:23]
   reg  reset_all_tags; // @[ifu_mem_ctl.scala 638:53]
@@ -1104,36 +1054,10 @@ module ifu_mem_ctl(
   wire  _T_230 = _T_229 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 189:59]
   wire  _T_231 = ~miss_pending; // @[ifu_mem_ctl.scala 189:82]
   wire  _T_232 = _T_230 & _T_231; // @[ifu_mem_ctl.scala 189:80]
-  wire  _T_233 = _T_232 | scnd_miss_req; // @[ifu_mem_ctl.scala 189:97]
-  wire  ic_act_miss_f = _T_233 & _T_209; // @[ifu_mem_ctl.scala 189:114]
-  reg  ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 511:56]
-  reg  bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 463:61]
-  wire  ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 525:49]
-  wire  bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 553:41]
+  wire  ic_act_miss_f = _T_232 & _T_209; // @[ifu_mem_ctl.scala 189:114]
   reg  uncacheable_miss_ff; // @[ifu_mem_ctl.scala 216:62]
-  reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 534:56]
-  wire  _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 551:69]
-  wire  _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 551:101]
-  wire  bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 551:28]
-  wire  _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 530:68]
-  wire  _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 530:48]
-  wire  bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 530:91]
-  wire  _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 529:50]
-  wire  _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 529:48]
   wire  _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 529:72]
-  wire  bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 529:70]
-  wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 533:115]
-  wire [2:0] _T_2631 = bus_inc_data_beat_cnt ? _T_2629 : 3'h0; // @[Mux.scala 27:72]
-  wire  _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 531:32]
-  wire  _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 531:57]
-  wire  bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 531:55]
-  wire [2:0] _T_2632 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] bus_new_data_beat_count = _T_2631 | _T_2632; // @[Mux.scala 27:72]
-  wire  _T_15 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 99:112]
-  wire  _T_16 = _T_14 & _T_15; // @[ifu_mem_ctl.scala 99:85]
   wire  _T_17 = ~uncacheable_miss_ff; // @[ifu_mem_ctl.scala 100:5]
-  wire  _T_18 = _T_16 & _T_17; // @[ifu_mem_ctl.scala 99:118]
-  wire  _T_19 = miss_state == 3'h5; // @[ifu_mem_ctl.scala 100:41]
   wire  _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_26 = ic_act_miss_f & _T_319; // @[ifu_mem_ctl.scala 106:43]
   wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[ifu_mem_ctl.scala 106:27]
@@ -1214,55 +1138,27 @@ module ifu_mem_ctl(
   wire  _T_215 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 184:35]
   wire  _T_216 = _T_215 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 184:52]
   wire  ic_byp_hit_f = _T_216 & miss_pending; // @[ifu_mem_ctl.scala 184:73]
-  reg  last_data_recieved_ff; // @[ifu_mem_ctl.scala 536:58]
-  wire  last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 563:35]
-  wire  _T_32 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 110:126]
-  wire  _T_33 = last_data_recieved_ff | _T_32; // @[ifu_mem_ctl.scala 110:106]
-  wire  _T_34 = ic_byp_hit_f & _T_33; // @[ifu_mem_ctl.scala 110:80]
-  wire  _T_35 = _T_34 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 110:140]
-  wire  _T_36 = io_dec_mem_ctrl_dec_tlu_force_halt | _T_35; // @[ifu_mem_ctl.scala 110:64]
-  wire  _T_38 = ~last_data_recieved_ff; // @[ifu_mem_ctl.scala 111:30]
-  wire  _T_39 = ic_byp_hit_f & _T_38; // @[ifu_mem_ctl.scala 111:27]
-  wire  _T_40 = _T_39 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 111:53]
-  wire  _T_42 = ~ic_byp_hit_f; // @[ifu_mem_ctl.scala 112:16]
-  wire  _T_44 = _T_42 & _T_319; // @[ifu_mem_ctl.scala 112:30]
-  wire  _T_46 = _T_44 & _T_32; // @[ifu_mem_ctl.scala 112:52]
-  wire  _T_47 = _T_46 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 112:85]
-  wire  _T_51 = _T_32 & _T_17; // @[ifu_mem_ctl.scala 113:49]
+  wire  _T_40 = ic_byp_hit_f & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 111:53]
   wire  _T_54 = ic_byp_hit_f & _T_319; // @[ifu_mem_ctl.scala 114:33]
-  wire  _T_56 = ~_T_32; // @[ifu_mem_ctl.scala 114:57]
-  wire  _T_57 = _T_54 & _T_56; // @[ifu_mem_ctl.scala 114:55]
   wire  ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[ifu_mem_ctl.scala 102:52]
   wire  _T_58 = ~ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 114:91]
-  wire  _T_59 = _T_57 & _T_58; // @[ifu_mem_ctl.scala 114:89]
+  wire  _T_59 = _T_54 & _T_58; // @[ifu_mem_ctl.scala 114:89]
   wire  _T_61 = _T_59 & _T_17; // @[ifu_mem_ctl.scala 114:113]
-  wire  _T_64 = bus_ifu_wr_en_ff & _T_319; // @[ifu_mem_ctl.scala 115:39]
-  wire  _T_67 = _T_64 & _T_56; // @[ifu_mem_ctl.scala 115:61]
-  wire  _T_69 = _T_67 & _T_58; // @[ifu_mem_ctl.scala 115:95]
-  wire  _T_71 = _T_69 & _T_17; // @[ifu_mem_ctl.scala 115:119]
-  wire  _T_79 = _T_46 & _T_17; // @[ifu_mem_ctl.scala 116:100]
   wire  _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 117:44]
-  wire  _T_84 = _T_81 & _T_56; // @[ifu_mem_ctl.scala 117:68]
-  wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 117:22]
-  wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[ifu_mem_ctl.scala 116:20]
-  wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[ifu_mem_ctl.scala 115:20]
-  wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[ifu_mem_ctl.scala 114:18]
-  wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[ifu_mem_ctl.scala 113:16]
-  wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[ifu_mem_ctl.scala 112:14]
-  wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[ifu_mem_ctl.scala 111:12]
-  wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 110:27]
+  wire [2:0] _T_86 = _T_81 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 117:22]
+  wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_86; // @[ifu_mem_ctl.scala 114:18]
+  wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_89; // @[ifu_mem_ctl.scala 111:12]
+  wire [2:0] _T_93 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 110:27]
   wire  _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_2280 = byp_fetch_index[4:1] == 4'hf; // @[ifu_mem_ctl.scala 374:60]
   wire  _T_2281 = _T_2280 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 374:94]
   wire  stream_eol_f = _T_2281 & stream_hit_f; // @[ifu_mem_ctl.scala 374:112]
   wire  _T_108 = _T_81 | stream_eol_f; // @[ifu_mem_ctl.scala 125:72]
-  wire  _T_111 = _T_108 & _T_56; // @[ifu_mem_ctl.scala 125:87]
-  wire  _T_113 = _T_111 & _T_2623; // @[ifu_mem_ctl.scala 125:122]
+  wire  _T_113 = _T_108 & _T_2623; // @[ifu_mem_ctl.scala 125:122]
   wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 125:27]
   wire  _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
-  wire  _T_124 = io_exu_flush_final & _T_56; // @[ifu_mem_ctl.scala 129:48]
-  wire  _T_126 = _T_124 & _T_2623; // @[ifu_mem_ctl.scala 129:82]
+  wire  _T_126 = io_exu_flush_final & _T_2623; // @[ifu_mem_ctl.scala 129:82]
   wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 129:27]
   wire  _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_236 = io_ic_rd_hit == 2'h0; // @[ifu_mem_ctl.scala 190:28]
@@ -1277,22 +1173,19 @@ module ifu_mem_ctl(
   wire  _T_247 = ~sel_mb_addr_ff; // @[ifu_mem_ctl.scala 191:116]
   wire  _T_248 = _T_246 & _T_247; // @[ifu_mem_ctl.scala 191:114]
   wire  ic_miss_under_miss_f = _T_248 & _T_209; // @[ifu_mem_ctl.scala 191:132]
-  wire  _T_135 = ic_miss_under_miss_f & _T_56; // @[ifu_mem_ctl.scala 133:50]
-  wire  _T_137 = _T_135 & _T_2623; // @[ifu_mem_ctl.scala 133:84]
+  wire  _T_137 = ic_miss_under_miss_f & _T_2623; // @[ifu_mem_ctl.scala 133:84]
   wire  _T_256 = _T_230 & _T_239; // @[ifu_mem_ctl.scala 192:85]
   wire  _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 193:39]
   wire  _T_260 = _T_259 | uncacheable_miss_ff; // @[ifu_mem_ctl.scala 193:91]
   wire  ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[ifu_mem_ctl.scala 192:117]
-  wire  _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[ifu_mem_ctl.scala 134:35]
-  wire  _T_143 = _T_141 & _T_2623; // @[ifu_mem_ctl.scala 134:69]
+  wire  _T_143 = ic_ignore_2nd_miss_f & _T_2623; // @[ifu_mem_ctl.scala 134:69]
   wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[ifu_mem_ctl.scala 134:12]
   wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[ifu_mem_ctl.scala 133:27]
   wire  _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[ifu_mem_ctl.scala 139:12]
-  wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[ifu_mem_ctl.scala 138:75]
+  wire [2:0] _T_155 = io_exu_flush_final ? 3'h2 : 3'h1; // @[ifu_mem_ctl.scala 138:75]
   wire [2:0] _T_156 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_155; // @[ifu_mem_ctl.scala 138:27]
   wire  _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[ifu_mem_ctl.scala 143:75]
+  wire [2:0] _T_164 = io_exu_flush_final ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 143:75]
   wire [2:0] _T_165 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_164; // @[ifu_mem_ctl.scala 143:27]
   wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67]
@@ -1302,43 +1195,31 @@ module ifu_mem_ctl(
   wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67]
   wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58]
-  wire  _T_20 = miss_nxtstate == 3'h5; // @[ifu_mem_ctl.scala 100:73]
-  wire  _T_21 = _T_19 | _T_20; // @[ifu_mem_ctl.scala 100:57]
-  wire  _T_22 = _T_18 & _T_21; // @[ifu_mem_ctl.scala 100:26]
   wire  _T_30 = ic_act_miss_f & _T_2623; // @[ifu_mem_ctl.scala 107:38]
   wire  _T_94 = io_dec_mem_ctrl_dec_tlu_force_halt | io_exu_flush_final; // @[ifu_mem_ctl.scala 118:59]
   wire  _T_95 = _T_94 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 118:80]
   wire  _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 118:95]
-  wire  _T_98 = _T_96 | _T_32; // @[ifu_mem_ctl.scala 118:118]
-  wire  _T_100 = bus_ifu_wr_en_ff & _T_17; // @[ifu_mem_ctl.scala 118:171]
-  wire  _T_101 = _T_98 | _T_100; // @[ifu_mem_ctl.scala 118:151]
   wire  _T_103 = io_exu_flush_final | flush_final_f; // @[ifu_mem_ctl.scala 122:43]
   wire  _T_104 = _T_103 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 122:59]
   wire  _T_105 = _T_104 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 122:74]
-  wire  _T_119 = _T_108 | _T_32; // @[ifu_mem_ctl.scala 126:84]
-  wire  _T_120 = _T_119 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:118]
-  wire  _T_130 = io_exu_flush_final | _T_32; // @[ifu_mem_ctl.scala 130:43]
-  wire  _T_131 = _T_130 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 130:76]
-  wire  _T_148 = _T_32 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 135:55]
-  wire  _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 135:78]
+  wire  _T_120 = _T_108 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:118]
+  wire  _T_131 = io_exu_flush_final | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 130:76]
+  wire  _T_149 = ic_miss_under_miss_f | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 135:78]
   wire  _T_150 = _T_149 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 135:101]
-  wire  _T_158 = _T_32 | io_exu_flush_final; // @[ifu_mem_ctl.scala 140:55]
-  wire  _T_159 = _T_158 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 140:76]
-  wire  _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67]
-  wire  _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67]
+  wire  _GEN_1 = _T_160 & _T_131; // @[Conditional.scala 39:67]
+  wire  _GEN_3 = _T_151 ? _T_131 : _GEN_1; // @[Conditional.scala 39:67]
   wire  _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67]
   wire  _GEN_7 = _T_121 ? _T_131 : _GEN_5; // @[Conditional.scala 39:67]
   wire  _GEN_9 = _T_106 ? _T_120 : _GEN_7; // @[Conditional.scala 39:67]
   wire  _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67]
-  wire  _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67]
+  wire  _GEN_13 = _T_31 ? _T_96 : _GEN_11; // @[Conditional.scala 39:67]
   wire  miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58]
   wire  _T_174 = ~flush_final_f; // @[ifu_mem_ctl.scala 160:95]
   wire  _T_175 = _T_2283 & _T_174; // @[ifu_mem_ctl.scala 160:93]
   wire  crit_wd_byp_ok_ff = _T_2284 | _T_175; // @[ifu_mem_ctl.scala 160:58]
-  wire  _T_178 = miss_pending & _T_56; // @[ifu_mem_ctl.scala 161:36]
   wire  _T_180 = _T_2283 & io_exu_flush_final; // @[ifu_mem_ctl.scala 161:106]
   wire  _T_181 = ~_T_180; // @[ifu_mem_ctl.scala 161:72]
-  wire  _T_182 = _T_178 & _T_181; // @[ifu_mem_ctl.scala 161:70]
+  wire  _T_182 = miss_pending & _T_181; // @[ifu_mem_ctl.scala 161:70]
   wire  _T_184 = _T_2283 & crit_byp_hit_f; // @[ifu_mem_ctl.scala 162:57]
   wire  _T_185 = ~_T_184; // @[ifu_mem_ctl.scala 162:23]
   wire  _T_186 = _T_182 & _T_185; // @[ifu_mem_ctl.scala 161:128]
@@ -1346,9 +1227,6 @@ module ifu_mem_ctl(
   wire  _T_188 = miss_nxtstate == 3'h4; // @[ifu_mem_ctl.scala 163:36]
   wire  _T_189 = miss_pending & _T_188; // @[ifu_mem_ctl.scala 163:19]
   wire  sel_hold_imb = _T_187 | _T_189; // @[ifu_mem_ctl.scala 162:93]
-  wire  _T_191 = _T_19 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 165:57]
-  wire  sel_hold_imb_scnd = _T_191 & _T_174; // @[ifu_mem_ctl.scala 165:81]
-  reg  way_status_mb_scnd_ff; // @[ifu_mem_ctl.scala 173:64]
   reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 670:14]
   wire  _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 666:80]
   reg  way_status_out_0; // @[Reg.scala 27:20]
@@ -1863,13 +1741,6 @@ module ifu_mem_ctl(
   wire  way_status = _T_5052 | _T_4926; // @[Mux.scala 27:72]
   wire  _T_195 = ~reset_all_tags; // @[ifu_mem_ctl.scala 168:96]
   wire [1:0] _T_197 = _T_195 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[ifu_mem_ctl.scala 168:113]
-  reg [1:0] tagv_mb_scnd_ff; // @[ifu_mem_ctl.scala 174:58]
-  reg  uncacheable_miss_scnd_ff; // @[ifu_mem_ctl.scala 170:67]
-  reg [30:0] imb_scnd_ff; // @[ifu_mem_ctl.scala 172:54]
-  wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 515:46]
-  wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[ifu_mem_ctl.scala 177:45]
   wire  _T_212 = _T_231 | _T_239; // @[ifu_mem_ctl.scala 182:59]
   wire  _T_214 = _T_212 | _T_2268; // @[ifu_mem_ctl.scala 182:91]
   wire  ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[ifu_mem_ctl.scala 182:41]
@@ -1880,21 +1751,6 @@ module ifu_mem_ctl(
   wire  _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[ifu_mem_ctl.scala 195:31]
   wire  _T_263 = _T_262 | ic_iccm_hit_f; // @[ifu_mem_ctl.scala 195:46]
   wire  _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 195:94]
-  wire  _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 196:84]
-  wire  uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[ifu_mem_ctl.scala 196:32]
-  wire  _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 199:79]
-  wire  _T_275 = _T_274 & scnd_miss_req; // @[ifu_mem_ctl.scala 199:135]
-  reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 513:51]
-  wire  _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 559:48]
-  wire  _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 559:52]
-  wire  bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 559:73]
-  reg  ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 276:61]
-  wire  ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 275:55]
-  wire  _T_276 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 199:153]
-  wire  scnd_miss_index_match = _T_275 & _T_276; // @[ifu_mem_ctl.scala 199:151]
-  wire  _T_277 = ~scnd_miss_index_match; // @[ifu_mem_ctl.scala 202:47]
-  wire  _T_278 = scnd_miss_req & _T_277; // @[ifu_mem_ctl.scala 202:45]
-  wire  _T_280 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 203:26]
   reg  way_status_mb_ff; // @[ifu_mem_ctl.scala 223:59]
   wire  _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 721:33]
   reg [1:0] tagv_mb_ff; // @[ifu_mem_ctl.scala 224:53]
@@ -1902,21 +1758,15 @@ module ifu_mem_ctl(
   wire  _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:67]
   wire  _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:86]
   wire  replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 721:84]
-  wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire  _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:50]
   wire  _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:66]
   wire  _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:85]
   wire  _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:100]
   wire  replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 722:83]
-  wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58]
-  wire [1:0] _T_289 = _T_287 & _T_288; // @[ifu_mem_ctl.scala 207:110]
-  wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[ifu_mem_ctl.scala 207:62]
   wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[ifu_mem_ctl.scala 208:56]
-  wire  _T_297 = ~scnd_miss_req_q; // @[ifu_mem_ctl.scala 211:36]
-  wire  _T_298 = miss_pending & _T_297; // @[ifu_mem_ctl.scala 211:34]
   reg  reset_ic_ff; // @[ifu_mem_ctl.scala 212:48]
   wire  _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 211:72]
-  wire  reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 211:53]
+  wire  reset_ic_in = miss_pending & _T_299; // @[ifu_mem_ctl.scala 211:53]
   reg  fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 213:62]
   reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 222:48]
   wire  _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 221:57]
@@ -1929,298 +1779,49 @@ module ifu_mem_ctl(
   wire  _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106]
   reg  ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68]
   reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 541:55]
-  wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58]
   wire  _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55]
-  wire  _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82]
-  wire  _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55]
-  wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2289}; // @[Cat.scala 29:58]
-  wire  _T_2290 = other_tag == 3'h0; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2314 = _T_2290 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72]
-  wire  _T_2293 = other_tag == 3'h1; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2315 = _T_2293 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72]
-  wire  _T_2322 = _T_2314 | _T_2315; // @[Mux.scala 27:72]
-  wire  _T_2296 = other_tag == 3'h2; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2316 = _T_2296 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72]
-  wire  _T_2323 = _T_2322 | _T_2316; // @[Mux.scala 27:72]
-  wire  _T_2299 = other_tag == 3'h3; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2317 = _T_2299 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72]
-  wire  _T_2324 = _T_2323 | _T_2317; // @[Mux.scala 27:72]
-  wire  _T_2302 = other_tag == 3'h4; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2318 = _T_2302 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72]
-  wire  _T_2325 = _T_2324 | _T_2318; // @[Mux.scala 27:72]
-  wire  _T_2305 = other_tag == 3'h5; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2319 = _T_2305 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72]
-  wire  _T_2326 = _T_2325 | _T_2319; // @[Mux.scala 27:72]
-  wire  _T_2308 = other_tag == 3'h6; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2320 = _T_2308 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72]
-  wire  _T_2327 = _T_2326 | _T_2320; // @[Mux.scala 27:72]
-  wire  _T_2311 = other_tag == 3'h7; // @[ifu_mem_ctl.scala 379:81]
-  wire  _T_2321 = _T_2311 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72]
-  wire  second_half_available = _T_2327 | _T_2321; // @[Mux.scala 27:72]
-  wire  write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 380:46]
-  wire  _T_332 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 238:35]
-  wire  _T_334 = _T_332 & _T_17; // @[ifu_mem_ctl.scala 238:55]
   reg  ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 556:61]
   wire  _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 557:53]
   wire  reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 557:84]
-  wire  sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 238:79]
-  wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58]
-  wire  _T_339 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 240:37]
-  wire [30:0] _T_340 = sel_mb_addr ? _T_338 : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_338 = {imb_ff[30:5],3'h0,imb_ff[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_339 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 240:37]
+  wire [30:0] _T_340 = reset_tag_valid_for_miss ? _T_338 : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72]
-  wire  _T_346 = _T_334 & last_beat; // @[ifu_mem_ctl.scala 242:85]
-  wire  _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 554:84]
-  wire  _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 554:82]
-  wire  bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 554:108]
-  wire  _T_347 = _T_346 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 242:97]
-  wire  sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 242:119]
-  wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31]
-  reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 514:48]
-  wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 276:13]
-  wire  _T_571 = ^_T_570; // @[lib.scala 276:20]
-  wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 276:30]
-  wire [7:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[lib.scala 276:30]
-  wire [14:0] _T_585 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_577}; // @[lib.scala 276:30]
-  wire [7:0] _T_592 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[lib.scala 276:30]
-  wire [30:0] _T_601 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_585}; // @[lib.scala 276:30]
-  wire  _T_602 = ^_T_601; // @[lib.scala 276:37]
-  wire [6:0] _T_608 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[lib.scala 276:47]
-  wire [14:0] _T_616 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_608}; // @[lib.scala 276:47]
-  wire [30:0] _T_632 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_616}; // @[lib.scala 276:47]
-  wire  _T_633 = ^_T_632; // @[lib.scala 276:54]
-  wire [6:0] _T_639 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[lib.scala 276:64]
-  wire [14:0] _T_647 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_639}; // @[lib.scala 276:64]
-  wire [30:0] _T_663 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_584,_T_647}; // @[lib.scala 276:64]
-  wire  _T_664 = ^_T_663; // @[lib.scala 276:71]
-  wire [7:0] _T_671 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[lib.scala 276:81]
-  wire [16:0] _T_680 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_671}; // @[lib.scala 276:81]
-  wire [8:0] _T_688 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:81]
-  wire [17:0] _T_697 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_688}; // @[lib.scala 276:81]
-  wire [34:0] _T_698 = {_T_697,_T_680}; // @[lib.scala 276:81]
-  wire  _T_699 = ^_T_698; // @[lib.scala 276:88]
-  wire [7:0] _T_706 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:98]
-  wire [16:0] _T_715 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_706}; // @[lib.scala 276:98]
-  wire [8:0] _T_723 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:98]
-  wire [17:0] _T_732 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_723}; // @[lib.scala 276:98]
-  wire [34:0] _T_733 = {_T_732,_T_715}; // @[lib.scala 276:98]
-  wire  _T_734 = ^_T_733; // @[lib.scala 276:105]
-  wire [7:0] _T_741 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:115]
-  wire [16:0] _T_750 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_741}; // @[lib.scala 276:115]
-  wire [8:0] _T_758 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[lib.scala 276:115]
-  wire [17:0] _T_767 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_758}; // @[lib.scala 276:115]
-  wire [34:0] _T_768 = {_T_767,_T_750}; // @[lib.scala 276:115]
-  wire  _T_769 = ^_T_768; // @[lib.scala 276:122]
-  wire [3:0] _T_2330 = {ifu_bus_rid_ff[2:1],_T_2289,1'h1}; // @[Cat.scala 29:58]
-  wire  _T_2331 = _T_2330 == 4'h0; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_0; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2378 = _T_2331 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_2334 = _T_2330 == 4'h1; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_1; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2379 = _T_2334 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2394 = _T_2378 | _T_2379; // @[Mux.scala 27:72]
-  wire  _T_2337 = _T_2330 == 4'h2; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_2; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2380 = _T_2337 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2395 = _T_2394 | _T_2380; // @[Mux.scala 27:72]
-  wire  _T_2340 = _T_2330 == 4'h3; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_3; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2381 = _T_2340 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2396 = _T_2395 | _T_2381; // @[Mux.scala 27:72]
-  wire  _T_2343 = _T_2330 == 4'h4; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_4; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2382 = _T_2343 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2397 = _T_2396 | _T_2382; // @[Mux.scala 27:72]
-  wire  _T_2346 = _T_2330 == 4'h5; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_5; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2383 = _T_2346 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2398 = _T_2397 | _T_2383; // @[Mux.scala 27:72]
-  wire  _T_2349 = _T_2330 == 4'h6; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_6; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2384 = _T_2349 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2399 = _T_2398 | _T_2384; // @[Mux.scala 27:72]
-  wire  _T_2352 = _T_2330 == 4'h7; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_7; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2385 = _T_2352 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2400 = _T_2399 | _T_2385; // @[Mux.scala 27:72]
-  wire  _T_2355 = _T_2330 == 4'h8; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_8; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2386 = _T_2355 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2401 = _T_2400 | _T_2386; // @[Mux.scala 27:72]
-  wire  _T_2358 = _T_2330 == 4'h9; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_9; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2387 = _T_2358 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2402 = _T_2401 | _T_2387; // @[Mux.scala 27:72]
-  wire  _T_2361 = _T_2330 == 4'ha; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_10; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2388 = _T_2361 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2403 = _T_2402 | _T_2388; // @[Mux.scala 27:72]
-  wire  _T_2364 = _T_2330 == 4'hb; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_11; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2389 = _T_2364 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2404 = _T_2403 | _T_2389; // @[Mux.scala 27:72]
-  wire  _T_2367 = _T_2330 == 4'hc; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_12; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2390 = _T_2367 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2405 = _T_2404 | _T_2390; // @[Mux.scala 27:72]
-  wire  _T_2370 = _T_2330 == 4'hd; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_13; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2391 = _T_2370 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2406 = _T_2405 | _T_2391; // @[Mux.scala 27:72]
-  wire  _T_2373 = _T_2330 == 4'he; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_14; // @[ifu_mem_ctl.scala 316:65]
-  wire [31:0] _T_2392 = _T_2373 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2407 = _T_2406 | _T_2392; // @[Mux.scala 27:72]
-  wire  _T_2376 = _T_2330 == 4'hf; // @[ifu_mem_ctl.scala 381:89]
-  reg [31:0] ic_miss_buff_data_15; // @[ifu_mem_ctl.scala 317:67]
-  wire [31:0] _T_2393 = _T_2376 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2408 = _T_2407 | _T_2393; // @[Mux.scala 27:72]
-  wire [3:0] _T_2410 = {ifu_bus_rid_ff[2:1],_T_2289,1'h0}; // @[Cat.scala 29:58]
-  wire  _T_2411 = _T_2410 == 4'h0; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2458 = _T_2411 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_2414 = _T_2410 == 4'h1; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2459 = _T_2414 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2474 = _T_2458 | _T_2459; // @[Mux.scala 27:72]
-  wire  _T_2417 = _T_2410 == 4'h2; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2460 = _T_2417 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2475 = _T_2474 | _T_2460; // @[Mux.scala 27:72]
-  wire  _T_2420 = _T_2410 == 4'h3; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2461 = _T_2420 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2476 = _T_2475 | _T_2461; // @[Mux.scala 27:72]
-  wire  _T_2423 = _T_2410 == 4'h4; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2462 = _T_2423 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2477 = _T_2476 | _T_2462; // @[Mux.scala 27:72]
-  wire  _T_2426 = _T_2410 == 4'h5; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2463 = _T_2426 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2478 = _T_2477 | _T_2463; // @[Mux.scala 27:72]
-  wire  _T_2429 = _T_2410 == 4'h6; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2464 = _T_2429 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2479 = _T_2478 | _T_2464; // @[Mux.scala 27:72]
-  wire  _T_2432 = _T_2410 == 4'h7; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2465 = _T_2432 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2480 = _T_2479 | _T_2465; // @[Mux.scala 27:72]
-  wire  _T_2435 = _T_2410 == 4'h8; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2466 = _T_2435 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2481 = _T_2480 | _T_2466; // @[Mux.scala 27:72]
-  wire  _T_2438 = _T_2410 == 4'h9; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2467 = _T_2438 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2482 = _T_2481 | _T_2467; // @[Mux.scala 27:72]
-  wire  _T_2441 = _T_2410 == 4'ha; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2468 = _T_2441 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2483 = _T_2482 | _T_2468; // @[Mux.scala 27:72]
-  wire  _T_2444 = _T_2410 == 4'hb; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2469 = _T_2444 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2484 = _T_2483 | _T_2469; // @[Mux.scala 27:72]
-  wire  _T_2447 = _T_2410 == 4'hc; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2470 = _T_2447 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2485 = _T_2484 | _T_2470; // @[Mux.scala 27:72]
-  wire  _T_2450 = _T_2410 == 4'hd; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2471 = _T_2450 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2486 = _T_2485 | _T_2471; // @[Mux.scala 27:72]
-  wire  _T_2453 = _T_2410 == 4'he; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2472 = _T_2453 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2487 = _T_2486 | _T_2472; // @[Mux.scala 27:72]
-  wire  _T_2456 = _T_2410 == 4'hf; // @[ifu_mem_ctl.scala 382:66]
-  wire [31:0] _T_2473 = _T_2456 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2488 = _T_2487 | _T_2473; // @[Mux.scala 27:72]
-  wire [63:0] ic_miss_buff_half = {_T_2408,_T_2488}; // @[Cat.scala 29:58]
-  wire [6:0] _T_992 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[lib.scala 276:13]
-  wire  _T_993 = ^_T_992; // @[lib.scala 276:20]
-  wire [6:0] _T_999 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[lib.scala 276:30]
-  wire [7:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[lib.scala 276:30]
-  wire [14:0] _T_1007 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_999}; // @[lib.scala 276:30]
-  wire [7:0] _T_1014 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[lib.scala 276:30]
-  wire [30:0] _T_1023 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1007}; // @[lib.scala 276:30]
-  wire  _T_1024 = ^_T_1023; // @[lib.scala 276:37]
-  wire [6:0] _T_1030 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[lib.scala 276:47]
-  wire [14:0] _T_1038 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1030}; // @[lib.scala 276:47]
-  wire [30:0] _T_1054 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1038}; // @[lib.scala 276:47]
-  wire  _T_1055 = ^_T_1054; // @[lib.scala 276:54]
-  wire [6:0] _T_1061 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[lib.scala 276:64]
-  wire [14:0] _T_1069 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1061}; // @[lib.scala 276:64]
-  wire [30:0] _T_1085 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1006,_T_1069}; // @[lib.scala 276:64]
-  wire  _T_1086 = ^_T_1085; // @[lib.scala 276:71]
-  wire [7:0] _T_1093 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[lib.scala 276:81]
-  wire [16:0] _T_1102 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1093}; // @[lib.scala 276:81]
-  wire [8:0] _T_1110 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:81]
-  wire [17:0] _T_1119 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1110}; // @[lib.scala 276:81]
-  wire [34:0] _T_1120 = {_T_1119,_T_1102}; // @[lib.scala 276:81]
-  wire  _T_1121 = ^_T_1120; // @[lib.scala 276:88]
-  wire [7:0] _T_1128 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[lib.scala 276:98]
-  wire [16:0] _T_1137 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1128}; // @[lib.scala 276:98]
-  wire [8:0] _T_1145 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:98]
-  wire [17:0] _T_1154 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1145}; // @[lib.scala 276:98]
-  wire [34:0] _T_1155 = {_T_1154,_T_1137}; // @[lib.scala 276:98]
-  wire  _T_1156 = ^_T_1155; // @[lib.scala 276:105]
-  wire [7:0] _T_1163 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[lib.scala 276:115]
-  wire [16:0] _T_1172 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1163}; // @[lib.scala 276:115]
-  wire [8:0] _T_1180 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[lib.scala 276:115]
-  wire [17:0] _T_1189 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1180}; // @[lib.scala 276:115]
-  wire [34:0] _T_1190 = {_T_1189,_T_1172}; // @[lib.scala 276:115]
-  wire  _T_1191 = ^_T_1190; // @[lib.scala 276:122]
-  wire [70:0] _T_1236 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff}; // @[Cat.scala 29:58]
-  wire [70:0] _T_1235 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488}; // @[Cat.scala 29:58]
-  wire [141:0] _T_1237 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff,_T_1235}; // @[Cat.scala 29:58]
-  wire [141:0] _T_1240 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488,_T_1236}; // @[Cat.scala 29:58]
-  wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1237 : _T_1240; // @[ifu_mem_ctl.scala 267:28]
+  wire [30:0] ifu_status_wr_addr = reset_tag_valid_for_miss ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31]
   wire  _T_1199 = |io_ic_eccerr; // @[ifu_mem_ctl.scala 256:73]
   wire  _T_1200 = _T_1199 & ic_act_hit_f; // @[ifu_mem_ctl.scala 256:100]
   wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 328:28]
   wire  _T_1404 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 330:114]
-  wire  bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 552:35]
-  wire  _T_1289 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_0 = bus_ifu_wr_en & _T_1289; // @[ifu_mem_ctl.scala 312:73]
   wire  _T_1330 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 319:118]
-  wire  _T_1331 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1331; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_0 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1427 = _T_1404 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72]
   wire  _T_1407 = bypass_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1290 = io_ifu_axi_r_bits_id == 3'h1; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_1 = bus_ifu_wr_en & _T_1290; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1334 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1334; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_1 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1428 = _T_1407 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72]
   wire  _T_1435 = _T_1427 | _T_1428; // @[Mux.scala 27:72]
   wire  _T_1410 = bypass_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1291 = io_ifu_axi_r_bits_id == 3'h2; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_2 = bus_ifu_wr_en & _T_1291; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1337 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1337; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_2 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1429 = _T_1410 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72]
   wire  _T_1436 = _T_1435 | _T_1429; // @[Mux.scala 27:72]
   wire  _T_1413 = bypass_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1292 = io_ifu_axi_r_bits_id == 3'h3; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_3 = bus_ifu_wr_en & _T_1292; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1340 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1340; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_3 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1430 = _T_1413 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72]
   wire  _T_1437 = _T_1436 | _T_1430; // @[Mux.scala 27:72]
   wire  _T_1416 = bypass_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1293 = io_ifu_axi_r_bits_id == 3'h4; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_4 = bus_ifu_wr_en & _T_1293; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1343 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1343; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_4 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1431 = _T_1416 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72]
   wire  _T_1438 = _T_1437 | _T_1431; // @[Mux.scala 27:72]
   wire  _T_1419 = bypass_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1294 = io_ifu_axi_r_bits_id == 3'h5; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_5 = bus_ifu_wr_en & _T_1294; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1346 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1346; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_5 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1432 = _T_1419 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72]
   wire  _T_1439 = _T_1438 | _T_1432; // @[Mux.scala 27:72]
   wire  _T_1422 = bypass_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1295 = io_ifu_axi_r_bits_id == 3'h6; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_6 = bus_ifu_wr_en & _T_1295; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1349 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1349; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_6 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1433 = _T_1422 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72]
   wire  _T_1440 = _T_1439 | _T_1433; // @[Mux.scala 27:72]
   wire  _T_1425 = bypass_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 330:114]
-  wire  _T_1296 = io_ifu_axi_r_bits_id == 3'h7; // @[ifu_mem_ctl.scala 312:91]
-  wire  write_fill_data_7 = bus_ifu_wr_en & _T_1296; // @[ifu_mem_ctl.scala 312:73]
-  wire  _T_1352 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
-  wire  ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1352; // @[ifu_mem_ctl.scala 319:88]
+  wire  ic_miss_buff_data_valid_in_7 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 319:116]
   wire  _T_1434 = _T_1425 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72]
   wire  bypass_valid_value_check = _T_1440 | _T_1434; // @[Mux.scala 27:72]
   wire  _T_1443 = ~bypass_index[1]; // @[ifu_mem_ctl.scala 331:58]
@@ -3090,239 +2691,7 @@ module ifu_mem_ctl(
   wire [63:0] ic_final_data = _T_1263 & io_ic_rd_data; // @[ifu_mem_ctl.scala 288:92]
   wire [63:0] _T_1265 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
   wire [63:0] _T_1266 = _T_1265 & io_iccm_rd_data; // @[ifu_mem_ctl.scala 292:69]
-  wire [63:0] _T_1268 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58]
-  wire  _T_1662 = byp_fetch_index_inc_0 == 4'h0; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1710 = _T_1662 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire  _T_1665 = byp_fetch_index_inc_0 == 4'h1; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1711 = _T_1665 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1726 = _T_1710 | _T_1711; // @[Mux.scala 27:72]
-  wire  _T_1668 = byp_fetch_index_inc_0 == 4'h2; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1712 = _T_1668 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1727 = _T_1726 | _T_1712; // @[Mux.scala 27:72]
-  wire  _T_1671 = byp_fetch_index_inc_0 == 4'h3; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1713 = _T_1671 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1728 = _T_1727 | _T_1713; // @[Mux.scala 27:72]
-  wire  _T_1674 = byp_fetch_index_inc_0 == 4'h4; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1714 = _T_1674 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1729 = _T_1728 | _T_1714; // @[Mux.scala 27:72]
-  wire  _T_1677 = byp_fetch_index_inc_0 == 4'h5; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1715 = _T_1677 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1730 = _T_1729 | _T_1715; // @[Mux.scala 27:72]
-  wire  _T_1680 = byp_fetch_index_inc_0 == 4'h6; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1716 = _T_1680 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1731 = _T_1730 | _T_1716; // @[Mux.scala 27:72]
-  wire  _T_1683 = byp_fetch_index_inc_0 == 4'h7; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1717 = _T_1683 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1732 = _T_1731 | _T_1717; // @[Mux.scala 27:72]
-  wire  _T_1686 = byp_fetch_index_inc_0 == 4'h8; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1718 = _T_1686 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1733 = _T_1732 | _T_1718; // @[Mux.scala 27:72]
-  wire  _T_1689 = byp_fetch_index_inc_0 == 4'h9; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1719 = _T_1689 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1734 = _T_1733 | _T_1719; // @[Mux.scala 27:72]
-  wire  _T_1692 = byp_fetch_index_inc_0 == 4'ha; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1720 = _T_1692 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1735 = _T_1734 | _T_1720; // @[Mux.scala 27:72]
-  wire  _T_1695 = byp_fetch_index_inc_0 == 4'hb; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1721 = _T_1695 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1736 = _T_1735 | _T_1721; // @[Mux.scala 27:72]
-  wire  _T_1698 = byp_fetch_index_inc_0 == 4'hc; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1722 = _T_1698 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1737 = _T_1736 | _T_1722; // @[Mux.scala 27:72]
-  wire  _T_1701 = byp_fetch_index_inc_0 == 4'hd; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1723 = _T_1701 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1738 = _T_1737 | _T_1723; // @[Mux.scala 27:72]
-  wire  _T_1704 = byp_fetch_index_inc_0 == 4'he; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1724 = _T_1704 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1739 = _T_1738 | _T_1724; // @[Mux.scala 27:72]
-  wire  _T_1707 = byp_fetch_index_inc_0 == 4'hf; // @[ifu_mem_ctl.scala 358:73]
-  wire [15:0] _T_1725 = _T_1707 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1740 = _T_1739 | _T_1725; // @[Mux.scala 27:72]
-  wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58]
-  wire  _T_1742 = byp_fetch_index_1 == 4'h0; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1790 = _T_1742 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_1745 = byp_fetch_index_1 == 4'h1; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1791 = _T_1745 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1806 = _T_1790 | _T_1791; // @[Mux.scala 27:72]
-  wire  _T_1748 = byp_fetch_index_1 == 4'h2; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1792 = _T_1748 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1807 = _T_1806 | _T_1792; // @[Mux.scala 27:72]
-  wire  _T_1751 = byp_fetch_index_1 == 4'h3; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1793 = _T_1751 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1808 = _T_1807 | _T_1793; // @[Mux.scala 27:72]
-  wire  _T_1754 = byp_fetch_index_1 == 4'h4; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1794 = _T_1754 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1809 = _T_1808 | _T_1794; // @[Mux.scala 27:72]
-  wire  _T_1757 = byp_fetch_index_1 == 4'h5; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1795 = _T_1757 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1810 = _T_1809 | _T_1795; // @[Mux.scala 27:72]
-  wire  _T_1760 = byp_fetch_index_1 == 4'h6; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1796 = _T_1760 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1811 = _T_1810 | _T_1796; // @[Mux.scala 27:72]
-  wire  _T_1763 = byp_fetch_index_1 == 4'h7; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1797 = _T_1763 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1812 = _T_1811 | _T_1797; // @[Mux.scala 27:72]
-  wire  _T_1766 = byp_fetch_index_1 == 4'h8; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1798 = _T_1766 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1813 = _T_1812 | _T_1798; // @[Mux.scala 27:72]
-  wire  _T_1769 = byp_fetch_index_1 == 4'h9; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1799 = _T_1769 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1814 = _T_1813 | _T_1799; // @[Mux.scala 27:72]
-  wire  _T_1772 = byp_fetch_index_1 == 4'ha; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1800 = _T_1772 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1815 = _T_1814 | _T_1800; // @[Mux.scala 27:72]
-  wire  _T_1775 = byp_fetch_index_1 == 4'hb; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1801 = _T_1775 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1816 = _T_1815 | _T_1801; // @[Mux.scala 27:72]
-  wire  _T_1778 = byp_fetch_index_1 == 4'hc; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1802 = _T_1778 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1817 = _T_1816 | _T_1802; // @[Mux.scala 27:72]
-  wire  _T_1781 = byp_fetch_index_1 == 4'hd; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1803 = _T_1781 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1818 = _T_1817 | _T_1803; // @[Mux.scala 27:72]
-  wire  _T_1784 = byp_fetch_index_1 == 4'he; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1804 = _T_1784 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1819 = _T_1818 | _T_1804; // @[Mux.scala 27:72]
-  wire  _T_1787 = byp_fetch_index_1 == 4'hf; // @[ifu_mem_ctl.scala 358:179]
-  wire [31:0] _T_1805 = _T_1787 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1820 = _T_1819 | _T_1805; // @[Mux.scala 27:72]
-  wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58]
-  wire  _T_1822 = byp_fetch_index_0 == 4'h0; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1870 = _T_1822 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_1825 = byp_fetch_index_0 == 4'h1; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1871 = _T_1825 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1886 = _T_1870 | _T_1871; // @[Mux.scala 27:72]
-  wire  _T_1828 = byp_fetch_index_0 == 4'h2; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1872 = _T_1828 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1887 = _T_1886 | _T_1872; // @[Mux.scala 27:72]
-  wire  _T_1831 = byp_fetch_index_0 == 4'h3; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1873 = _T_1831 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1888 = _T_1887 | _T_1873; // @[Mux.scala 27:72]
-  wire  _T_1834 = byp_fetch_index_0 == 4'h4; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1874 = _T_1834 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1889 = _T_1888 | _T_1874; // @[Mux.scala 27:72]
-  wire  _T_1837 = byp_fetch_index_0 == 4'h5; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1875 = _T_1837 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1890 = _T_1889 | _T_1875; // @[Mux.scala 27:72]
-  wire  _T_1840 = byp_fetch_index_0 == 4'h6; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1876 = _T_1840 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1891 = _T_1890 | _T_1876; // @[Mux.scala 27:72]
-  wire  _T_1843 = byp_fetch_index_0 == 4'h7; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1877 = _T_1843 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1892 = _T_1891 | _T_1877; // @[Mux.scala 27:72]
-  wire  _T_1846 = byp_fetch_index_0 == 4'h8; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1878 = _T_1846 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1893 = _T_1892 | _T_1878; // @[Mux.scala 27:72]
-  wire  _T_1849 = byp_fetch_index_0 == 4'h9; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1879 = _T_1849 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1894 = _T_1893 | _T_1879; // @[Mux.scala 27:72]
-  wire  _T_1852 = byp_fetch_index_0 == 4'ha; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1880 = _T_1852 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1895 = _T_1894 | _T_1880; // @[Mux.scala 27:72]
-  wire  _T_1855 = byp_fetch_index_0 == 4'hb; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1881 = _T_1855 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1896 = _T_1895 | _T_1881; // @[Mux.scala 27:72]
-  wire  _T_1858 = byp_fetch_index_0 == 4'hc; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1882 = _T_1858 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1897 = _T_1896 | _T_1882; // @[Mux.scala 27:72]
-  wire  _T_1861 = byp_fetch_index_0 == 4'hd; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1883 = _T_1861 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1898 = _T_1897 | _T_1883; // @[Mux.scala 27:72]
-  wire  _T_1864 = byp_fetch_index_0 == 4'he; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1884 = _T_1864 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1899 = _T_1898 | _T_1884; // @[Mux.scala 27:72]
-  wire  _T_1867 = byp_fetch_index_0 == 4'hf; // @[ifu_mem_ctl.scala 358:285]
-  wire [31:0] _T_1885 = _T_1867 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1900 = _T_1899 | _T_1885; // @[Mux.scala 27:72]
-  wire [79:0] _T_1903 = {_T_1740,_T_1820,_T_1900}; // @[Cat.scala 29:58]
-  wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58]
-  wire  _T_1904 = byp_fetch_index_inc_1 == 4'h0; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1952 = _T_1904 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire  _T_1907 = byp_fetch_index_inc_1 == 4'h1; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1953 = _T_1907 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1968 = _T_1952 | _T_1953; // @[Mux.scala 27:72]
-  wire  _T_1910 = byp_fetch_index_inc_1 == 4'h2; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1954 = _T_1910 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1969 = _T_1968 | _T_1954; // @[Mux.scala 27:72]
-  wire  _T_1913 = byp_fetch_index_inc_1 == 4'h3; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1955 = _T_1913 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1970 = _T_1969 | _T_1955; // @[Mux.scala 27:72]
-  wire  _T_1916 = byp_fetch_index_inc_1 == 4'h4; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1956 = _T_1916 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1971 = _T_1970 | _T_1956; // @[Mux.scala 27:72]
-  wire  _T_1919 = byp_fetch_index_inc_1 == 4'h5; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1957 = _T_1919 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1972 = _T_1971 | _T_1957; // @[Mux.scala 27:72]
-  wire  _T_1922 = byp_fetch_index_inc_1 == 4'h6; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1958 = _T_1922 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1973 = _T_1972 | _T_1958; // @[Mux.scala 27:72]
-  wire  _T_1925 = byp_fetch_index_inc_1 == 4'h7; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1959 = _T_1925 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1974 = _T_1973 | _T_1959; // @[Mux.scala 27:72]
-  wire  _T_1928 = byp_fetch_index_inc_1 == 4'h8; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1960 = _T_1928 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1975 = _T_1974 | _T_1960; // @[Mux.scala 27:72]
-  wire  _T_1931 = byp_fetch_index_inc_1 == 4'h9; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1961 = _T_1931 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1976 = _T_1975 | _T_1961; // @[Mux.scala 27:72]
-  wire  _T_1934 = byp_fetch_index_inc_1 == 4'ha; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1962 = _T_1934 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1977 = _T_1976 | _T_1962; // @[Mux.scala 27:72]
-  wire  _T_1937 = byp_fetch_index_inc_1 == 4'hb; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1963 = _T_1937 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1978 = _T_1977 | _T_1963; // @[Mux.scala 27:72]
-  wire  _T_1940 = byp_fetch_index_inc_1 == 4'hc; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1964 = _T_1940 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1979 = _T_1978 | _T_1964; // @[Mux.scala 27:72]
-  wire  _T_1943 = byp_fetch_index_inc_1 == 4'hd; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1965 = _T_1943 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1980 = _T_1979 | _T_1965; // @[Mux.scala 27:72]
-  wire  _T_1946 = byp_fetch_index_inc_1 == 4'he; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1966 = _T_1946 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1981 = _T_1980 | _T_1966; // @[Mux.scala 27:72]
-  wire  _T_1949 = byp_fetch_index_inc_1 == 4'hf; // @[ifu_mem_ctl.scala 359:73]
-  wire [15:0] _T_1967 = _T_1949 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72]
-  wire [15:0] _T_1982 = _T_1981 | _T_1967; // @[Mux.scala 27:72]
-  wire [31:0] _T_2032 = _T_1662 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2033 = _T_1665 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2048 = _T_2032 | _T_2033; // @[Mux.scala 27:72]
-  wire [31:0] _T_2034 = _T_1668 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2049 = _T_2048 | _T_2034; // @[Mux.scala 27:72]
-  wire [31:0] _T_2035 = _T_1671 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2050 = _T_2049 | _T_2035; // @[Mux.scala 27:72]
-  wire [31:0] _T_2036 = _T_1674 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2051 = _T_2050 | _T_2036; // @[Mux.scala 27:72]
-  wire [31:0] _T_2037 = _T_1677 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2052 = _T_2051 | _T_2037; // @[Mux.scala 27:72]
-  wire [31:0] _T_2038 = _T_1680 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2053 = _T_2052 | _T_2038; // @[Mux.scala 27:72]
-  wire [31:0] _T_2039 = _T_1683 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2054 = _T_2053 | _T_2039; // @[Mux.scala 27:72]
-  wire [31:0] _T_2040 = _T_1686 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2055 = _T_2054 | _T_2040; // @[Mux.scala 27:72]
-  wire [31:0] _T_2041 = _T_1689 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2056 = _T_2055 | _T_2041; // @[Mux.scala 27:72]
-  wire [31:0] _T_2042 = _T_1692 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2057 = _T_2056 | _T_2042; // @[Mux.scala 27:72]
-  wire [31:0] _T_2043 = _T_1695 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2058 = _T_2057 | _T_2043; // @[Mux.scala 27:72]
-  wire [31:0] _T_2044 = _T_1698 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72]
-  wire [31:0] _T_2045 = _T_1701 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72]
-  wire [31:0] _T_2046 = _T_1704 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72]
-  wire [31:0] _T_2047 = _T_1707 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72]
-  wire [79:0] _T_2145 = {_T_1982,_T_2062,_T_1820}; // @[Cat.scala 29:58]
-  wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1903 : _T_2145; // @[ifu_mem_ctl.scala 357:37]
-  wire [79:0] _T_2150 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
-  wire [79:0] ic_byp_data_only_new = _T_1614 ? ic_byp_data_only_pre_new : _T_2150; // @[ifu_mem_ctl.scala 361:30]
-  wire [79:0] _GEN_437 = {{16'd0}, _T_1268}; // @[ifu_mem_ctl.scala 292:114]
-  wire [79:0] _T_1269 = _GEN_437 & ic_byp_data_only_new; // @[ifu_mem_ctl.scala 292:114]
-  wire [79:0] _GEN_438 = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88]
-  wire [79:0] ic_premux_data_temp = _GEN_438 | _T_1269; // @[ifu_mem_ctl.scala 292:88]
+  wire [79:0] ic_premux_data_temp = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88]
   wire  fetch_req_f_qual = io_ic_hit_f & _T_319; // @[ifu_mem_ctl.scala 299:38]
   reg  ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 784:66]
   wire [1:0] _T_1277 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 304:10]
@@ -3334,25 +2703,14 @@ module ifu_mem_ctl(
   wire  _T_1285 = err_stop_state != 2'h2; // @[ifu_mem_ctl.scala 305:131]
   wire  _T_1286 = _T_1284 & _T_1285; // @[ifu_mem_ctl.scala 305:114]
   wire [6:0] _T_1358 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58]
-  wire  _T_1364 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 558:47]
-  wire  _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 558:50]
-  wire  bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 558:68]
-  wire  ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1364; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1368 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1368; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1372 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1372; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1376 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1376; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1380 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1380; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1384 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1384; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1388 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1388; // @[ifu_mem_ctl.scala 323:72]
-  wire  _T_1392 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
-  wire  ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1392; // @[ifu_mem_ctl.scala 323:72]
+  wire  ic_miss_buff_data_error_in_0 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_1 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_2 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_3 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_4 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_5 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_6 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
+  wire  ic_miss_buff_data_error_in_7 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 324:32]
   wire [6:0] _T_1398 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58]
   reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20]
   wire  _T_2500 = 3'h0 == perr_state; // @[Conditional.scala 37:30]
@@ -3401,46 +2759,9 @@ module ifu_mem_ctl(
   wire  _T_2591 = ic_act_miss_f | bus_cmd_req_hold; // @[ifu_mem_ctl.scala 471:45]
   reg  ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 472:55]
   wire  _T_2592 = _T_2591 | ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:64]
-  wire  _T_2594 = _T_2592 & _T_2623; // @[ifu_mem_ctl.scala 471:85]
-  reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20]
-  wire  _T_2596 = bus_cmd_beat_count == 3'h7; // @[ifu_mem_ctl.scala 471:146]
-  wire  _T_2597 = _T_2596 & ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:177]
-  wire  _T_2598 = _T_2597 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 471:197]
-  wire  _T_2599 = _T_2598 & miss_pending; // @[ifu_mem_ctl.scala 471:217]
-  wire  _T_2600 = ~_T_2599; // @[ifu_mem_ctl.scala 471:125]
-  wire  ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 523:45]
-  wire  _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 527:35]
-  wire  _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 527:53]
-  wire  bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 527:68]
-  wire  _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61]
-  wire  _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59]
-  wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58]
   wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  reg  ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 510:57]
   reg  ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 512:53]
-  wire  ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 524:51]
-  wire  _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 535:73]
-  wire  _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 535:71]
-  wire  _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 535:114]
-  wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 540:45]
-  wire  _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 543:48]
-  wire  _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 543:68]
-  wire  bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 543:83]
-  wire  bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 545:57]
-  wire  _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 546:31]
-  wire  _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 546:71]
-  wire  _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 546:87]
-  wire  _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 546:55]
-  wire  bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 546:53]
-  wire  _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 547:46]
-  wire  bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 547:62]
-  wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 549:46]
-  wire [2:0] _T_2665 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_2666 = bus_inc_cmd_beat_cnt ? _T_2663 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_2667 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_2669 = _T_2665 | _T_2666; // @[Mux.scala 27:72]
-  wire [2:0] bus_new_cmd_beat_count = _T_2669 | _T_2667; // @[Mux.scala 27:72]
   reg  ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 561:62]
   wire  _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 566:50]
   wire  _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 566:47]
@@ -3799,28 +3120,12 @@ module ifu_mem_ctl(
   wire  _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 634:28]
   wire  _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 634:50]
   wire  _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 634:81]
-  wire [1:0] _T_3974 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire  _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 728:74]
-  wire  bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 728:98]
-  wire  _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 728:74]
-  wire  bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 728:98]
-  wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58]
-  wire  _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 637:106]
-  wire  _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 637:104]
-  wire  _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 637:77]
-  wire  _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 637:172]
-  wire  _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 637:170]
-  wire  _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 637:44]
   wire  _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 640:64]
   wire  _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 640:50]
-  wire  _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 640:48]
-  wire  _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 640:81]
-  wire  ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 640:79]
+  wire  ic_valid = _T_3993 & _T_339; // @[ifu_mem_ctl.scala 640:79]
   wire  _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 641:82]
   reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 644:14]
   wire  _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 647:74]
-  wire  _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 727:45]
-  wire  way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 727:58]
   reg  way_status_wr_en_ff; // @[ifu_mem_ctl.scala 649:14]
   wire  way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 723:41]
   reg  way_status_new_ff; // @[ifu_mem_ctl.scala 655:14]
@@ -3840,17 +3145,9 @@ module ifu_mem_ctl(
   wire  _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136]
   wire  _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 661:128]
   wire  _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136]
-  wire  _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 730:84]
-  wire  _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 730:108]
-  wire  bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123]
   wire  wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84]
-  wire  _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 732:73]
-  wire  _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 730:84]
-  wire  _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 730:108]
-  wire  bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123]
   wire  wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84]
-  wire  _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 732:73]
-  wire [1:0] ifu_tag_wren = {_T_9786,_T_9785}; // @[Cat.scala 29:58]
+  wire [1:0] ifu_tag_wren = {wren_reset_miss_1,wren_reset_miss_0}; // @[Cat.scala 29:58]
   wire [1:0] _T_9821 = _T_4000 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 766:90]
   reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 676:14]
@@ -5060,10 +4357,7 @@ module ifu_mem_ctl(
   reg  _T_9799; // @[ifu_mem_ctl.scala 753:70]
   reg  _T_9800; // @[ifu_mem_ctl.scala 754:69]
   reg  _T_9801; // @[ifu_mem_ctl.scala 755:72]
-  wire  _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 756:93]
-  wire  _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 756:91]
   reg  _T_9805; // @[ifu_mem_ctl.scala 756:71]
-  reg  _T_9806; // @[ifu_mem_ctl.scala 757:71]
   wire  _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 764:84]
   wire  _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 764:150]
   wire  _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 765:63]
@@ -5653,17 +4947,13 @@ module ifu_mem_ctl(
   assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 754:34]
   assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 755:37]
   assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 756:36]
-  assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 757:36]
   assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1200 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 256:38]
   assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 613:46]
   assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1212; // @[ifu_mem_ctl.scala 263:40]
   assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 771:46]
   assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39]
   assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23]
-  assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25]
   assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27]
-  assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29]
-  assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22]
   assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 600:19]
   assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27]
   assign io_iccm_correction_state = _T_2526 ? 1'h0 : _GEN_42; // @[ifu_mem_ctl.scala 430:28 ifu_mem_ctl.scala 442:32 ifu_mem_ctl.scala 449:32 ifu_mem_ctl.scala 456:32]
@@ -5673,10 +4963,7 @@ module ifu_mem_ctl(
   assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 577:19]
   assign io_ic_rw_addr = _T_340 | _T_341; // @[ifu_mem_ctl.scala 244:17]
   assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 748:19]
-  assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 636:15]
   assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 627:15]
-  assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 253:17]
-  assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 253:17]
   assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 254:23]
   assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 760:20]
   assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 762:21]
@@ -5685,9 +4972,8 @@ module ifu_mem_ctl(
   assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 764:19]
   assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 295:21]
   assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[ifu_mem_ctl.scala 296:25]
-  assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[ifu_mem_ctl.scala 234:22]
+  assign io_ifu_ic_mb_empty = _T_325 | _T_231; // @[ifu_mem_ctl.scala 234:22]
   assign io_ic_dma_active = _T_11 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 97:20]
-  assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 637:21]
   assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 596:25]
   assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 594:22]
   assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 598:21]
@@ -5708,202 +4994,202 @@ module ifu_mem_ctl(
   assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[lib.scala 345:16]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[lib.scala 345:16]
+  assign rvclkhdr_2_io_en = _T_1 | io_exu_flush_final; // @[lib.scala 345:16]
   assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_3_io_en = _T_309 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[lib.scala 345:16]
   assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_4_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_5_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_6_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_7_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_8_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_9_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_12_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_12_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_13_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_13_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_14_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_14_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_15_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_15_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_16_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_16_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_17_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_17_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_18_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_18_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_19_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_19_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_20_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_20_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_21_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_21_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_22_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_22_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_23_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_23_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_24_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_24_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_25_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_25_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_26_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_26_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_27_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_27_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_28_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_28_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_29_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_29_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_30_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_30_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_31_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_31_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_32_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_32_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_33_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_33_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_34_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_35_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_35_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_36_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_36_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_37_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_37_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_38_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_38_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_39_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_39_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_40_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_40_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_41_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_41_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_42_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_42_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_43_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_43_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_44_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_44_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_45_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_45_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_46_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_46_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_47_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_47_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_48_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_48_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_49_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_49_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_50_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_50_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_51_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_51_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_52_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_52_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_53_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_53_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_54_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_54_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_55_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_55_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_56_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_56_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_57_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_57_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_58_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_58_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_59_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_59_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_60_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16]
+  assign rvclkhdr_60_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_61_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16]
+  assign rvclkhdr_61_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_62_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16]
+  assign rvclkhdr_62_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_63_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16]
+  assign rvclkhdr_63_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_64_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16]
+  assign rvclkhdr_64_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_65_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16]
+  assign rvclkhdr_65_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_66_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16]
+  assign rvclkhdr_66_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_67_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16]
+  assign rvclkhdr_67_io_en = 1'h0; // @[lib.scala 345:16]
   assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_68_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[lib.scala 345:16]
@@ -6025,945 +5311,881 @@ initial begin
   _RAND_2 = {1{`RANDOM}};
   miss_state = _RAND_2[2:0];
   _RAND_3 = {1{`RANDOM}};
-  scnd_miss_req_q = _RAND_3[0:0];
+  ifu_fetch_addr_int_f = _RAND_3[30:0];
   _RAND_4 = {1{`RANDOM}};
-  ifu_fetch_addr_int_f = _RAND_4[30:0];
+  ifc_iccm_access_f = _RAND_4[0:0];
   _RAND_5 = {1{`RANDOM}};
-  ifc_iccm_access_f = _RAND_5[0:0];
+  iccm_dma_rvalid_in = _RAND_5[0:0];
   _RAND_6 = {1{`RANDOM}};
-  iccm_dma_rvalid_in = _RAND_6[0:0];
+  dma_iccm_req_f = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  dma_iccm_req_f = _RAND_7[0:0];
+  perr_state = _RAND_7[2:0];
   _RAND_8 = {1{`RANDOM}};
-  perr_state = _RAND_8[2:0];
+  err_stop_state = _RAND_8[1:0];
   _RAND_9 = {1{`RANDOM}};
-  err_stop_state = _RAND_9[1:0];
+  reset_all_tags = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  reset_all_tags = _RAND_10[0:0];
+  ifc_region_acc_fault_final_f = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  ifc_region_acc_fault_final_f = _RAND_11[0:0];
+  uncacheable_miss_ff = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  ifu_bus_rvalid_unq_ff = _RAND_12[0:0];
+  ic_miss_buff_data_valid = _RAND_12[7:0];
   _RAND_13 = {1{`RANDOM}};
-  bus_ifu_bus_clk_en_ff = _RAND_13[0:0];
+  imb_ff = _RAND_13[30:0];
   _RAND_14 = {1{`RANDOM}};
-  uncacheable_miss_ff = _RAND_14[0:0];
+  sel_mb_addr_ff = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  bus_data_beat_count = _RAND_15[2:0];
+  ifu_ic_rw_int_addr_ff = _RAND_15[6:0];
   _RAND_16 = {1{`RANDOM}};
-  ic_miss_buff_data_valid = _RAND_16[7:0];
+  way_status_out_0 = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  imb_ff = _RAND_17[30:0];
+  way_status_out_1 = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  last_data_recieved_ff = _RAND_18[0:0];
+  way_status_out_2 = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  sel_mb_addr_ff = _RAND_19[0:0];
+  way_status_out_3 = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  way_status_mb_scnd_ff = _RAND_20[0:0];
+  way_status_out_4 = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  ifu_ic_rw_int_addr_ff = _RAND_21[6:0];
+  way_status_out_5 = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
-  way_status_out_0 = _RAND_22[0:0];
+  way_status_out_6 = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  way_status_out_1 = _RAND_23[0:0];
+  way_status_out_7 = _RAND_23[0:0];
   _RAND_24 = {1{`RANDOM}};
-  way_status_out_2 = _RAND_24[0:0];
+  way_status_out_8 = _RAND_24[0:0];
   _RAND_25 = {1{`RANDOM}};
-  way_status_out_3 = _RAND_25[0:0];
+  way_status_out_9 = _RAND_25[0:0];
   _RAND_26 = {1{`RANDOM}};
-  way_status_out_4 = _RAND_26[0:0];
+  way_status_out_10 = _RAND_26[0:0];
   _RAND_27 = {1{`RANDOM}};
-  way_status_out_5 = _RAND_27[0:0];
+  way_status_out_11 = _RAND_27[0:0];
   _RAND_28 = {1{`RANDOM}};
-  way_status_out_6 = _RAND_28[0:0];
+  way_status_out_12 = _RAND_28[0:0];
   _RAND_29 = {1{`RANDOM}};
-  way_status_out_7 = _RAND_29[0:0];
+  way_status_out_13 = _RAND_29[0:0];
   _RAND_30 = {1{`RANDOM}};
-  way_status_out_8 = _RAND_30[0:0];
+  way_status_out_14 = _RAND_30[0:0];
   _RAND_31 = {1{`RANDOM}};
-  way_status_out_9 = _RAND_31[0:0];
+  way_status_out_15 = _RAND_31[0:0];
   _RAND_32 = {1{`RANDOM}};
-  way_status_out_10 = _RAND_32[0:0];
+  way_status_out_16 = _RAND_32[0:0];
   _RAND_33 = {1{`RANDOM}};
-  way_status_out_11 = _RAND_33[0:0];
+  way_status_out_17 = _RAND_33[0:0];
   _RAND_34 = {1{`RANDOM}};
-  way_status_out_12 = _RAND_34[0:0];
+  way_status_out_18 = _RAND_34[0:0];
   _RAND_35 = {1{`RANDOM}};
-  way_status_out_13 = _RAND_35[0:0];
+  way_status_out_19 = _RAND_35[0:0];
   _RAND_36 = {1{`RANDOM}};
-  way_status_out_14 = _RAND_36[0:0];
+  way_status_out_20 = _RAND_36[0:0];
   _RAND_37 = {1{`RANDOM}};
-  way_status_out_15 = _RAND_37[0:0];
+  way_status_out_21 = _RAND_37[0:0];
   _RAND_38 = {1{`RANDOM}};
-  way_status_out_16 = _RAND_38[0:0];
+  way_status_out_22 = _RAND_38[0:0];
   _RAND_39 = {1{`RANDOM}};
-  way_status_out_17 = _RAND_39[0:0];
+  way_status_out_23 = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  way_status_out_18 = _RAND_40[0:0];
+  way_status_out_24 = _RAND_40[0:0];
   _RAND_41 = {1{`RANDOM}};
-  way_status_out_19 = _RAND_41[0:0];
+  way_status_out_25 = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  way_status_out_20 = _RAND_42[0:0];
+  way_status_out_26 = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  way_status_out_21 = _RAND_43[0:0];
+  way_status_out_27 = _RAND_43[0:0];
   _RAND_44 = {1{`RANDOM}};
-  way_status_out_22 = _RAND_44[0:0];
+  way_status_out_28 = _RAND_44[0:0];
   _RAND_45 = {1{`RANDOM}};
-  way_status_out_23 = _RAND_45[0:0];
+  way_status_out_29 = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  way_status_out_24 = _RAND_46[0:0];
+  way_status_out_30 = _RAND_46[0:0];
   _RAND_47 = {1{`RANDOM}};
-  way_status_out_25 = _RAND_47[0:0];
+  way_status_out_31 = _RAND_47[0:0];
   _RAND_48 = {1{`RANDOM}};
-  way_status_out_26 = _RAND_48[0:0];
+  way_status_out_32 = _RAND_48[0:0];
   _RAND_49 = {1{`RANDOM}};
-  way_status_out_27 = _RAND_49[0:0];
+  way_status_out_33 = _RAND_49[0:0];
   _RAND_50 = {1{`RANDOM}};
-  way_status_out_28 = _RAND_50[0:0];
+  way_status_out_34 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  way_status_out_29 = _RAND_51[0:0];
+  way_status_out_35 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  way_status_out_30 = _RAND_52[0:0];
+  way_status_out_36 = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  way_status_out_31 = _RAND_53[0:0];
+  way_status_out_37 = _RAND_53[0:0];
   _RAND_54 = {1{`RANDOM}};
-  way_status_out_32 = _RAND_54[0:0];
+  way_status_out_38 = _RAND_54[0:0];
   _RAND_55 = {1{`RANDOM}};
-  way_status_out_33 = _RAND_55[0:0];
+  way_status_out_39 = _RAND_55[0:0];
   _RAND_56 = {1{`RANDOM}};
-  way_status_out_34 = _RAND_56[0:0];
+  way_status_out_40 = _RAND_56[0:0];
   _RAND_57 = {1{`RANDOM}};
-  way_status_out_35 = _RAND_57[0:0];
+  way_status_out_41 = _RAND_57[0:0];
   _RAND_58 = {1{`RANDOM}};
-  way_status_out_36 = _RAND_58[0:0];
+  way_status_out_42 = _RAND_58[0:0];
   _RAND_59 = {1{`RANDOM}};
-  way_status_out_37 = _RAND_59[0:0];
+  way_status_out_43 = _RAND_59[0:0];
   _RAND_60 = {1{`RANDOM}};
-  way_status_out_38 = _RAND_60[0:0];
+  way_status_out_44 = _RAND_60[0:0];
   _RAND_61 = {1{`RANDOM}};
-  way_status_out_39 = _RAND_61[0:0];
+  way_status_out_45 = _RAND_61[0:0];
   _RAND_62 = {1{`RANDOM}};
-  way_status_out_40 = _RAND_62[0:0];
+  way_status_out_46 = _RAND_62[0:0];
   _RAND_63 = {1{`RANDOM}};
-  way_status_out_41 = _RAND_63[0:0];
+  way_status_out_47 = _RAND_63[0:0];
   _RAND_64 = {1{`RANDOM}};
-  way_status_out_42 = _RAND_64[0:0];
+  way_status_out_48 = _RAND_64[0:0];
   _RAND_65 = {1{`RANDOM}};
-  way_status_out_43 = _RAND_65[0:0];
+  way_status_out_49 = _RAND_65[0:0];
   _RAND_66 = {1{`RANDOM}};
-  way_status_out_44 = _RAND_66[0:0];
+  way_status_out_50 = _RAND_66[0:0];
   _RAND_67 = {1{`RANDOM}};
-  way_status_out_45 = _RAND_67[0:0];
+  way_status_out_51 = _RAND_67[0:0];
   _RAND_68 = {1{`RANDOM}};
-  way_status_out_46 = _RAND_68[0:0];
+  way_status_out_52 = _RAND_68[0:0];
   _RAND_69 = {1{`RANDOM}};
-  way_status_out_47 = _RAND_69[0:0];
+  way_status_out_53 = _RAND_69[0:0];
   _RAND_70 = {1{`RANDOM}};
-  way_status_out_48 = _RAND_70[0:0];
+  way_status_out_54 = _RAND_70[0:0];
   _RAND_71 = {1{`RANDOM}};
-  way_status_out_49 = _RAND_71[0:0];
+  way_status_out_55 = _RAND_71[0:0];
   _RAND_72 = {1{`RANDOM}};
-  way_status_out_50 = _RAND_72[0:0];
+  way_status_out_56 = _RAND_72[0:0];
   _RAND_73 = {1{`RANDOM}};
-  way_status_out_51 = _RAND_73[0:0];
+  way_status_out_57 = _RAND_73[0:0];
   _RAND_74 = {1{`RANDOM}};
-  way_status_out_52 = _RAND_74[0:0];
+  way_status_out_58 = _RAND_74[0:0];
   _RAND_75 = {1{`RANDOM}};
-  way_status_out_53 = _RAND_75[0:0];
+  way_status_out_59 = _RAND_75[0:0];
   _RAND_76 = {1{`RANDOM}};
-  way_status_out_54 = _RAND_76[0:0];
+  way_status_out_60 = _RAND_76[0:0];
   _RAND_77 = {1{`RANDOM}};
-  way_status_out_55 = _RAND_77[0:0];
+  way_status_out_61 = _RAND_77[0:0];
   _RAND_78 = {1{`RANDOM}};
-  way_status_out_56 = _RAND_78[0:0];
+  way_status_out_62 = _RAND_78[0:0];
   _RAND_79 = {1{`RANDOM}};
-  way_status_out_57 = _RAND_79[0:0];
+  way_status_out_63 = _RAND_79[0:0];
   _RAND_80 = {1{`RANDOM}};
-  way_status_out_58 = _RAND_80[0:0];
+  way_status_out_64 = _RAND_80[0:0];
   _RAND_81 = {1{`RANDOM}};
-  way_status_out_59 = _RAND_81[0:0];
+  way_status_out_65 = _RAND_81[0:0];
   _RAND_82 = {1{`RANDOM}};
-  way_status_out_60 = _RAND_82[0:0];
+  way_status_out_66 = _RAND_82[0:0];
   _RAND_83 = {1{`RANDOM}};
-  way_status_out_61 = _RAND_83[0:0];
+  way_status_out_67 = _RAND_83[0:0];
   _RAND_84 = {1{`RANDOM}};
-  way_status_out_62 = _RAND_84[0:0];
+  way_status_out_68 = _RAND_84[0:0];
   _RAND_85 = {1{`RANDOM}};
-  way_status_out_63 = _RAND_85[0:0];
+  way_status_out_69 = _RAND_85[0:0];
   _RAND_86 = {1{`RANDOM}};
-  way_status_out_64 = _RAND_86[0:0];
+  way_status_out_70 = _RAND_86[0:0];
   _RAND_87 = {1{`RANDOM}};
-  way_status_out_65 = _RAND_87[0:0];
+  way_status_out_71 = _RAND_87[0:0];
   _RAND_88 = {1{`RANDOM}};
-  way_status_out_66 = _RAND_88[0:0];
+  way_status_out_72 = _RAND_88[0:0];
   _RAND_89 = {1{`RANDOM}};
-  way_status_out_67 = _RAND_89[0:0];
+  way_status_out_73 = _RAND_89[0:0];
   _RAND_90 = {1{`RANDOM}};
-  way_status_out_68 = _RAND_90[0:0];
+  way_status_out_74 = _RAND_90[0:0];
   _RAND_91 = {1{`RANDOM}};
-  way_status_out_69 = _RAND_91[0:0];
+  way_status_out_75 = _RAND_91[0:0];
   _RAND_92 = {1{`RANDOM}};
-  way_status_out_70 = _RAND_92[0:0];
+  way_status_out_76 = _RAND_92[0:0];
   _RAND_93 = {1{`RANDOM}};
-  way_status_out_71 = _RAND_93[0:0];
+  way_status_out_77 = _RAND_93[0:0];
   _RAND_94 = {1{`RANDOM}};
-  way_status_out_72 = _RAND_94[0:0];
+  way_status_out_78 = _RAND_94[0:0];
   _RAND_95 = {1{`RANDOM}};
-  way_status_out_73 = _RAND_95[0:0];
+  way_status_out_79 = _RAND_95[0:0];
   _RAND_96 = {1{`RANDOM}};
-  way_status_out_74 = _RAND_96[0:0];
+  way_status_out_80 = _RAND_96[0:0];
   _RAND_97 = {1{`RANDOM}};
-  way_status_out_75 = _RAND_97[0:0];
+  way_status_out_81 = _RAND_97[0:0];
   _RAND_98 = {1{`RANDOM}};
-  way_status_out_76 = _RAND_98[0:0];
+  way_status_out_82 = _RAND_98[0:0];
   _RAND_99 = {1{`RANDOM}};
-  way_status_out_77 = _RAND_99[0:0];
+  way_status_out_83 = _RAND_99[0:0];
   _RAND_100 = {1{`RANDOM}};
-  way_status_out_78 = _RAND_100[0:0];
+  way_status_out_84 = _RAND_100[0:0];
   _RAND_101 = {1{`RANDOM}};
-  way_status_out_79 = _RAND_101[0:0];
+  way_status_out_85 = _RAND_101[0:0];
   _RAND_102 = {1{`RANDOM}};
-  way_status_out_80 = _RAND_102[0:0];
+  way_status_out_86 = _RAND_102[0:0];
   _RAND_103 = {1{`RANDOM}};
-  way_status_out_81 = _RAND_103[0:0];
+  way_status_out_87 = _RAND_103[0:0];
   _RAND_104 = {1{`RANDOM}};
-  way_status_out_82 = _RAND_104[0:0];
+  way_status_out_88 = _RAND_104[0:0];
   _RAND_105 = {1{`RANDOM}};
-  way_status_out_83 = _RAND_105[0:0];
+  way_status_out_89 = _RAND_105[0:0];
   _RAND_106 = {1{`RANDOM}};
-  way_status_out_84 = _RAND_106[0:0];
+  way_status_out_90 = _RAND_106[0:0];
   _RAND_107 = {1{`RANDOM}};
-  way_status_out_85 = _RAND_107[0:0];
+  way_status_out_91 = _RAND_107[0:0];
   _RAND_108 = {1{`RANDOM}};
-  way_status_out_86 = _RAND_108[0:0];
+  way_status_out_92 = _RAND_108[0:0];
   _RAND_109 = {1{`RANDOM}};
-  way_status_out_87 = _RAND_109[0:0];
+  way_status_out_93 = _RAND_109[0:0];
   _RAND_110 = {1{`RANDOM}};
-  way_status_out_88 = _RAND_110[0:0];
+  way_status_out_94 = _RAND_110[0:0];
   _RAND_111 = {1{`RANDOM}};
-  way_status_out_89 = _RAND_111[0:0];
+  way_status_out_95 = _RAND_111[0:0];
   _RAND_112 = {1{`RANDOM}};
-  way_status_out_90 = _RAND_112[0:0];
+  way_status_out_96 = _RAND_112[0:0];
   _RAND_113 = {1{`RANDOM}};
-  way_status_out_91 = _RAND_113[0:0];
+  way_status_out_97 = _RAND_113[0:0];
   _RAND_114 = {1{`RANDOM}};
-  way_status_out_92 = _RAND_114[0:0];
+  way_status_out_98 = _RAND_114[0:0];
   _RAND_115 = {1{`RANDOM}};
-  way_status_out_93 = _RAND_115[0:0];
+  way_status_out_99 = _RAND_115[0:0];
   _RAND_116 = {1{`RANDOM}};
-  way_status_out_94 = _RAND_116[0:0];
+  way_status_out_100 = _RAND_116[0:0];
   _RAND_117 = {1{`RANDOM}};
-  way_status_out_95 = _RAND_117[0:0];
+  way_status_out_101 = _RAND_117[0:0];
   _RAND_118 = {1{`RANDOM}};
-  way_status_out_96 = _RAND_118[0:0];
+  way_status_out_102 = _RAND_118[0:0];
   _RAND_119 = {1{`RANDOM}};
-  way_status_out_97 = _RAND_119[0:0];
+  way_status_out_103 = _RAND_119[0:0];
   _RAND_120 = {1{`RANDOM}};
-  way_status_out_98 = _RAND_120[0:0];
+  way_status_out_104 = _RAND_120[0:0];
   _RAND_121 = {1{`RANDOM}};
-  way_status_out_99 = _RAND_121[0:0];
+  way_status_out_105 = _RAND_121[0:0];
   _RAND_122 = {1{`RANDOM}};
-  way_status_out_100 = _RAND_122[0:0];
+  way_status_out_106 = _RAND_122[0:0];
   _RAND_123 = {1{`RANDOM}};
-  way_status_out_101 = _RAND_123[0:0];
+  way_status_out_107 = _RAND_123[0:0];
   _RAND_124 = {1{`RANDOM}};
-  way_status_out_102 = _RAND_124[0:0];
+  way_status_out_108 = _RAND_124[0:0];
   _RAND_125 = {1{`RANDOM}};
-  way_status_out_103 = _RAND_125[0:0];
+  way_status_out_109 = _RAND_125[0:0];
   _RAND_126 = {1{`RANDOM}};
-  way_status_out_104 = _RAND_126[0:0];
+  way_status_out_110 = _RAND_126[0:0];
   _RAND_127 = {1{`RANDOM}};
-  way_status_out_105 = _RAND_127[0:0];
+  way_status_out_111 = _RAND_127[0:0];
   _RAND_128 = {1{`RANDOM}};
-  way_status_out_106 = _RAND_128[0:0];
+  way_status_out_112 = _RAND_128[0:0];
   _RAND_129 = {1{`RANDOM}};
-  way_status_out_107 = _RAND_129[0:0];
+  way_status_out_113 = _RAND_129[0:0];
   _RAND_130 = {1{`RANDOM}};
-  way_status_out_108 = _RAND_130[0:0];
+  way_status_out_114 = _RAND_130[0:0];
   _RAND_131 = {1{`RANDOM}};
-  way_status_out_109 = _RAND_131[0:0];
+  way_status_out_115 = _RAND_131[0:0];
   _RAND_132 = {1{`RANDOM}};
-  way_status_out_110 = _RAND_132[0:0];
+  way_status_out_116 = _RAND_132[0:0];
   _RAND_133 = {1{`RANDOM}};
-  way_status_out_111 = _RAND_133[0:0];
+  way_status_out_117 = _RAND_133[0:0];
   _RAND_134 = {1{`RANDOM}};
-  way_status_out_112 = _RAND_134[0:0];
+  way_status_out_118 = _RAND_134[0:0];
   _RAND_135 = {1{`RANDOM}};
-  way_status_out_113 = _RAND_135[0:0];
+  way_status_out_119 = _RAND_135[0:0];
   _RAND_136 = {1{`RANDOM}};
-  way_status_out_114 = _RAND_136[0:0];
+  way_status_out_120 = _RAND_136[0:0];
   _RAND_137 = {1{`RANDOM}};
-  way_status_out_115 = _RAND_137[0:0];
+  way_status_out_121 = _RAND_137[0:0];
   _RAND_138 = {1{`RANDOM}};
-  way_status_out_116 = _RAND_138[0:0];
+  way_status_out_122 = _RAND_138[0:0];
   _RAND_139 = {1{`RANDOM}};
-  way_status_out_117 = _RAND_139[0:0];
+  way_status_out_123 = _RAND_139[0:0];
   _RAND_140 = {1{`RANDOM}};
-  way_status_out_118 = _RAND_140[0:0];
+  way_status_out_124 = _RAND_140[0:0];
   _RAND_141 = {1{`RANDOM}};
-  way_status_out_119 = _RAND_141[0:0];
+  way_status_out_125 = _RAND_141[0:0];
   _RAND_142 = {1{`RANDOM}};
-  way_status_out_120 = _RAND_142[0:0];
+  way_status_out_126 = _RAND_142[0:0];
   _RAND_143 = {1{`RANDOM}};
-  way_status_out_121 = _RAND_143[0:0];
+  way_status_out_127 = _RAND_143[0:0];
   _RAND_144 = {1{`RANDOM}};
-  way_status_out_122 = _RAND_144[0:0];
+  way_status_mb_ff = _RAND_144[0:0];
   _RAND_145 = {1{`RANDOM}};
-  way_status_out_123 = _RAND_145[0:0];
+  tagv_mb_ff = _RAND_145[1:0];
   _RAND_146 = {1{`RANDOM}};
-  way_status_out_124 = _RAND_146[0:0];
+  reset_ic_ff = _RAND_146[0:0];
   _RAND_147 = {1{`RANDOM}};
-  way_status_out_125 = _RAND_147[0:0];
+  fetch_uncacheable_ff = _RAND_147[0:0];
   _RAND_148 = {1{`RANDOM}};
-  way_status_out_126 = _RAND_148[0:0];
+  miss_addr = _RAND_148[25:0];
   _RAND_149 = {1{`RANDOM}};
-  way_status_out_127 = _RAND_149[0:0];
+  ifc_region_acc_fault_f = _RAND_149[0:0];
   _RAND_150 = {1{`RANDOM}};
-  tagv_mb_scnd_ff = _RAND_150[1:0];
+  bus_rd_addr_count = _RAND_150[2:0];
   _RAND_151 = {1{`RANDOM}};
-  uncacheable_miss_scnd_ff = _RAND_151[0:0];
+  ic_act_miss_f_delayed = _RAND_151[0:0];
   _RAND_152 = {1{`RANDOM}};
-  imb_scnd_ff = _RAND_152[30:0];
+  ic_crit_wd_rdy_new_ff = _RAND_152[0:0];
   _RAND_153 = {1{`RANDOM}};
-  ifu_bus_rid_ff = _RAND_153[2:0];
+  ic_miss_buff_data_error = _RAND_153[7:0];
   _RAND_154 = {1{`RANDOM}};
-  ifu_bus_rresp_ff = _RAND_154[1:0];
+  ic_debug_ict_array_sel_ff = _RAND_154[0:0];
   _RAND_155 = {1{`RANDOM}};
-  ifu_wr_data_comb_err_ff = _RAND_155[0:0];
+  ic_tag_valid_out_1_0 = _RAND_155[0:0];
   _RAND_156 = {1{`RANDOM}};
-  way_status_mb_ff = _RAND_156[0:0];
+  ic_tag_valid_out_1_1 = _RAND_156[0:0];
   _RAND_157 = {1{`RANDOM}};
-  tagv_mb_ff = _RAND_157[1:0];
+  ic_tag_valid_out_1_2 = _RAND_157[0:0];
   _RAND_158 = {1{`RANDOM}};
-  reset_ic_ff = _RAND_158[0:0];
+  ic_tag_valid_out_1_3 = _RAND_158[0:0];
   _RAND_159 = {1{`RANDOM}};
-  fetch_uncacheable_ff = _RAND_159[0:0];
+  ic_tag_valid_out_1_4 = _RAND_159[0:0];
   _RAND_160 = {1{`RANDOM}};
-  miss_addr = _RAND_160[25:0];
+  ic_tag_valid_out_1_5 = _RAND_160[0:0];
   _RAND_161 = {1{`RANDOM}};
-  ifc_region_acc_fault_f = _RAND_161[0:0];
+  ic_tag_valid_out_1_6 = _RAND_161[0:0];
   _RAND_162 = {1{`RANDOM}};
-  bus_rd_addr_count = _RAND_162[2:0];
+  ic_tag_valid_out_1_7 = _RAND_162[0:0];
   _RAND_163 = {1{`RANDOM}};
-  ic_act_miss_f_delayed = _RAND_163[0:0];
-  _RAND_164 = {2{`RANDOM}};
-  ifu_bus_rdata_ff = _RAND_164[63:0];
+  ic_tag_valid_out_1_8 = _RAND_163[0:0];
+  _RAND_164 = {1{`RANDOM}};
+  ic_tag_valid_out_1_9 = _RAND_164[0:0];
   _RAND_165 = {1{`RANDOM}};
-  ic_miss_buff_data_0 = _RAND_165[31:0];
+  ic_tag_valid_out_1_10 = _RAND_165[0:0];
   _RAND_166 = {1{`RANDOM}};
-  ic_miss_buff_data_1 = _RAND_166[31:0];
+  ic_tag_valid_out_1_11 = _RAND_166[0:0];
   _RAND_167 = {1{`RANDOM}};
-  ic_miss_buff_data_2 = _RAND_167[31:0];
+  ic_tag_valid_out_1_12 = _RAND_167[0:0];
   _RAND_168 = {1{`RANDOM}};
-  ic_miss_buff_data_3 = _RAND_168[31:0];
+  ic_tag_valid_out_1_13 = _RAND_168[0:0];
   _RAND_169 = {1{`RANDOM}};
-  ic_miss_buff_data_4 = _RAND_169[31:0];
+  ic_tag_valid_out_1_14 = _RAND_169[0:0];
   _RAND_170 = {1{`RANDOM}};
-  ic_miss_buff_data_5 = _RAND_170[31:0];
+  ic_tag_valid_out_1_15 = _RAND_170[0:0];
   _RAND_171 = {1{`RANDOM}};
-  ic_miss_buff_data_6 = _RAND_171[31:0];
+  ic_tag_valid_out_1_16 = _RAND_171[0:0];
   _RAND_172 = {1{`RANDOM}};
-  ic_miss_buff_data_7 = _RAND_172[31:0];
+  ic_tag_valid_out_1_17 = _RAND_172[0:0];
   _RAND_173 = {1{`RANDOM}};
-  ic_miss_buff_data_8 = _RAND_173[31:0];
+  ic_tag_valid_out_1_18 = _RAND_173[0:0];
   _RAND_174 = {1{`RANDOM}};
-  ic_miss_buff_data_9 = _RAND_174[31:0];
+  ic_tag_valid_out_1_19 = _RAND_174[0:0];
   _RAND_175 = {1{`RANDOM}};
-  ic_miss_buff_data_10 = _RAND_175[31:0];
+  ic_tag_valid_out_1_20 = _RAND_175[0:0];
   _RAND_176 = {1{`RANDOM}};
-  ic_miss_buff_data_11 = _RAND_176[31:0];
+  ic_tag_valid_out_1_21 = _RAND_176[0:0];
   _RAND_177 = {1{`RANDOM}};
-  ic_miss_buff_data_12 = _RAND_177[31:0];
+  ic_tag_valid_out_1_22 = _RAND_177[0:0];
   _RAND_178 = {1{`RANDOM}};
-  ic_miss_buff_data_13 = _RAND_178[31:0];
+  ic_tag_valid_out_1_23 = _RAND_178[0:0];
   _RAND_179 = {1{`RANDOM}};
-  ic_miss_buff_data_14 = _RAND_179[31:0];
+  ic_tag_valid_out_1_24 = _RAND_179[0:0];
   _RAND_180 = {1{`RANDOM}};
-  ic_miss_buff_data_15 = _RAND_180[31:0];
+  ic_tag_valid_out_1_25 = _RAND_180[0:0];
   _RAND_181 = {1{`RANDOM}};
-  ic_crit_wd_rdy_new_ff = _RAND_181[0:0];
+  ic_tag_valid_out_1_26 = _RAND_181[0:0];
   _RAND_182 = {1{`RANDOM}};
-  ic_miss_buff_data_error = _RAND_182[7:0];
+  ic_tag_valid_out_1_27 = _RAND_182[0:0];
   _RAND_183 = {1{`RANDOM}};
-  ic_debug_ict_array_sel_ff = _RAND_183[0:0];
+  ic_tag_valid_out_1_28 = _RAND_183[0:0];
   _RAND_184 = {1{`RANDOM}};
-  ic_tag_valid_out_1_0 = _RAND_184[0:0];
+  ic_tag_valid_out_1_29 = _RAND_184[0:0];
   _RAND_185 = {1{`RANDOM}};
-  ic_tag_valid_out_1_1 = _RAND_185[0:0];
+  ic_tag_valid_out_1_30 = _RAND_185[0:0];
   _RAND_186 = {1{`RANDOM}};
-  ic_tag_valid_out_1_2 = _RAND_186[0:0];
+  ic_tag_valid_out_1_31 = _RAND_186[0:0];
   _RAND_187 = {1{`RANDOM}};
-  ic_tag_valid_out_1_3 = _RAND_187[0:0];
+  ic_tag_valid_out_1_32 = _RAND_187[0:0];
   _RAND_188 = {1{`RANDOM}};
-  ic_tag_valid_out_1_4 = _RAND_188[0:0];
+  ic_tag_valid_out_1_33 = _RAND_188[0:0];
   _RAND_189 = {1{`RANDOM}};
-  ic_tag_valid_out_1_5 = _RAND_189[0:0];
+  ic_tag_valid_out_1_34 = _RAND_189[0:0];
   _RAND_190 = {1{`RANDOM}};
-  ic_tag_valid_out_1_6 = _RAND_190[0:0];
+  ic_tag_valid_out_1_35 = _RAND_190[0:0];
   _RAND_191 = {1{`RANDOM}};
-  ic_tag_valid_out_1_7 = _RAND_191[0:0];
+  ic_tag_valid_out_1_36 = _RAND_191[0:0];
   _RAND_192 = {1{`RANDOM}};
-  ic_tag_valid_out_1_8 = _RAND_192[0:0];
+  ic_tag_valid_out_1_37 = _RAND_192[0:0];
   _RAND_193 = {1{`RANDOM}};
-  ic_tag_valid_out_1_9 = _RAND_193[0:0];
+  ic_tag_valid_out_1_38 = _RAND_193[0:0];
   _RAND_194 = {1{`RANDOM}};
-  ic_tag_valid_out_1_10 = _RAND_194[0:0];
+  ic_tag_valid_out_1_39 = _RAND_194[0:0];
   _RAND_195 = {1{`RANDOM}};
-  ic_tag_valid_out_1_11 = _RAND_195[0:0];
+  ic_tag_valid_out_1_40 = _RAND_195[0:0];
   _RAND_196 = {1{`RANDOM}};
-  ic_tag_valid_out_1_12 = _RAND_196[0:0];
+  ic_tag_valid_out_1_41 = _RAND_196[0:0];
   _RAND_197 = {1{`RANDOM}};
-  ic_tag_valid_out_1_13 = _RAND_197[0:0];
+  ic_tag_valid_out_1_42 = _RAND_197[0:0];
   _RAND_198 = {1{`RANDOM}};
-  ic_tag_valid_out_1_14 = _RAND_198[0:0];
+  ic_tag_valid_out_1_43 = _RAND_198[0:0];
   _RAND_199 = {1{`RANDOM}};
-  ic_tag_valid_out_1_15 = _RAND_199[0:0];
+  ic_tag_valid_out_1_44 = _RAND_199[0:0];
   _RAND_200 = {1{`RANDOM}};
-  ic_tag_valid_out_1_16 = _RAND_200[0:0];
+  ic_tag_valid_out_1_45 = _RAND_200[0:0];
   _RAND_201 = {1{`RANDOM}};
-  ic_tag_valid_out_1_17 = _RAND_201[0:0];
+  ic_tag_valid_out_1_46 = _RAND_201[0:0];
   _RAND_202 = {1{`RANDOM}};
-  ic_tag_valid_out_1_18 = _RAND_202[0:0];
+  ic_tag_valid_out_1_47 = _RAND_202[0:0];
   _RAND_203 = {1{`RANDOM}};
-  ic_tag_valid_out_1_19 = _RAND_203[0:0];
+  ic_tag_valid_out_1_48 = _RAND_203[0:0];
   _RAND_204 = {1{`RANDOM}};
-  ic_tag_valid_out_1_20 = _RAND_204[0:0];
+  ic_tag_valid_out_1_49 = _RAND_204[0:0];
   _RAND_205 = {1{`RANDOM}};
-  ic_tag_valid_out_1_21 = _RAND_205[0:0];
+  ic_tag_valid_out_1_50 = _RAND_205[0:0];
   _RAND_206 = {1{`RANDOM}};
-  ic_tag_valid_out_1_22 = _RAND_206[0:0];
+  ic_tag_valid_out_1_51 = _RAND_206[0:0];
   _RAND_207 = {1{`RANDOM}};
-  ic_tag_valid_out_1_23 = _RAND_207[0:0];
+  ic_tag_valid_out_1_52 = _RAND_207[0:0];
   _RAND_208 = {1{`RANDOM}};
-  ic_tag_valid_out_1_24 = _RAND_208[0:0];
+  ic_tag_valid_out_1_53 = _RAND_208[0:0];
   _RAND_209 = {1{`RANDOM}};
-  ic_tag_valid_out_1_25 = _RAND_209[0:0];
+  ic_tag_valid_out_1_54 = _RAND_209[0:0];
   _RAND_210 = {1{`RANDOM}};
-  ic_tag_valid_out_1_26 = _RAND_210[0:0];
+  ic_tag_valid_out_1_55 = _RAND_210[0:0];
   _RAND_211 = {1{`RANDOM}};
-  ic_tag_valid_out_1_27 = _RAND_211[0:0];
+  ic_tag_valid_out_1_56 = _RAND_211[0:0];
   _RAND_212 = {1{`RANDOM}};
-  ic_tag_valid_out_1_28 = _RAND_212[0:0];
+  ic_tag_valid_out_1_57 = _RAND_212[0:0];
   _RAND_213 = {1{`RANDOM}};
-  ic_tag_valid_out_1_29 = _RAND_213[0:0];
+  ic_tag_valid_out_1_58 = _RAND_213[0:0];
   _RAND_214 = {1{`RANDOM}};
-  ic_tag_valid_out_1_30 = _RAND_214[0:0];
+  ic_tag_valid_out_1_59 = _RAND_214[0:0];
   _RAND_215 = {1{`RANDOM}};
-  ic_tag_valid_out_1_31 = _RAND_215[0:0];
+  ic_tag_valid_out_1_60 = _RAND_215[0:0];
   _RAND_216 = {1{`RANDOM}};
-  ic_tag_valid_out_1_32 = _RAND_216[0:0];
+  ic_tag_valid_out_1_61 = _RAND_216[0:0];
   _RAND_217 = {1{`RANDOM}};
-  ic_tag_valid_out_1_33 = _RAND_217[0:0];
+  ic_tag_valid_out_1_62 = _RAND_217[0:0];
   _RAND_218 = {1{`RANDOM}};
-  ic_tag_valid_out_1_34 = _RAND_218[0:0];
+  ic_tag_valid_out_1_63 = _RAND_218[0:0];
   _RAND_219 = {1{`RANDOM}};
-  ic_tag_valid_out_1_35 = _RAND_219[0:0];
+  ic_tag_valid_out_1_64 = _RAND_219[0:0];
   _RAND_220 = {1{`RANDOM}};
-  ic_tag_valid_out_1_36 = _RAND_220[0:0];
+  ic_tag_valid_out_1_65 = _RAND_220[0:0];
   _RAND_221 = {1{`RANDOM}};
-  ic_tag_valid_out_1_37 = _RAND_221[0:0];
+  ic_tag_valid_out_1_66 = _RAND_221[0:0];
   _RAND_222 = {1{`RANDOM}};
-  ic_tag_valid_out_1_38 = _RAND_222[0:0];
+  ic_tag_valid_out_1_67 = _RAND_222[0:0];
   _RAND_223 = {1{`RANDOM}};
-  ic_tag_valid_out_1_39 = _RAND_223[0:0];
+  ic_tag_valid_out_1_68 = _RAND_223[0:0];
   _RAND_224 = {1{`RANDOM}};
-  ic_tag_valid_out_1_40 = _RAND_224[0:0];
+  ic_tag_valid_out_1_69 = _RAND_224[0:0];
   _RAND_225 = {1{`RANDOM}};
-  ic_tag_valid_out_1_41 = _RAND_225[0:0];
+  ic_tag_valid_out_1_70 = _RAND_225[0:0];
   _RAND_226 = {1{`RANDOM}};
-  ic_tag_valid_out_1_42 = _RAND_226[0:0];
+  ic_tag_valid_out_1_71 = _RAND_226[0:0];
   _RAND_227 = {1{`RANDOM}};
-  ic_tag_valid_out_1_43 = _RAND_227[0:0];
+  ic_tag_valid_out_1_72 = _RAND_227[0:0];
   _RAND_228 = {1{`RANDOM}};
-  ic_tag_valid_out_1_44 = _RAND_228[0:0];
+  ic_tag_valid_out_1_73 = _RAND_228[0:0];
   _RAND_229 = {1{`RANDOM}};
-  ic_tag_valid_out_1_45 = _RAND_229[0:0];
+  ic_tag_valid_out_1_74 = _RAND_229[0:0];
   _RAND_230 = {1{`RANDOM}};
-  ic_tag_valid_out_1_46 = _RAND_230[0:0];
+  ic_tag_valid_out_1_75 = _RAND_230[0:0];
   _RAND_231 = {1{`RANDOM}};
-  ic_tag_valid_out_1_47 = _RAND_231[0:0];
+  ic_tag_valid_out_1_76 = _RAND_231[0:0];
   _RAND_232 = {1{`RANDOM}};
-  ic_tag_valid_out_1_48 = _RAND_232[0:0];
+  ic_tag_valid_out_1_77 = _RAND_232[0:0];
   _RAND_233 = {1{`RANDOM}};
-  ic_tag_valid_out_1_49 = _RAND_233[0:0];
+  ic_tag_valid_out_1_78 = _RAND_233[0:0];
   _RAND_234 = {1{`RANDOM}};
-  ic_tag_valid_out_1_50 = _RAND_234[0:0];
+  ic_tag_valid_out_1_79 = _RAND_234[0:0];
   _RAND_235 = {1{`RANDOM}};
-  ic_tag_valid_out_1_51 = _RAND_235[0:0];
+  ic_tag_valid_out_1_80 = _RAND_235[0:0];
   _RAND_236 = {1{`RANDOM}};
-  ic_tag_valid_out_1_52 = _RAND_236[0:0];
+  ic_tag_valid_out_1_81 = _RAND_236[0:0];
   _RAND_237 = {1{`RANDOM}};
-  ic_tag_valid_out_1_53 = _RAND_237[0:0];
+  ic_tag_valid_out_1_82 = _RAND_237[0:0];
   _RAND_238 = {1{`RANDOM}};
-  ic_tag_valid_out_1_54 = _RAND_238[0:0];
+  ic_tag_valid_out_1_83 = _RAND_238[0:0];
   _RAND_239 = {1{`RANDOM}};
-  ic_tag_valid_out_1_55 = _RAND_239[0:0];
+  ic_tag_valid_out_1_84 = _RAND_239[0:0];
   _RAND_240 = {1{`RANDOM}};
-  ic_tag_valid_out_1_56 = _RAND_240[0:0];
+  ic_tag_valid_out_1_85 = _RAND_240[0:0];
   _RAND_241 = {1{`RANDOM}};
-  ic_tag_valid_out_1_57 = _RAND_241[0:0];
+  ic_tag_valid_out_1_86 = _RAND_241[0:0];
   _RAND_242 = {1{`RANDOM}};
-  ic_tag_valid_out_1_58 = _RAND_242[0:0];
+  ic_tag_valid_out_1_87 = _RAND_242[0:0];
   _RAND_243 = {1{`RANDOM}};
-  ic_tag_valid_out_1_59 = _RAND_243[0:0];
+  ic_tag_valid_out_1_88 = _RAND_243[0:0];
   _RAND_244 = {1{`RANDOM}};
-  ic_tag_valid_out_1_60 = _RAND_244[0:0];
+  ic_tag_valid_out_1_89 = _RAND_244[0:0];
   _RAND_245 = {1{`RANDOM}};
-  ic_tag_valid_out_1_61 = _RAND_245[0:0];
+  ic_tag_valid_out_1_90 = _RAND_245[0:0];
   _RAND_246 = {1{`RANDOM}};
-  ic_tag_valid_out_1_62 = _RAND_246[0:0];
+  ic_tag_valid_out_1_91 = _RAND_246[0:0];
   _RAND_247 = {1{`RANDOM}};
-  ic_tag_valid_out_1_63 = _RAND_247[0:0];
+  ic_tag_valid_out_1_92 = _RAND_247[0:0];
   _RAND_248 = {1{`RANDOM}};
-  ic_tag_valid_out_1_64 = _RAND_248[0:0];
+  ic_tag_valid_out_1_93 = _RAND_248[0:0];
   _RAND_249 = {1{`RANDOM}};
-  ic_tag_valid_out_1_65 = _RAND_249[0:0];
+  ic_tag_valid_out_1_94 = _RAND_249[0:0];
   _RAND_250 = {1{`RANDOM}};
-  ic_tag_valid_out_1_66 = _RAND_250[0:0];
+  ic_tag_valid_out_1_95 = _RAND_250[0:0];
   _RAND_251 = {1{`RANDOM}};
-  ic_tag_valid_out_1_67 = _RAND_251[0:0];
+  ic_tag_valid_out_1_96 = _RAND_251[0:0];
   _RAND_252 = {1{`RANDOM}};
-  ic_tag_valid_out_1_68 = _RAND_252[0:0];
+  ic_tag_valid_out_1_97 = _RAND_252[0:0];
   _RAND_253 = {1{`RANDOM}};
-  ic_tag_valid_out_1_69 = _RAND_253[0:0];
+  ic_tag_valid_out_1_98 = _RAND_253[0:0];
   _RAND_254 = {1{`RANDOM}};
-  ic_tag_valid_out_1_70 = _RAND_254[0:0];
+  ic_tag_valid_out_1_99 = _RAND_254[0:0];
   _RAND_255 = {1{`RANDOM}};
-  ic_tag_valid_out_1_71 = _RAND_255[0:0];
+  ic_tag_valid_out_1_100 = _RAND_255[0:0];
   _RAND_256 = {1{`RANDOM}};
-  ic_tag_valid_out_1_72 = _RAND_256[0:0];
+  ic_tag_valid_out_1_101 = _RAND_256[0:0];
   _RAND_257 = {1{`RANDOM}};
-  ic_tag_valid_out_1_73 = _RAND_257[0:0];
+  ic_tag_valid_out_1_102 = _RAND_257[0:0];
   _RAND_258 = {1{`RANDOM}};
-  ic_tag_valid_out_1_74 = _RAND_258[0:0];
+  ic_tag_valid_out_1_103 = _RAND_258[0:0];
   _RAND_259 = {1{`RANDOM}};
-  ic_tag_valid_out_1_75 = _RAND_259[0:0];
+  ic_tag_valid_out_1_104 = _RAND_259[0:0];
   _RAND_260 = {1{`RANDOM}};
-  ic_tag_valid_out_1_76 = _RAND_260[0:0];
+  ic_tag_valid_out_1_105 = _RAND_260[0:0];
   _RAND_261 = {1{`RANDOM}};
-  ic_tag_valid_out_1_77 = _RAND_261[0:0];
+  ic_tag_valid_out_1_106 = _RAND_261[0:0];
   _RAND_262 = {1{`RANDOM}};
-  ic_tag_valid_out_1_78 = _RAND_262[0:0];
+  ic_tag_valid_out_1_107 = _RAND_262[0:0];
   _RAND_263 = {1{`RANDOM}};
-  ic_tag_valid_out_1_79 = _RAND_263[0:0];
+  ic_tag_valid_out_1_108 = _RAND_263[0:0];
   _RAND_264 = {1{`RANDOM}};
-  ic_tag_valid_out_1_80 = _RAND_264[0:0];
+  ic_tag_valid_out_1_109 = _RAND_264[0:0];
   _RAND_265 = {1{`RANDOM}};
-  ic_tag_valid_out_1_81 = _RAND_265[0:0];
+  ic_tag_valid_out_1_110 = _RAND_265[0:0];
   _RAND_266 = {1{`RANDOM}};
-  ic_tag_valid_out_1_82 = _RAND_266[0:0];
+  ic_tag_valid_out_1_111 = _RAND_266[0:0];
   _RAND_267 = {1{`RANDOM}};
-  ic_tag_valid_out_1_83 = _RAND_267[0:0];
+  ic_tag_valid_out_1_112 = _RAND_267[0:0];
   _RAND_268 = {1{`RANDOM}};
-  ic_tag_valid_out_1_84 = _RAND_268[0:0];
+  ic_tag_valid_out_1_113 = _RAND_268[0:0];
   _RAND_269 = {1{`RANDOM}};
-  ic_tag_valid_out_1_85 = _RAND_269[0:0];
+  ic_tag_valid_out_1_114 = _RAND_269[0:0];
   _RAND_270 = {1{`RANDOM}};
-  ic_tag_valid_out_1_86 = _RAND_270[0:0];
+  ic_tag_valid_out_1_115 = _RAND_270[0:0];
   _RAND_271 = {1{`RANDOM}};
-  ic_tag_valid_out_1_87 = _RAND_271[0:0];
+  ic_tag_valid_out_1_116 = _RAND_271[0:0];
   _RAND_272 = {1{`RANDOM}};
-  ic_tag_valid_out_1_88 = _RAND_272[0:0];
+  ic_tag_valid_out_1_117 = _RAND_272[0:0];
   _RAND_273 = {1{`RANDOM}};
-  ic_tag_valid_out_1_89 = _RAND_273[0:0];
+  ic_tag_valid_out_1_118 = _RAND_273[0:0];
   _RAND_274 = {1{`RANDOM}};
-  ic_tag_valid_out_1_90 = _RAND_274[0:0];
+  ic_tag_valid_out_1_119 = _RAND_274[0:0];
   _RAND_275 = {1{`RANDOM}};
-  ic_tag_valid_out_1_91 = _RAND_275[0:0];
+  ic_tag_valid_out_1_120 = _RAND_275[0:0];
   _RAND_276 = {1{`RANDOM}};
-  ic_tag_valid_out_1_92 = _RAND_276[0:0];
+  ic_tag_valid_out_1_121 = _RAND_276[0:0];
   _RAND_277 = {1{`RANDOM}};
-  ic_tag_valid_out_1_93 = _RAND_277[0:0];
+  ic_tag_valid_out_1_122 = _RAND_277[0:0];
   _RAND_278 = {1{`RANDOM}};
-  ic_tag_valid_out_1_94 = _RAND_278[0:0];
+  ic_tag_valid_out_1_123 = _RAND_278[0:0];
   _RAND_279 = {1{`RANDOM}};
-  ic_tag_valid_out_1_95 = _RAND_279[0:0];
+  ic_tag_valid_out_1_124 = _RAND_279[0:0];
   _RAND_280 = {1{`RANDOM}};
-  ic_tag_valid_out_1_96 = _RAND_280[0:0];
+  ic_tag_valid_out_1_125 = _RAND_280[0:0];
   _RAND_281 = {1{`RANDOM}};
-  ic_tag_valid_out_1_97 = _RAND_281[0:0];
+  ic_tag_valid_out_1_126 = _RAND_281[0:0];
   _RAND_282 = {1{`RANDOM}};
-  ic_tag_valid_out_1_98 = _RAND_282[0:0];
+  ic_tag_valid_out_1_127 = _RAND_282[0:0];
   _RAND_283 = {1{`RANDOM}};
-  ic_tag_valid_out_1_99 = _RAND_283[0:0];
+  ic_tag_valid_out_0_0 = _RAND_283[0:0];
   _RAND_284 = {1{`RANDOM}};
-  ic_tag_valid_out_1_100 = _RAND_284[0:0];
+  ic_tag_valid_out_0_1 = _RAND_284[0:0];
   _RAND_285 = {1{`RANDOM}};
-  ic_tag_valid_out_1_101 = _RAND_285[0:0];
+  ic_tag_valid_out_0_2 = _RAND_285[0:0];
   _RAND_286 = {1{`RANDOM}};
-  ic_tag_valid_out_1_102 = _RAND_286[0:0];
+  ic_tag_valid_out_0_3 = _RAND_286[0:0];
   _RAND_287 = {1{`RANDOM}};
-  ic_tag_valid_out_1_103 = _RAND_287[0:0];
+  ic_tag_valid_out_0_4 = _RAND_287[0:0];
   _RAND_288 = {1{`RANDOM}};
-  ic_tag_valid_out_1_104 = _RAND_288[0:0];
+  ic_tag_valid_out_0_5 = _RAND_288[0:0];
   _RAND_289 = {1{`RANDOM}};
-  ic_tag_valid_out_1_105 = _RAND_289[0:0];
+  ic_tag_valid_out_0_6 = _RAND_289[0:0];
   _RAND_290 = {1{`RANDOM}};
-  ic_tag_valid_out_1_106 = _RAND_290[0:0];
+  ic_tag_valid_out_0_7 = _RAND_290[0:0];
   _RAND_291 = {1{`RANDOM}};
-  ic_tag_valid_out_1_107 = _RAND_291[0:0];
+  ic_tag_valid_out_0_8 = _RAND_291[0:0];
   _RAND_292 = {1{`RANDOM}};
-  ic_tag_valid_out_1_108 = _RAND_292[0:0];
+  ic_tag_valid_out_0_9 = _RAND_292[0:0];
   _RAND_293 = {1{`RANDOM}};
-  ic_tag_valid_out_1_109 = _RAND_293[0:0];
+  ic_tag_valid_out_0_10 = _RAND_293[0:0];
   _RAND_294 = {1{`RANDOM}};
-  ic_tag_valid_out_1_110 = _RAND_294[0:0];
+  ic_tag_valid_out_0_11 = _RAND_294[0:0];
   _RAND_295 = {1{`RANDOM}};
-  ic_tag_valid_out_1_111 = _RAND_295[0:0];
+  ic_tag_valid_out_0_12 = _RAND_295[0:0];
   _RAND_296 = {1{`RANDOM}};
-  ic_tag_valid_out_1_112 = _RAND_296[0:0];
+  ic_tag_valid_out_0_13 = _RAND_296[0:0];
   _RAND_297 = {1{`RANDOM}};
-  ic_tag_valid_out_1_113 = _RAND_297[0:0];
+  ic_tag_valid_out_0_14 = _RAND_297[0:0];
   _RAND_298 = {1{`RANDOM}};
-  ic_tag_valid_out_1_114 = _RAND_298[0:0];
+  ic_tag_valid_out_0_15 = _RAND_298[0:0];
   _RAND_299 = {1{`RANDOM}};
-  ic_tag_valid_out_1_115 = _RAND_299[0:0];
+  ic_tag_valid_out_0_16 = _RAND_299[0:0];
   _RAND_300 = {1{`RANDOM}};
-  ic_tag_valid_out_1_116 = _RAND_300[0:0];
+  ic_tag_valid_out_0_17 = _RAND_300[0:0];
   _RAND_301 = {1{`RANDOM}};
-  ic_tag_valid_out_1_117 = _RAND_301[0:0];
+  ic_tag_valid_out_0_18 = _RAND_301[0:0];
   _RAND_302 = {1{`RANDOM}};
-  ic_tag_valid_out_1_118 = _RAND_302[0:0];
+  ic_tag_valid_out_0_19 = _RAND_302[0:0];
   _RAND_303 = {1{`RANDOM}};
-  ic_tag_valid_out_1_119 = _RAND_303[0:0];
+  ic_tag_valid_out_0_20 = _RAND_303[0:0];
   _RAND_304 = {1{`RANDOM}};
-  ic_tag_valid_out_1_120 = _RAND_304[0:0];
+  ic_tag_valid_out_0_21 = _RAND_304[0:0];
   _RAND_305 = {1{`RANDOM}};
-  ic_tag_valid_out_1_121 = _RAND_305[0:0];
+  ic_tag_valid_out_0_22 = _RAND_305[0:0];
   _RAND_306 = {1{`RANDOM}};
-  ic_tag_valid_out_1_122 = _RAND_306[0:0];
+  ic_tag_valid_out_0_23 = _RAND_306[0:0];
   _RAND_307 = {1{`RANDOM}};
-  ic_tag_valid_out_1_123 = _RAND_307[0:0];
+  ic_tag_valid_out_0_24 = _RAND_307[0:0];
   _RAND_308 = {1{`RANDOM}};
-  ic_tag_valid_out_1_124 = _RAND_308[0:0];
+  ic_tag_valid_out_0_25 = _RAND_308[0:0];
   _RAND_309 = {1{`RANDOM}};
-  ic_tag_valid_out_1_125 = _RAND_309[0:0];
+  ic_tag_valid_out_0_26 = _RAND_309[0:0];
   _RAND_310 = {1{`RANDOM}};
-  ic_tag_valid_out_1_126 = _RAND_310[0:0];
+  ic_tag_valid_out_0_27 = _RAND_310[0:0];
   _RAND_311 = {1{`RANDOM}};
-  ic_tag_valid_out_1_127 = _RAND_311[0:0];
+  ic_tag_valid_out_0_28 = _RAND_311[0:0];
   _RAND_312 = {1{`RANDOM}};
-  ic_tag_valid_out_0_0 = _RAND_312[0:0];
+  ic_tag_valid_out_0_29 = _RAND_312[0:0];
   _RAND_313 = {1{`RANDOM}};
-  ic_tag_valid_out_0_1 = _RAND_313[0:0];
+  ic_tag_valid_out_0_30 = _RAND_313[0:0];
   _RAND_314 = {1{`RANDOM}};
-  ic_tag_valid_out_0_2 = _RAND_314[0:0];
+  ic_tag_valid_out_0_31 = _RAND_314[0:0];
   _RAND_315 = {1{`RANDOM}};
-  ic_tag_valid_out_0_3 = _RAND_315[0:0];
+  ic_tag_valid_out_0_32 = _RAND_315[0:0];
   _RAND_316 = {1{`RANDOM}};
-  ic_tag_valid_out_0_4 = _RAND_316[0:0];
+  ic_tag_valid_out_0_33 = _RAND_316[0:0];
   _RAND_317 = {1{`RANDOM}};
-  ic_tag_valid_out_0_5 = _RAND_317[0:0];
+  ic_tag_valid_out_0_34 = _RAND_317[0:0];
   _RAND_318 = {1{`RANDOM}};
-  ic_tag_valid_out_0_6 = _RAND_318[0:0];
+  ic_tag_valid_out_0_35 = _RAND_318[0:0];
   _RAND_319 = {1{`RANDOM}};
-  ic_tag_valid_out_0_7 = _RAND_319[0:0];
+  ic_tag_valid_out_0_36 = _RAND_319[0:0];
   _RAND_320 = {1{`RANDOM}};
-  ic_tag_valid_out_0_8 = _RAND_320[0:0];
+  ic_tag_valid_out_0_37 = _RAND_320[0:0];
   _RAND_321 = {1{`RANDOM}};
-  ic_tag_valid_out_0_9 = _RAND_321[0:0];
+  ic_tag_valid_out_0_38 = _RAND_321[0:0];
   _RAND_322 = {1{`RANDOM}};
-  ic_tag_valid_out_0_10 = _RAND_322[0:0];
+  ic_tag_valid_out_0_39 = _RAND_322[0:0];
   _RAND_323 = {1{`RANDOM}};
-  ic_tag_valid_out_0_11 = _RAND_323[0:0];
+  ic_tag_valid_out_0_40 = _RAND_323[0:0];
   _RAND_324 = {1{`RANDOM}};
-  ic_tag_valid_out_0_12 = _RAND_324[0:0];
+  ic_tag_valid_out_0_41 = _RAND_324[0:0];
   _RAND_325 = {1{`RANDOM}};
-  ic_tag_valid_out_0_13 = _RAND_325[0:0];
+  ic_tag_valid_out_0_42 = _RAND_325[0:0];
   _RAND_326 = {1{`RANDOM}};
-  ic_tag_valid_out_0_14 = _RAND_326[0:0];
+  ic_tag_valid_out_0_43 = _RAND_326[0:0];
   _RAND_327 = {1{`RANDOM}};
-  ic_tag_valid_out_0_15 = _RAND_327[0:0];
+  ic_tag_valid_out_0_44 = _RAND_327[0:0];
   _RAND_328 = {1{`RANDOM}};
-  ic_tag_valid_out_0_16 = _RAND_328[0:0];
+  ic_tag_valid_out_0_45 = _RAND_328[0:0];
   _RAND_329 = {1{`RANDOM}};
-  ic_tag_valid_out_0_17 = _RAND_329[0:0];
+  ic_tag_valid_out_0_46 = _RAND_329[0:0];
   _RAND_330 = {1{`RANDOM}};
-  ic_tag_valid_out_0_18 = _RAND_330[0:0];
+  ic_tag_valid_out_0_47 = _RAND_330[0:0];
   _RAND_331 = {1{`RANDOM}};
-  ic_tag_valid_out_0_19 = _RAND_331[0:0];
+  ic_tag_valid_out_0_48 = _RAND_331[0:0];
   _RAND_332 = {1{`RANDOM}};
-  ic_tag_valid_out_0_20 = _RAND_332[0:0];
+  ic_tag_valid_out_0_49 = _RAND_332[0:0];
   _RAND_333 = {1{`RANDOM}};
-  ic_tag_valid_out_0_21 = _RAND_333[0:0];
+  ic_tag_valid_out_0_50 = _RAND_333[0:0];
   _RAND_334 = {1{`RANDOM}};
-  ic_tag_valid_out_0_22 = _RAND_334[0:0];
+  ic_tag_valid_out_0_51 = _RAND_334[0:0];
   _RAND_335 = {1{`RANDOM}};
-  ic_tag_valid_out_0_23 = _RAND_335[0:0];
+  ic_tag_valid_out_0_52 = _RAND_335[0:0];
   _RAND_336 = {1{`RANDOM}};
-  ic_tag_valid_out_0_24 = _RAND_336[0:0];
+  ic_tag_valid_out_0_53 = _RAND_336[0:0];
   _RAND_337 = {1{`RANDOM}};
-  ic_tag_valid_out_0_25 = _RAND_337[0:0];
+  ic_tag_valid_out_0_54 = _RAND_337[0:0];
   _RAND_338 = {1{`RANDOM}};
-  ic_tag_valid_out_0_26 = _RAND_338[0:0];
+  ic_tag_valid_out_0_55 = _RAND_338[0:0];
   _RAND_339 = {1{`RANDOM}};
-  ic_tag_valid_out_0_27 = _RAND_339[0:0];
+  ic_tag_valid_out_0_56 = _RAND_339[0:0];
   _RAND_340 = {1{`RANDOM}};
-  ic_tag_valid_out_0_28 = _RAND_340[0:0];
+  ic_tag_valid_out_0_57 = _RAND_340[0:0];
   _RAND_341 = {1{`RANDOM}};
-  ic_tag_valid_out_0_29 = _RAND_341[0:0];
+  ic_tag_valid_out_0_58 = _RAND_341[0:0];
   _RAND_342 = {1{`RANDOM}};
-  ic_tag_valid_out_0_30 = _RAND_342[0:0];
+  ic_tag_valid_out_0_59 = _RAND_342[0:0];
   _RAND_343 = {1{`RANDOM}};
-  ic_tag_valid_out_0_31 = _RAND_343[0:0];
+  ic_tag_valid_out_0_60 = _RAND_343[0:0];
   _RAND_344 = {1{`RANDOM}};
-  ic_tag_valid_out_0_32 = _RAND_344[0:0];
+  ic_tag_valid_out_0_61 = _RAND_344[0:0];
   _RAND_345 = {1{`RANDOM}};
-  ic_tag_valid_out_0_33 = _RAND_345[0:0];
+  ic_tag_valid_out_0_62 = _RAND_345[0:0];
   _RAND_346 = {1{`RANDOM}};
-  ic_tag_valid_out_0_34 = _RAND_346[0:0];
+  ic_tag_valid_out_0_63 = _RAND_346[0:0];
   _RAND_347 = {1{`RANDOM}};
-  ic_tag_valid_out_0_35 = _RAND_347[0:0];
+  ic_tag_valid_out_0_64 = _RAND_347[0:0];
   _RAND_348 = {1{`RANDOM}};
-  ic_tag_valid_out_0_36 = _RAND_348[0:0];
+  ic_tag_valid_out_0_65 = _RAND_348[0:0];
   _RAND_349 = {1{`RANDOM}};
-  ic_tag_valid_out_0_37 = _RAND_349[0:0];
+  ic_tag_valid_out_0_66 = _RAND_349[0:0];
   _RAND_350 = {1{`RANDOM}};
-  ic_tag_valid_out_0_38 = _RAND_350[0:0];
+  ic_tag_valid_out_0_67 = _RAND_350[0:0];
   _RAND_351 = {1{`RANDOM}};
-  ic_tag_valid_out_0_39 = _RAND_351[0:0];
+  ic_tag_valid_out_0_68 = _RAND_351[0:0];
   _RAND_352 = {1{`RANDOM}};
-  ic_tag_valid_out_0_40 = _RAND_352[0:0];
+  ic_tag_valid_out_0_69 = _RAND_352[0:0];
   _RAND_353 = {1{`RANDOM}};
-  ic_tag_valid_out_0_41 = _RAND_353[0:0];
+  ic_tag_valid_out_0_70 = _RAND_353[0:0];
   _RAND_354 = {1{`RANDOM}};
-  ic_tag_valid_out_0_42 = _RAND_354[0:0];
+  ic_tag_valid_out_0_71 = _RAND_354[0:0];
   _RAND_355 = {1{`RANDOM}};
-  ic_tag_valid_out_0_43 = _RAND_355[0:0];
+  ic_tag_valid_out_0_72 = _RAND_355[0:0];
   _RAND_356 = {1{`RANDOM}};
-  ic_tag_valid_out_0_44 = _RAND_356[0:0];
+  ic_tag_valid_out_0_73 = _RAND_356[0:0];
   _RAND_357 = {1{`RANDOM}};
-  ic_tag_valid_out_0_45 = _RAND_357[0:0];
+  ic_tag_valid_out_0_74 = _RAND_357[0:0];
   _RAND_358 = {1{`RANDOM}};
-  ic_tag_valid_out_0_46 = _RAND_358[0:0];
+  ic_tag_valid_out_0_75 = _RAND_358[0:0];
   _RAND_359 = {1{`RANDOM}};
-  ic_tag_valid_out_0_47 = _RAND_359[0:0];
+  ic_tag_valid_out_0_76 = _RAND_359[0:0];
   _RAND_360 = {1{`RANDOM}};
-  ic_tag_valid_out_0_48 = _RAND_360[0:0];
+  ic_tag_valid_out_0_77 = _RAND_360[0:0];
   _RAND_361 = {1{`RANDOM}};
-  ic_tag_valid_out_0_49 = _RAND_361[0:0];
+  ic_tag_valid_out_0_78 = _RAND_361[0:0];
   _RAND_362 = {1{`RANDOM}};
-  ic_tag_valid_out_0_50 = _RAND_362[0:0];
+  ic_tag_valid_out_0_79 = _RAND_362[0:0];
   _RAND_363 = {1{`RANDOM}};
-  ic_tag_valid_out_0_51 = _RAND_363[0:0];
+  ic_tag_valid_out_0_80 = _RAND_363[0:0];
   _RAND_364 = {1{`RANDOM}};
-  ic_tag_valid_out_0_52 = _RAND_364[0:0];
+  ic_tag_valid_out_0_81 = _RAND_364[0:0];
   _RAND_365 = {1{`RANDOM}};
-  ic_tag_valid_out_0_53 = _RAND_365[0:0];
+  ic_tag_valid_out_0_82 = _RAND_365[0:0];
   _RAND_366 = {1{`RANDOM}};
-  ic_tag_valid_out_0_54 = _RAND_366[0:0];
+  ic_tag_valid_out_0_83 = _RAND_366[0:0];
   _RAND_367 = {1{`RANDOM}};
-  ic_tag_valid_out_0_55 = _RAND_367[0:0];
+  ic_tag_valid_out_0_84 = _RAND_367[0:0];
   _RAND_368 = {1{`RANDOM}};
-  ic_tag_valid_out_0_56 = _RAND_368[0:0];
+  ic_tag_valid_out_0_85 = _RAND_368[0:0];
   _RAND_369 = {1{`RANDOM}};
-  ic_tag_valid_out_0_57 = _RAND_369[0:0];
+  ic_tag_valid_out_0_86 = _RAND_369[0:0];
   _RAND_370 = {1{`RANDOM}};
-  ic_tag_valid_out_0_58 = _RAND_370[0:0];
+  ic_tag_valid_out_0_87 = _RAND_370[0:0];
   _RAND_371 = {1{`RANDOM}};
-  ic_tag_valid_out_0_59 = _RAND_371[0:0];
+  ic_tag_valid_out_0_88 = _RAND_371[0:0];
   _RAND_372 = {1{`RANDOM}};
-  ic_tag_valid_out_0_60 = _RAND_372[0:0];
+  ic_tag_valid_out_0_89 = _RAND_372[0:0];
   _RAND_373 = {1{`RANDOM}};
-  ic_tag_valid_out_0_61 = _RAND_373[0:0];
+  ic_tag_valid_out_0_90 = _RAND_373[0:0];
   _RAND_374 = {1{`RANDOM}};
-  ic_tag_valid_out_0_62 = _RAND_374[0:0];
+  ic_tag_valid_out_0_91 = _RAND_374[0:0];
   _RAND_375 = {1{`RANDOM}};
-  ic_tag_valid_out_0_63 = _RAND_375[0:0];
+  ic_tag_valid_out_0_92 = _RAND_375[0:0];
   _RAND_376 = {1{`RANDOM}};
-  ic_tag_valid_out_0_64 = _RAND_376[0:0];
+  ic_tag_valid_out_0_93 = _RAND_376[0:0];
   _RAND_377 = {1{`RANDOM}};
-  ic_tag_valid_out_0_65 = _RAND_377[0:0];
+  ic_tag_valid_out_0_94 = _RAND_377[0:0];
   _RAND_378 = {1{`RANDOM}};
-  ic_tag_valid_out_0_66 = _RAND_378[0:0];
+  ic_tag_valid_out_0_95 = _RAND_378[0:0];
   _RAND_379 = {1{`RANDOM}};
-  ic_tag_valid_out_0_67 = _RAND_379[0:0];
+  ic_tag_valid_out_0_96 = _RAND_379[0:0];
   _RAND_380 = {1{`RANDOM}};
-  ic_tag_valid_out_0_68 = _RAND_380[0:0];
+  ic_tag_valid_out_0_97 = _RAND_380[0:0];
   _RAND_381 = {1{`RANDOM}};
-  ic_tag_valid_out_0_69 = _RAND_381[0:0];
+  ic_tag_valid_out_0_98 = _RAND_381[0:0];
   _RAND_382 = {1{`RANDOM}};
-  ic_tag_valid_out_0_70 = _RAND_382[0:0];
+  ic_tag_valid_out_0_99 = _RAND_382[0:0];
   _RAND_383 = {1{`RANDOM}};
-  ic_tag_valid_out_0_71 = _RAND_383[0:0];
+  ic_tag_valid_out_0_100 = _RAND_383[0:0];
   _RAND_384 = {1{`RANDOM}};
-  ic_tag_valid_out_0_72 = _RAND_384[0:0];
+  ic_tag_valid_out_0_101 = _RAND_384[0:0];
   _RAND_385 = {1{`RANDOM}};
-  ic_tag_valid_out_0_73 = _RAND_385[0:0];
+  ic_tag_valid_out_0_102 = _RAND_385[0:0];
   _RAND_386 = {1{`RANDOM}};
-  ic_tag_valid_out_0_74 = _RAND_386[0:0];
+  ic_tag_valid_out_0_103 = _RAND_386[0:0];
   _RAND_387 = {1{`RANDOM}};
-  ic_tag_valid_out_0_75 = _RAND_387[0:0];
+  ic_tag_valid_out_0_104 = _RAND_387[0:0];
   _RAND_388 = {1{`RANDOM}};
-  ic_tag_valid_out_0_76 = _RAND_388[0:0];
+  ic_tag_valid_out_0_105 = _RAND_388[0:0];
   _RAND_389 = {1{`RANDOM}};
-  ic_tag_valid_out_0_77 = _RAND_389[0:0];
+  ic_tag_valid_out_0_106 = _RAND_389[0:0];
   _RAND_390 = {1{`RANDOM}};
-  ic_tag_valid_out_0_78 = _RAND_390[0:0];
+  ic_tag_valid_out_0_107 = _RAND_390[0:0];
   _RAND_391 = {1{`RANDOM}};
-  ic_tag_valid_out_0_79 = _RAND_391[0:0];
+  ic_tag_valid_out_0_108 = _RAND_391[0:0];
   _RAND_392 = {1{`RANDOM}};
-  ic_tag_valid_out_0_80 = _RAND_392[0:0];
+  ic_tag_valid_out_0_109 = _RAND_392[0:0];
   _RAND_393 = {1{`RANDOM}};
-  ic_tag_valid_out_0_81 = _RAND_393[0:0];
+  ic_tag_valid_out_0_110 = _RAND_393[0:0];
   _RAND_394 = {1{`RANDOM}};
-  ic_tag_valid_out_0_82 = _RAND_394[0:0];
+  ic_tag_valid_out_0_111 = _RAND_394[0:0];
   _RAND_395 = {1{`RANDOM}};
-  ic_tag_valid_out_0_83 = _RAND_395[0:0];
+  ic_tag_valid_out_0_112 = _RAND_395[0:0];
   _RAND_396 = {1{`RANDOM}};
-  ic_tag_valid_out_0_84 = _RAND_396[0:0];
+  ic_tag_valid_out_0_113 = _RAND_396[0:0];
   _RAND_397 = {1{`RANDOM}};
-  ic_tag_valid_out_0_85 = _RAND_397[0:0];
+  ic_tag_valid_out_0_114 = _RAND_397[0:0];
   _RAND_398 = {1{`RANDOM}};
-  ic_tag_valid_out_0_86 = _RAND_398[0:0];
+  ic_tag_valid_out_0_115 = _RAND_398[0:0];
   _RAND_399 = {1{`RANDOM}};
-  ic_tag_valid_out_0_87 = _RAND_399[0:0];
+  ic_tag_valid_out_0_116 = _RAND_399[0:0];
   _RAND_400 = {1{`RANDOM}};
-  ic_tag_valid_out_0_88 = _RAND_400[0:0];
+  ic_tag_valid_out_0_117 = _RAND_400[0:0];
   _RAND_401 = {1{`RANDOM}};
-  ic_tag_valid_out_0_89 = _RAND_401[0:0];
+  ic_tag_valid_out_0_118 = _RAND_401[0:0];
   _RAND_402 = {1{`RANDOM}};
-  ic_tag_valid_out_0_90 = _RAND_402[0:0];
+  ic_tag_valid_out_0_119 = _RAND_402[0:0];
   _RAND_403 = {1{`RANDOM}};
-  ic_tag_valid_out_0_91 = _RAND_403[0:0];
+  ic_tag_valid_out_0_120 = _RAND_403[0:0];
   _RAND_404 = {1{`RANDOM}};
-  ic_tag_valid_out_0_92 = _RAND_404[0:0];
+  ic_tag_valid_out_0_121 = _RAND_404[0:0];
   _RAND_405 = {1{`RANDOM}};
-  ic_tag_valid_out_0_93 = _RAND_405[0:0];
+  ic_tag_valid_out_0_122 = _RAND_405[0:0];
   _RAND_406 = {1{`RANDOM}};
-  ic_tag_valid_out_0_94 = _RAND_406[0:0];
+  ic_tag_valid_out_0_123 = _RAND_406[0:0];
   _RAND_407 = {1{`RANDOM}};
-  ic_tag_valid_out_0_95 = _RAND_407[0:0];
+  ic_tag_valid_out_0_124 = _RAND_407[0:0];
   _RAND_408 = {1{`RANDOM}};
-  ic_tag_valid_out_0_96 = _RAND_408[0:0];
+  ic_tag_valid_out_0_125 = _RAND_408[0:0];
   _RAND_409 = {1{`RANDOM}};
-  ic_tag_valid_out_0_97 = _RAND_409[0:0];
+  ic_tag_valid_out_0_126 = _RAND_409[0:0];
   _RAND_410 = {1{`RANDOM}};
-  ic_tag_valid_out_0_98 = _RAND_410[0:0];
+  ic_tag_valid_out_0_127 = _RAND_410[0:0];
   _RAND_411 = {1{`RANDOM}};
-  ic_tag_valid_out_0_99 = _RAND_411[0:0];
+  ic_debug_way_ff = _RAND_411[1:0];
   _RAND_412 = {1{`RANDOM}};
-  ic_tag_valid_out_0_100 = _RAND_412[0:0];
-  _RAND_413 = {1{`RANDOM}};
-  ic_tag_valid_out_0_101 = _RAND_413[0:0];
+  ic_debug_rd_en_ff = _RAND_412[0:0];
+  _RAND_413 = {3{`RANDOM}};
+  _T_1212 = _RAND_413[70:0];
   _RAND_414 = {1{`RANDOM}};
-  ic_tag_valid_out_0_102 = _RAND_414[0:0];
+  ifc_region_acc_fault_memory_f = _RAND_414[0:0];
   _RAND_415 = {1{`RANDOM}};
-  ic_tag_valid_out_0_103 = _RAND_415[0:0];
+  perr_ic_index_ff = _RAND_415[6:0];
   _RAND_416 = {1{`RANDOM}};
-  ic_tag_valid_out_0_104 = _RAND_416[0:0];
+  dma_sb_err_state_ff = _RAND_416[0:0];
   _RAND_417 = {1{`RANDOM}};
-  ic_tag_valid_out_0_105 = _RAND_417[0:0];
+  bus_cmd_req_hold = _RAND_417[0:0];
   _RAND_418 = {1{`RANDOM}};
-  ic_tag_valid_out_0_106 = _RAND_418[0:0];
+  ifu_bus_cmd_valid = _RAND_418[0:0];
   _RAND_419 = {1{`RANDOM}};
-  ic_tag_valid_out_0_107 = _RAND_419[0:0];
+  ifu_bus_arvalid_ff = _RAND_419[0:0];
   _RAND_420 = {1{`RANDOM}};
-  ic_tag_valid_out_0_108 = _RAND_420[0:0];
-  _RAND_421 = {1{`RANDOM}};
-  ic_tag_valid_out_0_109 = _RAND_421[0:0];
+  ifc_dma_access_ok_prev = _RAND_420[0:0];
+  _RAND_421 = {2{`RANDOM}};
+  iccm_ecc_corr_data_ff = _RAND_421[38:0];
   _RAND_422 = {1{`RANDOM}};
-  ic_tag_valid_out_0_110 = _RAND_422[0:0];
+  dma_mem_addr_ff = _RAND_422[1:0];
   _RAND_423 = {1{`RANDOM}};
-  ic_tag_valid_out_0_111 = _RAND_423[0:0];
+  dma_mem_tag_ff = _RAND_423[2:0];
   _RAND_424 = {1{`RANDOM}};
-  ic_tag_valid_out_0_112 = _RAND_424[0:0];
+  iccm_dma_rtag_temp = _RAND_424[2:0];
   _RAND_425 = {1{`RANDOM}};
-  ic_tag_valid_out_0_113 = _RAND_425[0:0];
+  iccm_dma_rvalid_temp = _RAND_425[0:0];
   _RAND_426 = {1{`RANDOM}};
-  ic_tag_valid_out_0_114 = _RAND_426[0:0];
-  _RAND_427 = {1{`RANDOM}};
-  ic_tag_valid_out_0_115 = _RAND_427[0:0];
+  iccm_dma_ecc_error = _RAND_426[0:0];
+  _RAND_427 = {2{`RANDOM}};
+  iccm_dma_rdata_temp = _RAND_427[63:0];
   _RAND_428 = {1{`RANDOM}};
-  ic_tag_valid_out_0_116 = _RAND_428[0:0];
+  iccm_ecc_corr_index_ff = _RAND_428[13:0];
   _RAND_429 = {1{`RANDOM}};
-  ic_tag_valid_out_0_117 = _RAND_429[0:0];
+  iccm_rd_ecc_single_err_ff = _RAND_429[0:0];
   _RAND_430 = {1{`RANDOM}};
-  ic_tag_valid_out_0_118 = _RAND_430[0:0];
+  iccm_rw_addr_f = _RAND_430[13:0];
   _RAND_431 = {1{`RANDOM}};
-  ic_tag_valid_out_0_119 = _RAND_431[0:0];
+  ifu_status_wr_addr_ff = _RAND_431[6:0];
   _RAND_432 = {1{`RANDOM}};
-  ic_tag_valid_out_0_120 = _RAND_432[0:0];
+  way_status_wr_en_ff = _RAND_432[0:0];
   _RAND_433 = {1{`RANDOM}};
-  ic_tag_valid_out_0_121 = _RAND_433[0:0];
+  way_status_new_ff = _RAND_433[0:0];
   _RAND_434 = {1{`RANDOM}};
-  ic_tag_valid_out_0_122 = _RAND_434[0:0];
+  ifu_tag_wren_ff = _RAND_434[1:0];
   _RAND_435 = {1{`RANDOM}};
-  ic_tag_valid_out_0_123 = _RAND_435[0:0];
+  ic_valid_ff = _RAND_435[0:0];
   _RAND_436 = {1{`RANDOM}};
-  ic_tag_valid_out_0_124 = _RAND_436[0:0];
+  _T_9799 = _RAND_436[0:0];
   _RAND_437 = {1{`RANDOM}};
-  ic_tag_valid_out_0_125 = _RAND_437[0:0];
+  _T_9800 = _RAND_437[0:0];
   _RAND_438 = {1{`RANDOM}};
-  ic_tag_valid_out_0_126 = _RAND_438[0:0];
+  _T_9801 = _RAND_438[0:0];
   _RAND_439 = {1{`RANDOM}};
-  ic_tag_valid_out_0_127 = _RAND_439[0:0];
+  _T_9805 = _RAND_439[0:0];
   _RAND_440 = {1{`RANDOM}};
-  ic_debug_way_ff = _RAND_440[1:0];
-  _RAND_441 = {1{`RANDOM}};
-  ic_debug_rd_en_ff = _RAND_441[0:0];
-  _RAND_442 = {3{`RANDOM}};
-  _T_1212 = _RAND_442[70:0];
-  _RAND_443 = {1{`RANDOM}};
-  ifc_region_acc_fault_memory_f = _RAND_443[0:0];
-  _RAND_444 = {1{`RANDOM}};
-  perr_ic_index_ff = _RAND_444[6:0];
-  _RAND_445 = {1{`RANDOM}};
-  dma_sb_err_state_ff = _RAND_445[0:0];
-  _RAND_446 = {1{`RANDOM}};
-  bus_cmd_req_hold = _RAND_446[0:0];
-  _RAND_447 = {1{`RANDOM}};
-  ifu_bus_cmd_valid = _RAND_447[0:0];
-  _RAND_448 = {1{`RANDOM}};
-  bus_cmd_beat_count = _RAND_448[2:0];
-  _RAND_449 = {1{`RANDOM}};
-  ifu_bus_arready_unq_ff = _RAND_449[0:0];
-  _RAND_450 = {1{`RANDOM}};
-  ifu_bus_arvalid_ff = _RAND_450[0:0];
-  _RAND_451 = {1{`RANDOM}};
-  ifc_dma_access_ok_prev = _RAND_451[0:0];
-  _RAND_452 = {2{`RANDOM}};
-  iccm_ecc_corr_data_ff = _RAND_452[38:0];
-  _RAND_453 = {1{`RANDOM}};
-  dma_mem_addr_ff = _RAND_453[1:0];
-  _RAND_454 = {1{`RANDOM}};
-  dma_mem_tag_ff = _RAND_454[2:0];
-  _RAND_455 = {1{`RANDOM}};
-  iccm_dma_rtag_temp = _RAND_455[2:0];
-  _RAND_456 = {1{`RANDOM}};
-  iccm_dma_rvalid_temp = _RAND_456[0:0];
-  _RAND_457 = {1{`RANDOM}};
-  iccm_dma_ecc_error = _RAND_457[0:0];
-  _RAND_458 = {2{`RANDOM}};
-  iccm_dma_rdata_temp = _RAND_458[63:0];
-  _RAND_459 = {1{`RANDOM}};
-  iccm_ecc_corr_index_ff = _RAND_459[13:0];
-  _RAND_460 = {1{`RANDOM}};
-  iccm_rd_ecc_single_err_ff = _RAND_460[0:0];
-  _RAND_461 = {1{`RANDOM}};
-  iccm_rw_addr_f = _RAND_461[13:0];
-  _RAND_462 = {1{`RANDOM}};
-  ifu_status_wr_addr_ff = _RAND_462[6:0];
-  _RAND_463 = {1{`RANDOM}};
-  way_status_wr_en_ff = _RAND_463[0:0];
-  _RAND_464 = {1{`RANDOM}};
-  way_status_new_ff = _RAND_464[0:0];
-  _RAND_465 = {1{`RANDOM}};
-  ifu_tag_wren_ff = _RAND_465[1:0];
-  _RAND_466 = {1{`RANDOM}};
-  ic_valid_ff = _RAND_466[0:0];
-  _RAND_467 = {1{`RANDOM}};
-  _T_9799 = _RAND_467[0:0];
-  _RAND_468 = {1{`RANDOM}};
-  _T_9800 = _RAND_468[0:0];
-  _RAND_469 = {1{`RANDOM}};
-  _T_9801 = _RAND_469[0:0];
-  _RAND_470 = {1{`RANDOM}};
-  _T_9805 = _RAND_470[0:0];
-  _RAND_471 = {1{`RANDOM}};
-  _T_9806 = _RAND_471[0:0];
-  _RAND_472 = {1{`RANDOM}};
-  _T_9826 = _RAND_472[0:0];
+  _T_9826 = _RAND_440[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     flush_final_f = 1'h0;
@@ -6974,9 +6196,6 @@ initial begin
   if (reset) begin
     miss_state = 3'h0;
   end
-  if (reset) begin
-    scnd_miss_req_q = 1'h0;
-  end
   if (reset) begin
     ifu_fetch_addr_int_f = 31'h0;
   end
@@ -7001,33 +6220,18 @@ initial begin
   if (reset) begin
     ifc_region_acc_fault_final_f = 1'h0;
   end
-  if (reset) begin
-    ifu_bus_rvalid_unq_ff = 1'h0;
-  end
-  if (reset) begin
-    bus_ifu_bus_clk_en_ff = 1'h0;
-  end
   if (reset) begin
     uncacheable_miss_ff = 1'h0;
   end
-  if (reset) begin
-    bus_data_beat_count = 3'h0;
-  end
   if (reset) begin
     ic_miss_buff_data_valid = 8'h0;
   end
   if (reset) begin
     imb_ff = 31'h0;
   end
-  if (reset) begin
-    last_data_recieved_ff = 1'h0;
-  end
   if (reset) begin
     sel_mb_addr_ff = 1'h0;
   end
-  if (reset) begin
-    way_status_mb_scnd_ff = 1'h0;
-  end
   if (reset) begin
     ifu_ic_rw_int_addr_ff = 7'h0;
   end
@@ -7415,24 +6619,6 @@ initial begin
   if (reset) begin
     way_status_out_127 = 1'h0;
   end
-  if (reset) begin
-    tagv_mb_scnd_ff = 2'h0;
-  end
-  if (reset) begin
-    uncacheable_miss_scnd_ff = 1'h0;
-  end
-  if (reset) begin
-    imb_scnd_ff = 31'h0;
-  end
-  if (reset) begin
-    ifu_bus_rid_ff = 3'h0;
-  end
-  if (reset) begin
-    ifu_bus_rresp_ff = 2'h0;
-  end
-  if (reset) begin
-    ifu_wr_data_comb_err_ff = 1'h0;
-  end
   if (reset) begin
     way_status_mb_ff = 1'h0;
   end
@@ -7457,57 +6643,6 @@ initial begin
   if (reset) begin
     ic_act_miss_f_delayed = 1'h0;
   end
-  if (reset) begin
-    ifu_bus_rdata_ff = 64'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_0 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_1 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_2 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_3 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_4 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_5 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_6 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_7 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_8 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_9 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_10 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_11 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_12 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_13 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_14 = 32'h0;
-  end
-  if (reset) begin
-    ic_miss_buff_data_15 = 32'h0;
-  end
   if (reset) begin
     ic_crit_wd_rdy_new_ff = 1'h0;
   end
@@ -8309,12 +7444,6 @@ initial begin
   if (reset) begin
     ifu_bus_cmd_valid = 1'h0;
   end
-  if (reset) begin
-    bus_cmd_beat_count = 3'h0;
-  end
-  if (reset) begin
-    ifu_bus_arready_unq_ff = 1'h0;
-  end
   if (reset) begin
     ifu_bus_arvalid_ff = 1'h0;
   end
@@ -8378,9 +7507,6 @@ initial begin
   if (reset) begin
     _T_9805 = 1'h0;
   end
-  if (reset) begin
-    _T_9806 = 1'h0;
-  end
   if (reset) begin
     _T_9826 = 1'h0;
   end
@@ -8415,21 +7541,13 @@ end // initial
           miss_state <= 3'h2;
         end
       end else if (_T_31) begin
-        if (_T_36) begin
+        if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
           miss_state <= 3'h0;
         end else if (_T_40) begin
           miss_state <= 3'h3;
-        end else if (_T_47) begin
-          miss_state <= 3'h4;
-        end else if (_T_51) begin
-          miss_state <= 3'h0;
         end else if (_T_61) begin
           miss_state <= 3'h6;
-        end else if (_T_71) begin
-          miss_state <= 3'h6;
-        end else if (_T_79) begin
-          miss_state <= 3'h0;
-        end else if (_T_84) begin
+        end else if (_T_81) begin
           miss_state <= 3'h2;
         end else begin
           miss_state <= 3'h0;
@@ -8460,11 +7578,7 @@ end // initial
         if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
           miss_state <= 3'h0;
         end else if (io_exu_flush_final) begin
-          if (_T_32) begin
-            miss_state <= 3'h0;
-          end else begin
-            miss_state <= 3'h2;
-          end
+          miss_state <= 3'h2;
         end else begin
           miss_state <= 3'h1;
         end
@@ -8472,11 +7586,7 @@ end // initial
         if (io_dec_mem_ctrl_dec_tlu_force_halt) begin
           miss_state <= 3'h0;
         end else if (io_exu_flush_final) begin
-          if (_T_32) begin
-            miss_state <= 3'h0;
-          end else begin
-            miss_state <= 3'h2;
-          end
+          miss_state <= 3'h2;
         end else begin
           miss_state <= 3'h0;
         end
@@ -8485,13 +7595,6 @@ end // initial
       end
     end
   end
-  always @(posedge io_free_clk or posedge reset) begin
-    if (reset) begin
-      scnd_miss_req_q <= 1'h0;
-    end else begin
-      scnd_miss_req_q <= _T_22 & _T_319;
-    end
-  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       ifu_fetch_addr_int_f <= 31'h0;
@@ -8602,36 +7705,13 @@ end // initial
       ifc_region_acc_fault_final_f <= io_ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;
     end
   end
-  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ifu_bus_rvalid_unq_ff <= 1'h0;
-    end else begin
-      ifu_bus_rvalid_unq_ff <= io_ifu_axi_r_valid;
-    end
-  end
-  always @(posedge io_free_clk or posedge reset) begin
-    if (reset) begin
-      bus_ifu_bus_clk_en_ff <= 1'h0;
-    end else begin
-      bus_ifu_bus_clk_en_ff <= io_ifu_bus_clk_en;
-    end
-  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       uncacheable_miss_ff <= 1'h0;
-    end else if (scnd_miss_req) begin
-      uncacheable_miss_ff <= uncacheable_miss_scnd_ff;
     end else if (!(sel_hold_imb)) begin
       uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
     end
   end
-  always @(posedge io_free_clk or posedge reset) begin
-    if (reset) begin
-      bus_data_beat_count <= 3'h0;
-    end else begin
-      bus_data_beat_count <= _T_2631 | _T_2632;
-    end
-  end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       ic_miss_buff_data_valid <= 8'h0;
@@ -8642,31 +7722,15 @@ end // initial
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       imb_ff <= 31'h0;
-    end else if (scnd_miss_req) begin
-      imb_ff <= imb_scnd_ff;
     end else if (!(sel_hold_imb)) begin
       imb_ff <= io_ifc_fetch_addr_bf;
     end
   end
-  always @(posedge io_free_clk or posedge reset) begin
-    if (reset) begin
-      last_data_recieved_ff <= 1'h0;
-    end else begin
-      last_data_recieved_ff <= _T_2639 | _T_2641;
-    end
-  end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       sel_mb_addr_ff <= 1'h0;
     end else begin
-      sel_mb_addr_ff <= _T_334 | reset_tag_valid_for_miss;
-    end
-  end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
-    if (reset) begin
-      way_status_mb_scnd_ff <= 1'h0;
-    end else if (!(_T_19)) begin
-      way_status_mb_scnd_ff <= way_status;
+      sel_mb_addr_ff <= _T_2687 & _T_17;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -9574,55 +8638,9 @@ end // initial
       way_status_out_127 <= way_status_new_ff;
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
-    if (reset) begin
-      tagv_mb_scnd_ff <= 2'h0;
-    end else if (!(_T_19)) begin
-      tagv_mb_scnd_ff <= _T_198;
-    end
-  end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
-    if (reset) begin
-      uncacheable_miss_scnd_ff <= 1'h0;
-    end else if (!(sel_hold_imb_scnd)) begin
-      uncacheable_miss_scnd_ff <= io_ifc_fetch_uncacheable_bf;
-    end
-  end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
-    if (reset) begin
-      imb_scnd_ff <= 31'h0;
-    end else if (!(sel_hold_imb_scnd)) begin
-      imb_scnd_ff <= io_ifc_fetch_addr_bf;
-    end
-  end
-  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ifu_bus_rid_ff <= 3'h0;
-    end else begin
-      ifu_bus_rid_ff <= io_ifu_axi_r_bits_id;
-    end
-  end
-  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ifu_bus_rresp_ff <= 2'h0;
-    end else begin
-      ifu_bus_rresp_ff <= io_ifu_axi_r_bits_resp;
-    end
-  end
-  always @(posedge io_free_clk or posedge reset) begin
-    if (reset) begin
-      ifu_wr_data_comb_err_ff <= 1'h0;
-    end else begin
-      ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err_data & _T_2627;
-    end
-  end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       way_status_mb_ff <= 1'h0;
-    end else if (_T_278) begin
-      way_status_mb_ff <= way_status_mb_scnd_ff;
-    end else if (_T_280) begin
-      way_status_mb_ff <= replace_way_mb_any_0;
     end else if (!(miss_pending)) begin
       way_status_mb_ff <= way_status;
     end
@@ -9630,8 +8648,6 @@ end // initial
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
     if (reset) begin
       tagv_mb_ff <= 2'h0;
-    end else if (scnd_miss_req) begin
-      tagv_mb_ff <= _T_290;
     end else if (!(miss_pending)) begin
       tagv_mb_ff <= _T_295;
     end
@@ -9640,7 +8656,7 @@ end // initial
     if (reset) begin
       reset_ic_ff <= 1'h0;
     end else begin
-      reset_ic_ff <= _T_298 & _T_299;
+      reset_ic_ff <= miss_pending & _T_299;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
@@ -9655,8 +8671,6 @@ end // initial
       miss_addr <= 26'h0;
     end else if (_T_231) begin
       miss_addr <= imb_ff[30:5];
-    end else if (scnd_miss_req_q) begin
-      miss_addr <= imb_scnd_ff[30:5];
     end
   end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
@@ -9671,136 +8685,13 @@ end // initial
       bus_rd_addr_count <= 3'h0;
     end else if (_T_231) begin
       bus_rd_addr_count <= imb_ff[4:2];
-    end else if (scnd_miss_req_q) begin
-      bus_rd_addr_count <= imb_scnd_ff[4:2];
-    end else if (bus_cmd_sent) begin
-      bus_rd_addr_count <= _T_2647;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       ic_act_miss_f_delayed <= 1'h0;
     end else begin
-      ic_act_miss_f_delayed <= _T_233 & _T_209;
-    end
-  end
-  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ifu_bus_rdata_ff <= 64'h0;
-    end else begin
-      ifu_bus_rdata_ff <= io_ifu_axi_r_bits_data;
-    end
-  end
-  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_0 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_0 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_1 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_1 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_2 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_2 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_3 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_3 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_4 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_4 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_5 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_5 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_6 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_6 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_7 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_7 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_8 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_8 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_40_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_9 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_9 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_10 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_10 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_49_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_11 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_11 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_12 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_12 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_58_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_13 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_13 <= io_ifu_axi_r_bits_data[63:32];
-    end
-  end
-  always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_14 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_14 <= io_ifu_axi_r_bits_data[31:0];
-    end
-  end
-  always @(posedge rvclkhdr_67_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ic_miss_buff_data_15 <= 32'h0;
-    end else begin
-      ic_miss_buff_data_15 <= io_ifu_axi_r_bits_data[63:32];
+      ic_act_miss_f_delayed <= _T_232 & _T_209;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -11664,28 +10555,14 @@ end // initial
     if (reset) begin
       bus_cmd_req_hold <= 1'h0;
     end else begin
-      bus_cmd_req_hold <= _T_2604 & _T_2623;
+      bus_cmd_req_hold <= _T_2591 & _T_2623;
     end
   end
   always @(posedge rvclkhdr_69_io_l1clk or posedge reset) begin
     if (reset) begin
       ifu_bus_cmd_valid <= 1'h0;
     end else begin
-      ifu_bus_cmd_valid <= _T_2594 & _T_2600;
-    end
-  end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
-    if (reset) begin
-      bus_cmd_beat_count <= 3'h0;
-    end else if (bus_cmd_beat_en) begin
-      bus_cmd_beat_count <= bus_new_cmd_beat_count;
-    end
-  end
-  always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
-    if (reset) begin
-      ifu_bus_arready_unq_ff <= 1'h0;
-    end else begin
-      ifu_bus_arready_unq_ff <= io_ifu_axi_ar_ready;
+      ifu_bus_cmd_valid <= _T_2592 & _T_2623;
     end
   end
   always @(posedge rvclkhdr_68_io_l1clk or posedge reset) begin
@@ -11791,7 +10668,7 @@ end // initial
     if (reset) begin
       way_status_wr_en_ff <= 1'h0;
     end else begin
-      way_status_wr_en_ff <= way_status_wr_en | _T_4000;
+      way_status_wr_en_ff <= ic_act_hit_f | _T_4000;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -11799,8 +10676,6 @@ end // initial
       way_status_new_ff <= 1'h0;
     end else if (_T_4000) begin
       way_status_new_ff <= io_ic_debug_wr_data[4];
-    end else if (_T_9777) begin
-      way_status_new_ff <= replace_way_mb_any_0;
     end else begin
       way_status_new_ff <= way_status_hit_new;
     end
@@ -11825,7 +10700,7 @@ end // initial
     if (reset) begin
       _T_9799 <= 1'h0;
     end else begin
-      _T_9799 <= _T_233 & _T_209;
+      _T_9799 <= _T_232 & _T_209;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
@@ -11846,14 +10721,7 @@ end // initial
     if (reset) begin
       _T_9805 <= 1'h0;
     end else begin
-      _T_9805 <= _T_9803 & miss_pending;
-    end
-  end
-  always @(posedge io_active_clk or posedge reset) begin
-    if (reset) begin
-      _T_9806 <= 1'h0;
-    end else begin
-      _T_9806 <= _T_2618 & _T_2623;
+      _T_9805 <= ifu_bus_arvalid_ff & miss_pending;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -44134,7 +43002,6 @@ module ifu_ifc_ctl(
   input         io_ifu_bp_hit_taken_f,
   input  [30:0] io_ifu_bp_btb_target_f,
   input         io_ic_dma_active,
-  input         io_ic_write_stall,
   input         io_dec_ifc_dec_tlu_flush_noredir_wb,
   input  [31:0] io_dec_ifc_dec_tlu_mrac_ff,
   output        io_dec_ifc_ifu_pmu_fetch_stall,
@@ -44233,8 +43100,6 @@ module ifu_ifc_ctl(
   wire  _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[ifu_ifc_ctl.scala 86:51]
   wire  _T_40 = ~dma_stall; // @[ifu_ifc_ctl.scala 87:5]
   wire  _T_41 = _T_39 & _T_40; // @[ifu_ifc_ctl.scala 86:114]
-  wire  _T_42 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 87:18]
-  wire  _T_43 = _T_41 & _T_42; // @[ifu_ifc_ctl.scala 87:16]
   wire  _T_44 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 87:39]
   wire  _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 93:39]
   wire  _T_53 = _T_51 & _T_40; // @[ifu_ifc_ctl.scala 93:61]
@@ -44290,7 +43155,7 @@ module ifu_ifc_ctl(
   assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[ifu_ifc_ctl.scala 73:24]
   assign io_ifc_fetch_req_f = _T_164; // @[ifu_ifc_ctl.scala 145:22]
   assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[ifu_ifc_ctl.scala 143:31]
-  assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[ifu_ifc_ctl.scala 86:23]
+  assign io_ifc_fetch_req_bf = _T_41 & _T_44; // @[ifu_ifc_ctl.scala 86:23]
   assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 84:27]
   assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 137:25]
   assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 142:30]
@@ -44467,7 +43332,6 @@ module ifu(
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
   output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
-  output        io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
   output        io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
   output        io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   output [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -44511,10 +43375,7 @@ module ifu(
   input  [77:0] io_iccm_rd_data_ecc,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
-  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
-  output [70:0] io_ic_wr_data_0,
-  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -44529,15 +43390,8 @@ module ifu(
   output [1:0]  io_ic_debug_way,
   output [63:0] io_ic_premux_data,
   output        io_ic_sel_premux_data,
-  input         io_ifu_ar_ready,
   output        io_ifu_ar_valid,
-  output [2:0]  io_ifu_ar_bits_id,
   output [31:0] io_ifu_ar_bits_addr,
-  output [3:0]  io_ifu_ar_bits_region,
-  input         io_ifu_r_valid,
-  input  [2:0]  io_ifu_r_bits_id,
-  input  [63:0] io_ifu_r_bits_data,
-  input  [1:0]  io_ifu_r_bits_resp,
   input         io_ifu_bus_clk_en,
   input         io_ifu_dma_dma_ifc_dma_iccm_stall_any,
   input         io_ifu_dma_dma_mem_ctl_dma_iccm_req,
@@ -44573,7 +43427,6 @@ module ifu(
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 34:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 34:23]
   wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 34:23]
@@ -44588,16 +43441,8 @@ module ifu(
   wire  mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 34:23]
-  wire  mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23]
-  wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23]
   wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23]
-  wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23]
-  wire  mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23]
-  wire  mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23]
-  wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23]
-  wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 34:23]
-  wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 34:23]
   wire  mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 34:23]
   wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 34:23]
@@ -44616,10 +43461,7 @@ module ifu(
   wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 34:23]
   wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 34:23]
   wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 34:23]
-  wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ic_rd_en; // @[ifu.scala 34:23]
-  wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 34:23]
-  wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 34:23]
   wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 34:23]
   wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 34:23]
   wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 34:23]
@@ -44637,7 +43479,6 @@ module ifu(
   wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 34:23]
   wire  mem_ctl_io_ic_dma_active; // @[ifu.scala 34:23]
-  wire  mem_ctl_io_ic_write_stall; // @[ifu.scala 34:23]
   wire  mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 34:23]
   wire  mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 34:23]
   wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 34:23]
@@ -44756,7 +43597,6 @@ module ifu(
   wire  ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:23]
   wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_ic_dma_active; // @[ifu.scala 37:23]
-  wire  ifc_ctl_io_ic_write_stall; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 37:23]
   wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 37:23]
   wire  ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 37:23]
@@ -44789,7 +43629,6 @@ module ifu(
     .io_dec_mem_ctrl_ifu_pmu_ic_hit(mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_dec_mem_ctrl_ifu_pmu_bus_error(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_dec_mem_ctrl_ifu_pmu_bus_busy(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy),
-    .io_dec_mem_ctrl_ifu_pmu_bus_trxn(mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_dec_mem_ctrl_ifu_ic_error_start(mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start),
     .io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_dec_mem_ctrl_ifu_ic_debug_rd_data(mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -44804,16 +43643,8 @@ module ifu(
     .io_ifc_dma_access_ok(mem_ctl_io_ifc_dma_access_ok),
     .io_ifu_bp_hit_taken_f(mem_ctl_io_ifu_bp_hit_taken_f),
     .io_ifu_bp_inst_mask_f(mem_ctl_io_ifu_bp_inst_mask_f),
-    .io_ifu_axi_ar_ready(mem_ctl_io_ifu_axi_ar_ready),
     .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid),
-    .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id),
     .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr),
-    .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region),
-    .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready),
-    .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid),
-    .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id),
-    .io_ifu_axi_r_bits_data(mem_ctl_io_ifu_axi_r_bits_data),
-    .io_ifu_axi_r_bits_resp(mem_ctl_io_ifu_axi_r_bits_resp),
     .io_ifu_bus_clk_en(mem_ctl_io_ifu_bus_clk_en),
     .io_dma_mem_ctl_dma_iccm_req(mem_ctl_io_dma_mem_ctl_dma_iccm_req),
     .io_dma_mem_ctl_dma_mem_addr(mem_ctl_io_dma_mem_ctl_dma_mem_addr),
@@ -44832,10 +43663,7 @@ module ifu(
     .io_iccm_rd_data_ecc(mem_ctl_io_iccm_rd_data_ecc),
     .io_ic_rw_addr(mem_ctl_io_ic_rw_addr),
     .io_ic_tag_valid(mem_ctl_io_ic_tag_valid),
-    .io_ic_wr_en(mem_ctl_io_ic_wr_en),
     .io_ic_rd_en(mem_ctl_io_ic_rd_en),
-    .io_ic_wr_data_0(mem_ctl_io_ic_wr_data_0),
-    .io_ic_wr_data_1(mem_ctl_io_ic_wr_data_1),
     .io_ic_debug_wr_data(mem_ctl_io_ic_debug_wr_data),
     .io_ic_debug_addr(mem_ctl_io_ic_debug_addr),
     .io_ic_rd_data(mem_ctl_io_ic_rd_data),
@@ -44853,7 +43681,6 @@ module ifu(
     .io_ifu_fetch_val(mem_ctl_io_ifu_fetch_val),
     .io_ifu_ic_mb_empty(mem_ctl_io_ifu_ic_mb_empty),
     .io_ic_dma_active(mem_ctl_io_ic_dma_active),
-    .io_ic_write_stall(mem_ctl_io_ic_write_stall),
     .io_iccm_dma_ecc_error(mem_ctl_io_iccm_dma_ecc_error),
     .io_iccm_dma_rvalid(mem_ctl_io_iccm_dma_rvalid),
     .io_iccm_dma_rdata(mem_ctl_io_iccm_dma_rdata),
@@ -44978,7 +43805,6 @@ module ifu(
     .io_ifu_bp_hit_taken_f(ifc_ctl_io_ifu_bp_hit_taken_f),
     .io_ifu_bp_btb_target_f(ifc_ctl_io_ifu_bp_btb_target_f),
     .io_ic_dma_active(ifc_ctl_io_ic_dma_active),
-    .io_ic_write_stall(ifc_ctl_io_ic_write_stall),
     .io_dec_ifc_dec_tlu_flush_noredir_wb(ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb),
     .io_dec_ifc_dec_tlu_mrac_ff(ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff),
     .io_dec_ifc_ifu_pmu_fetch_stall(ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall),
@@ -45018,7 +43844,6 @@ module ifu(
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 93:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 93:27]
   assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 93:27]
@@ -45034,10 +43859,7 @@ module ifu(
   assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 107:19]
   assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 106:17]
   assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 106:17]
-  assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 106:17]
   assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 106:17]
-  assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 106:17]
-  assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 106:17]
   assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 106:17]
   assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 106:17]
   assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 106:17]
@@ -45047,9 +43869,7 @@ module ifu(
   assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 106:17]
   assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 106:17]
   assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22]
-  assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22]
   assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22]
-  assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22]
   assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25]
   assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22]
   assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21]
@@ -45079,11 +43899,6 @@ module ifu(
   assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 100:32]
   assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 101:33]
   assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 102:33]
-  assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 103:22]
-  assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 103:22]
-  assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 103:22]
-  assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 103:22]
-  assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 103:22]
   assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 104:29]
   assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 105:26]
   assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 105:26]
@@ -45171,7 +43986,6 @@ module ifu(
   assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 48:33]
   assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 49:34]
   assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 50:28]
-  assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 51:29]
   assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 46:22]
   assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 46:22]
   assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 52:22]
@@ -50482,7 +49296,6 @@ module csr_tlu(
   output        io_trigger_pkt_any_3_execute,
   output        io_trigger_pkt_any_3_m,
   output [31:0] io_trigger_pkt_any_3_tdata2,
-  input         io_ifu_pmu_bus_trxn,
   input         io_dma_iccm_stall_any,
   input         io_dma_dccm_stall_any,
   input         io_lsu_store_stall_any,
@@ -50535,7 +49348,6 @@ module csr_tlu(
   input         io_lsu_pmu_bus_error,
   input         io_ifu_pmu_bus_error,
   input         io_lsu_pmu_bus_misaligned,
-  input         io_lsu_pmu_bus_trxn,
   input  [70:0] io_ifu_ic_debug_rd_data,
   output [3:0]  io_dec_tlu_meipt,
   input  [3:0]  io_pic_pl,
@@ -50932,13 +49744,13 @@ module csr_tlu(
   wire  _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1451:68]
   wire  _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1452:71]
   wire  wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1452:42]
-  wire  _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68]
-  wire  wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1838:39]
-  wire  _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37]
+  wire  _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68]
+  wire  wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1838:39]
+  wire  _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37]
   reg  mpmc_b; // @[dec_tlu_ctl.scala 1848:44]
   wire  mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1851:10]
-  wire  _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62]
-  wire  mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1846:18]
+  wire  _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62]
+  wire  mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1846:18]
   wire  _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1455:28]
   wire  set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1455:39]
   wire  _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1458:5]
@@ -50973,24 +49785,24 @@ module csr_tlu(
   wire  _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1477:69]
   reg [30:0] _T_62; // @[lib.scala 374:16]
   reg [31:0] mdccmect; // @[lib.scala 374:16]
-  wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41]
-  wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58]
-  wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1898:61]
-  wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61]
-  wire  mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1898:94]
+  wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41]
+  wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58]
+  wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1898:61]
+  wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61]
+  wire  mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1898:94]
   reg [31:0] miccmect; // @[lib.scala 374:16]
-  wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40]
-  wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58]
-  wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1883:60]
-  wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60]
-  wire  miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1883:93]
+  wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40]
+  wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58]
+  wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1883:60]
+  wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60]
+  wire  miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1883:93]
   wire  _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1491:30]
   reg [31:0] micect; // @[lib.scala 374:16]
-  wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39]
-  wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58]
-  wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1868:57]
-  wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57]
-  wire  mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1868:88]
+  wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39]
+  wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58]
+  wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1868:57]
+  wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57]
+  wire  mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1868:88]
   wire  ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1491:46]
   wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58]
   wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58]
@@ -51182,423 +49994,425 @@ module csr_tlu(
   reg [8:0] mcgc; // @[lib.scala 374:16]
   wire  _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1744:68]
   reg [14:0] mfdc_int; // @[lib.scala 374:16]
-  wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1753:20]
-  wire  _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1753:75]
-  wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58]
-  wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58]
-  wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1754:20]
-  wire  _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1754:63]
-  wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58]
-  wire  _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77]
-  wire  _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1777:48]
-  wire  _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1777:87]
-  wire  _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113]
-  wire  _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68]
-  wire  _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71]
-  wire  _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1787:69]
-  wire  _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73]
-  wire  _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1788:71]
-  wire  _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73]
-  wire  _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1789:71]
-  wire  _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73]
-  wire  _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1790:71]
-  wire  _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73]
-  wire  _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1791:71]
-  wire  _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73]
-  wire  _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1792:71]
-  wire  _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73]
-  wire  _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1793:71]
-  wire  _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73]
-  wire  _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1794:71]
-  wire  _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73]
-  wire  _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1795:71]
-  wire  _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73]
-  wire  _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1796:71]
-  wire  _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73]
-  wire  _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1797:71]
-  wire  _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73]
-  wire  _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1798:70]
-  wire  _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73]
-  wire  _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1799:70]
-  wire  _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73]
-  wire  _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1800:70]
-  wire  _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73]
-  wire  _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1801:70]
-  wire  _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1802:70]
-  wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58]
-  wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58]
-  wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58]
-  wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58]
+  wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1757:19]
+  wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1758:19]
+  wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58]
+  wire  _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77]
+  wire  _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1777:48]
+  wire  _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1777:87]
+  wire  _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113]
+  wire  _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68]
+  wire  _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71]
+  wire  _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1787:69]
+  wire  _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73]
+  wire  _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1788:71]
+  wire  _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73]
+  wire  _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1789:71]
+  wire  _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73]
+  wire  _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1790:71]
+  wire  _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73]
+  wire  _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1791:71]
+  wire  _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73]
+  wire  _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1792:71]
+  wire  _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73]
+  wire  _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1793:71]
+  wire  _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73]
+  wire  _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1794:71]
+  wire  _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73]
+  wire  _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1795:71]
+  wire  _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73]
+  wire  _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1796:71]
+  wire  _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73]
+  wire  _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1797:71]
+  wire  _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73]
+  wire  _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1798:70]
+  wire  _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73]
+  wire  _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1799:70]
+  wire  _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73]
+  wire  _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1800:70]
+  wire  _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73]
+  wire  _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1801:70]
+  wire  _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1802:70]
+  wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58]
+  wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58]
+  wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58]
+  wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58]
   reg [31:0] mrac; // @[lib.scala 374:16]
-  wire  _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69]
-  wire  wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1815:40]
-  wire  _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59]
-  wire  _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1825:57]
-  wire  _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49]
-  wire  _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86]
-  wire  _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1827:84]
-  wire  _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111]
-  wire  mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1827:109]
+  wire  _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69]
+  wire  wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1815:40]
+  wire  _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59]
+  wire  _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1825:57]
+  wire  _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49]
+  wire  _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86]
+  wire  _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1827:84]
+  wire  _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111]
+  wire  mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1827:109]
   reg [31:0] mdseac; // @[lib.scala 374:16]
-  wire  _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30]
-  wire  _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57]
-  wire  _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1842:55]
-  wire  _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89]
-  wire  _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48]
-  wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19]
-  wire  _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70]
-  wire  wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1862:41]
-  wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58]
-  wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1863:23]
-  wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23]
-  wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58]
-  wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1863:13]
-  wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58]
-  wire  _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76]
-  wire  wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1877:47]
-  wire  _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70]
-  wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58]
-  wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1878:33]
-  wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58]
-  wire  _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48]
-  wire  _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76]
-  wire  wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1892:47]
-  wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58]
-  wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1893:33]
-  wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58]
-  wire  _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69]
-  wire  wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1908:40]
+  wire  _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30]
+  wire  _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57]
+  wire  _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1842:55]
+  wire  _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89]
+  wire  _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48]
+  wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19]
+  wire  _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70]
+  wire  wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1862:41]
+  wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58]
+  wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1863:23]
+  wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23]
+  wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58]
+  wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1863:13]
+  wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58]
+  wire  _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76]
+  wire  wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1877:47]
+  wire  _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70]
+  wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58]
+  wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1878:33]
+  wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58]
+  wire  _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48]
+  wire  _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76]
+  wire  wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1892:47]
+  wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58]
+  wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1893:33]
+  wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58]
+  wire  _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69]
+  wire  wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1908:40]
   reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1912:43]
-  wire  _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69]
-  wire  wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1921:40]
-  wire  _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43]
-  wire  _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1924:41]
-  wire  _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78]
-  wire  _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98]
-  wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58]
+  wire  _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69]
+  wire  wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1921:40]
+  wire  _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43]
+  wire  _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1924:41]
+  wire  _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78]
+  wire  _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98]
+  wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58]
   reg [1:0] mfdhs; // @[Reg.scala 27:20]
-  wire  _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71]
+  wire  _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71]
   reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20]
-  wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74]
-  wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71]
+  wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74]
+  wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71]
   wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1933:48]
-  wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1933:48]
-  wire  _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1933:87]
-  wire  _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69]
+  wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1933:48]
+  wire  _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1933:87]
+  wire  _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69]
   reg [21:0] meivt; // @[lib.scala 374:16]
-  wire  _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69]
-  wire  _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1992:40]
-  wire  wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83]
+  wire  _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69]
+  wire  _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1992:40]
+  wire  wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83]
   reg [7:0] meihap; // @[lib.scala 374:16]
-  wire  _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72]
-  wire  wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1965:43]
+  wire  _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72]
+  wire  wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1965:43]
   reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1968:46]
-  wire  _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73]
-  wire  _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1980:44]
-  wire  wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88]
+  wire  _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73]
+  wire  _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1980:44]
+  wire  wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88]
   reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1985:44]
-  wire  _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69]
-  wire  wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 2001:40]
+  wire  _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69]
+  wire  wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2001:40]
   reg [3:0] meipt; // @[dec_tlu_ctl.scala 2004:43]
-  wire  _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89]
-  wire  trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2032:66]
-  wire  _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31]
-  wire  _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2035:29]
-  wire  _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63]
-  wire  _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2035:61]
-  wire  _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98]
-  wire  _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2035:96]
-  wire  _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2036:46]
-  wire  _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2036:78]
-  wire  _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2037:75]
-  wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72]
-  wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72]
-  wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72]
-  wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72]
-  wire  _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46]
-  wire  _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98]
-  wire  wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2040:69]
-  wire  _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75]
-  wire  dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2046:59]
-  wire  _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59]
-  wire  _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78]
-  wire  enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2047:56]
+  wire  _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89]
+  wire  trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2032:66]
+  wire  _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31]
+  wire  _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2035:29]
+  wire  _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63]
+  wire  _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2035:61]
+  wire  _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98]
+  wire  _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2035:96]
+  wire  _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2036:46]
+  wire  _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2036:78]
+  wire  _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2037:75]
+  wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72]
+  wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72]
+  wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72]
+  wire  _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46]
+  wire  _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98]
+  wire  wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2040:69]
+  wire  _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75]
+  wire  dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2046:59]
+  wire  _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59]
+  wire  _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78]
+  wire  enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2047:56]
   wire  nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2049:48]
-  wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58]
-  wire  _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145]
-  wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58]
-  wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58]
-  wire  _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54]
-  wire  _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66]
-  reg [15:0] _T_701; // @[lib.scala 374:16]
-  wire  _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97]
-  wire  wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2061:68]
-  wire  _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67]
-  wire  dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2062:65]
-  wire  _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21]
-  wire  _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39]
-  wire  _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2066:37]
-  wire  _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56]
-  wire  _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49]
-  wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
-  wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72]
-  wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
-  wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72]
-  wire  _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36]
-  reg [30:0] _T_726; // @[lib.scala 374:16]
-  wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58]
-  wire  _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102]
+  wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58]
+  wire  _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145]
+  wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58]
+  wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58]
+  wire  _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54]
+  wire  _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66]
+  reg [15:0] _T_691; // @[lib.scala 374:16]
+  wire  _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97]
+  wire  wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2061:68]
+  wire  _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67]
+  wire  dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2062:65]
+  wire  _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21]
+  wire  _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39]
+  wire  _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2066:37]
+  wire  _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56]
+  wire  _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49]
+  wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72]
+  wire  _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36]
+  reg [30:0] _T_716; // @[lib.scala 374:16]
+  wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58]
+  wire  _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102]
   reg [16:0] dicawics; // @[lib.scala 374:16]
-  wire  _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100]
-  wire  wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2103:71]
+  wire  _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100]
+  wire  wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2103:71]
   reg [70:0] dicad0; // @[lib.scala 374:16]
-  wire  _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101]
-  wire  wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2116:72]
+  wire  _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101]
+  wire  wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2116:72]
   reg [31:0] dicad0h; // @[lib.scala 374:16]
-  wire  _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100]
-  wire  _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2128:71]
-  wire  _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78]
-  reg [6:0] _T_759; // @[Reg.scala 27:20]
-  wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58]
-  wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58]
-  wire  _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52]
-  wire  _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75]
-  wire  _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98]
-  wire  _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2160:96]
-  wire  _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149]
-  wire  _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104]
+  wire  _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100]
+  wire  _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2128:71]
+  wire  _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78]
+  reg [6:0] _T_749; // @[Reg.scala 27:20]
+  wire [31:0] dicad1 = {25'h0,_T_749}; // @[Cat.scala 29:58]
+  wire [38:0] _T_754 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58]
+  wire  _T_756 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52]
+  wire  _T_757 = _T_756 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75]
+  wire  _T_758 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98]
+  wire  _T_759 = _T_757 & _T_758; // @[dec_tlu_ctl.scala 2160:96]
+  wire  _T_761 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149]
+  wire  _T_764 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104]
   reg  icache_rd_valid_f; // @[dec_tlu_ctl.scala 2163:58]
   reg  icache_wr_valid_f; // @[dec_tlu_ctl.scala 2164:58]
-  wire  _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69]
-  wire  wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2175:40]
+  wire  _T_766 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69]
+  wire  wr_mtsel_r = io_dec_csr_wen_r_mod & _T_766; // @[dec_tlu_ctl.scala 2175:40]
   reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2178:43]
-  wire  tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2213:42]
-  wire  tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2215:44]
-  wire  _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46]
-  wire  tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69]
-  wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58]
-  wire  _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99]
-  wire  _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2223:70]
-  wire  _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121]
-  wire  _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2223:112]
-  wire  _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138]
-  wire  _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
-  wire  wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2223:135]
-  wire  _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121]
-  wire  _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2223:112]
-  wire  _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138]
-  wire  _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
-  wire  wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2223:135]
-  wire  _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121]
-  wire  _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2223:112]
-  wire  _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138]
-  wire  _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
-  wire  wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2223:135]
-  wire  _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121]
-  wire  _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2223:112]
-  wire  _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138]
-  wire  _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
-  wire  wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2223:135]
-  wire  _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139]
-  wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58]
-  wire  _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139]
-  wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58]
-  wire  _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139]
-  wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58]
-  wire  _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139]
-  wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58]
-  reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2226:74]
-  reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2226:74]
-  reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2226:74]
-  reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2226:74]
-  wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72]
-  wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72]
-  wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72]
-  wire  _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98]
-  wire  _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2243:69]
-  wire  _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2243:111]
-  wire  _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2243:111]
-  wire  _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2243:111]
-  wire  _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2243:111]
+  wire  tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2213:42]
+  wire  tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2215:44]
+  wire  _T_777 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46]
+  wire  tdata_action = _T_777 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69]
+  wire [9:0] tdata_wrdata_r = {_T_777,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58]
+  wire  _T_792 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99]
+  wire  _T_793 = io_dec_csr_wen_r_mod & _T_792; // @[dec_tlu_ctl.scala 2223:70]
+  wire  _T_794 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121]
+  wire  _T_795 = _T_793 & _T_794; // @[dec_tlu_ctl.scala 2223:112]
+  wire  _T_797 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138]
+  wire  _T_798 = _T_797 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
+  wire  wr_mtdata1_t_r_0 = _T_795 & _T_798; // @[dec_tlu_ctl.scala 2223:135]
+  wire  _T_803 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121]
+  wire  _T_804 = _T_793 & _T_803; // @[dec_tlu_ctl.scala 2223:112]
+  wire  _T_806 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138]
+  wire  _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
+  wire  wr_mtdata1_t_r_1 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2223:135]
+  wire  _T_812 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121]
+  wire  _T_813 = _T_793 & _T_812; // @[dec_tlu_ctl.scala 2223:112]
+  wire  _T_815 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138]
+  wire  _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
+  wire  wr_mtdata1_t_r_2 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2223:135]
+  wire  _T_821 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121]
+  wire  _T_822 = _T_793 & _T_821; // @[dec_tlu_ctl.scala 2223:112]
+  wire  _T_824 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138]
+  wire  _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170]
+  wire  wr_mtdata1_t_r_3 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2223:135]
+  wire  _T_831 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139]
+  wire [9:0] _T_834 = {io_mtdata1_t_0[9],_T_831,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58]
+  wire  _T_840 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139]
+  wire [9:0] _T_843 = {io_mtdata1_t_1[9],_T_840,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58]
+  wire  _T_849 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139]
+  wire [9:0] _T_852 = {io_mtdata1_t_2[9],_T_849,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58]
+  wire  _T_858 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139]
+  wire [9:0] _T_861 = {io_mtdata1_t_3[9],_T_858,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58]
+  reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2226:74]
+  reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2226:74]
+  reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2226:74]
+  reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2226:74]
+  wire [31:0] _T_881 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_896 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_911 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_926 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_927 = _T_794 ? _T_881 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_928 = _T_803 ? _T_896 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_929 = _T_812 ? _T_911 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_930 = _T_821 ? _T_926 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_931 = _T_927 | _T_928; // @[Mux.scala 27:72]
+  wire [31:0] _T_932 = _T_931 | _T_929; // @[Mux.scala 27:72]
+  wire [31:0] mtdata1_tsel_out = _T_932 | _T_930; // @[Mux.scala 27:72]
+  wire  _T_959 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98]
+  wire  _T_960 = io_dec_csr_wen_r_mod & _T_959; // @[dec_tlu_ctl.scala 2243:69]
+  wire  _T_962 = _T_960 & _T_794; // @[dec_tlu_ctl.scala 2243:111]
+  wire  _T_971 = _T_960 & _T_803; // @[dec_tlu_ctl.scala 2243:111]
+  wire  _T_980 = _T_960 & _T_812; // @[dec_tlu_ctl.scala 2243:111]
+  wire  _T_989 = _T_960 & _T_821; // @[dec_tlu_ctl.scala 2243:111]
   reg [31:0] mtdata2_t_0; // @[lib.scala 374:16]
   reg [31:0] mtdata2_t_1; // @[lib.scala 374:16]
   reg [31:0] mtdata2_t_2; // @[lib.scala 374:16]
   reg [31:0] mtdata2_t_3; // @[lib.scala 374:16]
-  wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72]
-  wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72]
-  wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72]
-  wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2268:59]
-  wire  _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24]
+  wire [31:0] _T_1006 = _T_794 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1007 = _T_803 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1008 = _T_812 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1009 = _T_821 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_1010 = _T_1006 | _T_1007; // @[Mux.scala 27:72]
+  wire [31:0] _T_1011 = _T_1010 | _T_1008; // @[Mux.scala 27:72]
+  wire [31:0] mtdata2_tsel_out = _T_1011 | _T_1009; // @[Mux.scala 27:72]
+  wire [3:0] _T_1014 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1014; // @[dec_tlu_ctl.scala 2268:59]
+  wire  _T_1016 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24]
   reg [9:0] mhpme3; // @[Reg.scala 27:20]
-  wire  _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
-  wire  _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
-  wire  _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
-  wire  _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
-  wire  _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96]
-  wire  _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2278:94]
-  wire  _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
-  wire  _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96]
-  wire  _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2279:94]
-  wire  _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2279:115]
-  wire  _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
-  wire  _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94]
-  wire  _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2280:115]
-  wire  _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
-  wire  _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
-  wire  _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
-  wire  _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
-  wire  _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91]
-  wire  _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
-  wire  _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105]
-  wire  _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
-  wire  _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91]
-  wire  _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
-  wire  _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91]
-  wire  _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
-  wire  _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100]
-  wire  _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
-  wire  _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101]
-  wire  _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
-  wire  _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89]
-  wire  _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
-  wire  _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89]
-  wire  _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
-  wire  _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89]
-  wire  _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
-  wire  _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89]
-  wire  _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
-  wire  _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89]
-  wire  _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
-  wire  _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89]
-  wire  _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
-  wire  _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89]
-  wire  _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
-  wire  _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89]
-  wire  _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
-  wire  _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89]
-  wire  _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
-  wire  _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89]
-  wire  _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122]
-  wire  _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2299:101]
-  wire  _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
-  wire  _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95]
-  wire  _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
-  wire  _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97]
-  wire  _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
-  wire  _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110]
-  wire  _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
-  wire  _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
-  wire  _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
-  wire  _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
-  wire  _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
-  wire  _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
-  wire  _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
-  wire  _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98]
-  wire  _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120]
-  wire  _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
-  wire  _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92]
-  wire  _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117]
-  wire  _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
-  wire  _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
-  wire  _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
-  wire  _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97]
-  wire  _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129]
-  wire  _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
-  wire  _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
-  wire  _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
-  wire  _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
-  wire  _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
-  wire  _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
-  wire  _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
-  wire  _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
-  wire  _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73]
-  wire  _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
-  wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113]
-  wire  _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2323:125]
-  wire  _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2323:98]
-  wire  _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
-  wire  _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91]
-  wire  _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
-  wire  _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94]
-  wire  _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
-  wire  _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94]
-  wire  _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
-  wire  _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
-  wire  _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
-  wire  _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
-  wire  _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
-  wire  _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
-  wire  _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
-  wire  _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72]
-  wire  _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72]
-  wire  _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72]
-  wire  _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
-  wire  _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
-  wire  _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
-  wire  _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72]
-  wire  _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72]
-  wire  _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72]
-  wire  _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72]
-  wire  _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72]
-  wire  _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72]
-  wire  _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72]
-  wire  _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72]
-  wire  _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72]
-  wire  _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72]
-  wire  _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72]
-  wire  _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72]
-  wire  _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72]
-  wire  _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72]
-  wire  _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72]
-  wire  _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72]
-  wire  _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72]
-  wire  _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72]
-  wire  _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72]
-  wire  _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
-  wire  _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
-  wire  _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
-  wire  _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72]
-  wire  _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72]
-  wire  _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72]
-  wire  _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
-  wire  _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72]
-  wire  _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
-  wire  _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72]
-  wire  _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72]
-  wire  _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72]
-  wire  _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72]
-  wire  _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72]
-  wire  _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
-  wire  _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
-  wire  _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
-  wire  _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
-  wire  _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
-  wire  _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72]
+  wire  _T_1017 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
+  wire  _T_1019 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
+  wire  _T_1021 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
+  wire  _T_1023 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
+  wire  _T_1025 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96]
+  wire  _T_1026 = io_tlu_i0_commit_cmt & _T_1025; // @[dec_tlu_ctl.scala 2278:94]
+  wire  _T_1027 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
+  wire  _T_1029 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96]
+  wire  _T_1030 = io_tlu_i0_commit_cmt & _T_1029; // @[dec_tlu_ctl.scala 2279:94]
+  wire  _T_1032 = _T_1030 & _T_1025; // @[dec_tlu_ctl.scala 2279:115]
+  wire  _T_1033 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
+  wire  _T_1035 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94]
+  wire  _T_1037 = _T_1035 & _T_1025; // @[dec_tlu_ctl.scala 2280:115]
+  wire  _T_1038 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
+  wire  _T_1040 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
+  wire  _T_1042 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
+  wire  _T_1044 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
+  wire  _T_1046 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91]
+  wire  _T_1047 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
+  wire  _T_1049 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105]
+  wire  _T_1050 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
+  wire  _T_1052 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91]
+  wire  _T_1053 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
+  wire  _T_1055 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91]
+  wire  _T_1056 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
+  wire  _T_1059 = _T_1052 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100]
+  wire  _T_1060 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
+  wire  _T_1064 = _T_1055 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101]
+  wire  _T_1065 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
+  wire  _T_1067 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89]
+  wire  _T_1068 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
+  wire  _T_1070 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89]
+  wire  _T_1071 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
+  wire  _T_1073 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89]
+  wire  _T_1074 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
+  wire  _T_1076 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89]
+  wire  _T_1077 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
+  wire  _T_1079 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89]
+  wire  _T_1080 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
+  wire  _T_1082 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89]
+  wire  _T_1083 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
+  wire  _T_1085 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89]
+  wire  _T_1086 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
+  wire  _T_1088 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89]
+  wire  _T_1089 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
+  wire  _T_1091 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89]
+  wire  _T_1092 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
+  wire  _T_1094 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89]
+  wire  _T_1095 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122]
+  wire  _T_1096 = _T_1094 | _T_1095; // @[dec_tlu_ctl.scala 2299:101]
+  wire  _T_1097 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
+  wire  _T_1099 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95]
+  wire  _T_1100 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
+  wire  _T_1102 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97]
+  wire  _T_1103 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
+  wire  _T_1105 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110]
+  wire  _T_1106 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
+  wire  _T_1110 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
+  wire  _T_1112 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
+  wire  _T_1114 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
+  wire  _T_1116 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
+  wire  _T_1118 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
+  wire  _T_1120 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
+  wire  _T_1122 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98]
+  wire  _T_1123 = _T_1122 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120]
+  wire  _T_1124 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
+  wire  _T_1126 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92]
+  wire  _T_1127 = _T_1126 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117]
+  wire  _T_1128 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
+  wire  _T_1130 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
+  wire  _T_1132 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1134 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97]
+  wire  _T_1135 = _T_1134 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129]
+  wire  _T_1140 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
+  wire  _T_1142 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
+  wire  _T_1144 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
+  wire  _T_1146 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
+  wire  _T_1148 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
+  wire  _T_1150 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
+  wire  _T_1154 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73]
+  wire  _T_1155 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
+  wire [5:0] _T_1162 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113]
+  wire  _T_1163 = |_T_1162; // @[dec_tlu_ctl.scala 2323:125]
+  wire  _T_1164 = _T_1154 & _T_1163; // @[dec_tlu_ctl.scala 2323:98]
+  wire  _T_1165 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
+  wire  _T_1167 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91]
+  wire  _T_1168 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
+  wire  _T_1170 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94]
+  wire  _T_1171 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
+  wire  _T_1173 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94]
+  wire  _T_1174 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
+  wire  _T_1176 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
+  wire  _T_1178 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
+  wire  _T_1180 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
+  wire  _T_1182 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
+  wire  _T_1185 = _T_1019 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
+  wire  _T_1186 = _T_1021 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
+  wire  _T_1187 = _T_1023 & _T_1026; // @[Mux.scala 27:72]
+  wire  _T_1188 = _T_1027 & _T_1032; // @[Mux.scala 27:72]
+  wire  _T_1189 = _T_1033 & _T_1037; // @[Mux.scala 27:72]
+  wire  _T_1190 = _T_1038 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
+  wire  _T_1191 = _T_1040 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
+  wire  _T_1192 = _T_1042 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
+  wire  _T_1193 = _T_1044 & _T_1046; // @[Mux.scala 27:72]
+  wire  _T_1194 = _T_1047 & _T_1049; // @[Mux.scala 27:72]
+  wire  _T_1195 = _T_1050 & _T_1052; // @[Mux.scala 27:72]
+  wire  _T_1196 = _T_1053 & _T_1055; // @[Mux.scala 27:72]
+  wire  _T_1197 = _T_1056 & _T_1059; // @[Mux.scala 27:72]
+  wire  _T_1198 = _T_1060 & _T_1064; // @[Mux.scala 27:72]
+  wire  _T_1199 = _T_1065 & _T_1067; // @[Mux.scala 27:72]
+  wire  _T_1200 = _T_1068 & _T_1070; // @[Mux.scala 27:72]
+  wire  _T_1201 = _T_1071 & _T_1073; // @[Mux.scala 27:72]
+  wire  _T_1202 = _T_1074 & _T_1076; // @[Mux.scala 27:72]
+  wire  _T_1203 = _T_1077 & _T_1079; // @[Mux.scala 27:72]
+  wire  _T_1204 = _T_1080 & _T_1082; // @[Mux.scala 27:72]
+  wire  _T_1205 = _T_1083 & _T_1085; // @[Mux.scala 27:72]
+  wire  _T_1206 = _T_1086 & _T_1088; // @[Mux.scala 27:72]
+  wire  _T_1207 = _T_1089 & _T_1091; // @[Mux.scala 27:72]
+  wire  _T_1208 = _T_1092 & _T_1096; // @[Mux.scala 27:72]
+  wire  _T_1209 = _T_1097 & _T_1099; // @[Mux.scala 27:72]
+  wire  _T_1210 = _T_1100 & _T_1102; // @[Mux.scala 27:72]
+  wire  _T_1211 = _T_1103 & _T_1105; // @[Mux.scala 27:72]
+  wire  _T_1212 = _T_1106 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
+  wire  _T_1214 = _T_1110 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
+  wire  _T_1215 = _T_1112 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
+  wire  _T_1216 = _T_1114 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1217 = _T_1116 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1218 = _T_1118 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1219 = _T_1120 & _T_1123; // @[Mux.scala 27:72]
+  wire  _T_1220 = _T_1124 & _T_1127; // @[Mux.scala 27:72]
+  wire  _T_1221 = _T_1128 & io_take_ext_int; // @[Mux.scala 27:72]
+  wire  _T_1222 = _T_1130 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
+  wire  _T_1223 = _T_1132 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1226 = _T_1140 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
+  wire  _T_1227 = _T_1142 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1228 = _T_1144 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1229 = _T_1146 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1230 = _T_1148 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1231 = _T_1150 & _T_1154; // @[Mux.scala 27:72]
+  wire  _T_1232 = _T_1155 & _T_1164; // @[Mux.scala 27:72]
+  wire  _T_1233 = _T_1165 & _T_1167; // @[Mux.scala 27:72]
+  wire  _T_1234 = _T_1168 & _T_1170; // @[Mux.scala 27:72]
+  wire  _T_1235 = _T_1171 & _T_1173; // @[Mux.scala 27:72]
+  wire  _T_1236 = _T_1174 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
+  wire  _T_1237 = _T_1176 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
+  wire  _T_1238 = _T_1178 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
+  wire  _T_1239 = _T_1180 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
+  wire  _T_1240 = _T_1182 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
+  wire  _T_1241 = _T_1017 | _T_1185; // @[Mux.scala 27:72]
+  wire  _T_1242 = _T_1241 | _T_1186; // @[Mux.scala 27:72]
+  wire  _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72]
+  wire  _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72]
+  wire  _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72]
+  wire  _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72]
+  wire  _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72]
+  wire  _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72]
+  wire  _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72]
+  wire  _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72]
+  wire  _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72]
   wire  _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72]
   wire  _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72]
   wire  _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72]
@@ -51616,7 +50430,7 @@ module csr_tlu(
   wire  _T_1266 = _T_1265 | _T_1210; // @[Mux.scala 27:72]
   wire  _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72]
   wire  _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72]
-  wire  _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72]
+  wire  _T_1269 = _T_1268 | _T_1192; // @[Mux.scala 27:72]
   wire  _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72]
   wire  _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72]
   wire  _T_1272 = _T_1271 | _T_1216; // @[Mux.scala 27:72]
@@ -51626,10 +50440,8 @@ module csr_tlu(
   wire  _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72]
   wire  _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72]
   wire  _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72]
-  wire  _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72]
-  wire  _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72]
-  wire  _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72]
-  wire  _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72]
+  wire  _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72]
+  wire  _T_1282 = _T_1279 | _T_1226; // @[Mux.scala 27:72]
   wire  _T_1283 = _T_1282 | _T_1227; // @[Mux.scala 27:72]
   wire  _T_1284 = _T_1283 | _T_1228; // @[Mux.scala 27:72]
   wire  _T_1285 = _T_1284 | _T_1229; // @[Mux.scala 27:72]
@@ -51644,131 +50456,127 @@ module csr_tlu(
   wire  _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72]
   wire  _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72]
   wire  _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72]
-  wire  _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72]
-  wire  _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72]
-  wire  _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72]
-  wire  _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72]
-  wire  _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72]
-  wire  _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72]
-  wire  _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72]
-  wire  _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72]
-  wire  _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72]
-  wire  _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72]
-  wire  mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2274:44]
-  wire  _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24]
+  wire  mhpmc_inc_r_0 = _T_1016 & _T_1296; // @[dec_tlu_ctl.scala 2274:44]
+  wire  _T_1300 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24]
   reg [9:0] mhpme4; // @[Reg.scala 27:20]
-  wire  _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
-  wire  _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
-  wire  _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
-  wire  _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
-  wire  _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
-  wire  _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
-  wire  _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
-  wire  _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
-  wire  _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
-  wire  _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
-  wire  _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
-  wire  _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
-  wire  _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
-  wire  _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
-  wire  _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
-  wire  _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
-  wire  _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
-  wire  _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
-  wire  _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
-  wire  _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
-  wire  _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
-  wire  _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
-  wire  _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
-  wire  _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
-  wire  _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
-  wire  _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
-  wire  _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
-  wire  _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
-  wire  _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
-  wire  _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
-  wire  _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
-  wire  _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
-  wire  _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
-  wire  _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
-  wire  _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
-  wire  _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
-  wire  _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
-  wire  _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
-  wire  _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
-  wire  _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
-  wire  _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
-  wire  _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
-  wire  _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
-  wire  _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
-  wire  _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
-  wire  _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
-  wire  _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
-  wire  _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
-  wire  _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
-  wire  _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
-  wire  _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
-  wire  _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
-  wire  _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
-  wire  _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
-  wire  _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
-  wire  _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
-  wire  _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
-  wire  _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
-  wire  _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72]
-  wire  _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72]
-  wire  _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72]
-  wire  _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
-  wire  _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
-  wire  _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
-  wire  _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72]
-  wire  _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72]
-  wire  _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72]
-  wire  _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72]
-  wire  _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72]
-  wire  _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72]
-  wire  _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72]
-  wire  _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72]
-  wire  _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72]
-  wire  _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72]
-  wire  _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72]
-  wire  _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72]
-  wire  _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72]
-  wire  _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72]
-  wire  _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72]
-  wire  _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72]
-  wire  _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72]
-  wire  _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72]
-  wire  _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72]
-  wire  _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
-  wire  _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
-  wire  _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
-  wire  _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72]
-  wire  _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72]
-  wire  _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72]
-  wire  _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
-  wire  _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72]
-  wire  _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
-  wire  _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72]
-  wire  _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72]
-  wire  _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72]
-  wire  _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72]
-  wire  _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72]
-  wire  _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
-  wire  _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
-  wire  _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
-  wire  _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
-  wire  _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
-  wire  _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72]
+  wire  _T_1301 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
+  wire  _T_1303 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
+  wire  _T_1305 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
+  wire  _T_1307 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
+  wire  _T_1311 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
+  wire  _T_1317 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
+  wire  _T_1322 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
+  wire  _T_1324 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
+  wire  _T_1326 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
+  wire  _T_1328 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
+  wire  _T_1331 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
+  wire  _T_1334 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
+  wire  _T_1337 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
+  wire  _T_1340 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
+  wire  _T_1344 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
+  wire  _T_1349 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
+  wire  _T_1352 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
+  wire  _T_1355 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
+  wire  _T_1358 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
+  wire  _T_1361 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
+  wire  _T_1364 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
+  wire  _T_1367 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
+  wire  _T_1370 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
+  wire  _T_1373 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
+  wire  _T_1376 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
+  wire  _T_1381 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
+  wire  _T_1384 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
+  wire  _T_1387 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
+  wire  _T_1390 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
+  wire  _T_1394 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
+  wire  _T_1396 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
+  wire  _T_1398 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
+  wire  _T_1400 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
+  wire  _T_1402 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
+  wire  _T_1404 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
+  wire  _T_1408 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
+  wire  _T_1412 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
+  wire  _T_1414 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
+  wire  _T_1416 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1424 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
+  wire  _T_1426 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
+  wire  _T_1428 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
+  wire  _T_1430 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
+  wire  _T_1432 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
+  wire  _T_1434 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
+  wire  _T_1439 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
+  wire  _T_1449 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
+  wire  _T_1452 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
+  wire  _T_1455 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
+  wire  _T_1458 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
+  wire  _T_1460 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
+  wire  _T_1462 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
+  wire  _T_1464 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
+  wire  _T_1466 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
+  wire  _T_1469 = _T_1303 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
+  wire  _T_1470 = _T_1305 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
+  wire  _T_1471 = _T_1307 & _T_1026; // @[Mux.scala 27:72]
+  wire  _T_1472 = _T_1311 & _T_1032; // @[Mux.scala 27:72]
+  wire  _T_1473 = _T_1317 & _T_1037; // @[Mux.scala 27:72]
+  wire  _T_1474 = _T_1322 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
+  wire  _T_1475 = _T_1324 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
+  wire  _T_1476 = _T_1326 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
+  wire  _T_1477 = _T_1328 & _T_1046; // @[Mux.scala 27:72]
+  wire  _T_1478 = _T_1331 & _T_1049; // @[Mux.scala 27:72]
+  wire  _T_1479 = _T_1334 & _T_1052; // @[Mux.scala 27:72]
+  wire  _T_1480 = _T_1337 & _T_1055; // @[Mux.scala 27:72]
+  wire  _T_1481 = _T_1340 & _T_1059; // @[Mux.scala 27:72]
+  wire  _T_1482 = _T_1344 & _T_1064; // @[Mux.scala 27:72]
+  wire  _T_1483 = _T_1349 & _T_1067; // @[Mux.scala 27:72]
+  wire  _T_1484 = _T_1352 & _T_1070; // @[Mux.scala 27:72]
+  wire  _T_1485 = _T_1355 & _T_1073; // @[Mux.scala 27:72]
+  wire  _T_1486 = _T_1358 & _T_1076; // @[Mux.scala 27:72]
+  wire  _T_1487 = _T_1361 & _T_1079; // @[Mux.scala 27:72]
+  wire  _T_1488 = _T_1364 & _T_1082; // @[Mux.scala 27:72]
+  wire  _T_1489 = _T_1367 & _T_1085; // @[Mux.scala 27:72]
+  wire  _T_1490 = _T_1370 & _T_1088; // @[Mux.scala 27:72]
+  wire  _T_1491 = _T_1373 & _T_1091; // @[Mux.scala 27:72]
+  wire  _T_1492 = _T_1376 & _T_1096; // @[Mux.scala 27:72]
+  wire  _T_1493 = _T_1381 & _T_1099; // @[Mux.scala 27:72]
+  wire  _T_1494 = _T_1384 & _T_1102; // @[Mux.scala 27:72]
+  wire  _T_1495 = _T_1387 & _T_1105; // @[Mux.scala 27:72]
+  wire  _T_1496 = _T_1390 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
+  wire  _T_1498 = _T_1394 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
+  wire  _T_1499 = _T_1396 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
+  wire  _T_1500 = _T_1398 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1501 = _T_1400 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1502 = _T_1402 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1503 = _T_1404 & _T_1123; // @[Mux.scala 27:72]
+  wire  _T_1504 = _T_1408 & _T_1127; // @[Mux.scala 27:72]
+  wire  _T_1505 = _T_1412 & io_take_ext_int; // @[Mux.scala 27:72]
+  wire  _T_1506 = _T_1414 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
+  wire  _T_1507 = _T_1416 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1510 = _T_1424 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
+  wire  _T_1511 = _T_1426 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1512 = _T_1428 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1513 = _T_1430 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1514 = _T_1432 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1515 = _T_1434 & _T_1154; // @[Mux.scala 27:72]
+  wire  _T_1516 = _T_1439 & _T_1164; // @[Mux.scala 27:72]
+  wire  _T_1517 = _T_1449 & _T_1167; // @[Mux.scala 27:72]
+  wire  _T_1518 = _T_1452 & _T_1170; // @[Mux.scala 27:72]
+  wire  _T_1519 = _T_1455 & _T_1173; // @[Mux.scala 27:72]
+  wire  _T_1520 = _T_1458 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
+  wire  _T_1521 = _T_1460 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
+  wire  _T_1522 = _T_1462 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
+  wire  _T_1523 = _T_1464 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
+  wire  _T_1524 = _T_1466 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
+  wire  _T_1525 = _T_1301 | _T_1469; // @[Mux.scala 27:72]
+  wire  _T_1526 = _T_1525 | _T_1470; // @[Mux.scala 27:72]
+  wire  _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72]
+  wire  _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72]
+  wire  _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72]
+  wire  _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72]
+  wire  _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72]
+  wire  _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72]
+  wire  _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72]
+  wire  _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72]
+  wire  _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72]
   wire  _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72]
   wire  _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72]
   wire  _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72]
@@ -51786,7 +50594,7 @@ module csr_tlu(
   wire  _T_1550 = _T_1549 | _T_1494; // @[Mux.scala 27:72]
   wire  _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72]
   wire  _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72]
-  wire  _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72]
+  wire  _T_1553 = _T_1552 | _T_1476; // @[Mux.scala 27:72]
   wire  _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72]
   wire  _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72]
   wire  _T_1556 = _T_1555 | _T_1500; // @[Mux.scala 27:72]
@@ -51796,10 +50604,8 @@ module csr_tlu(
   wire  _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72]
   wire  _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72]
   wire  _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72]
-  wire  _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72]
-  wire  _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72]
-  wire  _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72]
-  wire  _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72]
+  wire  _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72]
+  wire  _T_1566 = _T_1563 | _T_1510; // @[Mux.scala 27:72]
   wire  _T_1567 = _T_1566 | _T_1511; // @[Mux.scala 27:72]
   wire  _T_1568 = _T_1567 | _T_1512; // @[Mux.scala 27:72]
   wire  _T_1569 = _T_1568 | _T_1513; // @[Mux.scala 27:72]
@@ -51814,131 +50620,127 @@ module csr_tlu(
   wire  _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72]
   wire  _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72]
   wire  _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72]
-  wire  _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72]
-  wire  _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72]
-  wire  _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72]
-  wire  _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72]
-  wire  _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72]
-  wire  _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72]
-  wire  _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72]
-  wire  _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72]
-  wire  _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72]
-  wire  _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72]
-  wire  mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2274:44]
-  wire  _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24]
+  wire  mhpmc_inc_r_1 = _T_1300 & _T_1580; // @[dec_tlu_ctl.scala 2274:44]
+  wire  _T_1584 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24]
   reg [9:0] mhpme5; // @[Reg.scala 27:20]
-  wire  _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
-  wire  _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
-  wire  _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
-  wire  _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
-  wire  _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
-  wire  _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
-  wire  _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
-  wire  _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
-  wire  _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
-  wire  _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
-  wire  _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
-  wire  _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
-  wire  _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
-  wire  _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
-  wire  _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
-  wire  _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
-  wire  _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
-  wire  _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
-  wire  _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
-  wire  _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
-  wire  _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
-  wire  _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
-  wire  _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
-  wire  _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
-  wire  _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
-  wire  _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
-  wire  _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
-  wire  _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
-  wire  _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
-  wire  _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
-  wire  _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
-  wire  _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
-  wire  _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
-  wire  _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
-  wire  _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
-  wire  _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
-  wire  _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
-  wire  _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
-  wire  _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
-  wire  _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
-  wire  _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
-  wire  _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
-  wire  _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
-  wire  _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
-  wire  _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
-  wire  _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
-  wire  _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
-  wire  _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
-  wire  _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
-  wire  _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
-  wire  _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
-  wire  _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
-  wire  _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
-  wire  _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
-  wire  _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
-  wire  _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
-  wire  _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
-  wire  _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
-  wire  _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72]
-  wire  _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72]
-  wire  _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72]
-  wire  _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
-  wire  _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
-  wire  _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
-  wire  _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72]
-  wire  _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72]
-  wire  _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72]
-  wire  _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72]
-  wire  _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72]
-  wire  _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72]
-  wire  _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72]
-  wire  _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72]
-  wire  _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72]
-  wire  _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72]
-  wire  _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72]
-  wire  _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72]
-  wire  _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72]
-  wire  _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72]
-  wire  _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72]
-  wire  _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72]
-  wire  _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72]
-  wire  _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72]
-  wire  _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72]
-  wire  _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
-  wire  _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
-  wire  _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
-  wire  _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72]
-  wire  _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72]
-  wire  _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72]
-  wire  _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
-  wire  _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72]
-  wire  _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
-  wire  _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72]
-  wire  _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72]
-  wire  _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72]
-  wire  _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72]
-  wire  _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72]
-  wire  _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
-  wire  _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
-  wire  _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
-  wire  _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
-  wire  _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
-  wire  _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72]
+  wire  _T_1585 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
+  wire  _T_1587 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
+  wire  _T_1589 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
+  wire  _T_1591 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
+  wire  _T_1595 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
+  wire  _T_1601 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
+  wire  _T_1606 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
+  wire  _T_1608 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
+  wire  _T_1610 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
+  wire  _T_1612 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
+  wire  _T_1615 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
+  wire  _T_1618 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
+  wire  _T_1621 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
+  wire  _T_1624 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
+  wire  _T_1628 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
+  wire  _T_1633 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
+  wire  _T_1636 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
+  wire  _T_1639 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
+  wire  _T_1642 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
+  wire  _T_1645 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
+  wire  _T_1648 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
+  wire  _T_1651 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
+  wire  _T_1654 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
+  wire  _T_1657 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
+  wire  _T_1660 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
+  wire  _T_1665 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
+  wire  _T_1668 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
+  wire  _T_1671 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
+  wire  _T_1674 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
+  wire  _T_1678 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
+  wire  _T_1680 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
+  wire  _T_1682 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
+  wire  _T_1684 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
+  wire  _T_1686 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
+  wire  _T_1688 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
+  wire  _T_1692 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
+  wire  _T_1696 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
+  wire  _T_1698 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
+  wire  _T_1700 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1708 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
+  wire  _T_1710 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
+  wire  _T_1712 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
+  wire  _T_1714 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
+  wire  _T_1716 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
+  wire  _T_1718 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
+  wire  _T_1723 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
+  wire  _T_1733 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
+  wire  _T_1736 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
+  wire  _T_1739 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
+  wire  _T_1742 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
+  wire  _T_1744 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
+  wire  _T_1746 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
+  wire  _T_1748 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
+  wire  _T_1750 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
+  wire  _T_1753 = _T_1587 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
+  wire  _T_1754 = _T_1589 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
+  wire  _T_1755 = _T_1591 & _T_1026; // @[Mux.scala 27:72]
+  wire  _T_1756 = _T_1595 & _T_1032; // @[Mux.scala 27:72]
+  wire  _T_1757 = _T_1601 & _T_1037; // @[Mux.scala 27:72]
+  wire  _T_1758 = _T_1606 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
+  wire  _T_1759 = _T_1608 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
+  wire  _T_1760 = _T_1610 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
+  wire  _T_1761 = _T_1612 & _T_1046; // @[Mux.scala 27:72]
+  wire  _T_1762 = _T_1615 & _T_1049; // @[Mux.scala 27:72]
+  wire  _T_1763 = _T_1618 & _T_1052; // @[Mux.scala 27:72]
+  wire  _T_1764 = _T_1621 & _T_1055; // @[Mux.scala 27:72]
+  wire  _T_1765 = _T_1624 & _T_1059; // @[Mux.scala 27:72]
+  wire  _T_1766 = _T_1628 & _T_1064; // @[Mux.scala 27:72]
+  wire  _T_1767 = _T_1633 & _T_1067; // @[Mux.scala 27:72]
+  wire  _T_1768 = _T_1636 & _T_1070; // @[Mux.scala 27:72]
+  wire  _T_1769 = _T_1639 & _T_1073; // @[Mux.scala 27:72]
+  wire  _T_1770 = _T_1642 & _T_1076; // @[Mux.scala 27:72]
+  wire  _T_1771 = _T_1645 & _T_1079; // @[Mux.scala 27:72]
+  wire  _T_1772 = _T_1648 & _T_1082; // @[Mux.scala 27:72]
+  wire  _T_1773 = _T_1651 & _T_1085; // @[Mux.scala 27:72]
+  wire  _T_1774 = _T_1654 & _T_1088; // @[Mux.scala 27:72]
+  wire  _T_1775 = _T_1657 & _T_1091; // @[Mux.scala 27:72]
+  wire  _T_1776 = _T_1660 & _T_1096; // @[Mux.scala 27:72]
+  wire  _T_1777 = _T_1665 & _T_1099; // @[Mux.scala 27:72]
+  wire  _T_1778 = _T_1668 & _T_1102; // @[Mux.scala 27:72]
+  wire  _T_1779 = _T_1671 & _T_1105; // @[Mux.scala 27:72]
+  wire  _T_1780 = _T_1674 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
+  wire  _T_1782 = _T_1678 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
+  wire  _T_1783 = _T_1680 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
+  wire  _T_1784 = _T_1682 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1785 = _T_1684 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1786 = _T_1686 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_1787 = _T_1688 & _T_1123; // @[Mux.scala 27:72]
+  wire  _T_1788 = _T_1692 & _T_1127; // @[Mux.scala 27:72]
+  wire  _T_1789 = _T_1696 & io_take_ext_int; // @[Mux.scala 27:72]
+  wire  _T_1790 = _T_1698 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
+  wire  _T_1791 = _T_1700 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_1794 = _T_1708 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
+  wire  _T_1795 = _T_1710 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1796 = _T_1712 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_1797 = _T_1714 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1798 = _T_1716 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_1799 = _T_1718 & _T_1154; // @[Mux.scala 27:72]
+  wire  _T_1800 = _T_1723 & _T_1164; // @[Mux.scala 27:72]
+  wire  _T_1801 = _T_1733 & _T_1167; // @[Mux.scala 27:72]
+  wire  _T_1802 = _T_1736 & _T_1170; // @[Mux.scala 27:72]
+  wire  _T_1803 = _T_1739 & _T_1173; // @[Mux.scala 27:72]
+  wire  _T_1804 = _T_1742 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
+  wire  _T_1805 = _T_1744 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
+  wire  _T_1806 = _T_1746 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
+  wire  _T_1807 = _T_1748 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
+  wire  _T_1808 = _T_1750 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
+  wire  _T_1809 = _T_1585 | _T_1753; // @[Mux.scala 27:72]
+  wire  _T_1810 = _T_1809 | _T_1754; // @[Mux.scala 27:72]
+  wire  _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72]
+  wire  _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72]
+  wire  _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72]
+  wire  _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72]
+  wire  _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72]
+  wire  _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72]
+  wire  _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72]
+  wire  _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72]
+  wire  _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72]
   wire  _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72]
   wire  _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72]
   wire  _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72]
@@ -51956,7 +50758,7 @@ module csr_tlu(
   wire  _T_1834 = _T_1833 | _T_1778; // @[Mux.scala 27:72]
   wire  _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72]
   wire  _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72]
-  wire  _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72]
+  wire  _T_1837 = _T_1836 | _T_1760; // @[Mux.scala 27:72]
   wire  _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72]
   wire  _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72]
   wire  _T_1840 = _T_1839 | _T_1784; // @[Mux.scala 27:72]
@@ -51966,10 +50768,8 @@ module csr_tlu(
   wire  _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72]
   wire  _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72]
   wire  _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72]
-  wire  _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72]
-  wire  _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72]
-  wire  _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72]
-  wire  _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72]
+  wire  _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72]
+  wire  _T_1850 = _T_1847 | _T_1794; // @[Mux.scala 27:72]
   wire  _T_1851 = _T_1850 | _T_1795; // @[Mux.scala 27:72]
   wire  _T_1852 = _T_1851 | _T_1796; // @[Mux.scala 27:72]
   wire  _T_1853 = _T_1852 | _T_1797; // @[Mux.scala 27:72]
@@ -51984,131 +50784,127 @@ module csr_tlu(
   wire  _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72]
   wire  _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72]
   wire  _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72]
-  wire  _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72]
-  wire  _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72]
-  wire  _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72]
-  wire  _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72]
-  wire  _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72]
-  wire  _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72]
-  wire  _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72]
-  wire  _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72]
-  wire  _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72]
-  wire  _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72]
-  wire  mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2274:44]
-  wire  _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24]
+  wire  mhpmc_inc_r_2 = _T_1584 & _T_1864; // @[dec_tlu_ctl.scala 2274:44]
+  wire  _T_1868 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24]
   reg [9:0] mhpme6; // @[Reg.scala 27:20]
-  wire  _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
-  wire  _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
-  wire  _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
-  wire  _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
-  wire  _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
-  wire  _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
-  wire  _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
-  wire  _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
-  wire  _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
-  wire  _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
-  wire  _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
-  wire  _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
-  wire  _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
-  wire  _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
-  wire  _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
-  wire  _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
-  wire  _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
-  wire  _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
-  wire  _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
-  wire  _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
-  wire  _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
-  wire  _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
-  wire  _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
-  wire  _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
-  wire  _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
-  wire  _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
-  wire  _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
-  wire  _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
-  wire  _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
-  wire  _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
-  wire  _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
-  wire  _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
-  wire  _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
-  wire  _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
-  wire  _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
-  wire  _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
-  wire  _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
-  wire  _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
-  wire  _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
-  wire  _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34]
-  wire  _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34]
-  wire  _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
-  wire  _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
-  wire  _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
-  wire  _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
-  wire  _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
-  wire  _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
-  wire  _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
-  wire  _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
-  wire  _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
-  wire  _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
-  wire  _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
-  wire  _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
-  wire  _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
-  wire  _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
-  wire  _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
-  wire  _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
-  wire  _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
-  wire  _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72]
-  wire  _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72]
-  wire  _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72]
-  wire  _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
-  wire  _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
-  wire  _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
-  wire  _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72]
-  wire  _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72]
-  wire  _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72]
-  wire  _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72]
-  wire  _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72]
-  wire  _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72]
-  wire  _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72]
-  wire  _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72]
-  wire  _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72]
-  wire  _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72]
-  wire  _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72]
-  wire  _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72]
-  wire  _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72]
-  wire  _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72]
-  wire  _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72]
-  wire  _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72]
-  wire  _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72]
-  wire  _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72]
-  wire  _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72]
-  wire  _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
-  wire  _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
-  wire  _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
-  wire  _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
-  wire  _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
-  wire  _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72]
-  wire  _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72]
-  wire  _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72]
-  wire  _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
-  wire  _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72]
-  wire  _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72]
-  wire  _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
-  wire  _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
-  wire  _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
-  wire  _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72]
-  wire  _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72]
-  wire  _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72]
-  wire  _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72]
-  wire  _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72]
-  wire  _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
-  wire  _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
-  wire  _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
-  wire  _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
-  wire  _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
-  wire  _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72]
+  wire  _T_1869 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34]
+  wire  _T_1871 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34]
+  wire  _T_1873 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34]
+  wire  _T_1875 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34]
+  wire  _T_1879 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34]
+  wire  _T_1885 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34]
+  wire  _T_1890 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34]
+  wire  _T_1892 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34]
+  wire  _T_1894 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34]
+  wire  _T_1896 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34]
+  wire  _T_1899 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34]
+  wire  _T_1902 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34]
+  wire  _T_1905 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34]
+  wire  _T_1908 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34]
+  wire  _T_1912 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34]
+  wire  _T_1917 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34]
+  wire  _T_1920 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34]
+  wire  _T_1923 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34]
+  wire  _T_1926 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34]
+  wire  _T_1929 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34]
+  wire  _T_1932 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34]
+  wire  _T_1935 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34]
+  wire  _T_1938 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34]
+  wire  _T_1941 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34]
+  wire  _T_1944 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34]
+  wire  _T_1949 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34]
+  wire  _T_1952 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34]
+  wire  _T_1955 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34]
+  wire  _T_1958 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34]
+  wire  _T_1962 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34]
+  wire  _T_1964 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34]
+  wire  _T_1966 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34]
+  wire  _T_1968 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34]
+  wire  _T_1970 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34]
+  wire  _T_1972 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34]
+  wire  _T_1976 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34]
+  wire  _T_1980 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34]
+  wire  _T_1982 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34]
+  wire  _T_1984 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34]
+  wire  _T_1992 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34]
+  wire  _T_1994 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34]
+  wire  _T_1996 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34]
+  wire  _T_1998 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34]
+  wire  _T_2000 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34]
+  wire  _T_2002 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34]
+  wire  _T_2007 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34]
+  wire  _T_2017 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34]
+  wire  _T_2020 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34]
+  wire  _T_2023 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34]
+  wire  _T_2026 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34]
+  wire  _T_2028 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34]
+  wire  _T_2030 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34]
+  wire  _T_2032 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34]
+  wire  _T_2034 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34]
+  wire  _T_2037 = _T_1871 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72]
+  wire  _T_2038 = _T_1873 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72]
+  wire  _T_2039 = _T_1875 & _T_1026; // @[Mux.scala 27:72]
+  wire  _T_2040 = _T_1879 & _T_1032; // @[Mux.scala 27:72]
+  wire  _T_2041 = _T_1885 & _T_1037; // @[Mux.scala 27:72]
+  wire  _T_2042 = _T_1890 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72]
+  wire  _T_2043 = _T_1892 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72]
+  wire  _T_2044 = _T_1894 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72]
+  wire  _T_2045 = _T_1896 & _T_1046; // @[Mux.scala 27:72]
+  wire  _T_2046 = _T_1899 & _T_1049; // @[Mux.scala 27:72]
+  wire  _T_2047 = _T_1902 & _T_1052; // @[Mux.scala 27:72]
+  wire  _T_2048 = _T_1905 & _T_1055; // @[Mux.scala 27:72]
+  wire  _T_2049 = _T_1908 & _T_1059; // @[Mux.scala 27:72]
+  wire  _T_2050 = _T_1912 & _T_1064; // @[Mux.scala 27:72]
+  wire  _T_2051 = _T_1917 & _T_1067; // @[Mux.scala 27:72]
+  wire  _T_2052 = _T_1920 & _T_1070; // @[Mux.scala 27:72]
+  wire  _T_2053 = _T_1923 & _T_1073; // @[Mux.scala 27:72]
+  wire  _T_2054 = _T_1926 & _T_1076; // @[Mux.scala 27:72]
+  wire  _T_2055 = _T_1929 & _T_1079; // @[Mux.scala 27:72]
+  wire  _T_2056 = _T_1932 & _T_1082; // @[Mux.scala 27:72]
+  wire  _T_2057 = _T_1935 & _T_1085; // @[Mux.scala 27:72]
+  wire  _T_2058 = _T_1938 & _T_1088; // @[Mux.scala 27:72]
+  wire  _T_2059 = _T_1941 & _T_1091; // @[Mux.scala 27:72]
+  wire  _T_2060 = _T_1944 & _T_1096; // @[Mux.scala 27:72]
+  wire  _T_2061 = _T_1949 & _T_1099; // @[Mux.scala 27:72]
+  wire  _T_2062 = _T_1952 & _T_1102; // @[Mux.scala 27:72]
+  wire  _T_2063 = _T_1955 & _T_1105; // @[Mux.scala 27:72]
+  wire  _T_2064 = _T_1958 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72]
+  wire  _T_2066 = _T_1962 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72]
+  wire  _T_2067 = _T_1964 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72]
+  wire  _T_2068 = _T_1966 & io_lsu_store_stall_any; // @[Mux.scala 27:72]
+  wire  _T_2069 = _T_1968 & io_dma_dccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_2070 = _T_1970 & io_dma_iccm_stall_any; // @[Mux.scala 27:72]
+  wire  _T_2071 = _T_1972 & _T_1123; // @[Mux.scala 27:72]
+  wire  _T_2072 = _T_1976 & _T_1127; // @[Mux.scala 27:72]
+  wire  _T_2073 = _T_1980 & io_take_ext_int; // @[Mux.scala 27:72]
+  wire  _T_2074 = _T_1982 & io_tlu_flush_lower_r; // @[Mux.scala 27:72]
+  wire  _T_2075 = _T_1984 & _T_1135; // @[Mux.scala 27:72]
+  wire  _T_2078 = _T_1992 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72]
+  wire  _T_2079 = _T_1994 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_2080 = _T_1996 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72]
+  wire  _T_2081 = _T_1998 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_2082 = _T_2000 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72]
+  wire  _T_2083 = _T_2002 & _T_1154; // @[Mux.scala 27:72]
+  wire  _T_2084 = _T_2007 & _T_1164; // @[Mux.scala 27:72]
+  wire  _T_2085 = _T_2017 & _T_1167; // @[Mux.scala 27:72]
+  wire  _T_2086 = _T_2020 & _T_1170; // @[Mux.scala 27:72]
+  wire  _T_2087 = _T_2023 & _T_1173; // @[Mux.scala 27:72]
+  wire  _T_2088 = _T_2026 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72]
+  wire  _T_2089 = _T_2028 & io_dma_pmu_any_read; // @[Mux.scala 27:72]
+  wire  _T_2090 = _T_2030 & io_dma_pmu_any_write; // @[Mux.scala 27:72]
+  wire  _T_2091 = _T_2032 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72]
+  wire  _T_2092 = _T_2034 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72]
+  wire  _T_2093 = _T_1869 | _T_2037; // @[Mux.scala 27:72]
+  wire  _T_2094 = _T_2093 | _T_2038; // @[Mux.scala 27:72]
+  wire  _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72]
+  wire  _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72]
+  wire  _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72]
+  wire  _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72]
+  wire  _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72]
+  wire  _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72]
+  wire  _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72]
+  wire  _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72]
+  wire  _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72]
   wire  _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72]
   wire  _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72]
   wire  _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72]
@@ -52126,7 +50922,7 @@ module csr_tlu(
   wire  _T_2118 = _T_2117 | _T_2062; // @[Mux.scala 27:72]
   wire  _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72]
   wire  _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72]
-  wire  _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72]
+  wire  _T_2121 = _T_2120 | _T_2044; // @[Mux.scala 27:72]
   wire  _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72]
   wire  _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72]
   wire  _T_2124 = _T_2123 | _T_2068; // @[Mux.scala 27:72]
@@ -52136,10 +50932,8 @@ module csr_tlu(
   wire  _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72]
   wire  _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72]
   wire  _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72]
-  wire  _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72]
-  wire  _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72]
-  wire  _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72]
-  wire  _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72]
+  wire  _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72]
+  wire  _T_2134 = _T_2131 | _T_2078; // @[Mux.scala 27:72]
   wire  _T_2135 = _T_2134 | _T_2079; // @[Mux.scala 27:72]
   wire  _T_2136 = _T_2135 | _T_2080; // @[Mux.scala 27:72]
   wire  _T_2137 = _T_2136 | _T_2081; // @[Mux.scala 27:72]
@@ -52154,196 +50948,196 @@ module csr_tlu(
   wire  _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72]
   wire  _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72]
   wire  _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72]
-  wire  _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72]
-  wire  _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72]
-  wire  _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72]
-  wire  _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72]
-  wire  _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72]
-  wire  _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72]
-  wire  _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72]
-  wire  _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72]
-  wire  _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72]
-  wire  _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72]
-  wire  mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2274:44]
+  wire  mhpmc_inc_r_3 = _T_1868 & _T_2148; // @[dec_tlu_ctl.scala 2274:44]
   reg  mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2335:53]
   reg  mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2336:53]
   reg  mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2337:53]
   reg  mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2338:53]
   reg  perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2339:56]
   wire  perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2342:67]
-  wire  _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37]
-  wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58]
-  wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2343:86]
-  wire  _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67]
-  wire  _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2345:65]
-  wire  _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2345:45]
-  wire  _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67]
-  wire  _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2346:65]
-  wire  _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2346:45]
-  wire  _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67]
-  wire  _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2347:65]
-  wire  _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2347:45]
-  wire  _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67]
-  wire  _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2348:65]
-  wire  _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2348:45]
-  wire  _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72]
-  wire  mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2354:43]
-  wire  _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23]
-  wire  _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39]
-  wire  _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86]
-  wire  mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2355:66]
+  wire  _T_2160 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37]
+  wire [3:0] _T_2162 = _T_2160 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_2169 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58]
+  wire [3:0] perfcnt_during_sleep = _T_2162 & _T_2169; // @[dec_tlu_ctl.scala 2343:86]
+  wire  _T_2171 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67]
+  wire  _T_2172 = perfcnt_halted_d1 & _T_2171; // @[dec_tlu_ctl.scala 2345:65]
+  wire  _T_2173 = ~_T_2172; // @[dec_tlu_ctl.scala 2345:45]
+  wire  _T_2176 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67]
+  wire  _T_2177 = perfcnt_halted_d1 & _T_2176; // @[dec_tlu_ctl.scala 2346:65]
+  wire  _T_2178 = ~_T_2177; // @[dec_tlu_ctl.scala 2346:45]
+  wire  _T_2181 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67]
+  wire  _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2347:65]
+  wire  _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2347:45]
+  wire  _T_2186 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67]
+  wire  _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2348:65]
+  wire  _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2348:45]
+  wire  _T_2191 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72]
+  wire  mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2191; // @[dec_tlu_ctl.scala 2354:43]
+  wire  _T_2192 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23]
+  wire  _T_2194 = _T_2192 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39]
+  wire  _T_2195 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86]
+  wire  mhpmc3_wr_en1 = _T_2194 & _T_2195; // @[dec_tlu_ctl.scala 2355:66]
   reg [31:0] mhpmc3h; // @[lib.scala 374:16]
   reg [31:0] mhpmc3; // @[lib.scala 374:16]
-  wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58]
-  wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58]
-  wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2359:49]
-  wire  _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73]
-  wire  mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2364:44]
-  wire  _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72]
-  wire  mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2373:43]
-  wire  _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39]
-  wire  _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86]
-  wire  mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2374:66]
+  wire [63:0] _T_2198 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58]
+  wire [63:0] _T_2199 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58]
+  wire [63:0] mhpmc3_incr = _T_2198 + _T_2199; // @[dec_tlu_ctl.scala 2359:49]
+  wire  _T_2207 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73]
+  wire  mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2207; // @[dec_tlu_ctl.scala 2364:44]
+  wire  _T_2213 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72]
+  wire  mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2213; // @[dec_tlu_ctl.scala 2373:43]
+  wire  _T_2216 = _T_2192 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39]
+  wire  _T_2217 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86]
+  wire  mhpmc4_wr_en1 = _T_2216 & _T_2217; // @[dec_tlu_ctl.scala 2374:66]
   reg [31:0] mhpmc4h; // @[lib.scala 374:16]
   reg [31:0] mhpmc4; // @[lib.scala 374:16]
-  wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58]
-  wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58]
-  wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2379:49]
-  wire  _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73]
-  wire  mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2383:44]
-  wire  _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72]
-  wire  mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2392:43]
-  wire  _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39]
-  wire  _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86]
-  wire  mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2393:66]
+  wire [63:0] _T_2220 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58]
+  wire [63:0] _T_2221 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58]
+  wire [63:0] mhpmc4_incr = _T_2220 + _T_2221; // @[dec_tlu_ctl.scala 2379:49]
+  wire  _T_2230 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73]
+  wire  mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2230; // @[dec_tlu_ctl.scala 2383:44]
+  wire  _T_2236 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72]
+  wire  mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2236; // @[dec_tlu_ctl.scala 2392:43]
+  wire  _T_2239 = _T_2192 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39]
+  wire  _T_2240 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86]
+  wire  mhpmc5_wr_en1 = _T_2239 & _T_2240; // @[dec_tlu_ctl.scala 2393:66]
   reg [31:0] mhpmc5h; // @[lib.scala 374:16]
   reg [31:0] mhpmc5; // @[lib.scala 374:16]
-  wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58]
-  wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58]
-  wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2396:49]
-  wire  _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73]
-  wire  mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2401:44]
-  wire  _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72]
-  wire  mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2410:43]
-  wire  _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39]
-  wire  _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86]
-  wire  mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2411:66]
+  wire [63:0] _T_2243 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58]
+  wire [63:0] _T_2244 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58]
+  wire [63:0] mhpmc5_incr = _T_2243 + _T_2244; // @[dec_tlu_ctl.scala 2396:49]
+  wire  _T_2252 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73]
+  wire  mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2252; // @[dec_tlu_ctl.scala 2401:44]
+  wire  _T_2258 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72]
+  wire  mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2258; // @[dec_tlu_ctl.scala 2410:43]
+  wire  _T_2261 = _T_2192 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39]
+  wire  _T_2262 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86]
+  wire  mhpmc6_wr_en1 = _T_2261 & _T_2262; // @[dec_tlu_ctl.scala 2411:66]
   reg [31:0] mhpmc6h; // @[lib.scala 374:16]
   reg [31:0] mhpmc6; // @[lib.scala 374:16]
-  wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58]
-  wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58]
-  wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2414:49]
-  wire  _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73]
-  wire  mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2419:44]
-  wire  _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56]
-  wire  _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102]
-  wire  _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2430:71]
-  wire  _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70]
-  wire  wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2432:41]
-  wire  _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70]
-  wire  wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2439:41]
-  wire  _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70]
-  wire  wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2446:41]
-  wire  _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70]
-  wire  wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2453:41]
-  wire  _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77]
-  wire  wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2470:48]
-  wire  _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51]
-  wire  _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78]
-  wire  _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104]
-  wire  _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130]
-  wire  _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32]
-  reg  _T_2331; // @[dec_tlu_ctl.scala 2488:62]
-  wire  _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91]
-  wire  _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137]
-  wire  _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2489:135]
-  reg  _T_2336; // @[dec_tlu_ctl.scala 2489:62]
-  reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2490:62]
-  reg  _T_2338; // @[dec_tlu_ctl.scala 2491:62]
-  wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72]
+  wire [63:0] _T_2265 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58]
+  wire [63:0] _T_2266 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58]
+  wire [63:0] mhpmc6_incr = _T_2265 + _T_2266; // @[dec_tlu_ctl.scala 2414:49]
+  wire  _T_2274 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73]
+  wire  mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2274; // @[dec_tlu_ctl.scala 2419:44]
+  wire  _T_2280 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56]
+  wire  _T_2282 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102]
+  wire  _T_2283 = _T_2280 | _T_2282; // @[dec_tlu_ctl.scala 2430:71]
+  wire  _T_2286 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70]
+  wire  wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2286; // @[dec_tlu_ctl.scala 2432:41]
+  wire  _T_2290 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70]
+  wire  wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2290; // @[dec_tlu_ctl.scala 2439:41]
+  wire  _T_2294 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70]
+  wire  wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2294; // @[dec_tlu_ctl.scala 2446:41]
+  wire  _T_2298 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70]
+  wire  wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2298; // @[dec_tlu_ctl.scala 2453:41]
+  wire  _T_2302 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77]
+  wire  wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2302; // @[dec_tlu_ctl.scala 2470:48]
+  wire  _T_2314 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51]
+  wire  _T_2315 = _T_2314 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78]
+  wire  _T_2316 = _T_2315 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104]
+  wire  _T_2317 = _T_2316 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130]
+  wire  _T_2318 = _T_2317 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32]
+  reg  _T_2321; // @[dec_tlu_ctl.scala 2488:62]
+  wire  _T_2322 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91]
+  wire  _T_2323 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137]
+  wire  _T_2324 = io_trigger_hit_r_d1 & _T_2323; // @[dec_tlu_ctl.scala 2489:135]
+  reg  _T_2326; // @[dec_tlu_ctl.scala 2489:62]
+  reg [4:0] _T_2327; // @[dec_tlu_ctl.scala 2490:62]
+  reg  _T_2328; // @[dec_tlu_ctl.scala 2491:62]
+  wire [31:0] _T_2334 = {io_core_id,4'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2343 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2348 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2361 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2374 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2386 = {io_mepc,1'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2391 = {28'h0,mscause}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2399 = {meivt,10'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2402 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2405 = {28'h0,meicurpl}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2408 = {28'h0,meicidpl}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2411 = {28'h0,meipt}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2414 = {23'h0,mcgc}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2417 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2421 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2423 = {io_dpc,1'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2439 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2442 = {30'h0,mtsel}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2471 = {26'h0,mfdht}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2474 = {30'h0,mfdhs}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2477 = {22'h0,mhpme3}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2480 = {22'h0,mhpme4}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2483 = {22'h0,mhpme5}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2486 = {22'h0,mhpme6}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2489 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2492 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_2495 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2496 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2497 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2498 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2499 = io_csr_pkt_csr_mhartid ? _T_2334 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2500 = io_csr_pkt_csr_mstatus ? _T_2343 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2501 = io_csr_pkt_csr_mtvec ? _T_2348 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2502 = io_csr_pkt_csr_mip ? _T_2361 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2503 = io_csr_pkt_csr_mie ? _T_2374 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2504 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2505 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2506 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2507 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2508 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2509 = io_csr_pkt_csr_mepc ? _T_2386 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2510 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2511 = io_csr_pkt_csr_mscause ? _T_2391 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2512 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2513 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2514 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2515 = io_csr_pkt_csr_meivt ? _T_2399 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2516 = io_csr_pkt_csr_meihap ? _T_2402 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2517 = io_csr_pkt_csr_meicurpl ? _T_2405 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2518 = io_csr_pkt_csr_meicidpl ? _T_2408 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2519 = io_csr_pkt_csr_meipt ? _T_2411 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2520 = io_csr_pkt_csr_mcgc ? _T_2414 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2521 = io_csr_pkt_csr_mfdc ? _T_2417 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2522 = io_csr_pkt_csr_dcsr ? _T_2421 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2523 = io_csr_pkt_csr_dpc ? _T_2423 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2524 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2525 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2526 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2527 = io_csr_pkt_csr_dicawics ? _T_2439 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2528 = io_csr_pkt_csr_mtsel ? _T_2442 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2529 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2530 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2531 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2532 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2533 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2534 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2542 = io_csr_pkt_csr_mfdht ? _T_2471 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2543 = io_csr_pkt_csr_mfdhs ? _T_2474 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2544 = io_csr_pkt_csr_mhpme3 ? _T_2477 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme4 ? _T_2480 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme5 ? _T_2483 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2547 = io_csr_pkt_csr_mhpme6 ? _T_2486 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2548 = io_csr_pkt_csr_mcountinhibit ? _T_2489 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2549 = io_csr_pkt_csr_mpmc ? _T_2492 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2550 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_2551 = _T_2495 | _T_2496; // @[Mux.scala 27:72]
+  wire [31:0] _T_2552 = _T_2551 | _T_2497; // @[Mux.scala 27:72]
+  wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72]
+  wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72]
+  wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72]
+  wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72]
+  wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72]
+  wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72]
+  wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72]
+  wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72]
+  wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72]
   wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72]
   wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72]
   wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72]
@@ -52387,16 +51181,6 @@ module csr_tlu(
   wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72]
   wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72]
   wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72]
-  wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72]
-  wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72]
-  wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72]
-  wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72]
-  wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72]
-  wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72]
-  wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72]
-  wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72]
-  wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72]
-  wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72]
   rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -52607,7 +51391,7 @@ module csr_tlu(
     .io_en(rvclkhdr_34_io_en),
     .io_scan_mode(rvclkhdr_34_io_scan_mode)
   );
-  assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56]
+  assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_754,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56]
   assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2158:41]
   assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2166:41]
   assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2167:41]
@@ -52639,15 +51423,15 @@ module csr_tlu(
   assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2235:40]
   assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2236:40]
   assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2249:51]
-  assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2491:30]
-  assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30]
-  assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2488:30]
+  assign io_dec_tlu_int_valid_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2491:30]
+  assign io_dec_tlu_i0_exc_valid_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2489:30]
+  assign io_dec_tlu_i0_valid_wb1 = _T_2321; // @[dec_tlu_ctl.scala 2488:30]
   assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2493:24]
-  assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30]
-  assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2345:22]
-  assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2346:22]
-  assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2347:22]
-  assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2348:22]
+  assign io_dec_tlu_exc_cause_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2490:30]
+  assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2173; // @[dec_tlu_ctl.scala 2345:22]
+  assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2178; // @[dec_tlu_ctl.scala 2346:22]
+  assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2183; // @[dec_tlu_ctl.scala 2347:22]
+  assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2188; // @[dec_tlu_ctl.scala 2348:22]
   assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31]
   assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31]
   assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31]
@@ -52655,9 +51439,9 @@ module csr_tlu(
   assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31]
   assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31]
   assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31]
-  assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2498:21]
+  assign io_dec_csr_rddata_d = _T_2604 | _T_2550; // @[dec_tlu_ctl.scala 2498:21]
   assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1768:39]
-  assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1777:24]
+  assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1777:24]
   assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2006:19]
   assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22]
   assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20]
@@ -52669,23 +51453,23 @@ module csr_tlu(
   assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1763:39]
   assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1762:39]
   assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1451:23]
-  assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1842:17]
+  assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1842:17]
   assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1467:13]
   assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1466:20]
-  assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2053:10]
+  assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2053:10]
   assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1479:11]
   assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1494:9]
   assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1508:12]
   assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1602:11]
   assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1608:14]
   assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1627:10]
-  assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1825:22]
-  assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1933:16]
-  assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2070:9]
-  assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2226:39]
-  assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2226:39]
-  assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2226:39]
-  assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2226:39]
+  assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1825:22]
+  assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1933:16]
+  assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2070:9]
+  assign io_mtdata1_t_0 = _T_863; // @[dec_tlu_ctl.scala 2226:39]
+  assign io_mtdata1_t_1 = _T_864; // @[dec_tlu_ctl.scala 2226:39]
+  assign io_mtdata1_t_2 = _T_865; // @[dec_tlu_ctl.scala 2226:39]
+  assign io_mtdata1_t_3 = _T_866; // @[dec_tlu_ctl.scala 2226:39]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
   assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
@@ -52717,34 +51501,34 @@ module csr_tlu(
   assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17]
+  assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17]
+  assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18]
   assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17]
   assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17]
+  assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17]
   assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18]
   assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17]
   assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17]
+  assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17]
   assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17]
+  assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17]
   assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17]
+  assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17]
   assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17]
+  assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17]
   assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17]
+  assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17]
   assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18]
   assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17]
@@ -52753,16 +51537,16 @@ module csr_tlu(
   assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17]
   assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17]
+  assign rvclkhdr_22_io_en = _T_962 & _T_798; // @[lib.scala 371:17]
   assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17]
+  assign rvclkhdr_23_io_en = _T_971 & _T_807; // @[lib.scala 371:17]
   assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17]
+  assign rvclkhdr_24_io_en = _T_980 & _T_816; // @[lib.scala 371:17]
   assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17]
+  assign rvclkhdr_25_io_en = _T_989 & _T_825; // @[lib.scala 371:17]
   assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18]
   assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17]
@@ -52789,7 +51573,7 @@ module csr_tlu(
   assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17]
   assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16]
+  assign rvclkhdr_34_io_en = _T_2318 | io_clk_override; // @[lib.scala 345:16]
   assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -52899,9 +51683,9 @@ initial begin
   _RAND_35 = {1{`RANDOM}};
   meipt = _RAND_35[3:0];
   _RAND_36 = {1{`RANDOM}};
-  _T_701 = _RAND_36[15:0];
+  _T_691 = _RAND_36[15:0];
   _RAND_37 = {1{`RANDOM}};
-  _T_726 = _RAND_37[30:0];
+  _T_716 = _RAND_37[30:0];
   _RAND_38 = {1{`RANDOM}};
   dicawics = _RAND_38[16:0];
   _RAND_39 = {3{`RANDOM}};
@@ -52909,7 +51693,7 @@ initial begin
   _RAND_40 = {1{`RANDOM}};
   dicad0h = _RAND_40[31:0];
   _RAND_41 = {1{`RANDOM}};
-  _T_759 = _RAND_41[6:0];
+  _T_749 = _RAND_41[6:0];
   _RAND_42 = {1{`RANDOM}};
   icache_rd_valid_f = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
@@ -52917,13 +51701,13 @@ initial begin
   _RAND_44 = {1{`RANDOM}};
   mtsel = _RAND_44[1:0];
   _RAND_45 = {1{`RANDOM}};
-  _T_873 = _RAND_45[9:0];
+  _T_863 = _RAND_45[9:0];
   _RAND_46 = {1{`RANDOM}};
-  _T_874 = _RAND_46[9:0];
+  _T_864 = _RAND_46[9:0];
   _RAND_47 = {1{`RANDOM}};
-  _T_875 = _RAND_47[9:0];
+  _T_865 = _RAND_47[9:0];
   _RAND_48 = {1{`RANDOM}};
-  _T_876 = _RAND_48[9:0];
+  _T_866 = _RAND_48[9:0];
   _RAND_49 = {1{`RANDOM}};
   mtdata2_t_0 = _RAND_49[31:0];
   _RAND_50 = {1{`RANDOM}};
@@ -52967,13 +51751,13 @@ initial begin
   _RAND_69 = {1{`RANDOM}};
   mhpmc6 = _RAND_69[31:0];
   _RAND_70 = {1{`RANDOM}};
-  _T_2331 = _RAND_70[0:0];
+  _T_2321 = _RAND_70[0:0];
   _RAND_71 = {1{`RANDOM}};
-  _T_2336 = _RAND_71[0:0];
+  _T_2326 = _RAND_71[0:0];
   _RAND_72 = {1{`RANDOM}};
-  _T_2337 = _RAND_72[4:0];
+  _T_2327 = _RAND_72[4:0];
   _RAND_73 = {1{`RANDOM}};
-  _T_2338 = _RAND_73[0:0];
+  _T_2328 = _RAND_73[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     mpmc_b = 1'h0;
@@ -53084,10 +51868,10 @@ initial begin
     meipt = 4'h0;
   end
   if (reset) begin
-    _T_701 = 16'h0;
+    _T_691 = 16'h0;
   end
   if (reset) begin
-    _T_726 = 31'h0;
+    _T_716 = 31'h0;
   end
   if (reset) begin
     dicawics = 17'h0;
@@ -53099,7 +51883,7 @@ initial begin
     dicad0h = 32'h0;
   end
   if (reset) begin
-    _T_759 = 7'h0;
+    _T_749 = 7'h0;
   end
   if (reset) begin
     icache_rd_valid_f = 1'h0;
@@ -53111,16 +51895,16 @@ initial begin
     mtsel = 2'h0;
   end
   if (reset) begin
-    _T_873 = 10'h0;
+    _T_863 = 10'h0;
   end
   if (reset) begin
-    _T_874 = 10'h0;
+    _T_864 = 10'h0;
   end
   if (reset) begin
-    _T_875 = 10'h0;
+    _T_865 = 10'h0;
   end
   if (reset) begin
-    _T_876 = 10'h0;
+    _T_866 = 10'h0;
   end
   if (reset) begin
     mtdata2_t_0 = 32'h0;
@@ -53186,16 +51970,16 @@ initial begin
     mhpmc6 = 32'h0;
   end
   if (reset) begin
-    _T_2331 = 1'h0;
+    _T_2321 = 1'h0;
   end
   if (reset) begin
-    _T_2336 = 1'h0;
+    _T_2326 = 1'h0;
   end
   if (reset) begin
-    _T_2337 = 5'h0;
+    _T_2327 = 5'h0;
   end
   if (reset) begin
-    _T_2338 = 1'h0;
+    _T_2328 = 1'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -53207,9 +51991,9 @@ end // initial
     if (reset) begin
       mpmc_b <= 1'h0;
     end else if (wr_mpmc_r) begin
-      mpmc_b <= _T_510;
+      mpmc_b <= _T_500;
     end else begin
-      mpmc_b <= _T_511;
+      mpmc_b <= _T_501;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -53230,27 +52014,27 @@ end // initial
     if (reset) begin
       mdccmect <= 32'h0;
     end else if (wr_mdccmect_r) begin
-      mdccmect <= _T_525;
+      mdccmect <= _T_515;
     end else begin
-      mdccmect <= _T_569;
+      mdccmect <= _T_559;
     end
   end
   always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
     if (reset) begin
       miccmect <= 32'h0;
     end else if (wr_miccmect_r) begin
-      miccmect <= _T_525;
+      miccmect <= _T_515;
     end else begin
-      miccmect <= _T_548;
+      miccmect <= _T_538;
     end
   end
   always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
     if (reset) begin
       micect <= 32'h0;
     end else if (wr_micect_r) begin
-      micect <= _T_525;
+      micect <= _T_515;
     end else begin
-      micect <= _T_527;
+      micect <= _T_517;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -53398,14 +52182,14 @@ end // initial
     if (reset) begin
       mfdc_int <= 15'h0;
     end else begin
-      mfdc_int <= {_T_347,_T_346};
+      mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]};
     end
   end
   always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
     if (reset) begin
       mrac <= 32'h0;
     end else begin
-      mrac <= {_T_484,_T_469};
+      mrac <= {_T_474,_T_459};
     end
   end
   always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
@@ -53425,11 +52209,11 @@ end // initial
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       mfdhs <= 2'h0;
-    end else if (_T_595) begin
+    end else if (_T_585) begin
       if (wr_mfdhs_r) begin
         mfdhs <= io_dec_csr_wrdata_r[1:0];
-      end else if (_T_589) begin
-        mfdhs <= _T_593;
+      end else if (_T_579) begin
+        mfdhs <= _T_583;
       end
     end
   end
@@ -53438,7 +52222,7 @@ end // initial
       force_halt_ctr_f <= 32'h0;
     end else if (mfdht[0]) begin
       if (io_debug_halt_req_f) begin
-        force_halt_ctr_f <= _T_600;
+        force_halt_ctr_f <= _T_590;
       end else if (io_dbg_tlu_halted_f) begin
         force_halt_ctr_f <= 32'h0;
       end
@@ -53483,27 +52267,27 @@ end // initial
   end
   always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_701 <= 16'h0;
+      _T_691 <= 16'h0;
     end else if (enter_debug_halt_req_le) begin
-      _T_701 <= _T_675;
+      _T_691 <= _T_665;
     end else if (wr_dcsr_r) begin
-      _T_701 <= _T_690;
+      _T_691 <= _T_680;
     end else begin
-      _T_701 <= _T_695;
+      _T_691 <= _T_685;
     end
   end
   always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_726 <= 31'h0;
+      _T_716 <= 31'h0;
     end else begin
-      _T_726 <= _T_721 | _T_720;
+      _T_716 <= _T_711 | _T_710;
     end
   end
   always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin
     if (reset) begin
       dicawics <= 17'h0;
     end else begin
-      dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]};
+      dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]};
     end
   end
   always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin
@@ -53526,12 +52310,12 @@ end // initial
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_759 <= 7'h0;
-    end else if (_T_757) begin
-      if (_T_752) begin
-        _T_759 <= io_dec_csr_wrdata_r[6:0];
+      _T_749 <= 7'h0;
+    end else if (_T_747) begin
+      if (_T_742) begin
+        _T_749 <= io_dec_csr_wrdata_r[6:0];
       end else begin
-        _T_759 <= io_ifu_ic_debug_rd_data[70:64];
+        _T_749 <= io_ifu_ic_debug_rd_data[70:64];
       end
     end
   end
@@ -53539,14 +52323,14 @@ end // initial
     if (reset) begin
       icache_rd_valid_f <= 1'h0;
     end else begin
-      icache_rd_valid_f <= _T_769 & _T_771;
+      icache_rd_valid_f <= _T_759 & _T_761;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       icache_wr_valid_f <= 1'h0;
     end else begin
-      icache_wr_valid_f <= _T_663 & _T_774;
+      icache_wr_valid_f <= _T_653 & _T_764;
     end
   end
   always @(posedge io_csr_wr_clk or posedge reset) begin
@@ -53558,38 +52342,38 @@ end // initial
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_873 <= 10'h0;
+      _T_863 <= 10'h0;
     end else if (wr_mtdata1_t_r_0) begin
-      _T_873 <= tdata_wrdata_r;
+      _T_863 <= tdata_wrdata_r;
     end else begin
-      _T_873 <= _T_844;
+      _T_863 <= _T_834;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_874 <= 10'h0;
+      _T_864 <= 10'h0;
     end else if (wr_mtdata1_t_r_1) begin
-      _T_874 <= tdata_wrdata_r;
+      _T_864 <= tdata_wrdata_r;
     end else begin
-      _T_874 <= _T_853;
+      _T_864 <= _T_843;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_875 <= 10'h0;
+      _T_865 <= 10'h0;
     end else if (wr_mtdata1_t_r_2) begin
-      _T_875 <= tdata_wrdata_r;
+      _T_865 <= tdata_wrdata_r;
     end else begin
-      _T_875 <= _T_862;
+      _T_865 <= _T_852;
     end
   end
   always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
-      _T_876 <= 10'h0;
+      _T_866 <= 10'h0;
     end else if (wr_mtdata1_t_r_3) begin
-      _T_876 <= tdata_wrdata_r;
+      _T_866 <= tdata_wrdata_r;
     end else begin
-      _T_876 <= _T_871;
+      _T_866 <= _T_861;
     end
   end
   always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin
@@ -53624,7 +52408,7 @@ end // initial
     if (reset) begin
       mhpme3 <= 10'h0;
     end else if (wr_mhpme3_r) begin
-      if (_T_2293) begin
+      if (_T_2283) begin
         mhpme3 <= 10'h204;
       end else begin
         mhpme3 <= io_dec_csr_wrdata_r[9:0];
@@ -53635,7 +52419,7 @@ end // initial
     if (reset) begin
       mhpme4 <= 10'h0;
     end else if (wr_mhpme4_r) begin
-      if (_T_2293) begin
+      if (_T_2283) begin
         mhpme4 <= 10'h204;
       end else begin
         mhpme4 <= io_dec_csr_wrdata_r[9:0];
@@ -53646,7 +52430,7 @@ end // initial
     if (reset) begin
       mhpme5 <= 10'h0;
     end else if (wr_mhpme5_r) begin
-      if (_T_2293) begin
+      if (_T_2283) begin
         mhpme5 <= 10'h204;
       end else begin
         mhpme5 <= io_dec_csr_wrdata_r[9:0];
@@ -53657,7 +52441,7 @@ end // initial
     if (reset) begin
       mhpme6 <= 10'h0;
     end else if (wr_mhpme6_r) begin
-      if (_T_2293) begin
+      if (_T_2283) begin
         mhpme6 <= 10'h204;
       end else begin
         mhpme6 <= io_dec_csr_wrdata_r[9:0];
@@ -53668,28 +52452,28 @@ end // initial
     if (reset) begin
       mhpmc_inc_r_d1_0 <= 1'h0;
     end else begin
-      mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306;
+      mhpmc_inc_r_d1_0 <= _T_1016 & _T_1296;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       mhpmc_inc_r_d1_1 <= 1'h0;
     end else begin
-      mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590;
+      mhpmc_inc_r_d1_1 <= _T_1300 & _T_1580;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       mhpmc_inc_r_d1_2 <= 1'h0;
     end else begin
-      mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874;
+      mhpmc_inc_r_d1_2 <= _T_1584 & _T_1864;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
     if (reset) begin
       mhpmc_inc_r_d1_3 <= 1'h0;
     end else begin
-      mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158;
+      mhpmc_inc_r_d1_3 <= _T_1868 & _T_2148;
     end
   end
   always @(posedge io_free_clk or posedge reset) begin
@@ -53773,30 +52557,30 @@ end // initial
   end
   always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_2331 <= 1'h0;
+      _T_2321 <= 1'h0;
     end else begin
-      _T_2331 <= io_i0_valid_wb;
+      _T_2321 <= io_i0_valid_wb;
     end
   end
   always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_2336 <= 1'h0;
+      _T_2326 <= 1'h0;
     end else begin
-      _T_2336 <= _T_2332 | _T_2334;
+      _T_2326 <= _T_2322 | _T_2324;
     end
   end
   always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_2337 <= 5'h0;
+      _T_2327 <= 5'h0;
     end else begin
-      _T_2337 <= io_exc_cause_wb;
+      _T_2327 <= io_exc_cause_wb;
     end
   end
   always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin
     if (reset) begin
-      _T_2338 <= 1'h0;
+      _T_2328 <= 1'h0;
     end else begin
-      _T_2338 <= io_interrupt_valid_r_d1;
+      _T_2328 <= io_interrupt_valid_r_d1;
     end
   end
 endmodule
@@ -54410,13 +53194,11 @@ module dec_tlu_ctl(
   input         io_tlu_mem_ifu_pmu_ic_hit,
   input         io_tlu_mem_ifu_pmu_bus_error,
   input         io_tlu_mem_ifu_pmu_bus_busy,
-  input         io_tlu_mem_ifu_pmu_bus_trxn,
   input         io_tlu_mem_ifu_ic_error_start,
   input         io_tlu_mem_ifu_iccm_rd_ecc_single_err,
   input  [70:0] io_tlu_mem_ifu_ic_debug_rd_data,
   input         io_tlu_mem_ifu_ic_debug_rd_data_valid,
   input         io_tlu_mem_ifu_miss_state_idle,
-  input         io_tlu_busbuff_lsu_pmu_bus_trxn,
   input         io_tlu_busbuff_lsu_pmu_bus_misaligned,
   input         io_tlu_busbuff_lsu_pmu_bus_error,
   input         io_tlu_busbuff_lsu_pmu_bus_busy,
@@ -54591,7 +53373,6 @@ module dec_tlu_ctl(
   wire  csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 818:15]
   wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 818:15]
-  wire  csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 818:15]
@@ -54644,7 +53425,6 @@ module dec_tlu_ctl(
   wire  csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15]
   wire  csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 818:15]
-  wire  csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15]
   wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 818:15]
   wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 818:15]
   wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 818:15]
@@ -55680,7 +54460,6 @@ module dec_tlu_ctl(
     .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute),
     .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m),
     .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2),
-    .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn),
     .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any),
     .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any),
     .io_lsu_store_stall_any(csr_io_lsu_store_stall_any),
@@ -55733,7 +54512,6 @@ module dec_tlu_ctl(
     .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error),
     .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error),
     .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned),
-    .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn),
     .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data),
     .io_dec_tlu_meipt(csr_io_dec_tlu_meipt),
     .io_pic_pl(csr_io_pic_pl),
@@ -56115,7 +54893,6 @@ module dec_tlu_ctl(
   assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 825:44]
   assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 826:44]
   assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 827:44]
-  assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 828:44]
   assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 829:44]
   assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 830:44]
   assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 831:44]
@@ -56149,7 +54926,6 @@ module dec_tlu_ctl(
   assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 856:44]
   assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 857:44]
   assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 858:44]
-  assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 859:44]
   assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 860:44]
   assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 861:44]
   assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 862:44]
@@ -57986,7 +56762,6 @@ module dec(
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit,
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error,
   input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy,
-  input         io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn,
   input         io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start,
   input         io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err,
   input  [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data,
@@ -58079,7 +56854,6 @@ module dec(
   output        io_dec_exu_ib_exu_dec_debug_wdata_rs1_d,
   output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d,
   output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d,
-  input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
   input         io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
@@ -58522,13 +57296,11 @@ module dec(
   wire  tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 120:19]
-  wire  tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 120:19]
   wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 120:19]
   wire  tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 120:19]
-  wire  tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19]
   wire  tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19]
@@ -58979,13 +57751,11 @@ module dec(
     .io_tlu_mem_ifu_pmu_ic_hit(tlu_io_tlu_mem_ifu_pmu_ic_hit),
     .io_tlu_mem_ifu_pmu_bus_error(tlu_io_tlu_mem_ifu_pmu_bus_error),
     .io_tlu_mem_ifu_pmu_bus_busy(tlu_io_tlu_mem_ifu_pmu_bus_busy),
-    .io_tlu_mem_ifu_pmu_bus_trxn(tlu_io_tlu_mem_ifu_pmu_bus_trxn),
     .io_tlu_mem_ifu_ic_error_start(tlu_io_tlu_mem_ifu_ic_error_start),
     .io_tlu_mem_ifu_iccm_rd_ecc_single_err(tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err),
     .io_tlu_mem_ifu_ic_debug_rd_data(tlu_io_tlu_mem_ifu_ic_debug_rd_data),
     .io_tlu_mem_ifu_ic_debug_rd_data_valid(tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid),
     .io_tlu_mem_ifu_miss_state_idle(tlu_io_tlu_mem_ifu_miss_state_idle),
-    .io_tlu_busbuff_lsu_pmu_bus_trxn(tlu_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy),
@@ -59364,13 +58134,11 @@ module dec(
   assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 202:18]
-  assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 202:18]
   assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 202:18]
-  assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 222:26]
   assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 222:26]
@@ -59423,27 +58191,14 @@ module dbg(
   input  [6:0]  io_dmi_reg_addr,
   input         io_dmi_reg_wr_en,
   input  [31:0] io_dmi_reg_wdata,
-  input         io_sb_axi_aw_ready,
   output        io_sb_axi_aw_valid,
   output [31:0] io_sb_axi_aw_bits_addr,
-  output [3:0]  io_sb_axi_aw_bits_region,
   output [2:0]  io_sb_axi_aw_bits_size,
-  input         io_sb_axi_w_ready,
   output        io_sb_axi_w_valid,
-  output [63:0] io_sb_axi_w_bits_data,
   output [7:0]  io_sb_axi_w_bits_strb,
-  output        io_sb_axi_b_ready,
-  input         io_sb_axi_b_valid,
-  input  [1:0]  io_sb_axi_b_bits_resp,
-  input         io_sb_axi_ar_ready,
   output        io_sb_axi_ar_valid,
   output [31:0] io_sb_axi_ar_bits_addr,
-  output [3:0]  io_sb_axi_ar_bits_region,
   output [2:0]  io_sb_axi_ar_bits_size,
-  output        io_sb_axi_r_ready,
-  input         io_sb_axi_r_valid,
-  input  [63:0] io_sb_axi_r_bits_data,
-  input  [1:0]  io_sb_axi_r_bits_resp,
   output        io_dbg_dec_dbg_ib_dbg_cmd_valid,
   output        io_dbg_dec_dbg_ib_dbg_cmd_write,
   output [1:0]  io_dbg_dec_dbg_ib_dbg_cmd_type,
@@ -59481,8 +58236,6 @@ module dbg(
   reg [31:0] _RAND_16;
   reg [31:0] _RAND_17;
   reg [31:0] _RAND_18;
-  reg [31:0] _RAND_19;
-  reg [31:0] _RAND_20;
 `endif // RANDOMIZE_REG_INIT
   wire [2:0] dbg_state;
   wire  dbg_state_en;
@@ -59492,7 +58245,6 @@ module dbg(
   wire [31:0] sbaddress0_reg;
   wire  sbcs_sbbusy_wren;
   wire  sbcs_sberror_wren;
-  wire [63:0] sb_bus_rdata;
   wire  sbaddress0_reg_wren1;
   wire [31:0] dmstatus_reg;
   wire  dmstatus_havereset;
@@ -59501,12 +58253,6 @@ module dbg(
   wire  dmstatus_running;
   wire  dmstatus_halted;
   wire  abstractcs_busy_wren;
-  wire  sb_bus_cmd_read;
-  wire  sb_bus_cmd_write_addr;
-  wire  sb_bus_cmd_write_data;
-  wire  sb_bus_rsp_read;
-  wire  sb_bus_rsp_error;
-  wire  sb_bus_rsp_write;
   wire  sbcs_sbbusy_din;
   wire [31:0] data1_reg;
   wire [31:0] sbcs_reg;
@@ -59582,23 +58328,14 @@ module dbg(
   wire  _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 136:76]
   wire  sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 136:74]
   wire  sbdata1_reg_wren0 = _T_83 & _T_24; // @[dbg.scala 138:60]
-  wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 141:49]
-  wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33]
-  wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 144:49]
-  wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33]
   wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
   wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  reg [31:0] sbdata0_reg; // @[lib.scala 374:16]
   wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
   wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
-  reg [31:0] sbdata1_reg; // @[lib.scala 374:16]
   wire  sbaddress0_reg_wren0 = _T_83 & _T_21; // @[dbg.scala 155:63]
   wire [31:0] _T_112 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_113 = _T_112 & io_dmi_reg_wdata; // @[dbg.scala 157:59]
@@ -59833,76 +58570,37 @@ module dbg(
   wire  _T_533 = _T_532 | sbcs_illegal_size; // @[dbg.scala 351:57]
   wire  _T_536 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
   wire  _T_543 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_544 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38]
   wire  _T_545 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_546 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48]
-  wire  _T_549 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45]
-  wire  _T_550 = _T_549 & io_dbg_bus_clk_en; // @[dbg.scala 367:70]
   wire  _T_551 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_552 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44]
   wire  _T_553 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_554 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44]
   wire  _T_555 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_556 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38]
-  wire  _T_557 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40]
   wire  _T_558 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_559 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39]
   wire  _T_561 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
   wire  _GEN_50 = _T_561 & sbcs_reg[16]; // @[Conditional.scala 39:67]
-  wire  _GEN_52 = _T_558 ? _T_559 : _T_561; // @[Conditional.scala 39:67]
-  wire  _GEN_53 = _T_558 & _T_557; // @[Conditional.scala 39:67]
-  wire  _GEN_55 = _T_558 ? 1'h0 : _T_561; // @[Conditional.scala 39:67]
+  wire  _GEN_52 = _T_558 ? 1'h0 : _T_561; // @[Conditional.scala 39:67]
   wire  _GEN_57 = _T_558 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67]
-  wire  _GEN_59 = _T_555 ? _T_556 : _GEN_52; // @[Conditional.scala 39:67]
-  wire  _GEN_60 = _T_555 ? _T_557 : _GEN_53; // @[Conditional.scala 39:67]
-  wire  _GEN_62 = _T_555 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_555 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
   wire  _GEN_64 = _T_555 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
-  wire  _GEN_66 = _T_553 ? _T_554 : _GEN_59; // @[Conditional.scala 39:67]
-  wire  _GEN_67 = _T_553 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
-  wire  _GEN_69 = _T_553 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_553 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
   wire  _GEN_71 = _T_553 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
-  wire  _GEN_73 = _T_551 ? _T_552 : _GEN_66; // @[Conditional.scala 39:67]
-  wire  _GEN_74 = _T_551 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
-  wire  _GEN_76 = _T_551 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_551 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
   wire  _GEN_78 = _T_551 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
-  wire  _GEN_80 = _T_545 ? _T_550 : _GEN_73; // @[Conditional.scala 39:67]
-  wire  _GEN_81 = _T_545 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
-  wire  _GEN_83 = _T_545 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67]
+  wire  _GEN_80 = _T_545 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
   wire  _GEN_85 = _T_545 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67]
-  wire  _GEN_87 = _T_543 ? _T_544 : _GEN_80; // @[Conditional.scala 39:67]
-  wire  _GEN_88 = _T_543 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
-  wire  _GEN_90 = _T_543 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67]
+  wire  _GEN_87 = _T_543 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
   wire  _GEN_92 = _T_543 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67]
   wire  _GEN_94 = _T_536 ? _T_533 : _GEN_87; // @[Conditional.scala 39:67]
-  wire  _GEN_95 = _T_536 ? _T_530 : _GEN_88; // @[Conditional.scala 39:67]
-  wire  _GEN_97 = _T_536 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67]
+  wire  _GEN_95 = _T_536 & _T_530; // @[Conditional.scala 39:67]
+  wire  _GEN_97 = _T_536 ? 1'h0 : _GEN_87; // @[Conditional.scala 39:67]
   wire  _GEN_99 = _T_536 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67]
   wire  _GEN_101 = _T_529 ? _T_533 : _GEN_94; // @[Conditional.scala 39:67]
   wire  _GEN_102 = _T_529 ? _T_530 : _GEN_95; // @[Conditional.scala 39:67]
   wire  _GEN_104 = _T_529 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67]
   wire  _GEN_106 = _T_529 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67]
   reg [3:0] _T_564; // @[Reg.scala 27:20]
-  wire  _T_571 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69]
-  wire  _T_572 = sb_bus_rsp_read & _T_571; // @[dbg.scala 406:39]
-  wire  _T_574 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122]
-  wire  _T_575 = sb_bus_rsp_write & _T_574; // @[dbg.scala 406:92]
   wire  _T_577 = sb_state == 4'h4; // @[dbg.scala 407:36]
   wire  _T_578 = sb_state == 4'h5; // @[dbg.scala 407:71]
   wire  _T_584 = sb_state == 4'h6; // @[dbg.scala 418:70]
-  wire [63:0] _T_590 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_594 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58]
-  wire [63:0] _T_595 = _T_590 & _T_594; // @[dbg.scala 419:65]
-  wire [63:0] _T_599 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_602 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58]
-  wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 419:138]
-  wire [63:0] _T_604 = _T_595 | _T_603; // @[dbg.scala 419:96]
-  wire [63:0] _T_608 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_610 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58]
-  wire [63:0] _T_611 = _T_608 & _T_610; // @[dbg.scala 420:45]
-  wire [63:0] _T_612 = _T_604 | _T_611; // @[dbg.scala 419:168]
-  wire [63:0] _T_616 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_619 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
-  wire [63:0] _T_620 = _T_616 & _T_619; // @[dbg.scala 420:119]
   wire [7:0] _T_625 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [14:0] _T_627 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82]
   wire [14:0] _GEN_115 = {{7'd0}, _T_625}; // @[dbg.scala 422:67]
@@ -59922,24 +58620,6 @@ module dbg(
   wire [7:0] _T_650 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 424:100]
   wire [14:0] _T_652 = _T_646 | _GEN_118; // @[dbg.scala 424:100]
-  wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99]
-  wire [6:0] _T_663 = 4'h8 * _GEN_119; // @[dbg.scala 441:99]
-  wire [63:0] _T_664 = io_sb_axi_r_bits_data >> _T_663; // @[dbg.scala 441:92]
-  wire [63:0] _T_665 = _T_664 & 64'hff; // @[dbg.scala 441:123]
-  wire [63:0] _T_666 = _T_590 & _T_665; // @[dbg.scala 441:59]
-  wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86]
-  wire [6:0] _T_673 = 5'h10 * _GEN_120; // @[dbg.scala 442:86]
-  wire [63:0] _T_674 = io_sb_axi_r_bits_data >> _T_673; // @[dbg.scala 442:78]
-  wire [63:0] _T_675 = _T_674 & 64'hffff; // @[dbg.scala 442:110]
-  wire [63:0] _T_676 = _T_599 & _T_675; // @[dbg.scala 442:45]
-  wire [63:0] _T_677 = _T_666 | _T_676; // @[dbg.scala 441:140]
-  wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86]
-  wire [6:0] _T_684 = 6'h20 * _GEN_121; // @[dbg.scala 443:86]
-  wire [63:0] _T_685 = io_sb_axi_r_bits_data >> _T_684; // @[dbg.scala 443:78]
-  wire [63:0] _T_686 = _T_685 & 64'hffffffff; // @[dbg.scala 443:107]
-  wire [63:0] _T_687 = _T_608 & _T_686; // @[dbg.scala 443:45]
-  wire [63:0] _T_688 = _T_677 | _T_687; // @[dbg.scala 442:129]
-  wire [63:0] _T_694 = _T_616 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45]
   rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -59994,17 +58674,12 @@ module dbg(
   assign io_dbg_resume_req = _T_313 ? 1'h0 : _GEN_38; // @[dbg.scala 262:21 dbg.scala 282:25]
   assign io_sb_axi_aw_valid = _T_577 | _T_578; // @[dbg.scala 407:22]
   assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26]
-  assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28]
   assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 410:26]
   assign io_sb_axi_w_valid = _T_577 | _T_584; // @[dbg.scala 418:21]
-  assign io_sb_axi_w_bits_data = _T_612 | _T_620; // @[dbg.scala 419:25]
   assign io_sb_axi_w_bits_strb = _T_652[7:0]; // @[dbg.scala 422:25]
-  assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 439:21]
   assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 428:22]
   assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 429:26]
-  assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 434:28]
   assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 431:26]
-  assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 440:21]
   assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_498 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35]
   assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35]
   assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_487 ? 2'h2 : _T_507; // @[dbg.scala 328:34]
@@ -60024,7 +58699,6 @@ module dbg(
   assign sbaddress0_reg = _T_121; // @[dbg.scala 159:18]
   assign sbcs_sbbusy_wren = _T_518 ? sb_state_en : _GEN_104; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24]
   assign sbcs_sberror_wren = _T_518 ? _T_524 : _GEN_102; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25]
-  assign sb_bus_rdata = _T_688 | _T_694; // @[dbg.scala 441:16]
   assign sbaddress0_reg_wren1 = _T_518 ? 1'h0 : _GEN_106; // @[dbg.scala 339:24 dbg.scala 394:28]
   assign dmstatus_reg = {_T_168,_T_164}; // @[dbg.scala 184:16]
   assign dmstatus_havereset = _T_200; // @[dbg.scala 201:22]
@@ -60033,12 +58707,6 @@ module dbg(
   assign dmstatus_running = ~_T_188; // @[dbg.scala 192:20]
   assign dmstatus_halted = _T_195; // @[dbg.scala 197:19]
   assign abstractcs_busy_wren = _T_313 ? 1'h0 : _GEN_36; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28]
-  assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19]
-  assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25]
-  assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25]
-  assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 404:19]
-  assign sb_bus_rsp_error = _T_572 | _T_575; // @[dbg.scala 406:20]
-  assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 405:20]
   assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 336:19 dbg.scala 345:23 dbg.scala 393:23]
   assign data1_reg = _T_312; // @[dbg.scala 252:13]
   assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 125:12]
@@ -60114,37 +58782,33 @@ initial begin
   _RAND_4 = {1{`RANDOM}};
   temp_sbcs_14_12 = _RAND_4[2:0];
   _RAND_5 = {1{`RANDOM}};
-  sbdata0_reg = _RAND_5[31:0];
+  _T_121 = _RAND_5[31:0];
   _RAND_6 = {1{`RANDOM}};
-  sbdata1_reg = _RAND_6[31:0];
+  dm_temp = _RAND_6[3:0];
   _RAND_7 = {1{`RANDOM}};
-  _T_121 = _RAND_7[31:0];
+  dm_temp_0 = _RAND_7[0:0];
   _RAND_8 = {1{`RANDOM}};
-  dm_temp = _RAND_8[3:0];
+  dmcontrol_wren_Q = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  dm_temp_0 = _RAND_9[0:0];
+  _T_191 = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  dmcontrol_wren_Q = _RAND_10[0:0];
+  _T_195 = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  _T_191 = _RAND_11[0:0];
+  _T_200 = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  _T_195 = _RAND_12[0:0];
+  abs_temp_12 = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  _T_200 = _RAND_13[0:0];
+  abs_temp_10_8 = _RAND_13[2:0];
   _RAND_14 = {1{`RANDOM}};
-  abs_temp_12 = _RAND_14[0:0];
+  command_reg = _RAND_14[31:0];
   _RAND_15 = {1{`RANDOM}};
-  abs_temp_10_8 = _RAND_15[2:0];
+  data0_reg = _RAND_15[31:0];
   _RAND_16 = {1{`RANDOM}};
-  command_reg = _RAND_16[31:0];
+  _T_312 = _RAND_16[31:0];
   _RAND_17 = {1{`RANDOM}};
-  data0_reg = _RAND_17[31:0];
+  _T_483 = _RAND_17[2:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_312 = _RAND_18[31:0];
-  _RAND_19 = {1{`RANDOM}};
-  _T_483 = _RAND_19[2:0];
-  _RAND_20 = {1{`RANDOM}};
-  _T_564 = _RAND_20[3:0];
+  _T_564 = _RAND_18[3:0];
 `endif // RANDOMIZE_REG_INIT
   if (_T_29) begin
     temp_sbcs_22 = 1'h0;
@@ -60161,12 +58825,6 @@ initial begin
   if (_T_36) begin
     temp_sbcs_14_12 = 3'h0;
   end
-  if (_T_29) begin
-    sbdata0_reg = 32'h0;
-  end
-  if (_T_29) begin
-    sbdata1_reg = 32'h0;
-  end
   if (_T_29) begin
     _T_121 = 32'h0;
   end
@@ -60278,20 +58936,6 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      sbdata0_reg <= 32'h0;
-    end else begin
-      sbdata0_reg <= _T_95 | _T_99;
-    end
-  end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      sbdata1_reg <= 32'h0;
-    end else begin
-      sbdata1_reg <= _T_102 | _T_106;
-    end
-  end
   always @(posedge rvclkhdr_4_io_l1clk or posedge _T_29) begin
     if (_T_29) begin
       _T_121 <= 32'h0;
@@ -60460,13 +59104,7 @@ end // initial
       end else if (_T_543) begin
         _T_564 <= 4'h7;
       end else if (_T_545) begin
-        if (_T_546) begin
-          _T_564 <= 4'h8;
-        end else if (sb_bus_cmd_write_data) begin
-          _T_564 <= 4'h5;
-        end else begin
-          _T_564 <= 4'h6;
-        end
+        _T_564 <= 4'h6;
       end else if (_T_551) begin
         _T_564 <= 4'h8;
       end else if (_T_553) begin
@@ -68145,7 +66783,6 @@ module lsu_bus_buffer(
   input         clock,
   input         reset,
   input         io_scan_mode,
-  output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
   output        io_tlu_busbuff_lsu_pmu_bus_busy,
@@ -68196,33 +66833,14 @@ module lsu_bus_buffer(
   input         io_ldst_dual_m,
   input         io_ldst_dual_r,
   input  [7:0]  io_ldst_byteen_ext_m,
-  input         io_lsu_axi_aw_ready,
   output        io_lsu_axi_aw_valid,
-  output [2:0]  io_lsu_axi_aw_bits_id,
   output [31:0] io_lsu_axi_aw_bits_addr,
-  output [3:0]  io_lsu_axi_aw_bits_region,
   output [2:0]  io_lsu_axi_aw_bits_size,
-  output [3:0]  io_lsu_axi_aw_bits_cache,
-  input         io_lsu_axi_w_ready,
   output        io_lsu_axi_w_valid,
-  output [63:0] io_lsu_axi_w_bits_data,
   output [7:0]  io_lsu_axi_w_bits_strb,
-  output        io_lsu_axi_b_ready,
-  input         io_lsu_axi_b_valid,
-  input  [1:0]  io_lsu_axi_b_bits_resp,
-  input  [2:0]  io_lsu_axi_b_bits_id,
-  input         io_lsu_axi_ar_ready,
   output        io_lsu_axi_ar_valid,
-  output [2:0]  io_lsu_axi_ar_bits_id,
   output [31:0] io_lsu_axi_ar_bits_addr,
-  output [3:0]  io_lsu_axi_ar_bits_region,
   output [2:0]  io_lsu_axi_ar_bits_size,
-  output [3:0]  io_lsu_axi_ar_bits_cache,
-  output        io_lsu_axi_r_ready,
-  input         io_lsu_axi_r_valid,
-  input  [2:0]  io_lsu_axi_r_bits_id,
-  input  [63:0] io_lsu_axi_r_bits_data,
-  input  [1:0]  io_lsu_axi_r_bits_resp,
   input         io_lsu_bus_clk_en,
   input         io_lsu_bus_clk_en_q,
   output        io_lsu_busreq_r,
@@ -68315,7 +66933,7 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_77;
   reg [31:0] _RAND_78;
   reg [31:0] _RAND_79;
-  reg [63:0] _RAND_80;
+  reg [31:0] _RAND_80;
   reg [31:0] _RAND_81;
   reg [31:0] _RAND_82;
   reg [31:0] _RAND_83;
@@ -68333,15 +66951,6 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_95;
   reg [31:0] _RAND_96;
   reg [31:0] _RAND_97;
-  reg [31:0] _RAND_98;
-  reg [31:0] _RAND_99;
-  reg [31:0] _RAND_100;
-  reg [31:0] _RAND_101;
-  reg [31:0] _RAND_102;
-  reg [31:0] _RAND_103;
-  reg [31:0] _RAND_104;
-  reg [31:0] _RAND_105;
-  reg [31:0] _RAND_106;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
@@ -69345,17 +67954,9 @@ module lsu_bus_buffer(
   wire  _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 284:164]
   wire  _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 282:98]
   reg  obuf_write; // @[Reg.scala 27:20]
-  reg  obuf_cmd_done; // @[lsu_bus_buffer.scala 347:54]
-  reg  obuf_data_done; // @[lsu_bus_buffer.scala 348:55]
-  wire  _T_4856 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 555:54]
-  wire  _T_4857 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 555:75]
-  wire  _T_4858 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 555:153]
-  wire  _T_4859 = _T_4856 ? _T_4857 : _T_4858; // @[lsu_bus_buffer.scala 555:39]
-  wire  bus_cmd_ready = obuf_write ? _T_4859 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 555:23]
   wire  _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 286:48]
-  wire  _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 286:46]
   reg  obuf_nosend; // @[Reg.scala 27:20]
-  wire  _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60]
+  wire  _T_1233 = _T_1231 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60]
   wire  _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 286:29]
   wire  _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 286:77]
   wire  _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 286:75]
@@ -69399,16 +68000,8 @@ module lsu_bus_buffer(
   wire  _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 286:116]
   wire  obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 286:142]
   wire  _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 288:47]
-  wire  bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40]
-  wire  _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35]
-  wire  bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 557:40]
-  wire  _T_4864 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 558:70]
-  wire  _T_4865 = _T_4863 & _T_4864; // @[lsu_bus_buffer.scala 558:52]
-  wire  _T_4866 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 558:112]
-  wire  bus_cmd_sent = _T_4865 | _T_4866; // @[lsu_bus_buffer.scala 558:89]
-  wire  _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 288:33]
   wire  _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 288:65]
-  wire  _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 288:63]
+  wire  _T_1245 = _T_1242 & _T_1244; // @[lsu_bus_buffer.scala 288:63]
   wire  _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 288:77]
   wire  obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 288:98]
   wire  obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 289:26]
@@ -69444,8 +68037,6 @@ module lsu_bus_buffer(
   wire  _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:104]
   wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58]
   wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 392:11]
-  wire  _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 303:39]
-  wire  _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 303:26]
   wire  _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 307:72]
   wire  _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 307:98]
   wire  _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 307:96]
@@ -69467,23 +68058,8 @@ module lsu_bus_buffer(
   wire  _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 321:128]
   wire  _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 322:20]
   wire  _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 322:18]
-  reg  obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 349:56]
-  wire  bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 559:38]
-  reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 350:55]
-  wire  _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 322:90]
-  wire  _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 322:70]
-  wire  _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 322:55]
-  wire  _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 322:53]
-  wire  _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 322:34]
-  wire  obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 321:177]
-  wire  _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 315:44]
-  wire  _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 315:42]
-  wire  _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 315:29]
-  wire  _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 315:61]
-  wire  _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 315:79]
-  wire  _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20]
+  wire  obuf_nosend_in = _T_1348 & _T_1350; // @[lsu_bus_buffer.scala 321:177]
   wire  _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37]
-  wire  _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35]
   wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58]
   wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58]
   wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46]
@@ -69523,34 +68099,6 @@ module lsu_bus_buffer(
   wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58]
   wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 326:8]
   wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 325:28]
-  wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 328:44]
-  wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72]
-  wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72]
-  wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72]
-  wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 329:8]
-  wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 328:26]
-  wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 330:44]
-  wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1517 = _T_1409 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_1518 = _T_1514 | _T_1515; // @[Mux.scala 27:72]
-  wire [31:0] _T_1519 = _T_1518 | _T_1516; // @[Mux.scala 27:72]
-  wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72]
-  wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 331:8]
-  wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 330:26]
   wire  _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 337:30]
   wire  _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 337:43]
   wire  _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 337:59]
@@ -69603,20 +68151,10 @@ module lsu_bus_buffer(
   wire  _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80]
   wire  _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63]
   wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 333:44]
-  wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 333:44]
-  wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58]
   wire  _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58]
   wire  _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93]
   reg [1:0] obuf_sz; // @[Reg.scala 27:20]
   reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
-  reg [63:0] obuf_data; // @[lib.scala 374:16]
   wire  _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65]
   wire  _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30]
   wire  _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 364:19]
@@ -69741,51 +68279,17 @@ module lsu_bus_buffer(
   wire  _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46]
   wire  _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 560:39]
-  wire  _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 468:73]
-  wire  _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 468:52]
-  wire  _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:46]
   reg  _T_4307; // @[Reg.scala 27:20]
   reg  _T_4305; // @[Reg.scala 27:20]
   reg  _T_4303; // @[Reg.scala 27:20]
   reg  _T_4301; // @[Reg.scala 27:20]
   wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58]
-  reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 470:27]
-  wire  _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 471:44]
-  wire  _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 471:42]
-  wire  _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 471:74]
-  wire  _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 469:25]
-  wire  _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 468:105]
-  wire  _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67]
-  wire  _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
-  wire  _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58]
   wire  _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
   wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 483:21]
-  reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20]
-  reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20]
-  reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20]
-  wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 483:58]
-  wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 483:38]
-  wire  _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 482:95]
-  wire  _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 482:45]
-  wire  _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67]
-  wire  _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67]
-  wire  _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_3555 & buf_cmd_state_bus_en_0; // @[Conditional.scala 39:67]
   wire  _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58]
   wire  _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -69846,41 +68350,12 @@ module lsu_bus_buffer(
   wire  _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73]
-  wire  _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 468:52]
-  wire  _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:46]
-  wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 470:27]
-  wire  _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 471:44]
-  wire  _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 471:42]
-  wire  _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 471:74]
-  wire  _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 469:25]
-  wire  _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 468:105]
-  wire  _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67]
-  wire  _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67]
-  wire  _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58]
   wire  _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
   wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 483:21]
-  wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 483:58]
-  wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 483:38]
-  wire  _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 482:95]
-  wire  _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 482:45]
-  wire  _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67]
-  wire  _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67]
-  wire  _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67]
+  wire  _GEN_129 = _T_3748 & buf_cmd_state_bus_en_1; // @[Conditional.scala 39:67]
   wire  _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58]
   wire  _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -69936,41 +68411,12 @@ module lsu_bus_buffer(
   wire  _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73]
-  wire  _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 468:52]
-  wire  _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:46]
-  wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 470:27]
-  wire  _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 471:44]
-  wire  _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 471:42]
-  wire  _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 471:74]
-  wire  _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 469:25]
-  wire  _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 468:105]
-  wire  _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67]
-  wire  _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67]
-  wire  _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58]
   wire  _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
   wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 483:21]
-  wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 483:58]
-  wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 483:38]
-  wire  _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 482:95]
-  wire  _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 482:45]
-  wire  _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67]
-  wire  _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67]
-  wire  _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67]
+  wire  _GEN_205 = _T_3941 & buf_cmd_state_bus_en_2; // @[Conditional.scala 39:67]
   wire  _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58]
   wire  _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -70026,41 +68472,12 @@ module lsu_bus_buffer(
   wire  _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 443:201]
   wire  _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183]
   wire  _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73]
-  wire  _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 468:52]
-  wire  _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:46]
-  wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 470:47]
-  wire  _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 470:27]
-  wire  _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 469:77]
   wire  _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 471:26]
   wire  _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 471:44]
-  wire  _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 471:42]
-  wire  _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 471:58]
   reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 471:94]
-  wire  _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 471:74]
-  wire  _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 469:25]
-  wire  _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 468:105]
-  wire  _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67]
-  wire  _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67]
-  wire  _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58]
   wire  _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
   wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 483:21]
-  wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 483:58]
-  wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 483:58]
-  wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 483:58]
-  wire  _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 483:38]
-  wire  _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 482:95]
-  wire  _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 482:45]
-  wire  _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67]
-  wire  _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67]
-  wire  _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67]
+  wire  _GEN_281 = _T_4134 & buf_cmd_state_bus_en_3; // @[Conditional.scala 39:67]
   wire  _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67]
   wire  buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58]
   wire  _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49]
@@ -70263,32 +68680,10 @@ module lsu_bus_buffer(
   wire  _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
   wire  _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
   wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58]
-  wire  _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 453:89]
-  wire  _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 453:104]
   wire  _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
-  wire  _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
-  wire  _T_4872 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:64]
-  wire  bus_rsp_read_error = bus_rsp_read & _T_4872; // @[lsu_bus_buffer.scala 564:38]
-  wire  _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
-  wire  _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 475:91]
-  wire  _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 476:31]
-  wire  _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 476:46]
-  wire  _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 475:143]
-  wire  _T_4870 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 563:66]
-  wire  bus_rsp_write_error = bus_rsp_write & _T_4870; // @[lsu_bus_buffer.scala 563:40]
-  wire  _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 477:53]
-  wire  _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 476:88]
-  wire  _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 475:68]
-  wire  _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67]
-  wire  _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67]
-  wire  _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
-  wire  buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58]
-  wire  _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 465:73]
-  wire  _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
-  wire  _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3594 = io_dec_tlu_force_halt | buf_write[0]; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 466:45]
@@ -70317,10 +68712,6 @@ module lsu_bus_buffer(
   wire  _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 467:53]
-  wire  _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
-  wire  _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
-  wire  _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 478:50]
-  wire  _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67]
@@ -70328,14 +68719,11 @@ module lsu_bus_buffer(
   wire  _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
   wire  _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
   wire  _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
-  wire  _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67]
   wire  _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
   wire  _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
   wire  _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67]
-  wire  _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67]
   wire  _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
   wire  _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67]
-  wire  _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
   wire  _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
   wire  buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58]
@@ -70343,22 +68731,7 @@ module lsu_bus_buffer(
   wire  _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
-  wire  _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
-  wire  _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
-  wire  _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 475:91]
-  wire  _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 476:31]
-  wire  _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 476:46]
-  wire  _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 475:143]
-  wire  _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 477:53]
-  wire  _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 476:88]
-  wire  _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 475:68]
-  wire  _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67]
-  wire  _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67]
-  wire  _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67]
-  wire  buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58]
-  wire  _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
-  wire  _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3787 = io_dec_tlu_force_halt | buf_write[1]; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 466:45]
@@ -70384,10 +68757,6 @@ module lsu_bus_buffer(
   wire  _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 467:53]
-  wire  _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
-  wire  _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
-  wire  _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 478:50]
-  wire  _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67]
@@ -70395,14 +68764,11 @@ module lsu_bus_buffer(
   wire  _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67]
   wire  _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67]
   wire  _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67]
-  wire  _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67]
   wire  _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67]
   wire  _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67]
   wire  _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67]
-  wire  _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67]
   wire  _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67]
   wire  _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67]
-  wire  _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67]
   wire  _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67]
   wire  buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58]
@@ -70410,22 +68776,7 @@ module lsu_bus_buffer(
   wire  _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
-  wire  _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
-  wire  _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
-  wire  _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 475:91]
-  wire  _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 476:31]
-  wire  _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 476:46]
-  wire  _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 475:143]
-  wire  _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 477:53]
-  wire  _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 476:88]
-  wire  _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 475:68]
-  wire  _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67]
-  wire  _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67]
-  wire  _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67]
-  wire  buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58]
-  wire  _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
-  wire  _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_3980 = io_dec_tlu_force_halt | buf_write[2]; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 466:45]
@@ -70451,10 +68802,6 @@ module lsu_bus_buffer(
   wire  _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 467:53]
-  wire  _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
-  wire  _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
-  wire  _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 478:50]
-  wire  _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67]
@@ -70462,14 +68809,11 @@ module lsu_bus_buffer(
   wire  _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67]
   wire  _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67]
   wire  _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67]
-  wire  _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67]
   wire  _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67]
   wire  _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67]
   wire  _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67]
-  wire  _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67]
   wire  _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67]
   wire  _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67]
-  wire  _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67]
   wire  _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67]
   wire  buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58]
@@ -70477,22 +68821,7 @@ module lsu_bus_buffer(
   wire  _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 458:44]
   wire  _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60]
   wire  _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 458:74]
-  wire  _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67]
-  wire  _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81]
-  wire  _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82]
-  wire  _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 475:91]
-  wire  _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 476:31]
-  wire  _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 476:46]
-  wire  _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 475:143]
-  wire  _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 477:53]
-  wire  _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 476:88]
-  wire  _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 475:68]
-  wire  _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67]
-  wire  _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67]
-  wire  _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67]
-  wire  buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58]
-  wire  _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 465:71]
-  wire  _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 465:55]
+  wire  _T_4173 = io_dec_tlu_force_halt | buf_write[3]; // @[lsu_bus_buffer.scala 465:55]
   wire  _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 466:30]
   wire  _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 466:28]
   wire  _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 466:45]
@@ -70518,10 +68847,6 @@ module lsu_bus_buffer(
   wire  _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 467:138]
   wire  _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187]
   wire  _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 467:53]
-  wire  _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47]
-  wire  _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62]
-  wire  _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 478:50]
-  wire  _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 478:48]
   wire  _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 481:90]
   wire  _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118]
   wire  _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67]
@@ -70529,14 +68854,11 @@ module lsu_bus_buffer(
   wire  _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67]
   wire  _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67]
   wire  _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67]
-  wire  _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67]
   wire  _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67]
   wire  _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67]
   wire  _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67]
-  wire  _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67]
   wire  _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67]
   wire  _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67]
-  wire  _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67]
   wire  _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67]
   wire  buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58]
   wire  buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58]
@@ -70551,26 +68873,22 @@ module lsu_bus_buffer(
   reg  _T_4401; // @[lsu_bus_buffer.scala 517:80]
   reg  _T_4396; // @[lsu_bus_buffer.scala 517:80]
   wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58]
-  wire  _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 517:126]
-  wire  _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 517:126]
-  wire  _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 517:126]
-  wire  _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 517:84]
   wire  _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 517:126]
   wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
   wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 520:28]
   wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
   wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 520:94]
   wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 520:88]
-  wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154]
-  wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 520:154]
+  wire [2:0] _GEN_376 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154]
+  wire [3:0] _T_4420 = _T_4419 + _GEN_376; // @[lsu_bus_buffer.scala 520:154]
   wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 520:217]
-  wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217]
-  wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 520:217]
-  wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217]
-  wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 520:217]
+  wire [1:0] _GEN_377 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217]
+  wire [2:0] _T_4426 = _T_4425 + _GEN_377; // @[lsu_bus_buffer.scala 520:217]
+  wire [2:0] _GEN_378 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217]
+  wire [3:0] _T_4427 = _T_4426 + _GEN_378; // @[lsu_bus_buffer.scala 520:217]
   wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 520:169]
   wire  _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 526:52]
   wire  _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 526:92]
@@ -70626,8 +68944,8 @@ module lsu_bus_buffer(
   wire  _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 536:119]
   wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_379 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4610 = _GEN_379 | _T_4607; // @[Mux.scala 27:72]
   wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
@@ -70673,8 +68991,8 @@ module lsu_bus_buffer(
   wire  _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72]
   wire  lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72]
   wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
-  wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121]
-  wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 543:121]
+  wire [3:0] _GEN_380 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121]
+  wire [5:0] _T_4740 = _GEN_380 * 4'h8; // @[lsu_bus_buffer.scala 543:121]
   wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 543:92]
   wire  _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 545:82]
   wire  _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 546:94]
@@ -70699,15 +69017,11 @@ module lsu_bus_buffer(
   wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72]
   wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72]
   wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72]
-  wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72]
-  wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72]
+  wire [63:0] _GEN_381 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72]
+  wire [63:0] _T_4776 = _GEN_381 | _T_4772; // @[Mux.scala 27:72]
   wire  _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37]
-  wire  _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52]
-  wire  _T_4876 = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:50]
   wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58]
   wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58]
-  wire  _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51]
-  wire  _T_4888 = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:49]
   wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire  _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37]
   wire  _T_4897 = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:51]
@@ -70733,8 +69047,8 @@ module lsu_bus_buffer(
   wire  _T_4954 = _T_4952 & buf_write[3]; // @[lsu_bus_buffer.scala 599:108]
   wire [1:0] _T_4957 = _T_4949 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_4958 = _T_4954 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_394 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4960 = _GEN_394 | _T_4957; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_382 = {{1'd0}, _T_4944}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4960 = _GEN_382 | _T_4957; // @[Mux.scala 27:72]
   wire [1:0] lsu_imprecise_error_store_tag = _T_4960 | _T_4958; // @[Mux.scala 27:72]
   wire  _T_4962 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 601:97]
   wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53]
@@ -70743,15 +69057,8 @@ module lsu_bus_buffer(
   wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53]
   wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 602:53]
   wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 602:53]
-  wire  _T_4967 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 608:82]
   wire  _T_4970 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 609:60]
-  wire  _T_4973 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 612:61]
-  wire  _T_4974 = io_lsu_axi_aw_valid & _T_4973; // @[lsu_bus_buffer.scala 612:59]
-  wire  _T_4975 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 612:107]
-  wire  _T_4976 = io_lsu_axi_w_valid & _T_4975; // @[lsu_bus_buffer.scala 612:105]
-  wire  _T_4977 = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 612:83]
-  wire  _T_4978 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 612:153]
-  wire  _T_4979 = io_lsu_axi_ar_valid & _T_4978; // @[lsu_bus_buffer.scala 612:151]
+  wire  _T_4977 = io_lsu_axi_aw_valid | io_lsu_axi_w_valid; // @[lsu_bus_buffer.scala 612:83]
   wire  _T_4983 = ~io_flush_r; // @[lsu_bus_buffer.scala 616:75]
   wire  _T_4984 = io_lsu_busreq_m & _T_4983; // @[lsu_bus_buffer.scala 616:73]
   reg  _T_4987; // @[lsu_bus_buffer.scala 616:56]
@@ -70827,10 +69134,9 @@ module lsu_bus_buffer(
     .io_en(rvclkhdr_11_io_en),
     .io_scan_mode(rvclkhdr_11_io_scan_mode)
   );
-  assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4967 | _T_4866; // @[lsu_bus_buffer.scala 608:35]
   assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4970 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 609:41]
   assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 610:36]
-  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | _T_4979; // @[lsu_bus_buffer.scala 612:35]
+  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4977 | io_lsu_axi_ar_valid; // @[lsu_bus_buffer.scala 612:35]
   assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4962; // @[lsu_bus_buffer.scala 601:47]
   assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4932 | _T_4930; // @[lsu_bus_buffer.scala 598:48]
   assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 602:47]
@@ -70842,23 +69148,14 @@ module lsu_bus_buffer(
   assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 535:48]
   assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 536:46]
   assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42]
-  assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 568:23]
-  assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25]
+  assign io_lsu_axi_aw_valid = _T_4874 & _T_1239; // @[lsu_bus_buffer.scala 568:23]
   assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27]
-  assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 574:29]
   assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27]
-  assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 573:28]
-  assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 580:22]
-  assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26]
+  assign io_lsu_axi_w_valid = _T_4874 & _T_1239; // @[lsu_bus_buffer.scala 580:22]
   assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26]
-  assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22]
   assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 585:23]
-  assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25]
   assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27]
-  assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 591:29]
   assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27]
-  assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 590:28]
-  assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22]
   assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19]
   assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30]
   assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 526:30]
@@ -70892,16 +69189,16 @@ module lsu_bus_buffer(
   assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[lib.scala 371:17]
+  assign rvclkhdr_8_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[lib.scala 371:17]
+  assign rvclkhdr_9_io_en = _T_3721 & buf_state_en_1; // @[lib.scala 371:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[lib.scala 371:17]
+  assign rvclkhdr_10_io_en = _T_3914 & buf_state_en_2; // @[lib.scala 371:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[lib.scala 371:17]
+  assign rvclkhdr_11_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -71067,91 +69364,73 @@ initial begin
   _RAND_63 = {1{`RANDOM}};
   obuf_write = _RAND_63[0:0];
   _RAND_64 = {1{`RANDOM}};
-  obuf_cmd_done = _RAND_64[0:0];
+  obuf_nosend = _RAND_64[0:0];
   _RAND_65 = {1{`RANDOM}};
-  obuf_data_done = _RAND_65[0:0];
+  obuf_addr = _RAND_65[31:0];
   _RAND_66 = {1{`RANDOM}};
-  obuf_nosend = _RAND_66[0:0];
+  buf_sz_0 = _RAND_66[1:0];
   _RAND_67 = {1{`RANDOM}};
-  obuf_addr = _RAND_67[31:0];
+  buf_sz_1 = _RAND_67[1:0];
   _RAND_68 = {1{`RANDOM}};
-  buf_sz_0 = _RAND_68[1:0];
+  buf_sz_2 = _RAND_68[1:0];
   _RAND_69 = {1{`RANDOM}};
-  buf_sz_1 = _RAND_69[1:0];
+  buf_sz_3 = _RAND_69[1:0];
   _RAND_70 = {1{`RANDOM}};
-  buf_sz_2 = _RAND_70[1:0];
+  buf_dualhi_3 = _RAND_70[0:0];
   _RAND_71 = {1{`RANDOM}};
-  buf_sz_3 = _RAND_71[1:0];
+  buf_dualhi_2 = _RAND_71[0:0];
   _RAND_72 = {1{`RANDOM}};
-  obuf_rdrsp_pend = _RAND_72[0:0];
+  buf_dualhi_1 = _RAND_72[0:0];
   _RAND_73 = {1{`RANDOM}};
-  obuf_rdrsp_tag = _RAND_73[2:0];
+  buf_dualhi_0 = _RAND_73[0:0];
   _RAND_74 = {1{`RANDOM}};
-  buf_dualhi_3 = _RAND_74[0:0];
+  obuf_sz = _RAND_74[1:0];
   _RAND_75 = {1{`RANDOM}};
-  buf_dualhi_2 = _RAND_75[0:0];
+  obuf_byteen = _RAND_75[7:0];
   _RAND_76 = {1{`RANDOM}};
-  buf_dualhi_1 = _RAND_76[0:0];
+  buf_rspageQ_0 = _RAND_76[3:0];
   _RAND_77 = {1{`RANDOM}};
-  buf_dualhi_0 = _RAND_77[0:0];
+  buf_rspageQ_1 = _RAND_77[3:0];
   _RAND_78 = {1{`RANDOM}};
-  obuf_sz = _RAND_78[1:0];
+  buf_rspageQ_2 = _RAND_78[3:0];
   _RAND_79 = {1{`RANDOM}};
-  obuf_byteen = _RAND_79[7:0];
-  _RAND_80 = {2{`RANDOM}};
-  obuf_data = _RAND_80[63:0];
+  buf_rspageQ_3 = _RAND_79[3:0];
+  _RAND_80 = {1{`RANDOM}};
+  _T_4307 = _RAND_80[0:0];
   _RAND_81 = {1{`RANDOM}};
-  buf_rspageQ_0 = _RAND_81[3:0];
+  _T_4305 = _RAND_81[0:0];
   _RAND_82 = {1{`RANDOM}};
-  buf_rspageQ_1 = _RAND_82[3:0];
+  _T_4303 = _RAND_82[0:0];
   _RAND_83 = {1{`RANDOM}};
-  buf_rspageQ_2 = _RAND_83[3:0];
+  _T_4301 = _RAND_83[0:0];
   _RAND_84 = {1{`RANDOM}};
-  buf_rspageQ_3 = _RAND_84[3:0];
+  buf_dualtag_0 = _RAND_84[1:0];
   _RAND_85 = {1{`RANDOM}};
-  _T_4307 = _RAND_85[0:0];
+  buf_dualtag_1 = _RAND_85[1:0];
   _RAND_86 = {1{`RANDOM}};
-  _T_4305 = _RAND_86[0:0];
+  buf_dualtag_2 = _RAND_86[1:0];
   _RAND_87 = {1{`RANDOM}};
-  _T_4303 = _RAND_87[0:0];
+  buf_dualtag_3 = _RAND_87[1:0];
   _RAND_88 = {1{`RANDOM}};
-  _T_4301 = _RAND_88[0:0];
+  _T_4336 = _RAND_88[0:0];
   _RAND_89 = {1{`RANDOM}};
-  buf_ldfwdtag_0 = _RAND_89[1:0];
+  _T_4339 = _RAND_89[0:0];
   _RAND_90 = {1{`RANDOM}};
-  buf_dualtag_0 = _RAND_90[1:0];
+  _T_4342 = _RAND_90[0:0];
   _RAND_91 = {1{`RANDOM}};
-  buf_ldfwdtag_3 = _RAND_91[1:0];
+  _T_4345 = _RAND_91[0:0];
   _RAND_92 = {1{`RANDOM}};
-  buf_ldfwdtag_2 = _RAND_92[1:0];
+  _T_4411 = _RAND_92[0:0];
   _RAND_93 = {1{`RANDOM}};
-  buf_ldfwdtag_1 = _RAND_93[1:0];
+  _T_4406 = _RAND_93[0:0];
   _RAND_94 = {1{`RANDOM}};
-  buf_dualtag_1 = _RAND_94[1:0];
+  _T_4401 = _RAND_94[0:0];
   _RAND_95 = {1{`RANDOM}};
-  buf_dualtag_2 = _RAND_95[1:0];
+  _T_4396 = _RAND_95[0:0];
   _RAND_96 = {1{`RANDOM}};
-  buf_dualtag_3 = _RAND_96[1:0];
+  lsu_nonblock_load_valid_r = _RAND_96[0:0];
   _RAND_97 = {1{`RANDOM}};
-  _T_4336 = _RAND_97[0:0];
-  _RAND_98 = {1{`RANDOM}};
-  _T_4339 = _RAND_98[0:0];
-  _RAND_99 = {1{`RANDOM}};
-  _T_4342 = _RAND_99[0:0];
-  _RAND_100 = {1{`RANDOM}};
-  _T_4345 = _RAND_100[0:0];
-  _RAND_101 = {1{`RANDOM}};
-  _T_4411 = _RAND_101[0:0];
-  _RAND_102 = {1{`RANDOM}};
-  _T_4406 = _RAND_102[0:0];
-  _RAND_103 = {1{`RANDOM}};
-  _T_4401 = _RAND_103[0:0];
-  _RAND_104 = {1{`RANDOM}};
-  _T_4396 = _RAND_104[0:0];
-  _RAND_105 = {1{`RANDOM}};
-  lsu_nonblock_load_valid_r = _RAND_105[0:0];
-  _RAND_106 = {1{`RANDOM}};
-  _T_4987 = _RAND_106[0:0];
+  _T_4987 = _RAND_97[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     buf_addr_0 = 32'h0;
@@ -71345,12 +69624,6 @@ initial begin
   if (reset) begin
     obuf_write = 1'h0;
   end
-  if (reset) begin
-    obuf_cmd_done = 1'h0;
-  end
-  if (reset) begin
-    obuf_data_done = 1'h0;
-  end
   if (reset) begin
     obuf_nosend = 1'h0;
   end
@@ -71369,12 +69642,6 @@ initial begin
   if (reset) begin
     buf_sz_3 = 2'h0;
   end
-  if (reset) begin
-    obuf_rdrsp_pend = 1'h0;
-  end
-  if (reset) begin
-    obuf_rdrsp_tag = 3'h0;
-  end
   if (reset) begin
     buf_dualhi_3 = 1'h0;
   end
@@ -71393,9 +69660,6 @@ initial begin
   if (reset) begin
     obuf_byteen = 8'h0;
   end
-  if (reset) begin
-    obuf_data = 64'h0;
-  end
   if (reset) begin
     buf_rspageQ_0 = 4'h0;
   end
@@ -71420,21 +69684,9 @@ initial begin
   if (reset) begin
     _T_4301 = 1'h0;
   end
-  if (reset) begin
-    buf_ldfwdtag_0 = 2'h0;
-  end
   if (reset) begin
     buf_dualtag_0 = 2'h0;
   end
-  if (reset) begin
-    buf_ldfwdtag_3 = 2'h0;
-  end
-  if (reset) begin
-    buf_ldfwdtag_2 = 2'h0;
-  end
-  if (reset) begin
-    buf_ldfwdtag_1 = 2'h0;
-  end
   if (reset) begin
     buf_dualtag_1 = 2'h0;
   end
@@ -71538,8 +69790,6 @@ end // initial
       end else if (_T_3555) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
-        end else if (_T_3559) begin
-          buf_state_0 <= 3'h5;
         end else begin
           buf_state_0 <= 3'h3;
         end
@@ -71602,8 +69852,6 @@ end // initial
       end else if (_T_3748) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
-        end else if (_T_3559) begin
-          buf_state_1 <= 3'h5;
         end else begin
           buf_state_1 <= 3'h3;
         end
@@ -71666,8 +69914,6 @@ end // initial
       end else if (_T_3941) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
-        end else if (_T_3559) begin
-          buf_state_2 <= 3'h5;
         end else begin
           buf_state_2 <= 3'h3;
         end
@@ -71730,8 +69976,6 @@ end // initial
       end else if (_T_4134) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
-        end else if (_T_3559) begin
-          buf_state_3 <= 3'h5;
         end else begin
           buf_state_3 <= 3'h3;
         end
@@ -71932,26 +70176,6 @@ end // initial
       end else begin
         buf_data_0 <= store_data_lo_r;
       end
-    end else if (_T_3551) begin
-      buf_data_0 <= 32'h0;
-    end else if (_T_3555) begin
-      if (buf_error_en_0) begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_0[2]) begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3589) begin
-      if (_T_3669) begin
-        if (buf_addr_0[2]) begin
-          buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
-        end else begin
-          buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-        end
-      end else begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-      end
     end else begin
       buf_data_0 <= 32'h0;
     end
@@ -71965,26 +70189,6 @@ end // initial
       end else begin
         buf_data_1 <= store_data_lo_r;
       end
-    end else if (_T_3744) begin
-      buf_data_1 <= 32'h0;
-    end else if (_T_3748) begin
-      if (buf_error_en_1) begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_1[2]) begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3782) begin
-      if (_T_3862) begin
-        if (buf_addr_1[2]) begin
-          buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
-        end else begin
-          buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-        end
-      end else begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-      end
     end else begin
       buf_data_1 <= 32'h0;
     end
@@ -71998,26 +70202,6 @@ end // initial
       end else begin
         buf_data_2 <= store_data_lo_r;
       end
-    end else if (_T_3937) begin
-      buf_data_2 <= 32'h0;
-    end else if (_T_3941) begin
-      if (buf_error_en_2) begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_2[2]) begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3975) begin
-      if (_T_4055) begin
-        if (buf_addr_2[2]) begin
-          buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
-        end else begin
-          buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-        end
-      end else begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-      end
     end else begin
       buf_data_2 <= 32'h0;
     end
@@ -72031,26 +70215,6 @@ end // initial
       end else begin
         buf_data_3 <= store_data_lo_r;
       end
-    end else if (_T_4130) begin
-      buf_data_3 <= 32'h0;
-    end else if (_T_4134) begin
-      if (buf_error_en_3) begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_3[2]) begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_4168) begin
-      if (_T_4248) begin
-        if (buf_addr_3[2]) begin
-          buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
-        end else begin
-          buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-        end
-      end else begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-      end
     end else begin
       buf_data_3 <= 32'h0;
     end
@@ -72302,20 +70466,6 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_cmd_done <= 1'h0;
-    end else begin
-      obuf_cmd_done <= _T_1305 & _T_4863;
-    end
-  end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_data_done <= 1'h0;
-    end else begin
-      obuf_data_done <= _T_1305 & _T_4864;
-    end
-  end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_nosend <= 1'h0;
@@ -72376,20 +70526,6 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_rdrsp_pend <= 1'h0;
-    end else begin
-      obuf_rdrsp_pend <= _T_1330 | _T_1334;
-    end
-  end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_rdrsp_tag <= 3'h0;
-    end else if (_T_1332) begin
-      obuf_rdrsp_tag <= obuf_tag0;
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualhi_3 <= 1'h0;
@@ -72436,13 +70572,6 @@ end // initial
       obuf_byteen <= obuf_byteen_in;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
-    if (reset) begin
-      obuf_data <= 64'h0;
-    end else begin
-      obuf_data <= {_T_1620,_T_1579};
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_0 <= 4'h0;
@@ -72523,21 +70652,6 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_0 <= 2'h0;
-    end else if (buf_ldfwd_en_0) begin
-      if (_T_3528) begin
-        buf_ldfwdtag_0 <= 2'h0;
-      end else if (_T_3551) begin
-        buf_ldfwdtag_0 <= 2'h0;
-      end else if (_T_3555) begin
-        buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_0 <= 2'h0;
-      end
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualtag_0 <= 2'h0;
@@ -72551,51 +70665,6 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_3 <= 2'h0;
-    end else if (buf_ldfwd_en_3) begin
-      if (_T_4107) begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end else if (_T_4130) begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end else if (_T_4134) begin
-        buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_2 <= 2'h0;
-    end else if (buf_ldfwd_en_2) begin
-      if (_T_3914) begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end else if (_T_3937) begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end else if (_T_3941) begin
-        buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_1 <= 2'h0;
-    end else if (buf_ldfwd_en_1) begin
-      if (_T_3721) begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end else if (_T_3744) begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end else if (_T_3748) begin
-        buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualtag_1 <= 2'h0;
@@ -72667,28 +70736,28 @@ end // initial
     if (reset) begin
       _T_4411 <= 1'h0;
     end else begin
-      _T_4411 <= _T_4408 & _T_4409;
+      _T_4411 <= buf_error[3] & _T_4409;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4406 <= 1'h0;
     end else begin
-      _T_4406 <= _T_4403 & _T_4404;
+      _T_4406 <= buf_error[2] & _T_4404;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4401 <= 1'h0;
     end else begin
-      _T_4401 <= _T_4398 & _T_4399;
+      _T_4401 <= buf_error[1] & _T_4399;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4396 <= 1'h0;
     end else begin
-      _T_4396 <= _T_4393 & _T_4394;
+      _T_4396 <= buf_error[0] & _T_4394;
     end
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
@@ -72710,7 +70779,6 @@ module lsu_bus_intf(
   input         clock,
   input         reset,
   input         io_scan_mode,
-  output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
   output        io_tlu_busbuff_lsu_pmu_bus_busy,
@@ -72729,31 +70797,14 @@ module lsu_bus_intf(
   input         io_lsu_free_c2_clk,
   input         io_free_clk,
   input         io_lsu_busm_clk,
-  input         io_axi_aw_ready,
   output        io_axi_aw_valid,
-  output [2:0]  io_axi_aw_bits_id,
   output [31:0] io_axi_aw_bits_addr,
-  output [3:0]  io_axi_aw_bits_region,
   output [2:0]  io_axi_aw_bits_size,
-  output [3:0]  io_axi_aw_bits_cache,
-  input         io_axi_w_ready,
   output        io_axi_w_valid,
-  output [63:0] io_axi_w_bits_data,
   output [7:0]  io_axi_w_bits_strb,
-  input         io_axi_b_valid,
-  input  [1:0]  io_axi_b_bits_resp,
-  input  [2:0]  io_axi_b_bits_id,
-  input         io_axi_ar_ready,
   output        io_axi_ar_valid,
-  output [2:0]  io_axi_ar_bits_id,
   output [31:0] io_axi_ar_bits_addr,
-  output [3:0]  io_axi_ar_bits_region,
   output [2:0]  io_axi_ar_bits_size,
-  output [3:0]  io_axi_ar_bits_cache,
-  input         io_axi_r_valid,
-  input  [2:0]  io_axi_r_bits_id,
-  input  [63:0] io_axi_r_bits_data,
-  input  [1:0]  io_axi_r_bits_resp,
   input         io_dec_lsu_valid_raw_d,
   input         io_lsu_busreq_m,
   input         io_lsu_pkt_m_valid,
@@ -72805,7 +70856,6 @@ module lsu_bus_intf(
   wire  bus_buffer_clock; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_reset; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 101:39]
@@ -72856,33 +70906,14 @@ module lsu_bus_intf(
   wire  bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 101:39]
   wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39]
-  wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39]
   wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39]
-  wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 101:39]
   wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39]
-  wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39]
-  wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39]
   wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39]
-  wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 101:39]
-  wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39]
-  wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39]
   wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39]
-  wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 101:39]
   wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39]
-  wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39]
-  wire  bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39]
-  wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39]
-  wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 101:39]
-  wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 101:39]
   wire  bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 101:39]
@@ -73078,7 +71109,6 @@ module lsu_bus_intf(
     .clock(bus_buffer_clock),
     .reset(bus_buffer_reset),
     .io_scan_mode(bus_buffer_io_scan_mode),
-    .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy),
@@ -73129,33 +71159,14 @@ module lsu_bus_intf(
     .io_ldst_dual_m(bus_buffer_io_ldst_dual_m),
     .io_ldst_dual_r(bus_buffer_io_ldst_dual_r),
     .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m),
-    .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready),
     .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid),
-    .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id),
     .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr),
-    .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region),
     .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size),
-    .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache),
-    .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready),
     .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid),
-    .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data),
     .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb),
-    .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready),
-    .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid),
-    .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp),
-    .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id),
-    .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready),
     .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid),
-    .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id),
     .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr),
-    .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region),
     .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size),
-    .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache),
-    .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready),
-    .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid),
-    .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id),
-    .io_lsu_axi_r_bits_data(bus_buffer_io_lsu_axi_r_bits_data),
-    .io_lsu_axi_r_bits_resp(bus_buffer_io_lsu_axi_r_bits_resp),
     .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en),
     .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q),
     .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r),
@@ -73167,7 +71178,6 @@ module lsu_bus_intf(
     .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo),
     .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi)
   );
-  assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 104:18]
@@ -73175,20 +71185,13 @@ module lsu_bus_intf(
   assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 104:18]
   assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18]
   assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 130:43]
   assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43]
-  assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 130:43]
   assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38]
   assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 134:38]
   assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 135:38]
@@ -73241,16 +71244,6 @@ module lsu_bus_intf(
   assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 147:51]
   assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 148:51]
   assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 149:51]
-  assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 130:43]
-  assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 130:43]
   assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 131:51]
   assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 151:51]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
@@ -73382,7 +71375,6 @@ module lsu(
   input  [31:0] io_lsu_pic_picm_rd_data,
   input  [31:0] io_lsu_exu_exu_lsu_rs1_d,
   input  [31:0] io_lsu_exu_exu_lsu_rs2_d,
-  output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error,
   output        io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy,
@@ -73412,31 +71404,14 @@ module lsu(
   input  [38:0] io_dccm_rd_data_hi,
   output        io_lsu_tlu_lsu_pmu_load_external_m,
   output        io_lsu_tlu_lsu_pmu_store_external_m,
-  input         io_axi_aw_ready,
   output        io_axi_aw_valid,
-  output [2:0]  io_axi_aw_bits_id,
   output [31:0] io_axi_aw_bits_addr,
-  output [3:0]  io_axi_aw_bits_region,
   output [2:0]  io_axi_aw_bits_size,
-  output [3:0]  io_axi_aw_bits_cache,
-  input         io_axi_w_ready,
   output        io_axi_w_valid,
-  output [63:0] io_axi_w_bits_data,
   output [7:0]  io_axi_w_bits_strb,
-  input         io_axi_b_valid,
-  input  [1:0]  io_axi_b_bits_resp,
-  input  [2:0]  io_axi_b_bits_id,
-  input         io_axi_ar_ready,
   output        io_axi_ar_valid,
-  output [2:0]  io_axi_ar_bits_id,
   output [31:0] io_axi_ar_bits_addr,
-  output [3:0]  io_axi_ar_bits_region,
   output [2:0]  io_axi_ar_bits_size,
-  output [3:0]  io_axi_ar_bits_cache,
-  input         io_axi_r_valid,
-  input  [2:0]  io_axi_r_bits_id,
-  input  [63:0] io_axi_r_bits_data,
-  input  [1:0]  io_axi_r_bits_resp,
   input         io_dec_tlu_flush_lower_r,
   input         io_dec_tlu_i0_kill_writeb_r,
   input         io_dec_tlu_force_halt,
@@ -73852,7 +71827,6 @@ module lsu(
   wire  bus_intf_clock; // @[lsu.scala 68:30]
   wire  bus_intf_reset; // @[lsu.scala 68:30]
   wire  bus_intf_io_scan_mode; // @[lsu.scala 68:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30]
   wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30]
@@ -73871,31 +71845,14 @@ module lsu(
   wire  bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 68:30]
   wire  bus_intf_io_free_clk; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_busm_clk; // @[lsu.scala 68:30]
-  wire  bus_intf_io_axi_aw_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30]
-  wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30]
   wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30]
-  wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30]
   wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30]
-  wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30]
-  wire  bus_intf_io_axi_w_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_w_valid; // @[lsu.scala 68:30]
-  wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30]
   wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 68:30]
-  wire  bus_intf_io_axi_b_valid; // @[lsu.scala 68:30]
-  wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 68:30]
-  wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 68:30]
-  wire  bus_intf_io_axi_ar_ready; // @[lsu.scala 68:30]
   wire  bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30]
-  wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30]
   wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30]
-  wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30]
   wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30]
-  wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30]
-  wire  bus_intf_io_axi_r_valid; // @[lsu.scala 68:30]
-  wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30]
-  wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30]
-  wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 68:30]
   wire  bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_busreq_m; // @[lsu.scala 68:30]
   wire  bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 68:30]
@@ -74337,7 +72294,6 @@ module lsu(
     .clock(bus_intf_clock),
     .reset(bus_intf_reset),
     .io_scan_mode(bus_intf_io_scan_mode),
-    .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error),
     .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy),
@@ -74356,31 +72312,14 @@ module lsu(
     .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk),
     .io_free_clk(bus_intf_io_free_clk),
     .io_lsu_busm_clk(bus_intf_io_lsu_busm_clk),
-    .io_axi_aw_ready(bus_intf_io_axi_aw_ready),
     .io_axi_aw_valid(bus_intf_io_axi_aw_valid),
-    .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr),
-    .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region),
     .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size),
-    .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache),
-    .io_axi_w_ready(bus_intf_io_axi_w_ready),
     .io_axi_w_valid(bus_intf_io_axi_w_valid),
-    .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data),
     .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb),
-    .io_axi_b_valid(bus_intf_io_axi_b_valid),
-    .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp),
-    .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id),
-    .io_axi_ar_ready(bus_intf_io_axi_ar_ready),
     .io_axi_ar_valid(bus_intf_io_axi_ar_valid),
-    .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr),
-    .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region),
     .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size),
-    .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache),
-    .io_axi_r_valid(bus_intf_io_axi_r_valid),
-    .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id),
-    .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data),
-    .io_axi_r_bits_resp(bus_intf_io_axi_r_bits_resp),
     .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d),
     .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m),
     .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid),
@@ -74433,7 +72372,6 @@ module lsu(
   assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 196:14]
   assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 196:14]
   assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 196:14]
-  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 286:26]
   assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 286:26]
@@ -74459,20 +72397,13 @@ module lsu(
   assign io_lsu_tlu_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 105:39]
   assign io_lsu_tlu_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 106:39]
   assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49]
-  assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49]
   assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49]
-  assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49]
   assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49]
-  assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49]
   assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49]
-  assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49]
   assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49]
   assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49]
-  assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49]
   assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49]
-  assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49]
   assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49]
-  assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49]
   assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19]
   assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24]
   assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25]
@@ -74718,16 +72649,6 @@ module lsu(
   assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 293:49]
   assign bus_intf_io_free_clk = io_free_clk; // @[lsu.scala 294:49]
   assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[lsu.scala 295:49]
-  assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 314:49]
-  assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 314:49]
   assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 296:49]
   assign bus_intf_io_lsu_busreq_m = _T_39 & _T_40; // @[lsu.scala 297:49]
   assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 305:49]
@@ -78491,28 +76412,8 @@ module dma_ctrl(
   input  [2:0]  io_iccm_dma_rtag,
   input  [63:0] io_iccm_dma_rdata,
   input         io_iccm_ready,
-  output        io_dma_axi_aw_ready,
-  input         io_dma_axi_aw_valid,
-  input         io_dma_axi_aw_bits_id,
-  input  [31:0] io_dma_axi_aw_bits_addr,
-  input  [2:0]  io_dma_axi_aw_bits_size,
-  output        io_dma_axi_w_ready,
-  input         io_dma_axi_w_valid,
-  input  [63:0] io_dma_axi_w_bits_data,
-  input  [7:0]  io_dma_axi_w_bits_strb,
-  input         io_dma_axi_b_ready,
   output        io_dma_axi_b_valid,
-  output [1:0]  io_dma_axi_b_bits_resp,
-  output        io_dma_axi_b_bits_id,
-  output        io_dma_axi_ar_ready,
-  input         io_dma_axi_ar_valid,
-  input         io_dma_axi_ar_bits_id,
-  input  [31:0] io_dma_axi_ar_bits_addr,
-  input  [2:0]  io_dma_axi_ar_bits_size,
-  input         io_dma_axi_r_ready,
   output        io_dma_axi_r_valid,
-  output        io_dma_axi_r_bits_id,
-  output [63:0] io_dma_axi_r_bits_data,
   output [1:0]  io_dma_axi_r_bits_resp,
   output        io_lsu_dma_dma_lsc_ctl_dma_dccm_req,
   output [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr,
@@ -78585,36 +76486,18 @@ module dma_ctrl(
   reg [31:0] _RAND_46;
   reg [31:0] _RAND_47;
   reg [31:0] _RAND_48;
-  reg [63:0] _RAND_49;
+  reg [31:0] _RAND_49;
   reg [31:0] _RAND_50;
   reg [31:0] _RAND_51;
   reg [31:0] _RAND_52;
   reg [31:0] _RAND_53;
-  reg [31:0] _RAND_54;
-  reg [31:0] _RAND_55;
-  reg [31:0] _RAND_56;
-  reg [31:0] _RAND_57;
-  reg [31:0] _RAND_58;
+  reg [63:0] _RAND_54;
+  reg [63:0] _RAND_55;
+  reg [63:0] _RAND_56;
+  reg [63:0] _RAND_57;
+  reg [63:0] _RAND_58;
   reg [31:0] _RAND_59;
   reg [31:0] _RAND_60;
-  reg [31:0] _RAND_61;
-  reg [31:0] _RAND_62;
-  reg [31:0] _RAND_63;
-  reg [31:0] _RAND_64;
-  reg [63:0] _RAND_65;
-  reg [63:0] _RAND_66;
-  reg [63:0] _RAND_67;
-  reg [63:0] _RAND_68;
-  reg [63:0] _RAND_69;
-  reg [31:0] _RAND_70;
-  reg [31:0] _RAND_71;
-  reg [31:0] _RAND_72;
-  reg [31:0] _RAND_73;
-  reg [31:0] _RAND_74;
-  reg [31:0] _RAND_75;
-  reg [31:0] _RAND_76;
-  reg [31:0] _RAND_77;
-  reg [31:0] _RAND_78;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
   wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
@@ -78695,53 +76578,29 @@ module dma_ctrl(
   wire  dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39]
   wire  dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39]
   wire  dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28]
-  reg  wrbuf_vld; // @[dma_ctrl.scala 415:59]
-  reg  wrbuf_data_vld; // @[dma_ctrl.scala 417:59]
-  wire  _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43]
-  reg  rdbuf_vld; // @[dma_ctrl.scala 441:47]
-  wire  _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60]
-  reg  axi_mstr_priority; // @[Reg.scala 27:20]
-  wire  axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31]
-  reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
-  reg [31:0] rdbuf_addr; // @[lib.scala 374:16]
-  wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43]
   wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91]
   wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91]
   wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83]
-  reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
-  wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 195:34]
+  wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : 19'h0; // @[dma_ctrl.scala 195:34]
   wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
-  reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
-  reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
-  wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45]
-  wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33]
-  wire  fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33]
-  wire  bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69]
-  reg  fifo_full; // @[dma_ctrl.scala 373:12]
+  wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : 3'h0; // @[dma_ctrl.scala 197:33]
+  wire  fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 199:33]
   reg  dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12]
-  wire  _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39]
-  wire  dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27]
-  wire  axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54]
-  wire  _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80]
   wire  _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136]
-  wire  _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101]
   reg [2:0] WrPtr; // @[Reg.scala 27:20]
   wire  _T_33 = 3'h0 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_34 = _T_32 & _T_33; // @[dma_ctrl.scala 206:181]
+  wire  _T_34 = _T_31 & _T_33; // @[dma_ctrl.scala 206:181]
   wire  _T_41 = 3'h1 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_42 = _T_32 & _T_41; // @[dma_ctrl.scala 206:181]
+  wire  _T_42 = _T_31 & _T_41; // @[dma_ctrl.scala 206:181]
   wire  _T_49 = 3'h2 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_50 = _T_32 & _T_49; // @[dma_ctrl.scala 206:181]
+  wire  _T_50 = _T_31 & _T_49; // @[dma_ctrl.scala 206:181]
   wire  _T_57 = 3'h3 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_58 = _T_32 & _T_57; // @[dma_ctrl.scala 206:181]
+  wire  _T_58 = _T_31 & _T_57; // @[dma_ctrl.scala 206:181]
   wire  _T_65 = 3'h4 == WrPtr; // @[dma_ctrl.scala 206:188]
-  wire  _T_66 = _T_32 & _T_65; // @[dma_ctrl.scala 206:181]
+  wire  _T_66 = _T_31 & _T_65; // @[dma_ctrl.scala 206:181]
   wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58]
-  wire  _T_71 = axi_mstr_prty_en & fifo_write_in; // @[dma_ctrl.scala 208:73]
-  wire  _T_72 = _T_71 & io_dma_bus_clk_en; // @[dma_ctrl.scala 208:89]
   wire  _T_75 = _T_31 & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 208:181]
-  wire  _T_76 = _T_72 | _T_75; // @[dma_ctrl.scala 208:110]
-  wire  _T_78 = _T_76 & _T_33; // @[dma_ctrl.scala 208:217]
+  wire  _T_78 = _T_75 & _T_33; // @[dma_ctrl.scala 208:217]
   reg  _T_598; // @[dma_ctrl.scala 226:82]
   reg  _T_591; // @[dma_ctrl.scala 226:82]
   reg  _T_584; // @[dma_ctrl.scala 226:82]
@@ -78860,7 +76719,7 @@ module dma_ctrl(
   wire  _T_86 = 3'h0 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_87 = io_iccm_dma_rvalid & _T_86; // @[dma_ctrl.scala 208:416]
   wire  _T_88 = _T_85 | _T_87; // @[dma_ctrl.scala 208:394]
-  wire  _T_96 = _T_76 & _T_41; // @[dma_ctrl.scala 208:217]
+  wire  _T_96 = _T_75 & _T_41; // @[dma_ctrl.scala 208:217]
   wire  _T_98 = 3'h1 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_99 = _T_79 & _T_98; // @[dma_ctrl.scala 208:281]
   wire  _T_100 = _T_96 | _T_99; // @[dma_ctrl.scala 208:236]
@@ -78870,7 +76729,7 @@ module dma_ctrl(
   wire  _T_104 = 3'h1 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_105 = io_iccm_dma_rvalid & _T_104; // @[dma_ctrl.scala 208:416]
   wire  _T_106 = _T_103 | _T_105; // @[dma_ctrl.scala 208:394]
-  wire  _T_114 = _T_76 & _T_49; // @[dma_ctrl.scala 208:217]
+  wire  _T_114 = _T_75 & _T_49; // @[dma_ctrl.scala 208:217]
   wire  _T_116 = 3'h2 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_117 = _T_79 & _T_116; // @[dma_ctrl.scala 208:281]
   wire  _T_118 = _T_114 | _T_117; // @[dma_ctrl.scala 208:236]
@@ -78880,7 +76739,7 @@ module dma_ctrl(
   wire  _T_122 = 3'h2 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_123 = io_iccm_dma_rvalid & _T_122; // @[dma_ctrl.scala 208:416]
   wire  _T_124 = _T_121 | _T_123; // @[dma_ctrl.scala 208:394]
-  wire  _T_132 = _T_76 & _T_57; // @[dma_ctrl.scala 208:217]
+  wire  _T_132 = _T_75 & _T_57; // @[dma_ctrl.scala 208:217]
   wire  _T_134 = 3'h3 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_135 = _T_79 & _T_134; // @[dma_ctrl.scala 208:281]
   wire  _T_136 = _T_132 | _T_135; // @[dma_ctrl.scala 208:236]
@@ -78890,7 +76749,7 @@ module dma_ctrl(
   wire  _T_140 = 3'h3 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423]
   wire  _T_141 = io_iccm_dma_rvalid & _T_140; // @[dma_ctrl.scala 208:416]
   wire  _T_142 = _T_139 | _T_141; // @[dma_ctrl.scala 208:394]
-  wire  _T_150 = _T_76 & _T_65; // @[dma_ctrl.scala 208:217]
+  wire  _T_150 = _T_75 & _T_65; // @[dma_ctrl.scala 208:217]
   wire  _T_152 = 3'h4 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_153 = _T_79 & _T_152; // @[dma_ctrl.scala 208:281]
   wire  _T_154 = _T_150 | _T_153; // @[dma_ctrl.scala 208:236]
@@ -79011,28 +76870,22 @@ module dma_ctrl(
   wire  _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75]
   wire  _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91]
   wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
-  wire  _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61]
-  wire  _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105]
-  wire  bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83]
-  wire  _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99]
-  wire  _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120]
   reg [2:0] RspPtr; // @[Reg.scala 27:20]
   wire  _T_408 = 3'h0 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_409 = _T_407 & _T_408; // @[dma_ctrl.scala 220:143]
+  wire  _T_409 = io_dma_dbg_cmd_done & _T_408; // @[dma_ctrl.scala 220:143]
   wire  _T_413 = 3'h1 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_414 = _T_407 & _T_413; // @[dma_ctrl.scala 220:143]
+  wire  _T_414 = io_dma_dbg_cmd_done & _T_413; // @[dma_ctrl.scala 220:143]
   wire  _T_418 = 3'h2 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_419 = _T_407 & _T_418; // @[dma_ctrl.scala 220:143]
+  wire  _T_419 = io_dma_dbg_cmd_done & _T_418; // @[dma_ctrl.scala 220:143]
   wire  _T_423 = 3'h3 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_424 = _T_407 & _T_423; // @[dma_ctrl.scala 220:143]
+  wire  _T_424 = io_dma_dbg_cmd_done & _T_423; // @[dma_ctrl.scala 220:143]
   wire  _T_428 = 3'h4 == RspPtr; // @[dma_ctrl.scala 220:150]
-  wire  _T_429 = _T_407 & _T_428; // @[dma_ctrl.scala 220:143]
+  wire  _T_429 = io_dma_dbg_cmd_done & _T_428; // @[dma_ctrl.scala 220:143]
   wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58]
   wire  _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77]
   wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58]
   wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58]
-  reg [63:0] wrbuf_data; // @[lib.scala 374:16]
-  wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347]
+  wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : 64'h0; // @[dma_ctrl.scala 224:347]
   wire  _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77]
   wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58]
   wire  _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77]
@@ -79095,14 +76948,6 @@ module dma_ctrl(
   reg [63:0] fifo_data_2; // @[lib.scala 374:16]
   reg [63:0] fifo_data_3; // @[lib.scala 374:16]
   reg [63:0] fifo_data_4; // @[lib.scala 374:16]
-  reg  fifo_tag_0; // @[Reg.scala 27:20]
-  reg  wrbuf_tag; // @[Reg.scala 27:20]
-  reg  rdbuf_tag; // @[Reg.scala 27:20]
-  wire  bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43]
-  reg  fifo_tag_1; // @[Reg.scala 27:20]
-  reg  fifo_tag_2; // @[Reg.scala 27:20]
-  reg  fifo_tag_3; // @[Reg.scala 27:20]
-  reg  fifo_tag_4; // @[Reg.scala 27:20]
   wire  _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30]
   wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76]
   wire  _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30]
@@ -79111,20 +76956,6 @@ module dma_ctrl(
   wire [2:0] _T_944 = RspPtr + 3'h1; // @[dma_ctrl.scala 264:78]
   wire  WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30]
   wire  RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93]
-  wire  RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39]
-  wire [3:0] _T_959 = {3'h0,axi_mstr_prty_en}; // @[Cat.scala 29:58]
-  wire [3:0] _T_961 = {3'h0,bus_rsp_sent}; // @[Cat.scala 29:58]
-  wire [3:0] num_fifo_vld_tmp = _T_959 - _T_961; // @[dma_ctrl.scala 291:62]
-  wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_980 = _T_966 + _T_969; // @[dma_ctrl.scala 293:102]
-  wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102]
-  wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102]
-  wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102]
-  wire [3:0] num_fifo_vld = num_fifo_vld_tmp + num_fifo_vld_tmp2; // @[dma_ctrl.scala 295:45]
   wire  _T_1143 = |fifo_valid; // @[dma_ctrl.scala 338:30]
   wire  fifo_empty = ~_T_1143; // @[dma_ctrl.scala 338:17]
   wire [4:0] _T_1106 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 324:39]
@@ -79167,38 +76998,11 @@ module dma_ctrl(
   wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40]
   wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40]
   reg  dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12]
-  wire  _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44]
-  wire  _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65]
   wire  bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60]
-  wire  _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44]
-  wire  _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
+  wire  _T_1215 = bus_rsp_valid | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
   wire  _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94]
   wire  _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116]
   wire  _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137]
-  wire  wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47]
-  wire  wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46]
-  wire  wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40]
-  wire  _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51]
-  wire  wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49]
-  wire  _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51]
-  wire  wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49]
-  wire  _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63]
-  wire  _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92]
-  wire  _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63]
-  wire  _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102]
-  wire  rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59]
-  wire  _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44]
-  wire  rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42]
-  wire  _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63]
-  wire  rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61]
-  wire  _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51]
-  wire  _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80]
-  wire  _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44]
-  wire  _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42]
-  wire  _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47]
-  wire  _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44]
-  wire  _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42]
-  wire  axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27]
   wire  _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50]
   wire  _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48]
   wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83]
@@ -79206,9 +77010,6 @@ module dma_ctrl(
   wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39]
   wire  axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39]
   wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64]
-  wire  _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33]
-  wire  _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33]
-  wire  _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33]
   wire  _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46]
   rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_io_l1clk),
@@ -79317,15 +77118,8 @@ module dma_ctrl(
   assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42]
   assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41]
   assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41]
-  assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27]
-  assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27]
   assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27]
-  assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41]
-  assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33]
-  assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27]
   assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27]
-  assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37]
-  assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43]
   assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41]
   assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40]
   assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40]
@@ -79373,7 +77167,7 @@ module dma_ctrl(
   assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 371:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33]
-  assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33]
+  assign dma_buffer_c1cgc_io_en = io_dbg_dma_dbg_ib_dbg_cmd_valid | io_clk_override; // @[dma_ctrl.scala 390:33]
   assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33]
   assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29]
   assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29]
@@ -79382,13 +77176,13 @@ module dma_ctrl(
   assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28]
   assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
+  assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 371:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
+  assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 371:17]
   assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
   assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
+  assign rvclkhdr_12_io_en = 1'h0; // @[lib.scala 371:17]
   assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -79438,151 +77232,115 @@ initial begin
   _RAND_5 = {1{`RANDOM}};
   fifo_addr_0 = _RAND_5[31:0];
   _RAND_6 = {1{`RANDOM}};
-  wrbuf_vld = _RAND_6[0:0];
+  dbg_dma_bubble_bus = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  wrbuf_data_vld = _RAND_7[0:0];
+  WrPtr = _RAND_7[2:0];
   _RAND_8 = {1{`RANDOM}};
-  rdbuf_vld = _RAND_8[0:0];
+  _T_598 = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  axi_mstr_priority = _RAND_9[0:0];
+  _T_591 = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  wrbuf_addr = _RAND_10[31:0];
+  _T_584 = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  rdbuf_addr = _RAND_11[31:0];
+  _T_577 = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  wrbuf_byteen = _RAND_12[7:0];
+  _T_570 = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  wrbuf_sz = _RAND_13[2:0];
+  _T_760 = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  rdbuf_sz = _RAND_14[2:0];
+  _T_753 = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  fifo_full = _RAND_15[0:0];
+  _T_746 = _RAND_15[0:0];
   _RAND_16 = {1{`RANDOM}};
-  dbg_dma_bubble_bus = _RAND_16[0:0];
+  _T_739 = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  WrPtr = _RAND_17[2:0];
+  _T_732 = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_598 = _RAND_18[0:0];
+  _T_886 = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  _T_591 = _RAND_19[0:0];
+  _T_884 = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  _T_584 = _RAND_20[0:0];
+  _T_882 = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  _T_577 = _RAND_21[0:0];
+  _T_880 = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
-  _T_570 = _RAND_22[0:0];
+  _T_878 = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  _T_760 = _RAND_23[0:0];
+  fifo_sz_4 = _RAND_23[2:0];
   _RAND_24 = {1{`RANDOM}};
-  _T_753 = _RAND_24[0:0];
+  fifo_sz_3 = _RAND_24[2:0];
   _RAND_25 = {1{`RANDOM}};
-  _T_746 = _RAND_25[0:0];
+  fifo_sz_2 = _RAND_25[2:0];
   _RAND_26 = {1{`RANDOM}};
-  _T_739 = _RAND_26[0:0];
+  fifo_sz_1 = _RAND_26[2:0];
   _RAND_27 = {1{`RANDOM}};
-  _T_732 = _RAND_27[0:0];
+  fifo_sz_0 = _RAND_27[2:0];
   _RAND_28 = {1{`RANDOM}};
-  _T_886 = _RAND_28[0:0];
+  fifo_byteen_4 = _RAND_28[7:0];
   _RAND_29 = {1{`RANDOM}};
-  _T_884 = _RAND_29[0:0];
+  fifo_byteen_3 = _RAND_29[7:0];
   _RAND_30 = {1{`RANDOM}};
-  _T_882 = _RAND_30[0:0];
+  fifo_byteen_2 = _RAND_30[7:0];
   _RAND_31 = {1{`RANDOM}};
-  _T_880 = _RAND_31[0:0];
+  fifo_byteen_1 = _RAND_31[7:0];
   _RAND_32 = {1{`RANDOM}};
-  _T_878 = _RAND_32[0:0];
+  fifo_byteen_0 = _RAND_32[7:0];
   _RAND_33 = {1{`RANDOM}};
-  fifo_sz_4 = _RAND_33[2:0];
+  fifo_error_0 = _RAND_33[1:0];
   _RAND_34 = {1{`RANDOM}};
-  fifo_sz_3 = _RAND_34[2:0];
+  fifo_error_1 = _RAND_34[1:0];
   _RAND_35 = {1{`RANDOM}};
-  fifo_sz_2 = _RAND_35[2:0];
+  fifo_error_2 = _RAND_35[1:0];
   _RAND_36 = {1{`RANDOM}};
-  fifo_sz_1 = _RAND_36[2:0];
+  fifo_error_3 = _RAND_36[1:0];
   _RAND_37 = {1{`RANDOM}};
-  fifo_sz_0 = _RAND_37[2:0];
+  fifo_error_4 = _RAND_37[1:0];
   _RAND_38 = {1{`RANDOM}};
-  fifo_byteen_4 = _RAND_38[7:0];
+  RspPtr = _RAND_38[2:0];
   _RAND_39 = {1{`RANDOM}};
-  fifo_byteen_3 = _RAND_39[7:0];
+  _T_721 = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  fifo_byteen_2 = _RAND_40[7:0];
+  _T_714 = _RAND_40[0:0];
   _RAND_41 = {1{`RANDOM}};
-  fifo_byteen_1 = _RAND_41[7:0];
+  _T_707 = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  fifo_byteen_0 = _RAND_42[7:0];
+  _T_700 = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  fifo_error_0 = _RAND_43[1:0];
+  _T_693 = _RAND_43[0:0];
   _RAND_44 = {1{`RANDOM}};
-  fifo_error_1 = _RAND_44[1:0];
+  _T_799 = _RAND_44[0:0];
   _RAND_45 = {1{`RANDOM}};
-  fifo_error_2 = _RAND_45[1:0];
+  _T_792 = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  fifo_error_3 = _RAND_46[1:0];
+  _T_785 = _RAND_46[0:0];
   _RAND_47 = {1{`RANDOM}};
-  fifo_error_4 = _RAND_47[1:0];
+  _T_778 = _RAND_47[0:0];
   _RAND_48 = {1{`RANDOM}};
-  RspPtr = _RAND_48[2:0];
-  _RAND_49 = {2{`RANDOM}};
-  wrbuf_data = _RAND_49[63:0];
+  _T_771 = _RAND_48[0:0];
+  _RAND_49 = {1{`RANDOM}};
+  _T_850 = _RAND_49[0:0];
   _RAND_50 = {1{`RANDOM}};
-  _T_721 = _RAND_50[0:0];
+  _T_852 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  _T_714 = _RAND_51[0:0];
+  _T_854 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  _T_707 = _RAND_52[0:0];
+  _T_856 = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  _T_700 = _RAND_53[0:0];
-  _RAND_54 = {1{`RANDOM}};
-  _T_693 = _RAND_54[0:0];
-  _RAND_55 = {1{`RANDOM}};
-  _T_799 = _RAND_55[0:0];
-  _RAND_56 = {1{`RANDOM}};
-  _T_792 = _RAND_56[0:0];
-  _RAND_57 = {1{`RANDOM}};
-  _T_785 = _RAND_57[0:0];
-  _RAND_58 = {1{`RANDOM}};
-  _T_778 = _RAND_58[0:0];
+  _T_858 = _RAND_53[0:0];
+  _RAND_54 = {2{`RANDOM}};
+  fifo_data_0 = _RAND_54[63:0];
+  _RAND_55 = {2{`RANDOM}};
+  fifo_data_1 = _RAND_55[63:0];
+  _RAND_56 = {2{`RANDOM}};
+  fifo_data_2 = _RAND_56[63:0];
+  _RAND_57 = {2{`RANDOM}};
+  fifo_data_3 = _RAND_57[63:0];
+  _RAND_58 = {2{`RANDOM}};
+  fifo_data_4 = _RAND_58[63:0];
   _RAND_59 = {1{`RANDOM}};
-  _T_771 = _RAND_59[0:0];
+  dma_nack_count = _RAND_59[2:0];
   _RAND_60 = {1{`RANDOM}};
-  _T_850 = _RAND_60[0:0];
-  _RAND_61 = {1{`RANDOM}};
-  _T_852 = _RAND_61[0:0];
-  _RAND_62 = {1{`RANDOM}};
-  _T_854 = _RAND_62[0:0];
-  _RAND_63 = {1{`RANDOM}};
-  _T_856 = _RAND_63[0:0];
-  _RAND_64 = {1{`RANDOM}};
-  _T_858 = _RAND_64[0:0];
-  _RAND_65 = {2{`RANDOM}};
-  fifo_data_0 = _RAND_65[63:0];
-  _RAND_66 = {2{`RANDOM}};
-  fifo_data_1 = _RAND_66[63:0];
-  _RAND_67 = {2{`RANDOM}};
-  fifo_data_2 = _RAND_67[63:0];
-  _RAND_68 = {2{`RANDOM}};
-  fifo_data_3 = _RAND_68[63:0];
-  _RAND_69 = {2{`RANDOM}};
-  fifo_data_4 = _RAND_69[63:0];
-  _RAND_70 = {1{`RANDOM}};
-  fifo_tag_0 = _RAND_70[0:0];
-  _RAND_71 = {1{`RANDOM}};
-  wrbuf_tag = _RAND_71[0:0];
-  _RAND_72 = {1{`RANDOM}};
-  rdbuf_tag = _RAND_72[0:0];
-  _RAND_73 = {1{`RANDOM}};
-  fifo_tag_1 = _RAND_73[0:0];
-  _RAND_74 = {1{`RANDOM}};
-  fifo_tag_2 = _RAND_74[0:0];
-  _RAND_75 = {1{`RANDOM}};
-  fifo_tag_3 = _RAND_75[0:0];
-  _RAND_76 = {1{`RANDOM}};
-  fifo_tag_4 = _RAND_76[0:0];
-  _RAND_77 = {1{`RANDOM}};
-  dma_nack_count = _RAND_77[2:0];
-  _RAND_78 = {1{`RANDOM}};
-  dma_dbg_cmd_done_q = _RAND_78[0:0];
+  dma_dbg_cmd_done_q = _RAND_60[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     RdPtr = 3'h0;
@@ -79602,36 +77360,6 @@ initial begin
   if (reset) begin
     fifo_addr_0 = 32'h0;
   end
-  if (reset) begin
-    wrbuf_vld = 1'h0;
-  end
-  if (reset) begin
-    wrbuf_data_vld = 1'h0;
-  end
-  if (reset) begin
-    rdbuf_vld = 1'h0;
-  end
-  if (reset) begin
-    axi_mstr_priority = 1'h0;
-  end
-  if (reset) begin
-    wrbuf_addr = 32'h0;
-  end
-  if (reset) begin
-    rdbuf_addr = 32'h0;
-  end
-  if (reset) begin
-    wrbuf_byteen = 8'h0;
-  end
-  if (reset) begin
-    wrbuf_sz = 3'h0;
-  end
-  if (reset) begin
-    rdbuf_sz = 3'h0;
-  end
-  if (reset) begin
-    fifo_full = 1'h0;
-  end
   if (reset) begin
     dbg_dma_bubble_bus = 1'h0;
   end
@@ -79731,9 +77459,6 @@ initial begin
   if (reset) begin
     RspPtr = 3'h0;
   end
-  if (reset) begin
-    wrbuf_data = 64'h0;
-  end
   if (reset) begin
     _T_721 = 1'h0;
   end
@@ -79794,27 +77519,6 @@ initial begin
   if (reset) begin
     fifo_data_4 = 64'h0;
   end
-  if (reset) begin
-    fifo_tag_0 = 1'h0;
-  end
-  if (reset) begin
-    wrbuf_tag = 1'h0;
-  end
-  if (reset) begin
-    rdbuf_tag = 1'h0;
-  end
-  if (reset) begin
-    fifo_tag_1 = 1'h0;
-  end
-  if (reset) begin
-    fifo_tag_2 = 1'h0;
-  end
-  if (reset) begin
-    fifo_tag_3 = 1'h0;
-  end
-  if (reset) begin
-    fifo_tag_4 = 1'h0;
-  end
   if (reset) begin
     dma_nack_count = 3'h0;
   end
@@ -79843,10 +77547,8 @@ end // initial
       fifo_addr_4 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_4 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
-    end else if (axi_mstr_sel) begin
-      fifo_addr_4 <= wrbuf_addr;
     end else begin
-      fifo_addr_4 <= rdbuf_addr;
+      fifo_addr_4 <= 32'h0;
     end
   end
   always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
@@ -79854,10 +77556,8 @@ end // initial
       fifo_addr_3 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_3 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
-    end else if (axi_mstr_sel) begin
-      fifo_addr_3 <= wrbuf_addr;
     end else begin
-      fifo_addr_3 <= rdbuf_addr;
+      fifo_addr_3 <= 32'h0;
     end
   end
   always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
@@ -79865,10 +77565,8 @@ end // initial
       fifo_addr_2 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_2 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
-    end else if (axi_mstr_sel) begin
-      fifo_addr_2 <= wrbuf_addr;
     end else begin
-      fifo_addr_2 <= rdbuf_addr;
+      fifo_addr_2 <= 32'h0;
     end
   end
   always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
@@ -79876,10 +77574,8 @@ end // initial
       fifo_addr_1 <= 32'h0;
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_1 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
-    end else if (axi_mstr_sel) begin
-      fifo_addr_1 <= wrbuf_addr;
     end else begin
-      fifo_addr_1 <= rdbuf_addr;
+      fifo_addr_1 <= 32'h0;
     end
   end
   always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
@@ -79888,77 +77584,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_addr_0 <= io_dbg_dma_dbg_ib_dbg_cmd_addr;
     end else begin
-      fifo_addr_0 <= bus_cmd_addr;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_vld <= 1'h0;
-    end else begin
-      wrbuf_vld <= _T_1224 & _T_1225;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_data_vld <= 1'h0;
-    end else begin
-      wrbuf_data_vld <= _T_1228 & _T_1229;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      rdbuf_vld <= 1'h0;
-    end else begin
-      rdbuf_vld <= _T_1237 & _T_1238;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      axi_mstr_priority <= 1'h0;
-    end else if (axi_mstr_prty_en) begin
-      axi_mstr_priority <= axi_mstr_prty_in;
-    end
-  end
-  always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_addr <= 32'h0;
-    end else begin
-      wrbuf_addr <= io_dma_axi_aw_bits_addr;
-    end
-  end
-  always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
-    if (reset) begin
-      rdbuf_addr <= 32'h0;
-    end else begin
-      rdbuf_addr <= io_dma_axi_ar_bits_addr;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_byteen <= 8'h0;
-    end else if (wrbuf_data_en) begin
-      wrbuf_byteen <= io_dma_axi_w_bits_strb;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_sz <= 3'h0;
-    end else if (wrbuf_en) begin
-      wrbuf_sz <= io_dma_axi_aw_bits_size;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      rdbuf_sz <= 3'h0;
-    end else if (rdbuf_en) begin
-      rdbuf_sz <= io_dma_axi_ar_bits_size;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      fifo_full <= 1'h0;
-    end else begin
-      fifo_full <= num_fifo_vld >= 4'h5;
+      fifo_addr_0 <= 32'h0;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
@@ -80090,10 +77716,8 @@ end // initial
     end else if (fifo_cmd_en[4]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_4 <= _T_23;
-      end else if (axi_mstr_sel) begin
-        fifo_sz_4 <= wrbuf_sz;
       end else begin
-        fifo_sz_4 <= rdbuf_sz;
+        fifo_sz_4 <= 3'h0;
       end
     end
   end
@@ -80103,10 +77727,8 @@ end // initial
     end else if (fifo_cmd_en[3]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_3 <= _T_23;
-      end else if (axi_mstr_sel) begin
-        fifo_sz_3 <= wrbuf_sz;
       end else begin
-        fifo_sz_3 <= rdbuf_sz;
+        fifo_sz_3 <= 3'h0;
       end
     end
   end
@@ -80116,10 +77738,8 @@ end // initial
     end else if (fifo_cmd_en[2]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_2 <= _T_23;
-      end else if (axi_mstr_sel) begin
-        fifo_sz_2 <= wrbuf_sz;
       end else begin
-        fifo_sz_2 <= rdbuf_sz;
+        fifo_sz_2 <= 3'h0;
       end
     end
   end
@@ -80129,10 +77749,8 @@ end // initial
     end else if (fifo_cmd_en[1]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         fifo_sz_1 <= _T_23;
-      end else if (axi_mstr_sel) begin
-        fifo_sz_1 <= wrbuf_sz;
       end else begin
-        fifo_sz_1 <= rdbuf_sz;
+        fifo_sz_1 <= 3'h0;
       end
     end
   end
@@ -80216,7 +77834,7 @@ end // initial
   always @(posedge dma_free_clk or posedge reset) begin
     if (reset) begin
       RspPtr <= 3'h0;
-    end else if (RspPtrEn) begin
+    end else if (io_dma_dbg_cmd_done) begin
       if (_T_941) begin
         RspPtr <= 3'h0;
       end else begin
@@ -80224,13 +77842,6 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_data <= 64'h0;
-    end else begin
-      wrbuf_data <= io_dma_axi_w_bits_data;
-    end
-  end
   always @(posedge dma_free_clk or posedge reset) begin
     if (reset) begin
       _T_721 <= 1'h0;
@@ -80305,52 +77916,28 @@ end // initial
     if (reset) begin
       _T_850 <= 1'h0;
     end else if (fifo_cmd_en[0]) begin
-      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
-        _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1261) begin
-        _T_850 <= axi_mstr_priority;
-      end else begin
-        _T_850 <= _T_1260;
-      end
+      _T_850 <= fifo_write_in;
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_852 <= 1'h0;
     end else if (fifo_cmd_en[1]) begin
-      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
-        _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1261) begin
-        _T_852 <= axi_mstr_priority;
-      end else begin
-        _T_852 <= _T_1260;
-      end
+      _T_852 <= fifo_write_in;
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_854 <= 1'h0;
     end else if (fifo_cmd_en[2]) begin
-      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
-        _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1261) begin
-        _T_854 <= axi_mstr_priority;
-      end else begin
-        _T_854 <= _T_1260;
-      end
+      _T_854 <= fifo_write_in;
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
     if (reset) begin
       _T_856 <= 1'h0;
     end else if (fifo_cmd_en[3]) begin
-      if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
-        _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1261) begin
-        _T_856 <= axi_mstr_priority;
-      end else begin
-        _T_856 <= _T_1260;
-      end
+      _T_856 <= fifo_write_in;
     end
   end
   always @(posedge dma_buffer_c1_clk or posedge reset) begin
@@ -80372,7 +77959,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_0 <= _T_498;
     end else begin
-      fifo_data_0 <= wrbuf_data;
+      fifo_data_0 <= 64'h0;
     end
   end
   always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
@@ -80387,7 +77974,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_1 <= _T_498;
     end else begin
-      fifo_data_1 <= wrbuf_data;
+      fifo_data_1 <= 64'h0;
     end
   end
   always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
@@ -80402,7 +77989,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_2 <= _T_498;
     end else begin
-      fifo_data_2 <= wrbuf_data;
+      fifo_data_2 <= 64'h0;
     end
   end
   always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
@@ -80417,7 +78004,7 @@ end // initial
     end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
       fifo_data_3 <= _T_498;
     end else begin
-      fifo_data_3 <= wrbuf_data;
+      fifo_data_3 <= 64'h0;
     end
   end
   always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
@@ -80433,71 +78020,6 @@ end // initial
       fifo_data_4 <= _T_500;
     end
   end
-  always @(posedge dma_buffer_c1_clk or posedge reset) begin
-    if (reset) begin
-      fifo_tag_0 <= 1'h0;
-    end else if (fifo_cmd_en[0]) begin
-      if (axi_mstr_sel) begin
-        fifo_tag_0 <= wrbuf_tag;
-      end else begin
-        fifo_tag_0 <= rdbuf_tag;
-      end
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      wrbuf_tag <= 1'h0;
-    end else if (wrbuf_en) begin
-      wrbuf_tag <= io_dma_axi_aw_bits_id;
-    end
-  end
-  always @(posedge dma_bus_clk or posedge reset) begin
-    if (reset) begin
-      rdbuf_tag <= 1'h0;
-    end else if (rdbuf_en) begin
-      rdbuf_tag <= io_dma_axi_ar_bits_id;
-    end
-  end
-  always @(posedge dma_buffer_c1_clk or posedge reset) begin
-    if (reset) begin
-      fifo_tag_1 <= 1'h0;
-    end else if (fifo_cmd_en[1]) begin
-      if (axi_mstr_sel) begin
-        fifo_tag_1 <= wrbuf_tag;
-      end else begin
-        fifo_tag_1 <= rdbuf_tag;
-      end
-    end
-  end
-  always @(posedge dma_buffer_c1_clk or posedge reset) begin
-    if (reset) begin
-      fifo_tag_2 <= 1'h0;
-    end else if (fifo_cmd_en[2]) begin
-      if (axi_mstr_sel) begin
-        fifo_tag_2 <= wrbuf_tag;
-      end else begin
-        fifo_tag_2 <= rdbuf_tag;
-      end
-    end
-  end
-  always @(posedge dma_buffer_c1_clk or posedge reset) begin
-    if (reset) begin
-      fifo_tag_3 <= 1'h0;
-    end else if (fifo_cmd_en[3]) begin
-      if (axi_mstr_sel) begin
-        fifo_tag_3 <= wrbuf_tag;
-      end else begin
-        fifo_tag_3 <= rdbuf_tag;
-      end
-    end
-  end
-  always @(posedge dma_buffer_c1_clk or posedge reset) begin
-    if (reset) begin
-      fifo_tag_4 <= 1'h0;
-    end else if (fifo_cmd_en[4]) begin
-      fifo_tag_4 <= bus_cmd_tag;
-    end
-  end
   always @(posedge dma_free_clk or posedge reset) begin
     if (reset) begin
       dma_nack_count <= 3'h0;
@@ -80520,23 +78042,45 @@ end // initial
   end
 endmodule
 module axi4_to_ahb(
-  input   clock,
-  input   reset,
-  input   io_scan_mode,
-  input   io_bus_clk_en,
-  input   io_clk_override,
-  input   io_axi_awvalid,
-  input   io_axi_wvalid,
-  input   io_axi_bready,
-  input   io_axi_arvalid,
-  input   io_axi_rready,
-  output  io_axi_awready,
-  output  io_axi_wready
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_bus_clk_en,
+  input         io_clk_override,
+  input         io_axi_awvalid,
+  input  [31:0] io_axi_awaddr,
+  input  [2:0]  io_axi_awsize,
+  input         io_axi_wvalid,
+  input  [7:0]  io_axi_wstrb,
+  input         io_axi_bready,
+  input         io_axi_arvalid,
+  input  [31:0] io_axi_araddr,
+  input  [2:0]  io_axi_arsize,
+  input         io_axi_rready,
+  output        io_axi_awready,
+  output        io_axi_wready,
+  input         io_ahb_in_hready,
+  input         io_ahb_in_hresp,
+  output [1:0]  io_ahb_out_htrans,
+  output        io_ahb_out_hwrite
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -80587,20 +78131,42 @@ module axi4_to_ahb(
   wire  wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 172:27]
   wire  master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 173:30]
   wire  _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
+  reg  ahb_hready_q; // @[axi4_to_ahb.scala 392:52]
+  reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 393:52]
+  wire  _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 235:58]
+  wire  _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 235:36]
+  wire  ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 58:27 axi4_to_ahb.scala 405:17]
+  reg  ahb_hwrite_q; // @[axi4_to_ahb.scala 394:57]
+  wire  _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 235:72]
+  wire  _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 235:70]
   wire  _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
+  reg  ahb_hresp_q; // @[axi4_to_ahb.scala 395:52]
+  wire  _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 249:37]
   wire  _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
   wire  _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
   wire  _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
+  wire  _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 281:33]
+  wire  _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 281:48]
   wire  _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
+  wire  _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67]
+  wire  _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67]
+  wire  _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
+  wire  _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
+  wire  _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
+  wire  trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
+  reg  cmd_doneQ; // @[axi4_to_ahb.scala 390:52]
+  wire  _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 291:34]
+  wire  _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 291:50]
   wire  _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
   wire  slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 190:32]
   wire  _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67]
-  wire  _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67]
-  wire  _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
-  wire  _GEN_35 = _T_186 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
-  wire  _GEN_51 = _T_175 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
-  wire  _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67]
-  wire  _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67]
+  wire  _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
+  wire  _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67]
+  wire  _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67]
+  wire  _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67]
+  wire  _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67]
   wire  buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58]
   wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 175:20]
   wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 175:14]
@@ -80616,36 +78182,139 @@ module axi4_to_ahb(
   wire  _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 234:61]
   wire  _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 234:41]
   wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 234:26]
-  wire  _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 292:51]
+  wire  _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 238:174]
+  wire  _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 238:88]
+  wire  _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 246:39]
+  wire  _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 246:37]
+  wire  _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 246:70]
+  wire  _T_142 = ~_T_141; // @[axi4_to_ahb.scala 246:55]
+  wire  _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 246:53]
+  wire  _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 292:36]
+  wire  _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 292:51]
   wire  _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67]
   wire  _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
   wire  _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
   wire  _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
-  wire  _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
-  wire  _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67]
+  wire  _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67]
   wire  master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58]
   wire  _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 248:82]
   wire  _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 248:97]
   wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 248:67]
+  wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 248:26]
   wire  _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 293:42]
+  wire  _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 293:40]
   wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 293:99]
   wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 293:65]
-  wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 293:26]
+  wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 293:26]
   wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67]
   wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67]
   wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58]
+  reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
+  wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 176:21]
+  reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
+  wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 177:21]
+  reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
+  wire  _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 303:55]
+  wire  _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 303:39]
+  wire  _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67]
+  wire  _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
+  wire  _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
+  wire  _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67]
+  wire  _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
+  wire  slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
+  wire  buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 403:12]
   wire  _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 193:56]
   wire  _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 193:91]
   wire  _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 193:74]
   wire  _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 224:54]
   wire  _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 224:38]
   wire  _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 229:51]
+  wire  _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 240:33]
+  wire  _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 255:64]
+  wire  _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 255:48]
+  wire  _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 255:79]
+  wire  _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 301:33]
+  wire  _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 301:48]
+  wire  _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67]
+  wire  _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
+  wire  _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
+  wire  _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
+  wire  _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67]
+  wire  _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67]
+  wire  bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
+  wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 230:49]
+  wire  _T_112 = ~master_valid; // @[axi4_to_ahb.scala 236:34]
+  wire  _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 236:32]
+  reg [31:0] buf_addr; // @[lib.scala 374:16]
+  wire  _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 242:48]
+  wire  _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 242:62]
+  wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 242:36]
+  wire  _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 257:63]
+  wire  _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 257:78]
+  wire  _T_171 = ~_T_170; // @[axi4_to_ahb.scala 257:47]
+  wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 257:36]
+  wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 267:41]
+  reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
+  reg [7:0] buf_byteen; // @[Reg.scala 27:20]
+  wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 168:52]
+  wire  _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 169:48]
+  wire  _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 169:62]
+  wire  _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 169:48]
+  wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
+  wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16]
+  wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16]
+  wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16]
+  wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16]
+  wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16]
+  wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16]
+  wire  _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 286:65]
+  reg  buf_aligned; // @[Reg.scala 27:20]
+  wire  _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 286:44]
+  wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 286:92]
+  wire  _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 286:163]
+  wire  _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 286:79]
+  wire  _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 286:29]
+  wire  _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 300:38]
+  wire  _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 299:80]
+  wire  _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 299:34]
+  wire  _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67]
+  wire  _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67]
+  wire  _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
+  wire  _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
+  wire  _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67]
+  wire  _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67]
+  wire  cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
+  wire  _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 287:47]
+  wire  _T_277 = ~_T_276; // @[axi4_to_ahb.scala 287:36]
+  wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 287:61]
   wire  _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 297:62]
   wire  _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 297:33]
+  wire  _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 302:61]
+  wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 302:75]
+  wire  _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 305:40]
   wire  _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67]
   wire  _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
   wire  _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
@@ -80654,18 +78323,65 @@ module axi4_to_ahb(
   wire  _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67]
   wire  buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58]
   wire  _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67]
+  wire  _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67]
+  wire  _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
   wire  _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67]
   wire  _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67]
   wire  _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67]
   wire  _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67]
+  wire  _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67]
   wire  _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67]
   wire  _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67]
   wire  _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67]
   wire  _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
   wire  _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67]
+  wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67]
   wire  _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
+  wire  _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
   wire  buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58]
+  wire  buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58]
   wire  slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
+  wire  _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 342:24]
+  wire  _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 341:48]
+  wire  _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 342:54]
+  wire  _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 342:33]
+  wire  _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 342:93]
+  wire  _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 342:72]
+  wire  _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 343:25]
+  wire  _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 343:62]
+  wire  _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 343:97]
+  wire  _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 343:74]
+  wire  _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 343:132]
+  wire  _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 343:109]
+  wire  _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 343:168]
+  wire  _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 343:145]
+  wire  _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 344:28]
+  wire  _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 343:181]
+  wire  _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 344:63]
+  wire  _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 344:40]
+  wire  _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 344:99]
+  wire  _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 344:76]
+  wire  _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 343:38]
+  wire  buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 342:106]
+  wire  _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 336:60]
+  wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 161:15]
+  wire  _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 162:56]
+  wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 162:15]
+  wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 161:63]
+  wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 163:15]
+  wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 162:96]
+  wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 336:43]
+  reg  buf_write; // @[Reg.scala 27:20]
   wire  wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 362:47]
   wire  wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 363:50]
   wire  wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 364:49]
@@ -80679,8 +78395,11 @@ module axi4_to_ahb(
   wire  _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 372:55]
   wire  _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 372:91]
   wire  _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 373:55]
+  wire  _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 390:92]
   wire  _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 398:43]
   wire  _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 398:58]
+  wire  _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 399:57]
+  wire  _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 399:81]
   wire  _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 400:50]
   wire  _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 400:60]
   rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
@@ -80745,6 +78464,8 @@ module axi4_to_ahb(
   );
   assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 367:18]
   assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 368:17]
+  assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 199:21 axi4_to_ahb.scala 230:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25 axi4_to_ahb.scala 267:25 axi4_to_ahb.scala 287:25 axi4_to_ahb.scala 302:25]
+  assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 352:21]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
@@ -80770,7 +78491,7 @@ module axi4_to_ahb(
   assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_8_io_en = io_bus_clk_en & io_clk_override; // @[lib.scala 345:16]
+  assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16]
@@ -80816,6 +78537,32 @@ initial begin
   wrbuf_vld = _RAND_1[0:0];
   _RAND_2 = {1{`RANDOM}};
   wrbuf_data_vld = _RAND_2[0:0];
+  _RAND_3 = {1{`RANDOM}};
+  ahb_hready_q = _RAND_3[0:0];
+  _RAND_4 = {1{`RANDOM}};
+  ahb_htrans_q = _RAND_4[1:0];
+  _RAND_5 = {1{`RANDOM}};
+  ahb_hwrite_q = _RAND_5[0:0];
+  _RAND_6 = {1{`RANDOM}};
+  ahb_hresp_q = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  cmd_doneQ = _RAND_7[0:0];
+  _RAND_8 = {1{`RANDOM}};
+  wrbuf_addr = _RAND_8[31:0];
+  _RAND_9 = {1{`RANDOM}};
+  wrbuf_size = _RAND_9[2:0];
+  _RAND_10 = {1{`RANDOM}};
+  wrbuf_byteen = _RAND_10[7:0];
+  _RAND_11 = {1{`RANDOM}};
+  buf_addr = _RAND_11[31:0];
+  _RAND_12 = {1{`RANDOM}};
+  buf_cmd_byte_ptrQ = _RAND_12[2:0];
+  _RAND_13 = {1{`RANDOM}};
+  buf_byteen = _RAND_13[7:0];
+  _RAND_14 = {1{`RANDOM}};
+  buf_aligned = _RAND_14[0:0];
+  _RAND_15 = {1{`RANDOM}};
+  buf_write = _RAND_15[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     buf_state = 3'h0;
@@ -80826,6 +78573,45 @@ initial begin
   if (reset) begin
     wrbuf_data_vld = 1'h0;
   end
+  if (reset) begin
+    ahb_hready_q = 1'h0;
+  end
+  if (reset) begin
+    ahb_htrans_q = 2'h0;
+  end
+  if (reset) begin
+    ahb_hwrite_q = 1'h0;
+  end
+  if (reset) begin
+    ahb_hresp_q = 1'h0;
+  end
+  if (reset) begin
+    cmd_doneQ = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    wrbuf_size = 3'h0;
+  end
+  if (reset) begin
+    wrbuf_byteen = 8'h0;
+  end
+  if (reset) begin
+    buf_addr = 32'h0;
+  end
+  if (reset) begin
+    buf_cmd_byte_ptrQ = 3'h0;
+  end
+  if (reset) begin
+    buf_byteen = 8'h0;
+  end
+  if (reset) begin
+    buf_aligned = 1'h0;
+  end
+  if (reset) begin
+    buf_write = 1'h0;
+  end
   `endif // RANDOMIZE
 end // initial
 `ifdef FIRRTL_AFTER_INITIAL
@@ -80849,7 +78635,9 @@ end // initial
           buf_state <= 3'h3;
         end
       end else if (_T_136) begin
-        if (_T_152) begin
+        if (ahb_hresp_q) begin
+          buf_state <= 3'h7;
+        end else if (_T_152) begin
           buf_state <= 3'h6;
         end else begin
           buf_state <= 3'h3;
@@ -80861,7 +78649,7 @@ end // initial
       end else if (_T_188) begin
         buf_state <= 3'h4;
       end else if (_T_281) begin
-        if (_T_287) begin
+        if (_T_288) begin
           buf_state <= 3'h5;
         end else if (master_valid) begin
           if (_T_51) begin
@@ -80891,25 +78679,240 @@ end // initial
       wrbuf_data_vld <= _T_641 & _T_637;
     end
   end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hready_q <= 1'h0;
+    end else begin
+      ahb_hready_q <= io_ahb_in_hready;
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      ahb_htrans_q <= 2'h0;
+    end else begin
+      ahb_htrans_q <= io_ahb_out_htrans;
+    end
+  end
+  always @(posedge ahbm_addr_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hwrite_q <= 1'h0;
+    end else begin
+      ahb_hwrite_q <= io_ahb_out_hwrite;
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hresp_q <= 1'h0;
+    end else begin
+      ahb_hresp_q <= io_ahb_in_hresp;
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      cmd_doneQ <= 1'h0;
+    end else begin
+      cmd_doneQ <= _T_276 & _T_691;
+    end
+  end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_addr <= 32'h0;
+    end else begin
+      wrbuf_addr <= io_axi_awaddr;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_size <= 3'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_size <= io_axi_awsize;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_byteen <= 8'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_byteen <= io_axi_wstrb;
+    end
+  end
+  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+    if (reset) begin
+      buf_addr <= 32'h0;
+    end else begin
+      buf_addr <= {master_addr[31:3],_T_485};
+    end
+  end
+  always @(posedge ahbm_clk or posedge reset) begin
+    if (reset) begin
+      buf_cmd_byte_ptrQ <= 3'h0;
+    end else if (buf_cmd_byte_ptr_en) begin
+      if (_T_49) begin
+        if (buf_write_in) begin
+          if (wrbuf_byteen[0]) begin
+            buf_cmd_byte_ptrQ <= 3'h0;
+          end else if (wrbuf_byteen[1]) begin
+            buf_cmd_byte_ptrQ <= 3'h1;
+          end else if (wrbuf_byteen[2]) begin
+            buf_cmd_byte_ptrQ <= 3'h2;
+          end else if (wrbuf_byteen[3]) begin
+            buf_cmd_byte_ptrQ <= 3'h3;
+          end else if (wrbuf_byteen[4]) begin
+            buf_cmd_byte_ptrQ <= 3'h4;
+          end else if (wrbuf_byteen[5]) begin
+            buf_cmd_byte_ptrQ <= 3'h5;
+          end else if (wrbuf_byteen[6]) begin
+            buf_cmd_byte_ptrQ <= 3'h6;
+          end else begin
+            buf_cmd_byte_ptrQ <= 3'h7;
+          end
+        end else begin
+          buf_cmd_byte_ptrQ <= master_addr[2:0];
+        end
+      end else if (_T_101) begin
+        if (bypass_en) begin
+          buf_cmd_byte_ptrQ <= master_addr[2:0];
+        end else begin
+          buf_cmd_byte_ptrQ <= buf_addr[2:0];
+        end
+      end else if (_T_136) begin
+        if (bypass_en) begin
+          buf_cmd_byte_ptrQ <= master_addr[2:0];
+        end else begin
+          buf_cmd_byte_ptrQ <= buf_addr[2:0];
+        end
+      end else if (_T_175) begin
+        buf_cmd_byte_ptrQ <= buf_addr[2:0];
+      end else if (_T_186) begin
+        buf_cmd_byte_ptrQ <= 3'h0;
+      end else if (_T_188) begin
+        if (trxn_done) begin
+          if (_T_201) begin
+            buf_cmd_byte_ptrQ <= 3'h0;
+          end else if (_T_204) begin
+            buf_cmd_byte_ptrQ <= 3'h1;
+          end else if (_T_207) begin
+            buf_cmd_byte_ptrQ <= 3'h2;
+          end else if (_T_210) begin
+            buf_cmd_byte_ptrQ <= 3'h3;
+          end else if (_T_213) begin
+            buf_cmd_byte_ptrQ <= 3'h4;
+          end else if (_T_216) begin
+            buf_cmd_byte_ptrQ <= 3'h5;
+          end else if (_T_219) begin
+            buf_cmd_byte_ptrQ <= 3'h6;
+          end else begin
+            buf_cmd_byte_ptrQ <= 3'h7;
+          end
+        end
+      end else if (_T_281) begin
+        if (bypass_en) begin
+          if (wrbuf_byteen[0]) begin
+            buf_cmd_byte_ptrQ <= 3'h0;
+          end else if (wrbuf_byteen[1]) begin
+            buf_cmd_byte_ptrQ <= 3'h1;
+          end else if (wrbuf_byteen[2]) begin
+            buf_cmd_byte_ptrQ <= 3'h2;
+          end else if (wrbuf_byteen[3]) begin
+            buf_cmd_byte_ptrQ <= 3'h3;
+          end else if (wrbuf_byteen[4]) begin
+            buf_cmd_byte_ptrQ <= 3'h4;
+          end else if (wrbuf_byteen[5]) begin
+            buf_cmd_byte_ptrQ <= 3'h5;
+          end else if (wrbuf_byteen[6]) begin
+            buf_cmd_byte_ptrQ <= 3'h6;
+          end else begin
+            buf_cmd_byte_ptrQ <= 3'h7;
+          end
+        end else if (trxn_done) begin
+          if (_T_201) begin
+            buf_cmd_byte_ptrQ <= 3'h0;
+          end else if (_T_204) begin
+            buf_cmd_byte_ptrQ <= 3'h1;
+          end else if (_T_207) begin
+            buf_cmd_byte_ptrQ <= 3'h2;
+          end else if (_T_210) begin
+            buf_cmd_byte_ptrQ <= 3'h3;
+          end else if (_T_213) begin
+            buf_cmd_byte_ptrQ <= 3'h4;
+          end else if (_T_216) begin
+            buf_cmd_byte_ptrQ <= 3'h5;
+          end else if (_T_219) begin
+            buf_cmd_byte_ptrQ <= 3'h6;
+          end else begin
+            buf_cmd_byte_ptrQ <= 3'h7;
+          end
+        end
+      end else begin
+        buf_cmd_byte_ptrQ <= 3'h0;
+      end
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_byteen <= 8'h0;
+    end else if (buf_wr_en) begin
+      buf_byteen <= wrbuf_byteen;
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_aligned <= 1'h0;
+    end else if (buf_wr_en) begin
+      buf_aligned <= buf_aligned_in;
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_write <= 1'h0;
+    end else if (buf_wr_en) begin
+      if (_T_49) begin
+        buf_write <= _T_51;
+      end else if (_T_101) begin
+        buf_write <= 1'h0;
+      end else if (_T_136) begin
+        buf_write <= 1'h0;
+      end else if (_T_175) begin
+        buf_write <= 1'h0;
+      end else if (_T_186) begin
+        buf_write <= 1'h0;
+      end else if (_T_188) begin
+        buf_write <= 1'h0;
+      end else begin
+        buf_write <= _GEN_8;
+      end
+    end
+  end
 endmodule
 module ahb_to_axi4(
-  input        clock,
-  input        reset,
-  input        io_scan_mode,
-  input        io_bus_clk_en,
-  input        io_axi_awready,
-  input        io_axi_arready,
-  input        io_axi_rvalid,
-  input  [1:0] io_axi_rresp,
-  output       io_axi_awvalid,
-  output       io_axi_arvalid,
-  output       io_ahb_sig_in_hresp
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_bus_clk_en,
+  input         io_axi_awready,
+  input         io_axi_arready,
+  input  [1:0]  io_axi_rresp,
+  output        io_axi_awvalid,
+  output        io_axi_arvalid,
+  output        io_ahb_sig_in_hready,
+  output        io_ahb_sig_in_hresp,
+  input  [31:0] io_ahb_sig_out_haddr,
+  input  [2:0]  io_ahb_sig_out_hsize,
+  input  [1:0]  io_ahb_sig_out_htrans,
+  input         io_ahb_sig_out_hwrite,
+  input         io_ahb_hsel,
+  input         io_ahb_hreadyin
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
   reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
@@ -80935,10 +78938,21 @@ module ahb_to_axi4(
   wire  rvclkhdr_5_io_clk; // @[lib.scala 343:22]
   wire  rvclkhdr_5_io_en; // @[lib.scala 343:22]
   wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22]
+  wire  ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 90:33 ahb_to_axi4.scala 179:31]
+  reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 172:65]
+  wire  ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29]
+  wire  ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29]
   wire  ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 89:33 ahb_to_axi4.scala 178:31]
   reg [1:0] buf_state; // @[Reg.scala 27:20]
   wire  _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
+  wire  ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 150:55]
+  wire  _T_9 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 122:34]
+  wire  _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 122:61]
   wire  _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
+  wire  _T_13 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 125:79]
+  wire  _T_14 = io_ahb_sig_in_hresp | _T_13; // @[ahb_to_axi4.scala 125:48]
+  wire  _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 125:93]
+  wire  _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 125:91]
   wire  bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 103:33 ahb_to_axi4.scala 228:27]
   reg  cmdbuf_vld; // @[ahb_to_axi4.scala 185:61]
   wire  _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 183:66]
@@ -80948,16 +78962,21 @@ module ahb_to_axi4(
   wire  cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 183:46]
   wire  _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 126:24]
   wire  _T_21 = _T_20 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 126:37]
-  wire  _T_27 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 127:38]
+  wire  _T_24 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 127:92]
+  wire  _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 127:110]
+  wire  _T_26 = io_ahb_sig_in_hresp | _T_25; // @[ahb_to_axi4.scala 127:60]
+  wire  _T_27 = ~_T_26; // @[ahb_to_axi4.scala 127:38]
   wire  _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 127:36]
   wire  _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
-  wire  _T_35 = _T_27 & _T_20; // @[ahb_to_axi4.scala 132:44]
+  wire  _T_33 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 132:23]
+  wire  _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 132:44]
   wire  _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
+  reg  cmdbuf_write; // @[Reg.scala 27:20]
+  wire  _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 136:39]
   wire  _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 138:62]
-  wire  _GEN_1 = _T_36 & io_axi_rvalid; // @[Conditional.scala 39:67]
-  wire  _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67]
+  wire  _GEN_5 = _T_29 & _T_21; // @[Conditional.scala 39:67]
   wire  _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67]
-  wire  buf_state_en = _T_6 ? 1'h0 : _GEN_10; // @[Conditional.scala 40:58]
+  wire  buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58]
   wire  _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 138:41]
   wire  _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67]
   wire  _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67]
@@ -80967,11 +78986,54 @@ module ahb_to_axi4(
   wire  _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
   wire  cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
   wire  buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
+  reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 170:65]
+  wire  _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 144:30]
+  wire  _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 145:30]
+  wire  _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 146:30]
+  reg  ahb_hready_q; // @[ahb_to_axi4.scala 168:60]
+  wire  _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 149:80]
   reg  ahb_hresp_q; // @[ahb_to_axi4.scala 167:60]
+  wire  _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 149:78]
+  wire  _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 149:124]
+  wire  _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 149:111]
+  wire  _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 149:149]
+  wire  _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 149:168]
+  wire  _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 149:156]
+  wire  _T_81 = ~_T_80; // @[ahb_to_axi4.scala 149:137]
+  wire  _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 149:135]
   reg  buf_read_error; // @[ahb_to_axi4.scala 164:60]
+  wire  _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 149:181]
+  wire  _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 149:179]
+  wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 169:60]
+  wire  _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 153:61]
+  wire  _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 153:83]
+  wire  _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 153:70]
+  wire  _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 154:26]
+  wire  _T_97 = ~_T_96; // @[ahb_to_axi4.scala 154:7]
+  reg  ahb_hwrite_q; // @[ahb_to_axi4.scala 171:65]
+  wire  _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 155:46]
+  wire  _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 155:26]
+  wire  _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 155:86]
+  wire  _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 155:115]
+  wire  _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 155:95]
+  wire  _T_105 = ~_T_104; // @[ahb_to_axi4.scala 155:66]
+  wire  _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 155:64]
+  wire  _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 154:47]
+  wire  _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 156:35]
+  wire  _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 155:126]
+  wire  _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 157:56]
+  wire  _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 157:35]
+  wire  _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 156:55]
+  wire  _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 158:56]
+  wire  _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 158:35]
+  wire  _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 157:61]
+  wire  _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 153:94]
+  wire  _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 158:63]
   wire  _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 182:109]
   wire  _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 182:107]
-  wire  cmdbuf_rst = _T_146 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 182:124]
+  wire  _T_148 = io_ahb_sig_in_hresp & _T_37; // @[ahb_to_axi4.scala 182:147]
+  wire  cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 182:124]
   wire  _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 185:66]
   wire  _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 185:110]
   rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
@@ -81010,14 +79072,15 @@ module ahb_to_axi4(
     .io_en(rvclkhdr_5_io_en),
     .io_scan_mode(rvclkhdr_5_io_scan_mode)
   );
-  assign io_axi_awvalid = 1'h0; // @[ahb_to_axi4.scala 202:27]
-  assign io_axi_arvalid = cmdbuf_vld; // @[ahb_to_axi4.scala 217:27]
-  assign io_ahb_sig_in_hresp = buf_read_error | ahb_hresp_q; // @[ahb_to_axi4.scala 153:38]
+  assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 202:27]
+  assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 217:27]
+  assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 149:38]
+  assign io_ahb_sig_in_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 153:38]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_1_io_en = 1'h0; // @[lib.scala 345:16]
+  assign rvclkhdr_1_io_en = io_bus_clk_en & _T_9; // @[lib.scala 345:16]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
   assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16]
@@ -81067,40 +79130,87 @@ initial begin
     `endif
 `ifdef RANDOMIZE_REG_INIT
   _RAND_0 = {1{`RANDOM}};
-  buf_state = _RAND_0[1:0];
+  ahb_haddr_q = _RAND_0[31:0];
   _RAND_1 = {1{`RANDOM}};
-  cmdbuf_vld = _RAND_1[0:0];
+  buf_state = _RAND_1[1:0];
   _RAND_2 = {1{`RANDOM}};
-  ahb_hresp_q = _RAND_2[0:0];
+  cmdbuf_vld = _RAND_2[0:0];
   _RAND_3 = {1{`RANDOM}};
-  buf_read_error = _RAND_3[0:0];
+  cmdbuf_write = _RAND_3[0:0];
+  _RAND_4 = {1{`RANDOM}};
+  ahb_hsize_q = _RAND_4[2:0];
+  _RAND_5 = {1{`RANDOM}};
+  ahb_hready_q = _RAND_5[0:0];
+  _RAND_6 = {1{`RANDOM}};
+  ahb_hresp_q = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  buf_read_error = _RAND_7[0:0];
+  _RAND_8 = {1{`RANDOM}};
+  ahb_htrans_q = _RAND_8[1:0];
+  _RAND_9 = {1{`RANDOM}};
+  ahb_hwrite_q = _RAND_9[0:0];
 `endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    ahb_haddr_q = 32'h0;
+  end
   if (reset) begin
     buf_state = 2'h0;
   end
   if (reset) begin
     cmdbuf_vld = 1'h0;
   end
+  if (reset) begin
+    cmdbuf_write = 1'h0;
+  end
+  if (reset) begin
+    ahb_hsize_q = 3'h0;
+  end
+  if (reset) begin
+    ahb_hready_q = 1'h0;
+  end
   if (reset) begin
     ahb_hresp_q = 1'h0;
   end
   if (reset) begin
     buf_read_error = 1'h0;
   end
+  if (reset) begin
+    ahb_htrans_q = 2'h0;
+  end
+  if (reset) begin
+    ahb_hwrite_q = 1'h0;
+  end
   `endif // RANDOMIZE
 end // initial
 `ifdef FIRRTL_AFTER_INITIAL
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
+  always @(posedge ahb_addr_clk or posedge reset) begin
+    if (reset) begin
+      ahb_haddr_q <= 32'h0;
+    end else begin
+      ahb_haddr_q <= io_ahb_sig_out_haddr;
+    end
+  end
   always @(posedge ahb_clk or posedge reset) begin
     if (reset) begin
       buf_state <= 2'h0;
     end else if (buf_state_en) begin
       if (_T_6) begin
-        buf_state <= 2'h2;
+        if (io_ahb_sig_out_hwrite) begin
+          buf_state <= 2'h1;
+        end else begin
+          buf_state <= 2'h2;
+        end
       end else if (_T_11) begin
-        buf_state <= 2'h0;
+        if (_T_16) begin
+          buf_state <= 2'h0;
+        end else if (io_ahb_sig_out_hwrite) begin
+          buf_state <= 2'h1;
+        end else begin
+          buf_state <= 2'h2;
+        end
       end else if (_T_29) begin
         if (io_ahb_sig_in_hresp) begin
           buf_state <= 2'h0;
@@ -81119,6 +79229,27 @@ end // initial
       cmdbuf_vld <= _T_156 & _T_157;
     end
   end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      cmdbuf_write <= 1'h0;
+    end else if (cmdbuf_wr_en) begin
+      cmdbuf_write <= ahb_hwrite_q;
+    end
+  end
+  always @(posedge ahb_addr_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hsize_q <= 3'h0;
+    end else begin
+      ahb_hsize_q <= io_ahb_sig_out_hsize;
+    end
+  end
+  always @(posedge ahb_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hready_q <= 1'h0;
+    end else begin
+      ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin;
+    end
+  end
   always @(posedge ahb_clk or posedge reset) begin
     if (reset) begin
       ahb_hresp_q <= 1'h0;
@@ -81139,94 +79270,69 @@ end // initial
       buf_read_error <= _GEN_3;
     end
   end
+  always @(posedge ahb_clk or posedge reset) begin
+    if (reset) begin
+      ahb_htrans_q <= 2'h0;
+    end else begin
+      ahb_htrans_q <= _T_88 & io_ahb_sig_out_htrans;
+    end
+  end
+  always @(posedge ahb_addr_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hwrite_q <= 1'h0;
+    end else begin
+      ahb_hwrite_q <= io_ahb_sig_out_hwrite;
+    end
+  end
 endmodule
 module quasar(
   input         clock,
   input         reset,
-  input         io_lsu_axi_aw_ready,
   output        io_lsu_axi_aw_valid,
-  output [2:0]  io_lsu_axi_aw_bits_id,
   output [31:0] io_lsu_axi_aw_bits_addr,
-  output [3:0]  io_lsu_axi_aw_bits_region,
   output [2:0]  io_lsu_axi_aw_bits_size,
-  output [3:0]  io_lsu_axi_aw_bits_cache,
-  input         io_lsu_axi_w_ready,
   output        io_lsu_axi_w_valid,
-  output [63:0] io_lsu_axi_w_bits_data,
   output [7:0]  io_lsu_axi_w_bits_strb,
   output        io_lsu_axi_b_ready,
-  input         io_lsu_axi_b_valid,
-  input  [1:0]  io_lsu_axi_b_bits_resp,
-  input  [2:0]  io_lsu_axi_b_bits_id,
-  input         io_lsu_axi_ar_ready,
   output        io_lsu_axi_ar_valid,
-  output [2:0]  io_lsu_axi_ar_bits_id,
   output [31:0] io_lsu_axi_ar_bits_addr,
-  output [3:0]  io_lsu_axi_ar_bits_region,
   output [2:0]  io_lsu_axi_ar_bits_size,
-  output [3:0]  io_lsu_axi_ar_bits_cache,
   output        io_lsu_axi_r_ready,
-  input         io_lsu_axi_r_valid,
-  input  [2:0]  io_lsu_axi_r_bits_id,
-  input  [63:0] io_lsu_axi_r_bits_data,
-  input  [1:0]  io_lsu_axi_r_bits_resp,
   output        io_ifu_axi_aw_valid,
+  output [31:0] io_ifu_axi_aw_bits_addr,
+  output [2:0]  io_ifu_axi_aw_bits_size,
   output        io_ifu_axi_w_valid,
+  output [7:0]  io_ifu_axi_w_bits_strb,
   output        io_ifu_axi_b_ready,
-  input         io_ifu_axi_ar_ready,
   output        io_ifu_axi_ar_valid,
-  output [2:0]  io_ifu_axi_ar_bits_id,
   output [31:0] io_ifu_axi_ar_bits_addr,
-  output [3:0]  io_ifu_axi_ar_bits_region,
+  output [2:0]  io_ifu_axi_ar_bits_size,
   output        io_ifu_axi_r_ready,
-  input         io_ifu_axi_r_valid,
-  input  [2:0]  io_ifu_axi_r_bits_id,
-  input  [63:0] io_ifu_axi_r_bits_data,
-  input  [1:0]  io_ifu_axi_r_bits_resp,
-  input         io_sb_axi_aw_ready,
   output        io_sb_axi_aw_valid,
   output [31:0] io_sb_axi_aw_bits_addr,
-  output [3:0]  io_sb_axi_aw_bits_region,
   output [2:0]  io_sb_axi_aw_bits_size,
-  input         io_sb_axi_w_ready,
   output        io_sb_axi_w_valid,
-  output [63:0] io_sb_axi_w_bits_data,
   output [7:0]  io_sb_axi_w_bits_strb,
   output        io_sb_axi_b_ready,
-  input         io_sb_axi_b_valid,
-  input  [1:0]  io_sb_axi_b_bits_resp,
-  input         io_sb_axi_ar_ready,
   output        io_sb_axi_ar_valid,
   output [31:0] io_sb_axi_ar_bits_addr,
-  output [3:0]  io_sb_axi_ar_bits_region,
   output [2:0]  io_sb_axi_ar_bits_size,
   output        io_sb_axi_r_ready,
-  input         io_sb_axi_r_valid,
-  input  [63:0] io_sb_axi_r_bits_data,
-  input  [1:0]  io_sb_axi_r_bits_resp,
   output        io_dma_axi_aw_ready,
-  input         io_dma_axi_aw_valid,
-  input         io_dma_axi_aw_bits_id,
-  input  [31:0] io_dma_axi_aw_bits_addr,
-  input  [2:0]  io_dma_axi_aw_bits_size,
-  output        io_dma_axi_w_ready,
-  input         io_dma_axi_w_valid,
-  input  [63:0] io_dma_axi_w_bits_data,
-  input  [7:0]  io_dma_axi_w_bits_strb,
-  input         io_dma_axi_b_ready,
-  output        io_dma_axi_b_valid,
-  output [1:0]  io_dma_axi_b_bits_resp,
-  output        io_dma_axi_b_bits_id,
   output        io_dma_axi_ar_ready,
-  input         io_dma_axi_ar_valid,
-  input         io_dma_axi_ar_bits_id,
-  input  [31:0] io_dma_axi_ar_bits_addr,
-  input  [2:0]  io_dma_axi_ar_bits_size,
-  input         io_dma_axi_r_ready,
-  output        io_dma_axi_r_valid,
-  output        io_dma_axi_r_bits_id,
-  output [63:0] io_dma_axi_r_bits_data,
   output [1:0]  io_dma_axi_r_bits_resp,
+  input         io_ahb_in_hready,
+  input         io_ahb_in_hresp,
+  input         io_lsu_ahb_in_hready,
+  input         io_lsu_ahb_in_hresp,
+  input         io_sb_ahb_in_hready,
+  input         io_sb_ahb_in_hresp,
+  input  [31:0] io_dma_ahb_out_haddr,
+  input  [2:0]  io_dma_ahb_out_hsize,
+  input  [1:0]  io_dma_ahb_out_htrans,
+  input         io_dma_ahb_out_hwrite,
+  input         io_dma_hsel,
+  input         io_dma_hreadyin,
   input         io_dbg_rst_l,
   input  [30:0] io_rst_vec,
   input         io_nmi_int,
@@ -81271,10 +79377,7 @@ module quasar(
   input  [38:0] io_dccm_rd_data_hi,
   output [30:0] io_ic_rw_addr,
   output [1:0]  io_ic_tag_valid,
-  output [1:0]  io_ic_wr_en,
   output        io_ic_rd_en,
-  output [70:0] io_ic_wr_data_0,
-  output [70:0] io_ic_wr_data_1,
   output [70:0] io_ic_debug_wr_data,
   output [9:0]  io_ic_debug_addr,
   input  [63:0] io_ic_rd_data,
@@ -81352,7 +79455,6 @@ module quasar(
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 125:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 125:19]
   wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 125:19]
@@ -81396,10 +79498,7 @@ module quasar(
   wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 125:19]
   wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 125:19]
   wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 125:19]
-  wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 125:19]
   wire  ifu_io_ic_rd_en; // @[quasar.scala 125:19]
-  wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 125:19]
-  wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 125:19]
   wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 125:19]
   wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 125:19]
   wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 125:19]
@@ -81414,15 +79513,8 @@ module quasar(
   wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 125:19]
   wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 125:19]
   wire  ifu_io_ic_sel_premux_data; // @[quasar.scala 125:19]
-  wire  ifu_io_ifu_ar_ready; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_ar_valid; // @[quasar.scala 125:19]
-  wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 125:19]
   wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 125:19]
-  wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 125:19]
-  wire  ifu_io_ifu_r_valid; // @[quasar.scala 125:19]
-  wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 125:19]
-  wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 125:19]
-  wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_bus_clk_en; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 125:19]
   wire  ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 125:19]
@@ -81579,7 +79671,6 @@ module quasar(
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 126:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 126:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 126:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 126:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 126:19]
   wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 126:19]
   wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 126:19]
@@ -81672,7 +79763,6 @@ module quasar(
   wire  dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 126:19]
   wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 126:19]
   wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 126:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19]
   wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19]
@@ -81728,27 +79818,14 @@ module quasar(
   wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 127:19]
   wire  dbg_io_dmi_reg_wr_en; // @[quasar.scala 127:19]
   wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_aw_ready; // @[quasar.scala 127:19]
   wire  dbg_io_sb_axi_aw_valid; // @[quasar.scala 127:19]
   wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 127:19]
-  wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 127:19]
   wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_w_ready; // @[quasar.scala 127:19]
   wire  dbg_io_sb_axi_w_valid; // @[quasar.scala 127:19]
-  wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 127:19]
   wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_b_ready; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_b_valid; // @[quasar.scala 127:19]
-  wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_ar_ready; // @[quasar.scala 127:19]
   wire  dbg_io_sb_axi_ar_valid; // @[quasar.scala 127:19]
   wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 127:19]
-  wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 127:19]
   wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_r_ready; // @[quasar.scala 127:19]
-  wire  dbg_io_sb_axi_r_valid; // @[quasar.scala 127:19]
-  wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 127:19]
-  wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 127:19]
   wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 127:19]
   wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 127:19]
   wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 127:19]
@@ -81893,7 +79970,6 @@ module quasar(
   wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 129:19]
   wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 129:19]
   wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 129:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 129:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 129:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 129:19]
   wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 129:19]
@@ -81923,31 +79999,14 @@ module quasar(
   wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 129:19]
   wire  lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 129:19]
   wire  lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 129:19]
-  wire  lsu_io_axi_aw_ready; // @[quasar.scala 129:19]
   wire  lsu_io_axi_aw_valid; // @[quasar.scala 129:19]
-  wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 129:19]
   wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 129:19]
-  wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 129:19]
   wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 129:19]
-  wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 129:19]
-  wire  lsu_io_axi_w_ready; // @[quasar.scala 129:19]
   wire  lsu_io_axi_w_valid; // @[quasar.scala 129:19]
-  wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 129:19]
   wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 129:19]
-  wire  lsu_io_axi_b_valid; // @[quasar.scala 129:19]
-  wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 129:19]
-  wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 129:19]
-  wire  lsu_io_axi_ar_ready; // @[quasar.scala 129:19]
   wire  lsu_io_axi_ar_valid; // @[quasar.scala 129:19]
-  wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 129:19]
   wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 129:19]
-  wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 129:19]
   wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 129:19]
-  wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 129:19]
-  wire  lsu_io_axi_r_valid; // @[quasar.scala 129:19]
-  wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 129:19]
-  wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 129:19]
-  wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 129:19]
   wire  lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 129:19]
   wire  lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 129:19]
   wire  lsu_io_dec_tlu_force_halt; // @[quasar.scala 129:19]
@@ -82055,28 +80114,8 @@ module quasar(
   wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 131:24]
   wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 131:24]
   wire  dma_ctrl_io_iccm_ready; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 131:24]
-  wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 131:24]
-  wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 131:24]
-  wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 131:24]
-  wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 131:24]
   wire  dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 131:24]
-  wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 131:24]
-  wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 131:24]
-  wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 131:24]
   wire  dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 131:24]
-  wire  dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 131:24]
-  wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 131:24]
   wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 131:24]
   wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 131:24]
   wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 131:24]
@@ -82112,47 +80151,80 @@ module quasar(
   wire  axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_clk_override; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 306:33]
+  wire [31:0] axi4_to_ahb_io_axi_awaddr; // @[quasar.scala 306:33]
+  wire [2:0] axi4_to_ahb_io_axi_awsize; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 306:33]
+  wire [7:0] axi4_to_ahb_io_axi_wstrb; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_bready; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 306:33]
+  wire [31:0] axi4_to_ahb_io_axi_araddr; // @[quasar.scala 306:33]
+  wire [2:0] axi4_to_ahb_io_axi_arsize; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_rready; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_awready; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_io_axi_wready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_ahb_in_hready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_ahb_in_hresp; // @[quasar.scala 306:33]
+  wire [1:0] axi4_to_ahb_io_ahb_out_htrans; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_ahb_out_hwrite; // @[quasar.scala 306:33]
   wire  axi4_to_ahb_1_clock; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_reset; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_clk_override; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 333:33]
+  wire [31:0] axi4_to_ahb_1_io_axi_awaddr; // @[quasar.scala 333:33]
+  wire [2:0] axi4_to_ahb_1_io_axi_awsize; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 333:33]
+  wire [7:0] axi4_to_ahb_1_io_axi_wstrb; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 333:33]
+  wire [31:0] axi4_to_ahb_1_io_axi_araddr; // @[quasar.scala 333:33]
+  wire [2:0] axi4_to_ahb_1_io_axi_arsize; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_ahb_in_hready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_ahb_in_hresp; // @[quasar.scala 333:33]
+  wire [1:0] axi4_to_ahb_1_io_ahb_out_htrans; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_ahb_out_hwrite; // @[quasar.scala 333:33]
   wire  axi4_to_ahb_2_clock; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_reset; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_clk_override; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 361:32]
+  wire [31:0] axi4_to_ahb_2_io_axi_awaddr; // @[quasar.scala 361:32]
+  wire [2:0] axi4_to_ahb_2_io_axi_awsize; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 361:32]
+  wire [7:0] axi4_to_ahb_2_io_axi_wstrb; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 361:32]
+  wire [31:0] axi4_to_ahb_2_io_axi_araddr; // @[quasar.scala 361:32]
+  wire [2:0] axi4_to_ahb_2_io_axi_arsize; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 361:32]
   wire  axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_ahb_in_hready; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_ahb_in_hresp; // @[quasar.scala 361:32]
+  wire [1:0] axi4_to_ahb_2_io_ahb_out_htrans; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_ahb_out_hwrite; // @[quasar.scala 361:32]
   wire  ahb_to_axi4_clock; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_reset; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_scan_mode; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_axi_awready; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_axi_arready; // @[quasar.scala 388:33]
-  wire  ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 388:33]
   wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 388:33]
   wire  ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 388:33]
+  wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 388:33]
+  wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 388:33]
+  wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 388:33]
   wire  _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 133:67]
   wire  _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 133:70]
   wire  _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 134:23]
@@ -82199,7 +80271,6 @@ module quasar(
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
-    .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
     .io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -82243,10 +80314,7 @@ module quasar(
     .io_iccm_rd_data_ecc(ifu_io_iccm_rd_data_ecc),
     .io_ic_rw_addr(ifu_io_ic_rw_addr),
     .io_ic_tag_valid(ifu_io_ic_tag_valid),
-    .io_ic_wr_en(ifu_io_ic_wr_en),
     .io_ic_rd_en(ifu_io_ic_rd_en),
-    .io_ic_wr_data_0(ifu_io_ic_wr_data_0),
-    .io_ic_wr_data_1(ifu_io_ic_wr_data_1),
     .io_ic_debug_wr_data(ifu_io_ic_debug_wr_data),
     .io_ic_debug_addr(ifu_io_ic_debug_addr),
     .io_ic_rd_data(ifu_io_ic_rd_data),
@@ -82261,15 +80329,8 @@ module quasar(
     .io_ic_debug_way(ifu_io_ic_debug_way),
     .io_ic_premux_data(ifu_io_ic_premux_data),
     .io_ic_sel_premux_data(ifu_io_ic_sel_premux_data),
-    .io_ifu_ar_ready(ifu_io_ifu_ar_ready),
     .io_ifu_ar_valid(ifu_io_ifu_ar_valid),
-    .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id),
     .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr),
-    .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region),
-    .io_ifu_r_valid(ifu_io_ifu_r_valid),
-    .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id),
-    .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data),
-    .io_ifu_r_bits_resp(ifu_io_ifu_r_bits_resp),
     .io_ifu_bus_clk_en(ifu_io_ifu_bus_clk_en),
     .io_ifu_dma_dma_ifc_dma_iccm_stall_any(ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any),
     .io_ifu_dma_dma_mem_ctl_dma_iccm_req(ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req),
@@ -82428,7 +80489,6 @@ module quasar(
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error),
     .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy),
-    .io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn(dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start),
     .io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err(dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err),
     .io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data(dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data),
@@ -82521,7 +80581,6 @@ module quasar(
     .io_dec_exu_ib_exu_dec_debug_wdata_rs1_d(dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d),
     .io_dec_exu_gpr_exu_gpr_i0_rs1_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d),
     .io_dec_exu_gpr_exu_gpr_i0_rs2_d(dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d),
-    .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
@@ -82579,27 +80638,14 @@ module quasar(
     .io_dmi_reg_addr(dbg_io_dmi_reg_addr),
     .io_dmi_reg_wr_en(dbg_io_dmi_reg_wr_en),
     .io_dmi_reg_wdata(dbg_io_dmi_reg_wdata),
-    .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready),
     .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid),
     .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr),
-    .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region),
     .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size),
-    .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready),
     .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid),
-    .io_sb_axi_w_bits_data(dbg_io_sb_axi_w_bits_data),
     .io_sb_axi_w_bits_strb(dbg_io_sb_axi_w_bits_strb),
-    .io_sb_axi_b_ready(dbg_io_sb_axi_b_ready),
-    .io_sb_axi_b_valid(dbg_io_sb_axi_b_valid),
-    .io_sb_axi_b_bits_resp(dbg_io_sb_axi_b_bits_resp),
-    .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready),
     .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid),
     .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr),
-    .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region),
     .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size),
-    .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready),
-    .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid),
-    .io_sb_axi_r_bits_data(dbg_io_sb_axi_r_bits_data),
-    .io_sb_axi_r_bits_resp(dbg_io_sb_axi_r_bits_resp),
     .io_dbg_dec_dbg_ib_dbg_cmd_valid(dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid),
     .io_dbg_dec_dbg_ib_dbg_cmd_write(dbg_io_dbg_dec_dbg_ib_dbg_cmd_write),
     .io_dbg_dec_dbg_ib_dbg_cmd_type(dbg_io_dbg_dec_dbg_ib_dbg_cmd_type),
@@ -82748,7 +80794,6 @@ module quasar(
     .io_lsu_pic_picm_rd_data(lsu_io_lsu_pic_picm_rd_data),
     .io_lsu_exu_exu_lsu_rs1_d(lsu_io_lsu_exu_exu_lsu_rs1_d),
     .io_lsu_exu_exu_lsu_rs2_d(lsu_io_lsu_exu_exu_lsu_rs2_d),
-    .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error),
     .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy),
@@ -82778,31 +80823,14 @@ module quasar(
     .io_dccm_rd_data_hi(lsu_io_dccm_rd_data_hi),
     .io_lsu_tlu_lsu_pmu_load_external_m(lsu_io_lsu_tlu_lsu_pmu_load_external_m),
     .io_lsu_tlu_lsu_pmu_store_external_m(lsu_io_lsu_tlu_lsu_pmu_store_external_m),
-    .io_axi_aw_ready(lsu_io_axi_aw_ready),
     .io_axi_aw_valid(lsu_io_axi_aw_valid),
-    .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr),
-    .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region),
     .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size),
-    .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache),
-    .io_axi_w_ready(lsu_io_axi_w_ready),
     .io_axi_w_valid(lsu_io_axi_w_valid),
-    .io_axi_w_bits_data(lsu_io_axi_w_bits_data),
     .io_axi_w_bits_strb(lsu_io_axi_w_bits_strb),
-    .io_axi_b_valid(lsu_io_axi_b_valid),
-    .io_axi_b_bits_resp(lsu_io_axi_b_bits_resp),
-    .io_axi_b_bits_id(lsu_io_axi_b_bits_id),
-    .io_axi_ar_ready(lsu_io_axi_ar_ready),
     .io_axi_ar_valid(lsu_io_axi_ar_valid),
-    .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr),
-    .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region),
     .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size),
-    .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache),
-    .io_axi_r_valid(lsu_io_axi_r_valid),
-    .io_axi_r_bits_id(lsu_io_axi_r_bits_id),
-    .io_axi_r_bits_data(lsu_io_axi_r_bits_data),
-    .io_axi_r_bits_resp(lsu_io_axi_r_bits_resp),
     .io_dec_tlu_flush_lower_r(lsu_io_dec_tlu_flush_lower_r),
     .io_dec_tlu_i0_kill_writeb_r(lsu_io_dec_tlu_i0_kill_writeb_r),
     .io_dec_tlu_force_halt(lsu_io_dec_tlu_force_halt),
@@ -82914,28 +80942,8 @@ module quasar(
     .io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag),
     .io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata),
     .io_iccm_ready(dma_ctrl_io_iccm_ready),
-    .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready),
-    .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid),
-    .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id),
-    .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr),
-    .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size),
-    .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready),
-    .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid),
-    .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data),
-    .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb),
-    .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready),
     .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid),
-    .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp),
-    .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id),
-    .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready),
-    .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid),
-    .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id),
-    .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr),
-    .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size),
-    .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready),
     .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid),
-    .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id),
-    .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data),
     .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp),
     .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req),
     .io_lsu_dma_dma_lsc_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr),
@@ -82977,12 +80985,21 @@ module quasar(
     .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en),
     .io_clk_override(axi4_to_ahb_io_clk_override),
     .io_axi_awvalid(axi4_to_ahb_io_axi_awvalid),
+    .io_axi_awaddr(axi4_to_ahb_io_axi_awaddr),
+    .io_axi_awsize(axi4_to_ahb_io_axi_awsize),
     .io_axi_wvalid(axi4_to_ahb_io_axi_wvalid),
+    .io_axi_wstrb(axi4_to_ahb_io_axi_wstrb),
     .io_axi_bready(axi4_to_ahb_io_axi_bready),
     .io_axi_arvalid(axi4_to_ahb_io_axi_arvalid),
+    .io_axi_araddr(axi4_to_ahb_io_axi_araddr),
+    .io_axi_arsize(axi4_to_ahb_io_axi_arsize),
     .io_axi_rready(axi4_to_ahb_io_axi_rready),
     .io_axi_awready(axi4_to_ahb_io_axi_awready),
-    .io_axi_wready(axi4_to_ahb_io_axi_wready)
+    .io_axi_wready(axi4_to_ahb_io_axi_wready),
+    .io_ahb_in_hready(axi4_to_ahb_io_ahb_in_hready),
+    .io_ahb_in_hresp(axi4_to_ahb_io_ahb_in_hresp),
+    .io_ahb_out_htrans(axi4_to_ahb_io_ahb_out_htrans),
+    .io_ahb_out_hwrite(axi4_to_ahb_io_ahb_out_hwrite)
   );
   axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 333:33]
     .clock(axi4_to_ahb_1_clock),
@@ -82991,12 +81008,21 @@ module quasar(
     .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en),
     .io_clk_override(axi4_to_ahb_1_io_clk_override),
     .io_axi_awvalid(axi4_to_ahb_1_io_axi_awvalid),
+    .io_axi_awaddr(axi4_to_ahb_1_io_axi_awaddr),
+    .io_axi_awsize(axi4_to_ahb_1_io_axi_awsize),
     .io_axi_wvalid(axi4_to_ahb_1_io_axi_wvalid),
+    .io_axi_wstrb(axi4_to_ahb_1_io_axi_wstrb),
     .io_axi_bready(axi4_to_ahb_1_io_axi_bready),
     .io_axi_arvalid(axi4_to_ahb_1_io_axi_arvalid),
+    .io_axi_araddr(axi4_to_ahb_1_io_axi_araddr),
+    .io_axi_arsize(axi4_to_ahb_1_io_axi_arsize),
     .io_axi_rready(axi4_to_ahb_1_io_axi_rready),
     .io_axi_awready(axi4_to_ahb_1_io_axi_awready),
-    .io_axi_wready(axi4_to_ahb_1_io_axi_wready)
+    .io_axi_wready(axi4_to_ahb_1_io_axi_wready),
+    .io_ahb_in_hready(axi4_to_ahb_1_io_ahb_in_hready),
+    .io_ahb_in_hresp(axi4_to_ahb_1_io_ahb_in_hresp),
+    .io_ahb_out_htrans(axi4_to_ahb_1_io_ahb_out_htrans),
+    .io_ahb_out_hwrite(axi4_to_ahb_1_io_ahb_out_hwrite)
   );
   axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 361:32]
     .clock(axi4_to_ahb_2_clock),
@@ -83005,12 +81031,21 @@ module quasar(
     .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en),
     .io_clk_override(axi4_to_ahb_2_io_clk_override),
     .io_axi_awvalid(axi4_to_ahb_2_io_axi_awvalid),
+    .io_axi_awaddr(axi4_to_ahb_2_io_axi_awaddr),
+    .io_axi_awsize(axi4_to_ahb_2_io_axi_awsize),
     .io_axi_wvalid(axi4_to_ahb_2_io_axi_wvalid),
+    .io_axi_wstrb(axi4_to_ahb_2_io_axi_wstrb),
     .io_axi_bready(axi4_to_ahb_2_io_axi_bready),
     .io_axi_arvalid(axi4_to_ahb_2_io_axi_arvalid),
+    .io_axi_araddr(axi4_to_ahb_2_io_axi_araddr),
+    .io_axi_arsize(axi4_to_ahb_2_io_axi_arsize),
     .io_axi_rready(axi4_to_ahb_2_io_axi_rready),
     .io_axi_awready(axi4_to_ahb_2_io_axi_awready),
-    .io_axi_wready(axi4_to_ahb_2_io_axi_wready)
+    .io_axi_wready(axi4_to_ahb_2_io_axi_wready),
+    .io_ahb_in_hready(axi4_to_ahb_2_io_ahb_in_hready),
+    .io_ahb_in_hresp(axi4_to_ahb_2_io_ahb_in_hresp),
+    .io_ahb_out_htrans(axi4_to_ahb_2_io_ahb_out_htrans),
+    .io_ahb_out_hwrite(axi4_to_ahb_2_io_ahb_out_hwrite)
   );
   ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 388:33]
     .clock(ahb_to_axi4_clock),
@@ -83019,59 +81054,50 @@ module quasar(
     .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en),
     .io_axi_awready(ahb_to_axi4_io_axi_awready),
     .io_axi_arready(ahb_to_axi4_io_axi_arready),
-    .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid),
     .io_axi_rresp(ahb_to_axi4_io_axi_rresp),
     .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid),
     .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid),
-    .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp)
+    .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready),
+    .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp),
+    .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr),
+    .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize),
+    .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans),
+    .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite),
+    .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel),
+    .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin)
   );
   assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 295:14]
-  assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 295:14]
   assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 295:14]
-  assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 295:14]
   assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 295:14]
-  assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 295:14]
   assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 295:14]
-  assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 295:14]
   assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 295:14]
   assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 295:14]
   assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 295:14]
-  assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 295:14]
   assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 295:14]
-  assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 295:14]
   assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 295:14]
-  assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 295:14]
   assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 295:14]
   assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar.scala 298:14]
   assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar.scala 298:14]
   assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 298:14]
   assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 298:14]
-  assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 298:14]
   assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 298:14]
-  assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 298:14]
+  assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar.scala 298:14]
   assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 298:14]
   assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 242:17]
   assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 242:17]
-  assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 242:17]
   assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 242:17]
   assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 242:17]
-  assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 242:17]
   assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 242:17]
   assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 242:17]
   assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 242:17]
   assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 242:17]
-  assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 242:17]
   assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 242:17]
   assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 242:17]
-  assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 299:14]
-  assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 299:14]
-  assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 299:14]
-  assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 299:14]
-  assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 299:14]
-  assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 299:14]
-  assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 299:14]
-  assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 299:14]
-  assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 299:14]
+  assign io_dma_axi_aw_ready = 1'h1; // @[quasar.scala 299:14]
+  assign io_dma_axi_ar_ready = 1'h1; // @[quasar.scala 299:14]
   assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 299:14]
   assign io_core_rst_l = reset & _T_2; // @[quasar.scala 133:17]
   assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 274:19]
@@ -83105,10 +81131,7 @@ module quasar(
   assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 292:11]
   assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 154:13]
   assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 154:13]
-  assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 154:13]
   assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 154:13]
-  assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 154:13]
-  assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 154:13]
   assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 154:13]
   assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 154:13]
   assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 154:13]
@@ -83174,11 +81197,6 @@ module quasar(
   assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 154:13]
   assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 154:13]
   assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 154:13]
-  assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 298:14 quasar.scala 430:25]
-  assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 298:14 quasar.scala 431:24]
-  assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 298:14 quasar.scala 432:26]
-  assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 298:14 quasar.scala 433:28]
-  assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 298:14 quasar.scala 434:28]
   assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 152:25]
   assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 153:18]
   assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 153:18]
@@ -83254,7 +81272,6 @@ module quasar(
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 142:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 142:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 142:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 142:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 142:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 142:18]
   assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 142:18]
@@ -83274,7 +81291,6 @@ module quasar(
   assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 205:18]
   assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 205:18]
   assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 205:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 176:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 176:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 176:18]
   assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 176:18]
@@ -83320,14 +81336,6 @@ module quasar(
   assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 239:23]
   assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 240:24]
   assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 241:24]
-  assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 242:17 quasar.scala 437:28]
-  assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 242:17 quasar.scala 438:27]
-  assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 242:17 quasar.scala 439:27]
-  assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 242:17 quasar.scala 440:31]
-  assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 242:17 quasar.scala 441:28]
-  assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 242:17 quasar.scala 442:27]
-  assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 242:17 quasar.scala 444:31]
-  assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 242:17 quasar.scala 445:31]
   assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 256:26]
   assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 243:25]
   assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 244:20]
@@ -83419,16 +81427,6 @@ module quasar(
   assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 176:18]
   assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 292:11]
   assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 292:11]
-  assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 295:14 quasar.scala 416:25]
-  assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 295:14 quasar.scala 417:24]
-  assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 295:14 quasar.scala 418:24]
-  assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 295:14 quasar.scala 419:28]
-  assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 295:14 quasar.scala 420:26]
-  assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 421:25]
-  assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 422:24]
-  assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 423:26]
-  assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 424:28]
-  assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 425:28]
   assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 213:32]
   assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 214:35]
   assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 215:29]
@@ -83503,19 +81501,6 @@ module quasar(
   assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 259:29]
   assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 260:30]
   assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 261:26]
-  assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 299:14 quasar.scala 447:34]
-  assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 299:14 quasar.scala 448:36]
-  assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 299:14 quasar.scala 449:38]
-  assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 299:14 quasar.scala 450:38]
-  assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 299:14 quasar.scala 451:33]
-  assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 299:14 quasar.scala 452:37]
-  assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 299:14 quasar.scala 453:37]
-  assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 299:14 quasar.scala 454:33]
-  assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 299:14 quasar.scala 455:34]
-  assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 299:14 quasar.scala 456:36]
-  assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 299:14 quasar.scala 457:38]
-  assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 299:14 quasar.scala 458:38]
-  assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 299:14 quasar.scala 459:33]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 225:18]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 225:18]
   assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 225:18]
@@ -83533,38 +81518,64 @@ module quasar(
   assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 309:35]
   assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 310:37]
   assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 307:36]
+  assign axi4_to_ahb_io_axi_awaddr = io_lsu_axi_aw_bits_addr; // @[quasar.scala 312:35]
+  assign axi4_to_ahb_io_axi_awsize = io_lsu_axi_aw_bits_size; // @[quasar.scala 313:35]
   assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 316:35]
+  assign axi4_to_ahb_io_axi_wstrb = io_lsu_axi_w_bits_strb; // @[quasar.scala 318:34]
   assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 320:35]
   assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 322:36]
+  assign axi4_to_ahb_io_axi_araddr = io_lsu_axi_ar_bits_addr; // @[quasar.scala 324:35]
+  assign axi4_to_ahb_io_axi_arsize = io_lsu_axi_ar_bits_size; // @[quasar.scala 325:35]
   assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 328:35]
+  assign axi4_to_ahb_io_ahb_in_hready = io_lsu_ahb_in_hready; // @[quasar.scala 470:16]
+  assign axi4_to_ahb_io_ahb_in_hresp = io_lsu_ahb_in_hresp; // @[quasar.scala 470:16]
   assign axi4_to_ahb_1_clock = clock;
   assign axi4_to_ahb_1_reset = reset;
   assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 335:34]
   assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 336:35]
   assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 337:37]
   assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 334:36]
+  assign axi4_to_ahb_1_io_axi_awaddr = io_ifu_axi_aw_bits_addr; // @[quasar.scala 339:35]
+  assign axi4_to_ahb_1_io_axi_awsize = io_ifu_axi_aw_bits_size; // @[quasar.scala 340:35]
   assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 343:35]
+  assign axi4_to_ahb_1_io_axi_wstrb = io_ifu_axi_w_bits_strb; // @[quasar.scala 345:34]
   assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 347:35]
   assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 349:36]
+  assign axi4_to_ahb_1_io_axi_araddr = io_ifu_axi_ar_bits_addr; // @[quasar.scala 351:35]
+  assign axi4_to_ahb_1_io_axi_arsize = io_ifu_axi_ar_bits_size; // @[quasar.scala 352:35]
   assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 355:35]
+  assign axi4_to_ahb_1_io_ahb_in_hready = io_ahb_in_hready; // @[quasar.scala 461:12]
+  assign axi4_to_ahb_1_io_ahb_in_hresp = io_ahb_in_hresp; // @[quasar.scala 461:12]
   assign axi4_to_ahb_2_clock = clock;
   assign axi4_to_ahb_2_reset = reset;
   assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 363:33]
   assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 364:34]
   assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 365:36]
   assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 362:35]
+  assign axi4_to_ahb_2_io_axi_awaddr = io_sb_axi_aw_bits_addr; // @[quasar.scala 367:34]
+  assign axi4_to_ahb_2_io_axi_awsize = io_sb_axi_aw_bits_size; // @[quasar.scala 368:34]
   assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 371:34]
+  assign axi4_to_ahb_2_io_axi_wstrb = io_sb_axi_w_bits_strb; // @[quasar.scala 373:33]
   assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 375:34]
   assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 377:35]
+  assign axi4_to_ahb_2_io_axi_araddr = io_sb_axi_ar_bits_addr; // @[quasar.scala 379:34]
+  assign axi4_to_ahb_2_io_axi_arsize = io_sb_axi_ar_bits_size; // @[quasar.scala 380:34]
   assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 383:34]
+  assign axi4_to_ahb_2_io_ahb_in_hready = io_sb_ahb_in_hready; // @[quasar.scala 480:15]
+  assign axi4_to_ahb_2_io_ahb_in_hresp = io_sb_ahb_in_hresp; // @[quasar.scala 480:15]
   assign ahb_to_axi4_clock = clock;
   assign ahb_to_axi4_reset = reset;
   assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 389:34]
   assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 390:35]
   assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 392:36]
   assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 399:36]
-  assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 400:35]
   assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 403:34]
+  assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_out_haddr; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_out_hsize; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_out_htrans; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 414:33]
+  assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 415:37]
 endmodule
 module quasar_wrapper(
   input         clock,
@@ -83574,162 +81585,52 @@ module quasar_wrapper(
   input         io_nmi_int,
   input  [30:0] io_nmi_vec,
   input  [30:0] io_jtag_id,
-  input         io_lsu_brg_aw_ready,
-  output        io_lsu_brg_aw_valid,
-  output [2:0]  io_lsu_brg_aw_bits_id,
-  output [31:0] io_lsu_brg_aw_bits_addr,
-  output [3:0]  io_lsu_brg_aw_bits_region,
-  output [7:0]  io_lsu_brg_aw_bits_len,
-  output [2:0]  io_lsu_brg_aw_bits_size,
-  output [1:0]  io_lsu_brg_aw_bits_burst,
-  output        io_lsu_brg_aw_bits_lock,
-  output [3:0]  io_lsu_brg_aw_bits_cache,
-  output [2:0]  io_lsu_brg_aw_bits_prot,
-  output [3:0]  io_lsu_brg_aw_bits_qos,
-  input         io_lsu_brg_w_ready,
-  output        io_lsu_brg_w_valid,
-  output [63:0] io_lsu_brg_w_bits_data,
-  output [7:0]  io_lsu_brg_w_bits_strb,
-  output        io_lsu_brg_w_bits_last,
-  output        io_lsu_brg_b_ready,
-  input         io_lsu_brg_b_valid,
-  input  [1:0]  io_lsu_brg_b_bits_resp,
-  input  [2:0]  io_lsu_brg_b_bits_id,
-  input         io_lsu_brg_ar_ready,
-  output        io_lsu_brg_ar_valid,
-  output [2:0]  io_lsu_brg_ar_bits_id,
-  output [31:0] io_lsu_brg_ar_bits_addr,
-  output [3:0]  io_lsu_brg_ar_bits_region,
-  output [7:0]  io_lsu_brg_ar_bits_len,
-  output [2:0]  io_lsu_brg_ar_bits_size,
-  output [1:0]  io_lsu_brg_ar_bits_burst,
-  output        io_lsu_brg_ar_bits_lock,
-  output [3:0]  io_lsu_brg_ar_bits_cache,
-  output [2:0]  io_lsu_brg_ar_bits_prot,
-  output [3:0]  io_lsu_brg_ar_bits_qos,
-  output        io_lsu_brg_r_ready,
-  input         io_lsu_brg_r_valid,
-  input  [2:0]  io_lsu_brg_r_bits_id,
-  input  [63:0] io_lsu_brg_r_bits_data,
-  input  [1:0]  io_lsu_brg_r_bits_resp,
-  input         io_lsu_brg_r_bits_last,
-  input         io_ifu_brg_aw_ready,
-  output        io_ifu_brg_aw_valid,
-  output [2:0]  io_ifu_brg_aw_bits_id,
-  output [31:0] io_ifu_brg_aw_bits_addr,
-  output [3:0]  io_ifu_brg_aw_bits_region,
-  output [7:0]  io_ifu_brg_aw_bits_len,
-  output [2:0]  io_ifu_brg_aw_bits_size,
-  output [1:0]  io_ifu_brg_aw_bits_burst,
-  output        io_ifu_brg_aw_bits_lock,
-  output [3:0]  io_ifu_brg_aw_bits_cache,
-  output [2:0]  io_ifu_brg_aw_bits_prot,
-  output [3:0]  io_ifu_brg_aw_bits_qos,
-  input         io_ifu_brg_w_ready,
-  output        io_ifu_brg_w_valid,
-  output [63:0] io_ifu_brg_w_bits_data,
-  output [7:0]  io_ifu_brg_w_bits_strb,
-  output        io_ifu_brg_w_bits_last,
-  output        io_ifu_brg_b_ready,
-  input         io_ifu_brg_b_valid,
-  input  [1:0]  io_ifu_brg_b_bits_resp,
-  input  [2:0]  io_ifu_brg_b_bits_id,
-  input         io_ifu_brg_ar_ready,
-  output        io_ifu_brg_ar_valid,
-  output [2:0]  io_ifu_brg_ar_bits_id,
-  output [31:0] io_ifu_brg_ar_bits_addr,
-  output [3:0]  io_ifu_brg_ar_bits_region,
-  output [7:0]  io_ifu_brg_ar_bits_len,
-  output [2:0]  io_ifu_brg_ar_bits_size,
-  output [1:0]  io_ifu_brg_ar_bits_burst,
-  output        io_ifu_brg_ar_bits_lock,
-  output [3:0]  io_ifu_brg_ar_bits_cache,
-  output [2:0]  io_ifu_brg_ar_bits_prot,
-  output [3:0]  io_ifu_brg_ar_bits_qos,
-  output        io_ifu_brg_r_ready,
-  input         io_ifu_brg_r_valid,
-  input  [2:0]  io_ifu_brg_r_bits_id,
-  input  [63:0] io_ifu_brg_r_bits_data,
-  input  [1:0]  io_ifu_brg_r_bits_resp,
-  input         io_ifu_brg_r_bits_last,
-  input         io_sb_brg_aw_ready,
-  output        io_sb_brg_aw_valid,
-  output        io_sb_brg_aw_bits_id,
-  output [31:0] io_sb_brg_aw_bits_addr,
-  output [3:0]  io_sb_brg_aw_bits_region,
-  output [7:0]  io_sb_brg_aw_bits_len,
-  output [2:0]  io_sb_brg_aw_bits_size,
-  output [1:0]  io_sb_brg_aw_bits_burst,
-  output        io_sb_brg_aw_bits_lock,
-  output [3:0]  io_sb_brg_aw_bits_cache,
-  output [2:0]  io_sb_brg_aw_bits_prot,
-  output [3:0]  io_sb_brg_aw_bits_qos,
-  input         io_sb_brg_w_ready,
-  output        io_sb_brg_w_valid,
-  output [63:0] io_sb_brg_w_bits_data,
-  output [7:0]  io_sb_brg_w_bits_strb,
-  output        io_sb_brg_w_bits_last,
-  output        io_sb_brg_b_ready,
-  input         io_sb_brg_b_valid,
-  input  [1:0]  io_sb_brg_b_bits_resp,
-  input         io_sb_brg_b_bits_id,
-  input         io_sb_brg_ar_ready,
-  output        io_sb_brg_ar_valid,
-  output        io_sb_brg_ar_bits_id,
-  output [31:0] io_sb_brg_ar_bits_addr,
-  output [3:0]  io_sb_brg_ar_bits_region,
-  output [7:0]  io_sb_brg_ar_bits_len,
-  output [2:0]  io_sb_brg_ar_bits_size,
-  output [1:0]  io_sb_brg_ar_bits_burst,
-  output        io_sb_brg_ar_bits_lock,
-  output [3:0]  io_sb_brg_ar_bits_cache,
-  output [2:0]  io_sb_brg_ar_bits_prot,
-  output [3:0]  io_sb_brg_ar_bits_qos,
-  output        io_sb_brg_r_ready,
-  input         io_sb_brg_r_valid,
-  input         io_sb_brg_r_bits_id,
-  input  [63:0] io_sb_brg_r_bits_data,
-  input  [1:0]  io_sb_brg_r_bits_resp,
-  input         io_sb_brg_r_bits_last,
-  output        io_dma_brg_aw_ready,
-  input         io_dma_brg_aw_valid,
-  input         io_dma_brg_aw_bits_id,
-  input  [31:0] io_dma_brg_aw_bits_addr,
-  input  [3:0]  io_dma_brg_aw_bits_region,
-  input  [7:0]  io_dma_brg_aw_bits_len,
-  input  [2:0]  io_dma_brg_aw_bits_size,
-  input  [1:0]  io_dma_brg_aw_bits_burst,
-  input         io_dma_brg_aw_bits_lock,
-  input  [3:0]  io_dma_brg_aw_bits_cache,
-  input  [2:0]  io_dma_brg_aw_bits_prot,
-  input  [3:0]  io_dma_brg_aw_bits_qos,
-  output        io_dma_brg_w_ready,
-  input         io_dma_brg_w_valid,
-  input  [63:0] io_dma_brg_w_bits_data,
-  input  [7:0]  io_dma_brg_w_bits_strb,
-  input         io_dma_brg_w_bits_last,
-  input         io_dma_brg_b_ready,
-  output        io_dma_brg_b_valid,
-  output [1:0]  io_dma_brg_b_bits_resp,
-  output        io_dma_brg_b_bits_id,
-  output        io_dma_brg_ar_ready,
-  input         io_dma_brg_ar_valid,
-  input         io_dma_brg_ar_bits_id,
-  input  [31:0] io_dma_brg_ar_bits_addr,
-  input  [3:0]  io_dma_brg_ar_bits_region,
-  input  [7:0]  io_dma_brg_ar_bits_len,
-  input  [2:0]  io_dma_brg_ar_bits_size,
-  input  [1:0]  io_dma_brg_ar_bits_burst,
-  input         io_dma_brg_ar_bits_lock,
-  input  [3:0]  io_dma_brg_ar_bits_cache,
-  input  [2:0]  io_dma_brg_ar_bits_prot,
-  input  [3:0]  io_dma_brg_ar_bits_qos,
-  input         io_dma_brg_r_ready,
-  output        io_dma_brg_r_valid,
-  output        io_dma_brg_r_bits_id,
-  output [63:0] io_dma_brg_r_bits_data,
-  output [1:0]  io_dma_brg_r_bits_resp,
-  output        io_dma_brg_r_bits_last,
+  input  [63:0] io_lsu_brg_in_hrdata,
+  input         io_lsu_brg_in_hready,
+  input         io_lsu_brg_in_hresp,
+  output [31:0] io_lsu_brg_out_haddr,
+  output [2:0]  io_lsu_brg_out_hburst,
+  output        io_lsu_brg_out_hmastlock,
+  output [3:0]  io_lsu_brg_out_hprot,
+  output [2:0]  io_lsu_brg_out_hsize,
+  output [1:0]  io_lsu_brg_out_htrans,
+  output        io_lsu_brg_out_hwrite,
+  output [63:0] io_lsu_brg_out_hwdata,
+  input  [63:0] io_ifu_brg_in_hrdata,
+  input         io_ifu_brg_in_hready,
+  input         io_ifu_brg_in_hresp,
+  output [31:0] io_ifu_brg_out_haddr,
+  output [2:0]  io_ifu_brg_out_hburst,
+  output        io_ifu_brg_out_hmastlock,
+  output [3:0]  io_ifu_brg_out_hprot,
+  output [2:0]  io_ifu_brg_out_hsize,
+  output [1:0]  io_ifu_brg_out_htrans,
+  output        io_ifu_brg_out_hwrite,
+  output [63:0] io_ifu_brg_out_hwdata,
+  input  [63:0] io_sb_brg_in_hrdata,
+  input         io_sb_brg_in_hready,
+  input         io_sb_brg_in_hresp,
+  output [31:0] io_sb_brg_out_haddr,
+  output [2:0]  io_sb_brg_out_hburst,
+  output        io_sb_brg_out_hmastlock,
+  output [3:0]  io_sb_brg_out_hprot,
+  output [2:0]  io_sb_brg_out_hsize,
+  output [1:0]  io_sb_brg_out_htrans,
+  output        io_sb_brg_out_hwrite,
+  output [63:0] io_sb_brg_out_hwdata,
+  output [63:0] io_dma_brg_ahb_in_hrdata,
+  output        io_dma_brg_ahb_in_hready,
+  output        io_dma_brg_ahb_in_hresp,
+  input  [31:0] io_dma_brg_ahb_out_haddr,
+  input  [2:0]  io_dma_brg_ahb_out_hburst,
+  input         io_dma_brg_ahb_out_hmastlock,
+  input  [3:0]  io_dma_brg_ahb_out_hprot,
+  input  [2:0]  io_dma_brg_ahb_out_hsize,
+  input  [1:0]  io_dma_brg_ahb_out_htrans,
+  input         io_dma_brg_ahb_out_hwrite,
+  input  [63:0] io_dma_brg_ahb_out_hwdata,
+  input         io_dma_brg_hsel,
+  input         io_dma_brg_hreadyin,
   input         io_lsu_bus_clk_en,
   input         io_ifu_bus_clk_en,
   input         io_dbg_bus_clk_en,
@@ -83830,175 +81731,133 @@ module quasar_wrapper(
   wire  dmi_wrapper_reg_en; // @[quasar_wrapper.scala 64:27]
   wire  dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 64:27]
   wire  dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27]
-  wire  swerv_clock; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_reset; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 65:21]
-  wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_nmi_int; // @[quasar_wrapper.scala 65:21]
-  wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_core_rst_l; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 65:21]
-  wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_icm_clk_override; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 65:21]
-  wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dccm_wren; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dccm_rden; // @[quasar_wrapper.scala 65:21]
-  wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 65:21]
-  wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 65:21]
-  wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 65:21]
-  wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 65:21]
-  wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 65:21]
-  wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 65:21]
-  wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 65:21]
-  wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 65:21]
-  wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_rd_en; // @[quasar_wrapper.scala 65:21]
-  wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 65:21]
-  wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 65:21]
-  wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 65:21]
-  wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 65:21]
-  wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 65:21]
-  wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 65:21]
-  wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 65:21]
-  wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_iccm_wren; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_iccm_rden; // @[quasar_wrapper.scala 65:21]
-  wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 65:21]
-  wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 65:21]
-  wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 65:21]
-  wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 65:21]
-  wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 65:21]
-  wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 65:21]
-  wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_timer_int; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_soft_int; // @[quasar_wrapper.scala 65:21]
-  wire  swerv_io_scan_mode; // @[quasar_wrapper.scala 65:21]
+  wire  core_clock; // @[quasar_wrapper.scala 65:20]
+  wire  core_reset; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20]
+  wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_ifu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_ifu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 65:20]
+  wire [7:0] core_io_ifu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_ifu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20]
+  wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_axi_b_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_axi_r_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_ahb_in_hready; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_sb_ahb_in_hresp; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_hsel; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_hreadyin; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20]
+  wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_nmi_int; // @[quasar_wrapper.scala 65:20]
+  wire [30:0] core_io_nmi_vec; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_core_rst_l; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 65:20]
+  wire [4:0] core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dccm_clk_override; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_icm_clk_override; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_i_cpu_halt_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_i_cpu_run_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_o_debug_mode_status; // @[quasar_wrapper.scala 65:20]
+  wire [27:0] core_io_core_id; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_mpc_debug_run_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_mpc_reset_run_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_debug_brkpt_status; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dccm_wren; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dccm_rden; // @[quasar_wrapper.scala 65:20]
+  wire [15:0] core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 65:20]
+  wire [15:0] core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 65:20]
+  wire [15:0] core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 65:20]
+  wire [15:0] core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 65:20]
+  wire [38:0] core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 65:20]
+  wire [38:0] core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 65:20]
+  wire [38:0] core_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 65:20]
+  wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 65:20]
+  wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_rd_en; // @[quasar_wrapper.scala 65:20]
+  wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 65:20]
+  wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 65:20]
+  wire [70:0] core_io_ic_debug_rd_data; // @[quasar_wrapper.scala 65:20]
+  wire [25:0] core_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ic_eccerr; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ic_rd_hit; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_tag_perr; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 65:20]
+  wire [1:0] core_io_ic_debug_way; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_ic_premux_data; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 65:20]
+  wire [14:0] core_io_iccm_rw_addr; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_iccm_correction_state; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_iccm_wren; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_iccm_rden; // @[quasar_wrapper.scala 65:20]
+  wire [2:0] core_io_iccm_wr_size; // @[quasar_wrapper.scala 65:20]
+  wire [77:0] core_io_iccm_wr_data; // @[quasar_wrapper.scala 65:20]
+  wire [63:0] core_io_iccm_rd_data; // @[quasar_wrapper.scala 65:20]
+  wire [77:0] core_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dma_bus_clk_en; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dmi_reg_en; // @[quasar_wrapper.scala 65:20]
+  wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 65:20]
+  wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 65:20]
+  wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_timer_int; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_soft_int; // @[quasar_wrapper.scala 65:20]
+  wire  core_io_scan_mode; // @[quasar_wrapper.scala 65:20]
   mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 63:19]
     .clk(mem_clk),
     .rst_l(mem_rst_l),
@@ -84064,325 +81923,215 @@ module quasar_wrapper(
     .reg_wr_en(dmi_wrapper_reg_wr_en),
     .dmi_hard_reset(dmi_wrapper_dmi_hard_reset)
   );
-  quasar swerv ( // @[quasar_wrapper.scala 65:21]
-    .clock(swerv_clock),
-    .reset(swerv_reset),
-    .io_lsu_axi_aw_ready(swerv_io_lsu_axi_aw_ready),
-    .io_lsu_axi_aw_valid(swerv_io_lsu_axi_aw_valid),
-    .io_lsu_axi_aw_bits_id(swerv_io_lsu_axi_aw_bits_id),
-    .io_lsu_axi_aw_bits_addr(swerv_io_lsu_axi_aw_bits_addr),
-    .io_lsu_axi_aw_bits_region(swerv_io_lsu_axi_aw_bits_region),
-    .io_lsu_axi_aw_bits_size(swerv_io_lsu_axi_aw_bits_size),
-    .io_lsu_axi_aw_bits_cache(swerv_io_lsu_axi_aw_bits_cache),
-    .io_lsu_axi_w_ready(swerv_io_lsu_axi_w_ready),
-    .io_lsu_axi_w_valid(swerv_io_lsu_axi_w_valid),
-    .io_lsu_axi_w_bits_data(swerv_io_lsu_axi_w_bits_data),
-    .io_lsu_axi_w_bits_strb(swerv_io_lsu_axi_w_bits_strb),
-    .io_lsu_axi_b_ready(swerv_io_lsu_axi_b_ready),
-    .io_lsu_axi_b_valid(swerv_io_lsu_axi_b_valid),
-    .io_lsu_axi_b_bits_resp(swerv_io_lsu_axi_b_bits_resp),
-    .io_lsu_axi_b_bits_id(swerv_io_lsu_axi_b_bits_id),
-    .io_lsu_axi_ar_ready(swerv_io_lsu_axi_ar_ready),
-    .io_lsu_axi_ar_valid(swerv_io_lsu_axi_ar_valid),
-    .io_lsu_axi_ar_bits_id(swerv_io_lsu_axi_ar_bits_id),
-    .io_lsu_axi_ar_bits_addr(swerv_io_lsu_axi_ar_bits_addr),
-    .io_lsu_axi_ar_bits_region(swerv_io_lsu_axi_ar_bits_region),
-    .io_lsu_axi_ar_bits_size(swerv_io_lsu_axi_ar_bits_size),
-    .io_lsu_axi_ar_bits_cache(swerv_io_lsu_axi_ar_bits_cache),
-    .io_lsu_axi_r_ready(swerv_io_lsu_axi_r_ready),
-    .io_lsu_axi_r_valid(swerv_io_lsu_axi_r_valid),
-    .io_lsu_axi_r_bits_id(swerv_io_lsu_axi_r_bits_id),
-    .io_lsu_axi_r_bits_data(swerv_io_lsu_axi_r_bits_data),
-    .io_lsu_axi_r_bits_resp(swerv_io_lsu_axi_r_bits_resp),
-    .io_ifu_axi_aw_valid(swerv_io_ifu_axi_aw_valid),
-    .io_ifu_axi_w_valid(swerv_io_ifu_axi_w_valid),
-    .io_ifu_axi_b_ready(swerv_io_ifu_axi_b_ready),
-    .io_ifu_axi_ar_ready(swerv_io_ifu_axi_ar_ready),
-    .io_ifu_axi_ar_valid(swerv_io_ifu_axi_ar_valid),
-    .io_ifu_axi_ar_bits_id(swerv_io_ifu_axi_ar_bits_id),
-    .io_ifu_axi_ar_bits_addr(swerv_io_ifu_axi_ar_bits_addr),
-    .io_ifu_axi_ar_bits_region(swerv_io_ifu_axi_ar_bits_region),
-    .io_ifu_axi_r_ready(swerv_io_ifu_axi_r_ready),
-    .io_ifu_axi_r_valid(swerv_io_ifu_axi_r_valid),
-    .io_ifu_axi_r_bits_id(swerv_io_ifu_axi_r_bits_id),
-    .io_ifu_axi_r_bits_data(swerv_io_ifu_axi_r_bits_data),
-    .io_ifu_axi_r_bits_resp(swerv_io_ifu_axi_r_bits_resp),
-    .io_sb_axi_aw_ready(swerv_io_sb_axi_aw_ready),
-    .io_sb_axi_aw_valid(swerv_io_sb_axi_aw_valid),
-    .io_sb_axi_aw_bits_addr(swerv_io_sb_axi_aw_bits_addr),
-    .io_sb_axi_aw_bits_region(swerv_io_sb_axi_aw_bits_region),
-    .io_sb_axi_aw_bits_size(swerv_io_sb_axi_aw_bits_size),
-    .io_sb_axi_w_ready(swerv_io_sb_axi_w_ready),
-    .io_sb_axi_w_valid(swerv_io_sb_axi_w_valid),
-    .io_sb_axi_w_bits_data(swerv_io_sb_axi_w_bits_data),
-    .io_sb_axi_w_bits_strb(swerv_io_sb_axi_w_bits_strb),
-    .io_sb_axi_b_ready(swerv_io_sb_axi_b_ready),
-    .io_sb_axi_b_valid(swerv_io_sb_axi_b_valid),
-    .io_sb_axi_b_bits_resp(swerv_io_sb_axi_b_bits_resp),
-    .io_sb_axi_ar_ready(swerv_io_sb_axi_ar_ready),
-    .io_sb_axi_ar_valid(swerv_io_sb_axi_ar_valid),
-    .io_sb_axi_ar_bits_addr(swerv_io_sb_axi_ar_bits_addr),
-    .io_sb_axi_ar_bits_region(swerv_io_sb_axi_ar_bits_region),
-    .io_sb_axi_ar_bits_size(swerv_io_sb_axi_ar_bits_size),
-    .io_sb_axi_r_ready(swerv_io_sb_axi_r_ready),
-    .io_sb_axi_r_valid(swerv_io_sb_axi_r_valid),
-    .io_sb_axi_r_bits_data(swerv_io_sb_axi_r_bits_data),
-    .io_sb_axi_r_bits_resp(swerv_io_sb_axi_r_bits_resp),
-    .io_dma_axi_aw_ready(swerv_io_dma_axi_aw_ready),
-    .io_dma_axi_aw_valid(swerv_io_dma_axi_aw_valid),
-    .io_dma_axi_aw_bits_id(swerv_io_dma_axi_aw_bits_id),
-    .io_dma_axi_aw_bits_addr(swerv_io_dma_axi_aw_bits_addr),
-    .io_dma_axi_aw_bits_size(swerv_io_dma_axi_aw_bits_size),
-    .io_dma_axi_w_ready(swerv_io_dma_axi_w_ready),
-    .io_dma_axi_w_valid(swerv_io_dma_axi_w_valid),
-    .io_dma_axi_w_bits_data(swerv_io_dma_axi_w_bits_data),
-    .io_dma_axi_w_bits_strb(swerv_io_dma_axi_w_bits_strb),
-    .io_dma_axi_b_ready(swerv_io_dma_axi_b_ready),
-    .io_dma_axi_b_valid(swerv_io_dma_axi_b_valid),
-    .io_dma_axi_b_bits_resp(swerv_io_dma_axi_b_bits_resp),
-    .io_dma_axi_b_bits_id(swerv_io_dma_axi_b_bits_id),
-    .io_dma_axi_ar_ready(swerv_io_dma_axi_ar_ready),
-    .io_dma_axi_ar_valid(swerv_io_dma_axi_ar_valid),
-    .io_dma_axi_ar_bits_id(swerv_io_dma_axi_ar_bits_id),
-    .io_dma_axi_ar_bits_addr(swerv_io_dma_axi_ar_bits_addr),
-    .io_dma_axi_ar_bits_size(swerv_io_dma_axi_ar_bits_size),
-    .io_dma_axi_r_ready(swerv_io_dma_axi_r_ready),
-    .io_dma_axi_r_valid(swerv_io_dma_axi_r_valid),
-    .io_dma_axi_r_bits_id(swerv_io_dma_axi_r_bits_id),
-    .io_dma_axi_r_bits_data(swerv_io_dma_axi_r_bits_data),
-    .io_dma_axi_r_bits_resp(swerv_io_dma_axi_r_bits_resp),
-    .io_dbg_rst_l(swerv_io_dbg_rst_l),
-    .io_rst_vec(swerv_io_rst_vec),
-    .io_nmi_int(swerv_io_nmi_int),
-    .io_nmi_vec(swerv_io_nmi_vec),
-    .io_core_rst_l(swerv_io_core_rst_l),
-    .io_rv_trace_pkt_rv_i_valid_ip(swerv_io_rv_trace_pkt_rv_i_valid_ip),
-    .io_rv_trace_pkt_rv_i_insn_ip(swerv_io_rv_trace_pkt_rv_i_insn_ip),
-    .io_rv_trace_pkt_rv_i_address_ip(swerv_io_rv_trace_pkt_rv_i_address_ip),
-    .io_rv_trace_pkt_rv_i_exception_ip(swerv_io_rv_trace_pkt_rv_i_exception_ip),
-    .io_rv_trace_pkt_rv_i_ecause_ip(swerv_io_rv_trace_pkt_rv_i_ecause_ip),
-    .io_rv_trace_pkt_rv_i_interrupt_ip(swerv_io_rv_trace_pkt_rv_i_interrupt_ip),
-    .io_rv_trace_pkt_rv_i_tval_ip(swerv_io_rv_trace_pkt_rv_i_tval_ip),
-    .io_dccm_clk_override(swerv_io_dccm_clk_override),
-    .io_icm_clk_override(swerv_io_icm_clk_override),
-    .io_dec_tlu_core_ecc_disable(swerv_io_dec_tlu_core_ecc_disable),
-    .io_i_cpu_halt_req(swerv_io_i_cpu_halt_req),
-    .io_i_cpu_run_req(swerv_io_i_cpu_run_req),
-    .io_o_cpu_halt_ack(swerv_io_o_cpu_halt_ack),
-    .io_o_cpu_halt_status(swerv_io_o_cpu_halt_status),
-    .io_o_cpu_run_ack(swerv_io_o_cpu_run_ack),
-    .io_o_debug_mode_status(swerv_io_o_debug_mode_status),
-    .io_core_id(swerv_io_core_id),
-    .io_mpc_debug_halt_req(swerv_io_mpc_debug_halt_req),
-    .io_mpc_debug_run_req(swerv_io_mpc_debug_run_req),
-    .io_mpc_reset_run_req(swerv_io_mpc_reset_run_req),
-    .io_mpc_debug_halt_ack(swerv_io_mpc_debug_halt_ack),
-    .io_mpc_debug_run_ack(swerv_io_mpc_debug_run_ack),
-    .io_debug_brkpt_status(swerv_io_debug_brkpt_status),
-    .io_dec_tlu_perfcnt0(swerv_io_dec_tlu_perfcnt0),
-    .io_dec_tlu_perfcnt1(swerv_io_dec_tlu_perfcnt1),
-    .io_dec_tlu_perfcnt2(swerv_io_dec_tlu_perfcnt2),
-    .io_dec_tlu_perfcnt3(swerv_io_dec_tlu_perfcnt3),
-    .io_dccm_wren(swerv_io_dccm_wren),
-    .io_dccm_rden(swerv_io_dccm_rden),
-    .io_dccm_wr_addr_lo(swerv_io_dccm_wr_addr_lo),
-    .io_dccm_wr_addr_hi(swerv_io_dccm_wr_addr_hi),
-    .io_dccm_rd_addr_lo(swerv_io_dccm_rd_addr_lo),
-    .io_dccm_rd_addr_hi(swerv_io_dccm_rd_addr_hi),
-    .io_dccm_wr_data_lo(swerv_io_dccm_wr_data_lo),
-    .io_dccm_wr_data_hi(swerv_io_dccm_wr_data_hi),
-    .io_dccm_rd_data_lo(swerv_io_dccm_rd_data_lo),
-    .io_dccm_rd_data_hi(swerv_io_dccm_rd_data_hi),
-    .io_ic_rw_addr(swerv_io_ic_rw_addr),
-    .io_ic_tag_valid(swerv_io_ic_tag_valid),
-    .io_ic_wr_en(swerv_io_ic_wr_en),
-    .io_ic_rd_en(swerv_io_ic_rd_en),
-    .io_ic_wr_data_0(swerv_io_ic_wr_data_0),
-    .io_ic_wr_data_1(swerv_io_ic_wr_data_1),
-    .io_ic_debug_wr_data(swerv_io_ic_debug_wr_data),
-    .io_ic_debug_addr(swerv_io_ic_debug_addr),
-    .io_ic_rd_data(swerv_io_ic_rd_data),
-    .io_ic_debug_rd_data(swerv_io_ic_debug_rd_data),
-    .io_ic_tag_debug_rd_data(swerv_io_ic_tag_debug_rd_data),
-    .io_ic_eccerr(swerv_io_ic_eccerr),
-    .io_ic_rd_hit(swerv_io_ic_rd_hit),
-    .io_ic_tag_perr(swerv_io_ic_tag_perr),
-    .io_ic_debug_rd_en(swerv_io_ic_debug_rd_en),
-    .io_ic_debug_wr_en(swerv_io_ic_debug_wr_en),
-    .io_ic_debug_tag_array(swerv_io_ic_debug_tag_array),
-    .io_ic_debug_way(swerv_io_ic_debug_way),
-    .io_ic_premux_data(swerv_io_ic_premux_data),
-    .io_ic_sel_premux_data(swerv_io_ic_sel_premux_data),
-    .io_iccm_rw_addr(swerv_io_iccm_rw_addr),
-    .io_iccm_buf_correct_ecc(swerv_io_iccm_buf_correct_ecc),
-    .io_iccm_correction_state(swerv_io_iccm_correction_state),
-    .io_iccm_wren(swerv_io_iccm_wren),
-    .io_iccm_rden(swerv_io_iccm_rden),
-    .io_iccm_wr_size(swerv_io_iccm_wr_size),
-    .io_iccm_wr_data(swerv_io_iccm_wr_data),
-    .io_iccm_rd_data(swerv_io_iccm_rd_data),
-    .io_iccm_rd_data_ecc(swerv_io_iccm_rd_data_ecc),
-    .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en),
-    .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en),
-    .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en),
-    .io_dma_bus_clk_en(swerv_io_dma_bus_clk_en),
-    .io_dmi_reg_en(swerv_io_dmi_reg_en),
-    .io_dmi_reg_addr(swerv_io_dmi_reg_addr),
-    .io_dmi_reg_wr_en(swerv_io_dmi_reg_wr_en),
-    .io_dmi_reg_wdata(swerv_io_dmi_reg_wdata),
-    .io_extintsrc_req(swerv_io_extintsrc_req),
-    .io_timer_int(swerv_io_timer_int),
-    .io_soft_int(swerv_io_soft_int),
-    .io_scan_mode(swerv_io_scan_mode)
+  quasar core ( // @[quasar_wrapper.scala 65:20]
+    .clock(core_clock),
+    .reset(core_reset),
+    .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid),
+    .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr),
+    .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size),
+    .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid),
+    .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb),
+    .io_lsu_axi_b_ready(core_io_lsu_axi_b_ready),
+    .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid),
+    .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr),
+    .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size),
+    .io_lsu_axi_r_ready(core_io_lsu_axi_r_ready),
+    .io_ifu_axi_aw_valid(core_io_ifu_axi_aw_valid),
+    .io_ifu_axi_aw_bits_addr(core_io_ifu_axi_aw_bits_addr),
+    .io_ifu_axi_aw_bits_size(core_io_ifu_axi_aw_bits_size),
+    .io_ifu_axi_w_valid(core_io_ifu_axi_w_valid),
+    .io_ifu_axi_w_bits_strb(core_io_ifu_axi_w_bits_strb),
+    .io_ifu_axi_b_ready(core_io_ifu_axi_b_ready),
+    .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid),
+    .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr),
+    .io_ifu_axi_ar_bits_size(core_io_ifu_axi_ar_bits_size),
+    .io_ifu_axi_r_ready(core_io_ifu_axi_r_ready),
+    .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid),
+    .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr),
+    .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size),
+    .io_sb_axi_w_valid(core_io_sb_axi_w_valid),
+    .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb),
+    .io_sb_axi_b_ready(core_io_sb_axi_b_ready),
+    .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid),
+    .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr),
+    .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size),
+    .io_sb_axi_r_ready(core_io_sb_axi_r_ready),
+    .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready),
+    .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready),
+    .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp),
+    .io_ahb_in_hready(core_io_ahb_in_hready),
+    .io_ahb_in_hresp(core_io_ahb_in_hresp),
+    .io_lsu_ahb_in_hready(core_io_lsu_ahb_in_hready),
+    .io_lsu_ahb_in_hresp(core_io_lsu_ahb_in_hresp),
+    .io_sb_ahb_in_hready(core_io_sb_ahb_in_hready),
+    .io_sb_ahb_in_hresp(core_io_sb_ahb_in_hresp),
+    .io_dma_ahb_out_haddr(core_io_dma_ahb_out_haddr),
+    .io_dma_ahb_out_hsize(core_io_dma_ahb_out_hsize),
+    .io_dma_ahb_out_htrans(core_io_dma_ahb_out_htrans),
+    .io_dma_ahb_out_hwrite(core_io_dma_ahb_out_hwrite),
+    .io_dma_hsel(core_io_dma_hsel),
+    .io_dma_hreadyin(core_io_dma_hreadyin),
+    .io_dbg_rst_l(core_io_dbg_rst_l),
+    .io_rst_vec(core_io_rst_vec),
+    .io_nmi_int(core_io_nmi_int),
+    .io_nmi_vec(core_io_nmi_vec),
+    .io_core_rst_l(core_io_core_rst_l),
+    .io_rv_trace_pkt_rv_i_valid_ip(core_io_rv_trace_pkt_rv_i_valid_ip),
+    .io_rv_trace_pkt_rv_i_insn_ip(core_io_rv_trace_pkt_rv_i_insn_ip),
+    .io_rv_trace_pkt_rv_i_address_ip(core_io_rv_trace_pkt_rv_i_address_ip),
+    .io_rv_trace_pkt_rv_i_exception_ip(core_io_rv_trace_pkt_rv_i_exception_ip),
+    .io_rv_trace_pkt_rv_i_ecause_ip(core_io_rv_trace_pkt_rv_i_ecause_ip),
+    .io_rv_trace_pkt_rv_i_interrupt_ip(core_io_rv_trace_pkt_rv_i_interrupt_ip),
+    .io_rv_trace_pkt_rv_i_tval_ip(core_io_rv_trace_pkt_rv_i_tval_ip),
+    .io_dccm_clk_override(core_io_dccm_clk_override),
+    .io_icm_clk_override(core_io_icm_clk_override),
+    .io_dec_tlu_core_ecc_disable(core_io_dec_tlu_core_ecc_disable),
+    .io_i_cpu_halt_req(core_io_i_cpu_halt_req),
+    .io_i_cpu_run_req(core_io_i_cpu_run_req),
+    .io_o_cpu_halt_ack(core_io_o_cpu_halt_ack),
+    .io_o_cpu_halt_status(core_io_o_cpu_halt_status),
+    .io_o_cpu_run_ack(core_io_o_cpu_run_ack),
+    .io_o_debug_mode_status(core_io_o_debug_mode_status),
+    .io_core_id(core_io_core_id),
+    .io_mpc_debug_halt_req(core_io_mpc_debug_halt_req),
+    .io_mpc_debug_run_req(core_io_mpc_debug_run_req),
+    .io_mpc_reset_run_req(core_io_mpc_reset_run_req),
+    .io_mpc_debug_halt_ack(core_io_mpc_debug_halt_ack),
+    .io_mpc_debug_run_ack(core_io_mpc_debug_run_ack),
+    .io_debug_brkpt_status(core_io_debug_brkpt_status),
+    .io_dec_tlu_perfcnt0(core_io_dec_tlu_perfcnt0),
+    .io_dec_tlu_perfcnt1(core_io_dec_tlu_perfcnt1),
+    .io_dec_tlu_perfcnt2(core_io_dec_tlu_perfcnt2),
+    .io_dec_tlu_perfcnt3(core_io_dec_tlu_perfcnt3),
+    .io_dccm_wren(core_io_dccm_wren),
+    .io_dccm_rden(core_io_dccm_rden),
+    .io_dccm_wr_addr_lo(core_io_dccm_wr_addr_lo),
+    .io_dccm_wr_addr_hi(core_io_dccm_wr_addr_hi),
+    .io_dccm_rd_addr_lo(core_io_dccm_rd_addr_lo),
+    .io_dccm_rd_addr_hi(core_io_dccm_rd_addr_hi),
+    .io_dccm_wr_data_lo(core_io_dccm_wr_data_lo),
+    .io_dccm_wr_data_hi(core_io_dccm_wr_data_hi),
+    .io_dccm_rd_data_lo(core_io_dccm_rd_data_lo),
+    .io_dccm_rd_data_hi(core_io_dccm_rd_data_hi),
+    .io_ic_rw_addr(core_io_ic_rw_addr),
+    .io_ic_tag_valid(core_io_ic_tag_valid),
+    .io_ic_rd_en(core_io_ic_rd_en),
+    .io_ic_debug_wr_data(core_io_ic_debug_wr_data),
+    .io_ic_debug_addr(core_io_ic_debug_addr),
+    .io_ic_rd_data(core_io_ic_rd_data),
+    .io_ic_debug_rd_data(core_io_ic_debug_rd_data),
+    .io_ic_tag_debug_rd_data(core_io_ic_tag_debug_rd_data),
+    .io_ic_eccerr(core_io_ic_eccerr),
+    .io_ic_rd_hit(core_io_ic_rd_hit),
+    .io_ic_tag_perr(core_io_ic_tag_perr),
+    .io_ic_debug_rd_en(core_io_ic_debug_rd_en),
+    .io_ic_debug_wr_en(core_io_ic_debug_wr_en),
+    .io_ic_debug_tag_array(core_io_ic_debug_tag_array),
+    .io_ic_debug_way(core_io_ic_debug_way),
+    .io_ic_premux_data(core_io_ic_premux_data),
+    .io_ic_sel_premux_data(core_io_ic_sel_premux_data),
+    .io_iccm_rw_addr(core_io_iccm_rw_addr),
+    .io_iccm_buf_correct_ecc(core_io_iccm_buf_correct_ecc),
+    .io_iccm_correction_state(core_io_iccm_correction_state),
+    .io_iccm_wren(core_io_iccm_wren),
+    .io_iccm_rden(core_io_iccm_rden),
+    .io_iccm_wr_size(core_io_iccm_wr_size),
+    .io_iccm_wr_data(core_io_iccm_wr_data),
+    .io_iccm_rd_data(core_io_iccm_rd_data),
+    .io_iccm_rd_data_ecc(core_io_iccm_rd_data_ecc),
+    .io_lsu_bus_clk_en(core_io_lsu_bus_clk_en),
+    .io_ifu_bus_clk_en(core_io_ifu_bus_clk_en),
+    .io_dbg_bus_clk_en(core_io_dbg_bus_clk_en),
+    .io_dma_bus_clk_en(core_io_dma_bus_clk_en),
+    .io_dmi_reg_en(core_io_dmi_reg_en),
+    .io_dmi_reg_addr(core_io_dmi_reg_addr),
+    .io_dmi_reg_wr_en(core_io_dmi_reg_wr_en),
+    .io_dmi_reg_wdata(core_io_dmi_reg_wdata),
+    .io_extintsrc_req(core_io_extintsrc_req),
+    .io_timer_int(core_io_timer_int),
+    .io_soft_int(core_io_soft_int),
+    .io_scan_mode(core_io_scan_mode)
   );
-  assign io_lsu_brg_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:22]
-  assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:22]
-  assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:22]
-  assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:22]
-  assign io_sb_brg_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 107:21]
-  assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 107:21]
-  assign io_dma_brg_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 108:22]
-  assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 108:22]
-  assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 160:23]
-  assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 161:23]
-  assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 162:23]
-  assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 163:23]
+  assign io_lsu_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_lsu_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 112:21]
+  assign io_ifu_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_ifu_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 111:17]
+  assign io_sb_brg_out_haddr = 32'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hburst = 3'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hmastlock = 1'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hprot = 4'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hsize = 3'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_htrans = 2'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hwrite = 1'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_sb_brg_out_hwdata = 64'h0; // @[quasar_wrapper.scala 113:20]
+  assign io_dma_brg_ahb_in_hrdata = 64'h0; // @[quasar_wrapper.scala 114:17]
+  assign io_dma_brg_ahb_in_hready = 1'h0; // @[quasar_wrapper.scala 114:17]
+  assign io_dma_brg_ahb_in_hresp = 1'h0; // @[quasar_wrapper.scala 114:17]
+  assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 160:23]
+  assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 161:23]
+  assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 162:23]
+  assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 163:23]
   assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 82:15]
-  assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 156:25]
-  assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 157:24]
-  assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 158:25]
-  assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 151:21]
-  assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 152:24]
-  assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 154:26]
-  assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 153:20]
-  assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 148:19]
-  assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 156:25]
+  assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 157:24]
+  assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 158:25]
+  assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 151:21]
+  assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 152:24]
+  assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 154:26]
+  assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 153:20]
+  assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 148:19]
+  assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 148:19]
   assign mem_clk = clock; // @[quasar_wrapper.scala 90:14]
   assign mem_rst_l = reset; // @[quasar_wrapper.scala 89:16]
-  assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 85:28]
-  assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 86:27]
-  assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 87:35]
-  assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 88:15]
-  assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 88:15]
-  assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 95:17]
-  assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 95:17]
-  assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 94:15]
-  assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 94:15]
+  assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 85:28]
+  assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 86:27]
+  assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 87:35]
+  assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 88:15]
+  assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 88:15]
+  assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 95:16]
+  assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 95:16]
+  assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_en = 2'h0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_data_0 = 71'h0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_wr_data_1 = 71'h0; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 94:14]
+  assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 94:14]
   assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 91:20]
   assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 67:25]
   assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 68:22]
@@ -84392,74 +82141,50 @@ module quasar_wrapper(
   assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 71:27]
   assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 72:26]
   assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26]
-  assign swerv_clock = clock;
-  assign swerv_reset = reset;
-  assign swerv_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:22]
-  assign swerv_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 106:22]
-  assign swerv_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 106:22]
-  assign swerv_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 106:22]
-  assign swerv_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 106:22]
-  assign swerv_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 106:22]
-  assign swerv_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 107:21]
-  assign swerv_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 108:22]
-  assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:22 quasar_wrapper.scala 122:22]
-  assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 123:20]
-  assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 124:20]
-  assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 125:20]
-  assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 128:27]
-  assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 129:26]
-  assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 130:20]
-  assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 133:31]
-  assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 134:30]
-  assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 135:30]
-  assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 88:15]
-  assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 88:15]
-  assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 94:15]
-  assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 95:17]
-  assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 95:17]
-  assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 137:27]
-  assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 138:27]
-  assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 139:27]
-  assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 140:27]
-  assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:23]
-  assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 78:25]
-  assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:26]
-  assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 77:26]
-  assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 144:26]
-  assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 142:22]
-  assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 143:21]
-  assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 66:22]
+  assign core_clock = clock;
+  assign core_reset = reset;
+  assign core_io_ahb_in_hready = io_ifu_brg_in_hready; // @[quasar_wrapper.scala 111:17]
+  assign core_io_ahb_in_hresp = io_ifu_brg_in_hresp; // @[quasar_wrapper.scala 111:17]
+  assign core_io_lsu_ahb_in_hready = io_lsu_brg_in_hready; // @[quasar_wrapper.scala 112:21]
+  assign core_io_lsu_ahb_in_hresp = io_lsu_brg_in_hresp; // @[quasar_wrapper.scala 112:21]
+  assign core_io_sb_ahb_in_hready = io_sb_brg_in_hready; // @[quasar_wrapper.scala 113:20]
+  assign core_io_sb_ahb_in_hresp = io_sb_brg_in_hresp; // @[quasar_wrapper.scala 113:20]
+  assign core_io_dma_ahb_out_haddr = io_dma_brg_ahb_out_haddr; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dma_ahb_out_hsize = io_dma_brg_ahb_out_hsize; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dma_ahb_out_htrans = io_dma_brg_ahb_out_htrans; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dma_ahb_out_hwrite = io_dma_brg_ahb_out_hwrite; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dma_hsel = io_dma_brg_hsel; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dma_hreadyin = io_dma_brg_hreadyin; // @[quasar_wrapper.scala 114:17]
+  assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 122:21]
+  assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 123:19]
+  assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 124:19]
+  assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 125:19]
+  assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 128:26]
+  assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 129:25]
+  assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 130:19]
+  assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 133:30]
+  assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 134:29]
+  assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 135:29]
+  assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 88:15]
+  assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 88:15]
+  assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 94:14]
+  assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 94:14]
+  assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 94:14]
+  assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 94:14]
+  assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 94:14]
+  assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 94:14]
+  assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 95:16]
+  assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 95:16]
+  assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 137:26]
+  assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 138:26]
+  assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 139:26]
+  assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 140:26]
+  assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:22]
+  assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 78:24]
+  assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:25]
+  assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 77:25]
+  assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 144:25]
+  assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 142:21]
+  assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 143:20]
+  assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 66:21]
 endmodule
diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala
index 0917162d..6571fff2 100644
--- a/src/main/scala/lib/param.scala
+++ b/src/main/scala/lib/param.scala
@@ -22,7 +22,7 @@ trait param {
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
   val BUILD_AHB_LITE         = 	0x0
-  val BUILD_AXI4             = 	0x1
+  val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3
   val DATA_ACCESS_ADDR0      = 	0x00000000
diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala
index 99d1c938..86e04fbb 100644
--- a/src/main/scala/quasar_wrapper.scala
+++ b/src/main/scala/quasar_wrapper.scala
@@ -62,105 +62,105 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   })
   val mem = Module(new quasar.mem())
   val dmi_wrapper = Module(new dmi_wrapper())
-  val swerv = Module(new quasar())
-  swerv.io.scan_mode := io.scan_mode
+  val core = Module(new quasar())
+  core.io.scan_mode := io.scan_mode
   dmi_wrapper.io.trst_n := io.jtag_trst_n
   dmi_wrapper.io.tck := io.jtag_tck
   dmi_wrapper.io.tms := io.jtag_tms
   dmi_wrapper.io.tdi := io.jtag_tdi
   dmi_wrapper.io.core_clk := clock
   dmi_wrapper.io.jtag_id := io.jtag_id
-  dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata
+  dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
 
 
   dmi_wrapper.io.core_rst_n := io.dbg_rst_l
-  swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
-  swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
-  swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en
-  swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
-  swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
+  core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
+  core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
+  core.io.dmi_reg_en := dmi_wrapper.io.reg_en
+  core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
+  core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
   io.jtag_tdo := dmi_wrapper.io.tdo
 
   // Memory signals
-  mem.io.dccm_clk_override := swerv.io.dccm_clk_override
-  mem.io.icm_clk_override := swerv.io.icm_clk_override
-  mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable
-  mem.io.dccm <> swerv.io.dccm
+  mem.io.dccm_clk_override := core.io.dccm_clk_override
+  mem.io.icm_clk_override := core.io.icm_clk_override
+  mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
+  mem.io.dccm <> core.io.dccm
   mem.io.rst_l := reset
   mem.io.clk := clock
   mem.io.scan_mode := io.scan_mode
   // Memory outputs
-  swerv.io.dbg_rst_l := io.dbg_rst_l
-  swerv.io.ic <> mem.io.ic
-  swerv.io.iccm <> mem.io.iccm
+  core.io.dbg_rst_l := io.dbg_rst_l
+  core.io.ic <> mem.io.ic
+  core.io.iccm <> mem.io.iccm
 
 
   if(BUILD_AXI4) {
-    swerv.io.ahb <> 0.U.asTypeOf(swerv.io.ahb)
-    swerv.io.lsu_ahb <> 0.U.asTypeOf(swerv.io.lsu_ahb)
-    swerv.io.sb_ahb <> 0.U.asTypeOf(swerv.io.sb_ahb)
-    swerv.io.dma.ahb <> 0.U.asTypeOf(swerv.io.dma.ahb)
-    swerv.io.dma.hsel := 0.U
-    swerv.io.dma.hreadyin := 0.U
-    swerv.io.lsu_axi <> io.lsu_brg
-    swerv.io.ifu_axi <> io.ifu_brg
-    swerv.io.sb_axi <> io.sb_brg
-    swerv.io.dma_axi <> io.dma_brg
+    core.io.ahb <> 0.U.asTypeOf(core.io.ahb)
+    core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
+    core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
+    core.io.dma.ahb <> 0.U.asTypeOf(core.io.dma.ahb)
+    core.io.dma.hsel := 0.U
+    core.io.dma.hreadyin := 0.U
+    core.io.lsu_axi <> io.lsu_brg
+    core.io.ifu_axi <> io.ifu_brg
+    core.io.sb_axi <> io.sb_brg
+    core.io.dma_axi <> io.dma_brg
   }
   else {
-    swerv.io.ahb <> io.ifu_brg
-    swerv.io.lsu_ahb <> io.lsu_brg
-    swerv.io.sb_ahb <> io.sb_brg
-    swerv.io.dma <> io.dma_brg
+    core.io.ahb <> io.ifu_brg
+    core.io.lsu_ahb <> io.lsu_brg
+    core.io.sb_ahb <> io.sb_brg
+    core.io.dma <> io.dma_brg
 
-    swerv.io.lsu_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
-    swerv.io.ifu_axi <> 0.U.asTypeOf(swerv.io.ifu_axi)
-    swerv.io.sb_axi <> 0.U.asTypeOf(swerv.io.sb_axi)
-    swerv.io.dma_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
+    core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
+    core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
+    core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
+    core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
   }
-  // SweRV Inputs
-  swerv.io.dbg_rst_l := io.dbg_rst_l
-  swerv.io.rst_vec := io.rst_vec
-  swerv.io.nmi_int := io.nmi_int
-  swerv.io.nmi_vec := io.nmi_vec
+  // core Inputs
+  core.io.dbg_rst_l := io.dbg_rst_l
+  core.io.rst_vec := io.rst_vec
+  core.io.nmi_int := io.nmi_int
+  core.io.nmi_vec := io.nmi_vec
 
   // external halt/run interface
-  swerv.io.i_cpu_halt_req := io.i_cpu_halt_req
-  swerv.io.i_cpu_run_req := io.i_cpu_run_req
-  swerv.io.core_id := io.core_id
+  core.io.i_cpu_halt_req := io.i_cpu_halt_req
+  core.io.i_cpu_run_req := io.i_cpu_run_req
+  core.io.core_id := io.core_id
 
   // external MPC halt/run interface
-  swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req
-  swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
-  swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
+  core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
+  core.io.mpc_debug_run_req := io.mpc_debug_run_req
+  core.io.mpc_reset_run_req := io.mpc_reset_run_req
 
-  swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
-  swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
-  swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
-  swerv.io.dma_bus_clk_en := io.dma_bus_clk_en
+  core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
+  core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
+  core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
+  core.io.dma_bus_clk_en := io.dma_bus_clk_en
 
-  swerv.io.timer_int := io.timer_int
-  swerv.io.soft_int := io.soft_int
-  swerv.io.extintsrc_req := io.extintsrc_req
+  core.io.timer_int := io.timer_int
+  core.io.soft_int := io.soft_int
+  core.io.extintsrc_req := io.extintsrc_req
 
   // Outputs
-  val core_rst_l = swerv.io.core_rst_l
-  io.rv_trace_pkt := swerv.io.rv_trace_pkt
+  val core_rst_l = core.io.core_rst_l
+  io.rv_trace_pkt := core.io.rv_trace_pkt
 
   // external halt/run interface
-  io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack
-  io.o_cpu_halt_status := swerv.io.o_cpu_halt_status
-  io.o_cpu_run_ack := swerv.io.o_cpu_run_ack
-  io.o_debug_mode_status := swerv.io.o_debug_mode_status
+  io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
+  io.o_cpu_halt_status := core.io.o_cpu_halt_status
+  io.o_cpu_run_ack := core.io.o_cpu_run_ack
+  io.o_debug_mode_status := core.io.o_debug_mode_status
 
-  io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack
-  io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack
-  io.debug_brkpt_status := swerv.io.debug_brkpt_status
+  io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
+  io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
+  io.debug_brkpt_status := core.io.debug_brkpt_status
 
-  io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0
-  io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1
-  io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
-  io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
+  io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
+  io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
+  io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
+  io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
 
 }
 object QUASAR_Wrp extends App {
diff --git a/target/scala-2.12/classes/dbg/dgb$.class b/target/scala-2.12/classes/dbg/dgb$.class
deleted file mode 100644
index 9ae9c352..00000000
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diff --git a/target/scala-2.12/classes/dbg/dgb$delayedInit$body.class b/target/scala-2.12/classes/dbg/dgb$delayedInit$body.class
deleted file mode 100644
index 9329560d..00000000
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diff --git a/target/scala-2.12/classes/dbg/dgb.class b/target/scala-2.12/classes/dbg/dgb.class
deleted file mode 100644
index 14a1779b..00000000
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diff --git a/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class
index 4343daa9..7cb29a3d 100644
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diff --git a/target/scala-2.12/classes/quasar_wrapper.class b/target/scala-2.12/classes/quasar_wrapper.class
index 681a32a4..e790d22c 100644
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