diff --git a/dbg.fir b/dbg.fir index 2eb3e425..d3ba81c9 100644 --- a/dbg.fir +++ b/dbg.fir @@ -147,7 +147,7 @@ circuit dbg : module dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") diff --git a/dbg.v b/dbg.v index 1ff57a64..3d32b5ff 100644 --- a/dbg.v +++ b/dbg.v @@ -81,12 +81,12 @@ module dbg( output io_dbg_dec_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_dbg_ib_dbg_cmd_valid, output io_dbg_dma_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_io_dbg_dma_bubble, input io_dbg_dma_io_dma_dbg_ready, input io_dbg_bus_clk_en, @@ -678,7 +678,7 @@ module dbg( assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] - assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg[1:0]; // @[dbg.scala 325:38] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index d4456bc6..40eae7ce 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/waleedbinehsan/Desktop/Quasar/gated_latch.v \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar/gated_latch.v +/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv +/home/waleedbinehsan/Desktop/Quasar/mem.sv \ No newline at end of file diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index f9da6512..f0cab509 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -66826,7 +66826,7 @@ circuit quasar_wrapper : module dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38] _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] @@ -80307,889 +80307,893 @@ circuit quasar_wrapper : node _T_403 = cat(_T_402, _T_399) @[lib.scala 89:14] node _T_404 = cat(_T_403, _T_396) @[lib.scala 89:14] node _T_405 = cat(_T_404, _T_389) @[lib.scala 89:14] - node _T_406 = and(_T_148, _T_405) @[dec_trigger.scala 15:109] - node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_409 : UInt<1>[32] @[lib.scala 84:24] - node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] - node _T_411 = not(_T_410) @[lib.scala 85:39] - node _T_412 = and(_T_408, _T_411) @[lib.scala 85:37] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] - node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 86:60] - node _T_415 = eq(_T_413, _T_414) @[lib.scala 86:52] - node _T_416 = or(_T_412, _T_415) @[lib.scala 86:41] - _T_409[0] <= _T_416 @[lib.scala 86:18] - node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] - node _T_418 = andr(_T_417) @[lib.scala 88:36] - node _T_419 = and(_T_418, _T_412) @[lib.scala 88:41] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] - node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 88:86] - node _T_422 = eq(_T_420, _T_421) @[lib.scala 88:78] - node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[lib.scala 88:23] - _T_409[1] <= _T_423 @[lib.scala 88:17] - node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] - node _T_425 = andr(_T_424) @[lib.scala 88:36] - node _T_426 = and(_T_425, _T_412) @[lib.scala 88:41] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] - node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 88:86] - node _T_429 = eq(_T_427, _T_428) @[lib.scala 88:78] - node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[lib.scala 88:23] - _T_409[2] <= _T_430 @[lib.scala 88:17] - node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] - node _T_432 = andr(_T_431) @[lib.scala 88:36] - node _T_433 = and(_T_432, _T_412) @[lib.scala 88:41] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] - node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 88:86] - node _T_436 = eq(_T_434, _T_435) @[lib.scala 88:78] - node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[lib.scala 88:23] - _T_409[3] <= _T_437 @[lib.scala 88:17] - node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] - node _T_439 = andr(_T_438) @[lib.scala 88:36] - node _T_440 = and(_T_439, _T_412) @[lib.scala 88:41] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] - node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 88:86] - node _T_443 = eq(_T_441, _T_442) @[lib.scala 88:78] - node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[lib.scala 88:23] - _T_409[4] <= _T_444 @[lib.scala 88:17] - node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] - node _T_446 = andr(_T_445) @[lib.scala 88:36] - node _T_447 = and(_T_446, _T_412) @[lib.scala 88:41] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] - node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 88:86] - node _T_450 = eq(_T_448, _T_449) @[lib.scala 88:78] - node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[lib.scala 88:23] - _T_409[5] <= _T_451 @[lib.scala 88:17] - node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] - node _T_453 = andr(_T_452) @[lib.scala 88:36] - node _T_454 = and(_T_453, _T_412) @[lib.scala 88:41] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] - node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 88:86] - node _T_457 = eq(_T_455, _T_456) @[lib.scala 88:78] - node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[lib.scala 88:23] - _T_409[6] <= _T_458 @[lib.scala 88:17] - node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] - node _T_460 = andr(_T_459) @[lib.scala 88:36] - node _T_461 = and(_T_460, _T_412) @[lib.scala 88:41] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] - node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 88:86] - node _T_464 = eq(_T_462, _T_463) @[lib.scala 88:78] - node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[lib.scala 88:23] - _T_409[7] <= _T_465 @[lib.scala 88:17] - node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] - node _T_467 = andr(_T_466) @[lib.scala 88:36] - node _T_468 = and(_T_467, _T_412) @[lib.scala 88:41] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] - node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 88:86] - node _T_471 = eq(_T_469, _T_470) @[lib.scala 88:78] - node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[lib.scala 88:23] - _T_409[8] <= _T_472 @[lib.scala 88:17] - node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] - node _T_474 = andr(_T_473) @[lib.scala 88:36] - node _T_475 = and(_T_474, _T_412) @[lib.scala 88:41] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] - node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 88:86] - node _T_478 = eq(_T_476, _T_477) @[lib.scala 88:78] - node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[lib.scala 88:23] - _T_409[9] <= _T_479 @[lib.scala 88:17] - node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] - node _T_481 = andr(_T_480) @[lib.scala 88:36] - node _T_482 = and(_T_481, _T_412) @[lib.scala 88:41] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] - node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 88:86] - node _T_485 = eq(_T_483, _T_484) @[lib.scala 88:78] - node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[lib.scala 88:23] - _T_409[10] <= _T_486 @[lib.scala 88:17] - node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] - node _T_488 = andr(_T_487) @[lib.scala 88:36] - node _T_489 = and(_T_488, _T_412) @[lib.scala 88:41] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] - node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 88:86] - node _T_492 = eq(_T_490, _T_491) @[lib.scala 88:78] - node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[lib.scala 88:23] - _T_409[11] <= _T_493 @[lib.scala 88:17] - node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] - node _T_495 = andr(_T_494) @[lib.scala 88:36] - node _T_496 = and(_T_495, _T_412) @[lib.scala 88:41] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] - node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 88:86] - node _T_499 = eq(_T_497, _T_498) @[lib.scala 88:78] - node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[lib.scala 88:23] - _T_409[12] <= _T_500 @[lib.scala 88:17] - node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] - node _T_502 = andr(_T_501) @[lib.scala 88:36] - node _T_503 = and(_T_502, _T_412) @[lib.scala 88:41] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] - node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 88:86] - node _T_506 = eq(_T_504, _T_505) @[lib.scala 88:78] - node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[lib.scala 88:23] - _T_409[13] <= _T_507 @[lib.scala 88:17] - node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] - node _T_509 = andr(_T_508) @[lib.scala 88:36] - node _T_510 = and(_T_509, _T_412) @[lib.scala 88:41] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] - node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 88:86] - node _T_513 = eq(_T_511, _T_512) @[lib.scala 88:78] - node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[lib.scala 88:23] - _T_409[14] <= _T_514 @[lib.scala 88:17] - node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] - node _T_516 = andr(_T_515) @[lib.scala 88:36] - node _T_517 = and(_T_516, _T_412) @[lib.scala 88:41] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] - node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 88:86] - node _T_520 = eq(_T_518, _T_519) @[lib.scala 88:78] - node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[lib.scala 88:23] - _T_409[15] <= _T_521 @[lib.scala 88:17] - node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] - node _T_523 = andr(_T_522) @[lib.scala 88:36] - node _T_524 = and(_T_523, _T_412) @[lib.scala 88:41] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] - node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 88:86] - node _T_527 = eq(_T_525, _T_526) @[lib.scala 88:78] - node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[lib.scala 88:23] - _T_409[16] <= _T_528 @[lib.scala 88:17] - node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] - node _T_530 = andr(_T_529) @[lib.scala 88:36] - node _T_531 = and(_T_530, _T_412) @[lib.scala 88:41] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] - node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 88:86] - node _T_534 = eq(_T_532, _T_533) @[lib.scala 88:78] - node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[lib.scala 88:23] - _T_409[17] <= _T_535 @[lib.scala 88:17] - node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] - node _T_537 = andr(_T_536) @[lib.scala 88:36] - node _T_538 = and(_T_537, _T_412) @[lib.scala 88:41] - node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] - node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 88:86] - node _T_541 = eq(_T_539, _T_540) @[lib.scala 88:78] - node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[lib.scala 88:23] - _T_409[18] <= _T_542 @[lib.scala 88:17] - node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] - node _T_544 = andr(_T_543) @[lib.scala 88:36] - node _T_545 = and(_T_544, _T_412) @[lib.scala 88:41] - node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] - node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 88:86] - node _T_548 = eq(_T_546, _T_547) @[lib.scala 88:78] - node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[lib.scala 88:23] - _T_409[19] <= _T_549 @[lib.scala 88:17] - node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] - node _T_551 = andr(_T_550) @[lib.scala 88:36] - node _T_552 = and(_T_551, _T_412) @[lib.scala 88:41] - node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] - node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 88:86] - node _T_555 = eq(_T_553, _T_554) @[lib.scala 88:78] - node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[lib.scala 88:23] - _T_409[20] <= _T_556 @[lib.scala 88:17] - node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] - node _T_558 = andr(_T_557) @[lib.scala 88:36] - node _T_559 = and(_T_558, _T_412) @[lib.scala 88:41] - node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] - node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 88:86] - node _T_562 = eq(_T_560, _T_561) @[lib.scala 88:78] - node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[lib.scala 88:23] - _T_409[21] <= _T_563 @[lib.scala 88:17] - node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] - node _T_565 = andr(_T_564) @[lib.scala 88:36] - node _T_566 = and(_T_565, _T_412) @[lib.scala 88:41] - node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] - node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 88:86] - node _T_569 = eq(_T_567, _T_568) @[lib.scala 88:78] - node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[lib.scala 88:23] - _T_409[22] <= _T_570 @[lib.scala 88:17] - node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] - node _T_572 = andr(_T_571) @[lib.scala 88:36] - node _T_573 = and(_T_572, _T_412) @[lib.scala 88:41] - node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] - node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 88:86] - node _T_576 = eq(_T_574, _T_575) @[lib.scala 88:78] - node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[lib.scala 88:23] - _T_409[23] <= _T_577 @[lib.scala 88:17] - node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] - node _T_579 = andr(_T_578) @[lib.scala 88:36] - node _T_580 = and(_T_579, _T_412) @[lib.scala 88:41] - node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] - node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 88:86] - node _T_583 = eq(_T_581, _T_582) @[lib.scala 88:78] - node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[lib.scala 88:23] - _T_409[24] <= _T_584 @[lib.scala 88:17] - node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] - node _T_586 = andr(_T_585) @[lib.scala 88:36] - node _T_587 = and(_T_586, _T_412) @[lib.scala 88:41] - node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] - node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 88:86] - node _T_590 = eq(_T_588, _T_589) @[lib.scala 88:78] - node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[lib.scala 88:23] - _T_409[25] <= _T_591 @[lib.scala 88:17] - node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] - node _T_593 = andr(_T_592) @[lib.scala 88:36] - node _T_594 = and(_T_593, _T_412) @[lib.scala 88:41] - node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] - node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 88:86] - node _T_597 = eq(_T_595, _T_596) @[lib.scala 88:78] - node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[lib.scala 88:23] - _T_409[26] <= _T_598 @[lib.scala 88:17] - node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] - node _T_600 = andr(_T_599) @[lib.scala 88:36] - node _T_601 = and(_T_600, _T_412) @[lib.scala 88:41] - node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] - node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 88:86] - node _T_604 = eq(_T_602, _T_603) @[lib.scala 88:78] - node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[lib.scala 88:23] - _T_409[27] <= _T_605 @[lib.scala 88:17] - node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] - node _T_607 = andr(_T_606) @[lib.scala 88:36] - node _T_608 = and(_T_607, _T_412) @[lib.scala 88:41] - node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] - node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 88:86] - node _T_611 = eq(_T_609, _T_610) @[lib.scala 88:78] - node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[lib.scala 88:23] - _T_409[28] <= _T_612 @[lib.scala 88:17] - node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] - node _T_614 = andr(_T_613) @[lib.scala 88:36] - node _T_615 = and(_T_614, _T_412) @[lib.scala 88:41] - node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] - node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 88:86] - node _T_618 = eq(_T_616, _T_617) @[lib.scala 88:78] - node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[lib.scala 88:23] - _T_409[29] <= _T_619 @[lib.scala 88:17] - node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] - node _T_621 = andr(_T_620) @[lib.scala 88:36] - node _T_622 = and(_T_621, _T_412) @[lib.scala 88:41] - node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] - node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 88:86] - node _T_625 = eq(_T_623, _T_624) @[lib.scala 88:78] - node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[lib.scala 88:23] - _T_409[30] <= _T_626 @[lib.scala 88:17] - node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] - node _T_628 = andr(_T_627) @[lib.scala 88:36] - node _T_629 = and(_T_628, _T_412) @[lib.scala 88:41] - node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] - node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 88:86] - node _T_632 = eq(_T_630, _T_631) @[lib.scala 88:78] - node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[lib.scala 88:23] - _T_409[31] <= _T_633 @[lib.scala 88:17] - node _T_634 = cat(_T_409[1], _T_409[0]) @[lib.scala 89:14] - node _T_635 = cat(_T_409[3], _T_409[2]) @[lib.scala 89:14] - node _T_636 = cat(_T_635, _T_634) @[lib.scala 89:14] - node _T_637 = cat(_T_409[5], _T_409[4]) @[lib.scala 89:14] - node _T_638 = cat(_T_409[7], _T_409[6]) @[lib.scala 89:14] - node _T_639 = cat(_T_638, _T_637) @[lib.scala 89:14] - node _T_640 = cat(_T_639, _T_636) @[lib.scala 89:14] - node _T_641 = cat(_T_409[9], _T_409[8]) @[lib.scala 89:14] - node _T_642 = cat(_T_409[11], _T_409[10]) @[lib.scala 89:14] - node _T_643 = cat(_T_642, _T_641) @[lib.scala 89:14] - node _T_644 = cat(_T_409[13], _T_409[12]) @[lib.scala 89:14] - node _T_645 = cat(_T_409[15], _T_409[14]) @[lib.scala 89:14] - node _T_646 = cat(_T_645, _T_644) @[lib.scala 89:14] - node _T_647 = cat(_T_646, _T_643) @[lib.scala 89:14] - node _T_648 = cat(_T_647, _T_640) @[lib.scala 89:14] - node _T_649 = cat(_T_409[17], _T_409[16]) @[lib.scala 89:14] - node _T_650 = cat(_T_409[19], _T_409[18]) @[lib.scala 89:14] - node _T_651 = cat(_T_650, _T_649) @[lib.scala 89:14] - node _T_652 = cat(_T_409[21], _T_409[20]) @[lib.scala 89:14] - node _T_653 = cat(_T_409[23], _T_409[22]) @[lib.scala 89:14] - node _T_654 = cat(_T_653, _T_652) @[lib.scala 89:14] - node _T_655 = cat(_T_654, _T_651) @[lib.scala 89:14] - node _T_656 = cat(_T_409[25], _T_409[24]) @[lib.scala 89:14] - node _T_657 = cat(_T_409[27], _T_409[26]) @[lib.scala 89:14] - node _T_658 = cat(_T_657, _T_656) @[lib.scala 89:14] - node _T_659 = cat(_T_409[29], _T_409[28]) @[lib.scala 89:14] - node _T_660 = cat(_T_409[31], _T_409[30]) @[lib.scala 89:14] - node _T_661 = cat(_T_660, _T_659) @[lib.scala 89:14] - node _T_662 = cat(_T_661, _T_658) @[lib.scala 89:14] - node _T_663 = cat(_T_662, _T_655) @[lib.scala 89:14] - node _T_664 = cat(_T_663, _T_648) @[lib.scala 89:14] - node _T_665 = and(_T_407, _T_664) @[dec_trigger.scala 15:109] - node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_668 : UInt<1>[32] @[lib.scala 84:24] - node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] - node _T_670 = not(_T_669) @[lib.scala 85:39] - node _T_671 = and(_T_667, _T_670) @[lib.scala 85:37] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] - node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 86:60] - node _T_674 = eq(_T_672, _T_673) @[lib.scala 86:52] - node _T_675 = or(_T_671, _T_674) @[lib.scala 86:41] - _T_668[0] <= _T_675 @[lib.scala 86:18] - node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] - node _T_677 = andr(_T_676) @[lib.scala 88:36] - node _T_678 = and(_T_677, _T_671) @[lib.scala 88:41] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] - node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 88:86] - node _T_681 = eq(_T_679, _T_680) @[lib.scala 88:78] - node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[lib.scala 88:23] - _T_668[1] <= _T_682 @[lib.scala 88:17] - node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] - node _T_684 = andr(_T_683) @[lib.scala 88:36] - node _T_685 = and(_T_684, _T_671) @[lib.scala 88:41] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] - node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 88:86] - node _T_688 = eq(_T_686, _T_687) @[lib.scala 88:78] - node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[lib.scala 88:23] - _T_668[2] <= _T_689 @[lib.scala 88:17] - node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] - node _T_691 = andr(_T_690) @[lib.scala 88:36] - node _T_692 = and(_T_691, _T_671) @[lib.scala 88:41] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] - node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 88:86] - node _T_695 = eq(_T_693, _T_694) @[lib.scala 88:78] - node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[lib.scala 88:23] - _T_668[3] <= _T_696 @[lib.scala 88:17] - node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] - node _T_698 = andr(_T_697) @[lib.scala 88:36] - node _T_699 = and(_T_698, _T_671) @[lib.scala 88:41] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] - node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 88:86] - node _T_702 = eq(_T_700, _T_701) @[lib.scala 88:78] - node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[lib.scala 88:23] - _T_668[4] <= _T_703 @[lib.scala 88:17] - node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] - node _T_705 = andr(_T_704) @[lib.scala 88:36] - node _T_706 = and(_T_705, _T_671) @[lib.scala 88:41] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] - node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 88:86] - node _T_709 = eq(_T_707, _T_708) @[lib.scala 88:78] - node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[lib.scala 88:23] - _T_668[5] <= _T_710 @[lib.scala 88:17] - node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] - node _T_712 = andr(_T_711) @[lib.scala 88:36] - node _T_713 = and(_T_712, _T_671) @[lib.scala 88:41] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] - node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 88:86] - node _T_716 = eq(_T_714, _T_715) @[lib.scala 88:78] - node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[lib.scala 88:23] - _T_668[6] <= _T_717 @[lib.scala 88:17] - node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] - node _T_719 = andr(_T_718) @[lib.scala 88:36] - node _T_720 = and(_T_719, _T_671) @[lib.scala 88:41] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] - node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 88:86] - node _T_723 = eq(_T_721, _T_722) @[lib.scala 88:78] - node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[lib.scala 88:23] - _T_668[7] <= _T_724 @[lib.scala 88:17] - node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] - node _T_726 = andr(_T_725) @[lib.scala 88:36] - node _T_727 = and(_T_726, _T_671) @[lib.scala 88:41] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] - node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 88:86] - node _T_730 = eq(_T_728, _T_729) @[lib.scala 88:78] - node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[lib.scala 88:23] - _T_668[8] <= _T_731 @[lib.scala 88:17] - node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] - node _T_733 = andr(_T_732) @[lib.scala 88:36] - node _T_734 = and(_T_733, _T_671) @[lib.scala 88:41] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] - node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 88:86] - node _T_737 = eq(_T_735, _T_736) @[lib.scala 88:78] - node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[lib.scala 88:23] - _T_668[9] <= _T_738 @[lib.scala 88:17] - node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] - node _T_740 = andr(_T_739) @[lib.scala 88:36] - node _T_741 = and(_T_740, _T_671) @[lib.scala 88:41] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] - node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 88:86] - node _T_744 = eq(_T_742, _T_743) @[lib.scala 88:78] - node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[lib.scala 88:23] - _T_668[10] <= _T_745 @[lib.scala 88:17] - node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] - node _T_747 = andr(_T_746) @[lib.scala 88:36] - node _T_748 = and(_T_747, _T_671) @[lib.scala 88:41] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] - node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 88:86] - node _T_751 = eq(_T_749, _T_750) @[lib.scala 88:78] - node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[lib.scala 88:23] - _T_668[11] <= _T_752 @[lib.scala 88:17] - node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] - node _T_754 = andr(_T_753) @[lib.scala 88:36] - node _T_755 = and(_T_754, _T_671) @[lib.scala 88:41] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] - node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 88:86] - node _T_758 = eq(_T_756, _T_757) @[lib.scala 88:78] - node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[lib.scala 88:23] - _T_668[12] <= _T_759 @[lib.scala 88:17] - node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] - node _T_761 = andr(_T_760) @[lib.scala 88:36] - node _T_762 = and(_T_761, _T_671) @[lib.scala 88:41] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] - node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 88:86] - node _T_765 = eq(_T_763, _T_764) @[lib.scala 88:78] - node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[lib.scala 88:23] - _T_668[13] <= _T_766 @[lib.scala 88:17] - node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] - node _T_768 = andr(_T_767) @[lib.scala 88:36] - node _T_769 = and(_T_768, _T_671) @[lib.scala 88:41] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] - node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 88:86] - node _T_772 = eq(_T_770, _T_771) @[lib.scala 88:78] - node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[lib.scala 88:23] - _T_668[14] <= _T_773 @[lib.scala 88:17] - node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] - node _T_775 = andr(_T_774) @[lib.scala 88:36] - node _T_776 = and(_T_775, _T_671) @[lib.scala 88:41] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] - node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 88:86] - node _T_779 = eq(_T_777, _T_778) @[lib.scala 88:78] - node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[lib.scala 88:23] - _T_668[15] <= _T_780 @[lib.scala 88:17] - node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] - node _T_782 = andr(_T_781) @[lib.scala 88:36] - node _T_783 = and(_T_782, _T_671) @[lib.scala 88:41] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] - node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 88:86] - node _T_786 = eq(_T_784, _T_785) @[lib.scala 88:78] - node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[lib.scala 88:23] - _T_668[16] <= _T_787 @[lib.scala 88:17] - node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] - node _T_789 = andr(_T_788) @[lib.scala 88:36] - node _T_790 = and(_T_789, _T_671) @[lib.scala 88:41] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] - node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 88:86] - node _T_793 = eq(_T_791, _T_792) @[lib.scala 88:78] - node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[lib.scala 88:23] - _T_668[17] <= _T_794 @[lib.scala 88:17] - node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] - node _T_796 = andr(_T_795) @[lib.scala 88:36] - node _T_797 = and(_T_796, _T_671) @[lib.scala 88:41] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] - node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 88:86] - node _T_800 = eq(_T_798, _T_799) @[lib.scala 88:78] - node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[lib.scala 88:23] - _T_668[18] <= _T_801 @[lib.scala 88:17] - node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] - node _T_803 = andr(_T_802) @[lib.scala 88:36] - node _T_804 = and(_T_803, _T_671) @[lib.scala 88:41] - node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] - node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 88:86] - node _T_807 = eq(_T_805, _T_806) @[lib.scala 88:78] - node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[lib.scala 88:23] - _T_668[19] <= _T_808 @[lib.scala 88:17] - node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] - node _T_810 = andr(_T_809) @[lib.scala 88:36] - node _T_811 = and(_T_810, _T_671) @[lib.scala 88:41] - node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] - node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 88:86] - node _T_814 = eq(_T_812, _T_813) @[lib.scala 88:78] - node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[lib.scala 88:23] - _T_668[20] <= _T_815 @[lib.scala 88:17] - node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] - node _T_817 = andr(_T_816) @[lib.scala 88:36] - node _T_818 = and(_T_817, _T_671) @[lib.scala 88:41] - node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] - node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 88:86] - node _T_821 = eq(_T_819, _T_820) @[lib.scala 88:78] - node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[lib.scala 88:23] - _T_668[21] <= _T_822 @[lib.scala 88:17] - node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] - node _T_824 = andr(_T_823) @[lib.scala 88:36] - node _T_825 = and(_T_824, _T_671) @[lib.scala 88:41] - node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] - node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 88:86] - node _T_828 = eq(_T_826, _T_827) @[lib.scala 88:78] - node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[lib.scala 88:23] - _T_668[22] <= _T_829 @[lib.scala 88:17] - node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] - node _T_831 = andr(_T_830) @[lib.scala 88:36] - node _T_832 = and(_T_831, _T_671) @[lib.scala 88:41] - node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] - node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 88:86] - node _T_835 = eq(_T_833, _T_834) @[lib.scala 88:78] - node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[lib.scala 88:23] - _T_668[23] <= _T_836 @[lib.scala 88:17] - node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] - node _T_838 = andr(_T_837) @[lib.scala 88:36] - node _T_839 = and(_T_838, _T_671) @[lib.scala 88:41] - node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] - node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 88:86] - node _T_842 = eq(_T_840, _T_841) @[lib.scala 88:78] - node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[lib.scala 88:23] - _T_668[24] <= _T_843 @[lib.scala 88:17] - node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] - node _T_845 = andr(_T_844) @[lib.scala 88:36] - node _T_846 = and(_T_845, _T_671) @[lib.scala 88:41] - node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] - node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 88:86] - node _T_849 = eq(_T_847, _T_848) @[lib.scala 88:78] - node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[lib.scala 88:23] - _T_668[25] <= _T_850 @[lib.scala 88:17] - node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] - node _T_852 = andr(_T_851) @[lib.scala 88:36] - node _T_853 = and(_T_852, _T_671) @[lib.scala 88:41] - node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] - node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 88:86] - node _T_856 = eq(_T_854, _T_855) @[lib.scala 88:78] - node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[lib.scala 88:23] - _T_668[26] <= _T_857 @[lib.scala 88:17] - node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] - node _T_859 = andr(_T_858) @[lib.scala 88:36] - node _T_860 = and(_T_859, _T_671) @[lib.scala 88:41] - node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] - node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 88:86] - node _T_863 = eq(_T_861, _T_862) @[lib.scala 88:78] - node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[lib.scala 88:23] - _T_668[27] <= _T_864 @[lib.scala 88:17] - node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] - node _T_866 = andr(_T_865) @[lib.scala 88:36] - node _T_867 = and(_T_866, _T_671) @[lib.scala 88:41] - node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] - node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 88:86] - node _T_870 = eq(_T_868, _T_869) @[lib.scala 88:78] - node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[lib.scala 88:23] - _T_668[28] <= _T_871 @[lib.scala 88:17] - node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] - node _T_873 = andr(_T_872) @[lib.scala 88:36] - node _T_874 = and(_T_873, _T_671) @[lib.scala 88:41] - node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] - node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 88:86] - node _T_877 = eq(_T_875, _T_876) @[lib.scala 88:78] - node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[lib.scala 88:23] - _T_668[29] <= _T_878 @[lib.scala 88:17] - node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] - node _T_880 = andr(_T_879) @[lib.scala 88:36] - node _T_881 = and(_T_880, _T_671) @[lib.scala 88:41] - node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] - node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 88:86] - node _T_884 = eq(_T_882, _T_883) @[lib.scala 88:78] - node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[lib.scala 88:23] - _T_668[30] <= _T_885 @[lib.scala 88:17] - node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] - node _T_887 = andr(_T_886) @[lib.scala 88:36] - node _T_888 = and(_T_887, _T_671) @[lib.scala 88:41] - node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] - node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 88:86] - node _T_891 = eq(_T_889, _T_890) @[lib.scala 88:78] - node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[lib.scala 88:23] - _T_668[31] <= _T_892 @[lib.scala 88:17] - node _T_893 = cat(_T_668[1], _T_668[0]) @[lib.scala 89:14] - node _T_894 = cat(_T_668[3], _T_668[2]) @[lib.scala 89:14] - node _T_895 = cat(_T_894, _T_893) @[lib.scala 89:14] - node _T_896 = cat(_T_668[5], _T_668[4]) @[lib.scala 89:14] - node _T_897 = cat(_T_668[7], _T_668[6]) @[lib.scala 89:14] - node _T_898 = cat(_T_897, _T_896) @[lib.scala 89:14] - node _T_899 = cat(_T_898, _T_895) @[lib.scala 89:14] - node _T_900 = cat(_T_668[9], _T_668[8]) @[lib.scala 89:14] - node _T_901 = cat(_T_668[11], _T_668[10]) @[lib.scala 89:14] - node _T_902 = cat(_T_901, _T_900) @[lib.scala 89:14] - node _T_903 = cat(_T_668[13], _T_668[12]) @[lib.scala 89:14] - node _T_904 = cat(_T_668[15], _T_668[14]) @[lib.scala 89:14] - node _T_905 = cat(_T_904, _T_903) @[lib.scala 89:14] - node _T_906 = cat(_T_905, _T_902) @[lib.scala 89:14] - node _T_907 = cat(_T_906, _T_899) @[lib.scala 89:14] - node _T_908 = cat(_T_668[17], _T_668[16]) @[lib.scala 89:14] - node _T_909 = cat(_T_668[19], _T_668[18]) @[lib.scala 89:14] - node _T_910 = cat(_T_909, _T_908) @[lib.scala 89:14] - node _T_911 = cat(_T_668[21], _T_668[20]) @[lib.scala 89:14] - node _T_912 = cat(_T_668[23], _T_668[22]) @[lib.scala 89:14] - node _T_913 = cat(_T_912, _T_911) @[lib.scala 89:14] - node _T_914 = cat(_T_913, _T_910) @[lib.scala 89:14] - node _T_915 = cat(_T_668[25], _T_668[24]) @[lib.scala 89:14] - node _T_916 = cat(_T_668[27], _T_668[26]) @[lib.scala 89:14] - node _T_917 = cat(_T_916, _T_915) @[lib.scala 89:14] - node _T_918 = cat(_T_668[29], _T_668[28]) @[lib.scala 89:14] - node _T_919 = cat(_T_668[31], _T_668[30]) @[lib.scala 89:14] - node _T_920 = cat(_T_919, _T_918) @[lib.scala 89:14] - node _T_921 = cat(_T_920, _T_917) @[lib.scala 89:14] - node _T_922 = cat(_T_921, _T_914) @[lib.scala 89:14] - node _T_923 = cat(_T_922, _T_907) @[lib.scala 89:14] - node _T_924 = and(_T_666, _T_923) @[dec_trigger.scala 15:109] - node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_927 : UInt<1>[32] @[lib.scala 84:24] - node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] - node _T_929 = not(_T_928) @[lib.scala 85:39] - node _T_930 = and(_T_926, _T_929) @[lib.scala 85:37] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] - node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 86:60] - node _T_933 = eq(_T_931, _T_932) @[lib.scala 86:52] - node _T_934 = or(_T_930, _T_933) @[lib.scala 86:41] - _T_927[0] <= _T_934 @[lib.scala 86:18] - node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] - node _T_936 = andr(_T_935) @[lib.scala 88:36] - node _T_937 = and(_T_936, _T_930) @[lib.scala 88:41] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] - node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 88:86] - node _T_940 = eq(_T_938, _T_939) @[lib.scala 88:78] - node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[lib.scala 88:23] - _T_927[1] <= _T_941 @[lib.scala 88:17] - node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] - node _T_943 = andr(_T_942) @[lib.scala 88:36] - node _T_944 = and(_T_943, _T_930) @[lib.scala 88:41] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] - node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 88:86] - node _T_947 = eq(_T_945, _T_946) @[lib.scala 88:78] - node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[lib.scala 88:23] - _T_927[2] <= _T_948 @[lib.scala 88:17] - node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] - node _T_950 = andr(_T_949) @[lib.scala 88:36] - node _T_951 = and(_T_950, _T_930) @[lib.scala 88:41] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] - node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 88:86] - node _T_954 = eq(_T_952, _T_953) @[lib.scala 88:78] - node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[lib.scala 88:23] - _T_927[3] <= _T_955 @[lib.scala 88:17] - node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] - node _T_957 = andr(_T_956) @[lib.scala 88:36] - node _T_958 = and(_T_957, _T_930) @[lib.scala 88:41] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] - node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 88:86] - node _T_961 = eq(_T_959, _T_960) @[lib.scala 88:78] - node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[lib.scala 88:23] - _T_927[4] <= _T_962 @[lib.scala 88:17] - node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] - node _T_964 = andr(_T_963) @[lib.scala 88:36] - node _T_965 = and(_T_964, _T_930) @[lib.scala 88:41] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] - node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 88:86] - node _T_968 = eq(_T_966, _T_967) @[lib.scala 88:78] - node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[lib.scala 88:23] - _T_927[5] <= _T_969 @[lib.scala 88:17] - node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] - node _T_971 = andr(_T_970) @[lib.scala 88:36] - node _T_972 = and(_T_971, _T_930) @[lib.scala 88:41] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] - node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 88:86] - node _T_975 = eq(_T_973, _T_974) @[lib.scala 88:78] - node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[lib.scala 88:23] - _T_927[6] <= _T_976 @[lib.scala 88:17] - node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] - node _T_978 = andr(_T_977) @[lib.scala 88:36] - node _T_979 = and(_T_978, _T_930) @[lib.scala 88:41] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] - node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 88:86] - node _T_982 = eq(_T_980, _T_981) @[lib.scala 88:78] - node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[lib.scala 88:23] - _T_927[7] <= _T_983 @[lib.scala 88:17] - node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] - node _T_985 = andr(_T_984) @[lib.scala 88:36] - node _T_986 = and(_T_985, _T_930) @[lib.scala 88:41] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] - node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 88:86] - node _T_989 = eq(_T_987, _T_988) @[lib.scala 88:78] - node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[lib.scala 88:23] - _T_927[8] <= _T_990 @[lib.scala 88:17] - node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] - node _T_992 = andr(_T_991) @[lib.scala 88:36] - node _T_993 = and(_T_992, _T_930) @[lib.scala 88:41] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] - node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 88:86] - node _T_996 = eq(_T_994, _T_995) @[lib.scala 88:78] - node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[lib.scala 88:23] - _T_927[9] <= _T_997 @[lib.scala 88:17] - node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] - node _T_999 = andr(_T_998) @[lib.scala 88:36] - node _T_1000 = and(_T_999, _T_930) @[lib.scala 88:41] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] - node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 88:86] - node _T_1003 = eq(_T_1001, _T_1002) @[lib.scala 88:78] - node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[lib.scala 88:23] - _T_927[10] <= _T_1004 @[lib.scala 88:17] - node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] - node _T_1006 = andr(_T_1005) @[lib.scala 88:36] - node _T_1007 = and(_T_1006, _T_930) @[lib.scala 88:41] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] - node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 88:86] - node _T_1010 = eq(_T_1008, _T_1009) @[lib.scala 88:78] - node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[lib.scala 88:23] - _T_927[11] <= _T_1011 @[lib.scala 88:17] - node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] - node _T_1013 = andr(_T_1012) @[lib.scala 88:36] - node _T_1014 = and(_T_1013, _T_930) @[lib.scala 88:41] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] - node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 88:86] - node _T_1017 = eq(_T_1015, _T_1016) @[lib.scala 88:78] - node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[lib.scala 88:23] - _T_927[12] <= _T_1018 @[lib.scala 88:17] - node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] - node _T_1020 = andr(_T_1019) @[lib.scala 88:36] - node _T_1021 = and(_T_1020, _T_930) @[lib.scala 88:41] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] - node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 88:86] - node _T_1024 = eq(_T_1022, _T_1023) @[lib.scala 88:78] - node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[lib.scala 88:23] - _T_927[13] <= _T_1025 @[lib.scala 88:17] - node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] - node _T_1027 = andr(_T_1026) @[lib.scala 88:36] - node _T_1028 = and(_T_1027, _T_930) @[lib.scala 88:41] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] - node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 88:86] - node _T_1031 = eq(_T_1029, _T_1030) @[lib.scala 88:78] - node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[lib.scala 88:23] - _T_927[14] <= _T_1032 @[lib.scala 88:17] - node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] - node _T_1034 = andr(_T_1033) @[lib.scala 88:36] - node _T_1035 = and(_T_1034, _T_930) @[lib.scala 88:41] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] - node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 88:86] - node _T_1038 = eq(_T_1036, _T_1037) @[lib.scala 88:78] - node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[lib.scala 88:23] - _T_927[15] <= _T_1039 @[lib.scala 88:17] - node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] - node _T_1041 = andr(_T_1040) @[lib.scala 88:36] - node _T_1042 = and(_T_1041, _T_930) @[lib.scala 88:41] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] - node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 88:86] - node _T_1045 = eq(_T_1043, _T_1044) @[lib.scala 88:78] - node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[lib.scala 88:23] - _T_927[16] <= _T_1046 @[lib.scala 88:17] - node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] - node _T_1048 = andr(_T_1047) @[lib.scala 88:36] - node _T_1049 = and(_T_1048, _T_930) @[lib.scala 88:41] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] - node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 88:86] - node _T_1052 = eq(_T_1050, _T_1051) @[lib.scala 88:78] - node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[lib.scala 88:23] - _T_927[17] <= _T_1053 @[lib.scala 88:17] - node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] - node _T_1055 = andr(_T_1054) @[lib.scala 88:36] - node _T_1056 = and(_T_1055, _T_930) @[lib.scala 88:41] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] - node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 88:86] - node _T_1059 = eq(_T_1057, _T_1058) @[lib.scala 88:78] - node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[lib.scala 88:23] - _T_927[18] <= _T_1060 @[lib.scala 88:17] - node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] - node _T_1062 = andr(_T_1061) @[lib.scala 88:36] - node _T_1063 = and(_T_1062, _T_930) @[lib.scala 88:41] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] - node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 88:86] - node _T_1066 = eq(_T_1064, _T_1065) @[lib.scala 88:78] - node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[lib.scala 88:23] - _T_927[19] <= _T_1067 @[lib.scala 88:17] - node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] - node _T_1069 = andr(_T_1068) @[lib.scala 88:36] - node _T_1070 = and(_T_1069, _T_930) @[lib.scala 88:41] - node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] - node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 88:86] - node _T_1073 = eq(_T_1071, _T_1072) @[lib.scala 88:78] - node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[lib.scala 88:23] - _T_927[20] <= _T_1074 @[lib.scala 88:17] - node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] - node _T_1076 = andr(_T_1075) @[lib.scala 88:36] - node _T_1077 = and(_T_1076, _T_930) @[lib.scala 88:41] - node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] - node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 88:86] - node _T_1080 = eq(_T_1078, _T_1079) @[lib.scala 88:78] - node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[lib.scala 88:23] - _T_927[21] <= _T_1081 @[lib.scala 88:17] - node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] - node _T_1083 = andr(_T_1082) @[lib.scala 88:36] - node _T_1084 = and(_T_1083, _T_930) @[lib.scala 88:41] - node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] - node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 88:86] - node _T_1087 = eq(_T_1085, _T_1086) @[lib.scala 88:78] - node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[lib.scala 88:23] - _T_927[22] <= _T_1088 @[lib.scala 88:17] - node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] - node _T_1090 = andr(_T_1089) @[lib.scala 88:36] - node _T_1091 = and(_T_1090, _T_930) @[lib.scala 88:41] - node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] - node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 88:86] - node _T_1094 = eq(_T_1092, _T_1093) @[lib.scala 88:78] - node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[lib.scala 88:23] - _T_927[23] <= _T_1095 @[lib.scala 88:17] - node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] - node _T_1097 = andr(_T_1096) @[lib.scala 88:36] - node _T_1098 = and(_T_1097, _T_930) @[lib.scala 88:41] - node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] - node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 88:86] - node _T_1101 = eq(_T_1099, _T_1100) @[lib.scala 88:78] - node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[lib.scala 88:23] - _T_927[24] <= _T_1102 @[lib.scala 88:17] - node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] - node _T_1104 = andr(_T_1103) @[lib.scala 88:36] - node _T_1105 = and(_T_1104, _T_930) @[lib.scala 88:41] - node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] - node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 88:86] - node _T_1108 = eq(_T_1106, _T_1107) @[lib.scala 88:78] - node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[lib.scala 88:23] - _T_927[25] <= _T_1109 @[lib.scala 88:17] - node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] - node _T_1111 = andr(_T_1110) @[lib.scala 88:36] - node _T_1112 = and(_T_1111, _T_930) @[lib.scala 88:41] - node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] - node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 88:86] - node _T_1115 = eq(_T_1113, _T_1114) @[lib.scala 88:78] - node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[lib.scala 88:23] - _T_927[26] <= _T_1116 @[lib.scala 88:17] - node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] - node _T_1118 = andr(_T_1117) @[lib.scala 88:36] - node _T_1119 = and(_T_1118, _T_930) @[lib.scala 88:41] - node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] - node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 88:86] - node _T_1122 = eq(_T_1120, _T_1121) @[lib.scala 88:78] - node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[lib.scala 88:23] - _T_927[27] <= _T_1123 @[lib.scala 88:17] - node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] - node _T_1125 = andr(_T_1124) @[lib.scala 88:36] - node _T_1126 = and(_T_1125, _T_930) @[lib.scala 88:41] - node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] - node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 88:86] - node _T_1129 = eq(_T_1127, _T_1128) @[lib.scala 88:78] - node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[lib.scala 88:23] - _T_927[28] <= _T_1130 @[lib.scala 88:17] - node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] - node _T_1132 = andr(_T_1131) @[lib.scala 88:36] - node _T_1133 = and(_T_1132, _T_930) @[lib.scala 88:41] - node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] - node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 88:86] - node _T_1136 = eq(_T_1134, _T_1135) @[lib.scala 88:78] - node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[lib.scala 88:23] - _T_927[29] <= _T_1137 @[lib.scala 88:17] - node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] - node _T_1139 = andr(_T_1138) @[lib.scala 88:36] - node _T_1140 = and(_T_1139, _T_930) @[lib.scala 88:41] - node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] - node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 88:86] - node _T_1143 = eq(_T_1141, _T_1142) @[lib.scala 88:78] - node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[lib.scala 88:23] - _T_927[30] <= _T_1144 @[lib.scala 88:17] - node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] - node _T_1146 = andr(_T_1145) @[lib.scala 88:36] - node _T_1147 = and(_T_1146, _T_930) @[lib.scala 88:41] - node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] - node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 88:86] - node _T_1150 = eq(_T_1148, _T_1149) @[lib.scala 88:78] - node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[lib.scala 88:23] - _T_927[31] <= _T_1151 @[lib.scala 88:17] - node _T_1152 = cat(_T_927[1], _T_927[0]) @[lib.scala 89:14] - node _T_1153 = cat(_T_927[3], _T_927[2]) @[lib.scala 89:14] - node _T_1154 = cat(_T_1153, _T_1152) @[lib.scala 89:14] - node _T_1155 = cat(_T_927[5], _T_927[4]) @[lib.scala 89:14] - node _T_1156 = cat(_T_927[7], _T_927[6]) @[lib.scala 89:14] + node _T_406 = andr(_T_405) @[lib.scala 89:25] + node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109] + node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] + node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_410 : UInt<1>[32] @[lib.scala 84:24] + node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] + node _T_412 = not(_T_411) @[lib.scala 85:39] + node _T_413 = and(_T_409, _T_412) @[lib.scala 85:37] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] + node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 86:60] + node _T_416 = eq(_T_414, _T_415) @[lib.scala 86:52] + node _T_417 = or(_T_413, _T_416) @[lib.scala 86:41] + _T_410[0] <= _T_417 @[lib.scala 86:18] + node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] + node _T_419 = andr(_T_418) @[lib.scala 88:36] + node _T_420 = and(_T_419, _T_413) @[lib.scala 88:41] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] + node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 88:86] + node _T_423 = eq(_T_421, _T_422) @[lib.scala 88:78] + node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 88:23] + _T_410[1] <= _T_424 @[lib.scala 88:17] + node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] + node _T_426 = andr(_T_425) @[lib.scala 88:36] + node _T_427 = and(_T_426, _T_413) @[lib.scala 88:41] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] + node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 88:86] + node _T_430 = eq(_T_428, _T_429) @[lib.scala 88:78] + node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 88:23] + _T_410[2] <= _T_431 @[lib.scala 88:17] + node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] + node _T_433 = andr(_T_432) @[lib.scala 88:36] + node _T_434 = and(_T_433, _T_413) @[lib.scala 88:41] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] + node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 88:86] + node _T_437 = eq(_T_435, _T_436) @[lib.scala 88:78] + node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 88:23] + _T_410[3] <= _T_438 @[lib.scala 88:17] + node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] + node _T_440 = andr(_T_439) @[lib.scala 88:36] + node _T_441 = and(_T_440, _T_413) @[lib.scala 88:41] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] + node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 88:86] + node _T_444 = eq(_T_442, _T_443) @[lib.scala 88:78] + node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 88:23] + _T_410[4] <= _T_445 @[lib.scala 88:17] + node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] + node _T_447 = andr(_T_446) @[lib.scala 88:36] + node _T_448 = and(_T_447, _T_413) @[lib.scala 88:41] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] + node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 88:86] + node _T_451 = eq(_T_449, _T_450) @[lib.scala 88:78] + node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 88:23] + _T_410[5] <= _T_452 @[lib.scala 88:17] + node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] + node _T_454 = andr(_T_453) @[lib.scala 88:36] + node _T_455 = and(_T_454, _T_413) @[lib.scala 88:41] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] + node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 88:86] + node _T_458 = eq(_T_456, _T_457) @[lib.scala 88:78] + node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 88:23] + _T_410[6] <= _T_459 @[lib.scala 88:17] + node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] + node _T_461 = andr(_T_460) @[lib.scala 88:36] + node _T_462 = and(_T_461, _T_413) @[lib.scala 88:41] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] + node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 88:86] + node _T_465 = eq(_T_463, _T_464) @[lib.scala 88:78] + node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 88:23] + _T_410[7] <= _T_466 @[lib.scala 88:17] + node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] + node _T_468 = andr(_T_467) @[lib.scala 88:36] + node _T_469 = and(_T_468, _T_413) @[lib.scala 88:41] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] + node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 88:86] + node _T_472 = eq(_T_470, _T_471) @[lib.scala 88:78] + node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 88:23] + _T_410[8] <= _T_473 @[lib.scala 88:17] + node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] + node _T_475 = andr(_T_474) @[lib.scala 88:36] + node _T_476 = and(_T_475, _T_413) @[lib.scala 88:41] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] + node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 88:86] + node _T_479 = eq(_T_477, _T_478) @[lib.scala 88:78] + node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 88:23] + _T_410[9] <= _T_480 @[lib.scala 88:17] + node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] + node _T_482 = andr(_T_481) @[lib.scala 88:36] + node _T_483 = and(_T_482, _T_413) @[lib.scala 88:41] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] + node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 88:86] + node _T_486 = eq(_T_484, _T_485) @[lib.scala 88:78] + node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 88:23] + _T_410[10] <= _T_487 @[lib.scala 88:17] + node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] + node _T_489 = andr(_T_488) @[lib.scala 88:36] + node _T_490 = and(_T_489, _T_413) @[lib.scala 88:41] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] + node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 88:86] + node _T_493 = eq(_T_491, _T_492) @[lib.scala 88:78] + node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 88:23] + _T_410[11] <= _T_494 @[lib.scala 88:17] + node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] + node _T_496 = andr(_T_495) @[lib.scala 88:36] + node _T_497 = and(_T_496, _T_413) @[lib.scala 88:41] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] + node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 88:86] + node _T_500 = eq(_T_498, _T_499) @[lib.scala 88:78] + node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 88:23] + _T_410[12] <= _T_501 @[lib.scala 88:17] + node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] + node _T_503 = andr(_T_502) @[lib.scala 88:36] + node _T_504 = and(_T_503, _T_413) @[lib.scala 88:41] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] + node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 88:86] + node _T_507 = eq(_T_505, _T_506) @[lib.scala 88:78] + node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 88:23] + _T_410[13] <= _T_508 @[lib.scala 88:17] + node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] + node _T_510 = andr(_T_509) @[lib.scala 88:36] + node _T_511 = and(_T_510, _T_413) @[lib.scala 88:41] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] + node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 88:86] + node _T_514 = eq(_T_512, _T_513) @[lib.scala 88:78] + node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 88:23] + _T_410[14] <= _T_515 @[lib.scala 88:17] + node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] + node _T_517 = andr(_T_516) @[lib.scala 88:36] + node _T_518 = and(_T_517, _T_413) @[lib.scala 88:41] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] + node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 88:86] + node _T_521 = eq(_T_519, _T_520) @[lib.scala 88:78] + node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 88:23] + _T_410[15] <= _T_522 @[lib.scala 88:17] + node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] + node _T_524 = andr(_T_523) @[lib.scala 88:36] + node _T_525 = and(_T_524, _T_413) @[lib.scala 88:41] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] + node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 88:86] + node _T_528 = eq(_T_526, _T_527) @[lib.scala 88:78] + node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 88:23] + _T_410[16] <= _T_529 @[lib.scala 88:17] + node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] + node _T_531 = andr(_T_530) @[lib.scala 88:36] + node _T_532 = and(_T_531, _T_413) @[lib.scala 88:41] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] + node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 88:86] + node _T_535 = eq(_T_533, _T_534) @[lib.scala 88:78] + node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 88:23] + _T_410[17] <= _T_536 @[lib.scala 88:17] + node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] + node _T_538 = andr(_T_537) @[lib.scala 88:36] + node _T_539 = and(_T_538, _T_413) @[lib.scala 88:41] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] + node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 88:86] + node _T_542 = eq(_T_540, _T_541) @[lib.scala 88:78] + node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 88:23] + _T_410[18] <= _T_543 @[lib.scala 88:17] + node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] + node _T_545 = andr(_T_544) @[lib.scala 88:36] + node _T_546 = and(_T_545, _T_413) @[lib.scala 88:41] + node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] + node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 88:86] + node _T_549 = eq(_T_547, _T_548) @[lib.scala 88:78] + node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 88:23] + _T_410[19] <= _T_550 @[lib.scala 88:17] + node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] + node _T_552 = andr(_T_551) @[lib.scala 88:36] + node _T_553 = and(_T_552, _T_413) @[lib.scala 88:41] + node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] + node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 88:86] + node _T_556 = eq(_T_554, _T_555) @[lib.scala 88:78] + node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 88:23] + _T_410[20] <= _T_557 @[lib.scala 88:17] + node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] + node _T_559 = andr(_T_558) @[lib.scala 88:36] + node _T_560 = and(_T_559, _T_413) @[lib.scala 88:41] + node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] + node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 88:86] + node _T_563 = eq(_T_561, _T_562) @[lib.scala 88:78] + node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 88:23] + _T_410[21] <= _T_564 @[lib.scala 88:17] + node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] + node _T_566 = andr(_T_565) @[lib.scala 88:36] + node _T_567 = and(_T_566, _T_413) @[lib.scala 88:41] + node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] + node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 88:86] + node _T_570 = eq(_T_568, _T_569) @[lib.scala 88:78] + node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 88:23] + _T_410[22] <= _T_571 @[lib.scala 88:17] + node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] + node _T_573 = andr(_T_572) @[lib.scala 88:36] + node _T_574 = and(_T_573, _T_413) @[lib.scala 88:41] + node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] + node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 88:86] + node _T_577 = eq(_T_575, _T_576) @[lib.scala 88:78] + node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 88:23] + _T_410[23] <= _T_578 @[lib.scala 88:17] + node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] + node _T_580 = andr(_T_579) @[lib.scala 88:36] + node _T_581 = and(_T_580, _T_413) @[lib.scala 88:41] + node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] + node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 88:86] + node _T_584 = eq(_T_582, _T_583) @[lib.scala 88:78] + node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 88:23] + _T_410[24] <= _T_585 @[lib.scala 88:17] + node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] + node _T_587 = andr(_T_586) @[lib.scala 88:36] + node _T_588 = and(_T_587, _T_413) @[lib.scala 88:41] + node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] + node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 88:86] + node _T_591 = eq(_T_589, _T_590) @[lib.scala 88:78] + node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 88:23] + _T_410[25] <= _T_592 @[lib.scala 88:17] + node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] + node _T_594 = andr(_T_593) @[lib.scala 88:36] + node _T_595 = and(_T_594, _T_413) @[lib.scala 88:41] + node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] + node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 88:86] + node _T_598 = eq(_T_596, _T_597) @[lib.scala 88:78] + node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 88:23] + _T_410[26] <= _T_599 @[lib.scala 88:17] + node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] + node _T_601 = andr(_T_600) @[lib.scala 88:36] + node _T_602 = and(_T_601, _T_413) @[lib.scala 88:41] + node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] + node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 88:86] + node _T_605 = eq(_T_603, _T_604) @[lib.scala 88:78] + node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 88:23] + _T_410[27] <= _T_606 @[lib.scala 88:17] + node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] + node _T_608 = andr(_T_607) @[lib.scala 88:36] + node _T_609 = and(_T_608, _T_413) @[lib.scala 88:41] + node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] + node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 88:86] + node _T_612 = eq(_T_610, _T_611) @[lib.scala 88:78] + node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 88:23] + _T_410[28] <= _T_613 @[lib.scala 88:17] + node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] + node _T_615 = andr(_T_614) @[lib.scala 88:36] + node _T_616 = and(_T_615, _T_413) @[lib.scala 88:41] + node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] + node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 88:86] + node _T_619 = eq(_T_617, _T_618) @[lib.scala 88:78] + node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 88:23] + _T_410[29] <= _T_620 @[lib.scala 88:17] + node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] + node _T_622 = andr(_T_621) @[lib.scala 88:36] + node _T_623 = and(_T_622, _T_413) @[lib.scala 88:41] + node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] + node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 88:86] + node _T_626 = eq(_T_624, _T_625) @[lib.scala 88:78] + node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 88:23] + _T_410[30] <= _T_627 @[lib.scala 88:17] + node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] + node _T_629 = andr(_T_628) @[lib.scala 88:36] + node _T_630 = and(_T_629, _T_413) @[lib.scala 88:41] + node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] + node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 88:86] + node _T_633 = eq(_T_631, _T_632) @[lib.scala 88:78] + node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 88:23] + _T_410[31] <= _T_634 @[lib.scala 88:17] + node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 89:14] + node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 89:14] + node _T_637 = cat(_T_636, _T_635) @[lib.scala 89:14] + node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 89:14] + node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 89:14] + node _T_640 = cat(_T_639, _T_638) @[lib.scala 89:14] + node _T_641 = cat(_T_640, _T_637) @[lib.scala 89:14] + node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 89:14] + node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 89:14] + node _T_644 = cat(_T_643, _T_642) @[lib.scala 89:14] + node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 89:14] + node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 89:14] + node _T_647 = cat(_T_646, _T_645) @[lib.scala 89:14] + node _T_648 = cat(_T_647, _T_644) @[lib.scala 89:14] + node _T_649 = cat(_T_648, _T_641) @[lib.scala 89:14] + node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 89:14] + node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 89:14] + node _T_652 = cat(_T_651, _T_650) @[lib.scala 89:14] + node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 89:14] + node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 89:14] + node _T_655 = cat(_T_654, _T_653) @[lib.scala 89:14] + node _T_656 = cat(_T_655, _T_652) @[lib.scala 89:14] + node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 89:14] + node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 89:14] + node _T_659 = cat(_T_658, _T_657) @[lib.scala 89:14] + node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 89:14] + node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 89:14] + node _T_662 = cat(_T_661, _T_660) @[lib.scala 89:14] + node _T_663 = cat(_T_662, _T_659) @[lib.scala 89:14] + node _T_664 = cat(_T_663, _T_656) @[lib.scala 89:14] + node _T_665 = cat(_T_664, _T_649) @[lib.scala 89:14] + node _T_666 = andr(_T_665) @[lib.scala 89:25] + node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109] + node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] + node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_670 : UInt<1>[32] @[lib.scala 84:24] + node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] + node _T_672 = not(_T_671) @[lib.scala 85:39] + node _T_673 = and(_T_669, _T_672) @[lib.scala 85:37] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] + node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 86:60] + node _T_676 = eq(_T_674, _T_675) @[lib.scala 86:52] + node _T_677 = or(_T_673, _T_676) @[lib.scala 86:41] + _T_670[0] <= _T_677 @[lib.scala 86:18] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] + node _T_679 = andr(_T_678) @[lib.scala 88:36] + node _T_680 = and(_T_679, _T_673) @[lib.scala 88:41] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] + node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 88:86] + node _T_683 = eq(_T_681, _T_682) @[lib.scala 88:78] + node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 88:23] + _T_670[1] <= _T_684 @[lib.scala 88:17] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] + node _T_686 = andr(_T_685) @[lib.scala 88:36] + node _T_687 = and(_T_686, _T_673) @[lib.scala 88:41] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] + node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 88:86] + node _T_690 = eq(_T_688, _T_689) @[lib.scala 88:78] + node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 88:23] + _T_670[2] <= _T_691 @[lib.scala 88:17] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] + node _T_693 = andr(_T_692) @[lib.scala 88:36] + node _T_694 = and(_T_693, _T_673) @[lib.scala 88:41] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] + node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 88:86] + node _T_697 = eq(_T_695, _T_696) @[lib.scala 88:78] + node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 88:23] + _T_670[3] <= _T_698 @[lib.scala 88:17] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] + node _T_700 = andr(_T_699) @[lib.scala 88:36] + node _T_701 = and(_T_700, _T_673) @[lib.scala 88:41] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] + node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 88:86] + node _T_704 = eq(_T_702, _T_703) @[lib.scala 88:78] + node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 88:23] + _T_670[4] <= _T_705 @[lib.scala 88:17] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] + node _T_707 = andr(_T_706) @[lib.scala 88:36] + node _T_708 = and(_T_707, _T_673) @[lib.scala 88:41] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] + node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 88:86] + node _T_711 = eq(_T_709, _T_710) @[lib.scala 88:78] + node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 88:23] + _T_670[5] <= _T_712 @[lib.scala 88:17] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] + node _T_714 = andr(_T_713) @[lib.scala 88:36] + node _T_715 = and(_T_714, _T_673) @[lib.scala 88:41] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] + node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 88:86] + node _T_718 = eq(_T_716, _T_717) @[lib.scala 88:78] + node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 88:23] + _T_670[6] <= _T_719 @[lib.scala 88:17] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] + node _T_721 = andr(_T_720) @[lib.scala 88:36] + node _T_722 = and(_T_721, _T_673) @[lib.scala 88:41] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] + node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 88:86] + node _T_725 = eq(_T_723, _T_724) @[lib.scala 88:78] + node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 88:23] + _T_670[7] <= _T_726 @[lib.scala 88:17] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] + node _T_728 = andr(_T_727) @[lib.scala 88:36] + node _T_729 = and(_T_728, _T_673) @[lib.scala 88:41] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] + node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 88:86] + node _T_732 = eq(_T_730, _T_731) @[lib.scala 88:78] + node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 88:23] + _T_670[8] <= _T_733 @[lib.scala 88:17] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] + node _T_735 = andr(_T_734) @[lib.scala 88:36] + node _T_736 = and(_T_735, _T_673) @[lib.scala 88:41] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] + node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 88:86] + node _T_739 = eq(_T_737, _T_738) @[lib.scala 88:78] + node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 88:23] + _T_670[9] <= _T_740 @[lib.scala 88:17] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] + node _T_742 = andr(_T_741) @[lib.scala 88:36] + node _T_743 = and(_T_742, _T_673) @[lib.scala 88:41] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] + node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 88:86] + node _T_746 = eq(_T_744, _T_745) @[lib.scala 88:78] + node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 88:23] + _T_670[10] <= _T_747 @[lib.scala 88:17] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] + node _T_749 = andr(_T_748) @[lib.scala 88:36] + node _T_750 = and(_T_749, _T_673) @[lib.scala 88:41] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] + node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 88:86] + node _T_753 = eq(_T_751, _T_752) @[lib.scala 88:78] + node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 88:23] + _T_670[11] <= _T_754 @[lib.scala 88:17] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] + node _T_756 = andr(_T_755) @[lib.scala 88:36] + node _T_757 = and(_T_756, _T_673) @[lib.scala 88:41] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] + node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 88:86] + node _T_760 = eq(_T_758, _T_759) @[lib.scala 88:78] + node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 88:23] + _T_670[12] <= _T_761 @[lib.scala 88:17] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] + node _T_763 = andr(_T_762) @[lib.scala 88:36] + node _T_764 = and(_T_763, _T_673) @[lib.scala 88:41] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] + node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 88:86] + node _T_767 = eq(_T_765, _T_766) @[lib.scala 88:78] + node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 88:23] + _T_670[13] <= _T_768 @[lib.scala 88:17] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] + node _T_770 = andr(_T_769) @[lib.scala 88:36] + node _T_771 = and(_T_770, _T_673) @[lib.scala 88:41] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] + node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 88:86] + node _T_774 = eq(_T_772, _T_773) @[lib.scala 88:78] + node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 88:23] + _T_670[14] <= _T_775 @[lib.scala 88:17] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] + node _T_777 = andr(_T_776) @[lib.scala 88:36] + node _T_778 = and(_T_777, _T_673) @[lib.scala 88:41] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] + node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 88:86] + node _T_781 = eq(_T_779, _T_780) @[lib.scala 88:78] + node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 88:23] + _T_670[15] <= _T_782 @[lib.scala 88:17] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] + node _T_784 = andr(_T_783) @[lib.scala 88:36] + node _T_785 = and(_T_784, _T_673) @[lib.scala 88:41] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] + node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 88:86] + node _T_788 = eq(_T_786, _T_787) @[lib.scala 88:78] + node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 88:23] + _T_670[16] <= _T_789 @[lib.scala 88:17] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] + node _T_791 = andr(_T_790) @[lib.scala 88:36] + node _T_792 = and(_T_791, _T_673) @[lib.scala 88:41] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] + node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 88:86] + node _T_795 = eq(_T_793, _T_794) @[lib.scala 88:78] + node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 88:23] + _T_670[17] <= _T_796 @[lib.scala 88:17] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] + node _T_798 = andr(_T_797) @[lib.scala 88:36] + node _T_799 = and(_T_798, _T_673) @[lib.scala 88:41] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] + node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 88:86] + node _T_802 = eq(_T_800, _T_801) @[lib.scala 88:78] + node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 88:23] + _T_670[18] <= _T_803 @[lib.scala 88:17] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] + node _T_805 = andr(_T_804) @[lib.scala 88:36] + node _T_806 = and(_T_805, _T_673) @[lib.scala 88:41] + node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] + node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 88:86] + node _T_809 = eq(_T_807, _T_808) @[lib.scala 88:78] + node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 88:23] + _T_670[19] <= _T_810 @[lib.scala 88:17] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] + node _T_812 = andr(_T_811) @[lib.scala 88:36] + node _T_813 = and(_T_812, _T_673) @[lib.scala 88:41] + node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] + node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 88:86] + node _T_816 = eq(_T_814, _T_815) @[lib.scala 88:78] + node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 88:23] + _T_670[20] <= _T_817 @[lib.scala 88:17] + node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] + node _T_819 = andr(_T_818) @[lib.scala 88:36] + node _T_820 = and(_T_819, _T_673) @[lib.scala 88:41] + node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] + node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 88:86] + node _T_823 = eq(_T_821, _T_822) @[lib.scala 88:78] + node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 88:23] + _T_670[21] <= _T_824 @[lib.scala 88:17] + node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] + node _T_826 = andr(_T_825) @[lib.scala 88:36] + node _T_827 = and(_T_826, _T_673) @[lib.scala 88:41] + node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] + node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 88:86] + node _T_830 = eq(_T_828, _T_829) @[lib.scala 88:78] + node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 88:23] + _T_670[22] <= _T_831 @[lib.scala 88:17] + node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] + node _T_833 = andr(_T_832) @[lib.scala 88:36] + node _T_834 = and(_T_833, _T_673) @[lib.scala 88:41] + node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] + node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 88:86] + node _T_837 = eq(_T_835, _T_836) @[lib.scala 88:78] + node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 88:23] + _T_670[23] <= _T_838 @[lib.scala 88:17] + node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] + node _T_840 = andr(_T_839) @[lib.scala 88:36] + node _T_841 = and(_T_840, _T_673) @[lib.scala 88:41] + node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] + node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 88:86] + node _T_844 = eq(_T_842, _T_843) @[lib.scala 88:78] + node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 88:23] + _T_670[24] <= _T_845 @[lib.scala 88:17] + node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] + node _T_847 = andr(_T_846) @[lib.scala 88:36] + node _T_848 = and(_T_847, _T_673) @[lib.scala 88:41] + node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] + node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 88:86] + node _T_851 = eq(_T_849, _T_850) @[lib.scala 88:78] + node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 88:23] + _T_670[25] <= _T_852 @[lib.scala 88:17] + node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] + node _T_854 = andr(_T_853) @[lib.scala 88:36] + node _T_855 = and(_T_854, _T_673) @[lib.scala 88:41] + node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] + node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 88:86] + node _T_858 = eq(_T_856, _T_857) @[lib.scala 88:78] + node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 88:23] + _T_670[26] <= _T_859 @[lib.scala 88:17] + node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] + node _T_861 = andr(_T_860) @[lib.scala 88:36] + node _T_862 = and(_T_861, _T_673) @[lib.scala 88:41] + node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] + node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 88:86] + node _T_865 = eq(_T_863, _T_864) @[lib.scala 88:78] + node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 88:23] + _T_670[27] <= _T_866 @[lib.scala 88:17] + node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] + node _T_868 = andr(_T_867) @[lib.scala 88:36] + node _T_869 = and(_T_868, _T_673) @[lib.scala 88:41] + node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] + node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 88:86] + node _T_872 = eq(_T_870, _T_871) @[lib.scala 88:78] + node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 88:23] + _T_670[28] <= _T_873 @[lib.scala 88:17] + node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] + node _T_875 = andr(_T_874) @[lib.scala 88:36] + node _T_876 = and(_T_875, _T_673) @[lib.scala 88:41] + node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] + node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 88:86] + node _T_879 = eq(_T_877, _T_878) @[lib.scala 88:78] + node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 88:23] + _T_670[29] <= _T_880 @[lib.scala 88:17] + node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] + node _T_882 = andr(_T_881) @[lib.scala 88:36] + node _T_883 = and(_T_882, _T_673) @[lib.scala 88:41] + node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] + node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 88:86] + node _T_886 = eq(_T_884, _T_885) @[lib.scala 88:78] + node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 88:23] + _T_670[30] <= _T_887 @[lib.scala 88:17] + node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] + node _T_889 = andr(_T_888) @[lib.scala 88:36] + node _T_890 = and(_T_889, _T_673) @[lib.scala 88:41] + node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] + node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 88:86] + node _T_893 = eq(_T_891, _T_892) @[lib.scala 88:78] + node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 88:23] + _T_670[31] <= _T_894 @[lib.scala 88:17] + node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 89:14] + node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 89:14] + node _T_897 = cat(_T_896, _T_895) @[lib.scala 89:14] + node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 89:14] + node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 89:14] + node _T_900 = cat(_T_899, _T_898) @[lib.scala 89:14] + node _T_901 = cat(_T_900, _T_897) @[lib.scala 89:14] + node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 89:14] + node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 89:14] + node _T_904 = cat(_T_903, _T_902) @[lib.scala 89:14] + node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 89:14] + node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 89:14] + node _T_907 = cat(_T_906, _T_905) @[lib.scala 89:14] + node _T_908 = cat(_T_907, _T_904) @[lib.scala 89:14] + node _T_909 = cat(_T_908, _T_901) @[lib.scala 89:14] + node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 89:14] + node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 89:14] + node _T_912 = cat(_T_911, _T_910) @[lib.scala 89:14] + node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 89:14] + node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 89:14] + node _T_915 = cat(_T_914, _T_913) @[lib.scala 89:14] + node _T_916 = cat(_T_915, _T_912) @[lib.scala 89:14] + node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 89:14] + node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 89:14] + node _T_919 = cat(_T_918, _T_917) @[lib.scala 89:14] + node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 89:14] + node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 89:14] + node _T_922 = cat(_T_921, _T_920) @[lib.scala 89:14] + node _T_923 = cat(_T_922, _T_919) @[lib.scala 89:14] + node _T_924 = cat(_T_923, _T_916) @[lib.scala 89:14] + node _T_925 = cat(_T_924, _T_909) @[lib.scala 89:14] + node _T_926 = andr(_T_925) @[lib.scala 89:25] + node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109] + node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] + node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_930 : UInt<1>[32] @[lib.scala 84:24] + node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] + node _T_932 = not(_T_931) @[lib.scala 85:39] + node _T_933 = and(_T_929, _T_932) @[lib.scala 85:37] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] + node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 86:60] + node _T_936 = eq(_T_934, _T_935) @[lib.scala 86:52] + node _T_937 = or(_T_933, _T_936) @[lib.scala 86:41] + _T_930[0] <= _T_937 @[lib.scala 86:18] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] + node _T_939 = andr(_T_938) @[lib.scala 88:36] + node _T_940 = and(_T_939, _T_933) @[lib.scala 88:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] + node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 88:86] + node _T_943 = eq(_T_941, _T_942) @[lib.scala 88:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 88:23] + _T_930[1] <= _T_944 @[lib.scala 88:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] + node _T_946 = andr(_T_945) @[lib.scala 88:36] + node _T_947 = and(_T_946, _T_933) @[lib.scala 88:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] + node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 88:86] + node _T_950 = eq(_T_948, _T_949) @[lib.scala 88:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 88:23] + _T_930[2] <= _T_951 @[lib.scala 88:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] + node _T_953 = andr(_T_952) @[lib.scala 88:36] + node _T_954 = and(_T_953, _T_933) @[lib.scala 88:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] + node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 88:86] + node _T_957 = eq(_T_955, _T_956) @[lib.scala 88:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 88:23] + _T_930[3] <= _T_958 @[lib.scala 88:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] + node _T_960 = andr(_T_959) @[lib.scala 88:36] + node _T_961 = and(_T_960, _T_933) @[lib.scala 88:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] + node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 88:86] + node _T_964 = eq(_T_962, _T_963) @[lib.scala 88:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 88:23] + _T_930[4] <= _T_965 @[lib.scala 88:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] + node _T_967 = andr(_T_966) @[lib.scala 88:36] + node _T_968 = and(_T_967, _T_933) @[lib.scala 88:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] + node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 88:86] + node _T_971 = eq(_T_969, _T_970) @[lib.scala 88:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 88:23] + _T_930[5] <= _T_972 @[lib.scala 88:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] + node _T_974 = andr(_T_973) @[lib.scala 88:36] + node _T_975 = and(_T_974, _T_933) @[lib.scala 88:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] + node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 88:86] + node _T_978 = eq(_T_976, _T_977) @[lib.scala 88:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 88:23] + _T_930[6] <= _T_979 @[lib.scala 88:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] + node _T_981 = andr(_T_980) @[lib.scala 88:36] + node _T_982 = and(_T_981, _T_933) @[lib.scala 88:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] + node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 88:86] + node _T_985 = eq(_T_983, _T_984) @[lib.scala 88:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 88:23] + _T_930[7] <= _T_986 @[lib.scala 88:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] + node _T_988 = andr(_T_987) @[lib.scala 88:36] + node _T_989 = and(_T_988, _T_933) @[lib.scala 88:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] + node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 88:86] + node _T_992 = eq(_T_990, _T_991) @[lib.scala 88:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 88:23] + _T_930[8] <= _T_993 @[lib.scala 88:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] + node _T_995 = andr(_T_994) @[lib.scala 88:36] + node _T_996 = and(_T_995, _T_933) @[lib.scala 88:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] + node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 88:86] + node _T_999 = eq(_T_997, _T_998) @[lib.scala 88:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 88:23] + _T_930[9] <= _T_1000 @[lib.scala 88:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] + node _T_1002 = andr(_T_1001) @[lib.scala 88:36] + node _T_1003 = and(_T_1002, _T_933) @[lib.scala 88:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] + node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 88:86] + node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 88:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 88:23] + _T_930[10] <= _T_1007 @[lib.scala 88:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] + node _T_1009 = andr(_T_1008) @[lib.scala 88:36] + node _T_1010 = and(_T_1009, _T_933) @[lib.scala 88:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] + node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 88:86] + node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 88:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 88:23] + _T_930[11] <= _T_1014 @[lib.scala 88:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] + node _T_1016 = andr(_T_1015) @[lib.scala 88:36] + node _T_1017 = and(_T_1016, _T_933) @[lib.scala 88:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] + node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 88:86] + node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 88:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 88:23] + _T_930[12] <= _T_1021 @[lib.scala 88:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] + node _T_1023 = andr(_T_1022) @[lib.scala 88:36] + node _T_1024 = and(_T_1023, _T_933) @[lib.scala 88:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] + node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 88:86] + node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 88:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 88:23] + _T_930[13] <= _T_1028 @[lib.scala 88:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] + node _T_1030 = andr(_T_1029) @[lib.scala 88:36] + node _T_1031 = and(_T_1030, _T_933) @[lib.scala 88:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] + node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 88:86] + node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 88:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 88:23] + _T_930[14] <= _T_1035 @[lib.scala 88:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] + node _T_1037 = andr(_T_1036) @[lib.scala 88:36] + node _T_1038 = and(_T_1037, _T_933) @[lib.scala 88:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] + node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 88:86] + node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 88:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 88:23] + _T_930[15] <= _T_1042 @[lib.scala 88:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] + node _T_1044 = andr(_T_1043) @[lib.scala 88:36] + node _T_1045 = and(_T_1044, _T_933) @[lib.scala 88:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] + node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 88:86] + node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 88:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 88:23] + _T_930[16] <= _T_1049 @[lib.scala 88:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] + node _T_1051 = andr(_T_1050) @[lib.scala 88:36] + node _T_1052 = and(_T_1051, _T_933) @[lib.scala 88:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] + node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 88:86] + node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 88:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 88:23] + _T_930[17] <= _T_1056 @[lib.scala 88:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] + node _T_1058 = andr(_T_1057) @[lib.scala 88:36] + node _T_1059 = and(_T_1058, _T_933) @[lib.scala 88:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] + node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 88:86] + node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 88:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 88:23] + _T_930[18] <= _T_1063 @[lib.scala 88:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] + node _T_1065 = andr(_T_1064) @[lib.scala 88:36] + node _T_1066 = and(_T_1065, _T_933) @[lib.scala 88:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] + node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 88:86] + node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 88:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 88:23] + _T_930[19] <= _T_1070 @[lib.scala 88:17] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] + node _T_1072 = andr(_T_1071) @[lib.scala 88:36] + node _T_1073 = and(_T_1072, _T_933) @[lib.scala 88:41] + node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] + node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 88:86] + node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 88:78] + node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 88:23] + _T_930[20] <= _T_1077 @[lib.scala 88:17] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] + node _T_1079 = andr(_T_1078) @[lib.scala 88:36] + node _T_1080 = and(_T_1079, _T_933) @[lib.scala 88:41] + node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] + node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 88:86] + node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 88:78] + node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 88:23] + _T_930[21] <= _T_1084 @[lib.scala 88:17] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] + node _T_1086 = andr(_T_1085) @[lib.scala 88:36] + node _T_1087 = and(_T_1086, _T_933) @[lib.scala 88:41] + node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] + node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 88:86] + node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 88:78] + node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 88:23] + _T_930[22] <= _T_1091 @[lib.scala 88:17] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] + node _T_1093 = andr(_T_1092) @[lib.scala 88:36] + node _T_1094 = and(_T_1093, _T_933) @[lib.scala 88:41] + node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] + node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 88:86] + node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 88:78] + node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 88:23] + _T_930[23] <= _T_1098 @[lib.scala 88:17] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] + node _T_1100 = andr(_T_1099) @[lib.scala 88:36] + node _T_1101 = and(_T_1100, _T_933) @[lib.scala 88:41] + node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] + node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 88:86] + node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 88:78] + node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 88:23] + _T_930[24] <= _T_1105 @[lib.scala 88:17] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] + node _T_1107 = andr(_T_1106) @[lib.scala 88:36] + node _T_1108 = and(_T_1107, _T_933) @[lib.scala 88:41] + node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] + node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 88:86] + node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 88:78] + node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 88:23] + _T_930[25] <= _T_1112 @[lib.scala 88:17] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] + node _T_1114 = andr(_T_1113) @[lib.scala 88:36] + node _T_1115 = and(_T_1114, _T_933) @[lib.scala 88:41] + node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] + node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 88:86] + node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 88:78] + node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 88:23] + _T_930[26] <= _T_1119 @[lib.scala 88:17] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] + node _T_1121 = andr(_T_1120) @[lib.scala 88:36] + node _T_1122 = and(_T_1121, _T_933) @[lib.scala 88:41] + node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] + node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 88:86] + node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 88:78] + node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 88:23] + _T_930[27] <= _T_1126 @[lib.scala 88:17] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] + node _T_1128 = andr(_T_1127) @[lib.scala 88:36] + node _T_1129 = and(_T_1128, _T_933) @[lib.scala 88:41] + node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] + node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 88:86] + node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 88:78] + node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 88:23] + _T_930[28] <= _T_1133 @[lib.scala 88:17] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] + node _T_1135 = andr(_T_1134) @[lib.scala 88:36] + node _T_1136 = and(_T_1135, _T_933) @[lib.scala 88:41] + node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] + node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 88:86] + node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 88:78] + node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 88:23] + _T_930[29] <= _T_1140 @[lib.scala 88:17] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] + node _T_1142 = andr(_T_1141) @[lib.scala 88:36] + node _T_1143 = and(_T_1142, _T_933) @[lib.scala 88:41] + node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] + node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 88:86] + node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 88:78] + node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 88:23] + _T_930[30] <= _T_1147 @[lib.scala 88:17] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] + node _T_1149 = andr(_T_1148) @[lib.scala 88:36] + node _T_1150 = and(_T_1149, _T_933) @[lib.scala 88:41] + node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] + node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 88:86] + node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 88:78] + node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 88:23] + _T_930[31] <= _T_1154 @[lib.scala 88:17] + node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 89:14] + node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 89:14] node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 89:14] - node _T_1158 = cat(_T_1157, _T_1154) @[lib.scala 89:14] - node _T_1159 = cat(_T_927[9], _T_927[8]) @[lib.scala 89:14] - node _T_1160 = cat(_T_927[11], _T_927[10]) @[lib.scala 89:14] - node _T_1161 = cat(_T_1160, _T_1159) @[lib.scala 89:14] - node _T_1162 = cat(_T_927[13], _T_927[12]) @[lib.scala 89:14] - node _T_1163 = cat(_T_927[15], _T_927[14]) @[lib.scala 89:14] + node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 89:14] + node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 89:14] + node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 89:14] + node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 89:14] + node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 89:14] + node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 89:14] node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 89:14] - node _T_1165 = cat(_T_1164, _T_1161) @[lib.scala 89:14] - node _T_1166 = cat(_T_1165, _T_1158) @[lib.scala 89:14] - node _T_1167 = cat(_T_927[17], _T_927[16]) @[lib.scala 89:14] - node _T_1168 = cat(_T_927[19], _T_927[18]) @[lib.scala 89:14] - node _T_1169 = cat(_T_1168, _T_1167) @[lib.scala 89:14] - node _T_1170 = cat(_T_927[21], _T_927[20]) @[lib.scala 89:14] - node _T_1171 = cat(_T_927[23], _T_927[22]) @[lib.scala 89:14] + node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 89:14] + node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 89:14] + node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 89:14] + node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 89:14] + node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 89:14] + node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 89:14] + node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 89:14] node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 89:14] - node _T_1173 = cat(_T_1172, _T_1169) @[lib.scala 89:14] - node _T_1174 = cat(_T_927[25], _T_927[24]) @[lib.scala 89:14] - node _T_1175 = cat(_T_927[27], _T_927[26]) @[lib.scala 89:14] - node _T_1176 = cat(_T_1175, _T_1174) @[lib.scala 89:14] - node _T_1177 = cat(_T_927[29], _T_927[28]) @[lib.scala 89:14] - node _T_1178 = cat(_T_927[31], _T_927[30]) @[lib.scala 89:14] + node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 89:14] + node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 89:14] + node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 89:14] + node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 89:14] + node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 89:14] + node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 89:14] node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 89:14] - node _T_1180 = cat(_T_1179, _T_1176) @[lib.scala 89:14] - node _T_1181 = cat(_T_1180, _T_1173) @[lib.scala 89:14] - node _T_1182 = cat(_T_1181, _T_1166) @[lib.scala 89:14] - node _T_1183 = and(_T_925, _T_1182) @[dec_trigger.scala 15:109] - node _T_1184 = cat(_T_1183, _T_924) @[Cat.scala 29:58] - node _T_1185 = cat(_T_1184, _T_665) @[Cat.scala 29:58] - node _T_1186 = cat(_T_1185, _T_406) @[Cat.scala 29:58] - io.dec_i0_trigger_match_d <= _T_1186 @[dec_trigger.scala 15:29] + node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 89:14] + node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 89:14] + node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 89:14] + node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 89:14] + node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 89:14] + node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 89:14] + node _T_1186 = andr(_T_1185) @[lib.scala 89:25] + node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109] + node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58] + node _T_1190 = cat(_T_1189, _T_407) @[Cat.scala 29:58] + io.dec_i0_trigger_match_d <= _T_1190 @[dec_trigger.scala 15:29] module dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -81793,7 +81797,7 @@ circuit quasar_wrapper : module dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") @@ -93283,905 +93287,909 @@ circuit quasar_wrapper : node _T_301 = cat(_T_300, _T_297) @[lib.scala 89:14] node _T_302 = cat(_T_301, _T_294) @[lib.scala 89:14] node _T_303 = cat(_T_302, _T_287) @[lib.scala 89:14] - node _T_304 = and(_T_46, _T_303) @[lsu_trigger.scala 19:92] - node _T_305 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_306 = and(io.lsu_pkt_m.valid, _T_305) @[lsu_trigger.scala 18:69] - node _T_307 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_308 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_309 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_310 = and(_T_308, _T_309) @[lsu_trigger.scala 19:58] - node _T_311 = or(_T_307, _T_310) @[lsu_trigger.scala 18:152] - node _T_312 = and(_T_306, _T_311) @[lsu_trigger.scala 18:94] - node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_314 : UInt<1>[32] @[lib.scala 84:24] - node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] - node _T_316 = not(_T_315) @[lib.scala 85:39] - node _T_317 = and(_T_313, _T_316) @[lib.scala 85:37] - node _T_318 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] - node _T_319 = bits(lsu_match_data_1, 0, 0) @[lib.scala 86:60] - node _T_320 = eq(_T_318, _T_319) @[lib.scala 86:52] - node _T_321 = or(_T_317, _T_320) @[lib.scala 86:41] - _T_314[0] <= _T_321 @[lib.scala 86:18] - node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] - node _T_323 = andr(_T_322) @[lib.scala 88:36] - node _T_324 = and(_T_323, _T_317) @[lib.scala 88:41] - node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] - node _T_326 = bits(lsu_match_data_1, 1, 1) @[lib.scala 88:86] - node _T_327 = eq(_T_325, _T_326) @[lib.scala 88:78] - node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[lib.scala 88:23] - _T_314[1] <= _T_328 @[lib.scala 88:17] - node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] - node _T_330 = andr(_T_329) @[lib.scala 88:36] - node _T_331 = and(_T_330, _T_317) @[lib.scala 88:41] - node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] - node _T_333 = bits(lsu_match_data_1, 2, 2) @[lib.scala 88:86] - node _T_334 = eq(_T_332, _T_333) @[lib.scala 88:78] - node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[lib.scala 88:23] - _T_314[2] <= _T_335 @[lib.scala 88:17] - node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] - node _T_337 = andr(_T_336) @[lib.scala 88:36] - node _T_338 = and(_T_337, _T_317) @[lib.scala 88:41] - node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] - node _T_340 = bits(lsu_match_data_1, 3, 3) @[lib.scala 88:86] - node _T_341 = eq(_T_339, _T_340) @[lib.scala 88:78] - node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[lib.scala 88:23] - _T_314[3] <= _T_342 @[lib.scala 88:17] - node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] - node _T_344 = andr(_T_343) @[lib.scala 88:36] - node _T_345 = and(_T_344, _T_317) @[lib.scala 88:41] - node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] - node _T_347 = bits(lsu_match_data_1, 4, 4) @[lib.scala 88:86] - node _T_348 = eq(_T_346, _T_347) @[lib.scala 88:78] - node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[lib.scala 88:23] - _T_314[4] <= _T_349 @[lib.scala 88:17] - node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] - node _T_351 = andr(_T_350) @[lib.scala 88:36] - node _T_352 = and(_T_351, _T_317) @[lib.scala 88:41] - node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] - node _T_354 = bits(lsu_match_data_1, 5, 5) @[lib.scala 88:86] - node _T_355 = eq(_T_353, _T_354) @[lib.scala 88:78] - node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[lib.scala 88:23] - _T_314[5] <= _T_356 @[lib.scala 88:17] - node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] - node _T_358 = andr(_T_357) @[lib.scala 88:36] - node _T_359 = and(_T_358, _T_317) @[lib.scala 88:41] - node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] - node _T_361 = bits(lsu_match_data_1, 6, 6) @[lib.scala 88:86] - node _T_362 = eq(_T_360, _T_361) @[lib.scala 88:78] - node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[lib.scala 88:23] - _T_314[6] <= _T_363 @[lib.scala 88:17] - node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] - node _T_365 = andr(_T_364) @[lib.scala 88:36] - node _T_366 = and(_T_365, _T_317) @[lib.scala 88:41] - node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] - node _T_368 = bits(lsu_match_data_1, 7, 7) @[lib.scala 88:86] - node _T_369 = eq(_T_367, _T_368) @[lib.scala 88:78] - node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[lib.scala 88:23] - _T_314[7] <= _T_370 @[lib.scala 88:17] - node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] - node _T_372 = andr(_T_371) @[lib.scala 88:36] - node _T_373 = and(_T_372, _T_317) @[lib.scala 88:41] - node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] - node _T_375 = bits(lsu_match_data_1, 8, 8) @[lib.scala 88:86] - node _T_376 = eq(_T_374, _T_375) @[lib.scala 88:78] - node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[lib.scala 88:23] - _T_314[8] <= _T_377 @[lib.scala 88:17] - node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] - node _T_379 = andr(_T_378) @[lib.scala 88:36] - node _T_380 = and(_T_379, _T_317) @[lib.scala 88:41] - node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] - node _T_382 = bits(lsu_match_data_1, 9, 9) @[lib.scala 88:86] - node _T_383 = eq(_T_381, _T_382) @[lib.scala 88:78] - node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[lib.scala 88:23] - _T_314[9] <= _T_384 @[lib.scala 88:17] - node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] - node _T_386 = andr(_T_385) @[lib.scala 88:36] - node _T_387 = and(_T_386, _T_317) @[lib.scala 88:41] - node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] - node _T_389 = bits(lsu_match_data_1, 10, 10) @[lib.scala 88:86] - node _T_390 = eq(_T_388, _T_389) @[lib.scala 88:78] - node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[lib.scala 88:23] - _T_314[10] <= _T_391 @[lib.scala 88:17] - node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] - node _T_393 = andr(_T_392) @[lib.scala 88:36] - node _T_394 = and(_T_393, _T_317) @[lib.scala 88:41] - node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] - node _T_396 = bits(lsu_match_data_1, 11, 11) @[lib.scala 88:86] - node _T_397 = eq(_T_395, _T_396) @[lib.scala 88:78] - node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[lib.scala 88:23] - _T_314[11] <= _T_398 @[lib.scala 88:17] - node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] - node _T_400 = andr(_T_399) @[lib.scala 88:36] - node _T_401 = and(_T_400, _T_317) @[lib.scala 88:41] - node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] - node _T_403 = bits(lsu_match_data_1, 12, 12) @[lib.scala 88:86] - node _T_404 = eq(_T_402, _T_403) @[lib.scala 88:78] - node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[lib.scala 88:23] - _T_314[12] <= _T_405 @[lib.scala 88:17] - node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] - node _T_407 = andr(_T_406) @[lib.scala 88:36] - node _T_408 = and(_T_407, _T_317) @[lib.scala 88:41] - node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] - node _T_410 = bits(lsu_match_data_1, 13, 13) @[lib.scala 88:86] - node _T_411 = eq(_T_409, _T_410) @[lib.scala 88:78] - node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[lib.scala 88:23] - _T_314[13] <= _T_412 @[lib.scala 88:17] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] - node _T_414 = andr(_T_413) @[lib.scala 88:36] - node _T_415 = and(_T_414, _T_317) @[lib.scala 88:41] - node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] - node _T_417 = bits(lsu_match_data_1, 14, 14) @[lib.scala 88:86] - node _T_418 = eq(_T_416, _T_417) @[lib.scala 88:78] - node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[lib.scala 88:23] - _T_314[14] <= _T_419 @[lib.scala 88:17] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] - node _T_421 = andr(_T_420) @[lib.scala 88:36] - node _T_422 = and(_T_421, _T_317) @[lib.scala 88:41] - node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] - node _T_424 = bits(lsu_match_data_1, 15, 15) @[lib.scala 88:86] - node _T_425 = eq(_T_423, _T_424) @[lib.scala 88:78] - node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[lib.scala 88:23] - _T_314[15] <= _T_426 @[lib.scala 88:17] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] - node _T_428 = andr(_T_427) @[lib.scala 88:36] - node _T_429 = and(_T_428, _T_317) @[lib.scala 88:41] - node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] - node _T_431 = bits(lsu_match_data_1, 16, 16) @[lib.scala 88:86] - node _T_432 = eq(_T_430, _T_431) @[lib.scala 88:78] - node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[lib.scala 88:23] - _T_314[16] <= _T_433 @[lib.scala 88:17] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] - node _T_435 = andr(_T_434) @[lib.scala 88:36] - node _T_436 = and(_T_435, _T_317) @[lib.scala 88:41] - node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] - node _T_438 = bits(lsu_match_data_1, 17, 17) @[lib.scala 88:86] - node _T_439 = eq(_T_437, _T_438) @[lib.scala 88:78] - node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[lib.scala 88:23] - _T_314[17] <= _T_440 @[lib.scala 88:17] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] - node _T_442 = andr(_T_441) @[lib.scala 88:36] - node _T_443 = and(_T_442, _T_317) @[lib.scala 88:41] - node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] - node _T_445 = bits(lsu_match_data_1, 18, 18) @[lib.scala 88:86] - node _T_446 = eq(_T_444, _T_445) @[lib.scala 88:78] - node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[lib.scala 88:23] - _T_314[18] <= _T_447 @[lib.scala 88:17] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] - node _T_449 = andr(_T_448) @[lib.scala 88:36] - node _T_450 = and(_T_449, _T_317) @[lib.scala 88:41] - node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] - node _T_452 = bits(lsu_match_data_1, 19, 19) @[lib.scala 88:86] - node _T_453 = eq(_T_451, _T_452) @[lib.scala 88:78] - node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[lib.scala 88:23] - _T_314[19] <= _T_454 @[lib.scala 88:17] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] - node _T_456 = andr(_T_455) @[lib.scala 88:36] - node _T_457 = and(_T_456, _T_317) @[lib.scala 88:41] - node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] - node _T_459 = bits(lsu_match_data_1, 20, 20) @[lib.scala 88:86] - node _T_460 = eq(_T_458, _T_459) @[lib.scala 88:78] - node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[lib.scala 88:23] - _T_314[20] <= _T_461 @[lib.scala 88:17] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] - node _T_463 = andr(_T_462) @[lib.scala 88:36] - node _T_464 = and(_T_463, _T_317) @[lib.scala 88:41] - node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] - node _T_466 = bits(lsu_match_data_1, 21, 21) @[lib.scala 88:86] - node _T_467 = eq(_T_465, _T_466) @[lib.scala 88:78] - node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[lib.scala 88:23] - _T_314[21] <= _T_468 @[lib.scala 88:17] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] - node _T_470 = andr(_T_469) @[lib.scala 88:36] - node _T_471 = and(_T_470, _T_317) @[lib.scala 88:41] - node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] - node _T_473 = bits(lsu_match_data_1, 22, 22) @[lib.scala 88:86] - node _T_474 = eq(_T_472, _T_473) @[lib.scala 88:78] - node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[lib.scala 88:23] - _T_314[22] <= _T_475 @[lib.scala 88:17] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] - node _T_477 = andr(_T_476) @[lib.scala 88:36] - node _T_478 = and(_T_477, _T_317) @[lib.scala 88:41] - node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] - node _T_480 = bits(lsu_match_data_1, 23, 23) @[lib.scala 88:86] - node _T_481 = eq(_T_479, _T_480) @[lib.scala 88:78] - node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[lib.scala 88:23] - _T_314[23] <= _T_482 @[lib.scala 88:17] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] - node _T_484 = andr(_T_483) @[lib.scala 88:36] - node _T_485 = and(_T_484, _T_317) @[lib.scala 88:41] - node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] - node _T_487 = bits(lsu_match_data_1, 24, 24) @[lib.scala 88:86] - node _T_488 = eq(_T_486, _T_487) @[lib.scala 88:78] - node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[lib.scala 88:23] - _T_314[24] <= _T_489 @[lib.scala 88:17] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] - node _T_491 = andr(_T_490) @[lib.scala 88:36] - node _T_492 = and(_T_491, _T_317) @[lib.scala 88:41] - node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] - node _T_494 = bits(lsu_match_data_1, 25, 25) @[lib.scala 88:86] - node _T_495 = eq(_T_493, _T_494) @[lib.scala 88:78] - node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[lib.scala 88:23] - _T_314[25] <= _T_496 @[lib.scala 88:17] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] - node _T_498 = andr(_T_497) @[lib.scala 88:36] - node _T_499 = and(_T_498, _T_317) @[lib.scala 88:41] - node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] - node _T_501 = bits(lsu_match_data_1, 26, 26) @[lib.scala 88:86] - node _T_502 = eq(_T_500, _T_501) @[lib.scala 88:78] - node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[lib.scala 88:23] - _T_314[26] <= _T_503 @[lib.scala 88:17] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] - node _T_505 = andr(_T_504) @[lib.scala 88:36] - node _T_506 = and(_T_505, _T_317) @[lib.scala 88:41] - node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] - node _T_508 = bits(lsu_match_data_1, 27, 27) @[lib.scala 88:86] - node _T_509 = eq(_T_507, _T_508) @[lib.scala 88:78] - node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[lib.scala 88:23] - _T_314[27] <= _T_510 @[lib.scala 88:17] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] - node _T_512 = andr(_T_511) @[lib.scala 88:36] - node _T_513 = and(_T_512, _T_317) @[lib.scala 88:41] - node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] - node _T_515 = bits(lsu_match_data_1, 28, 28) @[lib.scala 88:86] - node _T_516 = eq(_T_514, _T_515) @[lib.scala 88:78] - node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[lib.scala 88:23] - _T_314[28] <= _T_517 @[lib.scala 88:17] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] - node _T_519 = andr(_T_518) @[lib.scala 88:36] - node _T_520 = and(_T_519, _T_317) @[lib.scala 88:41] - node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] - node _T_522 = bits(lsu_match_data_1, 29, 29) @[lib.scala 88:86] - node _T_523 = eq(_T_521, _T_522) @[lib.scala 88:78] - node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[lib.scala 88:23] - _T_314[29] <= _T_524 @[lib.scala 88:17] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] - node _T_526 = andr(_T_525) @[lib.scala 88:36] - node _T_527 = and(_T_526, _T_317) @[lib.scala 88:41] - node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] - node _T_529 = bits(lsu_match_data_1, 30, 30) @[lib.scala 88:86] - node _T_530 = eq(_T_528, _T_529) @[lib.scala 88:78] - node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[lib.scala 88:23] - _T_314[30] <= _T_531 @[lib.scala 88:17] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] - node _T_533 = andr(_T_532) @[lib.scala 88:36] - node _T_534 = and(_T_533, _T_317) @[lib.scala 88:41] - node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] - node _T_536 = bits(lsu_match_data_1, 31, 31) @[lib.scala 88:86] - node _T_537 = eq(_T_535, _T_536) @[lib.scala 88:78] - node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[lib.scala 88:23] - _T_314[31] <= _T_538 @[lib.scala 88:17] - node _T_539 = cat(_T_314[1], _T_314[0]) @[lib.scala 89:14] - node _T_540 = cat(_T_314[3], _T_314[2]) @[lib.scala 89:14] - node _T_541 = cat(_T_540, _T_539) @[lib.scala 89:14] - node _T_542 = cat(_T_314[5], _T_314[4]) @[lib.scala 89:14] - node _T_543 = cat(_T_314[7], _T_314[6]) @[lib.scala 89:14] - node _T_544 = cat(_T_543, _T_542) @[lib.scala 89:14] - node _T_545 = cat(_T_544, _T_541) @[lib.scala 89:14] - node _T_546 = cat(_T_314[9], _T_314[8]) @[lib.scala 89:14] - node _T_547 = cat(_T_314[11], _T_314[10]) @[lib.scala 89:14] - node _T_548 = cat(_T_547, _T_546) @[lib.scala 89:14] - node _T_549 = cat(_T_314[13], _T_314[12]) @[lib.scala 89:14] - node _T_550 = cat(_T_314[15], _T_314[14]) @[lib.scala 89:14] - node _T_551 = cat(_T_550, _T_549) @[lib.scala 89:14] - node _T_552 = cat(_T_551, _T_548) @[lib.scala 89:14] - node _T_553 = cat(_T_552, _T_545) @[lib.scala 89:14] - node _T_554 = cat(_T_314[17], _T_314[16]) @[lib.scala 89:14] - node _T_555 = cat(_T_314[19], _T_314[18]) @[lib.scala 89:14] - node _T_556 = cat(_T_555, _T_554) @[lib.scala 89:14] - node _T_557 = cat(_T_314[21], _T_314[20]) @[lib.scala 89:14] - node _T_558 = cat(_T_314[23], _T_314[22]) @[lib.scala 89:14] - node _T_559 = cat(_T_558, _T_557) @[lib.scala 89:14] - node _T_560 = cat(_T_559, _T_556) @[lib.scala 89:14] - node _T_561 = cat(_T_314[25], _T_314[24]) @[lib.scala 89:14] - node _T_562 = cat(_T_314[27], _T_314[26]) @[lib.scala 89:14] - node _T_563 = cat(_T_562, _T_561) @[lib.scala 89:14] - node _T_564 = cat(_T_314[29], _T_314[28]) @[lib.scala 89:14] - node _T_565 = cat(_T_314[31], _T_314[30]) @[lib.scala 89:14] - node _T_566 = cat(_T_565, _T_564) @[lib.scala 89:14] - node _T_567 = cat(_T_566, _T_563) @[lib.scala 89:14] - node _T_568 = cat(_T_567, _T_560) @[lib.scala 89:14] - node _T_569 = cat(_T_568, _T_553) @[lib.scala 89:14] - node _T_570 = and(_T_312, _T_569) @[lsu_trigger.scala 19:92] - node _T_571 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_572 = and(io.lsu_pkt_m.valid, _T_571) @[lsu_trigger.scala 18:69] - node _T_573 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_574 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_575 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_576 = and(_T_574, _T_575) @[lsu_trigger.scala 19:58] - node _T_577 = or(_T_573, _T_576) @[lsu_trigger.scala 18:152] - node _T_578 = and(_T_572, _T_577) @[lsu_trigger.scala 18:94] - node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_580 : UInt<1>[32] @[lib.scala 84:24] - node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] - node _T_582 = not(_T_581) @[lib.scala 85:39] - node _T_583 = and(_T_579, _T_582) @[lib.scala 85:37] - node _T_584 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] - node _T_585 = bits(lsu_match_data_2, 0, 0) @[lib.scala 86:60] - node _T_586 = eq(_T_584, _T_585) @[lib.scala 86:52] - node _T_587 = or(_T_583, _T_586) @[lib.scala 86:41] - _T_580[0] <= _T_587 @[lib.scala 86:18] - node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] - node _T_589 = andr(_T_588) @[lib.scala 88:36] - node _T_590 = and(_T_589, _T_583) @[lib.scala 88:41] - node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] - node _T_592 = bits(lsu_match_data_2, 1, 1) @[lib.scala 88:86] - node _T_593 = eq(_T_591, _T_592) @[lib.scala 88:78] - node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[lib.scala 88:23] - _T_580[1] <= _T_594 @[lib.scala 88:17] - node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] - node _T_596 = andr(_T_595) @[lib.scala 88:36] - node _T_597 = and(_T_596, _T_583) @[lib.scala 88:41] - node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] - node _T_599 = bits(lsu_match_data_2, 2, 2) @[lib.scala 88:86] - node _T_600 = eq(_T_598, _T_599) @[lib.scala 88:78] - node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[lib.scala 88:23] - _T_580[2] <= _T_601 @[lib.scala 88:17] - node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] - node _T_603 = andr(_T_602) @[lib.scala 88:36] - node _T_604 = and(_T_603, _T_583) @[lib.scala 88:41] - node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] - node _T_606 = bits(lsu_match_data_2, 3, 3) @[lib.scala 88:86] - node _T_607 = eq(_T_605, _T_606) @[lib.scala 88:78] - node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[lib.scala 88:23] - _T_580[3] <= _T_608 @[lib.scala 88:17] - node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] - node _T_610 = andr(_T_609) @[lib.scala 88:36] - node _T_611 = and(_T_610, _T_583) @[lib.scala 88:41] - node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] - node _T_613 = bits(lsu_match_data_2, 4, 4) @[lib.scala 88:86] - node _T_614 = eq(_T_612, _T_613) @[lib.scala 88:78] - node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[lib.scala 88:23] - _T_580[4] <= _T_615 @[lib.scala 88:17] - node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] - node _T_617 = andr(_T_616) @[lib.scala 88:36] - node _T_618 = and(_T_617, _T_583) @[lib.scala 88:41] - node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] - node _T_620 = bits(lsu_match_data_2, 5, 5) @[lib.scala 88:86] - node _T_621 = eq(_T_619, _T_620) @[lib.scala 88:78] - node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[lib.scala 88:23] - _T_580[5] <= _T_622 @[lib.scala 88:17] - node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] - node _T_624 = andr(_T_623) @[lib.scala 88:36] - node _T_625 = and(_T_624, _T_583) @[lib.scala 88:41] - node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] - node _T_627 = bits(lsu_match_data_2, 6, 6) @[lib.scala 88:86] - node _T_628 = eq(_T_626, _T_627) @[lib.scala 88:78] - node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[lib.scala 88:23] - _T_580[6] <= _T_629 @[lib.scala 88:17] - node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] - node _T_631 = andr(_T_630) @[lib.scala 88:36] - node _T_632 = and(_T_631, _T_583) @[lib.scala 88:41] - node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] - node _T_634 = bits(lsu_match_data_2, 7, 7) @[lib.scala 88:86] - node _T_635 = eq(_T_633, _T_634) @[lib.scala 88:78] - node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[lib.scala 88:23] - _T_580[7] <= _T_636 @[lib.scala 88:17] - node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] - node _T_638 = andr(_T_637) @[lib.scala 88:36] - node _T_639 = and(_T_638, _T_583) @[lib.scala 88:41] - node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] - node _T_641 = bits(lsu_match_data_2, 8, 8) @[lib.scala 88:86] - node _T_642 = eq(_T_640, _T_641) @[lib.scala 88:78] - node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[lib.scala 88:23] - _T_580[8] <= _T_643 @[lib.scala 88:17] - node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] - node _T_645 = andr(_T_644) @[lib.scala 88:36] - node _T_646 = and(_T_645, _T_583) @[lib.scala 88:41] - node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] - node _T_648 = bits(lsu_match_data_2, 9, 9) @[lib.scala 88:86] - node _T_649 = eq(_T_647, _T_648) @[lib.scala 88:78] - node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[lib.scala 88:23] - _T_580[9] <= _T_650 @[lib.scala 88:17] - node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] - node _T_652 = andr(_T_651) @[lib.scala 88:36] - node _T_653 = and(_T_652, _T_583) @[lib.scala 88:41] - node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] - node _T_655 = bits(lsu_match_data_2, 10, 10) @[lib.scala 88:86] - node _T_656 = eq(_T_654, _T_655) @[lib.scala 88:78] - node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[lib.scala 88:23] - _T_580[10] <= _T_657 @[lib.scala 88:17] - node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] - node _T_659 = andr(_T_658) @[lib.scala 88:36] - node _T_660 = and(_T_659, _T_583) @[lib.scala 88:41] - node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] - node _T_662 = bits(lsu_match_data_2, 11, 11) @[lib.scala 88:86] - node _T_663 = eq(_T_661, _T_662) @[lib.scala 88:78] - node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[lib.scala 88:23] - _T_580[11] <= _T_664 @[lib.scala 88:17] - node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] - node _T_666 = andr(_T_665) @[lib.scala 88:36] - node _T_667 = and(_T_666, _T_583) @[lib.scala 88:41] - node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] - node _T_669 = bits(lsu_match_data_2, 12, 12) @[lib.scala 88:86] - node _T_670 = eq(_T_668, _T_669) @[lib.scala 88:78] - node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[lib.scala 88:23] - _T_580[12] <= _T_671 @[lib.scala 88:17] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] - node _T_673 = andr(_T_672) @[lib.scala 88:36] - node _T_674 = and(_T_673, _T_583) @[lib.scala 88:41] - node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] - node _T_676 = bits(lsu_match_data_2, 13, 13) @[lib.scala 88:86] - node _T_677 = eq(_T_675, _T_676) @[lib.scala 88:78] - node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[lib.scala 88:23] - _T_580[13] <= _T_678 @[lib.scala 88:17] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] - node _T_680 = andr(_T_679) @[lib.scala 88:36] - node _T_681 = and(_T_680, _T_583) @[lib.scala 88:41] - node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] - node _T_683 = bits(lsu_match_data_2, 14, 14) @[lib.scala 88:86] - node _T_684 = eq(_T_682, _T_683) @[lib.scala 88:78] - node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[lib.scala 88:23] - _T_580[14] <= _T_685 @[lib.scala 88:17] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] - node _T_687 = andr(_T_686) @[lib.scala 88:36] - node _T_688 = and(_T_687, _T_583) @[lib.scala 88:41] - node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] - node _T_690 = bits(lsu_match_data_2, 15, 15) @[lib.scala 88:86] - node _T_691 = eq(_T_689, _T_690) @[lib.scala 88:78] - node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[lib.scala 88:23] - _T_580[15] <= _T_692 @[lib.scala 88:17] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] - node _T_694 = andr(_T_693) @[lib.scala 88:36] - node _T_695 = and(_T_694, _T_583) @[lib.scala 88:41] - node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] - node _T_697 = bits(lsu_match_data_2, 16, 16) @[lib.scala 88:86] - node _T_698 = eq(_T_696, _T_697) @[lib.scala 88:78] - node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[lib.scala 88:23] - _T_580[16] <= _T_699 @[lib.scala 88:17] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] - node _T_701 = andr(_T_700) @[lib.scala 88:36] - node _T_702 = and(_T_701, _T_583) @[lib.scala 88:41] - node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] - node _T_704 = bits(lsu_match_data_2, 17, 17) @[lib.scala 88:86] - node _T_705 = eq(_T_703, _T_704) @[lib.scala 88:78] - node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[lib.scala 88:23] - _T_580[17] <= _T_706 @[lib.scala 88:17] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] - node _T_708 = andr(_T_707) @[lib.scala 88:36] - node _T_709 = and(_T_708, _T_583) @[lib.scala 88:41] - node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] - node _T_711 = bits(lsu_match_data_2, 18, 18) @[lib.scala 88:86] - node _T_712 = eq(_T_710, _T_711) @[lib.scala 88:78] - node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[lib.scala 88:23] - _T_580[18] <= _T_713 @[lib.scala 88:17] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] - node _T_715 = andr(_T_714) @[lib.scala 88:36] - node _T_716 = and(_T_715, _T_583) @[lib.scala 88:41] - node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] - node _T_718 = bits(lsu_match_data_2, 19, 19) @[lib.scala 88:86] - node _T_719 = eq(_T_717, _T_718) @[lib.scala 88:78] - node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[lib.scala 88:23] - _T_580[19] <= _T_720 @[lib.scala 88:17] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] - node _T_722 = andr(_T_721) @[lib.scala 88:36] - node _T_723 = and(_T_722, _T_583) @[lib.scala 88:41] - node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] - node _T_725 = bits(lsu_match_data_2, 20, 20) @[lib.scala 88:86] - node _T_726 = eq(_T_724, _T_725) @[lib.scala 88:78] - node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[lib.scala 88:23] - _T_580[20] <= _T_727 @[lib.scala 88:17] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] - node _T_729 = andr(_T_728) @[lib.scala 88:36] - node _T_730 = and(_T_729, _T_583) @[lib.scala 88:41] - node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] - node _T_732 = bits(lsu_match_data_2, 21, 21) @[lib.scala 88:86] - node _T_733 = eq(_T_731, _T_732) @[lib.scala 88:78] - node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[lib.scala 88:23] - _T_580[21] <= _T_734 @[lib.scala 88:17] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] - node _T_736 = andr(_T_735) @[lib.scala 88:36] - node _T_737 = and(_T_736, _T_583) @[lib.scala 88:41] - node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] - node _T_739 = bits(lsu_match_data_2, 22, 22) @[lib.scala 88:86] - node _T_740 = eq(_T_738, _T_739) @[lib.scala 88:78] - node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[lib.scala 88:23] - _T_580[22] <= _T_741 @[lib.scala 88:17] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] - node _T_743 = andr(_T_742) @[lib.scala 88:36] - node _T_744 = and(_T_743, _T_583) @[lib.scala 88:41] - node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] - node _T_746 = bits(lsu_match_data_2, 23, 23) @[lib.scala 88:86] - node _T_747 = eq(_T_745, _T_746) @[lib.scala 88:78] - node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[lib.scala 88:23] - _T_580[23] <= _T_748 @[lib.scala 88:17] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] - node _T_750 = andr(_T_749) @[lib.scala 88:36] - node _T_751 = and(_T_750, _T_583) @[lib.scala 88:41] - node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] - node _T_753 = bits(lsu_match_data_2, 24, 24) @[lib.scala 88:86] - node _T_754 = eq(_T_752, _T_753) @[lib.scala 88:78] - node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[lib.scala 88:23] - _T_580[24] <= _T_755 @[lib.scala 88:17] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] - node _T_757 = andr(_T_756) @[lib.scala 88:36] - node _T_758 = and(_T_757, _T_583) @[lib.scala 88:41] - node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] - node _T_760 = bits(lsu_match_data_2, 25, 25) @[lib.scala 88:86] - node _T_761 = eq(_T_759, _T_760) @[lib.scala 88:78] - node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[lib.scala 88:23] - _T_580[25] <= _T_762 @[lib.scala 88:17] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] - node _T_764 = andr(_T_763) @[lib.scala 88:36] - node _T_765 = and(_T_764, _T_583) @[lib.scala 88:41] - node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] - node _T_767 = bits(lsu_match_data_2, 26, 26) @[lib.scala 88:86] - node _T_768 = eq(_T_766, _T_767) @[lib.scala 88:78] - node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[lib.scala 88:23] - _T_580[26] <= _T_769 @[lib.scala 88:17] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] - node _T_771 = andr(_T_770) @[lib.scala 88:36] - node _T_772 = and(_T_771, _T_583) @[lib.scala 88:41] - node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] - node _T_774 = bits(lsu_match_data_2, 27, 27) @[lib.scala 88:86] - node _T_775 = eq(_T_773, _T_774) @[lib.scala 88:78] - node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[lib.scala 88:23] - _T_580[27] <= _T_776 @[lib.scala 88:17] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] - node _T_778 = andr(_T_777) @[lib.scala 88:36] - node _T_779 = and(_T_778, _T_583) @[lib.scala 88:41] - node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] - node _T_781 = bits(lsu_match_data_2, 28, 28) @[lib.scala 88:86] - node _T_782 = eq(_T_780, _T_781) @[lib.scala 88:78] - node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[lib.scala 88:23] - _T_580[28] <= _T_783 @[lib.scala 88:17] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] - node _T_785 = andr(_T_784) @[lib.scala 88:36] - node _T_786 = and(_T_785, _T_583) @[lib.scala 88:41] - node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] - node _T_788 = bits(lsu_match_data_2, 29, 29) @[lib.scala 88:86] - node _T_789 = eq(_T_787, _T_788) @[lib.scala 88:78] - node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[lib.scala 88:23] - _T_580[29] <= _T_790 @[lib.scala 88:17] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] - node _T_792 = andr(_T_791) @[lib.scala 88:36] - node _T_793 = and(_T_792, _T_583) @[lib.scala 88:41] - node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] - node _T_795 = bits(lsu_match_data_2, 30, 30) @[lib.scala 88:86] - node _T_796 = eq(_T_794, _T_795) @[lib.scala 88:78] - node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[lib.scala 88:23] - _T_580[30] <= _T_797 @[lib.scala 88:17] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] - node _T_799 = andr(_T_798) @[lib.scala 88:36] - node _T_800 = and(_T_799, _T_583) @[lib.scala 88:41] - node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] - node _T_802 = bits(lsu_match_data_2, 31, 31) @[lib.scala 88:86] - node _T_803 = eq(_T_801, _T_802) @[lib.scala 88:78] - node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[lib.scala 88:23] - _T_580[31] <= _T_804 @[lib.scala 88:17] - node _T_805 = cat(_T_580[1], _T_580[0]) @[lib.scala 89:14] - node _T_806 = cat(_T_580[3], _T_580[2]) @[lib.scala 89:14] - node _T_807 = cat(_T_806, _T_805) @[lib.scala 89:14] - node _T_808 = cat(_T_580[5], _T_580[4]) @[lib.scala 89:14] - node _T_809 = cat(_T_580[7], _T_580[6]) @[lib.scala 89:14] - node _T_810 = cat(_T_809, _T_808) @[lib.scala 89:14] - node _T_811 = cat(_T_810, _T_807) @[lib.scala 89:14] - node _T_812 = cat(_T_580[9], _T_580[8]) @[lib.scala 89:14] - node _T_813 = cat(_T_580[11], _T_580[10]) @[lib.scala 89:14] - node _T_814 = cat(_T_813, _T_812) @[lib.scala 89:14] - node _T_815 = cat(_T_580[13], _T_580[12]) @[lib.scala 89:14] - node _T_816 = cat(_T_580[15], _T_580[14]) @[lib.scala 89:14] - node _T_817 = cat(_T_816, _T_815) @[lib.scala 89:14] - node _T_818 = cat(_T_817, _T_814) @[lib.scala 89:14] - node _T_819 = cat(_T_818, _T_811) @[lib.scala 89:14] - node _T_820 = cat(_T_580[17], _T_580[16]) @[lib.scala 89:14] - node _T_821 = cat(_T_580[19], _T_580[18]) @[lib.scala 89:14] - node _T_822 = cat(_T_821, _T_820) @[lib.scala 89:14] - node _T_823 = cat(_T_580[21], _T_580[20]) @[lib.scala 89:14] - node _T_824 = cat(_T_580[23], _T_580[22]) @[lib.scala 89:14] - node _T_825 = cat(_T_824, _T_823) @[lib.scala 89:14] - node _T_826 = cat(_T_825, _T_822) @[lib.scala 89:14] - node _T_827 = cat(_T_580[25], _T_580[24]) @[lib.scala 89:14] - node _T_828 = cat(_T_580[27], _T_580[26]) @[lib.scala 89:14] - node _T_829 = cat(_T_828, _T_827) @[lib.scala 89:14] - node _T_830 = cat(_T_580[29], _T_580[28]) @[lib.scala 89:14] - node _T_831 = cat(_T_580[31], _T_580[30]) @[lib.scala 89:14] - node _T_832 = cat(_T_831, _T_830) @[lib.scala 89:14] - node _T_833 = cat(_T_832, _T_829) @[lib.scala 89:14] - node _T_834 = cat(_T_833, _T_826) @[lib.scala 89:14] - node _T_835 = cat(_T_834, _T_819) @[lib.scala 89:14] - node _T_836 = and(_T_578, _T_835) @[lsu_trigger.scala 19:92] - node _T_837 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_838 = and(io.lsu_pkt_m.valid, _T_837) @[lsu_trigger.scala 18:69] - node _T_839 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_840 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_841 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_842 = and(_T_840, _T_841) @[lsu_trigger.scala 19:58] - node _T_843 = or(_T_839, _T_842) @[lsu_trigger.scala 18:152] - node _T_844 = and(_T_838, _T_843) @[lsu_trigger.scala 18:94] - node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_846 : UInt<1>[32] @[lib.scala 84:24] - node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] - node _T_848 = not(_T_847) @[lib.scala 85:39] - node _T_849 = and(_T_845, _T_848) @[lib.scala 85:37] - node _T_850 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] - node _T_851 = bits(lsu_match_data_3, 0, 0) @[lib.scala 86:60] - node _T_852 = eq(_T_850, _T_851) @[lib.scala 86:52] - node _T_853 = or(_T_849, _T_852) @[lib.scala 86:41] - _T_846[0] <= _T_853 @[lib.scala 86:18] - node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] - node _T_855 = andr(_T_854) @[lib.scala 88:36] - node _T_856 = and(_T_855, _T_849) @[lib.scala 88:41] - node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] - node _T_858 = bits(lsu_match_data_3, 1, 1) @[lib.scala 88:86] - node _T_859 = eq(_T_857, _T_858) @[lib.scala 88:78] - node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[lib.scala 88:23] - _T_846[1] <= _T_860 @[lib.scala 88:17] - node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] - node _T_862 = andr(_T_861) @[lib.scala 88:36] - node _T_863 = and(_T_862, _T_849) @[lib.scala 88:41] - node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] - node _T_865 = bits(lsu_match_data_3, 2, 2) @[lib.scala 88:86] - node _T_866 = eq(_T_864, _T_865) @[lib.scala 88:78] - node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[lib.scala 88:23] - _T_846[2] <= _T_867 @[lib.scala 88:17] - node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] - node _T_869 = andr(_T_868) @[lib.scala 88:36] - node _T_870 = and(_T_869, _T_849) @[lib.scala 88:41] - node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] - node _T_872 = bits(lsu_match_data_3, 3, 3) @[lib.scala 88:86] - node _T_873 = eq(_T_871, _T_872) @[lib.scala 88:78] - node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[lib.scala 88:23] - _T_846[3] <= _T_874 @[lib.scala 88:17] - node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] - node _T_876 = andr(_T_875) @[lib.scala 88:36] - node _T_877 = and(_T_876, _T_849) @[lib.scala 88:41] - node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] - node _T_879 = bits(lsu_match_data_3, 4, 4) @[lib.scala 88:86] - node _T_880 = eq(_T_878, _T_879) @[lib.scala 88:78] - node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[lib.scala 88:23] - _T_846[4] <= _T_881 @[lib.scala 88:17] - node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] - node _T_883 = andr(_T_882) @[lib.scala 88:36] - node _T_884 = and(_T_883, _T_849) @[lib.scala 88:41] - node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] - node _T_886 = bits(lsu_match_data_3, 5, 5) @[lib.scala 88:86] - node _T_887 = eq(_T_885, _T_886) @[lib.scala 88:78] - node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[lib.scala 88:23] - _T_846[5] <= _T_888 @[lib.scala 88:17] - node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] - node _T_890 = andr(_T_889) @[lib.scala 88:36] - node _T_891 = and(_T_890, _T_849) @[lib.scala 88:41] - node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] - node _T_893 = bits(lsu_match_data_3, 6, 6) @[lib.scala 88:86] - node _T_894 = eq(_T_892, _T_893) @[lib.scala 88:78] - node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[lib.scala 88:23] - _T_846[6] <= _T_895 @[lib.scala 88:17] - node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] - node _T_897 = andr(_T_896) @[lib.scala 88:36] - node _T_898 = and(_T_897, _T_849) @[lib.scala 88:41] - node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] - node _T_900 = bits(lsu_match_data_3, 7, 7) @[lib.scala 88:86] - node _T_901 = eq(_T_899, _T_900) @[lib.scala 88:78] - node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[lib.scala 88:23] - _T_846[7] <= _T_902 @[lib.scala 88:17] - node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] - node _T_904 = andr(_T_903) @[lib.scala 88:36] - node _T_905 = and(_T_904, _T_849) @[lib.scala 88:41] - node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] - node _T_907 = bits(lsu_match_data_3, 8, 8) @[lib.scala 88:86] - node _T_908 = eq(_T_906, _T_907) @[lib.scala 88:78] - node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[lib.scala 88:23] - _T_846[8] <= _T_909 @[lib.scala 88:17] - node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] - node _T_911 = andr(_T_910) @[lib.scala 88:36] - node _T_912 = and(_T_911, _T_849) @[lib.scala 88:41] - node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] - node _T_914 = bits(lsu_match_data_3, 9, 9) @[lib.scala 88:86] - node _T_915 = eq(_T_913, _T_914) @[lib.scala 88:78] - node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[lib.scala 88:23] - _T_846[9] <= _T_916 @[lib.scala 88:17] - node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] - node _T_918 = andr(_T_917) @[lib.scala 88:36] - node _T_919 = and(_T_918, _T_849) @[lib.scala 88:41] - node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] - node _T_921 = bits(lsu_match_data_3, 10, 10) @[lib.scala 88:86] - node _T_922 = eq(_T_920, _T_921) @[lib.scala 88:78] - node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[lib.scala 88:23] - _T_846[10] <= _T_923 @[lib.scala 88:17] - node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] - node _T_925 = andr(_T_924) @[lib.scala 88:36] - node _T_926 = and(_T_925, _T_849) @[lib.scala 88:41] - node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] - node _T_928 = bits(lsu_match_data_3, 11, 11) @[lib.scala 88:86] - node _T_929 = eq(_T_927, _T_928) @[lib.scala 88:78] - node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[lib.scala 88:23] - _T_846[11] <= _T_930 @[lib.scala 88:17] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] - node _T_932 = andr(_T_931) @[lib.scala 88:36] - node _T_933 = and(_T_932, _T_849) @[lib.scala 88:41] - node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] - node _T_935 = bits(lsu_match_data_3, 12, 12) @[lib.scala 88:86] - node _T_936 = eq(_T_934, _T_935) @[lib.scala 88:78] - node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[lib.scala 88:23] - _T_846[12] <= _T_937 @[lib.scala 88:17] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] - node _T_939 = andr(_T_938) @[lib.scala 88:36] - node _T_940 = and(_T_939, _T_849) @[lib.scala 88:41] - node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] - node _T_942 = bits(lsu_match_data_3, 13, 13) @[lib.scala 88:86] - node _T_943 = eq(_T_941, _T_942) @[lib.scala 88:78] - node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 88:23] - _T_846[13] <= _T_944 @[lib.scala 88:17] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] - node _T_946 = andr(_T_945) @[lib.scala 88:36] - node _T_947 = and(_T_946, _T_849) @[lib.scala 88:41] - node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] - node _T_949 = bits(lsu_match_data_3, 14, 14) @[lib.scala 88:86] - node _T_950 = eq(_T_948, _T_949) @[lib.scala 88:78] - node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 88:23] - _T_846[14] <= _T_951 @[lib.scala 88:17] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] - node _T_953 = andr(_T_952) @[lib.scala 88:36] - node _T_954 = and(_T_953, _T_849) @[lib.scala 88:41] - node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] - node _T_956 = bits(lsu_match_data_3, 15, 15) @[lib.scala 88:86] - node _T_957 = eq(_T_955, _T_956) @[lib.scala 88:78] - node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 88:23] - _T_846[15] <= _T_958 @[lib.scala 88:17] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] - node _T_960 = andr(_T_959) @[lib.scala 88:36] - node _T_961 = and(_T_960, _T_849) @[lib.scala 88:41] - node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] - node _T_963 = bits(lsu_match_data_3, 16, 16) @[lib.scala 88:86] - node _T_964 = eq(_T_962, _T_963) @[lib.scala 88:78] - node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 88:23] - _T_846[16] <= _T_965 @[lib.scala 88:17] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] - node _T_967 = andr(_T_966) @[lib.scala 88:36] - node _T_968 = and(_T_967, _T_849) @[lib.scala 88:41] - node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] - node _T_970 = bits(lsu_match_data_3, 17, 17) @[lib.scala 88:86] - node _T_971 = eq(_T_969, _T_970) @[lib.scala 88:78] - node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 88:23] - _T_846[17] <= _T_972 @[lib.scala 88:17] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] - node _T_974 = andr(_T_973) @[lib.scala 88:36] - node _T_975 = and(_T_974, _T_849) @[lib.scala 88:41] - node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] - node _T_977 = bits(lsu_match_data_3, 18, 18) @[lib.scala 88:86] - node _T_978 = eq(_T_976, _T_977) @[lib.scala 88:78] - node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 88:23] - _T_846[18] <= _T_979 @[lib.scala 88:17] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] - node _T_981 = andr(_T_980) @[lib.scala 88:36] - node _T_982 = and(_T_981, _T_849) @[lib.scala 88:41] - node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] - node _T_984 = bits(lsu_match_data_3, 19, 19) @[lib.scala 88:86] - node _T_985 = eq(_T_983, _T_984) @[lib.scala 88:78] - node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 88:23] - _T_846[19] <= _T_986 @[lib.scala 88:17] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] - node _T_988 = andr(_T_987) @[lib.scala 88:36] - node _T_989 = and(_T_988, _T_849) @[lib.scala 88:41] - node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] - node _T_991 = bits(lsu_match_data_3, 20, 20) @[lib.scala 88:86] - node _T_992 = eq(_T_990, _T_991) @[lib.scala 88:78] - node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 88:23] - _T_846[20] <= _T_993 @[lib.scala 88:17] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] - node _T_995 = andr(_T_994) @[lib.scala 88:36] - node _T_996 = and(_T_995, _T_849) @[lib.scala 88:41] - node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] - node _T_998 = bits(lsu_match_data_3, 21, 21) @[lib.scala 88:86] - node _T_999 = eq(_T_997, _T_998) @[lib.scala 88:78] - node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 88:23] - _T_846[21] <= _T_1000 @[lib.scala 88:17] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] - node _T_1002 = andr(_T_1001) @[lib.scala 88:36] - node _T_1003 = and(_T_1002, _T_849) @[lib.scala 88:41] - node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] - node _T_1005 = bits(lsu_match_data_3, 22, 22) @[lib.scala 88:86] - node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 88:78] - node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 88:23] - _T_846[22] <= _T_1007 @[lib.scala 88:17] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] - node _T_1009 = andr(_T_1008) @[lib.scala 88:36] - node _T_1010 = and(_T_1009, _T_849) @[lib.scala 88:41] - node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] - node _T_1012 = bits(lsu_match_data_3, 23, 23) @[lib.scala 88:86] - node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 88:78] - node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 88:23] - _T_846[23] <= _T_1014 @[lib.scala 88:17] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] - node _T_1016 = andr(_T_1015) @[lib.scala 88:36] - node _T_1017 = and(_T_1016, _T_849) @[lib.scala 88:41] - node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] - node _T_1019 = bits(lsu_match_data_3, 24, 24) @[lib.scala 88:86] - node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 88:78] - node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 88:23] - _T_846[24] <= _T_1021 @[lib.scala 88:17] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] - node _T_1023 = andr(_T_1022) @[lib.scala 88:36] - node _T_1024 = and(_T_1023, _T_849) @[lib.scala 88:41] - node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] - node _T_1026 = bits(lsu_match_data_3, 25, 25) @[lib.scala 88:86] - node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 88:78] - node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 88:23] - _T_846[25] <= _T_1028 @[lib.scala 88:17] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] - node _T_1030 = andr(_T_1029) @[lib.scala 88:36] - node _T_1031 = and(_T_1030, _T_849) @[lib.scala 88:41] - node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] - node _T_1033 = bits(lsu_match_data_3, 26, 26) @[lib.scala 88:86] - node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 88:78] - node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 88:23] - _T_846[26] <= _T_1035 @[lib.scala 88:17] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] - node _T_1037 = andr(_T_1036) @[lib.scala 88:36] - node _T_1038 = and(_T_1037, _T_849) @[lib.scala 88:41] - node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] - node _T_1040 = bits(lsu_match_data_3, 27, 27) @[lib.scala 88:86] - node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 88:78] - node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 88:23] - _T_846[27] <= _T_1042 @[lib.scala 88:17] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] - node _T_1044 = andr(_T_1043) @[lib.scala 88:36] - node _T_1045 = and(_T_1044, _T_849) @[lib.scala 88:41] - node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] - node _T_1047 = bits(lsu_match_data_3, 28, 28) @[lib.scala 88:86] - node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 88:78] - node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 88:23] - _T_846[28] <= _T_1049 @[lib.scala 88:17] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] - node _T_1051 = andr(_T_1050) @[lib.scala 88:36] - node _T_1052 = and(_T_1051, _T_849) @[lib.scala 88:41] - node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] - node _T_1054 = bits(lsu_match_data_3, 29, 29) @[lib.scala 88:86] - node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 88:78] - node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 88:23] - _T_846[29] <= _T_1056 @[lib.scala 88:17] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] - node _T_1058 = andr(_T_1057) @[lib.scala 88:36] - node _T_1059 = and(_T_1058, _T_849) @[lib.scala 88:41] - node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] - node _T_1061 = bits(lsu_match_data_3, 30, 30) @[lib.scala 88:86] - node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 88:78] - node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 88:23] - _T_846[30] <= _T_1063 @[lib.scala 88:17] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] - node _T_1065 = andr(_T_1064) @[lib.scala 88:36] - node _T_1066 = and(_T_1065, _T_849) @[lib.scala 88:41] - node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] - node _T_1068 = bits(lsu_match_data_3, 31, 31) @[lib.scala 88:86] - node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 88:78] - node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 88:23] - _T_846[31] <= _T_1070 @[lib.scala 88:17] - node _T_1071 = cat(_T_846[1], _T_846[0]) @[lib.scala 89:14] - node _T_1072 = cat(_T_846[3], _T_846[2]) @[lib.scala 89:14] - node _T_1073 = cat(_T_1072, _T_1071) @[lib.scala 89:14] - node _T_1074 = cat(_T_846[5], _T_846[4]) @[lib.scala 89:14] - node _T_1075 = cat(_T_846[7], _T_846[6]) @[lib.scala 89:14] + node _T_304 = andr(_T_303) @[lib.scala 89:25] + node _T_305 = and(_T_46, _T_304) @[lsu_trigger.scala 19:92] + node _T_306 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_307 = and(io.lsu_pkt_m.valid, _T_306) @[lsu_trigger.scala 18:69] + node _T_308 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_309 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_310 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_311 = and(_T_309, _T_310) @[lsu_trigger.scala 19:58] + node _T_312 = or(_T_308, _T_311) @[lsu_trigger.scala 18:152] + node _T_313 = and(_T_307, _T_312) @[lsu_trigger.scala 18:94] + node _T_314 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_315 : UInt<1>[32] @[lib.scala 84:24] + node _T_316 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] + node _T_317 = not(_T_316) @[lib.scala 85:39] + node _T_318 = and(_T_314, _T_317) @[lib.scala 85:37] + node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] + node _T_320 = bits(lsu_match_data_1, 0, 0) @[lib.scala 86:60] + node _T_321 = eq(_T_319, _T_320) @[lib.scala 86:52] + node _T_322 = or(_T_318, _T_321) @[lib.scala 86:41] + _T_315[0] <= _T_322 @[lib.scala 86:18] + node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] + node _T_324 = andr(_T_323) @[lib.scala 88:36] + node _T_325 = and(_T_324, _T_318) @[lib.scala 88:41] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] + node _T_327 = bits(lsu_match_data_1, 1, 1) @[lib.scala 88:86] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 88:78] + node _T_329 = mux(_T_325, UInt<1>("h01"), _T_328) @[lib.scala 88:23] + _T_315[1] <= _T_329 @[lib.scala 88:17] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] + node _T_331 = andr(_T_330) @[lib.scala 88:36] + node _T_332 = and(_T_331, _T_318) @[lib.scala 88:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] + node _T_334 = bits(lsu_match_data_1, 2, 2) @[lib.scala 88:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 88:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 88:23] + _T_315[2] <= _T_336 @[lib.scala 88:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] + node _T_338 = andr(_T_337) @[lib.scala 88:36] + node _T_339 = and(_T_338, _T_318) @[lib.scala 88:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] + node _T_341 = bits(lsu_match_data_1, 3, 3) @[lib.scala 88:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 88:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 88:23] + _T_315[3] <= _T_343 @[lib.scala 88:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] + node _T_345 = andr(_T_344) @[lib.scala 88:36] + node _T_346 = and(_T_345, _T_318) @[lib.scala 88:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] + node _T_348 = bits(lsu_match_data_1, 4, 4) @[lib.scala 88:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 88:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 88:23] + _T_315[4] <= _T_350 @[lib.scala 88:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] + node _T_352 = andr(_T_351) @[lib.scala 88:36] + node _T_353 = and(_T_352, _T_318) @[lib.scala 88:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] + node _T_355 = bits(lsu_match_data_1, 5, 5) @[lib.scala 88:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 88:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 88:23] + _T_315[5] <= _T_357 @[lib.scala 88:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] + node _T_359 = andr(_T_358) @[lib.scala 88:36] + node _T_360 = and(_T_359, _T_318) @[lib.scala 88:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] + node _T_362 = bits(lsu_match_data_1, 6, 6) @[lib.scala 88:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 88:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 88:23] + _T_315[6] <= _T_364 @[lib.scala 88:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] + node _T_366 = andr(_T_365) @[lib.scala 88:36] + node _T_367 = and(_T_366, _T_318) @[lib.scala 88:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] + node _T_369 = bits(lsu_match_data_1, 7, 7) @[lib.scala 88:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 88:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 88:23] + _T_315[7] <= _T_371 @[lib.scala 88:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] + node _T_373 = andr(_T_372) @[lib.scala 88:36] + node _T_374 = and(_T_373, _T_318) @[lib.scala 88:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] + node _T_376 = bits(lsu_match_data_1, 8, 8) @[lib.scala 88:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 88:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 88:23] + _T_315[8] <= _T_378 @[lib.scala 88:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] + node _T_380 = andr(_T_379) @[lib.scala 88:36] + node _T_381 = and(_T_380, _T_318) @[lib.scala 88:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] + node _T_383 = bits(lsu_match_data_1, 9, 9) @[lib.scala 88:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 88:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 88:23] + _T_315[9] <= _T_385 @[lib.scala 88:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] + node _T_387 = andr(_T_386) @[lib.scala 88:36] + node _T_388 = and(_T_387, _T_318) @[lib.scala 88:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] + node _T_390 = bits(lsu_match_data_1, 10, 10) @[lib.scala 88:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 88:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 88:23] + _T_315[10] <= _T_392 @[lib.scala 88:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] + node _T_394 = andr(_T_393) @[lib.scala 88:36] + node _T_395 = and(_T_394, _T_318) @[lib.scala 88:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] + node _T_397 = bits(lsu_match_data_1, 11, 11) @[lib.scala 88:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 88:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 88:23] + _T_315[11] <= _T_399 @[lib.scala 88:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] + node _T_401 = andr(_T_400) @[lib.scala 88:36] + node _T_402 = and(_T_401, _T_318) @[lib.scala 88:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] + node _T_404 = bits(lsu_match_data_1, 12, 12) @[lib.scala 88:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 88:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 88:23] + _T_315[12] <= _T_406 @[lib.scala 88:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] + node _T_408 = andr(_T_407) @[lib.scala 88:36] + node _T_409 = and(_T_408, _T_318) @[lib.scala 88:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] + node _T_411 = bits(lsu_match_data_1, 13, 13) @[lib.scala 88:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 88:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 88:23] + _T_315[13] <= _T_413 @[lib.scala 88:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] + node _T_415 = andr(_T_414) @[lib.scala 88:36] + node _T_416 = and(_T_415, _T_318) @[lib.scala 88:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] + node _T_418 = bits(lsu_match_data_1, 14, 14) @[lib.scala 88:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 88:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 88:23] + _T_315[14] <= _T_420 @[lib.scala 88:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] + node _T_422 = andr(_T_421) @[lib.scala 88:36] + node _T_423 = and(_T_422, _T_318) @[lib.scala 88:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] + node _T_425 = bits(lsu_match_data_1, 15, 15) @[lib.scala 88:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 88:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 88:23] + _T_315[15] <= _T_427 @[lib.scala 88:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] + node _T_429 = andr(_T_428) @[lib.scala 88:36] + node _T_430 = and(_T_429, _T_318) @[lib.scala 88:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] + node _T_432 = bits(lsu_match_data_1, 16, 16) @[lib.scala 88:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 88:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 88:23] + _T_315[16] <= _T_434 @[lib.scala 88:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] + node _T_436 = andr(_T_435) @[lib.scala 88:36] + node _T_437 = and(_T_436, _T_318) @[lib.scala 88:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] + node _T_439 = bits(lsu_match_data_1, 17, 17) @[lib.scala 88:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 88:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 88:23] + _T_315[17] <= _T_441 @[lib.scala 88:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] + node _T_443 = andr(_T_442) @[lib.scala 88:36] + node _T_444 = and(_T_443, _T_318) @[lib.scala 88:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] + node _T_446 = bits(lsu_match_data_1, 18, 18) @[lib.scala 88:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 88:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 88:23] + _T_315[18] <= _T_448 @[lib.scala 88:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] + node _T_450 = andr(_T_449) @[lib.scala 88:36] + node _T_451 = and(_T_450, _T_318) @[lib.scala 88:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] + node _T_453 = bits(lsu_match_data_1, 19, 19) @[lib.scala 88:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 88:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 88:23] + _T_315[19] <= _T_455 @[lib.scala 88:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] + node _T_457 = andr(_T_456) @[lib.scala 88:36] + node _T_458 = and(_T_457, _T_318) @[lib.scala 88:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] + node _T_460 = bits(lsu_match_data_1, 20, 20) @[lib.scala 88:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 88:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 88:23] + _T_315[20] <= _T_462 @[lib.scala 88:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] + node _T_464 = andr(_T_463) @[lib.scala 88:36] + node _T_465 = and(_T_464, _T_318) @[lib.scala 88:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] + node _T_467 = bits(lsu_match_data_1, 21, 21) @[lib.scala 88:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 88:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 88:23] + _T_315[21] <= _T_469 @[lib.scala 88:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] + node _T_471 = andr(_T_470) @[lib.scala 88:36] + node _T_472 = and(_T_471, _T_318) @[lib.scala 88:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] + node _T_474 = bits(lsu_match_data_1, 22, 22) @[lib.scala 88:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 88:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 88:23] + _T_315[22] <= _T_476 @[lib.scala 88:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] + node _T_478 = andr(_T_477) @[lib.scala 88:36] + node _T_479 = and(_T_478, _T_318) @[lib.scala 88:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] + node _T_481 = bits(lsu_match_data_1, 23, 23) @[lib.scala 88:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 88:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 88:23] + _T_315[23] <= _T_483 @[lib.scala 88:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] + node _T_485 = andr(_T_484) @[lib.scala 88:36] + node _T_486 = and(_T_485, _T_318) @[lib.scala 88:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] + node _T_488 = bits(lsu_match_data_1, 24, 24) @[lib.scala 88:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 88:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 88:23] + _T_315[24] <= _T_490 @[lib.scala 88:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] + node _T_492 = andr(_T_491) @[lib.scala 88:36] + node _T_493 = and(_T_492, _T_318) @[lib.scala 88:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] + node _T_495 = bits(lsu_match_data_1, 25, 25) @[lib.scala 88:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 88:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 88:23] + _T_315[25] <= _T_497 @[lib.scala 88:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] + node _T_499 = andr(_T_498) @[lib.scala 88:36] + node _T_500 = and(_T_499, _T_318) @[lib.scala 88:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] + node _T_502 = bits(lsu_match_data_1, 26, 26) @[lib.scala 88:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 88:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 88:23] + _T_315[26] <= _T_504 @[lib.scala 88:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] + node _T_506 = andr(_T_505) @[lib.scala 88:36] + node _T_507 = and(_T_506, _T_318) @[lib.scala 88:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] + node _T_509 = bits(lsu_match_data_1, 27, 27) @[lib.scala 88:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 88:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 88:23] + _T_315[27] <= _T_511 @[lib.scala 88:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] + node _T_513 = andr(_T_512) @[lib.scala 88:36] + node _T_514 = and(_T_513, _T_318) @[lib.scala 88:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] + node _T_516 = bits(lsu_match_data_1, 28, 28) @[lib.scala 88:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 88:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 88:23] + _T_315[28] <= _T_518 @[lib.scala 88:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] + node _T_520 = andr(_T_519) @[lib.scala 88:36] + node _T_521 = and(_T_520, _T_318) @[lib.scala 88:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] + node _T_523 = bits(lsu_match_data_1, 29, 29) @[lib.scala 88:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 88:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 88:23] + _T_315[29] <= _T_525 @[lib.scala 88:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] + node _T_527 = andr(_T_526) @[lib.scala 88:36] + node _T_528 = and(_T_527, _T_318) @[lib.scala 88:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] + node _T_530 = bits(lsu_match_data_1, 30, 30) @[lib.scala 88:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 88:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 88:23] + _T_315[30] <= _T_532 @[lib.scala 88:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] + node _T_534 = andr(_T_533) @[lib.scala 88:36] + node _T_535 = and(_T_534, _T_318) @[lib.scala 88:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] + node _T_537 = bits(lsu_match_data_1, 31, 31) @[lib.scala 88:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 88:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 88:23] + _T_315[31] <= _T_539 @[lib.scala 88:17] + node _T_540 = cat(_T_315[1], _T_315[0]) @[lib.scala 89:14] + node _T_541 = cat(_T_315[3], _T_315[2]) @[lib.scala 89:14] + node _T_542 = cat(_T_541, _T_540) @[lib.scala 89:14] + node _T_543 = cat(_T_315[5], _T_315[4]) @[lib.scala 89:14] + node _T_544 = cat(_T_315[7], _T_315[6]) @[lib.scala 89:14] + node _T_545 = cat(_T_544, _T_543) @[lib.scala 89:14] + node _T_546 = cat(_T_545, _T_542) @[lib.scala 89:14] + node _T_547 = cat(_T_315[9], _T_315[8]) @[lib.scala 89:14] + node _T_548 = cat(_T_315[11], _T_315[10]) @[lib.scala 89:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 89:14] + node _T_550 = cat(_T_315[13], _T_315[12]) @[lib.scala 89:14] + node _T_551 = cat(_T_315[15], _T_315[14]) @[lib.scala 89:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 89:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 89:14] + node _T_554 = cat(_T_553, _T_546) @[lib.scala 89:14] + node _T_555 = cat(_T_315[17], _T_315[16]) @[lib.scala 89:14] + node _T_556 = cat(_T_315[19], _T_315[18]) @[lib.scala 89:14] + node _T_557 = cat(_T_556, _T_555) @[lib.scala 89:14] + node _T_558 = cat(_T_315[21], _T_315[20]) @[lib.scala 89:14] + node _T_559 = cat(_T_315[23], _T_315[22]) @[lib.scala 89:14] + node _T_560 = cat(_T_559, _T_558) @[lib.scala 89:14] + node _T_561 = cat(_T_560, _T_557) @[lib.scala 89:14] + node _T_562 = cat(_T_315[25], _T_315[24]) @[lib.scala 89:14] + node _T_563 = cat(_T_315[27], _T_315[26]) @[lib.scala 89:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 89:14] + node _T_565 = cat(_T_315[29], _T_315[28]) @[lib.scala 89:14] + node _T_566 = cat(_T_315[31], _T_315[30]) @[lib.scala 89:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 89:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 89:14] + node _T_569 = cat(_T_568, _T_561) @[lib.scala 89:14] + node _T_570 = cat(_T_569, _T_554) @[lib.scala 89:14] + node _T_571 = andr(_T_570) @[lib.scala 89:25] + node _T_572 = and(_T_313, _T_571) @[lsu_trigger.scala 19:92] + node _T_573 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_574 = and(io.lsu_pkt_m.valid, _T_573) @[lsu_trigger.scala 18:69] + node _T_575 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_576 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_577 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_578 = and(_T_576, _T_577) @[lsu_trigger.scala 19:58] + node _T_579 = or(_T_575, _T_578) @[lsu_trigger.scala 18:152] + node _T_580 = and(_T_574, _T_579) @[lsu_trigger.scala 18:94] + node _T_581 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_582 : UInt<1>[32] @[lib.scala 84:24] + node _T_583 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] + node _T_584 = not(_T_583) @[lib.scala 85:39] + node _T_585 = and(_T_581, _T_584) @[lib.scala 85:37] + node _T_586 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] + node _T_587 = bits(lsu_match_data_2, 0, 0) @[lib.scala 86:60] + node _T_588 = eq(_T_586, _T_587) @[lib.scala 86:52] + node _T_589 = or(_T_585, _T_588) @[lib.scala 86:41] + _T_582[0] <= _T_589 @[lib.scala 86:18] + node _T_590 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] + node _T_591 = andr(_T_590) @[lib.scala 88:36] + node _T_592 = and(_T_591, _T_585) @[lib.scala 88:41] + node _T_593 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] + node _T_594 = bits(lsu_match_data_2, 1, 1) @[lib.scala 88:86] + node _T_595 = eq(_T_593, _T_594) @[lib.scala 88:78] + node _T_596 = mux(_T_592, UInt<1>("h01"), _T_595) @[lib.scala 88:23] + _T_582[1] <= _T_596 @[lib.scala 88:17] + node _T_597 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] + node _T_598 = andr(_T_597) @[lib.scala 88:36] + node _T_599 = and(_T_598, _T_585) @[lib.scala 88:41] + node _T_600 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] + node _T_601 = bits(lsu_match_data_2, 2, 2) @[lib.scala 88:86] + node _T_602 = eq(_T_600, _T_601) @[lib.scala 88:78] + node _T_603 = mux(_T_599, UInt<1>("h01"), _T_602) @[lib.scala 88:23] + _T_582[2] <= _T_603 @[lib.scala 88:17] + node _T_604 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] + node _T_605 = andr(_T_604) @[lib.scala 88:36] + node _T_606 = and(_T_605, _T_585) @[lib.scala 88:41] + node _T_607 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] + node _T_608 = bits(lsu_match_data_2, 3, 3) @[lib.scala 88:86] + node _T_609 = eq(_T_607, _T_608) @[lib.scala 88:78] + node _T_610 = mux(_T_606, UInt<1>("h01"), _T_609) @[lib.scala 88:23] + _T_582[3] <= _T_610 @[lib.scala 88:17] + node _T_611 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] + node _T_612 = andr(_T_611) @[lib.scala 88:36] + node _T_613 = and(_T_612, _T_585) @[lib.scala 88:41] + node _T_614 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] + node _T_615 = bits(lsu_match_data_2, 4, 4) @[lib.scala 88:86] + node _T_616 = eq(_T_614, _T_615) @[lib.scala 88:78] + node _T_617 = mux(_T_613, UInt<1>("h01"), _T_616) @[lib.scala 88:23] + _T_582[4] <= _T_617 @[lib.scala 88:17] + node _T_618 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] + node _T_619 = andr(_T_618) @[lib.scala 88:36] + node _T_620 = and(_T_619, _T_585) @[lib.scala 88:41] + node _T_621 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] + node _T_622 = bits(lsu_match_data_2, 5, 5) @[lib.scala 88:86] + node _T_623 = eq(_T_621, _T_622) @[lib.scala 88:78] + node _T_624 = mux(_T_620, UInt<1>("h01"), _T_623) @[lib.scala 88:23] + _T_582[5] <= _T_624 @[lib.scala 88:17] + node _T_625 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] + node _T_626 = andr(_T_625) @[lib.scala 88:36] + node _T_627 = and(_T_626, _T_585) @[lib.scala 88:41] + node _T_628 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] + node _T_629 = bits(lsu_match_data_2, 6, 6) @[lib.scala 88:86] + node _T_630 = eq(_T_628, _T_629) @[lib.scala 88:78] + node _T_631 = mux(_T_627, UInt<1>("h01"), _T_630) @[lib.scala 88:23] + _T_582[6] <= _T_631 @[lib.scala 88:17] + node _T_632 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] + node _T_633 = andr(_T_632) @[lib.scala 88:36] + node _T_634 = and(_T_633, _T_585) @[lib.scala 88:41] + node _T_635 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] + node _T_636 = bits(lsu_match_data_2, 7, 7) @[lib.scala 88:86] + node _T_637 = eq(_T_635, _T_636) @[lib.scala 88:78] + node _T_638 = mux(_T_634, UInt<1>("h01"), _T_637) @[lib.scala 88:23] + _T_582[7] <= _T_638 @[lib.scala 88:17] + node _T_639 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] + node _T_640 = andr(_T_639) @[lib.scala 88:36] + node _T_641 = and(_T_640, _T_585) @[lib.scala 88:41] + node _T_642 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] + node _T_643 = bits(lsu_match_data_2, 8, 8) @[lib.scala 88:86] + node _T_644 = eq(_T_642, _T_643) @[lib.scala 88:78] + node _T_645 = mux(_T_641, UInt<1>("h01"), _T_644) @[lib.scala 88:23] + _T_582[8] <= _T_645 @[lib.scala 88:17] + node _T_646 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] + node _T_647 = andr(_T_646) @[lib.scala 88:36] + node _T_648 = and(_T_647, _T_585) @[lib.scala 88:41] + node _T_649 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] + node _T_650 = bits(lsu_match_data_2, 9, 9) @[lib.scala 88:86] + node _T_651 = eq(_T_649, _T_650) @[lib.scala 88:78] + node _T_652 = mux(_T_648, UInt<1>("h01"), _T_651) @[lib.scala 88:23] + _T_582[9] <= _T_652 @[lib.scala 88:17] + node _T_653 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] + node _T_654 = andr(_T_653) @[lib.scala 88:36] + node _T_655 = and(_T_654, _T_585) @[lib.scala 88:41] + node _T_656 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] + node _T_657 = bits(lsu_match_data_2, 10, 10) @[lib.scala 88:86] + node _T_658 = eq(_T_656, _T_657) @[lib.scala 88:78] + node _T_659 = mux(_T_655, UInt<1>("h01"), _T_658) @[lib.scala 88:23] + _T_582[10] <= _T_659 @[lib.scala 88:17] + node _T_660 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] + node _T_661 = andr(_T_660) @[lib.scala 88:36] + node _T_662 = and(_T_661, _T_585) @[lib.scala 88:41] + node _T_663 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] + node _T_664 = bits(lsu_match_data_2, 11, 11) @[lib.scala 88:86] + node _T_665 = eq(_T_663, _T_664) @[lib.scala 88:78] + node _T_666 = mux(_T_662, UInt<1>("h01"), _T_665) @[lib.scala 88:23] + _T_582[11] <= _T_666 @[lib.scala 88:17] + node _T_667 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] + node _T_668 = andr(_T_667) @[lib.scala 88:36] + node _T_669 = and(_T_668, _T_585) @[lib.scala 88:41] + node _T_670 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] + node _T_671 = bits(lsu_match_data_2, 12, 12) @[lib.scala 88:86] + node _T_672 = eq(_T_670, _T_671) @[lib.scala 88:78] + node _T_673 = mux(_T_669, UInt<1>("h01"), _T_672) @[lib.scala 88:23] + _T_582[12] <= _T_673 @[lib.scala 88:17] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] + node _T_675 = andr(_T_674) @[lib.scala 88:36] + node _T_676 = and(_T_675, _T_585) @[lib.scala 88:41] + node _T_677 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] + node _T_678 = bits(lsu_match_data_2, 13, 13) @[lib.scala 88:86] + node _T_679 = eq(_T_677, _T_678) @[lib.scala 88:78] + node _T_680 = mux(_T_676, UInt<1>("h01"), _T_679) @[lib.scala 88:23] + _T_582[13] <= _T_680 @[lib.scala 88:17] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] + node _T_682 = andr(_T_681) @[lib.scala 88:36] + node _T_683 = and(_T_682, _T_585) @[lib.scala 88:41] + node _T_684 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] + node _T_685 = bits(lsu_match_data_2, 14, 14) @[lib.scala 88:86] + node _T_686 = eq(_T_684, _T_685) @[lib.scala 88:78] + node _T_687 = mux(_T_683, UInt<1>("h01"), _T_686) @[lib.scala 88:23] + _T_582[14] <= _T_687 @[lib.scala 88:17] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] + node _T_689 = andr(_T_688) @[lib.scala 88:36] + node _T_690 = and(_T_689, _T_585) @[lib.scala 88:41] + node _T_691 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] + node _T_692 = bits(lsu_match_data_2, 15, 15) @[lib.scala 88:86] + node _T_693 = eq(_T_691, _T_692) @[lib.scala 88:78] + node _T_694 = mux(_T_690, UInt<1>("h01"), _T_693) @[lib.scala 88:23] + _T_582[15] <= _T_694 @[lib.scala 88:17] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] + node _T_696 = andr(_T_695) @[lib.scala 88:36] + node _T_697 = and(_T_696, _T_585) @[lib.scala 88:41] + node _T_698 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] + node _T_699 = bits(lsu_match_data_2, 16, 16) @[lib.scala 88:86] + node _T_700 = eq(_T_698, _T_699) @[lib.scala 88:78] + node _T_701 = mux(_T_697, UInt<1>("h01"), _T_700) @[lib.scala 88:23] + _T_582[16] <= _T_701 @[lib.scala 88:17] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] + node _T_703 = andr(_T_702) @[lib.scala 88:36] + node _T_704 = and(_T_703, _T_585) @[lib.scala 88:41] + node _T_705 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] + node _T_706 = bits(lsu_match_data_2, 17, 17) @[lib.scala 88:86] + node _T_707 = eq(_T_705, _T_706) @[lib.scala 88:78] + node _T_708 = mux(_T_704, UInt<1>("h01"), _T_707) @[lib.scala 88:23] + _T_582[17] <= _T_708 @[lib.scala 88:17] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] + node _T_710 = andr(_T_709) @[lib.scala 88:36] + node _T_711 = and(_T_710, _T_585) @[lib.scala 88:41] + node _T_712 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] + node _T_713 = bits(lsu_match_data_2, 18, 18) @[lib.scala 88:86] + node _T_714 = eq(_T_712, _T_713) @[lib.scala 88:78] + node _T_715 = mux(_T_711, UInt<1>("h01"), _T_714) @[lib.scala 88:23] + _T_582[18] <= _T_715 @[lib.scala 88:17] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] + node _T_717 = andr(_T_716) @[lib.scala 88:36] + node _T_718 = and(_T_717, _T_585) @[lib.scala 88:41] + node _T_719 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] + node _T_720 = bits(lsu_match_data_2, 19, 19) @[lib.scala 88:86] + node _T_721 = eq(_T_719, _T_720) @[lib.scala 88:78] + node _T_722 = mux(_T_718, UInt<1>("h01"), _T_721) @[lib.scala 88:23] + _T_582[19] <= _T_722 @[lib.scala 88:17] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] + node _T_724 = andr(_T_723) @[lib.scala 88:36] + node _T_725 = and(_T_724, _T_585) @[lib.scala 88:41] + node _T_726 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] + node _T_727 = bits(lsu_match_data_2, 20, 20) @[lib.scala 88:86] + node _T_728 = eq(_T_726, _T_727) @[lib.scala 88:78] + node _T_729 = mux(_T_725, UInt<1>("h01"), _T_728) @[lib.scala 88:23] + _T_582[20] <= _T_729 @[lib.scala 88:17] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] + node _T_731 = andr(_T_730) @[lib.scala 88:36] + node _T_732 = and(_T_731, _T_585) @[lib.scala 88:41] + node _T_733 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] + node _T_734 = bits(lsu_match_data_2, 21, 21) @[lib.scala 88:86] + node _T_735 = eq(_T_733, _T_734) @[lib.scala 88:78] + node _T_736 = mux(_T_732, UInt<1>("h01"), _T_735) @[lib.scala 88:23] + _T_582[21] <= _T_736 @[lib.scala 88:17] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] + node _T_738 = andr(_T_737) @[lib.scala 88:36] + node _T_739 = and(_T_738, _T_585) @[lib.scala 88:41] + node _T_740 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] + node _T_741 = bits(lsu_match_data_2, 22, 22) @[lib.scala 88:86] + node _T_742 = eq(_T_740, _T_741) @[lib.scala 88:78] + node _T_743 = mux(_T_739, UInt<1>("h01"), _T_742) @[lib.scala 88:23] + _T_582[22] <= _T_743 @[lib.scala 88:17] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] + node _T_745 = andr(_T_744) @[lib.scala 88:36] + node _T_746 = and(_T_745, _T_585) @[lib.scala 88:41] + node _T_747 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] + node _T_748 = bits(lsu_match_data_2, 23, 23) @[lib.scala 88:86] + node _T_749 = eq(_T_747, _T_748) @[lib.scala 88:78] + node _T_750 = mux(_T_746, UInt<1>("h01"), _T_749) @[lib.scala 88:23] + _T_582[23] <= _T_750 @[lib.scala 88:17] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] + node _T_752 = andr(_T_751) @[lib.scala 88:36] + node _T_753 = and(_T_752, _T_585) @[lib.scala 88:41] + node _T_754 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] + node _T_755 = bits(lsu_match_data_2, 24, 24) @[lib.scala 88:86] + node _T_756 = eq(_T_754, _T_755) @[lib.scala 88:78] + node _T_757 = mux(_T_753, UInt<1>("h01"), _T_756) @[lib.scala 88:23] + _T_582[24] <= _T_757 @[lib.scala 88:17] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] + node _T_759 = andr(_T_758) @[lib.scala 88:36] + node _T_760 = and(_T_759, _T_585) @[lib.scala 88:41] + node _T_761 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] + node _T_762 = bits(lsu_match_data_2, 25, 25) @[lib.scala 88:86] + node _T_763 = eq(_T_761, _T_762) @[lib.scala 88:78] + node _T_764 = mux(_T_760, UInt<1>("h01"), _T_763) @[lib.scala 88:23] + _T_582[25] <= _T_764 @[lib.scala 88:17] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] + node _T_766 = andr(_T_765) @[lib.scala 88:36] + node _T_767 = and(_T_766, _T_585) @[lib.scala 88:41] + node _T_768 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] + node _T_769 = bits(lsu_match_data_2, 26, 26) @[lib.scala 88:86] + node _T_770 = eq(_T_768, _T_769) @[lib.scala 88:78] + node _T_771 = mux(_T_767, UInt<1>("h01"), _T_770) @[lib.scala 88:23] + _T_582[26] <= _T_771 @[lib.scala 88:17] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] + node _T_773 = andr(_T_772) @[lib.scala 88:36] + node _T_774 = and(_T_773, _T_585) @[lib.scala 88:41] + node _T_775 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] + node _T_776 = bits(lsu_match_data_2, 27, 27) @[lib.scala 88:86] + node _T_777 = eq(_T_775, _T_776) @[lib.scala 88:78] + node _T_778 = mux(_T_774, UInt<1>("h01"), _T_777) @[lib.scala 88:23] + _T_582[27] <= _T_778 @[lib.scala 88:17] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] + node _T_780 = andr(_T_779) @[lib.scala 88:36] + node _T_781 = and(_T_780, _T_585) @[lib.scala 88:41] + node _T_782 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] + node _T_783 = bits(lsu_match_data_2, 28, 28) @[lib.scala 88:86] + node _T_784 = eq(_T_782, _T_783) @[lib.scala 88:78] + node _T_785 = mux(_T_781, UInt<1>("h01"), _T_784) @[lib.scala 88:23] + _T_582[28] <= _T_785 @[lib.scala 88:17] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] + node _T_787 = andr(_T_786) @[lib.scala 88:36] + node _T_788 = and(_T_787, _T_585) @[lib.scala 88:41] + node _T_789 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] + node _T_790 = bits(lsu_match_data_2, 29, 29) @[lib.scala 88:86] + node _T_791 = eq(_T_789, _T_790) @[lib.scala 88:78] + node _T_792 = mux(_T_788, UInt<1>("h01"), _T_791) @[lib.scala 88:23] + _T_582[29] <= _T_792 @[lib.scala 88:17] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] + node _T_794 = andr(_T_793) @[lib.scala 88:36] + node _T_795 = and(_T_794, _T_585) @[lib.scala 88:41] + node _T_796 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] + node _T_797 = bits(lsu_match_data_2, 30, 30) @[lib.scala 88:86] + node _T_798 = eq(_T_796, _T_797) @[lib.scala 88:78] + node _T_799 = mux(_T_795, UInt<1>("h01"), _T_798) @[lib.scala 88:23] + _T_582[30] <= _T_799 @[lib.scala 88:17] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] + node _T_801 = andr(_T_800) @[lib.scala 88:36] + node _T_802 = and(_T_801, _T_585) @[lib.scala 88:41] + node _T_803 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] + node _T_804 = bits(lsu_match_data_2, 31, 31) @[lib.scala 88:86] + node _T_805 = eq(_T_803, _T_804) @[lib.scala 88:78] + node _T_806 = mux(_T_802, UInt<1>("h01"), _T_805) @[lib.scala 88:23] + _T_582[31] <= _T_806 @[lib.scala 88:17] + node _T_807 = cat(_T_582[1], _T_582[0]) @[lib.scala 89:14] + node _T_808 = cat(_T_582[3], _T_582[2]) @[lib.scala 89:14] + node _T_809 = cat(_T_808, _T_807) @[lib.scala 89:14] + node _T_810 = cat(_T_582[5], _T_582[4]) @[lib.scala 89:14] + node _T_811 = cat(_T_582[7], _T_582[6]) @[lib.scala 89:14] + node _T_812 = cat(_T_811, _T_810) @[lib.scala 89:14] + node _T_813 = cat(_T_812, _T_809) @[lib.scala 89:14] + node _T_814 = cat(_T_582[9], _T_582[8]) @[lib.scala 89:14] + node _T_815 = cat(_T_582[11], _T_582[10]) @[lib.scala 89:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 89:14] + node _T_817 = cat(_T_582[13], _T_582[12]) @[lib.scala 89:14] + node _T_818 = cat(_T_582[15], _T_582[14]) @[lib.scala 89:14] + node _T_819 = cat(_T_818, _T_817) @[lib.scala 89:14] + node _T_820 = cat(_T_819, _T_816) @[lib.scala 89:14] + node _T_821 = cat(_T_820, _T_813) @[lib.scala 89:14] + node _T_822 = cat(_T_582[17], _T_582[16]) @[lib.scala 89:14] + node _T_823 = cat(_T_582[19], _T_582[18]) @[lib.scala 89:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 89:14] + node _T_825 = cat(_T_582[21], _T_582[20]) @[lib.scala 89:14] + node _T_826 = cat(_T_582[23], _T_582[22]) @[lib.scala 89:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 89:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 89:14] + node _T_829 = cat(_T_582[25], _T_582[24]) @[lib.scala 89:14] + node _T_830 = cat(_T_582[27], _T_582[26]) @[lib.scala 89:14] + node _T_831 = cat(_T_830, _T_829) @[lib.scala 89:14] + node _T_832 = cat(_T_582[29], _T_582[28]) @[lib.scala 89:14] + node _T_833 = cat(_T_582[31], _T_582[30]) @[lib.scala 89:14] + node _T_834 = cat(_T_833, _T_832) @[lib.scala 89:14] + node _T_835 = cat(_T_834, _T_831) @[lib.scala 89:14] + node _T_836 = cat(_T_835, _T_828) @[lib.scala 89:14] + node _T_837 = cat(_T_836, _T_821) @[lib.scala 89:14] + node _T_838 = andr(_T_837) @[lib.scala 89:25] + node _T_839 = and(_T_580, _T_838) @[lsu_trigger.scala 19:92] + node _T_840 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_841 = and(io.lsu_pkt_m.valid, _T_840) @[lsu_trigger.scala 18:69] + node _T_842 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_843 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_844 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_845 = and(_T_843, _T_844) @[lsu_trigger.scala 19:58] + node _T_846 = or(_T_842, _T_845) @[lsu_trigger.scala 18:152] + node _T_847 = and(_T_841, _T_846) @[lsu_trigger.scala 18:94] + node _T_848 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_849 : UInt<1>[32] @[lib.scala 84:24] + node _T_850 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] + node _T_851 = not(_T_850) @[lib.scala 85:39] + node _T_852 = and(_T_848, _T_851) @[lib.scala 85:37] + node _T_853 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] + node _T_854 = bits(lsu_match_data_3, 0, 0) @[lib.scala 86:60] + node _T_855 = eq(_T_853, _T_854) @[lib.scala 86:52] + node _T_856 = or(_T_852, _T_855) @[lib.scala 86:41] + _T_849[0] <= _T_856 @[lib.scala 86:18] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] + node _T_858 = andr(_T_857) @[lib.scala 88:36] + node _T_859 = and(_T_858, _T_852) @[lib.scala 88:41] + node _T_860 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] + node _T_861 = bits(lsu_match_data_3, 1, 1) @[lib.scala 88:86] + node _T_862 = eq(_T_860, _T_861) @[lib.scala 88:78] + node _T_863 = mux(_T_859, UInt<1>("h01"), _T_862) @[lib.scala 88:23] + _T_849[1] <= _T_863 @[lib.scala 88:17] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] + node _T_865 = andr(_T_864) @[lib.scala 88:36] + node _T_866 = and(_T_865, _T_852) @[lib.scala 88:41] + node _T_867 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] + node _T_868 = bits(lsu_match_data_3, 2, 2) @[lib.scala 88:86] + node _T_869 = eq(_T_867, _T_868) @[lib.scala 88:78] + node _T_870 = mux(_T_866, UInt<1>("h01"), _T_869) @[lib.scala 88:23] + _T_849[2] <= _T_870 @[lib.scala 88:17] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] + node _T_872 = andr(_T_871) @[lib.scala 88:36] + node _T_873 = and(_T_872, _T_852) @[lib.scala 88:41] + node _T_874 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] + node _T_875 = bits(lsu_match_data_3, 3, 3) @[lib.scala 88:86] + node _T_876 = eq(_T_874, _T_875) @[lib.scala 88:78] + node _T_877 = mux(_T_873, UInt<1>("h01"), _T_876) @[lib.scala 88:23] + _T_849[3] <= _T_877 @[lib.scala 88:17] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] + node _T_879 = andr(_T_878) @[lib.scala 88:36] + node _T_880 = and(_T_879, _T_852) @[lib.scala 88:41] + node _T_881 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] + node _T_882 = bits(lsu_match_data_3, 4, 4) @[lib.scala 88:86] + node _T_883 = eq(_T_881, _T_882) @[lib.scala 88:78] + node _T_884 = mux(_T_880, UInt<1>("h01"), _T_883) @[lib.scala 88:23] + _T_849[4] <= _T_884 @[lib.scala 88:17] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] + node _T_886 = andr(_T_885) @[lib.scala 88:36] + node _T_887 = and(_T_886, _T_852) @[lib.scala 88:41] + node _T_888 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] + node _T_889 = bits(lsu_match_data_3, 5, 5) @[lib.scala 88:86] + node _T_890 = eq(_T_888, _T_889) @[lib.scala 88:78] + node _T_891 = mux(_T_887, UInt<1>("h01"), _T_890) @[lib.scala 88:23] + _T_849[5] <= _T_891 @[lib.scala 88:17] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] + node _T_893 = andr(_T_892) @[lib.scala 88:36] + node _T_894 = and(_T_893, _T_852) @[lib.scala 88:41] + node _T_895 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] + node _T_896 = bits(lsu_match_data_3, 6, 6) @[lib.scala 88:86] + node _T_897 = eq(_T_895, _T_896) @[lib.scala 88:78] + node _T_898 = mux(_T_894, UInt<1>("h01"), _T_897) @[lib.scala 88:23] + _T_849[6] <= _T_898 @[lib.scala 88:17] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] + node _T_900 = andr(_T_899) @[lib.scala 88:36] + node _T_901 = and(_T_900, _T_852) @[lib.scala 88:41] + node _T_902 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] + node _T_903 = bits(lsu_match_data_3, 7, 7) @[lib.scala 88:86] + node _T_904 = eq(_T_902, _T_903) @[lib.scala 88:78] + node _T_905 = mux(_T_901, UInt<1>("h01"), _T_904) @[lib.scala 88:23] + _T_849[7] <= _T_905 @[lib.scala 88:17] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] + node _T_907 = andr(_T_906) @[lib.scala 88:36] + node _T_908 = and(_T_907, _T_852) @[lib.scala 88:41] + node _T_909 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] + node _T_910 = bits(lsu_match_data_3, 8, 8) @[lib.scala 88:86] + node _T_911 = eq(_T_909, _T_910) @[lib.scala 88:78] + node _T_912 = mux(_T_908, UInt<1>("h01"), _T_911) @[lib.scala 88:23] + _T_849[8] <= _T_912 @[lib.scala 88:17] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] + node _T_914 = andr(_T_913) @[lib.scala 88:36] + node _T_915 = and(_T_914, _T_852) @[lib.scala 88:41] + node _T_916 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] + node _T_917 = bits(lsu_match_data_3, 9, 9) @[lib.scala 88:86] + node _T_918 = eq(_T_916, _T_917) @[lib.scala 88:78] + node _T_919 = mux(_T_915, UInt<1>("h01"), _T_918) @[lib.scala 88:23] + _T_849[9] <= _T_919 @[lib.scala 88:17] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] + node _T_921 = andr(_T_920) @[lib.scala 88:36] + node _T_922 = and(_T_921, _T_852) @[lib.scala 88:41] + node _T_923 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] + node _T_924 = bits(lsu_match_data_3, 10, 10) @[lib.scala 88:86] + node _T_925 = eq(_T_923, _T_924) @[lib.scala 88:78] + node _T_926 = mux(_T_922, UInt<1>("h01"), _T_925) @[lib.scala 88:23] + _T_849[10] <= _T_926 @[lib.scala 88:17] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] + node _T_928 = andr(_T_927) @[lib.scala 88:36] + node _T_929 = and(_T_928, _T_852) @[lib.scala 88:41] + node _T_930 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] + node _T_931 = bits(lsu_match_data_3, 11, 11) @[lib.scala 88:86] + node _T_932 = eq(_T_930, _T_931) @[lib.scala 88:78] + node _T_933 = mux(_T_929, UInt<1>("h01"), _T_932) @[lib.scala 88:23] + _T_849[11] <= _T_933 @[lib.scala 88:17] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] + node _T_935 = andr(_T_934) @[lib.scala 88:36] + node _T_936 = and(_T_935, _T_852) @[lib.scala 88:41] + node _T_937 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] + node _T_938 = bits(lsu_match_data_3, 12, 12) @[lib.scala 88:86] + node _T_939 = eq(_T_937, _T_938) @[lib.scala 88:78] + node _T_940 = mux(_T_936, UInt<1>("h01"), _T_939) @[lib.scala 88:23] + _T_849[12] <= _T_940 @[lib.scala 88:17] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] + node _T_942 = andr(_T_941) @[lib.scala 88:36] + node _T_943 = and(_T_942, _T_852) @[lib.scala 88:41] + node _T_944 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] + node _T_945 = bits(lsu_match_data_3, 13, 13) @[lib.scala 88:86] + node _T_946 = eq(_T_944, _T_945) @[lib.scala 88:78] + node _T_947 = mux(_T_943, UInt<1>("h01"), _T_946) @[lib.scala 88:23] + _T_849[13] <= _T_947 @[lib.scala 88:17] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] + node _T_949 = andr(_T_948) @[lib.scala 88:36] + node _T_950 = and(_T_949, _T_852) @[lib.scala 88:41] + node _T_951 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] + node _T_952 = bits(lsu_match_data_3, 14, 14) @[lib.scala 88:86] + node _T_953 = eq(_T_951, _T_952) @[lib.scala 88:78] + node _T_954 = mux(_T_950, UInt<1>("h01"), _T_953) @[lib.scala 88:23] + _T_849[14] <= _T_954 @[lib.scala 88:17] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] + node _T_956 = andr(_T_955) @[lib.scala 88:36] + node _T_957 = and(_T_956, _T_852) @[lib.scala 88:41] + node _T_958 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] + node _T_959 = bits(lsu_match_data_3, 15, 15) @[lib.scala 88:86] + node _T_960 = eq(_T_958, _T_959) @[lib.scala 88:78] + node _T_961 = mux(_T_957, UInt<1>("h01"), _T_960) @[lib.scala 88:23] + _T_849[15] <= _T_961 @[lib.scala 88:17] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] + node _T_963 = andr(_T_962) @[lib.scala 88:36] + node _T_964 = and(_T_963, _T_852) @[lib.scala 88:41] + node _T_965 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] + node _T_966 = bits(lsu_match_data_3, 16, 16) @[lib.scala 88:86] + node _T_967 = eq(_T_965, _T_966) @[lib.scala 88:78] + node _T_968 = mux(_T_964, UInt<1>("h01"), _T_967) @[lib.scala 88:23] + _T_849[16] <= _T_968 @[lib.scala 88:17] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] + node _T_970 = andr(_T_969) @[lib.scala 88:36] + node _T_971 = and(_T_970, _T_852) @[lib.scala 88:41] + node _T_972 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] + node _T_973 = bits(lsu_match_data_3, 17, 17) @[lib.scala 88:86] + node _T_974 = eq(_T_972, _T_973) @[lib.scala 88:78] + node _T_975 = mux(_T_971, UInt<1>("h01"), _T_974) @[lib.scala 88:23] + _T_849[17] <= _T_975 @[lib.scala 88:17] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] + node _T_977 = andr(_T_976) @[lib.scala 88:36] + node _T_978 = and(_T_977, _T_852) @[lib.scala 88:41] + node _T_979 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] + node _T_980 = bits(lsu_match_data_3, 18, 18) @[lib.scala 88:86] + node _T_981 = eq(_T_979, _T_980) @[lib.scala 88:78] + node _T_982 = mux(_T_978, UInt<1>("h01"), _T_981) @[lib.scala 88:23] + _T_849[18] <= _T_982 @[lib.scala 88:17] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] + node _T_984 = andr(_T_983) @[lib.scala 88:36] + node _T_985 = and(_T_984, _T_852) @[lib.scala 88:41] + node _T_986 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] + node _T_987 = bits(lsu_match_data_3, 19, 19) @[lib.scala 88:86] + node _T_988 = eq(_T_986, _T_987) @[lib.scala 88:78] + node _T_989 = mux(_T_985, UInt<1>("h01"), _T_988) @[lib.scala 88:23] + _T_849[19] <= _T_989 @[lib.scala 88:17] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] + node _T_991 = andr(_T_990) @[lib.scala 88:36] + node _T_992 = and(_T_991, _T_852) @[lib.scala 88:41] + node _T_993 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] + node _T_994 = bits(lsu_match_data_3, 20, 20) @[lib.scala 88:86] + node _T_995 = eq(_T_993, _T_994) @[lib.scala 88:78] + node _T_996 = mux(_T_992, UInt<1>("h01"), _T_995) @[lib.scala 88:23] + _T_849[20] <= _T_996 @[lib.scala 88:17] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] + node _T_998 = andr(_T_997) @[lib.scala 88:36] + node _T_999 = and(_T_998, _T_852) @[lib.scala 88:41] + node _T_1000 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] + node _T_1001 = bits(lsu_match_data_3, 21, 21) @[lib.scala 88:86] + node _T_1002 = eq(_T_1000, _T_1001) @[lib.scala 88:78] + node _T_1003 = mux(_T_999, UInt<1>("h01"), _T_1002) @[lib.scala 88:23] + _T_849[21] <= _T_1003 @[lib.scala 88:17] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] + node _T_1005 = andr(_T_1004) @[lib.scala 88:36] + node _T_1006 = and(_T_1005, _T_852) @[lib.scala 88:41] + node _T_1007 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] + node _T_1008 = bits(lsu_match_data_3, 22, 22) @[lib.scala 88:86] + node _T_1009 = eq(_T_1007, _T_1008) @[lib.scala 88:78] + node _T_1010 = mux(_T_1006, UInt<1>("h01"), _T_1009) @[lib.scala 88:23] + _T_849[22] <= _T_1010 @[lib.scala 88:17] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] + node _T_1012 = andr(_T_1011) @[lib.scala 88:36] + node _T_1013 = and(_T_1012, _T_852) @[lib.scala 88:41] + node _T_1014 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] + node _T_1015 = bits(lsu_match_data_3, 23, 23) @[lib.scala 88:86] + node _T_1016 = eq(_T_1014, _T_1015) @[lib.scala 88:78] + node _T_1017 = mux(_T_1013, UInt<1>("h01"), _T_1016) @[lib.scala 88:23] + _T_849[23] <= _T_1017 @[lib.scala 88:17] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] + node _T_1019 = andr(_T_1018) @[lib.scala 88:36] + node _T_1020 = and(_T_1019, _T_852) @[lib.scala 88:41] + node _T_1021 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] + node _T_1022 = bits(lsu_match_data_3, 24, 24) @[lib.scala 88:86] + node _T_1023 = eq(_T_1021, _T_1022) @[lib.scala 88:78] + node _T_1024 = mux(_T_1020, UInt<1>("h01"), _T_1023) @[lib.scala 88:23] + _T_849[24] <= _T_1024 @[lib.scala 88:17] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] + node _T_1026 = andr(_T_1025) @[lib.scala 88:36] + node _T_1027 = and(_T_1026, _T_852) @[lib.scala 88:41] + node _T_1028 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] + node _T_1029 = bits(lsu_match_data_3, 25, 25) @[lib.scala 88:86] + node _T_1030 = eq(_T_1028, _T_1029) @[lib.scala 88:78] + node _T_1031 = mux(_T_1027, UInt<1>("h01"), _T_1030) @[lib.scala 88:23] + _T_849[25] <= _T_1031 @[lib.scala 88:17] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] + node _T_1033 = andr(_T_1032) @[lib.scala 88:36] + node _T_1034 = and(_T_1033, _T_852) @[lib.scala 88:41] + node _T_1035 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] + node _T_1036 = bits(lsu_match_data_3, 26, 26) @[lib.scala 88:86] + node _T_1037 = eq(_T_1035, _T_1036) @[lib.scala 88:78] + node _T_1038 = mux(_T_1034, UInt<1>("h01"), _T_1037) @[lib.scala 88:23] + _T_849[26] <= _T_1038 @[lib.scala 88:17] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] + node _T_1040 = andr(_T_1039) @[lib.scala 88:36] + node _T_1041 = and(_T_1040, _T_852) @[lib.scala 88:41] + node _T_1042 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] + node _T_1043 = bits(lsu_match_data_3, 27, 27) @[lib.scala 88:86] + node _T_1044 = eq(_T_1042, _T_1043) @[lib.scala 88:78] + node _T_1045 = mux(_T_1041, UInt<1>("h01"), _T_1044) @[lib.scala 88:23] + _T_849[27] <= _T_1045 @[lib.scala 88:17] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] + node _T_1047 = andr(_T_1046) @[lib.scala 88:36] + node _T_1048 = and(_T_1047, _T_852) @[lib.scala 88:41] + node _T_1049 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] + node _T_1050 = bits(lsu_match_data_3, 28, 28) @[lib.scala 88:86] + node _T_1051 = eq(_T_1049, _T_1050) @[lib.scala 88:78] + node _T_1052 = mux(_T_1048, UInt<1>("h01"), _T_1051) @[lib.scala 88:23] + _T_849[28] <= _T_1052 @[lib.scala 88:17] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] + node _T_1054 = andr(_T_1053) @[lib.scala 88:36] + node _T_1055 = and(_T_1054, _T_852) @[lib.scala 88:41] + node _T_1056 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] + node _T_1057 = bits(lsu_match_data_3, 29, 29) @[lib.scala 88:86] + node _T_1058 = eq(_T_1056, _T_1057) @[lib.scala 88:78] + node _T_1059 = mux(_T_1055, UInt<1>("h01"), _T_1058) @[lib.scala 88:23] + _T_849[29] <= _T_1059 @[lib.scala 88:17] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] + node _T_1061 = andr(_T_1060) @[lib.scala 88:36] + node _T_1062 = and(_T_1061, _T_852) @[lib.scala 88:41] + node _T_1063 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] + node _T_1064 = bits(lsu_match_data_3, 30, 30) @[lib.scala 88:86] + node _T_1065 = eq(_T_1063, _T_1064) @[lib.scala 88:78] + node _T_1066 = mux(_T_1062, UInt<1>("h01"), _T_1065) @[lib.scala 88:23] + _T_849[30] <= _T_1066 @[lib.scala 88:17] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] + node _T_1068 = andr(_T_1067) @[lib.scala 88:36] + node _T_1069 = and(_T_1068, _T_852) @[lib.scala 88:41] + node _T_1070 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] + node _T_1071 = bits(lsu_match_data_3, 31, 31) @[lib.scala 88:86] + node _T_1072 = eq(_T_1070, _T_1071) @[lib.scala 88:78] + node _T_1073 = mux(_T_1069, UInt<1>("h01"), _T_1072) @[lib.scala 88:23] + _T_849[31] <= _T_1073 @[lib.scala 88:17] + node _T_1074 = cat(_T_849[1], _T_849[0]) @[lib.scala 89:14] + node _T_1075 = cat(_T_849[3], _T_849[2]) @[lib.scala 89:14] node _T_1076 = cat(_T_1075, _T_1074) @[lib.scala 89:14] - node _T_1077 = cat(_T_1076, _T_1073) @[lib.scala 89:14] - node _T_1078 = cat(_T_846[9], _T_846[8]) @[lib.scala 89:14] - node _T_1079 = cat(_T_846[11], _T_846[10]) @[lib.scala 89:14] - node _T_1080 = cat(_T_1079, _T_1078) @[lib.scala 89:14] - node _T_1081 = cat(_T_846[13], _T_846[12]) @[lib.scala 89:14] - node _T_1082 = cat(_T_846[15], _T_846[14]) @[lib.scala 89:14] + node _T_1077 = cat(_T_849[5], _T_849[4]) @[lib.scala 89:14] + node _T_1078 = cat(_T_849[7], _T_849[6]) @[lib.scala 89:14] + node _T_1079 = cat(_T_1078, _T_1077) @[lib.scala 89:14] + node _T_1080 = cat(_T_1079, _T_1076) @[lib.scala 89:14] + node _T_1081 = cat(_T_849[9], _T_849[8]) @[lib.scala 89:14] + node _T_1082 = cat(_T_849[11], _T_849[10]) @[lib.scala 89:14] node _T_1083 = cat(_T_1082, _T_1081) @[lib.scala 89:14] - node _T_1084 = cat(_T_1083, _T_1080) @[lib.scala 89:14] - node _T_1085 = cat(_T_1084, _T_1077) @[lib.scala 89:14] - node _T_1086 = cat(_T_846[17], _T_846[16]) @[lib.scala 89:14] - node _T_1087 = cat(_T_846[19], _T_846[18]) @[lib.scala 89:14] - node _T_1088 = cat(_T_1087, _T_1086) @[lib.scala 89:14] - node _T_1089 = cat(_T_846[21], _T_846[20]) @[lib.scala 89:14] - node _T_1090 = cat(_T_846[23], _T_846[22]) @[lib.scala 89:14] + node _T_1084 = cat(_T_849[13], _T_849[12]) @[lib.scala 89:14] + node _T_1085 = cat(_T_849[15], _T_849[14]) @[lib.scala 89:14] + node _T_1086 = cat(_T_1085, _T_1084) @[lib.scala 89:14] + node _T_1087 = cat(_T_1086, _T_1083) @[lib.scala 89:14] + node _T_1088 = cat(_T_1087, _T_1080) @[lib.scala 89:14] + node _T_1089 = cat(_T_849[17], _T_849[16]) @[lib.scala 89:14] + node _T_1090 = cat(_T_849[19], _T_849[18]) @[lib.scala 89:14] node _T_1091 = cat(_T_1090, _T_1089) @[lib.scala 89:14] - node _T_1092 = cat(_T_1091, _T_1088) @[lib.scala 89:14] - node _T_1093 = cat(_T_846[25], _T_846[24]) @[lib.scala 89:14] - node _T_1094 = cat(_T_846[27], _T_846[26]) @[lib.scala 89:14] - node _T_1095 = cat(_T_1094, _T_1093) @[lib.scala 89:14] - node _T_1096 = cat(_T_846[29], _T_846[28]) @[lib.scala 89:14] - node _T_1097 = cat(_T_846[31], _T_846[30]) @[lib.scala 89:14] + node _T_1092 = cat(_T_849[21], _T_849[20]) @[lib.scala 89:14] + node _T_1093 = cat(_T_849[23], _T_849[22]) @[lib.scala 89:14] + node _T_1094 = cat(_T_1093, _T_1092) @[lib.scala 89:14] + node _T_1095 = cat(_T_1094, _T_1091) @[lib.scala 89:14] + node _T_1096 = cat(_T_849[25], _T_849[24]) @[lib.scala 89:14] + node _T_1097 = cat(_T_849[27], _T_849[26]) @[lib.scala 89:14] node _T_1098 = cat(_T_1097, _T_1096) @[lib.scala 89:14] - node _T_1099 = cat(_T_1098, _T_1095) @[lib.scala 89:14] - node _T_1100 = cat(_T_1099, _T_1092) @[lib.scala 89:14] - node _T_1101 = cat(_T_1100, _T_1085) @[lib.scala 89:14] - node _T_1102 = and(_T_844, _T_1101) @[lsu_trigger.scala 19:92] - node _T_1103 = cat(_T_1102, _T_836) @[Cat.scala 29:58] - node _T_1104 = cat(_T_1103, _T_570) @[Cat.scala 29:58] - node _T_1105 = cat(_T_1104, _T_304) @[Cat.scala 29:58] - io.lsu_trigger_match_m <= _T_1105 @[lsu_trigger.scala 18:26] + node _T_1099 = cat(_T_849[29], _T_849[28]) @[lib.scala 89:14] + node _T_1100 = cat(_T_849[31], _T_849[30]) @[lib.scala 89:14] + node _T_1101 = cat(_T_1100, _T_1099) @[lib.scala 89:14] + node _T_1102 = cat(_T_1101, _T_1098) @[lib.scala 89:14] + node _T_1103 = cat(_T_1102, _T_1095) @[lib.scala 89:14] + node _T_1104 = cat(_T_1103, _T_1088) @[lib.scala 89:14] + node _T_1105 = andr(_T_1104) @[lib.scala 89:25] + node _T_1106 = and(_T_847, _T_1105) @[lsu_trigger.scala 19:92] + node _T_1107 = cat(_T_1106, _T_839) @[Cat.scala 29:58] + node _T_1108 = cat(_T_1107, _T_572) @[Cat.scala 29:58] + node _T_1109 = cat(_T_1108, _T_305) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1109 @[lsu_trigger.scala 18:26] extmodule gated_latch_800 : output Q : Clock @@ -107065,7 +107073,7 @@ circuit quasar_wrapper : module dma_ctrl : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, flip iccm_ready : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} + output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, flip iccm_ready : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} wire fifo_error : UInt<2>[5] @[dma_ctrl.scala 36:24] wire fifo_error_bus : UInt<5> @@ -109243,29 +109251,29 @@ circuit quasar_wrapper : module axi4_to_ahb : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -109300,8 +109308,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -109410,141 +109418,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_847 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -109553,193 +109561,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -109748,39 +109756,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -109789,83 +109797,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -109874,62 +109882,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -109938,35 +109946,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -109975,268 +109983,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_849 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -110245,8 +110253,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_850 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -110255,37 +110263,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_851 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -110294,30 +110302,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_852 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -110326,98 +110334,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_853 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_854 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_855 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_856 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_857 : output Q : Clock @@ -110662,29 +110670,29 @@ circuit quasar_wrapper : module axi4_to_ahb_1 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -110719,8 +110727,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -110829,141 +110837,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_857 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_858 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -110972,193 +110980,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -111167,39 +111175,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -111208,83 +111216,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -111293,62 +111301,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -111357,35 +111365,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -111394,268 +111402,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_859 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -111664,8 +111672,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_860 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -111674,37 +111682,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_861 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -111713,30 +111721,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_862 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -111745,98 +111753,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_863 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_864 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_865 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_866 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_867 : output Q : Clock @@ -112081,29 +112089,29 @@ circuit quasar_wrapper : module axi4_to_ahb_2 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -112138,8 +112146,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -112248,141 +112256,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_867 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_868 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -112391,193 +112399,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -112586,39 +112594,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -112627,83 +112635,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -112712,62 +112720,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -112776,35 +112784,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -112813,268 +112821,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_869 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -113083,8 +113091,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_870 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113093,37 +113101,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_871 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113132,30 +113140,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_872 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -113164,98 +113172,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_873 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_874 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_875 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_876 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_877 : output Q : Clock @@ -113404,7 +113412,7 @@ circuit quasar_wrapper : module ahb_to_axi4 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_haddr : UInt<32>, flip ahb_hburst : UInt<3>, flip ahb_hmastlock : UInt<1>, flip ahb_hprot : UInt<4>, flip ahb_hsize : UInt<3>, flip ahb_htrans : UInt<2>, flip ahb_hwrite : UInt<1>, flip ahb_hwdata : UInt<64>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb_hrdata : UInt<64>, ahb_hreadyout : UInt<1>, ahb_hresp : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, flip ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire master_wstrb : UInt<8> master_wstrb <= UInt<8>("h00") @@ -113440,9 +113448,9 @@ circuit quasar_wrapper : ahb_bus_addr_clk_en <= UInt<1>("h00") wire buf_rdata_clk_en : UInt<1> buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 85:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 86:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 87:33] + wire ahb_clk : Clock @[ahb_to_axi4.scala 86:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 87:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 88:33] wire cmdbuf_wr_en : UInt<1> cmdbuf_wr_en <= UInt<1>("h00") wire cmdbuf_rst : UInt<1> @@ -113461,7 +113469,7 @@ circuit quasar_wrapper : cmdbuf_addr <= UInt<32>("h00") wire cmdbuf_wdata : UInt<64> cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 99:33] + wire bus_clk : Clock @[ahb_to_axi4.scala 100:33] node _T = bits(ahb_haddr_q, 31, 28) @[lib.scala 68:25] node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[lib.scala 68:47] node _T_1 = bits(ahb_haddr_q, 31, 16) @[lib.scala 71:14] @@ -113478,260 +113486,260 @@ circuit quasar_wrapper : buf_state <= UInt<2>("h00") wire buf_nxtstate : UInt<2> buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 109:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 110:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 111:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 112:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 113:31] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 110:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 111:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 112:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 113:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 114:31] node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] when _T_6 : @[Conditional.scala 40:58] - node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 117:26] - buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 117:20] - node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 118:49] - node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 118:34] - node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 118:53] - buf_state_en <= _T_10 @[ahb_to_axi4.scala 118:20] + node _T_7 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 118:26] + buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 118:20] + node _T_8 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 119:53] + node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 119:34] + node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 119:57] + buf_state_en <= _T_10 @[ahb_to_axi4.scala 119:20] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] when _T_11 : @[Conditional.scala 39:67] - node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 121:57] - node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 121:64] - node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 121:41] - node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 121:78] - node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 121:76] - node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 121:92] - node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 121:109] - node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 121:26] - buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 121:20] - node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 122:24] - node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 122:37] - buf_state_en <= _T_21 @[ahb_to_axi4.scala 122:20] - node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 123:23] - node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 123:70] - node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 123:77] - node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 123:95] - node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 123:53] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 123:38] - node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 123:36] - cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 123:20] + node _T_12 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 122:64] + node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 122:71] + node _T_14 = or(io.ahb.in.hresp, _T_13) @[ahb_to_axi4.scala 122:44] + node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 122:85] + node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 122:83] + node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 122:99] + node _T_18 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 122:116] + node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 122:26] + buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 122:20] + node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 123:24] + node _T_21 = or(_T_20, io.ahb.in.hresp) @[ahb_to_axi4.scala 123:37] + buf_state_en <= _T_21 @[ahb_to_axi4.scala 123:20] + node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 124:23] + node _T_23 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 124:77] + node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 124:84] + node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 124:102] + node _T_26 = or(io.ahb.in.hresp, _T_25) @[ahb_to_axi4.scala 124:56] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 124:38] + node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 124:36] + cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 124:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] when _T_29 : @[Conditional.scala 39:67] - node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 126:26] - buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 126:20] - node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 127:24] - node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 127:37] - buf_state_en <= _T_32 @[ahb_to_axi4.scala 127:20] - node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 128:23] - node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 128:39] - node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 128:37] - cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 128:20] + node _T_30 = mux(io.ahb.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 127:26] + buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 127:20] + node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 128:24] + node _T_32 = or(_T_31, io.ahb.in.hresp) @[ahb_to_axi4.scala 128:37] + buf_state_en <= _T_32 @[ahb_to_axi4.scala 128:20] + node _T_33 = eq(io.ahb.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 129:23] + node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 129:42] + node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 129:40] + cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 129:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] when _T_36 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 131:20] - node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 132:39] - node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 132:37] - buf_state_en <= _T_38 @[ahb_to_axi4.scala 132:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 133:20] - node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 134:55] - node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 134:62] - node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 134:41] - buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 134:25] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 132:20] + node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 133:39] + node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 133:37] + buf_state_en <= _T_38 @[ahb_to_axi4.scala 133:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 134:20] + node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 135:55] + node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 135:62] + node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 135:41] + buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 135:25] skip @[Conditional.scala 39:67] - node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 137:99] + node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 138:99] reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_42 : @[Reg.scala 28:19] _T_43 <= buf_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state <= _T_43 @[ahb_to_axi4.scala 137:31] - node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 139:54] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 139:60] + buf_state <= _T_43 @[ahb_to_axi4.scala 138:31] + node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 140:54] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 140:60] node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15] node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 139:92] - node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 139:78] - node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 139:70] - node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 140:24] - node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 140:30] + node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 140:92] + node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 140:78] + node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 140:70] + node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 141:24] + node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 141:30] node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15] node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 140:62] - node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 140:48] - node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 140:40] - node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 139:109] - node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 141:24] - node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 141:30] + node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 141:62] + node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 141:48] + node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 141:40] + node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 140:109] + node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 142:24] + node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 142:30] node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 141:62] - node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 141:48] - node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 141:40] - node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 140:79] - node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 142:24] - node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 142:30] + node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 142:62] + node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 142:48] + node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 142:40] + node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 141:79] + node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 143:24] + node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 143:30] node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15] node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 142:40] - node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 141:79] - master_wstrb <= _T_72 @[ahb_to_axi4.scala 139:31] - node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 145:66] - node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 145:64] - node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 145:84] - node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 145:110] - node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 145:97] - node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 145:135] - node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 145:154] - node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 145:142] - node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 145:123] - node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 145:121] - node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 145:167] - node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 145:165] - node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 145:37] - io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 145:31] - node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 146:51] - ahb_hready <= _T_86 @[ahb_to_axi4.scala 146:31] + node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 143:40] + node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 142:79] + master_wstrb <= _T_72 @[ahb_to_axi4.scala 140:31] + node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 146:72] + node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 146:70] + node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 146:90] + node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 146:116] + node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 146:103] + node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 146:141] + node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 146:160] + node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 146:148] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 146:129] + node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 146:127] + node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 146:173] + node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 146:171] + node _T_85 = mux(io.ahb.in.hresp, _T_74, _T_84) @[ahb_to_axi4.scala 146:40] + io.ahb.in.hready <= _T_85 @[ahb_to_axi4.scala 146:34] + node _T_86 = and(io.ahb.in.hready, io.ahb_hreadyin) @[ahb_to_axi4.scala 147:51] + ahb_hready <= _T_86 @[ahb_to_axi4.scala 147:31] node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15] node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 147:69] - node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 147:54] - ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 147:31] - node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 148:43] - io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 148:31] - node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 149:48] - node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 149:54] - node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 149:76] - node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 149:63] - node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 150:26] - node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 150:7] - node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 151:46] - node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 151:26] - node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 151:80] - node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 151:86] - node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 151:109] - node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 151:115] - node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 151:95] - node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 151:66] - node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 151:64] - node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 150:47] - node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 152:20] - node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 152:26] - node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 152:48] - node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 152:35] - node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 151:126] - node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 153:20] - node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 153:26] - node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 153:49] - node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 153:56] - node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 153:35] - node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 152:55] - node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 154:20] - node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 154:26] - node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 154:49] - node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 154:56] - node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 154:35] - node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 153:61] - node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 149:87] - node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 154:63] - node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 156:20] - node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 156:18] - node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 155:20] - io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 149:31] - reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 159:66] - _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 159:66] - buf_rdata <= _T_130 @[ahb_to_axi4.scala 159:31] - reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 160:60] - _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 160:60] - buf_read_error <= _T_131 @[ahb_to_axi4.scala 160:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 163:60] - _T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 163:60] - ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 163:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60] - _T_133 <= ahb_hready @[ahb_to_axi4.scala 164:60] - ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 164:31] - reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 165:60] - _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 165:60] - ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 165:31] - reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 166:65] - _T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 166:65] - ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 166:31] - reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:65] - _T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 167:65] - ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 167:31] - reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:65] - _T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 168:65] - ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 168:31] - node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 171:77] - node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 171:62] - node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 171:48] - ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 171:31] - node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 172:48] - buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 172:31] + node _T_89 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 148:73] + node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 148:54] + ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 148:31] + node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 149:46] + io.ahb.in.hrdata <= _T_91 @[ahb_to_axi4.scala 149:34] + node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 150:51] + node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 150:57] + node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 150:79] + node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 150:66] + node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 151:26] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 151:7] + node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 152:46] + node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 152:26] + node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:80] + node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 152:86] + node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:109] + node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 152:115] + node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 152:95] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 152:66] + node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 152:64] + node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 151:47] + node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 153:20] + node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 153:26] + node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 153:48] + node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 153:35] + node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 152:126] + node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 154:20] + node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 154:26] + node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 154:49] + node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 154:56] + node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 154:35] + node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 153:55] + node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 155:20] + node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 155:26] + node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 155:49] + node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 155:56] + node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 155:35] + node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 154:61] + node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 150:90] + node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 155:63] + node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 157:20] + node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 157:18] + node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 156:20] + io.ahb.in.hresp <= _T_129 @[ahb_to_axi4.scala 150:34] + reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 160:66] + _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 160:66] + buf_rdata <= _T_130 @[ahb_to_axi4.scala 160:31] + reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 161:60] + _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 161:60] + buf_read_error <= _T_131 @[ahb_to_axi4.scala 161:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60] + _T_132 <= io.ahb.in.hresp @[ahb_to_axi4.scala 164:60] + ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 164:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 165:60] + _T_133 <= ahb_hready @[ahb_to_axi4.scala 165:60] + ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 165:31] + reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 166:60] + _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 166:60] + ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 166:31] + reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:65] + _T_135 <= io.ahb.out.hsize @[ahb_to_axi4.scala 167:65] + ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 167:31] + reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:65] + _T_136 <= io.ahb.out.hwrite @[ahb_to_axi4.scala 168:65] + ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 168:31] + reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:65] + _T_137 <= io.ahb.out.haddr @[ahb_to_axi4.scala 169:65] + ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 169:31] + node _T_138 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 172:81] + node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 172:62] + node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 172:48] + ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 172:31] + node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 173:48] + buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 173:31] inst rvclkhdr of rvclkhdr_877 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 174:31] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 175:31] inst rvclkhdr_1 of rvclkhdr_878 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 175:31] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 176:31] inst rvclkhdr_2 of rvclkhdr_879 @[lib.scala 327:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 328:17] rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 329:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 176:31] - node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 178:52] - node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 178:88] - node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 178:70] - node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 178:109] - node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 178:107] - node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 178:142] - node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 178:140] - node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 178:124] - cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 178:31] - node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 179:66] - node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 179:102] - node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 179:84] - node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 179:48] - node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 179:46] - cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 179:31] - node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 181:86] - node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 181:66] - node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 181:110] - node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 181:108] - reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 181:61] - _T_159 <= _T_158 @[ahb_to_axi4.scala 181:61] - cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 181:31] - node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 185:53] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 177:31] + node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 179:52] + node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 179:88] + node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 179:70] + node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 179:109] + node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 179:107] + node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 179:145] + node _T_148 = and(io.ahb.in.hresp, _T_147) @[ahb_to_axi4.scala 179:143] + node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 179:124] + cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 179:31] + node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 180:66] + node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 180:102] + node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 180:84] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 180:48] + node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 180:46] + cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 180:31] + node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 182:86] + node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 182:66] + node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 182:110] + node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 182:108] + reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 182:61] + _T_159 <= _T_158 @[ahb_to_axi4.scala 182:61] + cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 182:31] + node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 186:53] reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_160 : @[Reg.scala 28:19] _T_161 <= ahb_hwrite_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 184:31] - node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 188:52] + cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 185:31] + node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 189:52] reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_162 : @[Reg.scala 28:19] _T_163 <= ahb_hsize_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 187:31] - node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 191:53] + cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 188:31] + node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 192:53] reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_164 : @[Reg.scala 28:19] _T_165 <= master_wstrb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 190:31] - node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 194:57] + cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 191:31] + node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:57] inst rvclkhdr_3 of rvclkhdr_880 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113740,8 +113748,8 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_167 <= ahb_haddr_q @[lib.scala 358:16] - cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 194:15] - node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:60] + cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 195:15] + node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 196:64] inst rvclkhdr_4 of rvclkhdr_881 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113749,953 +113757,986 @@ circuit quasar_wrapper : rvclkhdr_4.io.en <= _T_168 @[lib.scala 355:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_169 <= io.ahb_hwdata @[lib.scala 358:16] - cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 195:16] - node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 198:41] - io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 198:27] - io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 199:27] - io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 200:27] - node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 201:53] + _T_169 <= io.ahb.out.hwdata @[lib.scala 358:16] + cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 196:16] + node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 199:41] + io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 199:27] + io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 200:27] + io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 201:27] + node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 202:53] node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58] - io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 201:27] + io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 202:27] node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 202:27] + io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 203:27] node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 203:27] - io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 204:27] - node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 206:41] - io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 206:27] - io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 207:27] - io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 208:27] - io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 209:27] - io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 211:27] - node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 213:43] - node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 213:41] - io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 213:27] - io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 214:27] - io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 215:27] - node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 216:53] + io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 204:27] + io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 205:27] + node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 207:41] + io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 207:27] + io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 208:27] + io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 209:27] + io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 210:27] + io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 212:27] + node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 214:43] + node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 214:41] + io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 214:27] + io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 215:27] + io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 216:27] + node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 217:53] node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58] - io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 216:27] + io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 217:27] node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 217:27] + io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 218:27] node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 218:27] - io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 219:27] - io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 221:27] + io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 219:27] + io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 220:27] + io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 222:27] inst rvclkhdr_5 of rvclkhdr_882 @[lib.scala 327:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 328:17] rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 224:27] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 225:27] module quasar : input clock : Clock input reset : AsyncReset - output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} + output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip dma_hsel : UInt<1>, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of ifu @[quasar.scala 116:19] + inst ifu of ifu @[quasar.scala 122:19] ifu.clock <= clock ifu.reset <= reset - inst dec of dec @[quasar.scala 117:19] + inst dec of dec @[quasar.scala 123:19] dec.clock <= clock dec.reset <= reset - inst dbg of dbg @[quasar.scala 118:19] + inst dbg of dbg @[quasar.scala 124:19] dbg.clock <= clock dbg.reset <= reset - inst exu of exu @[quasar.scala 119:19] + inst exu of exu @[quasar.scala 125:19] exu.clock <= clock exu.reset <= reset - inst lsu of lsu @[quasar.scala 120:19] + inst lsu of lsu @[quasar.scala 126:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctrl_inst of pic_ctrl @[quasar.scala 121:29] + inst pic_ctrl_inst of pic_ctrl @[quasar.scala 127:29] pic_ctrl_inst.clock <= clock pic_ctrl_inst.reset <= reset - inst dma_ctrl of dma_ctrl @[quasar.scala 122:24] + inst dma_ctrl of dma_ctrl @[quasar.scala 128:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[quasar.scala 124:33] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 124:67] - node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 124:70] - node _T_3 = and(_T, _T_2) @[quasar.scala 124:36] - node _T_4 = asAsyncReset(_T_3) @[quasar.scala 124:99] - io.core_rst_l <= _T_4 @[quasar.scala 124:17] - node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 125:23] - node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 125:50] - node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 125:98] + node _T = asUInt(reset) @[quasar.scala 130:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 130:67] + node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 130:70] + node _T_3 = and(_T, _T_2) @[quasar.scala 130:36] + node _T_4 = asAsyncReset(_T_3) @[quasar.scala 130:99] + io.core_rst_l <= _T_4 @[quasar.scala 130:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 131:23] + node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 131:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 131:98] inst rvclkhdr of rvclkhdr_845 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_7 = bits(active_state, 0, 0) @[quasar.scala 127:49] + node _T_7 = bits(active_state, 0, 0) @[quasar.scala 133:49] inst rvclkhdr_1 of rvclkhdr_846 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 128:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 129:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 130:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 133:18] - ifu.reset <= io.core_rst_l @[quasar.scala 135:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 136:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 137:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 138:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 140:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 141:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 143:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 144:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 145:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 145:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 145:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 145:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 145:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 145:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 145:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 145:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 145:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 145:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 145:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 145:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 145:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 145:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 145:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 145:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 145:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 145:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 145:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 145:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 145:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 146:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 146:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 146:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 146:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 146:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 146:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 146:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 146:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 146:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 148:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 149:43] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 150:33] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 151:51] - dec.reset <= io.core_rst_l @[quasar.scala 154:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 155:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 156:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 157:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 158:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 159:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 160:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 161:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 162:24] - dec.io.core_id <= io.core_id @[quasar.scala 163:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 164:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 165:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 166:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 167:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 168:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 168:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 169:31] - dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 170:18] - dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 170:18] - dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 170:18] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 172:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 173:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 174:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 175:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 176:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 177:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 178:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 179:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 180:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 181:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 182:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 183:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 184:30] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 185:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 186:26] - dec.io.soft_int <= io.soft_int @[quasar.scala 188:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 189:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 190:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 191:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 192:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 193:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 196:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 196:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 196:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 196:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 196:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 196:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 196:18] - exu.reset <= io.core_rst_l @[quasar.scala 197:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 198:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 199:25] - lsu.reset <= io.core_rst_l @[quasar.scala 202:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 203:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 204:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 205:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 206:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 207:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 208:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 208:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 209:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 210:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 210:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 210:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 210:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 210:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 210:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 210:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 210:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 210:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 210:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 210:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 210:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 210:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 211:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 212:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 213:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 215:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 216:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 217:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 218:19] - dbg.reset <= io.core_rst_l @[quasar.scala 221:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 222:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 222:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 223:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 223:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 224:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 224:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 225:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 226:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 227:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 228:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 229:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 230:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 231:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 232:24] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 233:17] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 233:17] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 233:17] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 233:17] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 233:17] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 233:17] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 233:17] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 233:17] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 233:17] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 233:17] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 233:17] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 233:17] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 233:17] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 233:17] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 233:17] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 233:17] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 233:17] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 233:17] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 233:17] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 233:17] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 233:17] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 233:17] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 233:17] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 233:17] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 233:17] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 233:17] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 233:17] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 233:17] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 233:17] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 233:17] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 233:17] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 233:17] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 233:17] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 233:17] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 233:17] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 233:17] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 234:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 235:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 235:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 236:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 237:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 241:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 242:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 243:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 244:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 245:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 246:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 247:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 247:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 248:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 249:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 250:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 251:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 252:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 253:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 256:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 257:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 258:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 259:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 260:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 261:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 262:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 263:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 263:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 263:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 263:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 263:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 263:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 265:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 268:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 269:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 270:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 271:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 272:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 273:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 274:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 275:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 276:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 277:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 278:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 279:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 280:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 281:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 283:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 283:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 283:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 283:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 283:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 283:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 283:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 283:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 283:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 283:11] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 286:14] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 286:14] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 286:14] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 286:14] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 286:14] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 286:14] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 286:14] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 286:14] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 286:14] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 286:14] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 286:14] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 286:14] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 286:14] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 286:14] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 286:14] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 286:14] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 286:14] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 286:14] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 286:14] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 286:14] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 286:14] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 286:14] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 286:14] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 286:14] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 286:14] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 286:14] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 286:14] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 286:14] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 286:14] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 286:14] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 286:14] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 286:14] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 286:14] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 286:14] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 286:14] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 286:14] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 286:14] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 286:14] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 286:14] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 289:14] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 289:14] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 289:14] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 289:14] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 289:14] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 289:14] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 289:14] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 289:14] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 289:14] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 289:14] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 289:14] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 289:14] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 289:14] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 289:14] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 289:14] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 289:14] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 289:14] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 289:14] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 289:14] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 289:14] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 289:14] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 289:14] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 289:14] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 289:14] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 289:14] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 289:14] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 289:14] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 289:14] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 289:14] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 289:14] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 289:14] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 289:14] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 289:14] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 289:14] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 289:14] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 289:14] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 289:14] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 289:14] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 289:14] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 290:14] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 290:14] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 290:14] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 290:14] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 290:14] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 290:14] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 290:14] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 290:14] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 290:14] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 290:14] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 290:14] - when UInt<1>("h00") : @[quasar.scala 296:26] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 297:33] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 134:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 135:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 136:28] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 139:18] + ifu.reset <= io.core_rst_l @[quasar.scala 141:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 142:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 143:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 144:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 146:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 147:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 149:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 150:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 151:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 151:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 151:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 151:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 151:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 151:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 151:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 151:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 151:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 151:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 151:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 151:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 151:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 151:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 151:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 151:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 151:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 151:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 151:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 151:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 151:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 152:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 152:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 152:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 152:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 152:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 152:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 152:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 152:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 152:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 154:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 155:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 156:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 157:51] + dec.reset <= io.core_rst_l @[quasar.scala 160:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 161:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 162:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 163:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 164:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 165:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 166:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 167:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 168:24] + dec.io.core_id <= io.core_id @[quasar.scala 169:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 170:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 171:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 172:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 173:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 174:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 174:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 175:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 176:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 176:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 176:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 178:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 179:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 180:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 181:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 182:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 183:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 184:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 185:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 186:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 187:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 188:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 189:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 190:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 191:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 192:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 194:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 195:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 196:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 197:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 198:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 199:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 202:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 202:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 202:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 202:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 202:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 202:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 202:18] + exu.reset <= io.core_rst_l @[quasar.scala 203:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 204:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 205:25] + lsu.reset <= io.core_rst_l @[quasar.scala 208:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 209:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 210:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 211:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 212:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 213:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 214:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 214:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 215:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 216:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 216:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 216:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 216:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 216:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 216:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 216:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 216:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 216:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 216:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 216:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 216:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 216:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 217:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 218:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 219:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 221:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 222:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 223:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 224:19] + dbg.reset <= io.core_rst_l @[quasar.scala 227:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 228:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 228:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 229:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 229:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 230:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 230:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 231:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 232:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 233:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 234:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 235:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 236:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 237:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 238:24] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 239:17] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 239:17] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 239:17] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 239:17] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 239:17] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 239:17] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 239:17] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 239:17] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 239:17] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 239:17] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 239:17] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 239:17] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 239:17] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 239:17] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 239:17] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 239:17] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 239:17] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 239:17] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 239:17] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 239:17] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 239:17] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 239:17] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 239:17] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 239:17] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 239:17] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 239:17] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 239:17] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 239:17] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 239:17] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 239:17] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 239:17] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 239:17] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 239:17] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 239:17] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 239:17] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 239:17] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 240:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 241:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 241:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 242:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 243:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 247:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 248:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 249:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 250:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 251:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 252:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 253:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 253:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 254:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 255:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 256:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 257:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 258:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 259:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 262:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 263:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 264:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 265:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 266:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 267:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 268:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 269:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 269:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 269:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 269:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 269:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 269:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 271:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 274:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 275:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 276:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 277:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 278:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 279:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 280:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 281:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 282:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 283:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 284:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 285:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 286:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 287:23] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 289:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 289:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 289:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 289:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 289:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 289:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 289:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 289:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 289:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 289:11] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 292:14] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 292:14] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 292:14] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 292:14] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 292:14] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 292:14] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 292:14] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 292:14] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 292:14] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 292:14] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 292:14] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 292:14] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 292:14] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 292:14] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 292:14] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 292:14] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 292:14] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 292:14] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 292:14] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 292:14] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 292:14] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 292:14] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 292:14] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 292:14] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 292:14] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 292:14] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 292:14] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 292:14] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 292:14] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 292:14] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 292:14] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 292:14] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 292:14] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 292:14] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 292:14] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 292:14] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 292:14] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 292:14] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 292:14] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 295:14] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 295:14] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 295:14] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 295:14] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 295:14] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 295:14] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 295:14] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 295:14] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 295:14] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 295:14] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 295:14] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 295:14] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 295:14] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 295:14] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 295:14] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 295:14] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 295:14] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 295:14] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 295:14] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 295:14] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 295:14] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 295:14] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 295:14] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 295:14] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 295:14] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 295:14] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 295:14] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 295:14] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 295:14] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 295:14] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 295:14] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 295:14] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 295:14] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 295:14] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 295:14] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 295:14] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 295:14] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 295:14] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 295:14] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 296:14] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 296:14] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 296:14] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 296:14] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 296:14] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 296:14] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 296:14] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 296:14] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 296:14] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 296:14] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 296:14] + when UInt<1>("h00") : @[quasar.scala 302:26] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 303:33] axi4_to_ahb.clock <= clock axi4_to_ahb.reset <= reset - axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 298:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 299:34] - axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 300:35] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 301:37] - axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 302:33] - axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 303:35] - axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 304:35] - axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 305:35] - axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 307:35] - axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 308:34] - axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 309:34] - axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 310:34] - axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 311:35] - axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 313:36] - axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 314:33] - axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 315:35] - axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 316:35] - axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 317:35] - axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 319:35] - axi4_to_ahb.io.ahb_hrdata <= io.lsu_hrdata @[quasar.scala 320:35] - axi4_to_ahb.io.ahb_hready <= io.lsu_hready @[quasar.scala 321:35] - axi4_to_ahb.io.ahb_hresp <= io.lsu_hresp @[quasar.scala 322:34] - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 324:33] + axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 304:36] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 305:34] + axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 306:35] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 307:37] + axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 308:33] + axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 309:35] + axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 310:35] + axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 311:35] + axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 313:35] + axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 314:34] + axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 315:34] + axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 316:34] + axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 317:35] + axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 319:36] + axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 320:33] + axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 321:35] + axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 322:35] + axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 323:35] + axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 325:35] + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 330:33] axi4_to_ahb_1.clock <= clock axi4_to_ahb_1.reset <= reset - axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 325:36] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 326:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 327:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 328:37] - axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 329:33] - axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 330:35] - axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 331:35] - axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 332:35] - axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 334:35] - axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 335:34] - axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 336:34] - axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 337:34] - axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 338:35] - axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 340:36] - axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 341:33] - axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 342:35] - axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 343:35] - axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 344:35] - axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 346:35] - axi4_to_ahb_1.io.ahb_hrdata <= io.hrdata @[quasar.scala 348:35] - axi4_to_ahb_1.io.ahb_hready <= io.hready @[quasar.scala 349:35] - axi4_to_ahb_1.io.ahb_hresp <= io.hresp @[quasar.scala 350:34] - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 352:32] + axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 331:36] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 332:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 333:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 334:37] + axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 335:33] + axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 336:35] + axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 337:35] + axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 338:35] + axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 340:35] + axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 341:34] + axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 342:34] + axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 343:34] + axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 344:35] + axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 346:36] + axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 347:33] + axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 348:35] + axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 349:35] + axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 350:35] + axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 352:35] + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 358:32] axi4_to_ahb_2.clock <= clock axi4_to_ahb_2.reset <= reset - axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 353:35] - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 354:33] - axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 355:34] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 356:36] - axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 357:32] - axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 358:34] - axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 359:34] - axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 360:34] - axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 362:34] - axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 363:33] - axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 364:33] - axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 365:33] - axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 366:34] - axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 368:35] - axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 369:32] - axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 370:34] - axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 371:34] - axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 372:34] - axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 374:34] - axi4_to_ahb_2.io.ahb_hrdata <= io.sb_hrdata @[quasar.scala 375:34] - axi4_to_ahb_2.io.ahb_hready <= io.sb_hready @[quasar.scala 376:34] - axi4_to_ahb_2.io.ahb_hresp <= io.sb_hresp @[quasar.scala 377:33] - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 379:33] + axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 359:35] + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 360:33] + axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 361:34] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 362:36] + axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 363:32] + axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 364:34] + axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 365:34] + axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 366:34] + axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 368:34] + axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 369:33] + axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 370:33] + axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 371:33] + axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 372:34] + axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 374:35] + axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 375:32] + axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 376:34] + axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 377:34] + axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 378:34] + axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 380:34] + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 385:33] ahb_to_axi4.clock <= clock ahb_to_axi4.reset <= reset - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 380:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 381:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 382:37] - ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 383:36] - ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 384:35] - ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 385:35] - ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 386:34] - ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 387:32] - ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 390:36] - ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 391:35] - ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 392:32] - ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 393:34] - ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 394:34] - ahb_to_axi4.io.ahb_haddr <= io.dma_haddr @[quasar.scala 397:34] - ahb_to_axi4.io.ahb_hburst <= io.dma_hburst @[quasar.scala 398:35] - ahb_to_axi4.io.ahb_hmastlock <= io.dma_hmastlock @[quasar.scala 399:38] - ahb_to_axi4.io.ahb_hprot <= io.dma_hprot @[quasar.scala 400:34] - ahb_to_axi4.io.ahb_hsize <= io.dma_hsize @[quasar.scala 401:34] - ahb_to_axi4.io.ahb_htrans <= io.dma_htrans @[quasar.scala 402:35] - ahb_to_axi4.io.ahb_hwrite <= io.dma_hwrite @[quasar.scala 403:35] - ahb_to_axi4.io.ahb_hwdata <= io.dma_hwdata @[quasar.scala 404:35] - ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 405:33] - ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 406:37] - node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 409:31] - lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 409:25] - node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 410:30] - lsu.io.axi.w.ready <= _T_13 @[quasar.scala 410:24] - node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 411:30] - lsu.io.axi.b.valid <= _T_14 @[quasar.scala 411:24] - node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 412:34] - lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 412:28] - node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 413:32] - lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 413:26] - node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 414:31] - lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 414:25] - node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 415:30] - lsu.io.axi.r.valid <= _T_18 @[quasar.scala 415:24] - node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 416:32] - lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 416:26] - node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 417:34] - lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 417:28] - node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 418:34] - lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 418:28] - node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 419:34] - lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 419:28] - node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 421:31] - ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 421:25] - node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 422:30] - ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 422:24] - node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 423:31] - ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 423:25] - node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 424:30] - ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 424:24] - node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 425:32] - ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 425:26] - node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 426:34] - ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 426:28] - node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 427:34] - ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 427:28] - node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 428:34] - ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 428:28] - node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 430:34] - dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 430:28] - node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 431:33] - dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 431:27] - node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 432:33] - dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 432:27] - node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 433:37] - dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 433:31] - node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 434:34] - dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 434:28] - node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 435:33] - dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 435:27] - node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 436:35] - dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 436:29] - node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 437:37] - dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 437:31] - node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 438:37] - dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 438:31] - node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 440:40] - dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 440:34] - node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 441:42] - dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 441:36] - node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 442:44] - dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 442:38] - node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 443:44] - dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 443:38] - node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 444:39] - dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 444:33] - node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 445:43] - dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 445:37] - node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 446:43] - dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 446:37] - node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 447:39] - dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 447:33] - node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 448:40] - dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 448:34] - node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 449:42] - dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 449:36] - node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 450:44] - dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 450:38] - node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 451:44] - dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 451:38] - node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 452:39] - dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 452:33] - io.haddr <= axi4_to_ahb_1.io.ahb_haddr @[quasar.scala 456:14] - io.hburst <= axi4_to_ahb_1.io.ahb_hburst @[quasar.scala 457:15] - io.hmastlock <= axi4_to_ahb_1.io.ahb_hmastlock @[quasar.scala 458:18] - io.hprot <= axi4_to_ahb_1.io.ahb_hprot @[quasar.scala 459:14] - io.hsize <= axi4_to_ahb_1.io.ahb_hsize @[quasar.scala 460:14] - io.htrans <= axi4_to_ahb_1.io.ahb_htrans @[quasar.scala 461:15] - io.hwrite <= axi4_to_ahb_1.io.ahb_hwrite @[quasar.scala 462:15] - io.lsu_haddr <= axi4_to_ahb.io.ahb_haddr @[quasar.scala 465:18] - io.lsu_hburst <= axi4_to_ahb.io.ahb_hburst @[quasar.scala 466:19] - io.lsu_hmastlock <= axi4_to_ahb.io.ahb_hmastlock @[quasar.scala 467:22] - io.lsu_hprot <= axi4_to_ahb.io.ahb_hprot @[quasar.scala 468:18] - io.lsu_hsize <= axi4_to_ahb.io.ahb_hsize @[quasar.scala 469:18] - io.lsu_htrans <= axi4_to_ahb.io.ahb_htrans @[quasar.scala 470:19] - io.lsu_hwrite <= axi4_to_ahb.io.ahb_hwrite @[quasar.scala 471:19] - io.lsu_hwdata <= axi4_to_ahb.io.ahb_hwdata @[quasar.scala 472:19] - io.sb_haddr <= axi4_to_ahb_2.io.ahb_haddr @[quasar.scala 474:17] - io.sb_hburst <= axi4_to_ahb_2.io.ahb_hburst @[quasar.scala 475:18] - io.sb_hmastlock <= axi4_to_ahb_2.io.ahb_hmastlock @[quasar.scala 476:21] - io.sb_hprot <= axi4_to_ahb_2.io.ahb_hprot @[quasar.scala 477:17] - io.sb_hsize <= axi4_to_ahb_2.io.ahb_hsize @[quasar.scala 478:17] - io.sb_htrans <= axi4_to_ahb_2.io.ahb_htrans @[quasar.scala 479:18] - io.sb_hwrite <= axi4_to_ahb_2.io.ahb_hwrite @[quasar.scala 480:18] - io.sb_hwdata <= axi4_to_ahb_2.io.ahb_hwdata @[quasar.scala 481:18] - io.dma_hrdata <= ahb_to_axi4.io.ahb_hrdata @[quasar.scala 483:19] - io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 484:22] - io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 485:18] - skip @[quasar.scala 296:26] - else : @[quasar.scala 487:17] - io.haddr <= UInt<1>("h00") @[quasar.scala 489:18] - io.hburst <= UInt<1>("h00") @[quasar.scala 490:19] - io.hmastlock <= UInt<1>("h00") @[quasar.scala 491:22] - io.hprot <= UInt<1>("h00") @[quasar.scala 492:18] - io.hsize <= UInt<1>("h00") @[quasar.scala 493:18] - io.htrans <= UInt<1>("h00") @[quasar.scala 494:19] - io.hwrite <= UInt<1>("h00") @[quasar.scala 495:19] - io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 498:22] - io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 499:23] - io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 500:26] - io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 501:22] - io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 502:22] - io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 503:23] - io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 504:23] - io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 505:23] - io.sb_haddr <= UInt<1>("h00") @[quasar.scala 507:21] - io.sb_hburst <= UInt<1>("h00") @[quasar.scala 508:22] - io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 509:25] - io.sb_hprot <= UInt<1>("h00") @[quasar.scala 510:21] - io.sb_hsize <= UInt<1>("h00") @[quasar.scala 511:21] - io.sb_htrans <= UInt<1>("h00") @[quasar.scala 512:22] - io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 513:22] - io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 514:22] - io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 516:23] - io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 517:26] - io.dma_hresp <= UInt<1>("h00") @[quasar.scala 518:22] - skip @[quasar.scala 487:17] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 521:20] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 386:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 387:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 388:37] + ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 389:36] + ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 390:35] + ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 391:35] + ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 392:34] + ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 393:32] + ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 396:36] + ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 397:35] + ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 398:32] + ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 399:34] + ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 400:34] + ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 411:33] + ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 412:37] + node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 413:31] + lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 413:25] + node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 414:30] + lsu.io.axi.w.ready <= _T_13 @[quasar.scala 414:24] + node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 415:30] + lsu.io.axi.b.valid <= _T_14 @[quasar.scala 415:24] + node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 416:34] + lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 416:28] + node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 417:32] + lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 417:26] + node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 418:31] + lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 418:25] + node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 419:30] + lsu.io.axi.r.valid <= _T_18 @[quasar.scala 419:24] + node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 420:32] + lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 420:26] + node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 421:34] + lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 421:28] + node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 422:34] + lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 422:28] + node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 423:34] + lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 423:28] + node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 425:31] + ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 425:25] + node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 426:30] + ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 426:24] + node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 427:31] + ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 427:25] + node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 428:30] + ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 428:24] + node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 429:32] + ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 429:26] + node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 430:34] + ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 430:28] + node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 431:34] + ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 431:28] + node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 432:34] + ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 432:28] + node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 434:34] + dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 434:28] + node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 435:33] + dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 435:27] + node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 436:33] + dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 436:27] + node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 437:37] + dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 437:31] + node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 438:34] + dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 438:28] + node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 439:33] + dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 439:27] + node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 440:35] + dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 440:29] + node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 441:37] + dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 441:31] + node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 442:37] + dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 442:31] + node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 444:40] + dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 444:34] + node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 445:42] + dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 445:36] + node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 446:44] + dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 446:38] + node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 447:44] + dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 447:38] + node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 448:39] + dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 448:33] + node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 449:43] + dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 449:37] + node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 450:43] + dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 450:37] + node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 451:39] + dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 451:33] + node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 452:40] + dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 452:34] + node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 453:42] + dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 453:36] + node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 454:44] + dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 454:38] + node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 455:44] + dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 455:38] + node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 456:39] + dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 456:33] + io.ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 458:12] + io.ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 458:12] + io.ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 458:12] + io.ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 458:12] + io.ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 458:12] + io.ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 458:12] + io.ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 458:12] + io.ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ahb.in.hresp @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hready <= io.ahb.in.hready @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ahb.in.hrdata @[quasar.scala 458:12] + io.lsu_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 467:16] + io.lsu_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 467:16] + io.lsu_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 467:16] + io.lsu_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 467:16] + io.lsu_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 467:16] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 467:16] + io.lsu_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 467:16] + io.lsu_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 467:16] + io.sb_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 477:15] + io.sb_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 477:15] + io.sb_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 477:15] + io.sb_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 477:15] + io.sb_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 477:15] + io.sb_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 477:15] + io.sb_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 477:15] + io.sb_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 477:15] + ahb_to_axi4.io.ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar.scala 487:16] + io.dma_ahb.in.hresp <= ahb_to_axi4.io.ahb.in.hresp @[quasar.scala 487:16] + io.dma_ahb.in.hready <= ahb_to_axi4.io.ahb.in.hready @[quasar.scala 487:16] + io.dma_ahb.in.hrdata <= ahb_to_axi4.io.ahb.in.hrdata @[quasar.scala 487:16] + skip @[quasar.scala 302:26] + else : @[quasar.scala 494:15] + wire _T_53 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 496:33] + _T_53.hwdata <= UInt<64>("h00") @[quasar.scala 496:33] + _T_53.hwrite <= UInt<1>("h00") @[quasar.scala 496:33] + _T_53.htrans <= UInt<2>("h00") @[quasar.scala 496:33] + _T_53.hsize <= UInt<3>("h00") @[quasar.scala 496:33] + _T_53.hprot <= UInt<4>("h00") @[quasar.scala 496:33] + _T_53.hmastlock <= UInt<1>("h00") @[quasar.scala 496:33] + _T_53.hburst <= UInt<3>("h00") @[quasar.scala 496:33] + _T_53.haddr <= UInt<32>("h00") @[quasar.scala 496:33] + io.ahb.out.hwdata <= _T_53.hwdata @[quasar.scala 496:18] + io.ahb.out.hwrite <= _T_53.hwrite @[quasar.scala 496:18] + io.ahb.out.htrans <= _T_53.htrans @[quasar.scala 496:18] + io.ahb.out.hsize <= _T_53.hsize @[quasar.scala 496:18] + io.ahb.out.hprot <= _T_53.hprot @[quasar.scala 496:18] + io.ahb.out.hmastlock <= _T_53.hmastlock @[quasar.scala 496:18] + io.ahb.out.hburst <= _T_53.hburst @[quasar.scala 496:18] + io.ahb.out.haddr <= _T_53.haddr @[quasar.scala 496:18] + wire _T_54 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 505:37] + _T_54.hwdata <= UInt<64>("h00") @[quasar.scala 505:37] + _T_54.hwrite <= UInt<1>("h00") @[quasar.scala 505:37] + _T_54.htrans <= UInt<2>("h00") @[quasar.scala 505:37] + _T_54.hsize <= UInt<3>("h00") @[quasar.scala 505:37] + _T_54.hprot <= UInt<4>("h00") @[quasar.scala 505:37] + _T_54.hmastlock <= UInt<1>("h00") @[quasar.scala 505:37] + _T_54.hburst <= UInt<3>("h00") @[quasar.scala 505:37] + _T_54.haddr <= UInt<32>("h00") @[quasar.scala 505:37] + io.lsu_ahb.out.hwdata <= _T_54.hwdata @[quasar.scala 505:22] + io.lsu_ahb.out.hwrite <= _T_54.hwrite @[quasar.scala 505:22] + io.lsu_ahb.out.htrans <= _T_54.htrans @[quasar.scala 505:22] + io.lsu_ahb.out.hsize <= _T_54.hsize @[quasar.scala 505:22] + io.lsu_ahb.out.hprot <= _T_54.hprot @[quasar.scala 505:22] + io.lsu_ahb.out.hmastlock <= _T_54.hmastlock @[quasar.scala 505:22] + io.lsu_ahb.out.hburst <= _T_54.hburst @[quasar.scala 505:22] + io.lsu_ahb.out.haddr <= _T_54.haddr @[quasar.scala 505:22] + wire _T_55 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 515:36] + _T_55.hwdata <= UInt<64>("h00") @[quasar.scala 515:36] + _T_55.hwrite <= UInt<1>("h00") @[quasar.scala 515:36] + _T_55.htrans <= UInt<2>("h00") @[quasar.scala 515:36] + _T_55.hsize <= UInt<3>("h00") @[quasar.scala 515:36] + _T_55.hprot <= UInt<4>("h00") @[quasar.scala 515:36] + _T_55.hmastlock <= UInt<1>("h00") @[quasar.scala 515:36] + _T_55.hburst <= UInt<3>("h00") @[quasar.scala 515:36] + _T_55.haddr <= UInt<32>("h00") @[quasar.scala 515:36] + io.sb_ahb.out.hwdata <= _T_55.hwdata @[quasar.scala 515:21] + io.sb_ahb.out.hwrite <= _T_55.hwrite @[quasar.scala 515:21] + io.sb_ahb.out.htrans <= _T_55.htrans @[quasar.scala 515:21] + io.sb_ahb.out.hsize <= _T_55.hsize @[quasar.scala 515:21] + io.sb_ahb.out.hprot <= _T_55.hprot @[quasar.scala 515:21] + io.sb_ahb.out.hmastlock <= _T_55.hmastlock @[quasar.scala 515:21] + io.sb_ahb.out.hburst <= _T_55.hburst @[quasar.scala 515:21] + io.sb_ahb.out.haddr <= _T_55.haddr @[quasar.scala 515:21] + wire _T_56 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar.scala 525:36] + _T_56.hresp <= UInt<1>("h00") @[quasar.scala 525:36] + _T_56.hready <= UInt<1>("h00") @[quasar.scala 525:36] + _T_56.hrdata <= UInt<64>("h00") @[quasar.scala 525:36] + io.dma_ahb.in.hresp <= _T_56.hresp @[quasar.scala 525:21] + io.dma_ahb.in.hready <= _T_56.hready @[quasar.scala 525:21] + io.dma_ahb.in.hrdata <= _T_56.hrdata @[quasar.scala 525:21] + skip @[quasar.scala 494:15] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 530:20] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} - inst mem of mem @[quasar_wrapper.scala 78:19] + inst mem of mem @[quasar_wrapper.scala 79:19] mem.scan_mode is invalid mem.ic is invalid mem.iccm is invalid @@ -114705,7 +114746,7 @@ circuit quasar_wrapper : mem.dccm_clk_override is invalid mem.rst_l is invalid mem.clk is invalid - inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 79:27] + inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 80:27] dmi_wrapper.dmi_hard_reset is invalid dmi_wrapper.reg_wr_en is invalid dmi_wrapper.reg_en is invalid @@ -114721,282 +114762,298 @@ circuit quasar_wrapper : dmi_wrapper.tms is invalid dmi_wrapper.tck is invalid dmi_wrapper.trst_n is invalid - inst core of quasar @[quasar_wrapper.scala 80:20] - core.clock <= clock - core.reset <= reset - dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25] - dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22] - dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22] - dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22] - dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27] - dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26] - dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26] - dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29] - core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:25] - core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:24] - core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:22] - core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:25] - core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:26] - io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15] - mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 99:28] - mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 100:27] - mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35] - core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15] - core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 102:15] - mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 102:15] - mem.rst_l <= reset @[quasar_wrapper.scala 103:16] - mem.clk <= clock @[quasar_wrapper.scala 104:14] - mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:21] - mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 108:14] - mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 108:14] - mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 108:14] - mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 108:14] - mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 108:14] - mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 108:14] - core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:14] - core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:14] - core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:14] - core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:14] - core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:14] - core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:14] - core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:14] - mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 108:14] - mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 108:14] - mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 108:14] - mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 108:14] - mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 108:14] - mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 108:14] - mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 108:14] - mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 108:14] - core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:16] - core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:16] - mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 109:16] - mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 109:16] - mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 109:16] - mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 109:16] - mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 109:16] - mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:16] - mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 109:16] - core.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:21] - core.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:18] - core.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:20] - core.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:22] - core.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:21] - core.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:22] - core.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:18] - core.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:17] - core.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:21] - core.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:21] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] - core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] - core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] - core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19] - core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26] - core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25] - core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19] - core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30] - core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29] - core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29] - core.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:19] - io.lsu_axi.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:19] - io.lsu_axi.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:19] - core.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:19] - io.ifu_axi.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:19] - io.ifu_axi.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:19] - core.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:18] - io.sb_axi.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:18] - io.sb_axi.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:18] - io.sb_axi.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:18] - io.dma_axi.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:19] - io.dma_axi.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 148:19] - core.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:19] - io.dma_axi.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:19] - io.dma_axi.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:19] - io.dma_axi.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 148:19] - core.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:19] - core.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:20] - core.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:21] - core.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:22] - core.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:25] - core.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:21] - core.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:21] - core.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:22] - core.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:22] - core.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:22] - core.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:24] - core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 162:26] - core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 163:26] - core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 164:26] - core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 165:26] - core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 167:21] - core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 168:20] - core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 169:25] - io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 173:19] - io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 176:21] - io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 177:24] - io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 178:20] - io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 179:26] - io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 181:25] - io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 182:24] - io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 183:25] - io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 185:23] - io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 186:23] - io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 187:23] - io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 188:23] - io.dma_hrdata <= core.io.dma_hrdata @[quasar_wrapper.scala 195:17] - io.dma_hreadyout <= core.io.dma_hreadyout @[quasar_wrapper.scala 196:20] - io.dma_hresp <= core.io.dma_hresp @[quasar_wrapper.scala 197:16] + inst swerv of quasar @[quasar_wrapper.scala 81:21] + swerv.clock <= clock + swerv.reset <= reset + dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 82:25] + dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 83:22] + dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 84:22] + dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 85:22] + dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 86:27] + dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 87:26] + dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 88:26] + dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 91:29] + swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 92:26] + swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 93:25] + swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 94:23] + swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 95:26] + swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 96:27] + io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 97:15] + mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 100:28] + mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 101:27] + mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 102:35] + swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 103:15] + swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 103:15] + mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 103:15] + mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 103:15] + mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 103:15] + mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 103:15] + mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 103:15] + mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 103:15] + mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 103:15] + mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 103:15] + mem.rst_l <= reset @[quasar_wrapper.scala 104:16] + mem.clk <= clock @[quasar_wrapper.scala 105:14] + mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 106:20] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 108:22] + mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 109:15] + mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 109:15] + mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 109:15] + mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 109:15] + mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 109:15] + mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 109:15] + swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 109:15] + swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 109:15] + swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 109:15] + swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 109:15] + swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 109:15] + swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 109:15] + swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 109:15] + mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 109:15] + mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 109:15] + mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 109:15] + mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 109:15] + mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 109:15] + mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 109:15] + mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 109:15] + mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 109:15] + swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 110:17] + swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 110:17] + mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 110:17] + mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 110:17] + mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 110:17] + mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 110:17] + mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 110:17] + mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 110:17] + mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 110:17] + wire _T : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 112:39] + _T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:39] + _T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 112:39] + _T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 112:39] + swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 112:24] + swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 112:24] + swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 112:24] + wire _T_1 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 113:39] + _T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 113:39] + _T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 113:39] + _T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 113:39] + swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 113:24] + swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 113:24] + swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 113:24] + wire _T_2 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 114:39] + _T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:39] + _T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 114:39] + _T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 114:39] + swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 114:24] + swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 114:24] + swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 114:24] + wire _T_3 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 115:34] + _T_3.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 115:34] + _T_3.hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:34] + _T_3.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 115:34] + io.dma_ahb.in.hresp <= _T_3.hresp @[quasar_wrapper.scala 115:19] + io.dma_ahb.in.hready <= _T_3.hready @[quasar_wrapper.scala 115:19] + io.dma_ahb.in.hrdata <= _T_3.hrdata @[quasar_wrapper.scala 115:19] + swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 125:22] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 127:22] + swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 128:20] + swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 129:20] + swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 130:20] + swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 133:27] + swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 134:26] + swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 135:20] + swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 138:31] + swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 139:30] + swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 140:30] + swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 144:20] + io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 144:20] + io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 144:20] + swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 147:20] + io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 147:20] + io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 147:20] + swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 150:19] + io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 150:19] + io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 150:19] + io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 150:19] + io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 154:20] + io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 154:20] + io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 154:20] + io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 154:20] + io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 157:21] + swerv.io.dma_ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar_wrapper.scala 158:24] + swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 167:25] + swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 185:27] + swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 186:27] + swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 187:27] + swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 188:27] + swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 190:22] + swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 191:21] + swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 192:26] + io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 196:19] + io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 199:21] + io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 200:24] + io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 201:20] + io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 202:26] + io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 204:25] + io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 205:24] + io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 206:25] + io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 208:23] + io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 209:23] + io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 210:23] + io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 211:23] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 20146a6a..76a2e207 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -46148,7 +46148,7 @@ module dec_decode_ctl( input io_scan_mode, output io_dec_aln_dec_i0_decode_d, input [15:0] io_dec_aln_ifu_i0_cinst, - input [1:0] io_dbg_dctl_dbg_cmd_wrdata + input [31:0] io_dbg_dctl_dbg_cmd_wrdata ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -57392,418 +57392,418 @@ module dec_trigger( wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[lib.scala 89:14] wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[lib.scala 89:14] wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[lib.scala 89:14] - wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_406 = _GEN_0 & _T_405; // @[dec_trigger.scala 15:109] - wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] - wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] - wire _T_411 = ~_T_410; // @[lib.scala 85:39] - wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[lib.scala 85:37] - wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 86:52] - wire _T_416 = _T_412 | _T_415; // @[lib.scala 86:41] - wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] - wire _T_419 = _T_418 & _T_412; // @[lib.scala 88:41] - wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 88:78] - wire _T_423 = _T_419 | _T_422; // @[lib.scala 88:23] - wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_426 = _T_425 & _T_412; // @[lib.scala 88:41] - wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 88:78] - wire _T_430 = _T_426 | _T_429; // @[lib.scala 88:23] - wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_433 = _T_432 & _T_412; // @[lib.scala 88:41] - wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 88:78] - wire _T_437 = _T_433 | _T_436; // @[lib.scala 88:23] - wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_440 = _T_439 & _T_412; // @[lib.scala 88:41] - wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 88:78] - wire _T_444 = _T_440 | _T_443; // @[lib.scala 88:23] - wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_447 = _T_446 & _T_412; // @[lib.scala 88:41] - wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 88:78] - wire _T_451 = _T_447 | _T_450; // @[lib.scala 88:23] - wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_454 = _T_453 & _T_412; // @[lib.scala 88:41] - wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 88:78] - wire _T_458 = _T_454 | _T_457; // @[lib.scala 88:23] - wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_461 = _T_460 & _T_412; // @[lib.scala 88:41] - wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 88:78] - wire _T_465 = _T_461 | _T_464; // @[lib.scala 88:23] - wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_468 = _T_467 & _T_412; // @[lib.scala 88:41] - wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 88:78] - wire _T_472 = _T_468 | _T_471; // @[lib.scala 88:23] - wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_475 = _T_474 & _T_412; // @[lib.scala 88:41] - wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 88:78] - wire _T_479 = _T_475 | _T_478; // @[lib.scala 88:23] - wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_482 = _T_481 & _T_412; // @[lib.scala 88:41] - wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 88:78] - wire _T_486 = _T_482 | _T_485; // @[lib.scala 88:23] - wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_489 = _T_488 & _T_412; // @[lib.scala 88:41] - wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 88:78] - wire _T_493 = _T_489 | _T_492; // @[lib.scala 88:23] - wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_496 = _T_495 & _T_412; // @[lib.scala 88:41] - wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 88:78] - wire _T_500 = _T_496 | _T_499; // @[lib.scala 88:23] - wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_503 = _T_502 & _T_412; // @[lib.scala 88:41] - wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 88:78] - wire _T_507 = _T_503 | _T_506; // @[lib.scala 88:23] - wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_510 = _T_509 & _T_412; // @[lib.scala 88:41] - wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 88:78] - wire _T_514 = _T_510 | _T_513; // @[lib.scala 88:23] - wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_517 = _T_516 & _T_412; // @[lib.scala 88:41] - wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 88:78] - wire _T_521 = _T_517 | _T_520; // @[lib.scala 88:23] - wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_524 = _T_523 & _T_412; // @[lib.scala 88:41] - wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 88:78] - wire _T_528 = _T_524 | _T_527; // @[lib.scala 88:23] - wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_531 = _T_530 & _T_412; // @[lib.scala 88:41] - wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 88:78] - wire _T_535 = _T_531 | _T_534; // @[lib.scala 88:23] - wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_538 = _T_537 & _T_412; // @[lib.scala 88:41] - wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 88:78] - wire _T_542 = _T_538 | _T_541; // @[lib.scala 88:23] - wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_545 = _T_544 & _T_412; // @[lib.scala 88:41] - wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 88:78] - wire _T_549 = _T_545 | _T_548; // @[lib.scala 88:23] - wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_552 = _T_551 & _T_412; // @[lib.scala 88:41] - wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 88:78] - wire _T_556 = _T_552 | _T_555; // @[lib.scala 88:23] - wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_559 = _T_558 & _T_412; // @[lib.scala 88:41] - wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 88:78] - wire _T_563 = _T_559 | _T_562; // @[lib.scala 88:23] - wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_566 = _T_565 & _T_412; // @[lib.scala 88:41] - wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 88:78] - wire _T_570 = _T_566 | _T_569; // @[lib.scala 88:23] - wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_573 = _T_572 & _T_412; // @[lib.scala 88:41] - wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 88:78] - wire _T_577 = _T_573 | _T_576; // @[lib.scala 88:23] - wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_580 = _T_579 & _T_412; // @[lib.scala 88:41] - wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 88:78] - wire _T_584 = _T_580 | _T_583; // @[lib.scala 88:23] - wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_587 = _T_586 & _T_412; // @[lib.scala 88:41] - wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 88:78] - wire _T_591 = _T_587 | _T_590; // @[lib.scala 88:23] - wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_594 = _T_593 & _T_412; // @[lib.scala 88:41] - wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 88:78] - wire _T_598 = _T_594 | _T_597; // @[lib.scala 88:23] - wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_601 = _T_600 & _T_412; // @[lib.scala 88:41] - wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 88:78] - wire _T_605 = _T_601 | _T_604; // @[lib.scala 88:23] - wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_608 = _T_607 & _T_412; // @[lib.scala 88:41] - wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 88:78] - wire _T_612 = _T_608 | _T_611; // @[lib.scala 88:23] - wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_615 = _T_614 & _T_412; // @[lib.scala 88:41] - wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 88:78] - wire _T_619 = _T_615 | _T_618; // @[lib.scala 88:23] - wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_622 = _T_621 & _T_412; // @[lib.scala 88:41] - wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 88:78] - wire _T_626 = _T_622 | _T_625; // @[lib.scala 88:23] - wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_629 = _T_628 & _T_412; // @[lib.scala 88:41] - wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 88:78] - wire _T_633 = _T_629 | _T_632; // @[lib.scala 88:23] - wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[lib.scala 89:14] - wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[lib.scala 89:14] - wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[lib.scala 89:14] - wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[lib.scala 89:14] - wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_665 = _GEN_1 & _T_664; // @[dec_trigger.scala 15:109] - wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] - wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] - wire _T_670 = ~_T_669; // @[lib.scala 85:39] - wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[lib.scala 85:37] - wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 86:52] - wire _T_675 = _T_671 | _T_674; // @[lib.scala 86:41] - wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] - wire _T_678 = _T_677 & _T_671; // @[lib.scala 88:41] - wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 88:78] - wire _T_682 = _T_678 | _T_681; // @[lib.scala 88:23] - wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_685 = _T_684 & _T_671; // @[lib.scala 88:41] - wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 88:78] - wire _T_689 = _T_685 | _T_688; // @[lib.scala 88:23] - wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_692 = _T_691 & _T_671; // @[lib.scala 88:41] - wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 88:78] - wire _T_696 = _T_692 | _T_695; // @[lib.scala 88:23] - wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_699 = _T_698 & _T_671; // @[lib.scala 88:41] - wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 88:78] - wire _T_703 = _T_699 | _T_702; // @[lib.scala 88:23] - wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_706 = _T_705 & _T_671; // @[lib.scala 88:41] - wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 88:78] - wire _T_710 = _T_706 | _T_709; // @[lib.scala 88:23] - wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_713 = _T_712 & _T_671; // @[lib.scala 88:41] - wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 88:78] - wire _T_717 = _T_713 | _T_716; // @[lib.scala 88:23] - wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_720 = _T_719 & _T_671; // @[lib.scala 88:41] - wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 88:78] - wire _T_724 = _T_720 | _T_723; // @[lib.scala 88:23] - wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_727 = _T_726 & _T_671; // @[lib.scala 88:41] - wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 88:78] - wire _T_731 = _T_727 | _T_730; // @[lib.scala 88:23] - wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_734 = _T_733 & _T_671; // @[lib.scala 88:41] - wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 88:78] - wire _T_738 = _T_734 | _T_737; // @[lib.scala 88:23] - wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_741 = _T_740 & _T_671; // @[lib.scala 88:41] - wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 88:78] - wire _T_745 = _T_741 | _T_744; // @[lib.scala 88:23] - wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_748 = _T_747 & _T_671; // @[lib.scala 88:41] - wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 88:78] - wire _T_752 = _T_748 | _T_751; // @[lib.scala 88:23] - wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_755 = _T_754 & _T_671; // @[lib.scala 88:41] - wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 88:78] - wire _T_759 = _T_755 | _T_758; // @[lib.scala 88:23] - wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_762 = _T_761 & _T_671; // @[lib.scala 88:41] - wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 88:78] - wire _T_766 = _T_762 | _T_765; // @[lib.scala 88:23] - wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_769 = _T_768 & _T_671; // @[lib.scala 88:41] - wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 88:78] - wire _T_773 = _T_769 | _T_772; // @[lib.scala 88:23] - wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_776 = _T_775 & _T_671; // @[lib.scala 88:41] - wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 88:78] - wire _T_780 = _T_776 | _T_779; // @[lib.scala 88:23] - wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_783 = _T_782 & _T_671; // @[lib.scala 88:41] - wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 88:78] - wire _T_787 = _T_783 | _T_786; // @[lib.scala 88:23] - wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_790 = _T_789 & _T_671; // @[lib.scala 88:41] - wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 88:78] - wire _T_794 = _T_790 | _T_793; // @[lib.scala 88:23] - wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_797 = _T_796 & _T_671; // @[lib.scala 88:41] - wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 88:78] - wire _T_801 = _T_797 | _T_800; // @[lib.scala 88:23] - wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_804 = _T_803 & _T_671; // @[lib.scala 88:41] - wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 88:78] - wire _T_808 = _T_804 | _T_807; // @[lib.scala 88:23] - wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_811 = _T_810 & _T_671; // @[lib.scala 88:41] - wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 88:78] - wire _T_815 = _T_811 | _T_814; // @[lib.scala 88:23] - wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_818 = _T_817 & _T_671; // @[lib.scala 88:41] - wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 88:78] - wire _T_822 = _T_818 | _T_821; // @[lib.scala 88:23] - wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_825 = _T_824 & _T_671; // @[lib.scala 88:41] - wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 88:78] - wire _T_829 = _T_825 | _T_828; // @[lib.scala 88:23] - wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_832 = _T_831 & _T_671; // @[lib.scala 88:41] - wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 88:78] - wire _T_836 = _T_832 | _T_835; // @[lib.scala 88:23] - wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_839 = _T_838 & _T_671; // @[lib.scala 88:41] - wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 88:78] - wire _T_843 = _T_839 | _T_842; // @[lib.scala 88:23] - wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_846 = _T_845 & _T_671; // @[lib.scala 88:41] - wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 88:78] - wire _T_850 = _T_846 | _T_849; // @[lib.scala 88:23] - wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_853 = _T_852 & _T_671; // @[lib.scala 88:41] - wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 88:78] - wire _T_857 = _T_853 | _T_856; // @[lib.scala 88:23] - wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_860 = _T_859 & _T_671; // @[lib.scala 88:41] - wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 88:78] - wire _T_864 = _T_860 | _T_863; // @[lib.scala 88:23] - wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_867 = _T_866 & _T_671; // @[lib.scala 88:41] - wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 88:78] - wire _T_871 = _T_867 | _T_870; // @[lib.scala 88:23] - wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_874 = _T_873 & _T_671; // @[lib.scala 88:41] - wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 88:78] - wire _T_878 = _T_874 | _T_877; // @[lib.scala 88:23] - wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_881 = _T_880 & _T_671; // @[lib.scala 88:41] - wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 88:78] - wire _T_885 = _T_881 | _T_884; // @[lib.scala 88:23] - wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_888 = _T_887 & _T_671; // @[lib.scala 88:41] - wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 88:78] - wire _T_892 = _T_888 | _T_891; // @[lib.scala 88:23] - wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[lib.scala 89:14] - wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[lib.scala 89:14] - wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[lib.scala 89:14] - wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[lib.scala 89:14] - wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_924 = _GEN_2 & _T_923; // @[dec_trigger.scala 15:109] - wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] - wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] - wire _T_929 = ~_T_928; // @[lib.scala 85:39] - wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[lib.scala 85:37] - wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 86:52] - wire _T_934 = _T_930 | _T_933; // @[lib.scala 86:41] - wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] - wire _T_937 = _T_936 & _T_930; // @[lib.scala 88:41] - wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 88:78] - wire _T_941 = _T_937 | _T_940; // @[lib.scala 88:23] - wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_944 = _T_943 & _T_930; // @[lib.scala 88:41] - wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 88:78] - wire _T_948 = _T_944 | _T_947; // @[lib.scala 88:23] - wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_951 = _T_950 & _T_930; // @[lib.scala 88:41] - wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 88:78] - wire _T_955 = _T_951 | _T_954; // @[lib.scala 88:23] - wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_958 = _T_957 & _T_930; // @[lib.scala 88:41] - wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 88:78] - wire _T_962 = _T_958 | _T_961; // @[lib.scala 88:23] - wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_965 = _T_964 & _T_930; // @[lib.scala 88:41] - wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 88:78] - wire _T_969 = _T_965 | _T_968; // @[lib.scala 88:23] - wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_972 = _T_971 & _T_930; // @[lib.scala 88:41] - wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 88:78] - wire _T_976 = _T_972 | _T_975; // @[lib.scala 88:23] - wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_979 = _T_978 & _T_930; // @[lib.scala 88:41] - wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 88:78] - wire _T_983 = _T_979 | _T_982; // @[lib.scala 88:23] - wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_986 = _T_985 & _T_930; // @[lib.scala 88:41] - wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 88:78] - wire _T_990 = _T_986 | _T_989; // @[lib.scala 88:23] - wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_993 = _T_992 & _T_930; // @[lib.scala 88:41] - wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 88:78] - wire _T_997 = _T_993 | _T_996; // @[lib.scala 88:23] - wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_1000 = _T_999 & _T_930; // @[lib.scala 88:41] - wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 88:78] - wire _T_1004 = _T_1000 | _T_1003; // @[lib.scala 88:23] - wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_1007 = _T_1006 & _T_930; // @[lib.scala 88:41] - wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 88:78] - wire _T_1011 = _T_1007 | _T_1010; // @[lib.scala 88:23] - wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_1014 = _T_1013 & _T_930; // @[lib.scala 88:41] - wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 88:78] - wire _T_1018 = _T_1014 | _T_1017; // @[lib.scala 88:23] - wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_1021 = _T_1020 & _T_930; // @[lib.scala 88:41] - wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 88:78] - wire _T_1025 = _T_1021 | _T_1024; // @[lib.scala 88:23] - wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_1028 = _T_1027 & _T_930; // @[lib.scala 88:41] - wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 88:78] - wire _T_1032 = _T_1028 | _T_1031; // @[lib.scala 88:23] - wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_1035 = _T_1034 & _T_930; // @[lib.scala 88:41] - wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 88:78] - wire _T_1039 = _T_1035 | _T_1038; // @[lib.scala 88:23] - wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_1042 = _T_1041 & _T_930; // @[lib.scala 88:41] - wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 88:78] - wire _T_1046 = _T_1042 | _T_1045; // @[lib.scala 88:23] - wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_1049 = _T_1048 & _T_930; // @[lib.scala 88:41] - wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 88:78] - wire _T_1053 = _T_1049 | _T_1052; // @[lib.scala 88:23] - wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_1056 = _T_1055 & _T_930; // @[lib.scala 88:41] - wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 88:78] - wire _T_1060 = _T_1056 | _T_1059; // @[lib.scala 88:23] - wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_1063 = _T_1062 & _T_930; // @[lib.scala 88:41] - wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 88:78] - wire _T_1067 = _T_1063 | _T_1066; // @[lib.scala 88:23] - wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_1070 = _T_1069 & _T_930; // @[lib.scala 88:41] - wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 88:78] - wire _T_1074 = _T_1070 | _T_1073; // @[lib.scala 88:23] - wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_1077 = _T_1076 & _T_930; // @[lib.scala 88:41] - wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 88:78] - wire _T_1081 = _T_1077 | _T_1080; // @[lib.scala 88:23] - wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_1084 = _T_1083 & _T_930; // @[lib.scala 88:41] - wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 88:78] - wire _T_1088 = _T_1084 | _T_1087; // @[lib.scala 88:23] - wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_1091 = _T_1090 & _T_930; // @[lib.scala 88:41] - wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 88:78] - wire _T_1095 = _T_1091 | _T_1094; // @[lib.scala 88:23] - wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_1098 = _T_1097 & _T_930; // @[lib.scala 88:41] - wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 88:78] - wire _T_1102 = _T_1098 | _T_1101; // @[lib.scala 88:23] - wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_1105 = _T_1104 & _T_930; // @[lib.scala 88:41] - wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 88:78] - wire _T_1109 = _T_1105 | _T_1108; // @[lib.scala 88:23] - wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_1112 = _T_1111 & _T_930; // @[lib.scala 88:41] - wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 88:78] - wire _T_1116 = _T_1112 | _T_1115; // @[lib.scala 88:23] - wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_1119 = _T_1118 & _T_930; // @[lib.scala 88:41] - wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 88:78] - wire _T_1123 = _T_1119 | _T_1122; // @[lib.scala 88:23] - wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_1126 = _T_1125 & _T_930; // @[lib.scala 88:41] - wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 88:78] - wire _T_1130 = _T_1126 | _T_1129; // @[lib.scala 88:23] - wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_1133 = _T_1132 & _T_930; // @[lib.scala 88:41] - wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 88:78] - wire _T_1137 = _T_1133 | _T_1136; // @[lib.scala 88:23] - wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_1140 = _T_1139 & _T_930; // @[lib.scala 88:41] - wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 88:78] - wire _T_1144 = _T_1140 | _T_1143; // @[lib.scala 88:23] - wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_1147 = _T_1146 & _T_930; // @[lib.scala 88:41] - wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 88:78] - wire _T_1151 = _T_1147 | _T_1150; // @[lib.scala 88:23] - wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[lib.scala 89:14] - wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[lib.scala 89:14] - wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[lib.scala 89:14] - wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[lib.scala 89:14] - wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[dec_trigger.scala 15:109] - wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58] - assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[dec_trigger.scala 15:29] + wire _T_406 = &_T_405; // @[lib.scala 89:25] + wire _T_407 = _T_148 & _T_406; // @[dec_trigger.scala 15:109] + wire _T_408 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] + wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] + wire _T_412 = ~_T_411; // @[lib.scala 85:39] + wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[lib.scala 85:37] + wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 86:52] + wire _T_417 = _T_413 | _T_416; // @[lib.scala 86:41] + wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] + wire _T_420 = _T_419 & _T_413; // @[lib.scala 88:41] + wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 88:78] + wire _T_424 = _T_420 | _T_423; // @[lib.scala 88:23] + wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_427 = _T_426 & _T_413; // @[lib.scala 88:41] + wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 88:78] + wire _T_431 = _T_427 | _T_430; // @[lib.scala 88:23] + wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_434 = _T_433 & _T_413; // @[lib.scala 88:41] + wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 88:78] + wire _T_438 = _T_434 | _T_437; // @[lib.scala 88:23] + wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_441 = _T_440 & _T_413; // @[lib.scala 88:41] + wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 88:78] + wire _T_445 = _T_441 | _T_444; // @[lib.scala 88:23] + wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_448 = _T_447 & _T_413; // @[lib.scala 88:41] + wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 88:78] + wire _T_452 = _T_448 | _T_451; // @[lib.scala 88:23] + wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_455 = _T_454 & _T_413; // @[lib.scala 88:41] + wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 88:78] + wire _T_459 = _T_455 | _T_458; // @[lib.scala 88:23] + wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_462 = _T_461 & _T_413; // @[lib.scala 88:41] + wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 88:78] + wire _T_466 = _T_462 | _T_465; // @[lib.scala 88:23] + wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_469 = _T_468 & _T_413; // @[lib.scala 88:41] + wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 88:78] + wire _T_473 = _T_469 | _T_472; // @[lib.scala 88:23] + wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_476 = _T_475 & _T_413; // @[lib.scala 88:41] + wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 88:78] + wire _T_480 = _T_476 | _T_479; // @[lib.scala 88:23] + wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_483 = _T_482 & _T_413; // @[lib.scala 88:41] + wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 88:78] + wire _T_487 = _T_483 | _T_486; // @[lib.scala 88:23] + wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_490 = _T_489 & _T_413; // @[lib.scala 88:41] + wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 88:78] + wire _T_494 = _T_490 | _T_493; // @[lib.scala 88:23] + wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_497 = _T_496 & _T_413; // @[lib.scala 88:41] + wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 88:78] + wire _T_501 = _T_497 | _T_500; // @[lib.scala 88:23] + wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_504 = _T_503 & _T_413; // @[lib.scala 88:41] + wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 88:78] + wire _T_508 = _T_504 | _T_507; // @[lib.scala 88:23] + wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_511 = _T_510 & _T_413; // @[lib.scala 88:41] + wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 88:78] + wire _T_515 = _T_511 | _T_514; // @[lib.scala 88:23] + wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_518 = _T_517 & _T_413; // @[lib.scala 88:41] + wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 88:78] + wire _T_522 = _T_518 | _T_521; // @[lib.scala 88:23] + wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_525 = _T_524 & _T_413; // @[lib.scala 88:41] + wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 88:78] + wire _T_529 = _T_525 | _T_528; // @[lib.scala 88:23] + wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_532 = _T_531 & _T_413; // @[lib.scala 88:41] + wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 88:78] + wire _T_536 = _T_532 | _T_535; // @[lib.scala 88:23] + wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_539 = _T_538 & _T_413; // @[lib.scala 88:41] + wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 88:78] + wire _T_543 = _T_539 | _T_542; // @[lib.scala 88:23] + wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_546 = _T_545 & _T_413; // @[lib.scala 88:41] + wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 88:78] + wire _T_550 = _T_546 | _T_549; // @[lib.scala 88:23] + wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_553 = _T_552 & _T_413; // @[lib.scala 88:41] + wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 88:78] + wire _T_557 = _T_553 | _T_556; // @[lib.scala 88:23] + wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_560 = _T_559 & _T_413; // @[lib.scala 88:41] + wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 88:78] + wire _T_564 = _T_560 | _T_563; // @[lib.scala 88:23] + wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_567 = _T_566 & _T_413; // @[lib.scala 88:41] + wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 88:78] + wire _T_571 = _T_567 | _T_570; // @[lib.scala 88:23] + wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_574 = _T_573 & _T_413; // @[lib.scala 88:41] + wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 88:78] + wire _T_578 = _T_574 | _T_577; // @[lib.scala 88:23] + wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_581 = _T_580 & _T_413; // @[lib.scala 88:41] + wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 88:78] + wire _T_585 = _T_581 | _T_584; // @[lib.scala 88:23] + wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_588 = _T_587 & _T_413; // @[lib.scala 88:41] + wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 88:78] + wire _T_592 = _T_588 | _T_591; // @[lib.scala 88:23] + wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_595 = _T_594 & _T_413; // @[lib.scala 88:41] + wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 88:78] + wire _T_599 = _T_595 | _T_598; // @[lib.scala 88:23] + wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_602 = _T_601 & _T_413; // @[lib.scala 88:41] + wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 88:78] + wire _T_606 = _T_602 | _T_605; // @[lib.scala 88:23] + wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_609 = _T_608 & _T_413; // @[lib.scala 88:41] + wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 88:78] + wire _T_613 = _T_609 | _T_612; // @[lib.scala 88:23] + wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_616 = _T_615 & _T_413; // @[lib.scala 88:41] + wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 88:78] + wire _T_620 = _T_616 | _T_619; // @[lib.scala 88:23] + wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_623 = _T_622 & _T_413; // @[lib.scala 88:41] + wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 88:78] + wire _T_627 = _T_623 | _T_626; // @[lib.scala 88:23] + wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_630 = _T_629 & _T_413; // @[lib.scala 88:41] + wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 88:78] + wire _T_634 = _T_630 | _T_633; // @[lib.scala 88:23] + wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[lib.scala 89:14] + wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[lib.scala 89:14] + wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[lib.scala 89:14] + wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[lib.scala 89:14] + wire _T_666 = &_T_665; // @[lib.scala 89:25] + wire _T_667 = _T_408 & _T_666; // @[dec_trigger.scala 15:109] + wire _T_668 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] + wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] + wire _T_672 = ~_T_671; // @[lib.scala 85:39] + wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[lib.scala 85:37] + wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 86:52] + wire _T_677 = _T_673 | _T_676; // @[lib.scala 86:41] + wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] + wire _T_680 = _T_679 & _T_673; // @[lib.scala 88:41] + wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 88:78] + wire _T_684 = _T_680 | _T_683; // @[lib.scala 88:23] + wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_687 = _T_686 & _T_673; // @[lib.scala 88:41] + wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 88:78] + wire _T_691 = _T_687 | _T_690; // @[lib.scala 88:23] + wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_694 = _T_693 & _T_673; // @[lib.scala 88:41] + wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 88:78] + wire _T_698 = _T_694 | _T_697; // @[lib.scala 88:23] + wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_701 = _T_700 & _T_673; // @[lib.scala 88:41] + wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 88:78] + wire _T_705 = _T_701 | _T_704; // @[lib.scala 88:23] + wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_708 = _T_707 & _T_673; // @[lib.scala 88:41] + wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 88:78] + wire _T_712 = _T_708 | _T_711; // @[lib.scala 88:23] + wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_715 = _T_714 & _T_673; // @[lib.scala 88:41] + wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 88:78] + wire _T_719 = _T_715 | _T_718; // @[lib.scala 88:23] + wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_722 = _T_721 & _T_673; // @[lib.scala 88:41] + wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 88:78] + wire _T_726 = _T_722 | _T_725; // @[lib.scala 88:23] + wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_729 = _T_728 & _T_673; // @[lib.scala 88:41] + wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 88:78] + wire _T_733 = _T_729 | _T_732; // @[lib.scala 88:23] + wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_736 = _T_735 & _T_673; // @[lib.scala 88:41] + wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 88:78] + wire _T_740 = _T_736 | _T_739; // @[lib.scala 88:23] + wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_743 = _T_742 & _T_673; // @[lib.scala 88:41] + wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 88:78] + wire _T_747 = _T_743 | _T_746; // @[lib.scala 88:23] + wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_750 = _T_749 & _T_673; // @[lib.scala 88:41] + wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 88:78] + wire _T_754 = _T_750 | _T_753; // @[lib.scala 88:23] + wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_757 = _T_756 & _T_673; // @[lib.scala 88:41] + wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 88:78] + wire _T_761 = _T_757 | _T_760; // @[lib.scala 88:23] + wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_764 = _T_763 & _T_673; // @[lib.scala 88:41] + wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 88:78] + wire _T_768 = _T_764 | _T_767; // @[lib.scala 88:23] + wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_771 = _T_770 & _T_673; // @[lib.scala 88:41] + wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 88:78] + wire _T_775 = _T_771 | _T_774; // @[lib.scala 88:23] + wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_778 = _T_777 & _T_673; // @[lib.scala 88:41] + wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 88:78] + wire _T_782 = _T_778 | _T_781; // @[lib.scala 88:23] + wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_785 = _T_784 & _T_673; // @[lib.scala 88:41] + wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 88:78] + wire _T_789 = _T_785 | _T_788; // @[lib.scala 88:23] + wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_792 = _T_791 & _T_673; // @[lib.scala 88:41] + wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 88:78] + wire _T_796 = _T_792 | _T_795; // @[lib.scala 88:23] + wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_799 = _T_798 & _T_673; // @[lib.scala 88:41] + wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 88:78] + wire _T_803 = _T_799 | _T_802; // @[lib.scala 88:23] + wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_806 = _T_805 & _T_673; // @[lib.scala 88:41] + wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 88:78] + wire _T_810 = _T_806 | _T_809; // @[lib.scala 88:23] + wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_813 = _T_812 & _T_673; // @[lib.scala 88:41] + wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 88:78] + wire _T_817 = _T_813 | _T_816; // @[lib.scala 88:23] + wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_820 = _T_819 & _T_673; // @[lib.scala 88:41] + wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 88:78] + wire _T_824 = _T_820 | _T_823; // @[lib.scala 88:23] + wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_827 = _T_826 & _T_673; // @[lib.scala 88:41] + wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 88:78] + wire _T_831 = _T_827 | _T_830; // @[lib.scala 88:23] + wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_834 = _T_833 & _T_673; // @[lib.scala 88:41] + wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 88:78] + wire _T_838 = _T_834 | _T_837; // @[lib.scala 88:23] + wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_841 = _T_840 & _T_673; // @[lib.scala 88:41] + wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 88:78] + wire _T_845 = _T_841 | _T_844; // @[lib.scala 88:23] + wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_848 = _T_847 & _T_673; // @[lib.scala 88:41] + wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 88:78] + wire _T_852 = _T_848 | _T_851; // @[lib.scala 88:23] + wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_855 = _T_854 & _T_673; // @[lib.scala 88:41] + wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 88:78] + wire _T_859 = _T_855 | _T_858; // @[lib.scala 88:23] + wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_862 = _T_861 & _T_673; // @[lib.scala 88:41] + wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 88:78] + wire _T_866 = _T_862 | _T_865; // @[lib.scala 88:23] + wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_869 = _T_868 & _T_673; // @[lib.scala 88:41] + wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 88:78] + wire _T_873 = _T_869 | _T_872; // @[lib.scala 88:23] + wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_876 = _T_875 & _T_673; // @[lib.scala 88:41] + wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 88:78] + wire _T_880 = _T_876 | _T_879; // @[lib.scala 88:23] + wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_883 = _T_882 & _T_673; // @[lib.scala 88:41] + wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 88:78] + wire _T_887 = _T_883 | _T_886; // @[lib.scala 88:23] + wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_890 = _T_889 & _T_673; // @[lib.scala 88:41] + wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 88:78] + wire _T_894 = _T_890 | _T_893; // @[lib.scala 88:23] + wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[lib.scala 89:14] + wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[lib.scala 89:14] + wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[lib.scala 89:14] + wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[lib.scala 89:14] + wire _T_926 = &_T_925; // @[lib.scala 89:25] + wire _T_927 = _T_668 & _T_926; // @[dec_trigger.scala 15:109] + wire _T_928 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] + wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] + wire _T_932 = ~_T_931; // @[lib.scala 85:39] + wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[lib.scala 85:37] + wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 86:52] + wire _T_937 = _T_933 | _T_936; // @[lib.scala 86:41] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] + wire _T_940 = _T_939 & _T_933; // @[lib.scala 88:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 88:78] + wire _T_944 = _T_940 | _T_943; // @[lib.scala 88:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_947 = _T_946 & _T_933; // @[lib.scala 88:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 88:78] + wire _T_951 = _T_947 | _T_950; // @[lib.scala 88:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_954 = _T_953 & _T_933; // @[lib.scala 88:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 88:78] + wire _T_958 = _T_954 | _T_957; // @[lib.scala 88:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_961 = _T_960 & _T_933; // @[lib.scala 88:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 88:78] + wire _T_965 = _T_961 | _T_964; // @[lib.scala 88:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_968 = _T_967 & _T_933; // @[lib.scala 88:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 88:78] + wire _T_972 = _T_968 | _T_971; // @[lib.scala 88:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_975 = _T_974 & _T_933; // @[lib.scala 88:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 88:78] + wire _T_979 = _T_975 | _T_978; // @[lib.scala 88:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_982 = _T_981 & _T_933; // @[lib.scala 88:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 88:78] + wire _T_986 = _T_982 | _T_985; // @[lib.scala 88:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_989 = _T_988 & _T_933; // @[lib.scala 88:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 88:78] + wire _T_993 = _T_989 | _T_992; // @[lib.scala 88:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_996 = _T_995 & _T_933; // @[lib.scala 88:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 88:78] + wire _T_1000 = _T_996 | _T_999; // @[lib.scala 88:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_1003 = _T_1002 & _T_933; // @[lib.scala 88:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 88:78] + wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 88:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_1010 = _T_1009 & _T_933; // @[lib.scala 88:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 88:78] + wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 88:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_1017 = _T_1016 & _T_933; // @[lib.scala 88:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 88:78] + wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 88:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_1024 = _T_1023 & _T_933; // @[lib.scala 88:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 88:78] + wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 88:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_1031 = _T_1030 & _T_933; // @[lib.scala 88:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 88:78] + wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 88:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_1038 = _T_1037 & _T_933; // @[lib.scala 88:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 88:78] + wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 88:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_1045 = _T_1044 & _T_933; // @[lib.scala 88:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 88:78] + wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 88:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_1052 = _T_1051 & _T_933; // @[lib.scala 88:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 88:78] + wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 88:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_1059 = _T_1058 & _T_933; // @[lib.scala 88:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 88:78] + wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 88:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_1066 = _T_1065 & _T_933; // @[lib.scala 88:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 88:78] + wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 88:23] + wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_1073 = _T_1072 & _T_933; // @[lib.scala 88:41] + wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 88:78] + wire _T_1077 = _T_1073 | _T_1076; // @[lib.scala 88:23] + wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_1080 = _T_1079 & _T_933; // @[lib.scala 88:41] + wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 88:78] + wire _T_1084 = _T_1080 | _T_1083; // @[lib.scala 88:23] + wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_1087 = _T_1086 & _T_933; // @[lib.scala 88:41] + wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 88:78] + wire _T_1091 = _T_1087 | _T_1090; // @[lib.scala 88:23] + wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_1094 = _T_1093 & _T_933; // @[lib.scala 88:41] + wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 88:78] + wire _T_1098 = _T_1094 | _T_1097; // @[lib.scala 88:23] + wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_1101 = _T_1100 & _T_933; // @[lib.scala 88:41] + wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 88:78] + wire _T_1105 = _T_1101 | _T_1104; // @[lib.scala 88:23] + wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_1108 = _T_1107 & _T_933; // @[lib.scala 88:41] + wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 88:78] + wire _T_1112 = _T_1108 | _T_1111; // @[lib.scala 88:23] + wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_1115 = _T_1114 & _T_933; // @[lib.scala 88:41] + wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 88:78] + wire _T_1119 = _T_1115 | _T_1118; // @[lib.scala 88:23] + wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_1122 = _T_1121 & _T_933; // @[lib.scala 88:41] + wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 88:78] + wire _T_1126 = _T_1122 | _T_1125; // @[lib.scala 88:23] + wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_1129 = _T_1128 & _T_933; // @[lib.scala 88:41] + wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 88:78] + wire _T_1133 = _T_1129 | _T_1132; // @[lib.scala 88:23] + wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_1136 = _T_1135 & _T_933; // @[lib.scala 88:41] + wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 88:78] + wire _T_1140 = _T_1136 | _T_1139; // @[lib.scala 88:23] + wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_1143 = _T_1142 & _T_933; // @[lib.scala 88:41] + wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 88:78] + wire _T_1147 = _T_1143 | _T_1146; // @[lib.scala 88:23] + wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_1150 = _T_1149 & _T_933; // @[lib.scala 88:41] + wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 88:78] + wire _T_1154 = _T_1150 | _T_1153; // @[lib.scala 88:23] + wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[lib.scala 89:14] + wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[lib.scala 89:14] + wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[lib.scala 89:14] + wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[lib.scala 89:14] + wire _T_1186 = &_T_1185; // @[lib.scala 89:25] + wire _T_1187 = _T_928 & _T_1186; // @[dec_trigger.scala 15:109] + wire [2:0] _T_1189 = {_T_1187,_T_927,_T_667}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = {_T_1189,_T_407}; // @[dec_trigger.scala 15:29] endmodule module dec( input clock, @@ -58063,7 +58063,7 @@ module dec( input io_dec_dbg_dbg_ib_dbg_cmd_write, input [1:0] io_dec_dbg_dbg_ib_dbg_cmd_type, input [31:0] io_dec_dbg_dbg_ib_dbg_cmd_addr, - input [1:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, + input [31:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, input io_dec_dma_dctl_dma_dma_dccm_stall_any, input io_dec_dma_tlu_dma_dma_pmu_dccm_read, input io_dec_dma_tlu_dma_dma_pmu_dccm_write, @@ -58292,7 +58292,7 @@ module dec( wire decode_io_scan_mode; // @[dec.scala 118:22] wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] - wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] + wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire gpr_clock; // @[dec.scala 119:19] wire gpr_reset; // @[dec.scala 119:19] wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19] @@ -59408,12 +59408,12 @@ module dbg( output io_dbg_dec_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_dbg_ib_dbg_cmd_valid, output io_dbg_dma_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_io_dbg_dma_bubble, input io_dbg_dma_io_dma_dbg_ready, input io_dbg_bus_clk_en, @@ -59952,7 +59952,7 @@ module dbg( assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] - assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg[1:0]; // @[dbg.scala 325:38] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] @@ -67327,430 +67327,430 @@ module lsu_trigger( wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[lib.scala 89:14] wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[lib.scala 89:14] wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[lib.scala 89:14] - wire [31:0] _GEN_0 = {{31'd0}, _T_46}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_304 = _GEN_0 & _T_303; // @[lsu_trigger.scala 19:92] - wire _T_307 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_308 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_310 = _T_308 & _T_19; // @[lsu_trigger.scala 19:58] - wire _T_311 = _T_307 | _T_310; // @[lsu_trigger.scala 18:152] - wire _T_312 = _T_40 & _T_311; // @[lsu_trigger.scala 18:94] - wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] - wire _T_316 = ~_T_315; // @[lib.scala 85:39] - wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[lib.scala 85:37] - wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 86:52] - wire _T_321 = _T_317 | _T_320; // @[lib.scala 86:41] - wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] - wire _T_324 = _T_323 & _T_317; // @[lib.scala 88:41] - wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 88:78] - wire _T_328 = _T_324 | _T_327; // @[lib.scala 88:23] - wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_331 = _T_330 & _T_317; // @[lib.scala 88:41] - wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 88:78] - wire _T_335 = _T_331 | _T_334; // @[lib.scala 88:23] - wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_338 = _T_337 & _T_317; // @[lib.scala 88:41] - wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 88:78] - wire _T_342 = _T_338 | _T_341; // @[lib.scala 88:23] - wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_345 = _T_344 & _T_317; // @[lib.scala 88:41] - wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 88:78] - wire _T_349 = _T_345 | _T_348; // @[lib.scala 88:23] - wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_352 = _T_351 & _T_317; // @[lib.scala 88:41] - wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 88:78] - wire _T_356 = _T_352 | _T_355; // @[lib.scala 88:23] - wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_359 = _T_358 & _T_317; // @[lib.scala 88:41] - wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 88:78] - wire _T_363 = _T_359 | _T_362; // @[lib.scala 88:23] - wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_366 = _T_365 & _T_317; // @[lib.scala 88:41] - wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 88:78] - wire _T_370 = _T_366 | _T_369; // @[lib.scala 88:23] - wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_373 = _T_372 & _T_317; // @[lib.scala 88:41] - wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 88:78] - wire _T_377 = _T_373 | _T_376; // @[lib.scala 88:23] - wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_380 = _T_379 & _T_317; // @[lib.scala 88:41] - wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 88:78] - wire _T_384 = _T_380 | _T_383; // @[lib.scala 88:23] - wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_387 = _T_386 & _T_317; // @[lib.scala 88:41] - wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 88:78] - wire _T_391 = _T_387 | _T_390; // @[lib.scala 88:23] - wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_394 = _T_393 & _T_317; // @[lib.scala 88:41] - wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 88:78] - wire _T_398 = _T_394 | _T_397; // @[lib.scala 88:23] - wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_401 = _T_400 & _T_317; // @[lib.scala 88:41] - wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 88:78] - wire _T_405 = _T_401 | _T_404; // @[lib.scala 88:23] - wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_408 = _T_407 & _T_317; // @[lib.scala 88:41] - wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 88:78] - wire _T_412 = _T_408 | _T_411; // @[lib.scala 88:23] - wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_415 = _T_414 & _T_317; // @[lib.scala 88:41] - wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 88:78] - wire _T_419 = _T_415 | _T_418; // @[lib.scala 88:23] - wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_422 = _T_421 & _T_317; // @[lib.scala 88:41] - wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 88:78] - wire _T_426 = _T_422 | _T_425; // @[lib.scala 88:23] - wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_429 = _T_428 & _T_317; // @[lib.scala 88:41] - wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 88:78] - wire _T_433 = _T_429 | _T_432; // @[lib.scala 88:23] - wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_436 = _T_435 & _T_317; // @[lib.scala 88:41] - wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 88:78] - wire _T_440 = _T_436 | _T_439; // @[lib.scala 88:23] - wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_443 = _T_442 & _T_317; // @[lib.scala 88:41] - wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 88:78] - wire _T_447 = _T_443 | _T_446; // @[lib.scala 88:23] - wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_450 = _T_449 & _T_317; // @[lib.scala 88:41] - wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 88:78] - wire _T_454 = _T_450 | _T_453; // @[lib.scala 88:23] - wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_457 = _T_456 & _T_317; // @[lib.scala 88:41] - wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 88:78] - wire _T_461 = _T_457 | _T_460; // @[lib.scala 88:23] - wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_464 = _T_463 & _T_317; // @[lib.scala 88:41] - wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 88:78] - wire _T_468 = _T_464 | _T_467; // @[lib.scala 88:23] - wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_471 = _T_470 & _T_317; // @[lib.scala 88:41] - wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 88:78] - wire _T_475 = _T_471 | _T_474; // @[lib.scala 88:23] - wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_478 = _T_477 & _T_317; // @[lib.scala 88:41] - wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 88:78] - wire _T_482 = _T_478 | _T_481; // @[lib.scala 88:23] - wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_485 = _T_484 & _T_317; // @[lib.scala 88:41] - wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 88:78] - wire _T_489 = _T_485 | _T_488; // @[lib.scala 88:23] - wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_492 = _T_491 & _T_317; // @[lib.scala 88:41] - wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 88:78] - wire _T_496 = _T_492 | _T_495; // @[lib.scala 88:23] - wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_499 = _T_498 & _T_317; // @[lib.scala 88:41] - wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 88:78] - wire _T_503 = _T_499 | _T_502; // @[lib.scala 88:23] - wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_506 = _T_505 & _T_317; // @[lib.scala 88:41] - wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 88:78] - wire _T_510 = _T_506 | _T_509; // @[lib.scala 88:23] - wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_513 = _T_512 & _T_317; // @[lib.scala 88:41] - wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 88:78] - wire _T_517 = _T_513 | _T_516; // @[lib.scala 88:23] - wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_520 = _T_519 & _T_317; // @[lib.scala 88:41] - wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 88:78] - wire _T_524 = _T_520 | _T_523; // @[lib.scala 88:23] - wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_527 = _T_526 & _T_317; // @[lib.scala 88:41] - wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 88:78] - wire _T_531 = _T_527 | _T_530; // @[lib.scala 88:23] - wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_534 = _T_533 & _T_317; // @[lib.scala 88:41] - wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 88:78] - wire _T_538 = _T_534 | _T_537; // @[lib.scala 88:23] - wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[lib.scala 89:14] - wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[lib.scala 89:14] - wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[lib.scala 89:14] - wire [31:0] _T_569 = {_T_538,_T_531,_T_524,_T_517,_T_510,_T_503,_T_496,_T_489,_T_560,_T_553}; // @[lib.scala 89:14] - wire [31:0] _GEN_1 = {{31'd0}, _T_312}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_570 = _GEN_1 & _T_569; // @[lsu_trigger.scala 19:92] - wire _T_573 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_574 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_576 = _T_574 & _T_26; // @[lsu_trigger.scala 19:58] - wire _T_577 = _T_573 | _T_576; // @[lsu_trigger.scala 18:152] - wire _T_578 = _T_40 & _T_577; // @[lsu_trigger.scala 18:94] - wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] - wire _T_582 = ~_T_581; // @[lib.scala 85:39] - wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[lib.scala 85:37] - wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 86:52] - wire _T_587 = _T_583 | _T_586; // @[lib.scala 86:41] - wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] - wire _T_590 = _T_589 & _T_583; // @[lib.scala 88:41] - wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 88:78] - wire _T_594 = _T_590 | _T_593; // @[lib.scala 88:23] - wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_597 = _T_596 & _T_583; // @[lib.scala 88:41] - wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 88:78] - wire _T_601 = _T_597 | _T_600; // @[lib.scala 88:23] - wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_604 = _T_603 & _T_583; // @[lib.scala 88:41] - wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 88:78] - wire _T_608 = _T_604 | _T_607; // @[lib.scala 88:23] - wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_611 = _T_610 & _T_583; // @[lib.scala 88:41] - wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 88:78] - wire _T_615 = _T_611 | _T_614; // @[lib.scala 88:23] - wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_618 = _T_617 & _T_583; // @[lib.scala 88:41] - wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 88:78] - wire _T_622 = _T_618 | _T_621; // @[lib.scala 88:23] - wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_625 = _T_624 & _T_583; // @[lib.scala 88:41] - wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 88:78] - wire _T_629 = _T_625 | _T_628; // @[lib.scala 88:23] - wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_632 = _T_631 & _T_583; // @[lib.scala 88:41] - wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 88:78] - wire _T_636 = _T_632 | _T_635; // @[lib.scala 88:23] - wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_639 = _T_638 & _T_583; // @[lib.scala 88:41] - wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 88:78] - wire _T_643 = _T_639 | _T_642; // @[lib.scala 88:23] - wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_646 = _T_645 & _T_583; // @[lib.scala 88:41] - wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 88:78] - wire _T_650 = _T_646 | _T_649; // @[lib.scala 88:23] - wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_653 = _T_652 & _T_583; // @[lib.scala 88:41] - wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 88:78] - wire _T_657 = _T_653 | _T_656; // @[lib.scala 88:23] - wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_660 = _T_659 & _T_583; // @[lib.scala 88:41] - wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 88:78] - wire _T_664 = _T_660 | _T_663; // @[lib.scala 88:23] - wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_667 = _T_666 & _T_583; // @[lib.scala 88:41] - wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 88:78] - wire _T_671 = _T_667 | _T_670; // @[lib.scala 88:23] - wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_674 = _T_673 & _T_583; // @[lib.scala 88:41] - wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 88:78] - wire _T_678 = _T_674 | _T_677; // @[lib.scala 88:23] - wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_681 = _T_680 & _T_583; // @[lib.scala 88:41] - wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 88:78] - wire _T_685 = _T_681 | _T_684; // @[lib.scala 88:23] - wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_688 = _T_687 & _T_583; // @[lib.scala 88:41] - wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 88:78] - wire _T_692 = _T_688 | _T_691; // @[lib.scala 88:23] - wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_695 = _T_694 & _T_583; // @[lib.scala 88:41] - wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 88:78] - wire _T_699 = _T_695 | _T_698; // @[lib.scala 88:23] - wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_702 = _T_701 & _T_583; // @[lib.scala 88:41] - wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 88:78] - wire _T_706 = _T_702 | _T_705; // @[lib.scala 88:23] - wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_709 = _T_708 & _T_583; // @[lib.scala 88:41] - wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 88:78] - wire _T_713 = _T_709 | _T_712; // @[lib.scala 88:23] - wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_716 = _T_715 & _T_583; // @[lib.scala 88:41] - wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 88:78] - wire _T_720 = _T_716 | _T_719; // @[lib.scala 88:23] - wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_723 = _T_722 & _T_583; // @[lib.scala 88:41] - wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 88:78] - wire _T_727 = _T_723 | _T_726; // @[lib.scala 88:23] - wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_730 = _T_729 & _T_583; // @[lib.scala 88:41] - wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 88:78] - wire _T_734 = _T_730 | _T_733; // @[lib.scala 88:23] - wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_737 = _T_736 & _T_583; // @[lib.scala 88:41] - wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 88:78] - wire _T_741 = _T_737 | _T_740; // @[lib.scala 88:23] - wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_744 = _T_743 & _T_583; // @[lib.scala 88:41] - wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 88:78] - wire _T_748 = _T_744 | _T_747; // @[lib.scala 88:23] - wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_751 = _T_750 & _T_583; // @[lib.scala 88:41] - wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 88:78] - wire _T_755 = _T_751 | _T_754; // @[lib.scala 88:23] - wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_758 = _T_757 & _T_583; // @[lib.scala 88:41] - wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 88:78] - wire _T_762 = _T_758 | _T_761; // @[lib.scala 88:23] - wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_765 = _T_764 & _T_583; // @[lib.scala 88:41] - wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 88:78] - wire _T_769 = _T_765 | _T_768; // @[lib.scala 88:23] - wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_772 = _T_771 & _T_583; // @[lib.scala 88:41] - wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 88:78] - wire _T_776 = _T_772 | _T_775; // @[lib.scala 88:23] - wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_779 = _T_778 & _T_583; // @[lib.scala 88:41] - wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 88:78] - wire _T_783 = _T_779 | _T_782; // @[lib.scala 88:23] - wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_786 = _T_785 & _T_583; // @[lib.scala 88:41] - wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 88:78] - wire _T_790 = _T_786 | _T_789; // @[lib.scala 88:23] - wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_793 = _T_792 & _T_583; // @[lib.scala 88:41] - wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 88:78] - wire _T_797 = _T_793 | _T_796; // @[lib.scala 88:23] - wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_800 = _T_799 & _T_583; // @[lib.scala 88:41] - wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 88:78] - wire _T_804 = _T_800 | _T_803; // @[lib.scala 88:23] - wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[lib.scala 89:14] - wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[lib.scala 89:14] - wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[lib.scala 89:14] - wire [31:0] _T_835 = {_T_804,_T_797,_T_790,_T_783,_T_776,_T_769,_T_762,_T_755,_T_826,_T_819}; // @[lib.scala 89:14] - wire [31:0] _GEN_2 = {{31'd0}, _T_578}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_836 = _GEN_2 & _T_835; // @[lsu_trigger.scala 19:92] - wire _T_839 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_840 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_842 = _T_840 & _T_33; // @[lsu_trigger.scala 19:58] - wire _T_843 = _T_839 | _T_842; // @[lsu_trigger.scala 18:152] - wire _T_844 = _T_40 & _T_843; // @[lsu_trigger.scala 18:94] - wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] - wire _T_848 = ~_T_847; // @[lib.scala 85:39] - wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[lib.scala 85:37] - wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 86:52] - wire _T_853 = _T_849 | _T_852; // @[lib.scala 86:41] - wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] - wire _T_856 = _T_855 & _T_849; // @[lib.scala 88:41] - wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 88:78] - wire _T_860 = _T_856 | _T_859; // @[lib.scala 88:23] - wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_863 = _T_862 & _T_849; // @[lib.scala 88:41] - wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 88:78] - wire _T_867 = _T_863 | _T_866; // @[lib.scala 88:23] - wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_870 = _T_869 & _T_849; // @[lib.scala 88:41] - wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 88:78] - wire _T_874 = _T_870 | _T_873; // @[lib.scala 88:23] - wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_877 = _T_876 & _T_849; // @[lib.scala 88:41] - wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 88:78] - wire _T_881 = _T_877 | _T_880; // @[lib.scala 88:23] - wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_884 = _T_883 & _T_849; // @[lib.scala 88:41] - wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 88:78] - wire _T_888 = _T_884 | _T_887; // @[lib.scala 88:23] - wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_891 = _T_890 & _T_849; // @[lib.scala 88:41] - wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 88:78] - wire _T_895 = _T_891 | _T_894; // @[lib.scala 88:23] - wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_898 = _T_897 & _T_849; // @[lib.scala 88:41] - wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 88:78] - wire _T_902 = _T_898 | _T_901; // @[lib.scala 88:23] - wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_905 = _T_904 & _T_849; // @[lib.scala 88:41] - wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 88:78] - wire _T_909 = _T_905 | _T_908; // @[lib.scala 88:23] - wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_912 = _T_911 & _T_849; // @[lib.scala 88:41] - wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 88:78] - wire _T_916 = _T_912 | _T_915; // @[lib.scala 88:23] - wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_919 = _T_918 & _T_849; // @[lib.scala 88:41] - wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 88:78] - wire _T_923 = _T_919 | _T_922; // @[lib.scala 88:23] - wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_926 = _T_925 & _T_849; // @[lib.scala 88:41] - wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 88:78] - wire _T_930 = _T_926 | _T_929; // @[lib.scala 88:23] - wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_933 = _T_932 & _T_849; // @[lib.scala 88:41] - wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 88:78] - wire _T_937 = _T_933 | _T_936; // @[lib.scala 88:23] - wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_940 = _T_939 & _T_849; // @[lib.scala 88:41] - wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 88:78] - wire _T_944 = _T_940 | _T_943; // @[lib.scala 88:23] - wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_947 = _T_946 & _T_849; // @[lib.scala 88:41] - wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 88:78] - wire _T_951 = _T_947 | _T_950; // @[lib.scala 88:23] - wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_954 = _T_953 & _T_849; // @[lib.scala 88:41] - wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 88:78] - wire _T_958 = _T_954 | _T_957; // @[lib.scala 88:23] - wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_961 = _T_960 & _T_849; // @[lib.scala 88:41] - wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 88:78] - wire _T_965 = _T_961 | _T_964; // @[lib.scala 88:23] - wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_968 = _T_967 & _T_849; // @[lib.scala 88:41] - wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 88:78] - wire _T_972 = _T_968 | _T_971; // @[lib.scala 88:23] - wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_975 = _T_974 & _T_849; // @[lib.scala 88:41] - wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 88:78] - wire _T_979 = _T_975 | _T_978; // @[lib.scala 88:23] - wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_982 = _T_981 & _T_849; // @[lib.scala 88:41] - wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 88:78] - wire _T_986 = _T_982 | _T_985; // @[lib.scala 88:23] - wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_989 = _T_988 & _T_849; // @[lib.scala 88:41] - wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 88:78] - wire _T_993 = _T_989 | _T_992; // @[lib.scala 88:23] - wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_996 = _T_995 & _T_849; // @[lib.scala 88:41] - wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 88:78] - wire _T_1000 = _T_996 | _T_999; // @[lib.scala 88:23] - wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_1003 = _T_1002 & _T_849; // @[lib.scala 88:41] - wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 88:78] - wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 88:23] - wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_1010 = _T_1009 & _T_849; // @[lib.scala 88:41] - wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 88:78] - wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 88:23] - wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_1017 = _T_1016 & _T_849; // @[lib.scala 88:41] - wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 88:78] - wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 88:23] - wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_1024 = _T_1023 & _T_849; // @[lib.scala 88:41] - wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 88:78] - wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 88:23] - wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_1031 = _T_1030 & _T_849; // @[lib.scala 88:41] - wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 88:78] - wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 88:23] - wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_1038 = _T_1037 & _T_849; // @[lib.scala 88:41] - wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 88:78] - wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 88:23] - wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_1045 = _T_1044 & _T_849; // @[lib.scala 88:41] - wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 88:78] - wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 88:23] - wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_1052 = _T_1051 & _T_849; // @[lib.scala 88:41] - wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 88:78] - wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 88:23] - wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_1059 = _T_1058 & _T_849; // @[lib.scala 88:41] - wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 88:78] - wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 88:23] - wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_1066 = _T_1065 & _T_849; // @[lib.scala 88:41] - wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 88:78] - wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 88:23] - wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[lib.scala 89:14] - wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[lib.scala 89:14] - wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[lib.scala 89:14] - wire [31:0] _T_1101 = {_T_1070,_T_1063,_T_1056,_T_1049,_T_1042,_T_1035,_T_1028,_T_1021,_T_1092,_T_1085}; // @[lib.scala 89:14] - wire [31:0] _GEN_3 = {{31'd0}, _T_844}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_1102 = _GEN_3 & _T_1101; // @[lsu_trigger.scala 19:92] - wire [127:0] _T_1105 = {_T_1102,_T_836,_T_570,_T_304}; // @[Cat.scala 29:58] - assign io_lsu_trigger_match_m = _T_1105[3:0]; // @[lsu_trigger.scala 18:26] + wire _T_304 = &_T_303; // @[lib.scala 89:25] + wire _T_305 = _T_46 & _T_304; // @[lsu_trigger.scala 19:92] + wire _T_308 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_309 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_311 = _T_309 & _T_19; // @[lsu_trigger.scala 19:58] + wire _T_312 = _T_308 | _T_311; // @[lsu_trigger.scala 18:152] + wire _T_313 = _T_40 & _T_312; // @[lsu_trigger.scala 18:94] + wire _T_316 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] + wire _T_317 = ~_T_316; // @[lib.scala 85:39] + wire _T_318 = io_trigger_pkt_any_1_match_pkt & _T_317; // @[lib.scala 85:37] + wire _T_321 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 86:52] + wire _T_322 = _T_318 | _T_321; // @[lib.scala 86:41] + wire _T_324 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] + wire _T_325 = _T_324 & _T_318; // @[lib.scala 88:41] + wire _T_328 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 88:78] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 88:23] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_332 = _T_331 & _T_318; // @[lib.scala 88:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 88:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 88:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_339 = _T_338 & _T_318; // @[lib.scala 88:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 88:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 88:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_346 = _T_345 & _T_318; // @[lib.scala 88:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 88:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 88:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_353 = _T_352 & _T_318; // @[lib.scala 88:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 88:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 88:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_360 = _T_359 & _T_318; // @[lib.scala 88:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 88:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 88:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_367 = _T_366 & _T_318; // @[lib.scala 88:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 88:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 88:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_374 = _T_373 & _T_318; // @[lib.scala 88:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 88:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 88:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_381 = _T_380 & _T_318; // @[lib.scala 88:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 88:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 88:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_388 = _T_387 & _T_318; // @[lib.scala 88:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 88:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 88:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_395 = _T_394 & _T_318; // @[lib.scala 88:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 88:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 88:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_402 = _T_401 & _T_318; // @[lib.scala 88:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 88:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 88:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_409 = _T_408 & _T_318; // @[lib.scala 88:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 88:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 88:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_416 = _T_415 & _T_318; // @[lib.scala 88:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 88:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 88:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_423 = _T_422 & _T_318; // @[lib.scala 88:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 88:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 88:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_430 = _T_429 & _T_318; // @[lib.scala 88:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 88:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 88:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_437 = _T_436 & _T_318; // @[lib.scala 88:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 88:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 88:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_444 = _T_443 & _T_318; // @[lib.scala 88:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 88:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 88:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_451 = _T_450 & _T_318; // @[lib.scala 88:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 88:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 88:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_458 = _T_457 & _T_318; // @[lib.scala 88:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 88:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 88:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_465 = _T_464 & _T_318; // @[lib.scala 88:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 88:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 88:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_472 = _T_471 & _T_318; // @[lib.scala 88:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 88:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 88:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_479 = _T_478 & _T_318; // @[lib.scala 88:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 88:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 88:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_486 = _T_485 & _T_318; // @[lib.scala 88:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 88:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 88:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_493 = _T_492 & _T_318; // @[lib.scala 88:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 88:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 88:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_500 = _T_499 & _T_318; // @[lib.scala 88:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 88:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 88:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_507 = _T_506 & _T_318; // @[lib.scala 88:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 88:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 88:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_514 = _T_513 & _T_318; // @[lib.scala 88:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 88:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 88:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_521 = _T_520 & _T_318; // @[lib.scala 88:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 88:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 88:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_528 = _T_527 & _T_318; // @[lib.scala 88:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 88:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 88:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_535 = _T_534 & _T_318; // @[lib.scala 88:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 88:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 88:23] + wire [7:0] _T_546 = {_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329,_T_322}; // @[lib.scala 89:14] + wire [15:0] _T_554 = {_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_378,_T_546}; // @[lib.scala 89:14] + wire [7:0] _T_561 = {_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441,_T_434}; // @[lib.scala 89:14] + wire [31:0] _T_570 = {_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_490,_T_561,_T_554}; // @[lib.scala 89:14] + wire _T_571 = &_T_570; // @[lib.scala 89:25] + wire _T_572 = _T_313 & _T_571; // @[lsu_trigger.scala 19:92] + wire _T_575 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_576 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_578 = _T_576 & _T_26; // @[lsu_trigger.scala 19:58] + wire _T_579 = _T_575 | _T_578; // @[lsu_trigger.scala 18:152] + wire _T_580 = _T_40 & _T_579; // @[lsu_trigger.scala 18:94] + wire _T_583 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] + wire _T_584 = ~_T_583; // @[lib.scala 85:39] + wire _T_585 = io_trigger_pkt_any_2_match_pkt & _T_584; // @[lib.scala 85:37] + wire _T_588 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 86:52] + wire _T_589 = _T_585 | _T_588; // @[lib.scala 86:41] + wire _T_591 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] + wire _T_592 = _T_591 & _T_585; // @[lib.scala 88:41] + wire _T_595 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 88:78] + wire _T_596 = _T_592 | _T_595; // @[lib.scala 88:23] + wire _T_598 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_599 = _T_598 & _T_585; // @[lib.scala 88:41] + wire _T_602 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 88:78] + wire _T_603 = _T_599 | _T_602; // @[lib.scala 88:23] + wire _T_605 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_606 = _T_605 & _T_585; // @[lib.scala 88:41] + wire _T_609 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 88:78] + wire _T_610 = _T_606 | _T_609; // @[lib.scala 88:23] + wire _T_612 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_613 = _T_612 & _T_585; // @[lib.scala 88:41] + wire _T_616 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 88:78] + wire _T_617 = _T_613 | _T_616; // @[lib.scala 88:23] + wire _T_619 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_620 = _T_619 & _T_585; // @[lib.scala 88:41] + wire _T_623 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 88:78] + wire _T_624 = _T_620 | _T_623; // @[lib.scala 88:23] + wire _T_626 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_627 = _T_626 & _T_585; // @[lib.scala 88:41] + wire _T_630 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 88:78] + wire _T_631 = _T_627 | _T_630; // @[lib.scala 88:23] + wire _T_633 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_634 = _T_633 & _T_585; // @[lib.scala 88:41] + wire _T_637 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 88:78] + wire _T_638 = _T_634 | _T_637; // @[lib.scala 88:23] + wire _T_640 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_641 = _T_640 & _T_585; // @[lib.scala 88:41] + wire _T_644 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 88:78] + wire _T_645 = _T_641 | _T_644; // @[lib.scala 88:23] + wire _T_647 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_648 = _T_647 & _T_585; // @[lib.scala 88:41] + wire _T_651 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 88:78] + wire _T_652 = _T_648 | _T_651; // @[lib.scala 88:23] + wire _T_654 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_655 = _T_654 & _T_585; // @[lib.scala 88:41] + wire _T_658 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 88:78] + wire _T_659 = _T_655 | _T_658; // @[lib.scala 88:23] + wire _T_661 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_662 = _T_661 & _T_585; // @[lib.scala 88:41] + wire _T_665 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 88:78] + wire _T_666 = _T_662 | _T_665; // @[lib.scala 88:23] + wire _T_668 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_669 = _T_668 & _T_585; // @[lib.scala 88:41] + wire _T_672 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 88:78] + wire _T_673 = _T_669 | _T_672; // @[lib.scala 88:23] + wire _T_675 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_676 = _T_675 & _T_585; // @[lib.scala 88:41] + wire _T_679 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 88:78] + wire _T_680 = _T_676 | _T_679; // @[lib.scala 88:23] + wire _T_682 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_683 = _T_682 & _T_585; // @[lib.scala 88:41] + wire _T_686 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 88:78] + wire _T_687 = _T_683 | _T_686; // @[lib.scala 88:23] + wire _T_689 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_690 = _T_689 & _T_585; // @[lib.scala 88:41] + wire _T_693 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 88:78] + wire _T_694 = _T_690 | _T_693; // @[lib.scala 88:23] + wire _T_696 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_697 = _T_696 & _T_585; // @[lib.scala 88:41] + wire _T_700 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 88:78] + wire _T_701 = _T_697 | _T_700; // @[lib.scala 88:23] + wire _T_703 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_704 = _T_703 & _T_585; // @[lib.scala 88:41] + wire _T_707 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 88:78] + wire _T_708 = _T_704 | _T_707; // @[lib.scala 88:23] + wire _T_710 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_711 = _T_710 & _T_585; // @[lib.scala 88:41] + wire _T_714 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 88:78] + wire _T_715 = _T_711 | _T_714; // @[lib.scala 88:23] + wire _T_717 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_718 = _T_717 & _T_585; // @[lib.scala 88:41] + wire _T_721 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 88:78] + wire _T_722 = _T_718 | _T_721; // @[lib.scala 88:23] + wire _T_724 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_725 = _T_724 & _T_585; // @[lib.scala 88:41] + wire _T_728 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 88:78] + wire _T_729 = _T_725 | _T_728; // @[lib.scala 88:23] + wire _T_731 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_732 = _T_731 & _T_585; // @[lib.scala 88:41] + wire _T_735 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 88:78] + wire _T_736 = _T_732 | _T_735; // @[lib.scala 88:23] + wire _T_738 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_739 = _T_738 & _T_585; // @[lib.scala 88:41] + wire _T_742 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 88:78] + wire _T_743 = _T_739 | _T_742; // @[lib.scala 88:23] + wire _T_745 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_746 = _T_745 & _T_585; // @[lib.scala 88:41] + wire _T_749 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 88:78] + wire _T_750 = _T_746 | _T_749; // @[lib.scala 88:23] + wire _T_752 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_753 = _T_752 & _T_585; // @[lib.scala 88:41] + wire _T_756 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 88:78] + wire _T_757 = _T_753 | _T_756; // @[lib.scala 88:23] + wire _T_759 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_760 = _T_759 & _T_585; // @[lib.scala 88:41] + wire _T_763 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 88:78] + wire _T_764 = _T_760 | _T_763; // @[lib.scala 88:23] + wire _T_766 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_767 = _T_766 & _T_585; // @[lib.scala 88:41] + wire _T_770 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 88:78] + wire _T_771 = _T_767 | _T_770; // @[lib.scala 88:23] + wire _T_773 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_774 = _T_773 & _T_585; // @[lib.scala 88:41] + wire _T_777 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 88:78] + wire _T_778 = _T_774 | _T_777; // @[lib.scala 88:23] + wire _T_780 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_781 = _T_780 & _T_585; // @[lib.scala 88:41] + wire _T_784 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 88:78] + wire _T_785 = _T_781 | _T_784; // @[lib.scala 88:23] + wire _T_787 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_788 = _T_787 & _T_585; // @[lib.scala 88:41] + wire _T_791 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 88:78] + wire _T_792 = _T_788 | _T_791; // @[lib.scala 88:23] + wire _T_794 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_795 = _T_794 & _T_585; // @[lib.scala 88:41] + wire _T_798 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 88:78] + wire _T_799 = _T_795 | _T_798; // @[lib.scala 88:23] + wire _T_801 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_802 = _T_801 & _T_585; // @[lib.scala 88:41] + wire _T_805 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 88:78] + wire _T_806 = _T_802 | _T_805; // @[lib.scala 88:23] + wire [7:0] _T_813 = {_T_638,_T_631,_T_624,_T_617,_T_610,_T_603,_T_596,_T_589}; // @[lib.scala 89:14] + wire [15:0] _T_821 = {_T_694,_T_687,_T_680,_T_673,_T_666,_T_659,_T_652,_T_645,_T_813}; // @[lib.scala 89:14] + wire [7:0] _T_828 = {_T_750,_T_743,_T_736,_T_729,_T_722,_T_715,_T_708,_T_701}; // @[lib.scala 89:14] + wire [31:0] _T_837 = {_T_806,_T_799,_T_792,_T_785,_T_778,_T_771,_T_764,_T_757,_T_828,_T_821}; // @[lib.scala 89:14] + wire _T_838 = &_T_837; // @[lib.scala 89:25] + wire _T_839 = _T_580 & _T_838; // @[lsu_trigger.scala 19:92] + wire _T_842 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_843 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_845 = _T_843 & _T_33; // @[lsu_trigger.scala 19:58] + wire _T_846 = _T_842 | _T_845; // @[lsu_trigger.scala 18:152] + wire _T_847 = _T_40 & _T_846; // @[lsu_trigger.scala 18:94] + wire _T_850 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] + wire _T_851 = ~_T_850; // @[lib.scala 85:39] + wire _T_852 = io_trigger_pkt_any_3_match_pkt & _T_851; // @[lib.scala 85:37] + wire _T_855 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 86:52] + wire _T_856 = _T_852 | _T_855; // @[lib.scala 86:41] + wire _T_858 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] + wire _T_859 = _T_858 & _T_852; // @[lib.scala 88:41] + wire _T_862 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 88:78] + wire _T_863 = _T_859 | _T_862; // @[lib.scala 88:23] + wire _T_865 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_866 = _T_865 & _T_852; // @[lib.scala 88:41] + wire _T_869 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 88:78] + wire _T_870 = _T_866 | _T_869; // @[lib.scala 88:23] + wire _T_872 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_873 = _T_872 & _T_852; // @[lib.scala 88:41] + wire _T_876 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 88:78] + wire _T_877 = _T_873 | _T_876; // @[lib.scala 88:23] + wire _T_879 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_880 = _T_879 & _T_852; // @[lib.scala 88:41] + wire _T_883 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 88:78] + wire _T_884 = _T_880 | _T_883; // @[lib.scala 88:23] + wire _T_886 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_887 = _T_886 & _T_852; // @[lib.scala 88:41] + wire _T_890 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 88:78] + wire _T_891 = _T_887 | _T_890; // @[lib.scala 88:23] + wire _T_893 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_894 = _T_893 & _T_852; // @[lib.scala 88:41] + wire _T_897 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 88:78] + wire _T_898 = _T_894 | _T_897; // @[lib.scala 88:23] + wire _T_900 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_901 = _T_900 & _T_852; // @[lib.scala 88:41] + wire _T_904 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 88:78] + wire _T_905 = _T_901 | _T_904; // @[lib.scala 88:23] + wire _T_907 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_908 = _T_907 & _T_852; // @[lib.scala 88:41] + wire _T_911 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 88:78] + wire _T_912 = _T_908 | _T_911; // @[lib.scala 88:23] + wire _T_914 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_915 = _T_914 & _T_852; // @[lib.scala 88:41] + wire _T_918 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 88:78] + wire _T_919 = _T_915 | _T_918; // @[lib.scala 88:23] + wire _T_921 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_922 = _T_921 & _T_852; // @[lib.scala 88:41] + wire _T_925 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 88:78] + wire _T_926 = _T_922 | _T_925; // @[lib.scala 88:23] + wire _T_928 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_929 = _T_928 & _T_852; // @[lib.scala 88:41] + wire _T_932 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 88:78] + wire _T_933 = _T_929 | _T_932; // @[lib.scala 88:23] + wire _T_935 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_936 = _T_935 & _T_852; // @[lib.scala 88:41] + wire _T_939 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 88:78] + wire _T_940 = _T_936 | _T_939; // @[lib.scala 88:23] + wire _T_942 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_943 = _T_942 & _T_852; // @[lib.scala 88:41] + wire _T_946 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 88:78] + wire _T_947 = _T_943 | _T_946; // @[lib.scala 88:23] + wire _T_949 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_950 = _T_949 & _T_852; // @[lib.scala 88:41] + wire _T_953 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 88:78] + wire _T_954 = _T_950 | _T_953; // @[lib.scala 88:23] + wire _T_956 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_957 = _T_956 & _T_852; // @[lib.scala 88:41] + wire _T_960 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 88:78] + wire _T_961 = _T_957 | _T_960; // @[lib.scala 88:23] + wire _T_963 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_964 = _T_963 & _T_852; // @[lib.scala 88:41] + wire _T_967 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 88:78] + wire _T_968 = _T_964 | _T_967; // @[lib.scala 88:23] + wire _T_970 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_971 = _T_970 & _T_852; // @[lib.scala 88:41] + wire _T_974 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 88:78] + wire _T_975 = _T_971 | _T_974; // @[lib.scala 88:23] + wire _T_977 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_978 = _T_977 & _T_852; // @[lib.scala 88:41] + wire _T_981 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 88:78] + wire _T_982 = _T_978 | _T_981; // @[lib.scala 88:23] + wire _T_984 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_985 = _T_984 & _T_852; // @[lib.scala 88:41] + wire _T_988 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 88:78] + wire _T_989 = _T_985 | _T_988; // @[lib.scala 88:23] + wire _T_991 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_992 = _T_991 & _T_852; // @[lib.scala 88:41] + wire _T_995 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 88:78] + wire _T_996 = _T_992 | _T_995; // @[lib.scala 88:23] + wire _T_998 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_999 = _T_998 & _T_852; // @[lib.scala 88:41] + wire _T_1002 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 88:78] + wire _T_1003 = _T_999 | _T_1002; // @[lib.scala 88:23] + wire _T_1005 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_1006 = _T_1005 & _T_852; // @[lib.scala 88:41] + wire _T_1009 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 88:78] + wire _T_1010 = _T_1006 | _T_1009; // @[lib.scala 88:23] + wire _T_1012 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_1013 = _T_1012 & _T_852; // @[lib.scala 88:41] + wire _T_1016 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 88:78] + wire _T_1017 = _T_1013 | _T_1016; // @[lib.scala 88:23] + wire _T_1019 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_1020 = _T_1019 & _T_852; // @[lib.scala 88:41] + wire _T_1023 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 88:78] + wire _T_1024 = _T_1020 | _T_1023; // @[lib.scala 88:23] + wire _T_1026 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_1027 = _T_1026 & _T_852; // @[lib.scala 88:41] + wire _T_1030 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 88:78] + wire _T_1031 = _T_1027 | _T_1030; // @[lib.scala 88:23] + wire _T_1033 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_1034 = _T_1033 & _T_852; // @[lib.scala 88:41] + wire _T_1037 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 88:78] + wire _T_1038 = _T_1034 | _T_1037; // @[lib.scala 88:23] + wire _T_1040 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_1041 = _T_1040 & _T_852; // @[lib.scala 88:41] + wire _T_1044 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 88:78] + wire _T_1045 = _T_1041 | _T_1044; // @[lib.scala 88:23] + wire _T_1047 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_1048 = _T_1047 & _T_852; // @[lib.scala 88:41] + wire _T_1051 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 88:78] + wire _T_1052 = _T_1048 | _T_1051; // @[lib.scala 88:23] + wire _T_1054 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_1055 = _T_1054 & _T_852; // @[lib.scala 88:41] + wire _T_1058 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 88:78] + wire _T_1059 = _T_1055 | _T_1058; // @[lib.scala 88:23] + wire _T_1061 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_1062 = _T_1061 & _T_852; // @[lib.scala 88:41] + wire _T_1065 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 88:78] + wire _T_1066 = _T_1062 | _T_1065; // @[lib.scala 88:23] + wire _T_1068 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_1069 = _T_1068 & _T_852; // @[lib.scala 88:41] + wire _T_1072 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 88:78] + wire _T_1073 = _T_1069 | _T_1072; // @[lib.scala 88:23] + wire [7:0] _T_1080 = {_T_905,_T_898,_T_891,_T_884,_T_877,_T_870,_T_863,_T_856}; // @[lib.scala 89:14] + wire [15:0] _T_1088 = {_T_961,_T_954,_T_947,_T_940,_T_933,_T_926,_T_919,_T_912,_T_1080}; // @[lib.scala 89:14] + wire [7:0] _T_1095 = {_T_1017,_T_1010,_T_1003,_T_996,_T_989,_T_982,_T_975,_T_968}; // @[lib.scala 89:14] + wire [31:0] _T_1104 = {_T_1073,_T_1066,_T_1059,_T_1052,_T_1045,_T_1038,_T_1031,_T_1024,_T_1095,_T_1088}; // @[lib.scala 89:14] + wire _T_1105 = &_T_1104; // @[lib.scala 89:25] + wire _T_1106 = _T_847 & _T_1105; // @[lsu_trigger.scala 19:92] + wire [2:0] _T_1108 = {_T_1106,_T_839,_T_572}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = {_T_1108,_T_305}; // @[lsu_trigger.scala 18:26] endmodule module lsu_clkdomain( input clock, @@ -78412,7 +78412,7 @@ module dma_ctrl( input io_dbg_dma_dbg_ib_dbg_cmd_write, input [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, input [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - input [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + input [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, input io_dbg_dma_io_dbg_dma_bubble, output io_dbg_dma_io_dma_dbg_ready, output io_dec_dma_dctl_dma_dma_dccm_stall_any, @@ -78952,9 +78952,9 @@ module dma_ctrl( wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58] wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] - wire [3:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] + wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] reg [63:0] wrbuf_data; // @[lib.scala 358:16] - wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? {{60'd0}, _T_498} : wrbuf_data; // @[dma_ctrl.scala 224:347] + wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347] wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77] @@ -80288,7 +80288,7 @@ end // initial end else if (_T_87) begin fifo_data_0 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_0 <= {{60'd0}, _T_498}; + fifo_data_0 <= _T_498; end else begin fifo_data_0 <= wrbuf_data; end @@ -80303,7 +80303,7 @@ end // initial end else if (_T_105) begin fifo_data_1 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_1 <= {{60'd0}, _T_498}; + fifo_data_1 <= _T_498; end else begin fifo_data_1 <= wrbuf_data; end @@ -80318,7 +80318,7 @@ end // initial end else if (_T_123) begin fifo_data_2 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_2 <= {{60'd0}, _T_498}; + fifo_data_2 <= _T_498; end else begin fifo_data_2 <= wrbuf_data; end @@ -80333,7 +80333,7 @@ end // initial end else if (_T_141) begin fifo_data_3 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_3 <= {{60'd0}, _T_498}; + fifo_data_3 <= _T_498; end else begin fifo_data_3 <= wrbuf_data; end @@ -80496,14 +80496,14 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[lib.scala 327:22] wire rvclkhdr_9_io_en; // @[lib.scala 327:22] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 327:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 410:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:45] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 57:22 axi4_to_ahb.scala 404:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 63:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 201:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 378:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 379:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 178:27] - wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 179:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 195:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 372:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 373:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 172:27] + wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 173:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] @@ -80511,7 +80511,7 @@ module axi4_to_ahb( wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 196:32] + wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 190:32] wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] @@ -80520,9 +80520,9 @@ module axi4_to_ahb( wire _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 181:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 181:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 226:41] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 175:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 175:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 220:41] wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -80530,11 +80530,11 @@ module axi4_to_ahb( wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 227:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 240:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 240:26] - wire _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 298:51] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 221:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 234:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 234:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 234:26] + wire _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 292:51] wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] @@ -80542,13 +80542,13 @@ module axi4_to_ahb( wire _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 254:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 254:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 299:65] - wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 299:26] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 248:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 248:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 248:67] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 293:42] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 293:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 293:65] + wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 293:26] wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] @@ -80556,14 +80556,14 @@ module axi4_to_ahb( wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56] - wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 303:33] + wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 193:56] + wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 193:91] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 193:74] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 224:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 224:38] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 229:51] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 297:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 297:33] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] @@ -80584,23 +80584,23 @@ module axi4_to_ahb( wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 368:47] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 369:50] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 370:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 371:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 373:33] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 373:21] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 374:37] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 374:20] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 378:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 378:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 379:55] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 404:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 404:58] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 406:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 406:60] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 362:47] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 363:50] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 364:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 365:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 365:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 367:35] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 367:33] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 367:21] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 368:37] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 368:20] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 372:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 372:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 373:55] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 398:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 398:58] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 400:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 400:60] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -80661,8 +80661,8 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 373:18] - assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 374:17] + assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 367:18] + assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 368:17] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -80819,16 +80819,16 @@ module ahb_to_axi4( input io_axi_arready, input io_axi_rvalid, input [1:0] io_axi_rresp, - input [31:0] io_ahb_haddr, - input [2:0] io_ahb_hsize, - input [1:0] io_ahb_htrans, - input io_ahb_hwrite, input io_ahb_hsel, input io_ahb_hreadyin, output io_axi_awvalid, output io_axi_arvalid, - output io_ahb_hreadyout, - output io_ahb_hresp + output io_ahb_in_hready, + output io_ahb_in_hresp, + input [31:0] io_ahb_out_haddr, + input [2:0] io_ahb_out_hsize, + input [1:0] io_ahb_out_htrans, + input io_ahb_out_hwrite ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -80866,48 +80866,48 @@ module ahb_to_axi4( wire rvclkhdr_5_io_clk; // @[lib.scala 327:22] wire rvclkhdr_5_io_en; // @[lib.scala 327:22] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 327:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 86:33 ahb_to_axi4.scala 175:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 168:65] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 87:33 ahb_to_axi4.scala 176:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 169:65] wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 71:29] wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 71:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 85:33 ahb_to_axi4.scala 174:31] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 86:33 ahb_to_axi4.scala 175:31] reg [1:0] buf_state; // @[Reg.scala 27:20] wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 146:51] - wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 118:34] - wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 118:53] + wire ahb_hready = io_ahb_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 147:51] + wire _T_9 = ahb_hready & io_ahb_out_htrans[1]; // @[ahb_to_axi4.scala 119:34] + wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 119:57] wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 121:64] - wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 121:41] - wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 121:78] - wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 121:76] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 99:33 ahb_to_axi4.scala 224:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 181:61] - wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 179:66] - wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 179:102] - wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 179:84] - wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 179:48] - wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 179:46] - wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 122:24] - wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 122:37] - wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 123:77] - wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 123:95] - wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 123:53] - wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 123:38] - wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 123:36] + wire _T_13 = io_ahb_out_htrans == 2'h0; // @[ahb_to_axi4.scala 122:71] + wire _T_14 = io_ahb_in_hresp | _T_13; // @[ahb_to_axi4.scala 122:44] + wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 122:85] + wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 122:83] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 100:33 ahb_to_axi4.scala 225:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 182:61] + wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 180:66] + wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 180:102] + wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 180:84] + wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 180:48] + wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 180:46] + wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 123:24] + wire _T_21 = _T_20 | io_ahb_in_hresp; // @[ahb_to_axi4.scala 123:37] + wire _T_24 = io_ahb_out_htrans == 2'h1; // @[ahb_to_axi4.scala 124:84] + wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 124:102] + wire _T_26 = io_ahb_in_hresp | _T_25; // @[ahb_to_axi4.scala 124:56] + wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 124:38] + wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 124:36] wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 128:23] - wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 128:37] + wire _T_33 = ~io_ahb_in_hresp; // @[ahb_to_axi4.scala 129:23] + wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 129:40] wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30] reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 132:39] - wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 132:37] - wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 134:62] + wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 133:39] + wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 133:37] + wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 135:62] wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67] wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67] wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 134:41] + wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 135:41] wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67] wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67] @@ -80916,56 +80916,56 @@ module ahb_to_axi4( wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 166:65] - wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 140:30] - wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 141:30] - wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 142:30] - reg ahb_hready_q; // @[ahb_to_axi4.scala 164:60] - wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 145:66] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 163:60] - wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 145:64] - wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 145:110] - wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 145:97] - wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 145:135] - wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 145:154] - wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 145:142] - wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 145:123] - wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 145:121] - reg buf_read_error; // @[ahb_to_axi4.scala 160:60] - wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 145:167] - wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 145:165] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 167:65] + wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 141:30] + wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 142:30] + wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 143:30] + reg ahb_hready_q; // @[ahb_to_axi4.scala 165:60] + wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 146:72] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 164:60] + wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 146:70] + wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 146:116] + wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 146:103] + wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 146:141] + wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 146:160] + wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 146:148] + wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 146:129] + wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 146:127] + reg buf_read_error; // @[ahb_to_axi4.scala 161:60] + wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 146:173] + wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 146:171] wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 165:60] - wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 149:54] - wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 149:76] - wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 149:63] - wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 150:26] - wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 150:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 167:65] - wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 151:46] - wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 151:26] - wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 151:86] - wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 151:115] - wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 151:95] - wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 151:66] - wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 151:64] - wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 150:47] - wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 152:35] - wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 151:126] - wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 153:56] - wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 153:35] - wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 152:55] - wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 154:56] - wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 154:35] - wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 153:61] - wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 149:87] - wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 154:63] - wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 178:109] - wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 178:107] - wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 178:140] - wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 178:124] - wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 181:66] - wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 181:110] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 166:60] + wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 150:57] + wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 150:79] + wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 150:66] + wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 151:26] + wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 151:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 168:65] + wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 152:46] + wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 152:26] + wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 152:86] + wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 152:115] + wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 152:95] + wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 152:66] + wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 152:64] + wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 151:47] + wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 153:35] + wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 152:126] + wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 154:56] + wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 154:35] + wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 153:55] + wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 155:56] + wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 155:35] + wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 154:61] + wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 150:90] + wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 155:63] + wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 179:109] + wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 179:107] + wire _T_148 = io_ahb_in_hresp & _T_37; // @[ahb_to_axi4.scala 179:143] + wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 179:124] + wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 182:66] + wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 182:110] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -81002,10 +81002,10 @@ module ahb_to_axi4( .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 198:27] - assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 213:27] - assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 145:31] - assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 149:31] + assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 199:27] + assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 214:27] + assign io_ahb_in_hready = io_ahb_in_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 146:34] + assign io_ahb_in_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 150:34] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -81120,7 +81120,7 @@ end // initial if (reset) begin ahb_haddr_q <= 32'h0; end else begin - ahb_haddr_q <= io_ahb_haddr; + ahb_haddr_q <= io_ahb_out_haddr; end end always @(posedge ahb_clk or posedge reset) begin @@ -81128,7 +81128,7 @@ end // initial buf_state <= 2'h0; end else if (buf_state_en) begin if (_T_6) begin - if (io_ahb_hwrite) begin + if (io_ahb_out_hwrite) begin buf_state <= 2'h1; end else begin buf_state <= 2'h2; @@ -81136,13 +81136,13 @@ end // initial end else if (_T_11) begin if (_T_16) begin buf_state <= 2'h0; - end else if (io_ahb_hwrite) begin + end else if (io_ahb_out_hwrite) begin buf_state <= 2'h1; end else begin buf_state <= 2'h2; end end else if (_T_29) begin - if (io_ahb_hresp) begin + if (io_ahb_in_hresp) begin buf_state <= 2'h0; end else begin buf_state <= 2'h3; @@ -81170,21 +81170,21 @@ end // initial if (reset) begin ahb_hsize_q <= 3'h0; end else begin - ahb_hsize_q <= io_ahb_hsize; + ahb_hsize_q <= io_ahb_out_hsize; end end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_hready_q <= 1'h0; end else begin - ahb_hready_q <= io_ahb_hreadyout & io_ahb_hreadyin; + ahb_hready_q <= io_ahb_in_hready & io_ahb_hreadyin; end end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_hresp_q <= 1'h0; end else begin - ahb_hresp_q <= io_ahb_hresp; + ahb_hresp_q <= io_ahb_in_hresp; end end always @(posedge ahb_clk or posedge reset) begin @@ -81204,14 +81204,14 @@ end // initial if (reset) begin ahb_htrans_q <= 2'h0; end else begin - ahb_htrans_q <= _T_88 & io_ahb_htrans; + ahb_htrans_q <= _T_88 & io_ahb_out_htrans; end end always @(posedge ahb_addr_clk or posedge reset) begin if (reset) begin ahb_hwrite_q <= 1'h0; end else begin - ahb_hwrite_q <= io_ahb_hwrite; + ahb_hwrite_q <= io_ahb_out_hwrite; end end endmodule @@ -81302,6 +81302,10 @@ module quasar( output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, + input [31:0] io_dma_ahb_out_haddr, + input [2:0] io_dma_ahb_out_hsize, + input [1:0] io_dma_ahb_out_htrans, + input io_dma_ahb_out_hwrite, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -81374,10 +81378,6 @@ module quasar( input [63:0] io_iccm_rd_data, input [77:0] io_iccm_rd_data_ecc, input io_dma_hsel, - input [31:0] io_dma_haddr, - input [2:0] io_dma_hsize, - input [1:0] io_dma_htrans, - input io_dma_hwrite, input io_dma_hreadyin, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, @@ -81392,793 +81392,793 @@ module quasar( input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[quasar.scala 116:19] - wire ifu_reset; // @[quasar.scala 116:19] - wire ifu_io_exu_flush_final; // @[quasar.scala 116:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 116:19] - wire ifu_io_free_clk; // @[quasar.scala 116:19] - wire ifu_io_active_clk; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 116:19] - wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 116:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 116:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 116:19] - wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 116:19] - wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 116:19] - wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 116:19] - wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 116:19] - wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 116:19] - wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 116:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 116:19] - wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 116:19] - wire ifu_io_iccm_correction_state; // @[quasar.scala 116:19] - wire ifu_io_iccm_wren; // @[quasar.scala 116:19] - wire ifu_io_iccm_rden; // @[quasar.scala 116:19] - wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 116:19] - wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 116:19] - wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 116:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 116:19] - wire ifu_io_ic_rd_en; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 116:19] - wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 116:19] - wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 116:19] - wire ifu_io_ic_tag_perr; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_rd_en; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_wr_en; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_tag_array; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 116:19] - wire ifu_io_ic_sel_premux_data; // @[quasar.scala 116:19] - wire ifu_io_ifu_ar_ready; // @[quasar.scala 116:19] - wire ifu_io_ifu_ar_valid; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 116:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 116:19] - wire ifu_io_ifu_r_valid; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 116:19] - wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 116:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 116:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 116:19] - wire ifu_io_iccm_ready; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 116:19] - wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 116:19] - wire ifu_io_scan_mode; // @[quasar.scala 116:19] - wire dec_clock; // @[quasar.scala 117:19] - wire dec_reset; // @[quasar.scala 117:19] - wire dec_io_free_clk; // @[quasar.scala 117:19] - wire dec_io_active_clk; // @[quasar.scala 117:19] - wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_pause_state_cg; // @[quasar.scala 117:19] - wire [30:0] dec_io_rst_vec; // @[quasar.scala 117:19] - wire dec_io_nmi_int; // @[quasar.scala 117:19] - wire [30:0] dec_io_nmi_vec; // @[quasar.scala 117:19] - wire dec_io_i_cpu_halt_req; // @[quasar.scala 117:19] - wire dec_io_i_cpu_run_req; // @[quasar.scala 117:19] - wire dec_io_o_cpu_halt_status; // @[quasar.scala 117:19] - wire dec_io_o_cpu_halt_ack; // @[quasar.scala 117:19] - wire dec_io_o_cpu_run_ack; // @[quasar.scala 117:19] - wire dec_io_o_debug_mode_status; // @[quasar.scala 117:19] - wire [27:0] dec_io_core_id; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_halt_req; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_run_req; // @[quasar.scala 117:19] - wire dec_io_mpc_reset_run_req; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_run_ack; // @[quasar.scala 117:19] - wire dec_io_debug_brkpt_status; // @[quasar.scala 117:19] - wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 117:19] - wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 117:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 117:19] - wire dec_io_lsu_idle_any; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 117:19] - wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 117:19] - wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 117:19] - wire [31:0] dec_io_exu_div_result; // @[quasar.scala 117:19] - wire dec_io_exu_div_wren; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 117:19] - wire dec_io_lsu_load_stall_any; // @[quasar.scala 117:19] - wire dec_io_lsu_store_stall_any; // @[quasar.scala 117:19] - wire dec_io_iccm_dma_sb_error; // @[quasar.scala 117:19] - wire dec_io_exu_flush_final; // @[quasar.scala 117:19] - wire dec_io_timer_int; // @[quasar.scala 117:19] - wire dec_io_soft_int; // @[quasar.scala 117:19] - wire dec_io_dbg_halt_req; // @[quasar.scala 117:19] - wire dec_io_dbg_resume_req; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 117:19] - wire dec_io_exu_i0_br_way_r; // @[quasar.scala 117:19] - wire dec_io_lsu_p_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_by; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_half; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_word; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_load; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_store; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 117:19] - wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 117:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 117:19] - wire dec_io_scan_mode; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 117:19] - wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 117:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 117:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 117:19] - wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 117:19] - wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 117:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 117:19] - wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 117:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 117:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 117:19] - wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 117:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 117:19] - wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 117:19] - wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 117:19] - wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 117:19] - wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 117:19] - wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 117:19] - wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 117:19] - wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 117:19] - wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 117:19] - wire dec_io_dec_pic_mexintpend; // @[quasar.scala 117:19] - wire dbg_clock; // @[quasar.scala 118:19] - wire dbg_reset; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 118:19] - wire dbg_io_dbg_core_rst_l; // @[quasar.scala 118:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 118:19] - wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 118:19] - wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 118:19] - wire dbg_io_dbg_halt_req; // @[quasar.scala 118:19] - wire dbg_io_dbg_resume_req; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 118:19] - wire dbg_io_dmi_reg_en; // @[quasar.scala 118:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 118:19] - wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 118:19] - wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 118:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 118:19] - wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_w_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_w_valid; // @[quasar.scala 118:19] - wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 118:19] - wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_b_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_b_valid; // @[quasar.scala 118:19] - wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 118:19] - wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 118:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 118:19] - wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_r_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_r_valid; // @[quasar.scala 118:19] - wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 118:19] - wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 118:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 118:19] - wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 118:19] - wire dbg_io_dbg_rst_l; // @[quasar.scala 118:19] - wire dbg_io_clk_override; // @[quasar.scala 118:19] - wire dbg_io_scan_mode; // @[quasar.scala 118:19] - wire exu_clock; // @[quasar.scala 119:19] - wire exu_reset; // @[quasar.scala 119:19] - wire exu_io_scan_mode; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 119:19] - wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 119:19] - wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 119:19] - wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 119:19] - wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 119:19] - wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 119:19] - wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 119:19] - wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 119:19] - wire exu_io_exu_flush_final; // @[quasar.scala 119:19] - wire [31:0] exu_io_exu_div_result; // @[quasar.scala 119:19] - wire exu_io_exu_div_wren; // @[quasar.scala 119:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 119:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 119:19] - wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 119:19] - wire lsu_clock; // @[quasar.scala 120:19] - wire lsu_reset; // @[quasar.scala 120:19] - wire lsu_io_clk_override; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 120:19] - wire lsu_io_dccm_wren; // @[quasar.scala 120:19] - wire lsu_io_dccm_rden; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 120:19] - wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 120:19] - wire lsu_io_axi_aw_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_aw_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 120:19] - wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 120:19] - wire lsu_io_axi_w_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_w_valid; // @[quasar.scala 120:19] - wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 120:19] - wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 120:19] - wire lsu_io_axi_b_valid; // @[quasar.scala 120:19] - wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 120:19] - wire lsu_io_axi_ar_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_ar_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 120:19] - wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 120:19] - wire lsu_io_axi_r_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 120:19] - wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 120:19] - wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 120:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_by; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_half; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_word; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_load; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_store; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 120:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 120:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 120:19] - wire lsu_io_lsu_load_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_store_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_idle_any; // @[quasar.scala 120:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 120:19] - wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 120:19] - wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 120:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 120:19] - wire lsu_io_scan_mode; // @[quasar.scala 120:19] - wire lsu_io_free_clk; // @[quasar.scala 120:19] - wire pic_ctrl_inst_clock; // @[quasar.scala 121:29] - wire pic_ctrl_inst_reset; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 121:29] - wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 121:29] - wire dma_ctrl_clock; // @[quasar.scala 122:24] - wire dma_ctrl_reset; // @[quasar.scala 122:24] - wire dma_ctrl_io_free_clk; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 122:24] - wire dma_ctrl_io_clk_override; // @[quasar.scala 122:24] - wire dma_ctrl_io_scan_mode; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 122:24] - wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:24] + wire ifu_clock; // @[quasar.scala 122:19] + wire ifu_reset; // @[quasar.scala 122:19] + wire ifu_io_exu_flush_final; // @[quasar.scala 122:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 122:19] + wire ifu_io_free_clk; // @[quasar.scala 122:19] + wire ifu_io_active_clk; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 122:19] + wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 122:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 122:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 122:19] + wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 122:19] + wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 122:19] + wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 122:19] + wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 122:19] + wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 122:19] + wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 122:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 122:19] + wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 122:19] + wire ifu_io_iccm_correction_state; // @[quasar.scala 122:19] + wire ifu_io_iccm_wren; // @[quasar.scala 122:19] + wire ifu_io_iccm_rden; // @[quasar.scala 122:19] + wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 122:19] + wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 122:19] + wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 122:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 122:19] + wire ifu_io_ic_rd_en; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 122:19] + wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 122:19] + wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 122:19] + wire ifu_io_ic_tag_perr; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_rd_en; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_wr_en; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_tag_array; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 122:19] + wire ifu_io_ic_sel_premux_data; // @[quasar.scala 122:19] + wire ifu_io_ifu_ar_ready; // @[quasar.scala 122:19] + wire ifu_io_ifu_ar_valid; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 122:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 122:19] + wire ifu_io_ifu_r_valid; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 122:19] + wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 122:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 122:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 122:19] + wire ifu_io_iccm_ready; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 122:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 122:19] + wire ifu_io_scan_mode; // @[quasar.scala 122:19] + wire dec_clock; // @[quasar.scala 123:19] + wire dec_reset; // @[quasar.scala 123:19] + wire dec_io_free_clk; // @[quasar.scala 123:19] + wire dec_io_active_clk; // @[quasar.scala 123:19] + wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_pause_state_cg; // @[quasar.scala 123:19] + wire [30:0] dec_io_rst_vec; // @[quasar.scala 123:19] + wire dec_io_nmi_int; // @[quasar.scala 123:19] + wire [30:0] dec_io_nmi_vec; // @[quasar.scala 123:19] + wire dec_io_i_cpu_halt_req; // @[quasar.scala 123:19] + wire dec_io_i_cpu_run_req; // @[quasar.scala 123:19] + wire dec_io_o_cpu_halt_status; // @[quasar.scala 123:19] + wire dec_io_o_cpu_halt_ack; // @[quasar.scala 123:19] + wire dec_io_o_cpu_run_ack; // @[quasar.scala 123:19] + wire dec_io_o_debug_mode_status; // @[quasar.scala 123:19] + wire [27:0] dec_io_core_id; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_halt_req; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_run_req; // @[quasar.scala 123:19] + wire dec_io_mpc_reset_run_req; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_run_ack; // @[quasar.scala 123:19] + wire dec_io_debug_brkpt_status; // @[quasar.scala 123:19] + wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 123:19] + wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 123:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 123:19] + wire dec_io_lsu_idle_any; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 123:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 123:19] + wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 123:19] + wire [31:0] dec_io_exu_div_result; // @[quasar.scala 123:19] + wire dec_io_exu_div_wren; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 123:19] + wire dec_io_lsu_load_stall_any; // @[quasar.scala 123:19] + wire dec_io_lsu_store_stall_any; // @[quasar.scala 123:19] + wire dec_io_iccm_dma_sb_error; // @[quasar.scala 123:19] + wire dec_io_exu_flush_final; // @[quasar.scala 123:19] + wire dec_io_timer_int; // @[quasar.scala 123:19] + wire dec_io_soft_int; // @[quasar.scala 123:19] + wire dec_io_dbg_halt_req; // @[quasar.scala 123:19] + wire dec_io_dbg_resume_req; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 123:19] + wire dec_io_exu_i0_br_way_r; // @[quasar.scala 123:19] + wire dec_io_lsu_p_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_by; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_half; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_word; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_load; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_store; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 123:19] + wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 123:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 123:19] + wire dec_io_scan_mode; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 123:19] + wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 123:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 123:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 123:19] + wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 123:19] + wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 123:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 123:19] + wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 123:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 123:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 123:19] + wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 123:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 123:19] + wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 123:19] + wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 123:19] + wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:19] + wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 123:19] + wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 123:19] + wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 123:19] + wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 123:19] + wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 123:19] + wire dec_io_dec_pic_mexintpend; // @[quasar.scala 123:19] + wire dbg_clock; // @[quasar.scala 124:19] + wire dbg_reset; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 124:19] + wire dbg_io_dbg_core_rst_l; // @[quasar.scala 124:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 124:19] + wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 124:19] + wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 124:19] + wire dbg_io_dbg_halt_req; // @[quasar.scala 124:19] + wire dbg_io_dbg_resume_req; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 124:19] + wire dbg_io_dmi_reg_en; // @[quasar.scala 124:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 124:19] + wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 124:19] + wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 124:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 124:19] + wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_w_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_w_valid; // @[quasar.scala 124:19] + wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 124:19] + wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_b_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_b_valid; // @[quasar.scala 124:19] + wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 124:19] + wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 124:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 124:19] + wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_r_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_r_valid; // @[quasar.scala 124:19] + wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 124:19] + wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 124:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 124:19] + wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 124:19] + wire dbg_io_dbg_rst_l; // @[quasar.scala 124:19] + wire dbg_io_clk_override; // @[quasar.scala 124:19] + wire dbg_io_scan_mode; // @[quasar.scala 124:19] + wire exu_clock; // @[quasar.scala 125:19] + wire exu_reset; // @[quasar.scala 125:19] + wire exu_io_scan_mode; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 125:19] + wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 125:19] + wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 125:19] + wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 125:19] + wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19] + wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19] + wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 125:19] + wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 125:19] + wire exu_io_exu_flush_final; // @[quasar.scala 125:19] + wire [31:0] exu_io_exu_div_result; // @[quasar.scala 125:19] + wire exu_io_exu_div_wren; // @[quasar.scala 125:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 125:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 125:19] + wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 125:19] + wire lsu_clock; // @[quasar.scala 126:19] + wire lsu_reset; // @[quasar.scala 126:19] + wire lsu_io_clk_override; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19] + wire lsu_io_dccm_wren; // @[quasar.scala 126:19] + wire lsu_io_dccm_rden; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 126:19] + wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19] + wire lsu_io_axi_aw_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_aw_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 126:19] + wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 126:19] + wire lsu_io_axi_w_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_w_valid; // @[quasar.scala 126:19] + wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 126:19] + wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 126:19] + wire lsu_io_axi_b_valid; // @[quasar.scala 126:19] + wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 126:19] + wire lsu_io_axi_ar_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_ar_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 126:19] + wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 126:19] + wire lsu_io_axi_r_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 126:19] + wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 126:19] + wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_by; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_half; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_word; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_load; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_store; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 126:19] + wire lsu_io_lsu_load_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_store_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_idle_any; // @[quasar.scala 126:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19] + wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 126:19] + wire lsu_io_scan_mode; // @[quasar.scala 126:19] + wire lsu_io_free_clk; // @[quasar.scala 126:19] + wire pic_ctrl_inst_clock; // @[quasar.scala 127:29] + wire pic_ctrl_inst_reset; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 127:29] + wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 127:29] + wire dma_ctrl_clock; // @[quasar.scala 128:24] + wire dma_ctrl_reset; // @[quasar.scala 128:24] + wire dma_ctrl_io_free_clk; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 128:24] + wire dma_ctrl_io_clk_override; // @[quasar.scala 128:24] + wire dma_ctrl_io_scan_mode; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 128:24] + wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 128:24] wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] wire rvclkhdr_io_en; // @[lib.scala 327:22] @@ -82187,65 +82187,65 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 327:22] wire rvclkhdr_1_io_en; // @[lib.scala 327:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 327:22] - wire axi4_to_ahb_clock; // @[quasar.scala 297:33] - wire axi4_to_ahb_reset; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 297:33] - wire axi4_to_ahb_1_clock; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 324:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_reset; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 352:32] - wire ahb_to_axi4_clock; // @[quasar.scala 379:33] - wire ahb_to_axi4_reset; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 379:33] - wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 379:33] - wire [31:0] ahb_to_axi4_io_ahb_haddr; // @[quasar.scala 379:33] - wire [2:0] ahb_to_axi4_io_ahb_hsize; // @[quasar.scala 379:33] - wire [1:0] ahb_to_axi4_io_ahb_htrans; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hwrite; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 379:33] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 124:67] - wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 124:70] - wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 125:23] - wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:50] - ifu ifu ( // @[quasar.scala 116:19] + wire axi4_to_ahb_clock; // @[quasar.scala 303:33] + wire axi4_to_ahb_reset; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 303:33] + wire axi4_to_ahb_1_clock; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 330:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_reset; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 358:32] + wire ahb_to_axi4_clock; // @[quasar.scala 385:33] + wire ahb_to_axi4_reset; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 385:33] + wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_in_hready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_in_hresp; // @[quasar.scala 385:33] + wire [31:0] ahb_to_axi4_io_ahb_out_haddr; // @[quasar.scala 385:33] + wire [2:0] ahb_to_axi4_io_ahb_out_hsize; // @[quasar.scala 385:33] + wire [1:0] ahb_to_axi4_io_ahb_out_htrans; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_out_hwrite; // @[quasar.scala 385:33] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 130:67] + wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 130:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 131:23] + wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 131:50] + ifu ifu ( // @[quasar.scala 122:19] .clock(ifu_clock), .reset(ifu_reset), .io_exu_flush_final(ifu_io_exu_flush_final), @@ -82375,7 +82375,7 @@ module quasar( .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), .io_scan_mode(ifu_io_scan_mode) ); - dec dec ( // @[quasar.scala 117:19] + dec dec ( // @[quasar.scala 123:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -82649,7 +82649,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend) ); - dbg dbg ( // @[quasar.scala 118:19] + dbg dbg ( // @[quasar.scala 124:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_size(dbg_io_dbg_cmd_size), @@ -82705,7 +82705,7 @@ module quasar( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - exu exu ( // @[quasar.scala 119:19] + exu exu ( // @[quasar.scala 125:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -82810,7 +82810,7 @@ module quasar( .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d), .io_exu_flush_path_final(exu_io_exu_flush_path_final) ); - lsu lsu ( // @[quasar.scala 120:19] + lsu lsu ( // @[quasar.scala 126:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -82949,7 +82949,7 @@ module quasar( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - pic_ctrl pic_ctrl_inst ( // @[quasar.scala 121:29] + pic_ctrl pic_ctrl_inst ( // @[quasar.scala 127:29] .clock(pic_ctrl_inst_clock), .reset(pic_ctrl_inst_reset), .io_scan_mode(pic_ctrl_inst_io_scan_mode), @@ -82971,7 +82971,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend) ); - dma_ctrl dma_ctrl ( // @[quasar.scala 122:24] + dma_ctrl dma_ctrl ( // @[quasar.scala 128:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -83058,7 +83058,7 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 297:33] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 303:33] .clock(axi4_to_ahb_clock), .reset(axi4_to_ahb_reset), .io_scan_mode(axi4_to_ahb_io_scan_mode), @@ -83072,7 +83072,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_io_axi_awready), .io_axi_wready(axi4_to_ahb_io_axi_wready) ); - axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 324:33] + axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 330:33] .clock(axi4_to_ahb_1_clock), .reset(axi4_to_ahb_1_reset), .io_scan_mode(axi4_to_ahb_1_io_scan_mode), @@ -83086,7 +83086,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_1_io_axi_awready), .io_axi_wready(axi4_to_ahb_1_io_axi_wready) ); - axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 352:32] + axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 358:32] .clock(axi4_to_ahb_2_clock), .reset(axi4_to_ahb_2_reset), .io_scan_mode(axi4_to_ahb_2_io_scan_mode), @@ -83100,7 +83100,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_2_io_axi_awready), .io_axi_wready(axi4_to_ahb_2_io_axi_wready) ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 379:33] + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 385:33] .clock(ahb_to_axi4_clock), .reset(ahb_to_axi4_reset), .io_scan_mode(ahb_to_axi4_io_scan_mode), @@ -83109,513 +83109,513 @@ module quasar( .io_axi_arready(ahb_to_axi4_io_axi_arready), .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid), .io_axi_rresp(ahb_to_axi4_io_axi_rresp), - .io_ahb_haddr(ahb_to_axi4_io_ahb_haddr), - .io_ahb_hsize(ahb_to_axi4_io_ahb_hsize), - .io_ahb_htrans(ahb_to_axi4_io_ahb_htrans), - .io_ahb_hwrite(ahb_to_axi4_io_ahb_hwrite), .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin), .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid), .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid), - .io_ahb_hreadyout(ahb_to_axi4_io_ahb_hreadyout), - .io_ahb_hresp(ahb_to_axi4_io_ahb_hresp) + .io_ahb_in_hready(ahb_to_axi4_io_ahb_in_hready), + .io_ahb_in_hresp(ahb_to_axi4_io_ahb_in_hresp), + .io_ahb_out_haddr(ahb_to_axi4_io_ahb_out_haddr), + .io_ahb_out_hsize(ahb_to_axi4_io_ahb_out_hsize), + .io_ahb_out_htrans(ahb_to_axi4_io_ahb_out_htrans), + .io_ahb_out_hwrite(ahb_to_axi4_io_ahb_out_hwrite) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 286:14] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 286:14] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 286:14] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 286:14] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 286:14] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 289:14] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 289:14] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 233:17] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 233:17] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 233:17] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 233:17] - assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 233:17] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 233:17] - assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 233:17] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 290:14] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 290:14] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 290:14] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 290:14] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 290:14] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 290:14] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 290:14] - assign io_core_rst_l = reset & _T_2; // @[quasar.scala 124:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 265:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 268:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 269:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 270:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 271:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 272:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 273:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 274:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 275:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 276:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 277:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 278:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 279:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 280:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 281:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 283:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 283:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 283:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 283:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 283:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 283:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 283:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 283:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 145:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 145:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 145:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 145:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 145:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 145:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 145:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 145:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 145:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 145:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 145:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 145:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 145:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 145:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 146:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 146:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 146:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 146:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 146:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 146:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 146:15] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 292:14] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 292:14] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 292:14] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 292:14] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 292:14] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 295:14] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 295:14] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 239:17] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 239:17] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 239:17] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 239:17] + assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 239:17] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 239:17] + assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 239:17] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 296:14] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 296:14] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 296:14] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 296:14] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 296:14] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 296:14] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 296:14] + assign io_core_rst_l = reset & _T_2; // @[quasar.scala 130:17] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 271:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 274:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 275:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 276:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 277:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 278:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 279:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 280:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 281:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 282:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 283:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 284:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 285:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 286:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 287:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 289:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 289:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 289:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 289:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 289:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 289:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 289:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 289:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 151:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 151:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 151:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 151:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 151:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 151:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 151:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 151:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 151:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 151:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 151:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 151:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 151:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 151:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 152:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 152:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 152:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 152:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 152:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 152:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 152:15] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 135:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 140:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 141:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 137:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 138:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 133:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 147:25 quasar.scala 149:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 147:25 quasar.scala 148:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 147:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 146:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 146:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 145:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 145:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 145:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 289:14 quasar.scala 423:25] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 289:14 quasar.scala 424:24] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 289:14 quasar.scala 425:26] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 289:14 quasar.scala 426:28] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 289:14 quasar.scala 427:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 143:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 144:18] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 150:33] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 136:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 141:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 146:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 147:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 143:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 144:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 139:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 153:25 quasar.scala 155:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 153:25 quasar.scala 154:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 153:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 152:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 152:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 151:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 151:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 151:13] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 427:25] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 428:24] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 429:26] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 430:28] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 431:28] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 149:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 150:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 156:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 142:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 154:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 155:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 156:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 157:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 158:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 159:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 160:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 161:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 162:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 163:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 164:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 165:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 166:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 169:31] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 172:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 173:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 174:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 176:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 177:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 178:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 179:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 180:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 181:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 182:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 183:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 184:30] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 185:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 186:26] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 192:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 188:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 189:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 190:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 191:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 193:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 133:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 196:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 167:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 168:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 168:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 175:18] - assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 263:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 263:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 263:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 263:28] + assign dec_reset = io_core_rst_l; // @[quasar.scala 160:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 161:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 162:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 163:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 164:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 165:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 166:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 167:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 168:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 169:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 170:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 171:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 172:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 175:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 178:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 179:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 180:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 182:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 183:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 184:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 185:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 186:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 187:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 188:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 189:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 190:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 191:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 192:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 198:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 194:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 195:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 196:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 197:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 199:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 139:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 202:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 173:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 174:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 174:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 181:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 269:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 269:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 269:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 269:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 221:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 222:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 223:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 224:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 225:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 226:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 227:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 228:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 229:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 230:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 231:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 232:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 233:17 quasar.scala 430:28] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 233:17 quasar.scala 431:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 233:17 quasar.scala 432:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 233:17 quasar.scala 433:31] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 233:17 quasar.scala 434:28] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 233:17 quasar.scala 435:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 233:17 quasar.scala 437:31] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 233:17 quasar.scala 438:31] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 247:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 234:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 235:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 236:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 237:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 227:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 228:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 229:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 230:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 231:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 232:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 233:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 234:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 235:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 236:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 237:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 238:24] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 239:17 quasar.scala 434:28] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 239:17 quasar.scala 435:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 239:17 quasar.scala 436:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 239:17 quasar.scala 437:31] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 239:17 quasar.scala 438:28] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 239:17 quasar.scala 439:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 239:17 quasar.scala 441:31] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 239:17 quasar.scala 442:31] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 253:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 240:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 241:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 242:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 243:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 197:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 198:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 196:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 196:18] - assign exu_io_dbg_cmd_wrdata = {{30'd0}, dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata}; // @[quasar.scala 199:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 203:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 204:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 202:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 202:18] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 205:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 202:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 203:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 216:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 262:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 208:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 208:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 167:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 167:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 167:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 283:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 283:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 286:14 quasar.scala 409:25] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 286:14 quasar.scala 410:24] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 286:14 quasar.scala 411:24] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 286:14 quasar.scala 412:28] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 286:14 quasar.scala 413:26] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 286:14 quasar.scala 414:25] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 286:14 quasar.scala 415:24] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 286:14 quasar.scala 416:26] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 286:14 quasar.scala 417:28] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 286:14 quasar.scala 418:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 204:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 205:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 206:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 207:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 209:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 210:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 213:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 211:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 212:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 215:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 217:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 218:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 208:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 209:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 222:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 268:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 214:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 214:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 173:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 173:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 173:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 289:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 289:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 292:14 quasar.scala 413:25] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 292:14 quasar.scala 414:24] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 292:14 quasar.scala 415:24] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 292:14 quasar.scala 416:28] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 292:14 quasar.scala 417:26] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 292:14 quasar.scala 418:25] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 292:14 quasar.scala 419:24] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 292:14 quasar.scala 420:26] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 292:14 quasar.scala 421:28] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 292:14 quasar.scala 422:28] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 210:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 211:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 212:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 213:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 215:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 216:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 219:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 217:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 218:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 221:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 223:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 224:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 257:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 256:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 258:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 259:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 260:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 261:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 263:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 263:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 263:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 262:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 264:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 265:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 266:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 267:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 269:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 269:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 241:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 242:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 243:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 244:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 245:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 248:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 247:26] - assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 170:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 249:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 253:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 250:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 251:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 252:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 290:14 quasar.scala 440:34] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 290:14 quasar.scala 441:36] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 290:14 quasar.scala 442:38] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 290:14 quasar.scala 443:38] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 290:14 quasar.scala 444:33] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 290:14 quasar.scala 445:37] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 290:14 quasar.scala 446:37] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 290:14 quasar.scala 447:33] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 290:14 quasar.scala 448:34] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 290:14 quasar.scala 449:36] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 290:14 quasar.scala 450:38] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 290:14 quasar.scala 451:38] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 290:14 quasar.scala 452:33] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 216:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 247:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 248:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 249:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 250:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 251:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 254:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 253:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 176:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 255:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 259:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 256:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 257:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 258:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 296:14 quasar.scala 444:34] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 296:14 quasar.scala 445:36] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 296:14 quasar.scala 446:38] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 296:14 quasar.scala 447:38] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 296:14 quasar.scala 448:33] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 296:14 quasar.scala 449:37] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 296:14 quasar.scala 450:37] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 296:14 quasar.scala 451:33] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 296:14 quasar.scala 452:34] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 296:14 quasar.scala 453:36] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 296:14 quasar.scala 454:38] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 296:14 quasar.scala 455:38] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 296:14 quasar.scala 456:33] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 222:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -83624,48 +83624,48 @@ module quasar( assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] assign axi4_to_ahb_clock = clock; assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 299:34] - assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 300:35] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 301:37] - assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 298:36] - assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 307:35] - assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 311:35] - assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 313:36] - assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 319:35] + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 305:34] + assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 306:35] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 307:37] + assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 304:36] + assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 313:35] + assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 317:35] + assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 319:36] + assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 325:35] assign axi4_to_ahb_1_clock = clock; assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 326:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 327:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 328:37] - assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 325:36] - assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 334:35] - assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 338:35] - assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 340:36] - assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 346:35] + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 332:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 333:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 334:37] + assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 331:36] + assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 340:35] + assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 344:35] + assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 346:36] + assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 352:35] assign axi4_to_ahb_2_clock = clock; assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 354:33] - assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 355:34] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 356:36] - assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 353:35] - assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 362:34] - assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 366:34] - assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 368:35] - assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 374:34] + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 360:33] + assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 361:34] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 362:36] + assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 359:35] + assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 368:34] + assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 372:34] + assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 374:35] + assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 380:34] assign ahb_to_axi4_clock = clock; assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 380:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 381:35] - assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 383:36] - assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 390:36] - assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 391:35] - assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 394:34] - assign ahb_to_axi4_io_ahb_haddr = io_dma_haddr; // @[quasar.scala 397:34] - assign ahb_to_axi4_io_ahb_hsize = io_dma_hsize; // @[quasar.scala 401:34] - assign ahb_to_axi4_io_ahb_htrans = io_dma_htrans; // @[quasar.scala 402:35] - assign ahb_to_axi4_io_ahb_hwrite = io_dma_hwrite; // @[quasar.scala 403:35] - assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 405:33] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 406:37] + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 386:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 387:35] + assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 389:36] + assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 396:36] + assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 397:35] + assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 400:34] + assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 411:33] + assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 412:37] + assign ahb_to_axi4_io_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar.scala 487:16] endmodule module quasar_wrapper( input clock, @@ -83832,18 +83832,18 @@ module quasar_wrapper( output [1:0] io_dma_axi_r_bits_resp, output io_dma_axi_r_bits_last, input io_dma_hsel, - input [31:0] io_dma_haddr, - input [2:0] io_dma_hburst, - input io_dma_hmastlock, - input [3:0] io_dma_hprot, - input [2:0] io_dma_hsize, - input [1:0] io_dma_htrans, - input io_dma_hwrite, - input [63:0] io_dma_hwdata, + output [63:0] io_dma_ahb_in_hrdata, + output io_dma_ahb_in_hready, + output io_dma_ahb_in_hresp, + input [31:0] io_dma_ahb_out_haddr, + input [2:0] io_dma_ahb_out_hburst, + input io_dma_ahb_out_hmastlock, + input [3:0] io_dma_ahb_out_hprot, + input [2:0] io_dma_ahb_out_hsize, + input [1:0] io_dma_ahb_out_htrans, + input io_dma_ahb_out_hwrite, + input [63:0] io_dma_ahb_out_hwdata, input io_dma_hreadyin, - output [63:0] io_dma_hrdata, - output io_dma_hreadyout, - output io_dma_hresp, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -83883,243 +83883,243 @@ module quasar_wrapper( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, input io_scan_mode ); - wire mem_clk; // @[quasar_wrapper.scala 78:19] - wire mem_rst_l; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_clk_override; // @[quasar_wrapper.scala 78:19] - wire mem_icm_clk_override; // @[quasar_wrapper.scala 78:19] - wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_wren; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_rden; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 78:19] - wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_correction_state; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_wren; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_rden; // @[quasar_wrapper.scala 78:19] - wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 78:19] - wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 78:19] - wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 78:19] - wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_rd_en; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 78:19] - wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 78:19] - wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 78:19] - wire mem_ic_tag_perr; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 78:19] - wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 78:19] - wire mem_scan_mode; // @[quasar_wrapper.scala 78:19] - wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tck; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tms; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 79:27] - wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 79:27] - wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 79:27] - wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 79:27] - wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 79:27] - wire core_clock; // @[quasar_wrapper.scala 80:20] - wire core_reset; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 80:20] - wire core_io_nmi_int; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_nmi_vec; // @[quasar_wrapper.scala 80:20] - wire core_io_core_rst_l; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 80:20] - wire [4:0] core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_clk_override; // @[quasar_wrapper.scala 80:20] - wire core_io_icm_clk_override; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 80:20] - wire core_io_i_cpu_halt_req; // @[quasar_wrapper.scala 80:20] - wire core_io_i_cpu_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_o_debug_mode_status; // @[quasar_wrapper.scala 80:20] - wire [27:0] core_io_core_id; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_reset_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_debug_brkpt_status; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_wren; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_rden; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_wr_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_rd_en; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_wr_data_0; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_wr_data_1; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 80:20] - wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_debug_rd_data; // @[quasar_wrapper.scala 80:20] - wire [25:0] core_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_eccerr; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_rd_hit; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_tag_perr; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_debug_way; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ic_premux_data; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 80:20] - wire [14:0] core_io_iccm_rw_addr; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_correction_state; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_wren; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_rden; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_iccm_wr_size; // @[quasar_wrapper.scala 80:20] - wire [77:0] core_io_iccm_wr_data; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_iccm_rd_data; // @[quasar_wrapper.scala 80:20] - wire [77:0] core_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hsel; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_haddr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_hsize; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_htrans; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hwrite; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hreadyin; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dmi_reg_en; // @[quasar_wrapper.scala 80:20] - wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 80:20] - wire core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 80:20] - wire core_io_timer_int; // @[quasar_wrapper.scala 80:20] - wire core_io_soft_int; // @[quasar_wrapper.scala 80:20] - wire core_io_scan_mode; // @[quasar_wrapper.scala 80:20] - mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 78:19] + wire mem_clk; // @[quasar_wrapper.scala 79:19] + wire mem_rst_l; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_clk_override; // @[quasar_wrapper.scala 79:19] + wire mem_icm_clk_override; // @[quasar_wrapper.scala 79:19] + wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_wren; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_rden; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 79:19] + wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_correction_state; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_wren; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_rden; // @[quasar_wrapper.scala 79:19] + wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 79:19] + wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 79:19] + wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 79:19] + wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_rd_en; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 79:19] + wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 79:19] + wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 79:19] + wire mem_ic_tag_perr; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 79:19] + wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 79:19] + wire mem_scan_mode; // @[quasar_wrapper.scala 79:19] + wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tck; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tms; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 80:27] + wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 80:27] + wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 80:27] + wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 80:27] + wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 80:27] + wire swerv_clock; // @[quasar_wrapper.scala 81:21] + wire swerv_reset; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 81:21] + wire swerv_io_nmi_int; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 81:21] + wire swerv_io_core_rst_l; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 81:21] + wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 81:21] + wire swerv_io_icm_clk_override; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 81:21] + wire swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 81:21] + wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_wren; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_rden; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_rd_en; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 81:21] + wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 81:21] + wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 81:21] + wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_wren; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_rden; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 81:21] + wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 81:21] + wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_hsel; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 81:21] + wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_timer_int; // @[quasar_wrapper.scala 81:21] + wire swerv_io_soft_int; // @[quasar_wrapper.scala 81:21] + wire swerv_io_scan_mode; // @[quasar_wrapper.scala 81:21] + mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 79:19] .clk(mem_clk), .rst_l(mem_rst_l), .dccm_clk_override(mem_dccm_clk_override), @@ -84167,7 +84167,7 @@ module quasar_wrapper( .ic_sel_premux_data(mem_ic_sel_premux_data), .scan_mode(mem_scan_mode) ); - dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 79:27] + dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 80:27] .trst_n(dmi_wrapper_trst_n), .tck(dmi_wrapper_tck), .tms(dmi_wrapper_tms), @@ -84184,417 +84184,417 @@ module quasar_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - quasar core ( // @[quasar_wrapper.scala 80:20] - .clock(core_clock), - .reset(core_reset), - .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), - .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), - .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), - .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), - .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_ready(core_io_lsu_axi_b_ready), - .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), - .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), - .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), - .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), - .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_ready(core_io_lsu_axi_r_ready), - .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), - .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), - .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), - .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), - .io_ifu_axi_aw_valid(core_io_ifu_axi_aw_valid), - .io_ifu_axi_w_valid(core_io_ifu_axi_w_valid), - .io_ifu_axi_b_ready(core_io_ifu_axi_b_ready), - .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), - .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), - .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_ready(core_io_ifu_axi_r_ready), - .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), - .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), - .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), - .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), - .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), - .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), - .io_sb_axi_w_ready(core_io_sb_axi_w_ready), - .io_sb_axi_w_valid(core_io_sb_axi_w_valid), - .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), - .io_sb_axi_b_ready(core_io_sb_axi_b_ready), - .io_sb_axi_b_valid(core_io_sb_axi_b_valid), - .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), - .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), - .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), - .io_sb_axi_r_ready(core_io_sb_axi_r_ready), - .io_sb_axi_r_valid(core_io_sb_axi_r_valid), - .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), - .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), - .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), - .io_dma_axi_w_ready(core_io_dma_axi_w_ready), - .io_dma_axi_w_valid(core_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(core_io_dma_axi_b_ready), - .io_dma_axi_b_valid(core_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), - .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), - .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(core_io_dma_axi_r_ready), - .io_dma_axi_r_valid(core_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), - .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), - .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), - .io_dbg_rst_l(core_io_dbg_rst_l), - .io_rst_vec(core_io_rst_vec), - .io_nmi_int(core_io_nmi_int), - .io_nmi_vec(core_io_nmi_vec), - .io_core_rst_l(core_io_core_rst_l), - .io_rv_trace_pkt_rv_i_valid_ip(core_io_rv_trace_pkt_rv_i_valid_ip), - .io_rv_trace_pkt_rv_i_insn_ip(core_io_rv_trace_pkt_rv_i_insn_ip), - .io_rv_trace_pkt_rv_i_address_ip(core_io_rv_trace_pkt_rv_i_address_ip), - .io_rv_trace_pkt_rv_i_exception_ip(core_io_rv_trace_pkt_rv_i_exception_ip), - .io_rv_trace_pkt_rv_i_ecause_ip(core_io_rv_trace_pkt_rv_i_ecause_ip), - .io_rv_trace_pkt_rv_i_interrupt_ip(core_io_rv_trace_pkt_rv_i_interrupt_ip), - .io_rv_trace_pkt_rv_i_tval_ip(core_io_rv_trace_pkt_rv_i_tval_ip), - .io_dccm_clk_override(core_io_dccm_clk_override), - .io_icm_clk_override(core_io_icm_clk_override), - .io_dec_tlu_core_ecc_disable(core_io_dec_tlu_core_ecc_disable), - .io_i_cpu_halt_req(core_io_i_cpu_halt_req), - .io_i_cpu_run_req(core_io_i_cpu_run_req), - .io_o_cpu_halt_ack(core_io_o_cpu_halt_ack), - .io_o_cpu_halt_status(core_io_o_cpu_halt_status), - .io_o_cpu_run_ack(core_io_o_cpu_run_ack), - .io_o_debug_mode_status(core_io_o_debug_mode_status), - .io_core_id(core_io_core_id), - .io_mpc_debug_halt_req(core_io_mpc_debug_halt_req), - .io_mpc_debug_run_req(core_io_mpc_debug_run_req), - .io_mpc_reset_run_req(core_io_mpc_reset_run_req), - .io_mpc_debug_halt_ack(core_io_mpc_debug_halt_ack), - .io_mpc_debug_run_ack(core_io_mpc_debug_run_ack), - .io_debug_brkpt_status(core_io_debug_brkpt_status), - .io_dec_tlu_perfcnt0(core_io_dec_tlu_perfcnt0), - .io_dec_tlu_perfcnt1(core_io_dec_tlu_perfcnt1), - .io_dec_tlu_perfcnt2(core_io_dec_tlu_perfcnt2), - .io_dec_tlu_perfcnt3(core_io_dec_tlu_perfcnt3), - .io_dccm_wren(core_io_dccm_wren), - .io_dccm_rden(core_io_dccm_rden), - .io_dccm_wr_addr_lo(core_io_dccm_wr_addr_lo), - .io_dccm_wr_addr_hi(core_io_dccm_wr_addr_hi), - .io_dccm_rd_addr_lo(core_io_dccm_rd_addr_lo), - .io_dccm_rd_addr_hi(core_io_dccm_rd_addr_hi), - .io_dccm_wr_data_lo(core_io_dccm_wr_data_lo), - .io_dccm_wr_data_hi(core_io_dccm_wr_data_hi), - .io_dccm_rd_data_lo(core_io_dccm_rd_data_lo), - .io_dccm_rd_data_hi(core_io_dccm_rd_data_hi), - .io_ic_rw_addr(core_io_ic_rw_addr), - .io_ic_tag_valid(core_io_ic_tag_valid), - .io_ic_wr_en(core_io_ic_wr_en), - .io_ic_rd_en(core_io_ic_rd_en), - .io_ic_wr_data_0(core_io_ic_wr_data_0), - .io_ic_wr_data_1(core_io_ic_wr_data_1), - .io_ic_debug_wr_data(core_io_ic_debug_wr_data), - .io_ic_debug_addr(core_io_ic_debug_addr), - .io_ic_rd_data(core_io_ic_rd_data), - .io_ic_debug_rd_data(core_io_ic_debug_rd_data), - .io_ic_tag_debug_rd_data(core_io_ic_tag_debug_rd_data), - .io_ic_eccerr(core_io_ic_eccerr), - .io_ic_rd_hit(core_io_ic_rd_hit), - .io_ic_tag_perr(core_io_ic_tag_perr), - .io_ic_debug_rd_en(core_io_ic_debug_rd_en), - .io_ic_debug_wr_en(core_io_ic_debug_wr_en), - .io_ic_debug_tag_array(core_io_ic_debug_tag_array), - .io_ic_debug_way(core_io_ic_debug_way), - .io_ic_premux_data(core_io_ic_premux_data), - .io_ic_sel_premux_data(core_io_ic_sel_premux_data), - .io_iccm_rw_addr(core_io_iccm_rw_addr), - .io_iccm_buf_correct_ecc(core_io_iccm_buf_correct_ecc), - .io_iccm_correction_state(core_io_iccm_correction_state), - .io_iccm_wren(core_io_iccm_wren), - .io_iccm_rden(core_io_iccm_rden), - .io_iccm_wr_size(core_io_iccm_wr_size), - .io_iccm_wr_data(core_io_iccm_wr_data), - .io_iccm_rd_data(core_io_iccm_rd_data), - .io_iccm_rd_data_ecc(core_io_iccm_rd_data_ecc), - .io_dma_hsel(core_io_dma_hsel), - .io_dma_haddr(core_io_dma_haddr), - .io_dma_hsize(core_io_dma_hsize), - .io_dma_htrans(core_io_dma_htrans), - .io_dma_hwrite(core_io_dma_hwrite), - .io_dma_hreadyin(core_io_dma_hreadyin), - .io_lsu_bus_clk_en(core_io_lsu_bus_clk_en), - .io_ifu_bus_clk_en(core_io_ifu_bus_clk_en), - .io_dbg_bus_clk_en(core_io_dbg_bus_clk_en), - .io_dma_bus_clk_en(core_io_dma_bus_clk_en), - .io_dmi_reg_en(core_io_dmi_reg_en), - .io_dmi_reg_addr(core_io_dmi_reg_addr), - .io_dmi_reg_wr_en(core_io_dmi_reg_wr_en), - .io_dmi_reg_wdata(core_io_dmi_reg_wdata), - .io_extintsrc_req(core_io_extintsrc_req), - .io_timer_int(core_io_timer_int), - .io_soft_int(core_io_soft_int), - .io_scan_mode(core_io_scan_mode) + quasar swerv ( // @[quasar_wrapper.scala 81:21] + .clock(swerv_clock), + .reset(swerv_reset), + .io_lsu_axi_aw_ready(swerv_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(swerv_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(swerv_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(swerv_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(swerv_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(swerv_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(swerv_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(swerv_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(swerv_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(swerv_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(swerv_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(swerv_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(swerv_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(swerv_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(swerv_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(swerv_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(swerv_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(swerv_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(swerv_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(swerv_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(swerv_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(swerv_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(swerv_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(swerv_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(swerv_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(swerv_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(swerv_io_lsu_axi_r_bits_resp), + .io_ifu_axi_aw_valid(swerv_io_ifu_axi_aw_valid), + .io_ifu_axi_w_valid(swerv_io_ifu_axi_w_valid), + .io_ifu_axi_b_ready(swerv_io_ifu_axi_b_ready), + .io_ifu_axi_ar_ready(swerv_io_ifu_axi_ar_ready), + .io_ifu_axi_ar_valid(swerv_io_ifu_axi_ar_valid), + .io_ifu_axi_ar_bits_id(swerv_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(swerv_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(swerv_io_ifu_axi_ar_bits_region), + .io_ifu_axi_r_ready(swerv_io_ifu_axi_r_ready), + .io_ifu_axi_r_valid(swerv_io_ifu_axi_r_valid), + .io_ifu_axi_r_bits_id(swerv_io_ifu_axi_r_bits_id), + .io_ifu_axi_r_bits_data(swerv_io_ifu_axi_r_bits_data), + .io_ifu_axi_r_bits_resp(swerv_io_ifu_axi_r_bits_resp), + .io_sb_axi_aw_ready(swerv_io_sb_axi_aw_ready), + .io_sb_axi_aw_valid(swerv_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_addr(swerv_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(swerv_io_sb_axi_aw_bits_region), + .io_sb_axi_aw_bits_size(swerv_io_sb_axi_aw_bits_size), + .io_sb_axi_w_ready(swerv_io_sb_axi_w_ready), + .io_sb_axi_w_valid(swerv_io_sb_axi_w_valid), + .io_sb_axi_w_bits_data(swerv_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(swerv_io_sb_axi_w_bits_strb), + .io_sb_axi_b_ready(swerv_io_sb_axi_b_ready), + .io_sb_axi_b_valid(swerv_io_sb_axi_b_valid), + .io_sb_axi_b_bits_resp(swerv_io_sb_axi_b_bits_resp), + .io_sb_axi_ar_ready(swerv_io_sb_axi_ar_ready), + .io_sb_axi_ar_valid(swerv_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_addr(swerv_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(swerv_io_sb_axi_ar_bits_region), + .io_sb_axi_ar_bits_size(swerv_io_sb_axi_ar_bits_size), + .io_sb_axi_r_ready(swerv_io_sb_axi_r_ready), + .io_sb_axi_r_valid(swerv_io_sb_axi_r_valid), + .io_sb_axi_r_bits_data(swerv_io_sb_axi_r_bits_data), + .io_sb_axi_r_bits_resp(swerv_io_sb_axi_r_bits_resp), + .io_dma_axi_aw_ready(swerv_io_dma_axi_aw_ready), + .io_dma_axi_aw_valid(swerv_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(swerv_io_dma_axi_aw_bits_id), + .io_dma_axi_aw_bits_addr(swerv_io_dma_axi_aw_bits_addr), + .io_dma_axi_aw_bits_size(swerv_io_dma_axi_aw_bits_size), + .io_dma_axi_w_ready(swerv_io_dma_axi_w_ready), + .io_dma_axi_w_valid(swerv_io_dma_axi_w_valid), + .io_dma_axi_w_bits_data(swerv_io_dma_axi_w_bits_data), + .io_dma_axi_w_bits_strb(swerv_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(swerv_io_dma_axi_b_ready), + .io_dma_axi_b_valid(swerv_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(swerv_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(swerv_io_dma_axi_b_bits_id), + .io_dma_axi_ar_ready(swerv_io_dma_axi_ar_ready), + .io_dma_axi_ar_valid(swerv_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(swerv_io_dma_axi_ar_bits_id), + .io_dma_axi_ar_bits_addr(swerv_io_dma_axi_ar_bits_addr), + .io_dma_axi_ar_bits_size(swerv_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(swerv_io_dma_axi_r_ready), + .io_dma_axi_r_valid(swerv_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(swerv_io_dma_axi_r_bits_id), + .io_dma_axi_r_bits_data(swerv_io_dma_axi_r_bits_data), + .io_dma_axi_r_bits_resp(swerv_io_dma_axi_r_bits_resp), + .io_dma_ahb_out_haddr(swerv_io_dma_ahb_out_haddr), + .io_dma_ahb_out_hsize(swerv_io_dma_ahb_out_hsize), + .io_dma_ahb_out_htrans(swerv_io_dma_ahb_out_htrans), + .io_dma_ahb_out_hwrite(swerv_io_dma_ahb_out_hwrite), + .io_dbg_rst_l(swerv_io_dbg_rst_l), + .io_rst_vec(swerv_io_rst_vec), + .io_nmi_int(swerv_io_nmi_int), + .io_nmi_vec(swerv_io_nmi_vec), + .io_core_rst_l(swerv_io_core_rst_l), + .io_rv_trace_pkt_rv_i_valid_ip(swerv_io_rv_trace_pkt_rv_i_valid_ip), + .io_rv_trace_pkt_rv_i_insn_ip(swerv_io_rv_trace_pkt_rv_i_insn_ip), + .io_rv_trace_pkt_rv_i_address_ip(swerv_io_rv_trace_pkt_rv_i_address_ip), + .io_rv_trace_pkt_rv_i_exception_ip(swerv_io_rv_trace_pkt_rv_i_exception_ip), + .io_rv_trace_pkt_rv_i_ecause_ip(swerv_io_rv_trace_pkt_rv_i_ecause_ip), + .io_rv_trace_pkt_rv_i_interrupt_ip(swerv_io_rv_trace_pkt_rv_i_interrupt_ip), + .io_rv_trace_pkt_rv_i_tval_ip(swerv_io_rv_trace_pkt_rv_i_tval_ip), + .io_dccm_clk_override(swerv_io_dccm_clk_override), + .io_icm_clk_override(swerv_io_icm_clk_override), + .io_dec_tlu_core_ecc_disable(swerv_io_dec_tlu_core_ecc_disable), + .io_i_cpu_halt_req(swerv_io_i_cpu_halt_req), + .io_i_cpu_run_req(swerv_io_i_cpu_run_req), + .io_o_cpu_halt_ack(swerv_io_o_cpu_halt_ack), + .io_o_cpu_halt_status(swerv_io_o_cpu_halt_status), + .io_o_cpu_run_ack(swerv_io_o_cpu_run_ack), + .io_o_debug_mode_status(swerv_io_o_debug_mode_status), + .io_core_id(swerv_io_core_id), + .io_mpc_debug_halt_req(swerv_io_mpc_debug_halt_req), + .io_mpc_debug_run_req(swerv_io_mpc_debug_run_req), + .io_mpc_reset_run_req(swerv_io_mpc_reset_run_req), + .io_mpc_debug_halt_ack(swerv_io_mpc_debug_halt_ack), + .io_mpc_debug_run_ack(swerv_io_mpc_debug_run_ack), + .io_debug_brkpt_status(swerv_io_debug_brkpt_status), + .io_dec_tlu_perfcnt0(swerv_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(swerv_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(swerv_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(swerv_io_dec_tlu_perfcnt3), + .io_dccm_wren(swerv_io_dccm_wren), + .io_dccm_rden(swerv_io_dccm_rden), + .io_dccm_wr_addr_lo(swerv_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(swerv_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(swerv_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(swerv_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(swerv_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(swerv_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(swerv_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(swerv_io_dccm_rd_data_hi), + .io_ic_rw_addr(swerv_io_ic_rw_addr), + .io_ic_tag_valid(swerv_io_ic_tag_valid), + .io_ic_wr_en(swerv_io_ic_wr_en), + .io_ic_rd_en(swerv_io_ic_rd_en), + .io_ic_wr_data_0(swerv_io_ic_wr_data_0), + .io_ic_wr_data_1(swerv_io_ic_wr_data_1), + .io_ic_debug_wr_data(swerv_io_ic_debug_wr_data), + .io_ic_debug_addr(swerv_io_ic_debug_addr), + .io_ic_rd_data(swerv_io_ic_rd_data), + .io_ic_debug_rd_data(swerv_io_ic_debug_rd_data), + .io_ic_tag_debug_rd_data(swerv_io_ic_tag_debug_rd_data), + .io_ic_eccerr(swerv_io_ic_eccerr), + .io_ic_rd_hit(swerv_io_ic_rd_hit), + .io_ic_tag_perr(swerv_io_ic_tag_perr), + .io_ic_debug_rd_en(swerv_io_ic_debug_rd_en), + .io_ic_debug_wr_en(swerv_io_ic_debug_wr_en), + .io_ic_debug_tag_array(swerv_io_ic_debug_tag_array), + .io_ic_debug_way(swerv_io_ic_debug_way), + .io_ic_premux_data(swerv_io_ic_premux_data), + .io_ic_sel_premux_data(swerv_io_ic_sel_premux_data), + .io_iccm_rw_addr(swerv_io_iccm_rw_addr), + .io_iccm_buf_correct_ecc(swerv_io_iccm_buf_correct_ecc), + .io_iccm_correction_state(swerv_io_iccm_correction_state), + .io_iccm_wren(swerv_io_iccm_wren), + .io_iccm_rden(swerv_io_iccm_rden), + .io_iccm_wr_size(swerv_io_iccm_wr_size), + .io_iccm_wr_data(swerv_io_iccm_wr_data), + .io_iccm_rd_data(swerv_io_iccm_rd_data), + .io_iccm_rd_data_ecc(swerv_io_iccm_rd_data_ecc), + .io_dma_hsel(swerv_io_dma_hsel), + .io_dma_hreadyin(swerv_io_dma_hreadyin), + .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en), + .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en), + .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en), + .io_dma_bus_clk_en(swerv_io_dma_bus_clk_en), + .io_dmi_reg_en(swerv_io_dmi_reg_en), + .io_dmi_reg_addr(swerv_io_dmi_reg_addr), + .io_dmi_reg_wr_en(swerv_io_dmi_reg_wr_en), + .io_dmi_reg_wdata(swerv_io_dmi_reg_wdata), + .io_extintsrc_req(swerv_io_extintsrc_req), + .io_timer_int(swerv_io_timer_int), + .io_soft_int(swerv_io_soft_int), + .io_scan_mode(swerv_io_scan_mode) ); - assign io_lsu_axi_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 141:19] - assign io_sb_axi_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_dma_axi_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 148:19] - assign io_dma_hrdata = 64'h0; // @[quasar_wrapper.scala 195:17] - assign io_dma_hreadyout = 1'h0; // @[quasar_wrapper.scala 196:20] - assign io_dma_hresp = 1'h0; // @[quasar_wrapper.scala 197:16] - assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 185:23] - assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 186:23] - assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 187:23] - assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 188:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 96:15] - assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 181:25] - assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 182:24] - assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 183:25] - assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 176:21] - assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 177:24] - assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 179:26] - assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 178:20] - assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 173:19] - assign mem_clk = clock; // @[quasar_wrapper.scala 104:14] - assign mem_rst_l = reset; // @[quasar_wrapper.scala 103:16] - assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 99:28] - assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 100:27] - assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 101:35] - assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 102:15] - assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 109:16] - assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 108:14] - assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 108:14] - assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 108:14] - assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 108:14] - assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 105:20] - assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 81:25] - assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 82:22] - assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 83:22] - assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 84:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 90:29] - assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 85:27] - assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 86:26] - assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 87:26] - assign core_clock = clock; - assign core_reset = reset; - assign core_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 138:19] - assign core_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 141:19] - assign core_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 144:18] - assign core_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 148:19] - assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 107:21 quasar_wrapper.scala 121:21] - assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] - assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] - assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:19] - assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:26] - assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:25] - assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:19] - assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:30] - assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:29] - assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:29] - assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 102:15] - assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 102:15] - assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 108:14] - assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 109:16] - assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 109:16] - assign core_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 151:20] - assign core_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 152:21] - assign core_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 156:21] - assign core_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 157:22] - assign core_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 158:22] - assign core_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 160:24] - assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 162:26] - assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 163:26] - assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 164:26] - assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 165:26] - assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 93:22] - assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 92:24] - assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 94:25] - assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 91:25] - assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 169:25] - assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 167:21] - assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 168:20] - assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 119:21] + assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 147:20] + assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 154:20] + assign io_dma_ahb_in_hrdata = 64'h0; // @[quasar_wrapper.scala 115:19] + assign io_dma_ahb_in_hready = 1'h0; // @[quasar_wrapper.scala 115:19] + assign io_dma_ahb_in_hresp = 1'h0; // @[quasar_wrapper.scala 115:19] + assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 208:23] + assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 209:23] + assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 210:23] + assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 211:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 97:15] + assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 204:25] + assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 205:24] + assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 206:25] + assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 199:21] + assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 200:24] + assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 202:26] + assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 201:20] + assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 196:19] + assign mem_clk = clock; // @[quasar_wrapper.scala 105:14] + assign mem_rst_l = reset; // @[quasar_wrapper.scala 104:16] + assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 100:28] + assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 101:27] + assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 102:35] + assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 103:15] + assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 110:17] + assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 109:15] + assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 109:15] + assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 109:15] + assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 109:15] + assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 106:20] + assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 82:25] + assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 83:22] + assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 84:22] + assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 85:22] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 91:29] + assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 86:27] + assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 87:26] + assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 88:26] + assign swerv_clock = clock; + assign swerv_reset = reset; + assign swerv_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 144:20] + assign swerv_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 147:20] + assign swerv_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 150:19] + assign swerv_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 108:22 quasar_wrapper.scala 127:22] + assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 128:20] + assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 129:20] + assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 130:20] + assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 133:27] + assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 134:26] + assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 135:20] + assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 138:31] + assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 139:30] + assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 140:30] + assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 103:15] + assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 103:15] + assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 109:15] + assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 110:17] + assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 110:17] + assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 157:21] + assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 167:25] + assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 185:27] + assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 186:27] + assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 187:27] + assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 188:27] + assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 94:23] + assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 93:25] + assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 95:26] + assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 92:26] + assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 192:26] + assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 190:22] + assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 191:21] + assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 125:22] endmodule diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index fc207b68..0f860ae7 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type } +object dbg extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) +} \ No newline at end of file diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 2be96902..662fd32d 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -34,7 +34,7 @@ class tlu_dma extends Bundle{ class dec_bp extends Bundle{ val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t)) -// val dec_tlu_flush_lower_wb = Input(Bool()) + // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_leak_one_wb = Input(Bool()) val dec_tlu_bpred_disable = Input(Bool()) } @@ -44,6 +44,25 @@ class dec_ifc extends Bundle{ val dec_tlu_mrac_ff = Input(UInt(32.W)) val ifu_pmu_fetch_stall = Output(Bool()) } +class ahb_in extends Bundle{ + val hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data + val hready = Input(Bool()) // slave ready to accept transaction + val hresp = Input(Bool()) // slave response (high indicates erro) +} +class ahb_out extends Bundle{ + val haddr = Output(UInt(32.W)) // [31:0] // ahb bus address + val hburst = Output(UInt(3.W)) // [2:0] // tied to 0 + val hmastlock = Output(Bool()) // tied to 0 + val hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 + val hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) + val htrans = Output(UInt(2.W)) + val hwrite = Output(Bool()) // ahb bus write + val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data +} +class ahb_channel extends Bundle{ + val in = Input(new ahb_in) + val out = Output(new ahb_out) +} class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ val aw = Decoupled(new write_addr(BUS_TAG)) val w = Decoupled(new write_data()) @@ -92,7 +111,7 @@ class write_resp(val TAG : Int=3) extends Bundle with lib{ // write_response } class dec_mem_ctrl extends Bundle with lib{ -// val dec_tlu_flush_lower_wb = Input(Bool()) + // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_err_wb = Input(Bool()) val dec_tlu_i0_commit_cmt = Input(Bool()) val dec_tlu_force_halt = Input(Bool()) @@ -288,7 +307,7 @@ class dbg_ib extends Bundle{ } class dbg_dctl extends Bundle{ - val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i + val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i } @@ -402,7 +421,7 @@ class rets_pkt_t extends Bundle { } class br_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val toffset = UInt(12.W) val hist = UInt(2.W) val br_error = UInt(1.W) @@ -415,7 +434,7 @@ class br_pkt_t extends Bundle { class br_tlu_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val hist = UInt(2.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) @@ -430,7 +449,7 @@ class predict_pkt_t extends Bundle { val pc4 = UInt(1.W) val hist = UInt(2.W) val toffset = UInt(12.W) - // val valid = UInt(1.W) + // val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) val prett = UInt(31.W) @@ -460,7 +479,7 @@ class dest_pkt_t extends Bundle { val i0store = UInt(1.W) val i0div = UInt(1.W) val i0v = UInt(1.W) - // val i0valid = UInt(1.W) + // val i0valid = UInt(1.W) val csrwen = UInt(1.W) val csrwonly = UInt(1.W) val csrwaddr = UInt(12.W) @@ -514,11 +533,11 @@ class lsu_pkt_t extends Bundle { val store_data_bypass_d = Bool() val load_ldst_bypass_d = Bool() val store_data_bypass_m = Bool() -// val valid = Bool() + // val valid = Bool() } class lsu_error_pkt_t extends Bundle { - // val exc_valid = UInt(1.W) + // val exc_valid = UInt(1.W) val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault @@ -580,7 +599,7 @@ class dec_pkt_t extends Bundle { } class mul_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val rs1_sign = UInt(1.W) val rs2_sign = UInt(1.W) val low = UInt(1.W) @@ -602,7 +621,7 @@ class mul_pkt_t extends Bundle { } class div_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val unsign = UInt(1.W) val rem = UInt(1.W) } @@ -744,4 +763,4 @@ class dec_tlu_csr_pkt extends Bundle{ val presync =UInt(1.W) val postsync =UInt(1.W) val legal =UInt(1.W) -} +} \ No newline at end of file diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 2b75019d..63a820b7 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -20,14 +20,14 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val axi_rid = Input(UInt(TAG.W)) val axi_rdata = Input(UInt(64.W)) val axi_rresp = Input(UInt(2.W)) - val ahb_haddr = Input(UInt(32.W)) // ahb bus address - val ahb_hburst = Input(UInt(3.W)) // tied to 0 - val ahb_hmastlock = Input(Bool()) // tied to 0 - val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 - val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) - val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) - val ahb_hwrite = Input(Bool()) // ahb bus write - val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data + // val ahb_haddr = Input(UInt(32.W)) // ahb bus address + // val ahb_hburst = Input(UInt(3.W)) // tied to 0 + // val ahb_hmastlock = Input(Bool()) // tied to 0 + // val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 + // val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) + // val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) + // val ahb_hwrite = Input(Bool()) // ahb bus write + // val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data val ahb_hsel = Input(Bool()) // this slave was selected val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not // outputs @@ -51,9 +51,10 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val axi_arlen = Output(UInt(8.W)) val axi_arburst = Output(UInt(2.W)) val axi_rready = Output(Bool()) - val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data - val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction - val ahb_hresp = Output(Bool()) // slave response (high indicates erro) + val ahb = Flipped(new ahb_channel()) + // val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data + // val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction + // val ahb_hresp = Output(Bool()) // slave response (high indicates erro) }) val idle:: wr :: rd :: pend :: Nil = Enum(4) val TAG= 1 @@ -114,18 +115,18 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { switch(buf_state) { is(idle) { - buf_nxtstate := Mux(io.ahb_hwrite, wr, rd) - buf_state_en := ahb_hready & io.ahb_htrans(1) & io.ahb_hsel // only transition on a valid hrtans + buf_nxtstate := Mux(io.ahb.out.hwrite, wr, rd) + buf_state_en := ahb_hready & io.ahb.out.htrans(1) & io.ahb_hsel // only transition on a valid hrtans } is(wr) { // Write command recieved last cycle - buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd)) - buf_state_en := (!cmdbuf_full | io.ahb_hresp) - cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. + buf_nxtstate := Mux((io.ahb.in.hresp | (io.ahb.out.htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb.out.hwrite, wr, rd)) + buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) + cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.in.hresp | ((io.ahb.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. } is(rd) { // Read command recieved last cycle. - buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data - buf_state_en := (!cmdbuf_full | io.ahb_hresp) // only when command can go, or if its an error - cmdbuf_wr_en := !io.ahb_hresp & !cmdbuf_full // send command only when no error + buf_nxtstate := Mux(io.ahb.in.hresp, idle, pend) // If error go to idle, else wait for read data + buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) // only when command can go, or if its an error + cmdbuf_wr_en := !io.ahb.in.hresp & !cmdbuf_full // send command only when no error } is(pend) { // Read Command has been sent. Waiting on Data. buf_nxtstate := idle // go back for next command and present data next cycle @@ -142,11 +143,11 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { (Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U) // AHB signals - io.ahb_hreadyout := Mux(io.ahb_hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) - ahb_hready := io.ahb_hreadyout & io.ahb_hreadyin - ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb_htrans(1,0) - io.ahb_hrdata := buf_rdata(63,0) - io.ahb_hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & + io.ahb.in.hready := Mux(io.ahb.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) + ahb_hready := io.ahb.in.hready & io.ahb_hreadyin + ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb.out.htrans(1,0) + io.ahb.in.hrdata := buf_rdata(63,0) + io.ahb.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned @@ -160,22 +161,22 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)} // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer. - ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb_hresp,0.U)} + ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.in.hresp,0.U)} ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)} ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)} - ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb_hsize,0.U)} - ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb_hwrite,0.U)} - ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb_haddr,0.U)} + ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hsize,0.U)} + ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hwrite,0.U)} + ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.haddr,0.U)} // Clock header logic - ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb_htrans(1)) + ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.out.htrans(1)) buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en; ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode) buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode) - cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write) + cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.in.hresp & !cmdbuf_write) cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready))) //rvdffsc cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)} @@ -192,7 +193,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { //rvdffe cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) - cmdbuf_wdata := rvdffe(io.ahb_hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) + cmdbuf_wdata := rvdffe(io.ahb.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) // AXI Write Command Channel io.axi_awvalid := cmdbuf_vld & cmdbuf_write @@ -222,4 +223,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) -} \ No newline at end of file +} +object AHB_main extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))} \ No newline at end of file diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index d237bee7..81f42ba3 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -2,6 +2,7 @@ package lib import chisel3._ import chisel3.util._ +import include._ trait Config { val TAG = 1 @@ -28,9 +29,6 @@ class axi4_to_ahb_IO extends Bundle with Config { val axi_arsize = Input(UInt(3.W)) // [2:0] val axi_arprot = Input(UInt(3.W)) // [2:0] val axi_rready = Input(Bool()) - val ahb_hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data - val ahb_hready = Input(Bool()) // slave ready to accept transaction - val ahb_hresp = Input(Bool()) // slave response (high indicates erro) //----------------------------outputs--------------------------- val axi_awready = Output(Bool()) val axi_wready = Output(Bool()) @@ -45,16 +43,12 @@ class axi4_to_ahb_IO extends Bundle with Config { val axi_rresp = Output(UInt(2.W)) // 1:0] val axi_rlast = Output(Bool()) // AHB-Lite signals - val ahb_haddr = Output(UInt(32.W)) // [31:0] // ahb bus address - val ahb_hburst = Output(UInt(3.W)) // [2:0] // tied to 0 - val ahb_hmastlock = Output(Bool()) // tied to 0 - val ahb_hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 - val ahb_hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) - val ahb_htrans = Output(UInt(2.W)) - val ahb_hwrite = Output(Bool()) // ahb bus write - val ahb_hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data + val ahb = new ahb_channel } + + + class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) val buf_rst = WireInit(0.U(1.W)) @@ -202,7 +196,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode) //State machine - io.ahb_htrans := 0.U + io.ahb.out.htrans := 0.U master_ready := 0.U buf_state_en := false.B buf_nxtstate := idle @@ -233,7 +227,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B)), master_addr(2, 0)) bypass_en := buf_state_en rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd) - io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U + io.ahb.out.htrans := (Fill(2, bypass_en)) & "b10".U } is(cmd_rd) { @@ -245,7 +239,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { buf_wr_en := master_ready bypass_en := master_ready & master_valid buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) - io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) + io.ahb.out.htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) } is(stream_rd) { @@ -260,7 +254,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) - io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) + io.ahb.out.htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) slvbuf_wr_en := buf_wr_en// shifting the contents from the buf to slv_buf for streaming cases } @@ -270,7 +264,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slave_valid_pre := buf_state_en slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer buf_cmd_byte_ptr := buf_addr(2, 0) - io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en) + io.ahb.out.htrans := "b10".U(2.W) & Fill(2, !buf_state_en) } is(data_rd) { @@ -290,7 +284,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slvbuf_wr_en := buf_state_en buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)), buf_cmd_byte_ptrQ) cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U)) - io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U + io.ahb.out.htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U } is(data_wr) { @@ -305,7 +299,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1,0) =/= 0.U) & ((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)) === 0.U)))) bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) - io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U + io.ahb.out.htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U) buf_cmd_byte_ptr_en := trxn_done | bypass_en @@ -349,21 +343,21 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) | (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) // Generate the ahb signals - io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) - io.ahb_hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))) + io.ahb.out.haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) + io.ahb.out.hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))) - io.ahb_hburst := "b0".U - io.ahb_hmastlock := "b0".U - io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2)) - io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) - io.ahb_hwdata := buf_data(63, 0) + io.ahb.out.hburst := "b0".U + io.ahb.out.hmastlock := "b0".U + io.ahb.out.hprot := Cat("b001".U, ~io.axi_arprot(2)) + io.ahb.out.hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) + io.ahb.out.hwdata := buf_data(63, 0) slave_valid := slave_valid_pre slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U) slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0))) slave_tag := slvbuf_tag(TAG - 1, 0) - last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite + last_addr_en := (io.ahb.out.htrans(1, 0) =/= "b0".U) & io.ahb.in.hready & io.ahb.out.hwrite // Write buffer wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready @@ -382,7 +376,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,bus_clk,io.scan_mode) wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,bus_clk,io.scan_mode) wrbuf_byteen := withClock(bus_clk) {RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())} - last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())} + last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb.out.haddr(31, 0), 0.U, last_addr_en.asBool())} buf_write := withClock(buf_clk) {RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())} buf_tag := withClock(buf_clk) {RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())} buf_addr := rvdffe(buf_addr_in(31, 0),(buf_wr_en & io.bus_clk_en).asBool,clock,io.scan_mode) @@ -395,14 +389,14 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slvbuf_error := withClock(ahbm_clk) {RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())} cmd_doneQ := withClock(ahbm_clk) {RegNext(Mux(cmd_done.asBool(),1.U,cmd_doneQ) & !cmd_done_rst, 0.U)} buf_cmd_byte_ptrQ := withClock(ahbm_clk) {RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())} - ahb_hready_q := withClock(ahbm_clk) {RegNext(io.ahb_hready, 0.U)} - ahb_htrans_q := withClock(ahbm_clk) {RegNext(io.ahb_htrans(1, 0), 0.U)} - ahb_hwrite_q := withClock(ahbm_addr_clk) {RegNext(io.ahb_hwrite, 0.U)} - ahb_hresp_q := withClock(ahbm_clk) {RegNext(io.ahb_hresp, 0.U)} - ahb_hrdata_q := withClock(ahbm_data_clk) {RegNext(io.ahb_hrdata(63, 0), 0.U)} + ahb_hready_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hready, 0.U)} + ahb_htrans_q := withClock(ahbm_clk) {RegNext(io.ahb.out.htrans(1, 0), 0.U)} + ahb_hwrite_q := withClock(ahbm_addr_clk) {RegNext(io.ahb.out.hwrite, 0.U)} + ahb_hresp_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hresp, 0.U)} + ahb_hrdata_q := withClock(ahbm_data_clk) {RegNext(io.ahb.in.hrdata(63, 0), 0.U)} buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) - ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override) + ahbm_addr_clken := io.bus_clk_en & ((io.ahb.in.hready & io.ahb.out.htrans(1)) | io.clk_override) ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) //Clkhdr @@ -410,4 +404,9 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) +} + +object AXImain extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) } \ No newline at end of file diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 365ee5ee..00235400 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -14,6 +14,11 @@ class quasar_bundle extends Bundle with lib{ val sb_axi = new axi_channels(SB_BUS_TAG) val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) + val ahb = new ahb_channel + val lsu_ahb = new ahb_channel + val sb_ahb = new ahb_channel + val dma_ahb = Flipped(new ahb_channel) + val dbg_rst_l = Input(AsyncReset()) val rst_vec = Input(UInt(31.W)) val nmi_int = Input(Bool()) @@ -44,58 +49,59 @@ class quasar_bundle extends Bundle with lib{ val ic = new ic_mem() val iccm = new iccm_mem() - // AHB Lite Bus - val haddr = Output(UInt(32.W)) - val hburst = Output(UInt(3.W)) - val hmastlock = Output(Bool()) - val hprot = Output(UInt(4.W)) - val hsize = Output(UInt(3.W)) - val htrans = Output(UInt(2.W)) - val hwrite = Output(Bool()) - val hrdata = Input(UInt(64.W)) - val hready = Input(Bool()) - val hresp = Input(Bool()) - - // AHB Master - val lsu_haddr = Output(UInt(32.W)) - val lsu_hburst = Output(UInt(3.W)) - val lsu_hmastlock = Output(Bool()) - val lsu_hprot = Output(UInt(4.W)) - val lsu_hsize = Output(UInt(3.W)) - val lsu_htrans = Output(UInt(2.W)) - val lsu_hwrite = Output(Bool()) - val lsu_hwdata = Output(UInt(64.W)) - val lsu_hrdata = Input(UInt(64.W)) - val lsu_hready = Input(Bool()) - val lsu_hresp = Input(Bool()) - - // System Bus Debug Master - val sb_haddr = Output(UInt(32.W)) - val sb_hburst = Output(UInt(3.W)) - val sb_hmastlock = Output(Bool()) - val sb_hprot = Output(UInt(4.W)) - val sb_hsize = Output(UInt(3.W)) - val sb_htrans = Output(UInt(2.W)) - val sb_hwrite = Output(Bool()) - val sb_hwdata = Output(UInt(64.W)) - val sb_hrdata = Input(UInt(64.W)) - val sb_hready = Input(Bool()) - val sb_hresp = Input(Bool()) - - // DMA slave + // // AHB Lite Bus + // val haddr = Output(UInt(32.W)) + // val hburst = Output(UInt(3.W)) + // val hmastlock = Output(Bool()) + // val hprot = Output(UInt(4.W)) + // val hsize = Output(UInt(3.W)) + // val htrans = Output(UInt(2.W)) + // val hwrite = Output(Bool()) + // val hrdata = Input(UInt(64.W)) + // val hready = Input(Bool()) + // val hresp = Input(Bool()) + // + // // AHB Master + // val lsu_haddr = Output(UInt(32.W)) + // val lsu_hburst = Output(UInt(3.W)) + // val lsu_hmastlock = Output(Bool()) + // val lsu_hprot = Output(UInt(4.W)) + // val lsu_hsize = Output(UInt(3.W)) + // val lsu_htrans = Output(UInt(2.W)) + // val lsu_hwrite = Output(Bool()) + // val lsu_hwdata = Output(UInt(64.W)) + // val lsu_hrdata = Input(UInt(64.W)) + // val lsu_hready = Input(Bool()) + // val lsu_hresp = Input(Bool()) + // + // // System Bus Debug Master + // val sb_haddr = Output(UInt(32.W)) + // val sb_hburst = Output(UInt(3.W)) + // val sb_hmastlock = Output(Bool()) + // val sb_hprot = Output(UInt(4.W)) + // val sb_hsize = Output(UInt(3.W)) + // val sb_htrans = Output(UInt(2.W)) + // val sb_hwrite = Output(Bool()) + // val sb_hwdata = Output(UInt(64.W)) + // val sb_hrdata = Input(UInt(64.W)) + // val sb_hready = Input(Bool()) + // val sb_hresp = Input(Bool()) + // + // // DMA slave val dma_hsel = Input(Bool()) - val dma_haddr = Input(UInt(32.W)) - val dma_hburst = Input(UInt(3.W)) - val dma_hmastlock = Input(Bool()) - val dma_hprot = Input(UInt(4.W)) - val dma_hsize = Input(UInt(3.W)) - val dma_htrans = Input(UInt(2.W)) - val dma_hwrite = Input(Bool()) - val dma_hwdata = Input(UInt(64.W)) + // val dma_haddr = Input(UInt(32.W)) + // val dma_hburst = Input(UInt(3.W)) + // val dma_hmastlock = Input(Bool()) + // val dma_hprot = Input(UInt(4.W)) + // val dma_hsize = Input(UInt(3.W)) + // val dma_htrans = Input(UInt(2.W)) + // val dma_hwrite = Input(Bool()) + // val dma_hwdata = Input(UInt(64.W)) val dma_hreadyin = Input(Bool()) - val dma_hrdata = Output(UInt(64.W)) - val dma_hreadyout = Output(Bool()) - val dma_hresp = Output(Bool()) + // val dma_hrdata = Output(UInt(64.W)) + // val dma_hreadyout = Output(Bool()) + // val dma_hresp = Output(Bool()) + val lsu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool()) val dbg_bus_clk_en = Input(Bool()) @@ -317,9 +323,9 @@ class quasar extends Module with RequireAsyncReset with lib { lsu_axi4_to_ahb.io.axi_arprot := io.lsu_axi.ar.bits.prot lsu_axi4_to_ahb.io.axi_rready := io.lsu_axi.r.ready - lsu_axi4_to_ahb.io.ahb_hrdata := io.lsu_hrdata - lsu_axi4_to_ahb.io.ahb_hready := io.lsu_hready - lsu_axi4_to_ahb.io.ahb_hresp := io.lsu_hresp + // lsu_axi4_to_ahb.io.ahb_hrdata := io.lsu_hrdata + // lsu_axi4_to_ahb.io.ahb_hready := io.lsu_hready + // lsu_axi4_to_ahb.io.ahb_hresp := io.lsu_hresp val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) ifu_axi4_to_ahb.io.axi_awvalid := io.ifu_axi.aw.valid @@ -345,9 +351,9 @@ class quasar extends Module with RequireAsyncReset with lib { ifu_axi4_to_ahb.io.axi_rready := io.ifu_axi.r.ready - ifu_axi4_to_ahb.io.ahb_hrdata := io.hrdata - ifu_axi4_to_ahb.io.ahb_hready := io.hready - ifu_axi4_to_ahb.io.ahb_hresp := io.hresp + // ifu_axi4_to_ahb.io.ahb_hrdata := io.hrdata + // ifu_axi4_to_ahb.io.ahb_hready := io.hready + // ifu_axi4_to_ahb.io.ahb_hresp := io.hresp val sb_axi4_to_ahb = Module(new axi4_to_ahb()) sb_axi4_to_ahb.io.axi_awvalid := io.sb_axi.aw.valid @@ -372,9 +378,9 @@ class quasar extends Module with RequireAsyncReset with lib { sb_axi4_to_ahb.io.axi_arprot := io.sb_axi.ar.bits.prot sb_axi4_to_ahb.io.axi_rready := io.sb_axi.r.ready - sb_axi4_to_ahb.io.ahb_hrdata := io.sb_hrdata - sb_axi4_to_ahb.io.ahb_hready := io.sb_hready - sb_axi4_to_ahb.io.ahb_hresp := io.sb_hresp + // sb_axi4_to_ahb.io.ahb_hrdata := io.sb_hrdata + // sb_axi4_to_ahb.io.ahb_hready := io.sb_hready + // sb_axi4_to_ahb.io.ahb_hresp := io.sb_hresp val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) dma_ahb_to_axi4.io.scan_mode := io.scan_mode @@ -394,18 +400,16 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ahb_to_axi4.io.axi_rresp := io.dma_axi.r.bits.resp // AHB-Lite signals - dma_ahb_to_axi4.io.ahb_haddr := io.dma_haddr - dma_ahb_to_axi4.io.ahb_hburst := io.dma_hburst - dma_ahb_to_axi4.io.ahb_hmastlock := io.dma_hmastlock - dma_ahb_to_axi4.io.ahb_hprot := io.dma_hprot - dma_ahb_to_axi4.io.ahb_hsize := io.dma_hsize - dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans - dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite - dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata + // dma_ahb_to_axi4.io.ahb_haddr := io.dma_haddr + // dma_ahb_to_axi4.io.ahb_hburst := io.dma_hburst + // dma_ahb_to_axi4.io.ahb_hmastlock := io.dma_hmastlock + // dma_ahb_to_axi4.io.ahb_hprot := io.dma_hprot + // dma_ahb_to_axi4.io.ahb_hsize := io.dma_hsize + // dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans + // dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite + // dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin - - // Mux for the axi-bridge lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @@ -450,77 +454,81 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) - - // AHB Signals - io.haddr := ifu_axi4_to_ahb.io.ahb_haddr - io.hburst := ifu_axi4_to_ahb.io.ahb_hburst - io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock - io.hprot := ifu_axi4_to_ahb.io.ahb_hprot - io.hsize := ifu_axi4_to_ahb.io.ahb_hsize - io.htrans := ifu_axi4_to_ahb.io.ahb_htrans - io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite + io.ahb <> ifu_axi4_to_ahb.io.ahb + // io.haddr := ifu_axi4_to_ahb.io.ahb_haddr + // io.hburst := ifu_axi4_to_ahb.io.ahb_hburst + // io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock + // io.hprot := ifu_axi4_to_ahb.io.ahb_hprot + // io.hsize := ifu_axi4_to_ahb.io.ahb_hsize + // io.htrans := ifu_axi4_to_ahb.io.ahb_htrans + // io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite + io.lsu_ahb <> lsu_axi4_to_ahb.io.ahb + // io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr + // io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst + // io.lsu_hmastlock := lsu_axi4_to_ahb.io.ahb_hmastlock + // io.lsu_hprot := lsu_axi4_to_ahb.io.ahb_hprot + // io.lsu_hsize := lsu_axi4_to_ahb.io.ahb_hsize + // io.lsu_htrans := lsu_axi4_to_ahb.io.ahb_htrans + // io.lsu_hwrite := lsu_axi4_to_ahb.io.ahb_hwrite + // io.lsu_hwdata := lsu_axi4_to_ahb.io.ahb_hwdata - io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr - io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst - io.lsu_hmastlock := lsu_axi4_to_ahb.io.ahb_hmastlock - io.lsu_hprot := lsu_axi4_to_ahb.io.ahb_hprot - io.lsu_hsize := lsu_axi4_to_ahb.io.ahb_hsize - io.lsu_htrans := lsu_axi4_to_ahb.io.ahb_htrans - io.lsu_hwrite := lsu_axi4_to_ahb.io.ahb_hwrite - io.lsu_hwdata := lsu_axi4_to_ahb.io.ahb_hwdata + io.sb_ahb <> sb_axi4_to_ahb.io.ahb + // io.sb_haddr := sb_axi4_to_ahb.io.ahb_haddr + // io.sb_hburst := sb_axi4_to_ahb.io.ahb_hburst + // io.sb_hmastlock := sb_axi4_to_ahb.io.ahb_hmastlock + // io.sb_hprot := sb_axi4_to_ahb.io.ahb_hprot + // io.sb_hsize := sb_axi4_to_ahb.io.ahb_hsize + // io.sb_htrans := sb_axi4_to_ahb.io.ahb_htrans + // io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite + // io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata - io.sb_haddr := sb_axi4_to_ahb.io.ahb_haddr - io.sb_hburst := sb_axi4_to_ahb.io.ahb_hburst - io.sb_hmastlock := sb_axi4_to_ahb.io.ahb_hmastlock - io.sb_hprot := sb_axi4_to_ahb.io.ahb_hprot - io.sb_hsize := sb_axi4_to_ahb.io.ahb_hsize - io.sb_htrans := sb_axi4_to_ahb.io.ahb_htrans - io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite - io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata - - io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata - io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout - io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp + io.dma_ahb <> dma_ahb_to_axi4.io.ahb + // io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata + // io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout + // io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp + // io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata + // io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata } - .otherwise{ - // AHB Signals - io.haddr := 0.U - io.hburst := 0.U - io.hmastlock := 0.U - io.hprot := 0.U - io.hsize := 0.U - io.htrans := 0.U - io.hwrite := 0.U + .otherwise{ + // AHB Signals + io.ahb.out <> 0.U.asTypeOf(io.ahb.out) + // io.haddr := 0.U + // io.hburst := 0.U + // io.hmastlock := 0.U + // io.hprot := 0.U + // io.hsize := 0.U + // io.htrans := 0.U + // io.hwrite := 0.U + io.lsu_ahb.out <> 0.U.asTypeOf(io.lsu_ahb.out) + // io.lsu_haddr := 0.U + // io.lsu_hburst := 0.U + // io.lsu_hmastlock := 0.U + // io.lsu_hprot := 0.U + // io.lsu_hsize := 0.U + // io.lsu_htrans := 0.U + // io.lsu_hwrite := 0.U + // io.lsu_hwdata := 0.U - io.lsu_haddr := 0.U - io.lsu_hburst := 0.U - io.lsu_hmastlock := 0.U - io.lsu_hprot := 0.U - io.lsu_hsize := 0.U - io.lsu_htrans := 0.U - io.lsu_hwrite := 0.U - io.lsu_hwdata := 0.U - - io.sb_haddr := 0.U - io.sb_hburst := 0.U - io.sb_hmastlock := 0.U - io.sb_hprot := 0.U - io.sb_hsize := 0.U - io.sb_htrans := 0.U - io.sb_hwrite := 0.U - io.sb_hwdata := 0.U - - io.dma_hrdata := 0.U - io.dma_hreadyout := 0.U - io.dma_hresp := 0.U - } + io.sb_ahb.out <> 0.U.asTypeOf(io.sb_ahb.out) + // io.sb_haddr := 0.U + // io.sb_hburst := 0.U + // io.sb_hmastlock := 0.U + // io.sb_hprot := 0.U + // io.sb_hsize := 0.U + // io.sb_htrans := 0.U + // io.sb_hwrite := 0.U + // io.sb_hwdata := 0.U + io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) + // io.dma_hrdata := 0.U + // io.dma_hreadyout := 0.U + // io.dma_hresp := 0.U + } io.dmi_reg_rdata := 0.U } - diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala index a694850d..4510af97 100644 --- a/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -20,18 +20,19 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { // DMA slave val dma_hsel = Input(Bool()) - val dma_haddr = Input(UInt(32.W)) - val dma_hburst = Input(UInt(3.W)) - val dma_hmastlock = Input(Bool()) - val dma_hprot = Input(UInt(4.W)) - val dma_hsize = Input(UInt(3.W)) - val dma_htrans = Input(UInt(2.W)) - val dma_hwrite = Input(Bool()) - val dma_hwdata = Input(UInt(64.W)) + val dma_ahb = Flipped(new ahb_channel()) + // val dma_haddr = Input(UInt(32.W)) + // val dma_hburst = Input(UInt(3.W)) + // val dma_hmastlock = Input(Bool()) + // val dma_hprot = Input(UInt(4.W)) + // val dma_hsize = Input(UInt(3.W)) + // val dma_htrans = Input(UInt(2.W)) + // val dma_hwrite = Input(Bool()) + // val dma_hwdata = Input(UInt(64.W)) val dma_hreadyin = Input(Bool()) - val dma_hrdata = Output(UInt(64.W)) - val dma_hreadyout = Output(Bool()) - val dma_hresp = Output(Bool()) + // val dma_hrdata = Output(UInt(64.W)) + // val dma_hreadyout = Output(Bool()) + // val dma_hresp = Output(Bool()) val lsu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool()) @@ -74,127 +75,149 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { val rv_trace_pkt = new trace_pkt_t() val scan_mode = Input(Bool()) -}) + }) val mem = Module(new quasar.mem()) val dmi_wrapper = Module(new dmi_wrapper()) - val core = Module(new quasar()) + val swerv = Module(new quasar()) dmi_wrapper.io.trst_n := io.jtag_trst_n dmi_wrapper.io.tck := io.jtag_tck dmi_wrapper.io.tms := io.jtag_tms dmi_wrapper.io.tdi := io.jtag_tdi dmi_wrapper.io.core_clk := clock dmi_wrapper.io.jtag_id := io.jtag_id - dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata + dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata dmi_wrapper.io.core_rst_n := io.dbg_rst_l - core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data - core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr - core.io.dmi_reg_en := dmi_wrapper.io.reg_en - core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en - core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset + swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data + swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr + swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en + swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en + swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset io.jtag_tdo := dmi_wrapper.io.tdo // Memory signals - mem.io.dccm_clk_override := core.io.dccm_clk_override - mem.io.icm_clk_override := core.io.icm_clk_override - mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable - mem.io.dccm <> core.io.dccm + mem.io.dccm_clk_override := swerv.io.dccm_clk_override + mem.io.icm_clk_override := swerv.io.icm_clk_override + mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable + mem.io.dccm <> swerv.io.dccm mem.io.rst_l := reset mem.io.clk := clock mem.io.scan_mode := io.scan_mode // Memory outputs - core.io.dbg_rst_l := io.dbg_rst_l - core.io.ic <> mem.io.ic - core.io.iccm <> mem.io.iccm - core.io.sb_hready := 0.U - core.io.hrdata := 0.U - core.io.sb_hresp := 0.U - core.io.lsu_hrdata := 0.U - core.io.lsu_hresp := 0.U - core.io.lsu_hready := 0.U - core.io.hready := 0.U - core.io.hresp := 0.U - core.io.sb_hrdata := 0.U - core.io.scan_mode := io.scan_mode + swerv.io.dbg_rst_l := io.dbg_rst_l + swerv.io.ic <> mem.io.ic + swerv.io.iccm <> mem.io.iccm + + swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in) + swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in) + swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in) + io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) + // swerv.io.sb_hready := 0.U + // swerv.io.hrdata := 0.U + // swerv.io.sb_hresp := 0.U + // swerv.io.lsu_hrdata := 0.U + // swerv.io.lsu_hresp := 0.U + // swerv.io.lsu_hready := 0.U + // swerv.io.hready := 0.U + // swerv.io.hresp := 0.U + // swerv.io.sb_hrdata := 0.U + swerv.io.scan_mode := io.scan_mode // SweRV Inputs - core.io.dbg_rst_l := io.dbg_rst_l - core.io.rst_vec := io.rst_vec - core.io.nmi_int := io.nmi_int - core.io.nmi_vec := io.nmi_vec + swerv.io.dbg_rst_l := io.dbg_rst_l + swerv.io.rst_vec := io.rst_vec + swerv.io.nmi_int := io.nmi_int + swerv.io.nmi_vec := io.nmi_vec // external halt/run interface - core.io.i_cpu_halt_req := io.i_cpu_halt_req - core.io.i_cpu_run_req := io.i_cpu_run_req - core.io.core_id := io.core_id + swerv.io.i_cpu_halt_req := io.i_cpu_halt_req + swerv.io.i_cpu_run_req := io.i_cpu_run_req + swerv.io.core_id := io.core_id // external MPC halt/run interface - core.io.mpc_debug_halt_req := io.mpc_debug_halt_req - core.io.mpc_debug_run_req := io.mpc_debug_run_req - core.io.mpc_reset_run_req := io.mpc_reset_run_req + swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req + swerv.io.mpc_debug_run_req := io.mpc_debug_run_req + swerv.io.mpc_reset_run_req := io.mpc_reset_run_req //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels - core.io.lsu_axi <> io.lsu_axi + swerv.io.lsu_axi <> io.lsu_axi //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels - core.io.ifu_axi <> io.ifu_axi + swerv.io.ifu_axi <> io.ifu_axi //-------------------------- SB AXI signals-------------------------- // AXI Write Channels - core.io.sb_axi <> io.sb_axi + swerv.io.sb_axi <> io.sb_axi //-------------------------- DMA AXI signals-------------------------- // AXI Write Channels - core.io.dma_axi <> io.dma_axi + swerv.io.dma_axi <> io.dma_axi // DMA Slave - core.io.dma_hsel := io.dma_hsel - core.io.dma_haddr := io.dma_haddr - core.io.dma_hburst := io.dma_hburst - core.io.dma_hmastlock := io.dma_hmastlock - core.io.dma_hprot := io.dma_hprot - core.io.dma_hsize := io.dma_hsize - core.io.dma_htrans := io.dma_htrans - core.io.dma_hwrite := io.dma_hwrite - core.io.dma_hwdata := io.dma_hwdata - core.io.dma_hreadyin := io.dma_hreadyin + swerv.io.dma_hsel := io.dma_hsel + swerv.io.dma_ahb.out <> io.dma_ahb.out + // swerv.io.dma_haddr := io.dma_haddr + // swerv.io.dma_hburst := io.dma_hburst + // swerv.io.dma_hmastlock := io.dma_hmastlock + // swerv.io.dma_hprot := io.dma_hprot + // swerv.io.dma_hsize := io.dma_hsize + // swerv.io.dma_htrans := io.dma_htrans + // swerv.io.dma_hwrite := io.dma_hwrite + // swerv.io.dma_hwdata := io.dma_hwdata + swerv.io.dma_hreadyin := io.dma_hreadyin - core.io.lsu_bus_clk_en := io.lsu_bus_clk_en - core.io.ifu_bus_clk_en := io.ifu_bus_clk_en - core.io.dbg_bus_clk_en := io.dbg_bus_clk_en - core.io.dma_bus_clk_en := io.dma_bus_clk_en + swerv.io.lsu_bus_clk_en + swerv.io.ifu_bus_clk_en + swerv.io.dbg_bus_clk_en + swerv.io.dma_bus_clk_en - core.io.timer_int := io.timer_int - core.io.soft_int := io.soft_int - core.io.extintsrc_req := io.extintsrc_req + swerv.io.dmi_reg_en + swerv.io.dmi_reg_addr + swerv.io.dmi_reg_wr_en + swerv.io.dmi_reg_wdata + swerv.io.dmi_hard_reset + + swerv.io.extintsrc_req + swerv.io.timer_int + swerv.io.soft_int + swerv.io.scan_mode + + swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en + swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en + swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en + swerv.io.dma_bus_clk_en := io.dma_bus_clk_en + + swerv.io.timer_int := io.timer_int + swerv.io.soft_int := io.soft_int + swerv.io.extintsrc_req := io.extintsrc_req // Outputs - val core_rst_l = core.io.core_rst_l - io.rv_trace_pkt := core.io.rv_trace_pkt + val core_rst_l = swerv.io.core_rst_l + io.rv_trace_pkt := swerv.io.rv_trace_pkt // external halt/run interface - io.o_cpu_halt_ack := core.io.o_cpu_halt_ack - io.o_cpu_halt_status := core.io.o_cpu_halt_status - io.o_cpu_run_ack := core.io.o_cpu_run_ack - io.o_debug_mode_status := core.io.o_debug_mode_status + io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack + io.o_cpu_halt_status := swerv.io.o_cpu_halt_status + io.o_cpu_run_ack := swerv.io.o_cpu_run_ack + io.o_debug_mode_status := swerv.io.o_debug_mode_status - io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack - io.mpc_debug_run_ack := core.io.mpc_debug_run_ack - io.debug_brkpt_status := core.io.debug_brkpt_status + io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack + io.debug_brkpt_status := swerv.io.debug_brkpt_status - io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0 - io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1 - io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2 - io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3 + io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels // DMA Slave - io.dma_hrdata := core.io.dma_hrdata - io.dma_hreadyout := core.io.dma_hreadyout - io.dma_hresp := core.io.dma_hresp + // io.dma_hrdata := swerv.io.dma_hrdata + // io.dma_hreadyout := swerv.io.dma_hreadyout + // io.dma_hresp := swerv.io.dma_hresp } object QUASAR_Wrp extends App { diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 269d4e31..a5fbfae2 100644 Binary files a/target/scala-2.12/classes/QUASAR_Wrp$.class and b/target/scala-2.12/classes/QUASAR_Wrp$.class differ diff --git a/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class b/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class index 684eeb3f..bf1fb1c5 100644 Binary files a/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class and b/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dbg/dbg$.class b/target/scala-2.12/classes/dbg/dbg$.class new file mode 100644 index 00000000..2f69190b Binary files /dev/null and b/target/scala-2.12/classes/dbg/dbg$.class differ diff --git a/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class b/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class new file mode 100644 index 00000000..6d36f6fc Binary files /dev/null and b/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index 3bc2083c..a3be25ad 100644 Binary files a/target/scala-2.12/classes/dbg/dbg.class and b/target/scala-2.12/classes/dbg/dbg.class differ diff --git a/target/scala-2.12/classes/include/ahb_channel.class b/target/scala-2.12/classes/include/ahb_channel.class new file mode 100644 index 00000000..1a78dfd0 Binary files /dev/null and b/target/scala-2.12/classes/include/ahb_channel.class differ diff --git a/target/scala-2.12/classes/include/ahb_in.class b/target/scala-2.12/classes/include/ahb_in.class new file mode 100644 index 00000000..0611f832 Binary files /dev/null and b/target/scala-2.12/classes/include/ahb_in.class differ diff --git a/target/scala-2.12/classes/include/ahb_out.class b/target/scala-2.12/classes/include/ahb_out.class new file mode 100644 index 00000000..f11f2b42 Binary files /dev/null and b/target/scala-2.12/classes/include/ahb_out.class differ diff --git a/target/scala-2.12/classes/include/aln_dec.class b/target/scala-2.12/classes/include/aln_dec.class index 44daf0fb..a320387a 100644 Binary files a/target/scala-2.12/classes/include/aln_dec.class and b/target/scala-2.12/classes/include/aln_dec.class differ diff --git a/target/scala-2.12/classes/include/aln_ib.class b/target/scala-2.12/classes/include/aln_ib.class index 3cfebe9a..9d3a8a2a 100644 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a/target/scala-2.12/classes/include/br_pkt_t.class b/target/scala-2.12/classes/include/br_pkt_t.class index 3974d3cc..366c583d 100644 Binary files a/target/scala-2.12/classes/include/br_pkt_t.class and b/target/scala-2.12/classes/include/br_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/br_tlu_pkt_t.class b/target/scala-2.12/classes/include/br_tlu_pkt_t.class index b3b06e2c..6101bed8 100644 Binary files a/target/scala-2.12/classes/include/br_tlu_pkt_t.class and b/target/scala-2.12/classes/include/br_tlu_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/cache_debug_pkt_t.class b/target/scala-2.12/classes/include/cache_debug_pkt_t.class index 319d0495..9cab16ff 100644 Binary files a/target/scala-2.12/classes/include/cache_debug_pkt_t.class and b/target/scala-2.12/classes/include/cache_debug_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class index 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a/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class index 189893c6..17f7a7bb 100644 Binary files a/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/dctl_busbuff.class b/target/scala-2.12/classes/include/dctl_busbuff.class index fa090c82..00c7a661 100644 Binary files a/target/scala-2.12/classes/include/dctl_busbuff.class and b/target/scala-2.12/classes/include/dctl_busbuff.class differ diff --git a/target/scala-2.12/classes/include/dec_aln.class b/target/scala-2.12/classes/include/dec_aln.class index 94306f91..a40f81cc 100644 Binary files a/target/scala-2.12/classes/include/dec_aln.class and b/target/scala-2.12/classes/include/dec_aln.class differ diff --git a/target/scala-2.12/classes/include/dec_alu.class b/target/scala-2.12/classes/include/dec_alu.class index 7c418a02..e05732bc 100644 Binary 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