From 59aecdc9831cc2efbee57571f3d4731cb8a369f0 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 10 Dec 2020 16:59:28 +0500 Subject: [PATCH] Bridges added --- dbg.fir | 2 +- dbg.v | 6 +- firrtl_black_box_resource_files.f | 4 +- quasar_wrapper.fir | 11033 ++++++++-------- quasar_wrapper.v | 6098 ++++----- src/main/scala/dbg/dbg.scala | 3 + src/main/scala/include/bundle.scala | 43 +- src/main/scala/lib/ahb_to_axi4.scala | 68 +- src/main/scala/lib/axi4_to_ahb.scala | 65 +- src/main/scala/quasar.scala | 268 +- src/main/scala/quasar_wrapper.scala | 189 +- target/scala-2.12/classes/QUASAR_Wrp$.class | Bin 3859 -> 3859 bytes .../classes/QUASAR_Wrp$delayedInit$body.class | Bin 729 -> 729 bytes target/scala-2.12/classes/dbg/dbg$.class | Bin 0 -> 3820 bytes .../classes/dbg/dbg$delayedInit$body.class | Bin 0 -> 700 bytes target/scala-2.12/classes/dbg/dbg.class | Bin 274944 -> 275434 bytes .../classes/include/ahb_channel.class | Bin 0 -> 1537 bytes .../scala-2.12/classes/include/ahb_in.class | Bin 0 -> 2081 bytes .../scala-2.12/classes/include/ahb_out.class | Bin 0 -> 2944 bytes .../scala-2.12/classes/include/aln_dec.class | Bin 2031 -> 2031 bytes .../scala-2.12/classes/include/aln_ib.class | Bin 46703 -> 46703 bytes .../classes/include/alu_pkt_t.class | Bin 4169 -> 4169 bytes .../classes/include/axi_channels$.class | Bin 501 -> 501 bytes .../classes/include/axi_channels.class | Bin 45935 -> 45935 bytes .../scala-2.12/classes/include/br_pkt_t.class | Bin 2549 -> 2549 bytes .../classes/include/br_tlu_pkt_t.class | Bin 2108 -> 2108 bytes .../classes/include/cache_debug_pkt_t.class | Bin 2066 -> 2066 bytes .../classes/include/ccm_ext_in_pkt_t.class | Bin 2649 -> 2649 bytes .../classes/include/class_pkt_t.class | Bin 1751 -> 1751 bytes .../scala-2.12/classes/include/dbg_dctl.class | Bin 1631 -> 1632 bytes .../scala-2.12/classes/include/dbg_ib.class | Bin 2340 -> 2340 bytes .../classes/include/dccm_ext_in_pkt_t.class | Bin 2652 -> 2652 bytes .../classes/include/dctl_busbuff.class | Bin 45943 -> 45943 bytes .../scala-2.12/classes/include/dec_aln.class | Bin 44359 -> 44359 bytes .../scala-2.12/classes/include/dec_alu.class | Bin 2443 -> 2443 bytes .../scala-2.12/classes/include/dec_dbg.class | Bin 1349 -> 1349 bytes .../scala-2.12/classes/include/dec_div.class | Bin 2240 -> 2240 bytes .../scala-2.12/classes/include/dec_exu.class | Bin 44843 -> 44843 bytes .../classes/include/dec_mem_ctrl.class | Bin 47560 -> 47560 bytes .../classes/include/dec_pkt_t.class | Bin 8199 -> 8199 bytes .../classes/include/dec_tlu_csr_pkt.class | Bin 13320 -> 13320 bytes .../classes/include/decode_exu.class | Bin 48961 -> 48961 bytes .../classes/include/dest_pkt_t.class | Bin 2551 -> 2551 bytes .../classes/include/div_pkt_t.class | Bin 1605 -> 1605 bytes .../classes/include/dma_dccm_ctl.class | Bin 2834 -> 2834 bytes .../scala-2.12/classes/include/dma_ifc.class | Bin 1369 -> 1369 bytes .../classes/include/dma_lsc_ctl.class | Bin 2541 -> 2541 bytes .../classes/include/dma_mem_ctl.class | Bin 2728 -> 2728 bytes .../scala-2.12/classes/include/exu_bp.class | Bin 45900 -> 45900 bytes .../scala-2.12/classes/include/exu_ifu.class | Bin 1243 -> 1243 bytes .../scala-2.12/classes/include/gpr_exu.class | Bin 1814 -> 1814 bytes .../scala-2.12/classes/include/ib_exu.class | Bin 1836 -> 1836 bytes .../include/ic_data_ext_in_pkt_t.class | Bin 2662 -> 2662 bytes .../scala-2.12/classes/include/ic_mem.class | Bin 48228 -> 48228 bytes .../classes/include/ic_tag_ext_in_pkt_t.class | Bin 2659 -> 2659 bytes .../scala-2.12/classes/include/iccm_mem.class | Bin 45726 -> 45726 bytes .../scala-2.12/classes/include/ifu_dec.class | Bin 1860 -> 1860 bytes .../scala-2.12/classes/include/ifu_dma.class | Bin 1378 -> 1378 bytes .../classes/include/inst_pkt_t$.class | Bin 3015 -> 3015 bytes .../classes/include/load_cam_pkt_t.class | Bin 1750 -> 1750 bytes .../scala-2.12/classes/include/lsu_dec.class | Bin 1415 -> 1415 bytes .../scala-2.12/classes/include/lsu_dma.class | Bin 2565 -> 2565 bytes .../classes/include/lsu_error_pkt_t.class | Bin 2148 -> 2148 bytes .../scala-2.12/classes/include/lsu_exu.class | Bin 1821 -> 1821 bytes .../scala-2.12/classes/include/lsu_pic.class | Bin 2921 -> 2921 bytes .../classes/include/lsu_pkt_t.class | Bin 2874 -> 2874 bytes .../scala-2.12/classes/include/lsu_tlu.class | Bin 1608 -> 1608 bytes .../classes/include/mul_pkt_t.class | Bin 4102 -> 4102 bytes .../classes/include/predict_pkt_t.class | Bin 3328 -> 3328 bytes .../classes/include/read_addr$.class | Bin 495 -> 495 bytes .../classes/include/read_addr.class | Bin 45927 -> 45927 bytes .../classes/include/read_data$.class | Bin 495 -> 495 bytes .../classes/include/read_data.class | Bin 45023 -> 45023 bytes .../classes/include/reg_pkt_t.class | Bin 1738 -> 1738 bytes .../classes/include/rets_pkt_t.class | Bin 1787 -> 1787 bytes .../classes/include/tlu_busbuff.class | Bin 3899 -> 3899 bytes .../scala-2.12/classes/include/tlu_exu.class | Bin 46917 -> 46917 bytes .../classes/include/trace_pkt_t.class | Bin 2835 -> 2835 bytes .../classes/include/trap_pkt_t.class | Bin 2987 -> 2987 bytes .../classes/include/trigger_pkt_t.class | Bin 2395 -> 2395 bytes .../classes/include/write_addr$.class | Bin 497 -> 497 bytes .../classes/include/write_addr.class | Bin 45933 -> 45933 bytes .../classes/include/write_data.class | Bin 44362 -> 44362 bytes .../classes/include/write_resp$.class | Bin 497 -> 497 bytes .../classes/include/write_resp.class | Bin 44620 -> 44620 bytes target/scala-2.12/classes/lib/AHB_main$.class | Bin 0 -> 3903 bytes .../lib/AHB_main$delayedInit$body.class | Bin 0 -> 738 bytes target/scala-2.12/classes/lib/AHB_main.class | Bin 0 -> 781 bytes target/scala-2.12/classes/lib/AXImain$.class | Bin 0 -> 3898 bytes .../lib/AXImain$delayedInit$body.class | Bin 0 -> 732 bytes target/scala-2.12/classes/lib/AXImain.class | Bin 0 -> 776 bytes target/scala-2.12/classes/lib/Config.class | Bin 684 -> 684 bytes .../classes/lib/ahb_to_axi4$$anon$1.class | Bin 7665 -> 6473 bytes .../scala-2.12/classes/lib/ahb_to_axi4.class | Bin 113427 -> 113509 bytes .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 106852 -> 107135 bytes .../classes/lib/axi4_to_ahb_IO.class | Bin 9408 -> 7655 bytes target/scala-2.12/classes/quasar.class | Bin 202229 -> 191621 bytes target/scala-2.12/classes/quasar_bundle.class | Bin 61901 -> 54810 bytes .../classes/quasar_wrapper$$anon$1.class | Bin 9177 -> 7920 bytes .../scala-2.12/classes/quasar_wrapper.class | Bin 93877 -> 87526 bytes 100 files changed, 8947 insertions(+), 8832 deletions(-) create mode 100644 target/scala-2.12/classes/dbg/dbg$.class create mode 100644 target/scala-2.12/classes/dbg/dbg$delayedInit$body.class create mode 100644 target/scala-2.12/classes/include/ahb_channel.class create mode 100644 target/scala-2.12/classes/include/ahb_in.class create mode 100644 target/scala-2.12/classes/include/ahb_out.class create mode 100644 target/scala-2.12/classes/lib/AHB_main$.class create mode 100644 target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lib/AHB_main.class create mode 100644 target/scala-2.12/classes/lib/AXImain$.class create mode 100644 target/scala-2.12/classes/lib/AXImain$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lib/AXImain.class diff --git a/dbg.fir b/dbg.fir index 2eb3e425..d3ba81c9 100644 --- a/dbg.fir +++ b/dbg.fir @@ -147,7 +147,7 @@ circuit dbg : module dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") diff --git a/dbg.v b/dbg.v index 1ff57a64..3d32b5ff 100644 --- a/dbg.v +++ b/dbg.v @@ -81,12 +81,12 @@ module dbg( output io_dbg_dec_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_dbg_ib_dbg_cmd_valid, output io_dbg_dma_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_io_dbg_dma_bubble, input io_dbg_dma_io_dma_dbg_ready, input io_dbg_bus_clk_en, @@ -678,7 +678,7 @@ module dbg( assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] - assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg[1:0]; // @[dbg.scala 325:38] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index d4456bc6..40eae7ce 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/waleedbinehsan/Desktop/Quasar/gated_latch.v \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar/gated_latch.v +/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv +/home/waleedbinehsan/Desktop/Quasar/mem.sv \ No newline at end of file diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index f9da6512..f0cab509 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -66826,7 +66826,7 @@ circuit quasar_wrapper : module dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38] _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] @@ -80307,889 +80307,893 @@ circuit quasar_wrapper : node _T_403 = cat(_T_402, _T_399) @[lib.scala 89:14] node _T_404 = cat(_T_403, _T_396) @[lib.scala 89:14] node _T_405 = cat(_T_404, _T_389) @[lib.scala 89:14] - node _T_406 = and(_T_148, _T_405) @[dec_trigger.scala 15:109] - node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_409 : UInt<1>[32] @[lib.scala 84:24] - node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] - node _T_411 = not(_T_410) @[lib.scala 85:39] - node _T_412 = and(_T_408, _T_411) @[lib.scala 85:37] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] - node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 86:60] - node _T_415 = eq(_T_413, _T_414) @[lib.scala 86:52] - node _T_416 = or(_T_412, _T_415) @[lib.scala 86:41] - _T_409[0] <= _T_416 @[lib.scala 86:18] - node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] - node _T_418 = andr(_T_417) @[lib.scala 88:36] - node _T_419 = and(_T_418, _T_412) @[lib.scala 88:41] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] - node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 88:86] - node _T_422 = eq(_T_420, _T_421) @[lib.scala 88:78] - node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[lib.scala 88:23] - _T_409[1] <= _T_423 @[lib.scala 88:17] - node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] - node _T_425 = andr(_T_424) @[lib.scala 88:36] - node _T_426 = and(_T_425, _T_412) @[lib.scala 88:41] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] - node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 88:86] - node _T_429 = eq(_T_427, _T_428) @[lib.scala 88:78] - node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[lib.scala 88:23] - _T_409[2] <= _T_430 @[lib.scala 88:17] - node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] - node _T_432 = andr(_T_431) @[lib.scala 88:36] - node _T_433 = and(_T_432, _T_412) @[lib.scala 88:41] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] - node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 88:86] - node _T_436 = eq(_T_434, _T_435) @[lib.scala 88:78] - node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[lib.scala 88:23] - _T_409[3] <= _T_437 @[lib.scala 88:17] - node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] - node _T_439 = andr(_T_438) @[lib.scala 88:36] - node _T_440 = and(_T_439, _T_412) @[lib.scala 88:41] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] - node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 88:86] - node _T_443 = eq(_T_441, _T_442) @[lib.scala 88:78] - node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[lib.scala 88:23] - _T_409[4] <= _T_444 @[lib.scala 88:17] - node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] - node _T_446 = andr(_T_445) @[lib.scala 88:36] - node _T_447 = and(_T_446, _T_412) @[lib.scala 88:41] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] - node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 88:86] - node _T_450 = eq(_T_448, _T_449) @[lib.scala 88:78] - node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[lib.scala 88:23] - _T_409[5] <= _T_451 @[lib.scala 88:17] - node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] - node _T_453 = andr(_T_452) @[lib.scala 88:36] - node _T_454 = and(_T_453, _T_412) @[lib.scala 88:41] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] - node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 88:86] - node _T_457 = eq(_T_455, _T_456) @[lib.scala 88:78] - node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[lib.scala 88:23] - _T_409[6] <= _T_458 @[lib.scala 88:17] - node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] - node _T_460 = andr(_T_459) @[lib.scala 88:36] - node _T_461 = and(_T_460, _T_412) @[lib.scala 88:41] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] - node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 88:86] - node _T_464 = eq(_T_462, _T_463) @[lib.scala 88:78] - node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[lib.scala 88:23] - _T_409[7] <= _T_465 @[lib.scala 88:17] - node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] - node _T_467 = andr(_T_466) @[lib.scala 88:36] - node _T_468 = and(_T_467, _T_412) @[lib.scala 88:41] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] - node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 88:86] - node _T_471 = eq(_T_469, _T_470) @[lib.scala 88:78] - node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[lib.scala 88:23] - _T_409[8] <= _T_472 @[lib.scala 88:17] - node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] - node _T_474 = andr(_T_473) @[lib.scala 88:36] - node _T_475 = and(_T_474, _T_412) @[lib.scala 88:41] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] - node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 88:86] - node _T_478 = eq(_T_476, _T_477) @[lib.scala 88:78] - node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[lib.scala 88:23] - _T_409[9] <= _T_479 @[lib.scala 88:17] - node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] - node _T_481 = andr(_T_480) @[lib.scala 88:36] - node _T_482 = and(_T_481, _T_412) @[lib.scala 88:41] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] - node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 88:86] - node _T_485 = eq(_T_483, _T_484) @[lib.scala 88:78] - node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[lib.scala 88:23] - _T_409[10] <= _T_486 @[lib.scala 88:17] - node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] - node _T_488 = andr(_T_487) @[lib.scala 88:36] - node _T_489 = and(_T_488, _T_412) @[lib.scala 88:41] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] - node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 88:86] - node _T_492 = eq(_T_490, _T_491) @[lib.scala 88:78] - node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[lib.scala 88:23] - _T_409[11] <= _T_493 @[lib.scala 88:17] - node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] - node _T_495 = andr(_T_494) @[lib.scala 88:36] - node _T_496 = and(_T_495, _T_412) @[lib.scala 88:41] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] - node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 88:86] - node _T_499 = eq(_T_497, _T_498) @[lib.scala 88:78] - node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[lib.scala 88:23] - _T_409[12] <= _T_500 @[lib.scala 88:17] - node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] - node _T_502 = andr(_T_501) @[lib.scala 88:36] - node _T_503 = and(_T_502, _T_412) @[lib.scala 88:41] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] - node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 88:86] - node _T_506 = eq(_T_504, _T_505) @[lib.scala 88:78] - node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[lib.scala 88:23] - _T_409[13] <= _T_507 @[lib.scala 88:17] - node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] - node _T_509 = andr(_T_508) @[lib.scala 88:36] - node _T_510 = and(_T_509, _T_412) @[lib.scala 88:41] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] - node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 88:86] - node _T_513 = eq(_T_511, _T_512) @[lib.scala 88:78] - node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[lib.scala 88:23] - _T_409[14] <= _T_514 @[lib.scala 88:17] - node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] - node _T_516 = andr(_T_515) @[lib.scala 88:36] - node _T_517 = and(_T_516, _T_412) @[lib.scala 88:41] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] - node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 88:86] - node _T_520 = eq(_T_518, _T_519) @[lib.scala 88:78] - node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[lib.scala 88:23] - _T_409[15] <= _T_521 @[lib.scala 88:17] - node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] - node _T_523 = andr(_T_522) @[lib.scala 88:36] - node _T_524 = and(_T_523, _T_412) @[lib.scala 88:41] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] - node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 88:86] - node _T_527 = eq(_T_525, _T_526) @[lib.scala 88:78] - node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[lib.scala 88:23] - _T_409[16] <= _T_528 @[lib.scala 88:17] - node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] - node _T_530 = andr(_T_529) @[lib.scala 88:36] - node _T_531 = and(_T_530, _T_412) @[lib.scala 88:41] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] - node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 88:86] - node _T_534 = eq(_T_532, _T_533) @[lib.scala 88:78] - node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[lib.scala 88:23] - _T_409[17] <= _T_535 @[lib.scala 88:17] - node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] - node _T_537 = andr(_T_536) @[lib.scala 88:36] - node _T_538 = and(_T_537, _T_412) @[lib.scala 88:41] - node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] - node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 88:86] - node _T_541 = eq(_T_539, _T_540) @[lib.scala 88:78] - node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[lib.scala 88:23] - _T_409[18] <= _T_542 @[lib.scala 88:17] - node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] - node _T_544 = andr(_T_543) @[lib.scala 88:36] - node _T_545 = and(_T_544, _T_412) @[lib.scala 88:41] - node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] - node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 88:86] - node _T_548 = eq(_T_546, _T_547) @[lib.scala 88:78] - node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[lib.scala 88:23] - _T_409[19] <= _T_549 @[lib.scala 88:17] - node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] - node _T_551 = andr(_T_550) @[lib.scala 88:36] - node _T_552 = and(_T_551, _T_412) @[lib.scala 88:41] - node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] - node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 88:86] - node _T_555 = eq(_T_553, _T_554) @[lib.scala 88:78] - node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[lib.scala 88:23] - _T_409[20] <= _T_556 @[lib.scala 88:17] - node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] - node _T_558 = andr(_T_557) @[lib.scala 88:36] - node _T_559 = and(_T_558, _T_412) @[lib.scala 88:41] - node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] - node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 88:86] - node _T_562 = eq(_T_560, _T_561) @[lib.scala 88:78] - node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[lib.scala 88:23] - _T_409[21] <= _T_563 @[lib.scala 88:17] - node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] - node _T_565 = andr(_T_564) @[lib.scala 88:36] - node _T_566 = and(_T_565, _T_412) @[lib.scala 88:41] - node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] - node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 88:86] - node _T_569 = eq(_T_567, _T_568) @[lib.scala 88:78] - node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[lib.scala 88:23] - _T_409[22] <= _T_570 @[lib.scala 88:17] - node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] - node _T_572 = andr(_T_571) @[lib.scala 88:36] - node _T_573 = and(_T_572, _T_412) @[lib.scala 88:41] - node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] - node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 88:86] - node _T_576 = eq(_T_574, _T_575) @[lib.scala 88:78] - node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[lib.scala 88:23] - _T_409[23] <= _T_577 @[lib.scala 88:17] - node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] - node _T_579 = andr(_T_578) @[lib.scala 88:36] - node _T_580 = and(_T_579, _T_412) @[lib.scala 88:41] - node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] - node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 88:86] - node _T_583 = eq(_T_581, _T_582) @[lib.scala 88:78] - node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[lib.scala 88:23] - _T_409[24] <= _T_584 @[lib.scala 88:17] - node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] - node _T_586 = andr(_T_585) @[lib.scala 88:36] - node _T_587 = and(_T_586, _T_412) @[lib.scala 88:41] - node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] - node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 88:86] - node _T_590 = eq(_T_588, _T_589) @[lib.scala 88:78] - node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[lib.scala 88:23] - _T_409[25] <= _T_591 @[lib.scala 88:17] - node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] - node _T_593 = andr(_T_592) @[lib.scala 88:36] - node _T_594 = and(_T_593, _T_412) @[lib.scala 88:41] - node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] - node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 88:86] - node _T_597 = eq(_T_595, _T_596) @[lib.scala 88:78] - node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[lib.scala 88:23] - _T_409[26] <= _T_598 @[lib.scala 88:17] - node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] - node _T_600 = andr(_T_599) @[lib.scala 88:36] - node _T_601 = and(_T_600, _T_412) @[lib.scala 88:41] - node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] - node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 88:86] - node _T_604 = eq(_T_602, _T_603) @[lib.scala 88:78] - node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[lib.scala 88:23] - _T_409[27] <= _T_605 @[lib.scala 88:17] - node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] - node _T_607 = andr(_T_606) @[lib.scala 88:36] - node _T_608 = and(_T_607, _T_412) @[lib.scala 88:41] - node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] - node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 88:86] - node _T_611 = eq(_T_609, _T_610) @[lib.scala 88:78] - node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[lib.scala 88:23] - _T_409[28] <= _T_612 @[lib.scala 88:17] - node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] - node _T_614 = andr(_T_613) @[lib.scala 88:36] - node _T_615 = and(_T_614, _T_412) @[lib.scala 88:41] - node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] - node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 88:86] - node _T_618 = eq(_T_616, _T_617) @[lib.scala 88:78] - node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[lib.scala 88:23] - _T_409[29] <= _T_619 @[lib.scala 88:17] - node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] - node _T_621 = andr(_T_620) @[lib.scala 88:36] - node _T_622 = and(_T_621, _T_412) @[lib.scala 88:41] - node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] - node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 88:86] - node _T_625 = eq(_T_623, _T_624) @[lib.scala 88:78] - node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[lib.scala 88:23] - _T_409[30] <= _T_626 @[lib.scala 88:17] - node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] - node _T_628 = andr(_T_627) @[lib.scala 88:36] - node _T_629 = and(_T_628, _T_412) @[lib.scala 88:41] - node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] - node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 88:86] - node _T_632 = eq(_T_630, _T_631) @[lib.scala 88:78] - node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[lib.scala 88:23] - _T_409[31] <= _T_633 @[lib.scala 88:17] - node _T_634 = cat(_T_409[1], _T_409[0]) @[lib.scala 89:14] - node _T_635 = cat(_T_409[3], _T_409[2]) @[lib.scala 89:14] - node _T_636 = cat(_T_635, _T_634) @[lib.scala 89:14] - node _T_637 = cat(_T_409[5], _T_409[4]) @[lib.scala 89:14] - node _T_638 = cat(_T_409[7], _T_409[6]) @[lib.scala 89:14] - node _T_639 = cat(_T_638, _T_637) @[lib.scala 89:14] - node _T_640 = cat(_T_639, _T_636) @[lib.scala 89:14] - node _T_641 = cat(_T_409[9], _T_409[8]) @[lib.scala 89:14] - node _T_642 = cat(_T_409[11], _T_409[10]) @[lib.scala 89:14] - node _T_643 = cat(_T_642, _T_641) @[lib.scala 89:14] - node _T_644 = cat(_T_409[13], _T_409[12]) @[lib.scala 89:14] - node _T_645 = cat(_T_409[15], _T_409[14]) @[lib.scala 89:14] - node _T_646 = cat(_T_645, _T_644) @[lib.scala 89:14] - node _T_647 = cat(_T_646, _T_643) @[lib.scala 89:14] - node _T_648 = cat(_T_647, _T_640) @[lib.scala 89:14] - node _T_649 = cat(_T_409[17], _T_409[16]) @[lib.scala 89:14] - node _T_650 = cat(_T_409[19], _T_409[18]) @[lib.scala 89:14] - node _T_651 = cat(_T_650, _T_649) @[lib.scala 89:14] - node _T_652 = cat(_T_409[21], _T_409[20]) @[lib.scala 89:14] - node _T_653 = cat(_T_409[23], _T_409[22]) @[lib.scala 89:14] - node _T_654 = cat(_T_653, _T_652) @[lib.scala 89:14] - node _T_655 = cat(_T_654, _T_651) @[lib.scala 89:14] - node _T_656 = cat(_T_409[25], _T_409[24]) @[lib.scala 89:14] - node _T_657 = cat(_T_409[27], _T_409[26]) @[lib.scala 89:14] - node _T_658 = cat(_T_657, _T_656) @[lib.scala 89:14] - node _T_659 = cat(_T_409[29], _T_409[28]) @[lib.scala 89:14] - node _T_660 = cat(_T_409[31], _T_409[30]) @[lib.scala 89:14] - node _T_661 = cat(_T_660, _T_659) @[lib.scala 89:14] - node _T_662 = cat(_T_661, _T_658) @[lib.scala 89:14] - node _T_663 = cat(_T_662, _T_655) @[lib.scala 89:14] - node _T_664 = cat(_T_663, _T_648) @[lib.scala 89:14] - node _T_665 = and(_T_407, _T_664) @[dec_trigger.scala 15:109] - node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_668 : UInt<1>[32] @[lib.scala 84:24] - node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] - node _T_670 = not(_T_669) @[lib.scala 85:39] - node _T_671 = and(_T_667, _T_670) @[lib.scala 85:37] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] - node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 86:60] - node _T_674 = eq(_T_672, _T_673) @[lib.scala 86:52] - node _T_675 = or(_T_671, _T_674) @[lib.scala 86:41] - _T_668[0] <= _T_675 @[lib.scala 86:18] - node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] - node _T_677 = andr(_T_676) @[lib.scala 88:36] - node _T_678 = and(_T_677, _T_671) @[lib.scala 88:41] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] - node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 88:86] - node _T_681 = eq(_T_679, _T_680) @[lib.scala 88:78] - node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[lib.scala 88:23] - _T_668[1] <= _T_682 @[lib.scala 88:17] - node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] - node _T_684 = andr(_T_683) @[lib.scala 88:36] - node _T_685 = and(_T_684, _T_671) @[lib.scala 88:41] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] - node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 88:86] - node _T_688 = eq(_T_686, _T_687) @[lib.scala 88:78] - node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[lib.scala 88:23] - _T_668[2] <= _T_689 @[lib.scala 88:17] - node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] - node _T_691 = andr(_T_690) @[lib.scala 88:36] - node _T_692 = and(_T_691, _T_671) @[lib.scala 88:41] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] - node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 88:86] - node _T_695 = eq(_T_693, _T_694) @[lib.scala 88:78] - node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[lib.scala 88:23] - _T_668[3] <= _T_696 @[lib.scala 88:17] - node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] - node _T_698 = andr(_T_697) @[lib.scala 88:36] - node _T_699 = and(_T_698, _T_671) @[lib.scala 88:41] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] - node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 88:86] - node _T_702 = eq(_T_700, _T_701) @[lib.scala 88:78] - node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[lib.scala 88:23] - _T_668[4] <= _T_703 @[lib.scala 88:17] - node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] - node _T_705 = andr(_T_704) @[lib.scala 88:36] - node _T_706 = and(_T_705, _T_671) @[lib.scala 88:41] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] - node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 88:86] - node _T_709 = eq(_T_707, _T_708) @[lib.scala 88:78] - node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[lib.scala 88:23] - _T_668[5] <= _T_710 @[lib.scala 88:17] - node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] - node _T_712 = andr(_T_711) @[lib.scala 88:36] - node _T_713 = and(_T_712, _T_671) @[lib.scala 88:41] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] - node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 88:86] - node _T_716 = eq(_T_714, _T_715) @[lib.scala 88:78] - node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[lib.scala 88:23] - _T_668[6] <= _T_717 @[lib.scala 88:17] - node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] - node _T_719 = andr(_T_718) @[lib.scala 88:36] - node _T_720 = and(_T_719, _T_671) @[lib.scala 88:41] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] - node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 88:86] - node _T_723 = eq(_T_721, _T_722) @[lib.scala 88:78] - node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[lib.scala 88:23] - _T_668[7] <= _T_724 @[lib.scala 88:17] - node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] - node _T_726 = andr(_T_725) @[lib.scala 88:36] - node _T_727 = and(_T_726, _T_671) @[lib.scala 88:41] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] - node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 88:86] - node _T_730 = eq(_T_728, _T_729) @[lib.scala 88:78] - node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[lib.scala 88:23] - _T_668[8] <= _T_731 @[lib.scala 88:17] - node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] - node _T_733 = andr(_T_732) @[lib.scala 88:36] - node _T_734 = and(_T_733, _T_671) @[lib.scala 88:41] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] - node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 88:86] - node _T_737 = eq(_T_735, _T_736) @[lib.scala 88:78] - node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[lib.scala 88:23] - _T_668[9] <= _T_738 @[lib.scala 88:17] - node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] - node _T_740 = andr(_T_739) @[lib.scala 88:36] - node _T_741 = and(_T_740, _T_671) @[lib.scala 88:41] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] - node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 88:86] - node _T_744 = eq(_T_742, _T_743) @[lib.scala 88:78] - node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[lib.scala 88:23] - _T_668[10] <= _T_745 @[lib.scala 88:17] - node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] - node _T_747 = andr(_T_746) @[lib.scala 88:36] - node _T_748 = and(_T_747, _T_671) @[lib.scala 88:41] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] - node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 88:86] - node _T_751 = eq(_T_749, _T_750) @[lib.scala 88:78] - node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[lib.scala 88:23] - _T_668[11] <= _T_752 @[lib.scala 88:17] - node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] - node _T_754 = andr(_T_753) @[lib.scala 88:36] - node _T_755 = and(_T_754, _T_671) @[lib.scala 88:41] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] - node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 88:86] - node _T_758 = eq(_T_756, _T_757) @[lib.scala 88:78] - node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[lib.scala 88:23] - _T_668[12] <= _T_759 @[lib.scala 88:17] - node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] - node _T_761 = andr(_T_760) @[lib.scala 88:36] - node _T_762 = and(_T_761, _T_671) @[lib.scala 88:41] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] - node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 88:86] - node _T_765 = eq(_T_763, _T_764) @[lib.scala 88:78] - node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[lib.scala 88:23] - _T_668[13] <= _T_766 @[lib.scala 88:17] - node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] - node _T_768 = andr(_T_767) @[lib.scala 88:36] - node _T_769 = and(_T_768, _T_671) @[lib.scala 88:41] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] - node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 88:86] - node _T_772 = eq(_T_770, _T_771) @[lib.scala 88:78] - node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[lib.scala 88:23] - _T_668[14] <= _T_773 @[lib.scala 88:17] - node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] - node _T_775 = andr(_T_774) @[lib.scala 88:36] - node _T_776 = and(_T_775, _T_671) @[lib.scala 88:41] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] - node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 88:86] - node _T_779 = eq(_T_777, _T_778) @[lib.scala 88:78] - node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[lib.scala 88:23] - _T_668[15] <= _T_780 @[lib.scala 88:17] - node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] - node _T_782 = andr(_T_781) @[lib.scala 88:36] - node _T_783 = and(_T_782, _T_671) @[lib.scala 88:41] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] - node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 88:86] - node _T_786 = eq(_T_784, _T_785) @[lib.scala 88:78] - node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[lib.scala 88:23] - _T_668[16] <= _T_787 @[lib.scala 88:17] - node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] - node _T_789 = andr(_T_788) @[lib.scala 88:36] - node _T_790 = and(_T_789, _T_671) @[lib.scala 88:41] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] - node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 88:86] - node _T_793 = eq(_T_791, _T_792) @[lib.scala 88:78] - node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[lib.scala 88:23] - _T_668[17] <= _T_794 @[lib.scala 88:17] - node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] - node _T_796 = andr(_T_795) @[lib.scala 88:36] - node _T_797 = and(_T_796, _T_671) @[lib.scala 88:41] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] - node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 88:86] - node _T_800 = eq(_T_798, _T_799) @[lib.scala 88:78] - node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[lib.scala 88:23] - _T_668[18] <= _T_801 @[lib.scala 88:17] - node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] - node _T_803 = andr(_T_802) @[lib.scala 88:36] - node _T_804 = and(_T_803, _T_671) @[lib.scala 88:41] - node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] - node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 88:86] - node _T_807 = eq(_T_805, _T_806) @[lib.scala 88:78] - node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[lib.scala 88:23] - _T_668[19] <= _T_808 @[lib.scala 88:17] - node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] - node _T_810 = andr(_T_809) @[lib.scala 88:36] - node _T_811 = and(_T_810, _T_671) @[lib.scala 88:41] - node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] - node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 88:86] - node _T_814 = eq(_T_812, _T_813) @[lib.scala 88:78] - node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[lib.scala 88:23] - _T_668[20] <= _T_815 @[lib.scala 88:17] - node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] - node _T_817 = andr(_T_816) @[lib.scala 88:36] - node _T_818 = and(_T_817, _T_671) @[lib.scala 88:41] - node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] - node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 88:86] - node _T_821 = eq(_T_819, _T_820) @[lib.scala 88:78] - node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[lib.scala 88:23] - _T_668[21] <= _T_822 @[lib.scala 88:17] - node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] - node _T_824 = andr(_T_823) @[lib.scala 88:36] - node _T_825 = and(_T_824, _T_671) @[lib.scala 88:41] - node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] - node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 88:86] - node _T_828 = eq(_T_826, _T_827) @[lib.scala 88:78] - node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[lib.scala 88:23] - _T_668[22] <= _T_829 @[lib.scala 88:17] - node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] - node _T_831 = andr(_T_830) @[lib.scala 88:36] - node _T_832 = and(_T_831, _T_671) @[lib.scala 88:41] - node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] - node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 88:86] - node _T_835 = eq(_T_833, _T_834) @[lib.scala 88:78] - node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[lib.scala 88:23] - _T_668[23] <= _T_836 @[lib.scala 88:17] - node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] - node _T_838 = andr(_T_837) @[lib.scala 88:36] - node _T_839 = and(_T_838, _T_671) @[lib.scala 88:41] - node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] - node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 88:86] - node _T_842 = eq(_T_840, _T_841) @[lib.scala 88:78] - node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[lib.scala 88:23] - _T_668[24] <= _T_843 @[lib.scala 88:17] - node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] - node _T_845 = andr(_T_844) @[lib.scala 88:36] - node _T_846 = and(_T_845, _T_671) @[lib.scala 88:41] - node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] - node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 88:86] - node _T_849 = eq(_T_847, _T_848) @[lib.scala 88:78] - node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[lib.scala 88:23] - _T_668[25] <= _T_850 @[lib.scala 88:17] - node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] - node _T_852 = andr(_T_851) @[lib.scala 88:36] - node _T_853 = and(_T_852, _T_671) @[lib.scala 88:41] - node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] - node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 88:86] - node _T_856 = eq(_T_854, _T_855) @[lib.scala 88:78] - node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[lib.scala 88:23] - _T_668[26] <= _T_857 @[lib.scala 88:17] - node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] - node _T_859 = andr(_T_858) @[lib.scala 88:36] - node _T_860 = and(_T_859, _T_671) @[lib.scala 88:41] - node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] - node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 88:86] - node _T_863 = eq(_T_861, _T_862) @[lib.scala 88:78] - node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[lib.scala 88:23] - _T_668[27] <= _T_864 @[lib.scala 88:17] - node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] - node _T_866 = andr(_T_865) @[lib.scala 88:36] - node _T_867 = and(_T_866, _T_671) @[lib.scala 88:41] - node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] - node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 88:86] - node _T_870 = eq(_T_868, _T_869) @[lib.scala 88:78] - node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[lib.scala 88:23] - _T_668[28] <= _T_871 @[lib.scala 88:17] - node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] - node _T_873 = andr(_T_872) @[lib.scala 88:36] - node _T_874 = and(_T_873, _T_671) @[lib.scala 88:41] - node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] - node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 88:86] - node _T_877 = eq(_T_875, _T_876) @[lib.scala 88:78] - node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[lib.scala 88:23] - _T_668[29] <= _T_878 @[lib.scala 88:17] - node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] - node _T_880 = andr(_T_879) @[lib.scala 88:36] - node _T_881 = and(_T_880, _T_671) @[lib.scala 88:41] - node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] - node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 88:86] - node _T_884 = eq(_T_882, _T_883) @[lib.scala 88:78] - node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[lib.scala 88:23] - _T_668[30] <= _T_885 @[lib.scala 88:17] - node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] - node _T_887 = andr(_T_886) @[lib.scala 88:36] - node _T_888 = and(_T_887, _T_671) @[lib.scala 88:41] - node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] - node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 88:86] - node _T_891 = eq(_T_889, _T_890) @[lib.scala 88:78] - node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[lib.scala 88:23] - _T_668[31] <= _T_892 @[lib.scala 88:17] - node _T_893 = cat(_T_668[1], _T_668[0]) @[lib.scala 89:14] - node _T_894 = cat(_T_668[3], _T_668[2]) @[lib.scala 89:14] - node _T_895 = cat(_T_894, _T_893) @[lib.scala 89:14] - node _T_896 = cat(_T_668[5], _T_668[4]) @[lib.scala 89:14] - node _T_897 = cat(_T_668[7], _T_668[6]) @[lib.scala 89:14] - node _T_898 = cat(_T_897, _T_896) @[lib.scala 89:14] - node _T_899 = cat(_T_898, _T_895) @[lib.scala 89:14] - node _T_900 = cat(_T_668[9], _T_668[8]) @[lib.scala 89:14] - node _T_901 = cat(_T_668[11], _T_668[10]) @[lib.scala 89:14] - node _T_902 = cat(_T_901, _T_900) @[lib.scala 89:14] - node _T_903 = cat(_T_668[13], _T_668[12]) @[lib.scala 89:14] - node _T_904 = cat(_T_668[15], _T_668[14]) @[lib.scala 89:14] - node _T_905 = cat(_T_904, _T_903) @[lib.scala 89:14] - node _T_906 = cat(_T_905, _T_902) @[lib.scala 89:14] - node _T_907 = cat(_T_906, _T_899) @[lib.scala 89:14] - node _T_908 = cat(_T_668[17], _T_668[16]) @[lib.scala 89:14] - node _T_909 = cat(_T_668[19], _T_668[18]) @[lib.scala 89:14] - node _T_910 = cat(_T_909, _T_908) @[lib.scala 89:14] - node _T_911 = cat(_T_668[21], _T_668[20]) @[lib.scala 89:14] - node _T_912 = cat(_T_668[23], _T_668[22]) @[lib.scala 89:14] - node _T_913 = cat(_T_912, _T_911) @[lib.scala 89:14] - node _T_914 = cat(_T_913, _T_910) @[lib.scala 89:14] - node _T_915 = cat(_T_668[25], _T_668[24]) @[lib.scala 89:14] - node _T_916 = cat(_T_668[27], _T_668[26]) @[lib.scala 89:14] - node _T_917 = cat(_T_916, _T_915) @[lib.scala 89:14] - node _T_918 = cat(_T_668[29], _T_668[28]) @[lib.scala 89:14] - node _T_919 = cat(_T_668[31], _T_668[30]) @[lib.scala 89:14] - node _T_920 = cat(_T_919, _T_918) @[lib.scala 89:14] - node _T_921 = cat(_T_920, _T_917) @[lib.scala 89:14] - node _T_922 = cat(_T_921, _T_914) @[lib.scala 89:14] - node _T_923 = cat(_T_922, _T_907) @[lib.scala 89:14] - node _T_924 = and(_T_666, _T_923) @[dec_trigger.scala 15:109] - node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_927 : UInt<1>[32] @[lib.scala 84:24] - node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] - node _T_929 = not(_T_928) @[lib.scala 85:39] - node _T_930 = and(_T_926, _T_929) @[lib.scala 85:37] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] - node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 86:60] - node _T_933 = eq(_T_931, _T_932) @[lib.scala 86:52] - node _T_934 = or(_T_930, _T_933) @[lib.scala 86:41] - _T_927[0] <= _T_934 @[lib.scala 86:18] - node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] - node _T_936 = andr(_T_935) @[lib.scala 88:36] - node _T_937 = and(_T_936, _T_930) @[lib.scala 88:41] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] - node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 88:86] - node _T_940 = eq(_T_938, _T_939) @[lib.scala 88:78] - node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[lib.scala 88:23] - _T_927[1] <= _T_941 @[lib.scala 88:17] - node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] - node _T_943 = andr(_T_942) @[lib.scala 88:36] - node _T_944 = and(_T_943, _T_930) @[lib.scala 88:41] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] - node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 88:86] - node _T_947 = eq(_T_945, _T_946) @[lib.scala 88:78] - node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[lib.scala 88:23] - _T_927[2] <= _T_948 @[lib.scala 88:17] - node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] - node _T_950 = andr(_T_949) @[lib.scala 88:36] - node _T_951 = and(_T_950, _T_930) @[lib.scala 88:41] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] - node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 88:86] - node _T_954 = eq(_T_952, _T_953) @[lib.scala 88:78] - node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[lib.scala 88:23] - _T_927[3] <= _T_955 @[lib.scala 88:17] - node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] - node _T_957 = andr(_T_956) @[lib.scala 88:36] - node _T_958 = and(_T_957, _T_930) @[lib.scala 88:41] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] - node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 88:86] - node _T_961 = eq(_T_959, _T_960) @[lib.scala 88:78] - node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[lib.scala 88:23] - _T_927[4] <= _T_962 @[lib.scala 88:17] - node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] - node _T_964 = andr(_T_963) @[lib.scala 88:36] - node _T_965 = and(_T_964, _T_930) @[lib.scala 88:41] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] - node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 88:86] - node _T_968 = eq(_T_966, _T_967) @[lib.scala 88:78] - node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[lib.scala 88:23] - _T_927[5] <= _T_969 @[lib.scala 88:17] - node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] - node _T_971 = andr(_T_970) @[lib.scala 88:36] - node _T_972 = and(_T_971, _T_930) @[lib.scala 88:41] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] - node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 88:86] - node _T_975 = eq(_T_973, _T_974) @[lib.scala 88:78] - node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[lib.scala 88:23] - _T_927[6] <= _T_976 @[lib.scala 88:17] - node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] - node _T_978 = andr(_T_977) @[lib.scala 88:36] - node _T_979 = and(_T_978, _T_930) @[lib.scala 88:41] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] - node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 88:86] - node _T_982 = eq(_T_980, _T_981) @[lib.scala 88:78] - node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[lib.scala 88:23] - _T_927[7] <= _T_983 @[lib.scala 88:17] - node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] - node _T_985 = andr(_T_984) @[lib.scala 88:36] - node _T_986 = and(_T_985, _T_930) @[lib.scala 88:41] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] - node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 88:86] - node _T_989 = eq(_T_987, _T_988) @[lib.scala 88:78] - node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[lib.scala 88:23] - _T_927[8] <= _T_990 @[lib.scala 88:17] - node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] - node _T_992 = andr(_T_991) @[lib.scala 88:36] - node _T_993 = and(_T_992, _T_930) @[lib.scala 88:41] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] - node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 88:86] - node _T_996 = eq(_T_994, _T_995) @[lib.scala 88:78] - node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[lib.scala 88:23] - _T_927[9] <= _T_997 @[lib.scala 88:17] - node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] - node _T_999 = andr(_T_998) @[lib.scala 88:36] - node _T_1000 = and(_T_999, _T_930) @[lib.scala 88:41] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] - node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 88:86] - node _T_1003 = eq(_T_1001, _T_1002) @[lib.scala 88:78] - node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[lib.scala 88:23] - _T_927[10] <= _T_1004 @[lib.scala 88:17] - node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] - node _T_1006 = andr(_T_1005) @[lib.scala 88:36] - node _T_1007 = and(_T_1006, _T_930) @[lib.scala 88:41] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] - node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 88:86] - node _T_1010 = eq(_T_1008, _T_1009) @[lib.scala 88:78] - node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[lib.scala 88:23] - _T_927[11] <= _T_1011 @[lib.scala 88:17] - node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] - node _T_1013 = andr(_T_1012) @[lib.scala 88:36] - node _T_1014 = and(_T_1013, _T_930) @[lib.scala 88:41] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] - node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 88:86] - node _T_1017 = eq(_T_1015, _T_1016) @[lib.scala 88:78] - node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[lib.scala 88:23] - _T_927[12] <= _T_1018 @[lib.scala 88:17] - node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] - node _T_1020 = andr(_T_1019) @[lib.scala 88:36] - node _T_1021 = and(_T_1020, _T_930) @[lib.scala 88:41] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] - node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 88:86] - node _T_1024 = eq(_T_1022, _T_1023) @[lib.scala 88:78] - node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[lib.scala 88:23] - _T_927[13] <= _T_1025 @[lib.scala 88:17] - node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] - node _T_1027 = andr(_T_1026) @[lib.scala 88:36] - node _T_1028 = and(_T_1027, _T_930) @[lib.scala 88:41] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] - node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 88:86] - node _T_1031 = eq(_T_1029, _T_1030) @[lib.scala 88:78] - node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[lib.scala 88:23] - _T_927[14] <= _T_1032 @[lib.scala 88:17] - node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] - node _T_1034 = andr(_T_1033) @[lib.scala 88:36] - node _T_1035 = and(_T_1034, _T_930) @[lib.scala 88:41] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] - node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 88:86] - node _T_1038 = eq(_T_1036, _T_1037) @[lib.scala 88:78] - node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[lib.scala 88:23] - _T_927[15] <= _T_1039 @[lib.scala 88:17] - node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] - node _T_1041 = andr(_T_1040) @[lib.scala 88:36] - node _T_1042 = and(_T_1041, _T_930) @[lib.scala 88:41] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] - node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 88:86] - node _T_1045 = eq(_T_1043, _T_1044) @[lib.scala 88:78] - node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[lib.scala 88:23] - _T_927[16] <= _T_1046 @[lib.scala 88:17] - node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] - node _T_1048 = andr(_T_1047) @[lib.scala 88:36] - node _T_1049 = and(_T_1048, _T_930) @[lib.scala 88:41] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] - node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 88:86] - node _T_1052 = eq(_T_1050, _T_1051) @[lib.scala 88:78] - node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[lib.scala 88:23] - _T_927[17] <= _T_1053 @[lib.scala 88:17] - node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] - node _T_1055 = andr(_T_1054) @[lib.scala 88:36] - node _T_1056 = and(_T_1055, _T_930) @[lib.scala 88:41] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] - node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 88:86] - node _T_1059 = eq(_T_1057, _T_1058) @[lib.scala 88:78] - node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[lib.scala 88:23] - _T_927[18] <= _T_1060 @[lib.scala 88:17] - node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] - node _T_1062 = andr(_T_1061) @[lib.scala 88:36] - node _T_1063 = and(_T_1062, _T_930) @[lib.scala 88:41] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] - node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 88:86] - node _T_1066 = eq(_T_1064, _T_1065) @[lib.scala 88:78] - node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[lib.scala 88:23] - _T_927[19] <= _T_1067 @[lib.scala 88:17] - node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] - node _T_1069 = andr(_T_1068) @[lib.scala 88:36] - node _T_1070 = and(_T_1069, _T_930) @[lib.scala 88:41] - node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] - node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 88:86] - node _T_1073 = eq(_T_1071, _T_1072) @[lib.scala 88:78] - node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[lib.scala 88:23] - _T_927[20] <= _T_1074 @[lib.scala 88:17] - node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] - node _T_1076 = andr(_T_1075) @[lib.scala 88:36] - node _T_1077 = and(_T_1076, _T_930) @[lib.scala 88:41] - node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] - node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 88:86] - node _T_1080 = eq(_T_1078, _T_1079) @[lib.scala 88:78] - node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[lib.scala 88:23] - _T_927[21] <= _T_1081 @[lib.scala 88:17] - node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] - node _T_1083 = andr(_T_1082) @[lib.scala 88:36] - node _T_1084 = and(_T_1083, _T_930) @[lib.scala 88:41] - node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] - node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 88:86] - node _T_1087 = eq(_T_1085, _T_1086) @[lib.scala 88:78] - node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[lib.scala 88:23] - _T_927[22] <= _T_1088 @[lib.scala 88:17] - node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] - node _T_1090 = andr(_T_1089) @[lib.scala 88:36] - node _T_1091 = and(_T_1090, _T_930) @[lib.scala 88:41] - node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] - node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 88:86] - node _T_1094 = eq(_T_1092, _T_1093) @[lib.scala 88:78] - node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[lib.scala 88:23] - _T_927[23] <= _T_1095 @[lib.scala 88:17] - node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] - node _T_1097 = andr(_T_1096) @[lib.scala 88:36] - node _T_1098 = and(_T_1097, _T_930) @[lib.scala 88:41] - node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] - node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 88:86] - node _T_1101 = eq(_T_1099, _T_1100) @[lib.scala 88:78] - node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[lib.scala 88:23] - _T_927[24] <= _T_1102 @[lib.scala 88:17] - node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] - node _T_1104 = andr(_T_1103) @[lib.scala 88:36] - node _T_1105 = and(_T_1104, _T_930) @[lib.scala 88:41] - node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] - node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 88:86] - node _T_1108 = eq(_T_1106, _T_1107) @[lib.scala 88:78] - node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[lib.scala 88:23] - _T_927[25] <= _T_1109 @[lib.scala 88:17] - node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] - node _T_1111 = andr(_T_1110) @[lib.scala 88:36] - node _T_1112 = and(_T_1111, _T_930) @[lib.scala 88:41] - node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] - node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 88:86] - node _T_1115 = eq(_T_1113, _T_1114) @[lib.scala 88:78] - node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[lib.scala 88:23] - _T_927[26] <= _T_1116 @[lib.scala 88:17] - node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] - node _T_1118 = andr(_T_1117) @[lib.scala 88:36] - node _T_1119 = and(_T_1118, _T_930) @[lib.scala 88:41] - node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] - node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 88:86] - node _T_1122 = eq(_T_1120, _T_1121) @[lib.scala 88:78] - node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[lib.scala 88:23] - _T_927[27] <= _T_1123 @[lib.scala 88:17] - node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] - node _T_1125 = andr(_T_1124) @[lib.scala 88:36] - node _T_1126 = and(_T_1125, _T_930) @[lib.scala 88:41] - node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] - node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 88:86] - node _T_1129 = eq(_T_1127, _T_1128) @[lib.scala 88:78] - node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[lib.scala 88:23] - _T_927[28] <= _T_1130 @[lib.scala 88:17] - node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] - node _T_1132 = andr(_T_1131) @[lib.scala 88:36] - node _T_1133 = and(_T_1132, _T_930) @[lib.scala 88:41] - node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] - node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 88:86] - node _T_1136 = eq(_T_1134, _T_1135) @[lib.scala 88:78] - node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[lib.scala 88:23] - _T_927[29] <= _T_1137 @[lib.scala 88:17] - node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] - node _T_1139 = andr(_T_1138) @[lib.scala 88:36] - node _T_1140 = and(_T_1139, _T_930) @[lib.scala 88:41] - node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] - node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 88:86] - node _T_1143 = eq(_T_1141, _T_1142) @[lib.scala 88:78] - node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[lib.scala 88:23] - _T_927[30] <= _T_1144 @[lib.scala 88:17] - node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] - node _T_1146 = andr(_T_1145) @[lib.scala 88:36] - node _T_1147 = and(_T_1146, _T_930) @[lib.scala 88:41] - node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] - node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 88:86] - node _T_1150 = eq(_T_1148, _T_1149) @[lib.scala 88:78] - node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[lib.scala 88:23] - _T_927[31] <= _T_1151 @[lib.scala 88:17] - node _T_1152 = cat(_T_927[1], _T_927[0]) @[lib.scala 89:14] - node _T_1153 = cat(_T_927[3], _T_927[2]) @[lib.scala 89:14] - node _T_1154 = cat(_T_1153, _T_1152) @[lib.scala 89:14] - node _T_1155 = cat(_T_927[5], _T_927[4]) @[lib.scala 89:14] - node _T_1156 = cat(_T_927[7], _T_927[6]) @[lib.scala 89:14] + node _T_406 = andr(_T_405) @[lib.scala 89:25] + node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109] + node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] + node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_410 : UInt<1>[32] @[lib.scala 84:24] + node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] + node _T_412 = not(_T_411) @[lib.scala 85:39] + node _T_413 = and(_T_409, _T_412) @[lib.scala 85:37] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] + node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 86:60] + node _T_416 = eq(_T_414, _T_415) @[lib.scala 86:52] + node _T_417 = or(_T_413, _T_416) @[lib.scala 86:41] + _T_410[0] <= _T_417 @[lib.scala 86:18] + node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] + node _T_419 = andr(_T_418) @[lib.scala 88:36] + node _T_420 = and(_T_419, _T_413) @[lib.scala 88:41] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] + node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 88:86] + node _T_423 = eq(_T_421, _T_422) @[lib.scala 88:78] + node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 88:23] + _T_410[1] <= _T_424 @[lib.scala 88:17] + node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] + node _T_426 = andr(_T_425) @[lib.scala 88:36] + node _T_427 = and(_T_426, _T_413) @[lib.scala 88:41] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] + node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 88:86] + node _T_430 = eq(_T_428, _T_429) @[lib.scala 88:78] + node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 88:23] + _T_410[2] <= _T_431 @[lib.scala 88:17] + node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] + node _T_433 = andr(_T_432) @[lib.scala 88:36] + node _T_434 = and(_T_433, _T_413) @[lib.scala 88:41] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] + node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 88:86] + node _T_437 = eq(_T_435, _T_436) @[lib.scala 88:78] + node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 88:23] + _T_410[3] <= _T_438 @[lib.scala 88:17] + node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] + node _T_440 = andr(_T_439) @[lib.scala 88:36] + node _T_441 = and(_T_440, _T_413) @[lib.scala 88:41] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] + node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 88:86] + node _T_444 = eq(_T_442, _T_443) @[lib.scala 88:78] + node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 88:23] + _T_410[4] <= _T_445 @[lib.scala 88:17] + node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] + node _T_447 = andr(_T_446) @[lib.scala 88:36] + node _T_448 = and(_T_447, _T_413) @[lib.scala 88:41] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] + node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 88:86] + node _T_451 = eq(_T_449, _T_450) @[lib.scala 88:78] + node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 88:23] + _T_410[5] <= _T_452 @[lib.scala 88:17] + node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] + node _T_454 = andr(_T_453) @[lib.scala 88:36] + node _T_455 = and(_T_454, _T_413) @[lib.scala 88:41] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] + node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 88:86] + node _T_458 = eq(_T_456, _T_457) @[lib.scala 88:78] + node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 88:23] + _T_410[6] <= _T_459 @[lib.scala 88:17] + node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] + node _T_461 = andr(_T_460) @[lib.scala 88:36] + node _T_462 = and(_T_461, _T_413) @[lib.scala 88:41] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] + node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 88:86] + node _T_465 = eq(_T_463, _T_464) @[lib.scala 88:78] + node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 88:23] + _T_410[7] <= _T_466 @[lib.scala 88:17] + node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] + node _T_468 = andr(_T_467) @[lib.scala 88:36] + node _T_469 = and(_T_468, _T_413) @[lib.scala 88:41] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] + node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 88:86] + node _T_472 = eq(_T_470, _T_471) @[lib.scala 88:78] + node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 88:23] + _T_410[8] <= _T_473 @[lib.scala 88:17] + node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] + node _T_475 = andr(_T_474) @[lib.scala 88:36] + node _T_476 = and(_T_475, _T_413) @[lib.scala 88:41] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] + node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 88:86] + node _T_479 = eq(_T_477, _T_478) @[lib.scala 88:78] + node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 88:23] + _T_410[9] <= _T_480 @[lib.scala 88:17] + node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] + node _T_482 = andr(_T_481) @[lib.scala 88:36] + node _T_483 = and(_T_482, _T_413) @[lib.scala 88:41] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] + node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 88:86] + node _T_486 = eq(_T_484, _T_485) @[lib.scala 88:78] + node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 88:23] + _T_410[10] <= _T_487 @[lib.scala 88:17] + node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] + node _T_489 = andr(_T_488) @[lib.scala 88:36] + node _T_490 = and(_T_489, _T_413) @[lib.scala 88:41] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] + node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 88:86] + node _T_493 = eq(_T_491, _T_492) @[lib.scala 88:78] + node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 88:23] + _T_410[11] <= _T_494 @[lib.scala 88:17] + node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] + node _T_496 = andr(_T_495) @[lib.scala 88:36] + node _T_497 = and(_T_496, _T_413) @[lib.scala 88:41] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] + node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 88:86] + node _T_500 = eq(_T_498, _T_499) @[lib.scala 88:78] + node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 88:23] + _T_410[12] <= _T_501 @[lib.scala 88:17] + node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] + node _T_503 = andr(_T_502) @[lib.scala 88:36] + node _T_504 = and(_T_503, _T_413) @[lib.scala 88:41] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] + node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 88:86] + node _T_507 = eq(_T_505, _T_506) @[lib.scala 88:78] + node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 88:23] + _T_410[13] <= _T_508 @[lib.scala 88:17] + node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] + node _T_510 = andr(_T_509) @[lib.scala 88:36] + node _T_511 = and(_T_510, _T_413) @[lib.scala 88:41] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] + node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 88:86] + node _T_514 = eq(_T_512, _T_513) @[lib.scala 88:78] + node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 88:23] + _T_410[14] <= _T_515 @[lib.scala 88:17] + node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] + node _T_517 = andr(_T_516) @[lib.scala 88:36] + node _T_518 = and(_T_517, _T_413) @[lib.scala 88:41] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] + node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 88:86] + node _T_521 = eq(_T_519, _T_520) @[lib.scala 88:78] + node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 88:23] + _T_410[15] <= _T_522 @[lib.scala 88:17] + node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] + node _T_524 = andr(_T_523) @[lib.scala 88:36] + node _T_525 = and(_T_524, _T_413) @[lib.scala 88:41] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] + node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 88:86] + node _T_528 = eq(_T_526, _T_527) @[lib.scala 88:78] + node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 88:23] + _T_410[16] <= _T_529 @[lib.scala 88:17] + node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] + node _T_531 = andr(_T_530) @[lib.scala 88:36] + node _T_532 = and(_T_531, _T_413) @[lib.scala 88:41] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] + node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 88:86] + node _T_535 = eq(_T_533, _T_534) @[lib.scala 88:78] + node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 88:23] + _T_410[17] <= _T_536 @[lib.scala 88:17] + node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] + node _T_538 = andr(_T_537) @[lib.scala 88:36] + node _T_539 = and(_T_538, _T_413) @[lib.scala 88:41] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] + node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 88:86] + node _T_542 = eq(_T_540, _T_541) @[lib.scala 88:78] + node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 88:23] + _T_410[18] <= _T_543 @[lib.scala 88:17] + node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] + node _T_545 = andr(_T_544) @[lib.scala 88:36] + node _T_546 = and(_T_545, _T_413) @[lib.scala 88:41] + node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] + node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 88:86] + node _T_549 = eq(_T_547, _T_548) @[lib.scala 88:78] + node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 88:23] + _T_410[19] <= _T_550 @[lib.scala 88:17] + node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] + node _T_552 = andr(_T_551) @[lib.scala 88:36] + node _T_553 = and(_T_552, _T_413) @[lib.scala 88:41] + node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] + node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 88:86] + node _T_556 = eq(_T_554, _T_555) @[lib.scala 88:78] + node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 88:23] + _T_410[20] <= _T_557 @[lib.scala 88:17] + node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] + node _T_559 = andr(_T_558) @[lib.scala 88:36] + node _T_560 = and(_T_559, _T_413) @[lib.scala 88:41] + node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] + node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 88:86] + node _T_563 = eq(_T_561, _T_562) @[lib.scala 88:78] + node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 88:23] + _T_410[21] <= _T_564 @[lib.scala 88:17] + node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] + node _T_566 = andr(_T_565) @[lib.scala 88:36] + node _T_567 = and(_T_566, _T_413) @[lib.scala 88:41] + node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] + node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 88:86] + node _T_570 = eq(_T_568, _T_569) @[lib.scala 88:78] + node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 88:23] + _T_410[22] <= _T_571 @[lib.scala 88:17] + node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] + node _T_573 = andr(_T_572) @[lib.scala 88:36] + node _T_574 = and(_T_573, _T_413) @[lib.scala 88:41] + node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] + node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 88:86] + node _T_577 = eq(_T_575, _T_576) @[lib.scala 88:78] + node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 88:23] + _T_410[23] <= _T_578 @[lib.scala 88:17] + node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] + node _T_580 = andr(_T_579) @[lib.scala 88:36] + node _T_581 = and(_T_580, _T_413) @[lib.scala 88:41] + node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] + node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 88:86] + node _T_584 = eq(_T_582, _T_583) @[lib.scala 88:78] + node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 88:23] + _T_410[24] <= _T_585 @[lib.scala 88:17] + node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] + node _T_587 = andr(_T_586) @[lib.scala 88:36] + node _T_588 = and(_T_587, _T_413) @[lib.scala 88:41] + node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] + node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 88:86] + node _T_591 = eq(_T_589, _T_590) @[lib.scala 88:78] + node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 88:23] + _T_410[25] <= _T_592 @[lib.scala 88:17] + node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] + node _T_594 = andr(_T_593) @[lib.scala 88:36] + node _T_595 = and(_T_594, _T_413) @[lib.scala 88:41] + node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] + node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 88:86] + node _T_598 = eq(_T_596, _T_597) @[lib.scala 88:78] + node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 88:23] + _T_410[26] <= _T_599 @[lib.scala 88:17] + node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] + node _T_601 = andr(_T_600) @[lib.scala 88:36] + node _T_602 = and(_T_601, _T_413) @[lib.scala 88:41] + node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] + node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 88:86] + node _T_605 = eq(_T_603, _T_604) @[lib.scala 88:78] + node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 88:23] + _T_410[27] <= _T_606 @[lib.scala 88:17] + node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] + node _T_608 = andr(_T_607) @[lib.scala 88:36] + node _T_609 = and(_T_608, _T_413) @[lib.scala 88:41] + node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] + node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 88:86] + node _T_612 = eq(_T_610, _T_611) @[lib.scala 88:78] + node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 88:23] + _T_410[28] <= _T_613 @[lib.scala 88:17] + node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] + node _T_615 = andr(_T_614) @[lib.scala 88:36] + node _T_616 = and(_T_615, _T_413) @[lib.scala 88:41] + node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] + node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 88:86] + node _T_619 = eq(_T_617, _T_618) @[lib.scala 88:78] + node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 88:23] + _T_410[29] <= _T_620 @[lib.scala 88:17] + node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] + node _T_622 = andr(_T_621) @[lib.scala 88:36] + node _T_623 = and(_T_622, _T_413) @[lib.scala 88:41] + node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] + node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 88:86] + node _T_626 = eq(_T_624, _T_625) @[lib.scala 88:78] + node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 88:23] + _T_410[30] <= _T_627 @[lib.scala 88:17] + node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] + node _T_629 = andr(_T_628) @[lib.scala 88:36] + node _T_630 = and(_T_629, _T_413) @[lib.scala 88:41] + node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] + node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 88:86] + node _T_633 = eq(_T_631, _T_632) @[lib.scala 88:78] + node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 88:23] + _T_410[31] <= _T_634 @[lib.scala 88:17] + node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 89:14] + node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 89:14] + node _T_637 = cat(_T_636, _T_635) @[lib.scala 89:14] + node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 89:14] + node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 89:14] + node _T_640 = cat(_T_639, _T_638) @[lib.scala 89:14] + node _T_641 = cat(_T_640, _T_637) @[lib.scala 89:14] + node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 89:14] + node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 89:14] + node _T_644 = cat(_T_643, _T_642) @[lib.scala 89:14] + node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 89:14] + node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 89:14] + node _T_647 = cat(_T_646, _T_645) @[lib.scala 89:14] + node _T_648 = cat(_T_647, _T_644) @[lib.scala 89:14] + node _T_649 = cat(_T_648, _T_641) @[lib.scala 89:14] + node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 89:14] + node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 89:14] + node _T_652 = cat(_T_651, _T_650) @[lib.scala 89:14] + node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 89:14] + node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 89:14] + node _T_655 = cat(_T_654, _T_653) @[lib.scala 89:14] + node _T_656 = cat(_T_655, _T_652) @[lib.scala 89:14] + node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 89:14] + node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 89:14] + node _T_659 = cat(_T_658, _T_657) @[lib.scala 89:14] + node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 89:14] + node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 89:14] + node _T_662 = cat(_T_661, _T_660) @[lib.scala 89:14] + node _T_663 = cat(_T_662, _T_659) @[lib.scala 89:14] + node _T_664 = cat(_T_663, _T_656) @[lib.scala 89:14] + node _T_665 = cat(_T_664, _T_649) @[lib.scala 89:14] + node _T_666 = andr(_T_665) @[lib.scala 89:25] + node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109] + node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] + node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_670 : UInt<1>[32] @[lib.scala 84:24] + node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] + node _T_672 = not(_T_671) @[lib.scala 85:39] + node _T_673 = and(_T_669, _T_672) @[lib.scala 85:37] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] + node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 86:60] + node _T_676 = eq(_T_674, _T_675) @[lib.scala 86:52] + node _T_677 = or(_T_673, _T_676) @[lib.scala 86:41] + _T_670[0] <= _T_677 @[lib.scala 86:18] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] + node _T_679 = andr(_T_678) @[lib.scala 88:36] + node _T_680 = and(_T_679, _T_673) @[lib.scala 88:41] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] + node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 88:86] + node _T_683 = eq(_T_681, _T_682) @[lib.scala 88:78] + node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 88:23] + _T_670[1] <= _T_684 @[lib.scala 88:17] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] + node _T_686 = andr(_T_685) @[lib.scala 88:36] + node _T_687 = and(_T_686, _T_673) @[lib.scala 88:41] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] + node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 88:86] + node _T_690 = eq(_T_688, _T_689) @[lib.scala 88:78] + node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 88:23] + _T_670[2] <= _T_691 @[lib.scala 88:17] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] + node _T_693 = andr(_T_692) @[lib.scala 88:36] + node _T_694 = and(_T_693, _T_673) @[lib.scala 88:41] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] + node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 88:86] + node _T_697 = eq(_T_695, _T_696) @[lib.scala 88:78] + node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 88:23] + _T_670[3] <= _T_698 @[lib.scala 88:17] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] + node _T_700 = andr(_T_699) @[lib.scala 88:36] + node _T_701 = and(_T_700, _T_673) @[lib.scala 88:41] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] + node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 88:86] + node _T_704 = eq(_T_702, _T_703) @[lib.scala 88:78] + node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 88:23] + _T_670[4] <= _T_705 @[lib.scala 88:17] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] + node _T_707 = andr(_T_706) @[lib.scala 88:36] + node _T_708 = and(_T_707, _T_673) @[lib.scala 88:41] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] + node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 88:86] + node _T_711 = eq(_T_709, _T_710) @[lib.scala 88:78] + node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 88:23] + _T_670[5] <= _T_712 @[lib.scala 88:17] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] + node _T_714 = andr(_T_713) @[lib.scala 88:36] + node _T_715 = and(_T_714, _T_673) @[lib.scala 88:41] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] + node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 88:86] + node _T_718 = eq(_T_716, _T_717) @[lib.scala 88:78] + node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 88:23] + _T_670[6] <= _T_719 @[lib.scala 88:17] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] + node _T_721 = andr(_T_720) @[lib.scala 88:36] + node _T_722 = and(_T_721, _T_673) @[lib.scala 88:41] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] + node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 88:86] + node _T_725 = eq(_T_723, _T_724) @[lib.scala 88:78] + node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 88:23] + _T_670[7] <= _T_726 @[lib.scala 88:17] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] + node _T_728 = andr(_T_727) @[lib.scala 88:36] + node _T_729 = and(_T_728, _T_673) @[lib.scala 88:41] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] + node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 88:86] + node _T_732 = eq(_T_730, _T_731) @[lib.scala 88:78] + node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 88:23] + _T_670[8] <= _T_733 @[lib.scala 88:17] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] + node _T_735 = andr(_T_734) @[lib.scala 88:36] + node _T_736 = and(_T_735, _T_673) @[lib.scala 88:41] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] + node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 88:86] + node _T_739 = eq(_T_737, _T_738) @[lib.scala 88:78] + node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 88:23] + _T_670[9] <= _T_740 @[lib.scala 88:17] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] + node _T_742 = andr(_T_741) @[lib.scala 88:36] + node _T_743 = and(_T_742, _T_673) @[lib.scala 88:41] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] + node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 88:86] + node _T_746 = eq(_T_744, _T_745) @[lib.scala 88:78] + node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 88:23] + _T_670[10] <= _T_747 @[lib.scala 88:17] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] + node _T_749 = andr(_T_748) @[lib.scala 88:36] + node _T_750 = and(_T_749, _T_673) @[lib.scala 88:41] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] + node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 88:86] + node _T_753 = eq(_T_751, _T_752) @[lib.scala 88:78] + node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 88:23] + _T_670[11] <= _T_754 @[lib.scala 88:17] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] + node _T_756 = andr(_T_755) @[lib.scala 88:36] + node _T_757 = and(_T_756, _T_673) @[lib.scala 88:41] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] + node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 88:86] + node _T_760 = eq(_T_758, _T_759) @[lib.scala 88:78] + node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 88:23] + _T_670[12] <= _T_761 @[lib.scala 88:17] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] + node _T_763 = andr(_T_762) @[lib.scala 88:36] + node _T_764 = and(_T_763, _T_673) @[lib.scala 88:41] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] + node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 88:86] + node _T_767 = eq(_T_765, _T_766) @[lib.scala 88:78] + node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 88:23] + _T_670[13] <= _T_768 @[lib.scala 88:17] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] + node _T_770 = andr(_T_769) @[lib.scala 88:36] + node _T_771 = and(_T_770, _T_673) @[lib.scala 88:41] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] + node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 88:86] + node _T_774 = eq(_T_772, _T_773) @[lib.scala 88:78] + node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 88:23] + _T_670[14] <= _T_775 @[lib.scala 88:17] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] + node _T_777 = andr(_T_776) @[lib.scala 88:36] + node _T_778 = and(_T_777, _T_673) @[lib.scala 88:41] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] + node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 88:86] + node _T_781 = eq(_T_779, _T_780) @[lib.scala 88:78] + node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 88:23] + _T_670[15] <= _T_782 @[lib.scala 88:17] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] + node _T_784 = andr(_T_783) @[lib.scala 88:36] + node _T_785 = and(_T_784, _T_673) @[lib.scala 88:41] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] + node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 88:86] + node _T_788 = eq(_T_786, _T_787) @[lib.scala 88:78] + node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 88:23] + _T_670[16] <= _T_789 @[lib.scala 88:17] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] + node _T_791 = andr(_T_790) @[lib.scala 88:36] + node _T_792 = and(_T_791, _T_673) @[lib.scala 88:41] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] + node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 88:86] + node _T_795 = eq(_T_793, _T_794) @[lib.scala 88:78] + node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 88:23] + _T_670[17] <= _T_796 @[lib.scala 88:17] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] + node _T_798 = andr(_T_797) @[lib.scala 88:36] + node _T_799 = and(_T_798, _T_673) @[lib.scala 88:41] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] + node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 88:86] + node _T_802 = eq(_T_800, _T_801) @[lib.scala 88:78] + node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 88:23] + _T_670[18] <= _T_803 @[lib.scala 88:17] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] + node _T_805 = andr(_T_804) @[lib.scala 88:36] + node _T_806 = and(_T_805, _T_673) @[lib.scala 88:41] + node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] + node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 88:86] + node _T_809 = eq(_T_807, _T_808) @[lib.scala 88:78] + node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 88:23] + _T_670[19] <= _T_810 @[lib.scala 88:17] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] + node _T_812 = andr(_T_811) @[lib.scala 88:36] + node _T_813 = and(_T_812, _T_673) @[lib.scala 88:41] + node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] + node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 88:86] + node _T_816 = eq(_T_814, _T_815) @[lib.scala 88:78] + node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 88:23] + _T_670[20] <= _T_817 @[lib.scala 88:17] + node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] + node _T_819 = andr(_T_818) @[lib.scala 88:36] + node _T_820 = and(_T_819, _T_673) @[lib.scala 88:41] + node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] + node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 88:86] + node _T_823 = eq(_T_821, _T_822) @[lib.scala 88:78] + node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 88:23] + _T_670[21] <= _T_824 @[lib.scala 88:17] + node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] + node _T_826 = andr(_T_825) @[lib.scala 88:36] + node _T_827 = and(_T_826, _T_673) @[lib.scala 88:41] + node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] + node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 88:86] + node _T_830 = eq(_T_828, _T_829) @[lib.scala 88:78] + node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 88:23] + _T_670[22] <= _T_831 @[lib.scala 88:17] + node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] + node _T_833 = andr(_T_832) @[lib.scala 88:36] + node _T_834 = and(_T_833, _T_673) @[lib.scala 88:41] + node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] + node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 88:86] + node _T_837 = eq(_T_835, _T_836) @[lib.scala 88:78] + node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 88:23] + _T_670[23] <= _T_838 @[lib.scala 88:17] + node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] + node _T_840 = andr(_T_839) @[lib.scala 88:36] + node _T_841 = and(_T_840, _T_673) @[lib.scala 88:41] + node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] + node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 88:86] + node _T_844 = eq(_T_842, _T_843) @[lib.scala 88:78] + node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 88:23] + _T_670[24] <= _T_845 @[lib.scala 88:17] + node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] + node _T_847 = andr(_T_846) @[lib.scala 88:36] + node _T_848 = and(_T_847, _T_673) @[lib.scala 88:41] + node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] + node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 88:86] + node _T_851 = eq(_T_849, _T_850) @[lib.scala 88:78] + node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 88:23] + _T_670[25] <= _T_852 @[lib.scala 88:17] + node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] + node _T_854 = andr(_T_853) @[lib.scala 88:36] + node _T_855 = and(_T_854, _T_673) @[lib.scala 88:41] + node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] + node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 88:86] + node _T_858 = eq(_T_856, _T_857) @[lib.scala 88:78] + node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 88:23] + _T_670[26] <= _T_859 @[lib.scala 88:17] + node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] + node _T_861 = andr(_T_860) @[lib.scala 88:36] + node _T_862 = and(_T_861, _T_673) @[lib.scala 88:41] + node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] + node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 88:86] + node _T_865 = eq(_T_863, _T_864) @[lib.scala 88:78] + node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 88:23] + _T_670[27] <= _T_866 @[lib.scala 88:17] + node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] + node _T_868 = andr(_T_867) @[lib.scala 88:36] + node _T_869 = and(_T_868, _T_673) @[lib.scala 88:41] + node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] + node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 88:86] + node _T_872 = eq(_T_870, _T_871) @[lib.scala 88:78] + node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 88:23] + _T_670[28] <= _T_873 @[lib.scala 88:17] + node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] + node _T_875 = andr(_T_874) @[lib.scala 88:36] + node _T_876 = and(_T_875, _T_673) @[lib.scala 88:41] + node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] + node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 88:86] + node _T_879 = eq(_T_877, _T_878) @[lib.scala 88:78] + node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 88:23] + _T_670[29] <= _T_880 @[lib.scala 88:17] + node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] + node _T_882 = andr(_T_881) @[lib.scala 88:36] + node _T_883 = and(_T_882, _T_673) @[lib.scala 88:41] + node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] + node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 88:86] + node _T_886 = eq(_T_884, _T_885) @[lib.scala 88:78] + node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 88:23] + _T_670[30] <= _T_887 @[lib.scala 88:17] + node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] + node _T_889 = andr(_T_888) @[lib.scala 88:36] + node _T_890 = and(_T_889, _T_673) @[lib.scala 88:41] + node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] + node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 88:86] + node _T_893 = eq(_T_891, _T_892) @[lib.scala 88:78] + node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 88:23] + _T_670[31] <= _T_894 @[lib.scala 88:17] + node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 89:14] + node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 89:14] + node _T_897 = cat(_T_896, _T_895) @[lib.scala 89:14] + node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 89:14] + node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 89:14] + node _T_900 = cat(_T_899, _T_898) @[lib.scala 89:14] + node _T_901 = cat(_T_900, _T_897) @[lib.scala 89:14] + node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 89:14] + node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 89:14] + node _T_904 = cat(_T_903, _T_902) @[lib.scala 89:14] + node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 89:14] + node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 89:14] + node _T_907 = cat(_T_906, _T_905) @[lib.scala 89:14] + node _T_908 = cat(_T_907, _T_904) @[lib.scala 89:14] + node _T_909 = cat(_T_908, _T_901) @[lib.scala 89:14] + node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 89:14] + node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 89:14] + node _T_912 = cat(_T_911, _T_910) @[lib.scala 89:14] + node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 89:14] + node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 89:14] + node _T_915 = cat(_T_914, _T_913) @[lib.scala 89:14] + node _T_916 = cat(_T_915, _T_912) @[lib.scala 89:14] + node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 89:14] + node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 89:14] + node _T_919 = cat(_T_918, _T_917) @[lib.scala 89:14] + node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 89:14] + node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 89:14] + node _T_922 = cat(_T_921, _T_920) @[lib.scala 89:14] + node _T_923 = cat(_T_922, _T_919) @[lib.scala 89:14] + node _T_924 = cat(_T_923, _T_916) @[lib.scala 89:14] + node _T_925 = cat(_T_924, _T_909) @[lib.scala 89:14] + node _T_926 = andr(_T_925) @[lib.scala 89:25] + node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109] + node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] + node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_930 : UInt<1>[32] @[lib.scala 84:24] + node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] + node _T_932 = not(_T_931) @[lib.scala 85:39] + node _T_933 = and(_T_929, _T_932) @[lib.scala 85:37] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] + node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 86:60] + node _T_936 = eq(_T_934, _T_935) @[lib.scala 86:52] + node _T_937 = or(_T_933, _T_936) @[lib.scala 86:41] + _T_930[0] <= _T_937 @[lib.scala 86:18] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] + node _T_939 = andr(_T_938) @[lib.scala 88:36] + node _T_940 = and(_T_939, _T_933) @[lib.scala 88:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] + node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 88:86] + node _T_943 = eq(_T_941, _T_942) @[lib.scala 88:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 88:23] + _T_930[1] <= _T_944 @[lib.scala 88:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] + node _T_946 = andr(_T_945) @[lib.scala 88:36] + node _T_947 = and(_T_946, _T_933) @[lib.scala 88:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] + node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 88:86] + node _T_950 = eq(_T_948, _T_949) @[lib.scala 88:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 88:23] + _T_930[2] <= _T_951 @[lib.scala 88:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] + node _T_953 = andr(_T_952) @[lib.scala 88:36] + node _T_954 = and(_T_953, _T_933) @[lib.scala 88:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] + node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 88:86] + node _T_957 = eq(_T_955, _T_956) @[lib.scala 88:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 88:23] + _T_930[3] <= _T_958 @[lib.scala 88:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] + node _T_960 = andr(_T_959) @[lib.scala 88:36] + node _T_961 = and(_T_960, _T_933) @[lib.scala 88:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] + node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 88:86] + node _T_964 = eq(_T_962, _T_963) @[lib.scala 88:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 88:23] + _T_930[4] <= _T_965 @[lib.scala 88:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] + node _T_967 = andr(_T_966) @[lib.scala 88:36] + node _T_968 = and(_T_967, _T_933) @[lib.scala 88:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] + node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 88:86] + node _T_971 = eq(_T_969, _T_970) @[lib.scala 88:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 88:23] + _T_930[5] <= _T_972 @[lib.scala 88:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] + node _T_974 = andr(_T_973) @[lib.scala 88:36] + node _T_975 = and(_T_974, _T_933) @[lib.scala 88:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] + node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 88:86] + node _T_978 = eq(_T_976, _T_977) @[lib.scala 88:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 88:23] + _T_930[6] <= _T_979 @[lib.scala 88:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] + node _T_981 = andr(_T_980) @[lib.scala 88:36] + node _T_982 = and(_T_981, _T_933) @[lib.scala 88:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] + node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 88:86] + node _T_985 = eq(_T_983, _T_984) @[lib.scala 88:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 88:23] + _T_930[7] <= _T_986 @[lib.scala 88:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] + node _T_988 = andr(_T_987) @[lib.scala 88:36] + node _T_989 = and(_T_988, _T_933) @[lib.scala 88:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] + node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 88:86] + node _T_992 = eq(_T_990, _T_991) @[lib.scala 88:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 88:23] + _T_930[8] <= _T_993 @[lib.scala 88:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] + node _T_995 = andr(_T_994) @[lib.scala 88:36] + node _T_996 = and(_T_995, _T_933) @[lib.scala 88:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] + node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 88:86] + node _T_999 = eq(_T_997, _T_998) @[lib.scala 88:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 88:23] + _T_930[9] <= _T_1000 @[lib.scala 88:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] + node _T_1002 = andr(_T_1001) @[lib.scala 88:36] + node _T_1003 = and(_T_1002, _T_933) @[lib.scala 88:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] + node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 88:86] + node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 88:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 88:23] + _T_930[10] <= _T_1007 @[lib.scala 88:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] + node _T_1009 = andr(_T_1008) @[lib.scala 88:36] + node _T_1010 = and(_T_1009, _T_933) @[lib.scala 88:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] + node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 88:86] + node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 88:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 88:23] + _T_930[11] <= _T_1014 @[lib.scala 88:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] + node _T_1016 = andr(_T_1015) @[lib.scala 88:36] + node _T_1017 = and(_T_1016, _T_933) @[lib.scala 88:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] + node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 88:86] + node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 88:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 88:23] + _T_930[12] <= _T_1021 @[lib.scala 88:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] + node _T_1023 = andr(_T_1022) @[lib.scala 88:36] + node _T_1024 = and(_T_1023, _T_933) @[lib.scala 88:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] + node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 88:86] + node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 88:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 88:23] + _T_930[13] <= _T_1028 @[lib.scala 88:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] + node _T_1030 = andr(_T_1029) @[lib.scala 88:36] + node _T_1031 = and(_T_1030, _T_933) @[lib.scala 88:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] + node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 88:86] + node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 88:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 88:23] + _T_930[14] <= _T_1035 @[lib.scala 88:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] + node _T_1037 = andr(_T_1036) @[lib.scala 88:36] + node _T_1038 = and(_T_1037, _T_933) @[lib.scala 88:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] + node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 88:86] + node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 88:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 88:23] + _T_930[15] <= _T_1042 @[lib.scala 88:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] + node _T_1044 = andr(_T_1043) @[lib.scala 88:36] + node _T_1045 = and(_T_1044, _T_933) @[lib.scala 88:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] + node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 88:86] + node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 88:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 88:23] + _T_930[16] <= _T_1049 @[lib.scala 88:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] + node _T_1051 = andr(_T_1050) @[lib.scala 88:36] + node _T_1052 = and(_T_1051, _T_933) @[lib.scala 88:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] + node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 88:86] + node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 88:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 88:23] + _T_930[17] <= _T_1056 @[lib.scala 88:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] + node _T_1058 = andr(_T_1057) @[lib.scala 88:36] + node _T_1059 = and(_T_1058, _T_933) @[lib.scala 88:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] + node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 88:86] + node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 88:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 88:23] + _T_930[18] <= _T_1063 @[lib.scala 88:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] + node _T_1065 = andr(_T_1064) @[lib.scala 88:36] + node _T_1066 = and(_T_1065, _T_933) @[lib.scala 88:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] + node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 88:86] + node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 88:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 88:23] + _T_930[19] <= _T_1070 @[lib.scala 88:17] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] + node _T_1072 = andr(_T_1071) @[lib.scala 88:36] + node _T_1073 = and(_T_1072, _T_933) @[lib.scala 88:41] + node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] + node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 88:86] + node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 88:78] + node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 88:23] + _T_930[20] <= _T_1077 @[lib.scala 88:17] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] + node _T_1079 = andr(_T_1078) @[lib.scala 88:36] + node _T_1080 = and(_T_1079, _T_933) @[lib.scala 88:41] + node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] + node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 88:86] + node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 88:78] + node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 88:23] + _T_930[21] <= _T_1084 @[lib.scala 88:17] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] + node _T_1086 = andr(_T_1085) @[lib.scala 88:36] + node _T_1087 = and(_T_1086, _T_933) @[lib.scala 88:41] + node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] + node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 88:86] + node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 88:78] + node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 88:23] + _T_930[22] <= _T_1091 @[lib.scala 88:17] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] + node _T_1093 = andr(_T_1092) @[lib.scala 88:36] + node _T_1094 = and(_T_1093, _T_933) @[lib.scala 88:41] + node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] + node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 88:86] + node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 88:78] + node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 88:23] + _T_930[23] <= _T_1098 @[lib.scala 88:17] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] + node _T_1100 = andr(_T_1099) @[lib.scala 88:36] + node _T_1101 = and(_T_1100, _T_933) @[lib.scala 88:41] + node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] + node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 88:86] + node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 88:78] + node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 88:23] + _T_930[24] <= _T_1105 @[lib.scala 88:17] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] + node _T_1107 = andr(_T_1106) @[lib.scala 88:36] + node _T_1108 = and(_T_1107, _T_933) @[lib.scala 88:41] + node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] + node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 88:86] + node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 88:78] + node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 88:23] + _T_930[25] <= _T_1112 @[lib.scala 88:17] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] + node _T_1114 = andr(_T_1113) @[lib.scala 88:36] + node _T_1115 = and(_T_1114, _T_933) @[lib.scala 88:41] + node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] + node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 88:86] + node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 88:78] + node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 88:23] + _T_930[26] <= _T_1119 @[lib.scala 88:17] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] + node _T_1121 = andr(_T_1120) @[lib.scala 88:36] + node _T_1122 = and(_T_1121, _T_933) @[lib.scala 88:41] + node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] + node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 88:86] + node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 88:78] + node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 88:23] + _T_930[27] <= _T_1126 @[lib.scala 88:17] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] + node _T_1128 = andr(_T_1127) @[lib.scala 88:36] + node _T_1129 = and(_T_1128, _T_933) @[lib.scala 88:41] + node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] + node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 88:86] + node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 88:78] + node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 88:23] + _T_930[28] <= _T_1133 @[lib.scala 88:17] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] + node _T_1135 = andr(_T_1134) @[lib.scala 88:36] + node _T_1136 = and(_T_1135, _T_933) @[lib.scala 88:41] + node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] + node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 88:86] + node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 88:78] + node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 88:23] + _T_930[29] <= _T_1140 @[lib.scala 88:17] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] + node _T_1142 = andr(_T_1141) @[lib.scala 88:36] + node _T_1143 = and(_T_1142, _T_933) @[lib.scala 88:41] + node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] + node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 88:86] + node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 88:78] + node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 88:23] + _T_930[30] <= _T_1147 @[lib.scala 88:17] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] + node _T_1149 = andr(_T_1148) @[lib.scala 88:36] + node _T_1150 = and(_T_1149, _T_933) @[lib.scala 88:41] + node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] + node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 88:86] + node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 88:78] + node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 88:23] + _T_930[31] <= _T_1154 @[lib.scala 88:17] + node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 89:14] + node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 89:14] node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 89:14] - node _T_1158 = cat(_T_1157, _T_1154) @[lib.scala 89:14] - node _T_1159 = cat(_T_927[9], _T_927[8]) @[lib.scala 89:14] - node _T_1160 = cat(_T_927[11], _T_927[10]) @[lib.scala 89:14] - node _T_1161 = cat(_T_1160, _T_1159) @[lib.scala 89:14] - node _T_1162 = cat(_T_927[13], _T_927[12]) @[lib.scala 89:14] - node _T_1163 = cat(_T_927[15], _T_927[14]) @[lib.scala 89:14] + node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 89:14] + node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 89:14] + node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 89:14] + node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 89:14] + node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 89:14] + node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 89:14] node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 89:14] - node _T_1165 = cat(_T_1164, _T_1161) @[lib.scala 89:14] - node _T_1166 = cat(_T_1165, _T_1158) @[lib.scala 89:14] - node _T_1167 = cat(_T_927[17], _T_927[16]) @[lib.scala 89:14] - node _T_1168 = cat(_T_927[19], _T_927[18]) @[lib.scala 89:14] - node _T_1169 = cat(_T_1168, _T_1167) @[lib.scala 89:14] - node _T_1170 = cat(_T_927[21], _T_927[20]) @[lib.scala 89:14] - node _T_1171 = cat(_T_927[23], _T_927[22]) @[lib.scala 89:14] + node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 89:14] + node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 89:14] + node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 89:14] + node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 89:14] + node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 89:14] + node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 89:14] + node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 89:14] node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 89:14] - node _T_1173 = cat(_T_1172, _T_1169) @[lib.scala 89:14] - node _T_1174 = cat(_T_927[25], _T_927[24]) @[lib.scala 89:14] - node _T_1175 = cat(_T_927[27], _T_927[26]) @[lib.scala 89:14] - node _T_1176 = cat(_T_1175, _T_1174) @[lib.scala 89:14] - node _T_1177 = cat(_T_927[29], _T_927[28]) @[lib.scala 89:14] - node _T_1178 = cat(_T_927[31], _T_927[30]) @[lib.scala 89:14] + node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 89:14] + node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 89:14] + node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 89:14] + node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 89:14] + node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 89:14] + node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 89:14] node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 89:14] - node _T_1180 = cat(_T_1179, _T_1176) @[lib.scala 89:14] - node _T_1181 = cat(_T_1180, _T_1173) @[lib.scala 89:14] - node _T_1182 = cat(_T_1181, _T_1166) @[lib.scala 89:14] - node _T_1183 = and(_T_925, _T_1182) @[dec_trigger.scala 15:109] - node _T_1184 = cat(_T_1183, _T_924) @[Cat.scala 29:58] - node _T_1185 = cat(_T_1184, _T_665) @[Cat.scala 29:58] - node _T_1186 = cat(_T_1185, _T_406) @[Cat.scala 29:58] - io.dec_i0_trigger_match_d <= _T_1186 @[dec_trigger.scala 15:29] + node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 89:14] + node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 89:14] + node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 89:14] + node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 89:14] + node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 89:14] + node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 89:14] + node _T_1186 = andr(_T_1185) @[lib.scala 89:25] + node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109] + node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58] + node _T_1190 = cat(_T_1189, _T_407) @[Cat.scala 29:58] + io.dec_i0_trigger_match_d <= _T_1190 @[dec_trigger.scala 15:29] module dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -81793,7 +81797,7 @@ circuit quasar_wrapper : module dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") @@ -93283,905 +93287,909 @@ circuit quasar_wrapper : node _T_301 = cat(_T_300, _T_297) @[lib.scala 89:14] node _T_302 = cat(_T_301, _T_294) @[lib.scala 89:14] node _T_303 = cat(_T_302, _T_287) @[lib.scala 89:14] - node _T_304 = and(_T_46, _T_303) @[lsu_trigger.scala 19:92] - node _T_305 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_306 = and(io.lsu_pkt_m.valid, _T_305) @[lsu_trigger.scala 18:69] - node _T_307 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_308 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_309 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_310 = and(_T_308, _T_309) @[lsu_trigger.scala 19:58] - node _T_311 = or(_T_307, _T_310) @[lsu_trigger.scala 18:152] - node _T_312 = and(_T_306, _T_311) @[lsu_trigger.scala 18:94] - node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_314 : UInt<1>[32] @[lib.scala 84:24] - node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] - node _T_316 = not(_T_315) @[lib.scala 85:39] - node _T_317 = and(_T_313, _T_316) @[lib.scala 85:37] - node _T_318 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] - node _T_319 = bits(lsu_match_data_1, 0, 0) @[lib.scala 86:60] - node _T_320 = eq(_T_318, _T_319) @[lib.scala 86:52] - node _T_321 = or(_T_317, _T_320) @[lib.scala 86:41] - _T_314[0] <= _T_321 @[lib.scala 86:18] - node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] - node _T_323 = andr(_T_322) @[lib.scala 88:36] - node _T_324 = and(_T_323, _T_317) @[lib.scala 88:41] - node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] - node _T_326 = bits(lsu_match_data_1, 1, 1) @[lib.scala 88:86] - node _T_327 = eq(_T_325, _T_326) @[lib.scala 88:78] - node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[lib.scala 88:23] - _T_314[1] <= _T_328 @[lib.scala 88:17] - node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] - node _T_330 = andr(_T_329) @[lib.scala 88:36] - node _T_331 = and(_T_330, _T_317) @[lib.scala 88:41] - node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] - node _T_333 = bits(lsu_match_data_1, 2, 2) @[lib.scala 88:86] - node _T_334 = eq(_T_332, _T_333) @[lib.scala 88:78] - node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[lib.scala 88:23] - _T_314[2] <= _T_335 @[lib.scala 88:17] - node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] - node _T_337 = andr(_T_336) @[lib.scala 88:36] - node _T_338 = and(_T_337, _T_317) @[lib.scala 88:41] - node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] - node _T_340 = bits(lsu_match_data_1, 3, 3) @[lib.scala 88:86] - node _T_341 = eq(_T_339, _T_340) @[lib.scala 88:78] - node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[lib.scala 88:23] - _T_314[3] <= _T_342 @[lib.scala 88:17] - node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] - node _T_344 = andr(_T_343) @[lib.scala 88:36] - node _T_345 = and(_T_344, _T_317) @[lib.scala 88:41] - node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] - node _T_347 = bits(lsu_match_data_1, 4, 4) @[lib.scala 88:86] - node _T_348 = eq(_T_346, _T_347) @[lib.scala 88:78] - node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[lib.scala 88:23] - _T_314[4] <= _T_349 @[lib.scala 88:17] - node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] - node _T_351 = andr(_T_350) @[lib.scala 88:36] - node _T_352 = and(_T_351, _T_317) @[lib.scala 88:41] - node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] - node _T_354 = bits(lsu_match_data_1, 5, 5) @[lib.scala 88:86] - node _T_355 = eq(_T_353, _T_354) @[lib.scala 88:78] - node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[lib.scala 88:23] - _T_314[5] <= _T_356 @[lib.scala 88:17] - node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] - node _T_358 = andr(_T_357) @[lib.scala 88:36] - node _T_359 = and(_T_358, _T_317) @[lib.scala 88:41] - node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] - node _T_361 = bits(lsu_match_data_1, 6, 6) @[lib.scala 88:86] - node _T_362 = eq(_T_360, _T_361) @[lib.scala 88:78] - node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[lib.scala 88:23] - _T_314[6] <= _T_363 @[lib.scala 88:17] - node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] - node _T_365 = andr(_T_364) @[lib.scala 88:36] - node _T_366 = and(_T_365, _T_317) @[lib.scala 88:41] - node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] - node _T_368 = bits(lsu_match_data_1, 7, 7) @[lib.scala 88:86] - node _T_369 = eq(_T_367, _T_368) @[lib.scala 88:78] - node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[lib.scala 88:23] - _T_314[7] <= _T_370 @[lib.scala 88:17] - node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] - node _T_372 = andr(_T_371) @[lib.scala 88:36] - node _T_373 = and(_T_372, _T_317) @[lib.scala 88:41] - node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] - node _T_375 = bits(lsu_match_data_1, 8, 8) @[lib.scala 88:86] - node _T_376 = eq(_T_374, _T_375) @[lib.scala 88:78] - node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[lib.scala 88:23] - _T_314[8] <= _T_377 @[lib.scala 88:17] - node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] - node _T_379 = andr(_T_378) @[lib.scala 88:36] - node _T_380 = and(_T_379, _T_317) @[lib.scala 88:41] - node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] - node _T_382 = bits(lsu_match_data_1, 9, 9) @[lib.scala 88:86] - node _T_383 = eq(_T_381, _T_382) @[lib.scala 88:78] - node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[lib.scala 88:23] - _T_314[9] <= _T_384 @[lib.scala 88:17] - node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] - node _T_386 = andr(_T_385) @[lib.scala 88:36] - node _T_387 = and(_T_386, _T_317) @[lib.scala 88:41] - node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] - node _T_389 = bits(lsu_match_data_1, 10, 10) @[lib.scala 88:86] - node _T_390 = eq(_T_388, _T_389) @[lib.scala 88:78] - node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[lib.scala 88:23] - _T_314[10] <= _T_391 @[lib.scala 88:17] - node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] - node _T_393 = andr(_T_392) @[lib.scala 88:36] - node _T_394 = and(_T_393, _T_317) @[lib.scala 88:41] - node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] - node _T_396 = bits(lsu_match_data_1, 11, 11) @[lib.scala 88:86] - node _T_397 = eq(_T_395, _T_396) @[lib.scala 88:78] - node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[lib.scala 88:23] - _T_314[11] <= _T_398 @[lib.scala 88:17] - node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] - node _T_400 = andr(_T_399) @[lib.scala 88:36] - node _T_401 = and(_T_400, _T_317) @[lib.scala 88:41] - node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] - node _T_403 = bits(lsu_match_data_1, 12, 12) @[lib.scala 88:86] - node _T_404 = eq(_T_402, _T_403) @[lib.scala 88:78] - node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[lib.scala 88:23] - _T_314[12] <= _T_405 @[lib.scala 88:17] - node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] - node _T_407 = andr(_T_406) @[lib.scala 88:36] - node _T_408 = and(_T_407, _T_317) @[lib.scala 88:41] - node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] - node _T_410 = bits(lsu_match_data_1, 13, 13) @[lib.scala 88:86] - node _T_411 = eq(_T_409, _T_410) @[lib.scala 88:78] - node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[lib.scala 88:23] - _T_314[13] <= _T_412 @[lib.scala 88:17] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] - node _T_414 = andr(_T_413) @[lib.scala 88:36] - node _T_415 = and(_T_414, _T_317) @[lib.scala 88:41] - node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] - node _T_417 = bits(lsu_match_data_1, 14, 14) @[lib.scala 88:86] - node _T_418 = eq(_T_416, _T_417) @[lib.scala 88:78] - node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[lib.scala 88:23] - _T_314[14] <= _T_419 @[lib.scala 88:17] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] - node _T_421 = andr(_T_420) @[lib.scala 88:36] - node _T_422 = and(_T_421, _T_317) @[lib.scala 88:41] - node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] - node _T_424 = bits(lsu_match_data_1, 15, 15) @[lib.scala 88:86] - node _T_425 = eq(_T_423, _T_424) @[lib.scala 88:78] - node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[lib.scala 88:23] - _T_314[15] <= _T_426 @[lib.scala 88:17] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] - node _T_428 = andr(_T_427) @[lib.scala 88:36] - node _T_429 = and(_T_428, _T_317) @[lib.scala 88:41] - node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] - node _T_431 = bits(lsu_match_data_1, 16, 16) @[lib.scala 88:86] - node _T_432 = eq(_T_430, _T_431) @[lib.scala 88:78] - node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[lib.scala 88:23] - _T_314[16] <= _T_433 @[lib.scala 88:17] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] - node _T_435 = andr(_T_434) @[lib.scala 88:36] - node _T_436 = and(_T_435, _T_317) @[lib.scala 88:41] - node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] - node _T_438 = bits(lsu_match_data_1, 17, 17) @[lib.scala 88:86] - node _T_439 = eq(_T_437, _T_438) @[lib.scala 88:78] - node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[lib.scala 88:23] - _T_314[17] <= _T_440 @[lib.scala 88:17] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] - node _T_442 = andr(_T_441) @[lib.scala 88:36] - node _T_443 = and(_T_442, _T_317) @[lib.scala 88:41] - node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] - node _T_445 = bits(lsu_match_data_1, 18, 18) @[lib.scala 88:86] - node _T_446 = eq(_T_444, _T_445) @[lib.scala 88:78] - node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[lib.scala 88:23] - _T_314[18] <= _T_447 @[lib.scala 88:17] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] - node _T_449 = andr(_T_448) @[lib.scala 88:36] - node _T_450 = and(_T_449, _T_317) @[lib.scala 88:41] - node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] - node _T_452 = bits(lsu_match_data_1, 19, 19) @[lib.scala 88:86] - node _T_453 = eq(_T_451, _T_452) @[lib.scala 88:78] - node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[lib.scala 88:23] - _T_314[19] <= _T_454 @[lib.scala 88:17] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] - node _T_456 = andr(_T_455) @[lib.scala 88:36] - node _T_457 = and(_T_456, _T_317) @[lib.scala 88:41] - node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] - node _T_459 = bits(lsu_match_data_1, 20, 20) @[lib.scala 88:86] - node _T_460 = eq(_T_458, _T_459) @[lib.scala 88:78] - node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[lib.scala 88:23] - _T_314[20] <= _T_461 @[lib.scala 88:17] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] - node _T_463 = andr(_T_462) @[lib.scala 88:36] - node _T_464 = and(_T_463, _T_317) @[lib.scala 88:41] - node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] - node _T_466 = bits(lsu_match_data_1, 21, 21) @[lib.scala 88:86] - node _T_467 = eq(_T_465, _T_466) @[lib.scala 88:78] - node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[lib.scala 88:23] - _T_314[21] <= _T_468 @[lib.scala 88:17] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] - node _T_470 = andr(_T_469) @[lib.scala 88:36] - node _T_471 = and(_T_470, _T_317) @[lib.scala 88:41] - node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] - node _T_473 = bits(lsu_match_data_1, 22, 22) @[lib.scala 88:86] - node _T_474 = eq(_T_472, _T_473) @[lib.scala 88:78] - node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[lib.scala 88:23] - _T_314[22] <= _T_475 @[lib.scala 88:17] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] - node _T_477 = andr(_T_476) @[lib.scala 88:36] - node _T_478 = and(_T_477, _T_317) @[lib.scala 88:41] - node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] - node _T_480 = bits(lsu_match_data_1, 23, 23) @[lib.scala 88:86] - node _T_481 = eq(_T_479, _T_480) @[lib.scala 88:78] - node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[lib.scala 88:23] - _T_314[23] <= _T_482 @[lib.scala 88:17] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] - node _T_484 = andr(_T_483) @[lib.scala 88:36] - node _T_485 = and(_T_484, _T_317) @[lib.scala 88:41] - node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] - node _T_487 = bits(lsu_match_data_1, 24, 24) @[lib.scala 88:86] - node _T_488 = eq(_T_486, _T_487) @[lib.scala 88:78] - node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[lib.scala 88:23] - _T_314[24] <= _T_489 @[lib.scala 88:17] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] - node _T_491 = andr(_T_490) @[lib.scala 88:36] - node _T_492 = and(_T_491, _T_317) @[lib.scala 88:41] - node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] - node _T_494 = bits(lsu_match_data_1, 25, 25) @[lib.scala 88:86] - node _T_495 = eq(_T_493, _T_494) @[lib.scala 88:78] - node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[lib.scala 88:23] - _T_314[25] <= _T_496 @[lib.scala 88:17] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] - node _T_498 = andr(_T_497) @[lib.scala 88:36] - node _T_499 = and(_T_498, _T_317) @[lib.scala 88:41] - node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] - node _T_501 = bits(lsu_match_data_1, 26, 26) @[lib.scala 88:86] - node _T_502 = eq(_T_500, _T_501) @[lib.scala 88:78] - node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[lib.scala 88:23] - _T_314[26] <= _T_503 @[lib.scala 88:17] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] - node _T_505 = andr(_T_504) @[lib.scala 88:36] - node _T_506 = and(_T_505, _T_317) @[lib.scala 88:41] - node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] - node _T_508 = bits(lsu_match_data_1, 27, 27) @[lib.scala 88:86] - node _T_509 = eq(_T_507, _T_508) @[lib.scala 88:78] - node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[lib.scala 88:23] - _T_314[27] <= _T_510 @[lib.scala 88:17] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] - node _T_512 = andr(_T_511) @[lib.scala 88:36] - node _T_513 = and(_T_512, _T_317) @[lib.scala 88:41] - node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] - node _T_515 = bits(lsu_match_data_1, 28, 28) @[lib.scala 88:86] - node _T_516 = eq(_T_514, _T_515) @[lib.scala 88:78] - node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[lib.scala 88:23] - _T_314[28] <= _T_517 @[lib.scala 88:17] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] - node _T_519 = andr(_T_518) @[lib.scala 88:36] - node _T_520 = and(_T_519, _T_317) @[lib.scala 88:41] - node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] - node _T_522 = bits(lsu_match_data_1, 29, 29) @[lib.scala 88:86] - node _T_523 = eq(_T_521, _T_522) @[lib.scala 88:78] - node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[lib.scala 88:23] - _T_314[29] <= _T_524 @[lib.scala 88:17] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] - node _T_526 = andr(_T_525) @[lib.scala 88:36] - node _T_527 = and(_T_526, _T_317) @[lib.scala 88:41] - node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] - node _T_529 = bits(lsu_match_data_1, 30, 30) @[lib.scala 88:86] - node _T_530 = eq(_T_528, _T_529) @[lib.scala 88:78] - node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[lib.scala 88:23] - _T_314[30] <= _T_531 @[lib.scala 88:17] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] - node _T_533 = andr(_T_532) @[lib.scala 88:36] - node _T_534 = and(_T_533, _T_317) @[lib.scala 88:41] - node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] - node _T_536 = bits(lsu_match_data_1, 31, 31) @[lib.scala 88:86] - node _T_537 = eq(_T_535, _T_536) @[lib.scala 88:78] - node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[lib.scala 88:23] - _T_314[31] <= _T_538 @[lib.scala 88:17] - node _T_539 = cat(_T_314[1], _T_314[0]) @[lib.scala 89:14] - node _T_540 = cat(_T_314[3], _T_314[2]) @[lib.scala 89:14] - node _T_541 = cat(_T_540, _T_539) @[lib.scala 89:14] - node _T_542 = cat(_T_314[5], _T_314[4]) @[lib.scala 89:14] - node _T_543 = cat(_T_314[7], _T_314[6]) @[lib.scala 89:14] - node _T_544 = cat(_T_543, _T_542) @[lib.scala 89:14] - node _T_545 = cat(_T_544, _T_541) @[lib.scala 89:14] - node _T_546 = cat(_T_314[9], _T_314[8]) @[lib.scala 89:14] - node _T_547 = cat(_T_314[11], _T_314[10]) @[lib.scala 89:14] - node _T_548 = cat(_T_547, _T_546) @[lib.scala 89:14] - node _T_549 = cat(_T_314[13], _T_314[12]) @[lib.scala 89:14] - node _T_550 = cat(_T_314[15], _T_314[14]) @[lib.scala 89:14] - node _T_551 = cat(_T_550, _T_549) @[lib.scala 89:14] - node _T_552 = cat(_T_551, _T_548) @[lib.scala 89:14] - node _T_553 = cat(_T_552, _T_545) @[lib.scala 89:14] - node _T_554 = cat(_T_314[17], _T_314[16]) @[lib.scala 89:14] - node _T_555 = cat(_T_314[19], _T_314[18]) @[lib.scala 89:14] - node _T_556 = cat(_T_555, _T_554) @[lib.scala 89:14] - node _T_557 = cat(_T_314[21], _T_314[20]) @[lib.scala 89:14] - node _T_558 = cat(_T_314[23], _T_314[22]) @[lib.scala 89:14] - node _T_559 = cat(_T_558, _T_557) @[lib.scala 89:14] - node _T_560 = cat(_T_559, _T_556) @[lib.scala 89:14] - node _T_561 = cat(_T_314[25], _T_314[24]) @[lib.scala 89:14] - node _T_562 = cat(_T_314[27], _T_314[26]) @[lib.scala 89:14] - node _T_563 = cat(_T_562, _T_561) @[lib.scala 89:14] - node _T_564 = cat(_T_314[29], _T_314[28]) @[lib.scala 89:14] - node _T_565 = cat(_T_314[31], _T_314[30]) @[lib.scala 89:14] - node _T_566 = cat(_T_565, _T_564) @[lib.scala 89:14] - node _T_567 = cat(_T_566, _T_563) @[lib.scala 89:14] - node _T_568 = cat(_T_567, _T_560) @[lib.scala 89:14] - node _T_569 = cat(_T_568, _T_553) @[lib.scala 89:14] - node _T_570 = and(_T_312, _T_569) @[lsu_trigger.scala 19:92] - node _T_571 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_572 = and(io.lsu_pkt_m.valid, _T_571) @[lsu_trigger.scala 18:69] - node _T_573 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_574 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_575 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_576 = and(_T_574, _T_575) @[lsu_trigger.scala 19:58] - node _T_577 = or(_T_573, _T_576) @[lsu_trigger.scala 18:152] - node _T_578 = and(_T_572, _T_577) @[lsu_trigger.scala 18:94] - node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_580 : UInt<1>[32] @[lib.scala 84:24] - node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] - node _T_582 = not(_T_581) @[lib.scala 85:39] - node _T_583 = and(_T_579, _T_582) @[lib.scala 85:37] - node _T_584 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] - node _T_585 = bits(lsu_match_data_2, 0, 0) @[lib.scala 86:60] - node _T_586 = eq(_T_584, _T_585) @[lib.scala 86:52] - node _T_587 = or(_T_583, _T_586) @[lib.scala 86:41] - _T_580[0] <= _T_587 @[lib.scala 86:18] - node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] - node _T_589 = andr(_T_588) @[lib.scala 88:36] - node _T_590 = and(_T_589, _T_583) @[lib.scala 88:41] - node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] - node _T_592 = bits(lsu_match_data_2, 1, 1) @[lib.scala 88:86] - node _T_593 = eq(_T_591, _T_592) @[lib.scala 88:78] - node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[lib.scala 88:23] - _T_580[1] <= _T_594 @[lib.scala 88:17] - node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] - node _T_596 = andr(_T_595) @[lib.scala 88:36] - node _T_597 = and(_T_596, _T_583) @[lib.scala 88:41] - node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] - node _T_599 = bits(lsu_match_data_2, 2, 2) @[lib.scala 88:86] - node _T_600 = eq(_T_598, _T_599) @[lib.scala 88:78] - node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[lib.scala 88:23] - _T_580[2] <= _T_601 @[lib.scala 88:17] - node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] - node _T_603 = andr(_T_602) @[lib.scala 88:36] - node _T_604 = and(_T_603, _T_583) @[lib.scala 88:41] - node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] - node _T_606 = bits(lsu_match_data_2, 3, 3) @[lib.scala 88:86] - node _T_607 = eq(_T_605, _T_606) @[lib.scala 88:78] - node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[lib.scala 88:23] - _T_580[3] <= _T_608 @[lib.scala 88:17] - node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] - node _T_610 = andr(_T_609) @[lib.scala 88:36] - node _T_611 = and(_T_610, _T_583) @[lib.scala 88:41] - node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] - node _T_613 = bits(lsu_match_data_2, 4, 4) @[lib.scala 88:86] - node _T_614 = eq(_T_612, _T_613) @[lib.scala 88:78] - node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[lib.scala 88:23] - _T_580[4] <= _T_615 @[lib.scala 88:17] - node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] - node _T_617 = andr(_T_616) @[lib.scala 88:36] - node _T_618 = and(_T_617, _T_583) @[lib.scala 88:41] - node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] - node _T_620 = bits(lsu_match_data_2, 5, 5) @[lib.scala 88:86] - node _T_621 = eq(_T_619, _T_620) @[lib.scala 88:78] - node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[lib.scala 88:23] - _T_580[5] <= _T_622 @[lib.scala 88:17] - node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] - node _T_624 = andr(_T_623) @[lib.scala 88:36] - node _T_625 = and(_T_624, _T_583) @[lib.scala 88:41] - node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] - node _T_627 = bits(lsu_match_data_2, 6, 6) @[lib.scala 88:86] - node _T_628 = eq(_T_626, _T_627) @[lib.scala 88:78] - node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[lib.scala 88:23] - _T_580[6] <= _T_629 @[lib.scala 88:17] - node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] - node _T_631 = andr(_T_630) @[lib.scala 88:36] - node _T_632 = and(_T_631, _T_583) @[lib.scala 88:41] - node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] - node _T_634 = bits(lsu_match_data_2, 7, 7) @[lib.scala 88:86] - node _T_635 = eq(_T_633, _T_634) @[lib.scala 88:78] - node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[lib.scala 88:23] - _T_580[7] <= _T_636 @[lib.scala 88:17] - node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] - node _T_638 = andr(_T_637) @[lib.scala 88:36] - node _T_639 = and(_T_638, _T_583) @[lib.scala 88:41] - node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] - node _T_641 = bits(lsu_match_data_2, 8, 8) @[lib.scala 88:86] - node _T_642 = eq(_T_640, _T_641) @[lib.scala 88:78] - node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[lib.scala 88:23] - _T_580[8] <= _T_643 @[lib.scala 88:17] - node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] - node _T_645 = andr(_T_644) @[lib.scala 88:36] - node _T_646 = and(_T_645, _T_583) @[lib.scala 88:41] - node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] - node _T_648 = bits(lsu_match_data_2, 9, 9) @[lib.scala 88:86] - node _T_649 = eq(_T_647, _T_648) @[lib.scala 88:78] - node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[lib.scala 88:23] - _T_580[9] <= _T_650 @[lib.scala 88:17] - node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] - node _T_652 = andr(_T_651) @[lib.scala 88:36] - node _T_653 = and(_T_652, _T_583) @[lib.scala 88:41] - node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] - node _T_655 = bits(lsu_match_data_2, 10, 10) @[lib.scala 88:86] - node _T_656 = eq(_T_654, _T_655) @[lib.scala 88:78] - node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[lib.scala 88:23] - _T_580[10] <= _T_657 @[lib.scala 88:17] - node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] - node _T_659 = andr(_T_658) @[lib.scala 88:36] - node _T_660 = and(_T_659, _T_583) @[lib.scala 88:41] - node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] - node _T_662 = bits(lsu_match_data_2, 11, 11) @[lib.scala 88:86] - node _T_663 = eq(_T_661, _T_662) @[lib.scala 88:78] - node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[lib.scala 88:23] - _T_580[11] <= _T_664 @[lib.scala 88:17] - node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] - node _T_666 = andr(_T_665) @[lib.scala 88:36] - node _T_667 = and(_T_666, _T_583) @[lib.scala 88:41] - node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] - node _T_669 = bits(lsu_match_data_2, 12, 12) @[lib.scala 88:86] - node _T_670 = eq(_T_668, _T_669) @[lib.scala 88:78] - node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[lib.scala 88:23] - _T_580[12] <= _T_671 @[lib.scala 88:17] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] - node _T_673 = andr(_T_672) @[lib.scala 88:36] - node _T_674 = and(_T_673, _T_583) @[lib.scala 88:41] - node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] - node _T_676 = bits(lsu_match_data_2, 13, 13) @[lib.scala 88:86] - node _T_677 = eq(_T_675, _T_676) @[lib.scala 88:78] - node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[lib.scala 88:23] - _T_580[13] <= _T_678 @[lib.scala 88:17] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] - node _T_680 = andr(_T_679) @[lib.scala 88:36] - node _T_681 = and(_T_680, _T_583) @[lib.scala 88:41] - node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] - node _T_683 = bits(lsu_match_data_2, 14, 14) @[lib.scala 88:86] - node _T_684 = eq(_T_682, _T_683) @[lib.scala 88:78] - node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[lib.scala 88:23] - _T_580[14] <= _T_685 @[lib.scala 88:17] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] - node _T_687 = andr(_T_686) @[lib.scala 88:36] - node _T_688 = and(_T_687, _T_583) @[lib.scala 88:41] - node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] - node _T_690 = bits(lsu_match_data_2, 15, 15) @[lib.scala 88:86] - node _T_691 = eq(_T_689, _T_690) @[lib.scala 88:78] - node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[lib.scala 88:23] - _T_580[15] <= _T_692 @[lib.scala 88:17] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] - node _T_694 = andr(_T_693) @[lib.scala 88:36] - node _T_695 = and(_T_694, _T_583) @[lib.scala 88:41] - node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] - node _T_697 = bits(lsu_match_data_2, 16, 16) @[lib.scala 88:86] - node _T_698 = eq(_T_696, _T_697) @[lib.scala 88:78] - node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[lib.scala 88:23] - _T_580[16] <= _T_699 @[lib.scala 88:17] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] - node _T_701 = andr(_T_700) @[lib.scala 88:36] - node _T_702 = and(_T_701, _T_583) @[lib.scala 88:41] - node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] - node _T_704 = bits(lsu_match_data_2, 17, 17) @[lib.scala 88:86] - node _T_705 = eq(_T_703, _T_704) @[lib.scala 88:78] - node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[lib.scala 88:23] - _T_580[17] <= _T_706 @[lib.scala 88:17] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] - node _T_708 = andr(_T_707) @[lib.scala 88:36] - node _T_709 = and(_T_708, _T_583) @[lib.scala 88:41] - node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] - node _T_711 = bits(lsu_match_data_2, 18, 18) @[lib.scala 88:86] - node _T_712 = eq(_T_710, _T_711) @[lib.scala 88:78] - node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[lib.scala 88:23] - _T_580[18] <= _T_713 @[lib.scala 88:17] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] - node _T_715 = andr(_T_714) @[lib.scala 88:36] - node _T_716 = and(_T_715, _T_583) @[lib.scala 88:41] - node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] - node _T_718 = bits(lsu_match_data_2, 19, 19) @[lib.scala 88:86] - node _T_719 = eq(_T_717, _T_718) @[lib.scala 88:78] - node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[lib.scala 88:23] - _T_580[19] <= _T_720 @[lib.scala 88:17] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] - node _T_722 = andr(_T_721) @[lib.scala 88:36] - node _T_723 = and(_T_722, _T_583) @[lib.scala 88:41] - node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] - node _T_725 = bits(lsu_match_data_2, 20, 20) @[lib.scala 88:86] - node _T_726 = eq(_T_724, _T_725) @[lib.scala 88:78] - node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[lib.scala 88:23] - _T_580[20] <= _T_727 @[lib.scala 88:17] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] - node _T_729 = andr(_T_728) @[lib.scala 88:36] - node _T_730 = and(_T_729, _T_583) @[lib.scala 88:41] - node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] - node _T_732 = bits(lsu_match_data_2, 21, 21) @[lib.scala 88:86] - node _T_733 = eq(_T_731, _T_732) @[lib.scala 88:78] - node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[lib.scala 88:23] - _T_580[21] <= _T_734 @[lib.scala 88:17] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] - node _T_736 = andr(_T_735) @[lib.scala 88:36] - node _T_737 = and(_T_736, _T_583) @[lib.scala 88:41] - node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] - node _T_739 = bits(lsu_match_data_2, 22, 22) @[lib.scala 88:86] - node _T_740 = eq(_T_738, _T_739) @[lib.scala 88:78] - node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[lib.scala 88:23] - _T_580[22] <= _T_741 @[lib.scala 88:17] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] - node _T_743 = andr(_T_742) @[lib.scala 88:36] - node _T_744 = and(_T_743, _T_583) @[lib.scala 88:41] - node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] - node _T_746 = bits(lsu_match_data_2, 23, 23) @[lib.scala 88:86] - node _T_747 = eq(_T_745, _T_746) @[lib.scala 88:78] - node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[lib.scala 88:23] - _T_580[23] <= _T_748 @[lib.scala 88:17] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] - node _T_750 = andr(_T_749) @[lib.scala 88:36] - node _T_751 = and(_T_750, _T_583) @[lib.scala 88:41] - node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] - node _T_753 = bits(lsu_match_data_2, 24, 24) @[lib.scala 88:86] - node _T_754 = eq(_T_752, _T_753) @[lib.scala 88:78] - node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[lib.scala 88:23] - _T_580[24] <= _T_755 @[lib.scala 88:17] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] - node _T_757 = andr(_T_756) @[lib.scala 88:36] - node _T_758 = and(_T_757, _T_583) @[lib.scala 88:41] - node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] - node _T_760 = bits(lsu_match_data_2, 25, 25) @[lib.scala 88:86] - node _T_761 = eq(_T_759, _T_760) @[lib.scala 88:78] - node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[lib.scala 88:23] - _T_580[25] <= _T_762 @[lib.scala 88:17] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] - node _T_764 = andr(_T_763) @[lib.scala 88:36] - node _T_765 = and(_T_764, _T_583) @[lib.scala 88:41] - node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] - node _T_767 = bits(lsu_match_data_2, 26, 26) @[lib.scala 88:86] - node _T_768 = eq(_T_766, _T_767) @[lib.scala 88:78] - node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[lib.scala 88:23] - _T_580[26] <= _T_769 @[lib.scala 88:17] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] - node _T_771 = andr(_T_770) @[lib.scala 88:36] - node _T_772 = and(_T_771, _T_583) @[lib.scala 88:41] - node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] - node _T_774 = bits(lsu_match_data_2, 27, 27) @[lib.scala 88:86] - node _T_775 = eq(_T_773, _T_774) @[lib.scala 88:78] - node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[lib.scala 88:23] - _T_580[27] <= _T_776 @[lib.scala 88:17] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] - node _T_778 = andr(_T_777) @[lib.scala 88:36] - node _T_779 = and(_T_778, _T_583) @[lib.scala 88:41] - node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] - node _T_781 = bits(lsu_match_data_2, 28, 28) @[lib.scala 88:86] - node _T_782 = eq(_T_780, _T_781) @[lib.scala 88:78] - node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[lib.scala 88:23] - _T_580[28] <= _T_783 @[lib.scala 88:17] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] - node _T_785 = andr(_T_784) @[lib.scala 88:36] - node _T_786 = and(_T_785, _T_583) @[lib.scala 88:41] - node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] - node _T_788 = bits(lsu_match_data_2, 29, 29) @[lib.scala 88:86] - node _T_789 = eq(_T_787, _T_788) @[lib.scala 88:78] - node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[lib.scala 88:23] - _T_580[29] <= _T_790 @[lib.scala 88:17] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] - node _T_792 = andr(_T_791) @[lib.scala 88:36] - node _T_793 = and(_T_792, _T_583) @[lib.scala 88:41] - node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] - node _T_795 = bits(lsu_match_data_2, 30, 30) @[lib.scala 88:86] - node _T_796 = eq(_T_794, _T_795) @[lib.scala 88:78] - node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[lib.scala 88:23] - _T_580[30] <= _T_797 @[lib.scala 88:17] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] - node _T_799 = andr(_T_798) @[lib.scala 88:36] - node _T_800 = and(_T_799, _T_583) @[lib.scala 88:41] - node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] - node _T_802 = bits(lsu_match_data_2, 31, 31) @[lib.scala 88:86] - node _T_803 = eq(_T_801, _T_802) @[lib.scala 88:78] - node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[lib.scala 88:23] - _T_580[31] <= _T_804 @[lib.scala 88:17] - node _T_805 = cat(_T_580[1], _T_580[0]) @[lib.scala 89:14] - node _T_806 = cat(_T_580[3], _T_580[2]) @[lib.scala 89:14] - node _T_807 = cat(_T_806, _T_805) @[lib.scala 89:14] - node _T_808 = cat(_T_580[5], _T_580[4]) @[lib.scala 89:14] - node _T_809 = cat(_T_580[7], _T_580[6]) @[lib.scala 89:14] - node _T_810 = cat(_T_809, _T_808) @[lib.scala 89:14] - node _T_811 = cat(_T_810, _T_807) @[lib.scala 89:14] - node _T_812 = cat(_T_580[9], _T_580[8]) @[lib.scala 89:14] - node _T_813 = cat(_T_580[11], _T_580[10]) @[lib.scala 89:14] - node _T_814 = cat(_T_813, _T_812) @[lib.scala 89:14] - node _T_815 = cat(_T_580[13], _T_580[12]) @[lib.scala 89:14] - node _T_816 = cat(_T_580[15], _T_580[14]) @[lib.scala 89:14] - node _T_817 = cat(_T_816, _T_815) @[lib.scala 89:14] - node _T_818 = cat(_T_817, _T_814) @[lib.scala 89:14] - node _T_819 = cat(_T_818, _T_811) @[lib.scala 89:14] - node _T_820 = cat(_T_580[17], _T_580[16]) @[lib.scala 89:14] - node _T_821 = cat(_T_580[19], _T_580[18]) @[lib.scala 89:14] - node _T_822 = cat(_T_821, _T_820) @[lib.scala 89:14] - node _T_823 = cat(_T_580[21], _T_580[20]) @[lib.scala 89:14] - node _T_824 = cat(_T_580[23], _T_580[22]) @[lib.scala 89:14] - node _T_825 = cat(_T_824, _T_823) @[lib.scala 89:14] - node _T_826 = cat(_T_825, _T_822) @[lib.scala 89:14] - node _T_827 = cat(_T_580[25], _T_580[24]) @[lib.scala 89:14] - node _T_828 = cat(_T_580[27], _T_580[26]) @[lib.scala 89:14] - node _T_829 = cat(_T_828, _T_827) @[lib.scala 89:14] - node _T_830 = cat(_T_580[29], _T_580[28]) @[lib.scala 89:14] - node _T_831 = cat(_T_580[31], _T_580[30]) @[lib.scala 89:14] - node _T_832 = cat(_T_831, _T_830) @[lib.scala 89:14] - node _T_833 = cat(_T_832, _T_829) @[lib.scala 89:14] - node _T_834 = cat(_T_833, _T_826) @[lib.scala 89:14] - node _T_835 = cat(_T_834, _T_819) @[lib.scala 89:14] - node _T_836 = and(_T_578, _T_835) @[lsu_trigger.scala 19:92] - node _T_837 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] - node _T_838 = and(io.lsu_pkt_m.valid, _T_837) @[lsu_trigger.scala 18:69] - node _T_839 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] - node _T_840 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] - node _T_841 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] - node _T_842 = and(_T_840, _T_841) @[lsu_trigger.scala 19:58] - node _T_843 = or(_T_839, _T_842) @[lsu_trigger.scala 18:152] - node _T_844 = and(_T_838, _T_843) @[lsu_trigger.scala 18:94] - node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_846 : UInt<1>[32] @[lib.scala 84:24] - node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] - node _T_848 = not(_T_847) @[lib.scala 85:39] - node _T_849 = and(_T_845, _T_848) @[lib.scala 85:37] - node _T_850 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] - node _T_851 = bits(lsu_match_data_3, 0, 0) @[lib.scala 86:60] - node _T_852 = eq(_T_850, _T_851) @[lib.scala 86:52] - node _T_853 = or(_T_849, _T_852) @[lib.scala 86:41] - _T_846[0] <= _T_853 @[lib.scala 86:18] - node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] - node _T_855 = andr(_T_854) @[lib.scala 88:36] - node _T_856 = and(_T_855, _T_849) @[lib.scala 88:41] - node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] - node _T_858 = bits(lsu_match_data_3, 1, 1) @[lib.scala 88:86] - node _T_859 = eq(_T_857, _T_858) @[lib.scala 88:78] - node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[lib.scala 88:23] - _T_846[1] <= _T_860 @[lib.scala 88:17] - node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] - node _T_862 = andr(_T_861) @[lib.scala 88:36] - node _T_863 = and(_T_862, _T_849) @[lib.scala 88:41] - node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] - node _T_865 = bits(lsu_match_data_3, 2, 2) @[lib.scala 88:86] - node _T_866 = eq(_T_864, _T_865) @[lib.scala 88:78] - node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[lib.scala 88:23] - _T_846[2] <= _T_867 @[lib.scala 88:17] - node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] - node _T_869 = andr(_T_868) @[lib.scala 88:36] - node _T_870 = and(_T_869, _T_849) @[lib.scala 88:41] - node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] - node _T_872 = bits(lsu_match_data_3, 3, 3) @[lib.scala 88:86] - node _T_873 = eq(_T_871, _T_872) @[lib.scala 88:78] - node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[lib.scala 88:23] - _T_846[3] <= _T_874 @[lib.scala 88:17] - node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] - node _T_876 = andr(_T_875) @[lib.scala 88:36] - node _T_877 = and(_T_876, _T_849) @[lib.scala 88:41] - node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] - node _T_879 = bits(lsu_match_data_3, 4, 4) @[lib.scala 88:86] - node _T_880 = eq(_T_878, _T_879) @[lib.scala 88:78] - node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[lib.scala 88:23] - _T_846[4] <= _T_881 @[lib.scala 88:17] - node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] - node _T_883 = andr(_T_882) @[lib.scala 88:36] - node _T_884 = and(_T_883, _T_849) @[lib.scala 88:41] - node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] - node _T_886 = bits(lsu_match_data_3, 5, 5) @[lib.scala 88:86] - node _T_887 = eq(_T_885, _T_886) @[lib.scala 88:78] - node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[lib.scala 88:23] - _T_846[5] <= _T_888 @[lib.scala 88:17] - node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] - node _T_890 = andr(_T_889) @[lib.scala 88:36] - node _T_891 = and(_T_890, _T_849) @[lib.scala 88:41] - node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] - node _T_893 = bits(lsu_match_data_3, 6, 6) @[lib.scala 88:86] - node _T_894 = eq(_T_892, _T_893) @[lib.scala 88:78] - node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[lib.scala 88:23] - _T_846[6] <= _T_895 @[lib.scala 88:17] - node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] - node _T_897 = andr(_T_896) @[lib.scala 88:36] - node _T_898 = and(_T_897, _T_849) @[lib.scala 88:41] - node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] - node _T_900 = bits(lsu_match_data_3, 7, 7) @[lib.scala 88:86] - node _T_901 = eq(_T_899, _T_900) @[lib.scala 88:78] - node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[lib.scala 88:23] - _T_846[7] <= _T_902 @[lib.scala 88:17] - node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] - node _T_904 = andr(_T_903) @[lib.scala 88:36] - node _T_905 = and(_T_904, _T_849) @[lib.scala 88:41] - node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] - node _T_907 = bits(lsu_match_data_3, 8, 8) @[lib.scala 88:86] - node _T_908 = eq(_T_906, _T_907) @[lib.scala 88:78] - node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[lib.scala 88:23] - _T_846[8] <= _T_909 @[lib.scala 88:17] - node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] - node _T_911 = andr(_T_910) @[lib.scala 88:36] - node _T_912 = and(_T_911, _T_849) @[lib.scala 88:41] - node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] - node _T_914 = bits(lsu_match_data_3, 9, 9) @[lib.scala 88:86] - node _T_915 = eq(_T_913, _T_914) @[lib.scala 88:78] - node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[lib.scala 88:23] - _T_846[9] <= _T_916 @[lib.scala 88:17] - node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] - node _T_918 = andr(_T_917) @[lib.scala 88:36] - node _T_919 = and(_T_918, _T_849) @[lib.scala 88:41] - node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] - node _T_921 = bits(lsu_match_data_3, 10, 10) @[lib.scala 88:86] - node _T_922 = eq(_T_920, _T_921) @[lib.scala 88:78] - node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[lib.scala 88:23] - _T_846[10] <= _T_923 @[lib.scala 88:17] - node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] - node _T_925 = andr(_T_924) @[lib.scala 88:36] - node _T_926 = and(_T_925, _T_849) @[lib.scala 88:41] - node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] - node _T_928 = bits(lsu_match_data_3, 11, 11) @[lib.scala 88:86] - node _T_929 = eq(_T_927, _T_928) @[lib.scala 88:78] - node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[lib.scala 88:23] - _T_846[11] <= _T_930 @[lib.scala 88:17] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] - node _T_932 = andr(_T_931) @[lib.scala 88:36] - node _T_933 = and(_T_932, _T_849) @[lib.scala 88:41] - node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] - node _T_935 = bits(lsu_match_data_3, 12, 12) @[lib.scala 88:86] - node _T_936 = eq(_T_934, _T_935) @[lib.scala 88:78] - node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[lib.scala 88:23] - _T_846[12] <= _T_937 @[lib.scala 88:17] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] - node _T_939 = andr(_T_938) @[lib.scala 88:36] - node _T_940 = and(_T_939, _T_849) @[lib.scala 88:41] - node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] - node _T_942 = bits(lsu_match_data_3, 13, 13) @[lib.scala 88:86] - node _T_943 = eq(_T_941, _T_942) @[lib.scala 88:78] - node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 88:23] - _T_846[13] <= _T_944 @[lib.scala 88:17] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] - node _T_946 = andr(_T_945) @[lib.scala 88:36] - node _T_947 = and(_T_946, _T_849) @[lib.scala 88:41] - node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] - node _T_949 = bits(lsu_match_data_3, 14, 14) @[lib.scala 88:86] - node _T_950 = eq(_T_948, _T_949) @[lib.scala 88:78] - node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 88:23] - _T_846[14] <= _T_951 @[lib.scala 88:17] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] - node _T_953 = andr(_T_952) @[lib.scala 88:36] - node _T_954 = and(_T_953, _T_849) @[lib.scala 88:41] - node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] - node _T_956 = bits(lsu_match_data_3, 15, 15) @[lib.scala 88:86] - node _T_957 = eq(_T_955, _T_956) @[lib.scala 88:78] - node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 88:23] - _T_846[15] <= _T_958 @[lib.scala 88:17] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] - node _T_960 = andr(_T_959) @[lib.scala 88:36] - node _T_961 = and(_T_960, _T_849) @[lib.scala 88:41] - node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] - node _T_963 = bits(lsu_match_data_3, 16, 16) @[lib.scala 88:86] - node _T_964 = eq(_T_962, _T_963) @[lib.scala 88:78] - node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 88:23] - _T_846[16] <= _T_965 @[lib.scala 88:17] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] - node _T_967 = andr(_T_966) @[lib.scala 88:36] - node _T_968 = and(_T_967, _T_849) @[lib.scala 88:41] - node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] - node _T_970 = bits(lsu_match_data_3, 17, 17) @[lib.scala 88:86] - node _T_971 = eq(_T_969, _T_970) @[lib.scala 88:78] - node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 88:23] - _T_846[17] <= _T_972 @[lib.scala 88:17] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] - node _T_974 = andr(_T_973) @[lib.scala 88:36] - node _T_975 = and(_T_974, _T_849) @[lib.scala 88:41] - node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] - node _T_977 = bits(lsu_match_data_3, 18, 18) @[lib.scala 88:86] - node _T_978 = eq(_T_976, _T_977) @[lib.scala 88:78] - node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 88:23] - _T_846[18] <= _T_979 @[lib.scala 88:17] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] - node _T_981 = andr(_T_980) @[lib.scala 88:36] - node _T_982 = and(_T_981, _T_849) @[lib.scala 88:41] - node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] - node _T_984 = bits(lsu_match_data_3, 19, 19) @[lib.scala 88:86] - node _T_985 = eq(_T_983, _T_984) @[lib.scala 88:78] - node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 88:23] - _T_846[19] <= _T_986 @[lib.scala 88:17] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] - node _T_988 = andr(_T_987) @[lib.scala 88:36] - node _T_989 = and(_T_988, _T_849) @[lib.scala 88:41] - node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] - node _T_991 = bits(lsu_match_data_3, 20, 20) @[lib.scala 88:86] - node _T_992 = eq(_T_990, _T_991) @[lib.scala 88:78] - node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 88:23] - _T_846[20] <= _T_993 @[lib.scala 88:17] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] - node _T_995 = andr(_T_994) @[lib.scala 88:36] - node _T_996 = and(_T_995, _T_849) @[lib.scala 88:41] - node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] - node _T_998 = bits(lsu_match_data_3, 21, 21) @[lib.scala 88:86] - node _T_999 = eq(_T_997, _T_998) @[lib.scala 88:78] - node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 88:23] - _T_846[21] <= _T_1000 @[lib.scala 88:17] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] - node _T_1002 = andr(_T_1001) @[lib.scala 88:36] - node _T_1003 = and(_T_1002, _T_849) @[lib.scala 88:41] - node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] - node _T_1005 = bits(lsu_match_data_3, 22, 22) @[lib.scala 88:86] - node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 88:78] - node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 88:23] - _T_846[22] <= _T_1007 @[lib.scala 88:17] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] - node _T_1009 = andr(_T_1008) @[lib.scala 88:36] - node _T_1010 = and(_T_1009, _T_849) @[lib.scala 88:41] - node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] - node _T_1012 = bits(lsu_match_data_3, 23, 23) @[lib.scala 88:86] - node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 88:78] - node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 88:23] - _T_846[23] <= _T_1014 @[lib.scala 88:17] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] - node _T_1016 = andr(_T_1015) @[lib.scala 88:36] - node _T_1017 = and(_T_1016, _T_849) @[lib.scala 88:41] - node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] - node _T_1019 = bits(lsu_match_data_3, 24, 24) @[lib.scala 88:86] - node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 88:78] - node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 88:23] - _T_846[24] <= _T_1021 @[lib.scala 88:17] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] - node _T_1023 = andr(_T_1022) @[lib.scala 88:36] - node _T_1024 = and(_T_1023, _T_849) @[lib.scala 88:41] - node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] - node _T_1026 = bits(lsu_match_data_3, 25, 25) @[lib.scala 88:86] - node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 88:78] - node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 88:23] - _T_846[25] <= _T_1028 @[lib.scala 88:17] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] - node _T_1030 = andr(_T_1029) @[lib.scala 88:36] - node _T_1031 = and(_T_1030, _T_849) @[lib.scala 88:41] - node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] - node _T_1033 = bits(lsu_match_data_3, 26, 26) @[lib.scala 88:86] - node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 88:78] - node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 88:23] - _T_846[26] <= _T_1035 @[lib.scala 88:17] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] - node _T_1037 = andr(_T_1036) @[lib.scala 88:36] - node _T_1038 = and(_T_1037, _T_849) @[lib.scala 88:41] - node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] - node _T_1040 = bits(lsu_match_data_3, 27, 27) @[lib.scala 88:86] - node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 88:78] - node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 88:23] - _T_846[27] <= _T_1042 @[lib.scala 88:17] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] - node _T_1044 = andr(_T_1043) @[lib.scala 88:36] - node _T_1045 = and(_T_1044, _T_849) @[lib.scala 88:41] - node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] - node _T_1047 = bits(lsu_match_data_3, 28, 28) @[lib.scala 88:86] - node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 88:78] - node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 88:23] - _T_846[28] <= _T_1049 @[lib.scala 88:17] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] - node _T_1051 = andr(_T_1050) @[lib.scala 88:36] - node _T_1052 = and(_T_1051, _T_849) @[lib.scala 88:41] - node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] - node _T_1054 = bits(lsu_match_data_3, 29, 29) @[lib.scala 88:86] - node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 88:78] - node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 88:23] - _T_846[29] <= _T_1056 @[lib.scala 88:17] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] - node _T_1058 = andr(_T_1057) @[lib.scala 88:36] - node _T_1059 = and(_T_1058, _T_849) @[lib.scala 88:41] - node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] - node _T_1061 = bits(lsu_match_data_3, 30, 30) @[lib.scala 88:86] - node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 88:78] - node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 88:23] - _T_846[30] <= _T_1063 @[lib.scala 88:17] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] - node _T_1065 = andr(_T_1064) @[lib.scala 88:36] - node _T_1066 = and(_T_1065, _T_849) @[lib.scala 88:41] - node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] - node _T_1068 = bits(lsu_match_data_3, 31, 31) @[lib.scala 88:86] - node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 88:78] - node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 88:23] - _T_846[31] <= _T_1070 @[lib.scala 88:17] - node _T_1071 = cat(_T_846[1], _T_846[0]) @[lib.scala 89:14] - node _T_1072 = cat(_T_846[3], _T_846[2]) @[lib.scala 89:14] - node _T_1073 = cat(_T_1072, _T_1071) @[lib.scala 89:14] - node _T_1074 = cat(_T_846[5], _T_846[4]) @[lib.scala 89:14] - node _T_1075 = cat(_T_846[7], _T_846[6]) @[lib.scala 89:14] + node _T_304 = andr(_T_303) @[lib.scala 89:25] + node _T_305 = and(_T_46, _T_304) @[lsu_trigger.scala 19:92] + node _T_306 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_307 = and(io.lsu_pkt_m.valid, _T_306) @[lsu_trigger.scala 18:69] + node _T_308 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_309 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_310 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_311 = and(_T_309, _T_310) @[lsu_trigger.scala 19:58] + node _T_312 = or(_T_308, _T_311) @[lsu_trigger.scala 18:152] + node _T_313 = and(_T_307, _T_312) @[lsu_trigger.scala 18:94] + node _T_314 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_315 : UInt<1>[32] @[lib.scala 84:24] + node _T_316 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 85:45] + node _T_317 = not(_T_316) @[lib.scala 85:39] + node _T_318 = and(_T_314, _T_317) @[lib.scala 85:37] + node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 86:48] + node _T_320 = bits(lsu_match_data_1, 0, 0) @[lib.scala 86:60] + node _T_321 = eq(_T_319, _T_320) @[lib.scala 86:52] + node _T_322 = or(_T_318, _T_321) @[lib.scala 86:41] + _T_315[0] <= _T_322 @[lib.scala 86:18] + node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 88:28] + node _T_324 = andr(_T_323) @[lib.scala 88:36] + node _T_325 = and(_T_324, _T_318) @[lib.scala 88:41] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 88:74] + node _T_327 = bits(lsu_match_data_1, 1, 1) @[lib.scala 88:86] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 88:78] + node _T_329 = mux(_T_325, UInt<1>("h01"), _T_328) @[lib.scala 88:23] + _T_315[1] <= _T_329 @[lib.scala 88:17] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 88:28] + node _T_331 = andr(_T_330) @[lib.scala 88:36] + node _T_332 = and(_T_331, _T_318) @[lib.scala 88:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 88:74] + node _T_334 = bits(lsu_match_data_1, 2, 2) @[lib.scala 88:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 88:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 88:23] + _T_315[2] <= _T_336 @[lib.scala 88:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 88:28] + node _T_338 = andr(_T_337) @[lib.scala 88:36] + node _T_339 = and(_T_338, _T_318) @[lib.scala 88:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 88:74] + node _T_341 = bits(lsu_match_data_1, 3, 3) @[lib.scala 88:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 88:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 88:23] + _T_315[3] <= _T_343 @[lib.scala 88:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 88:28] + node _T_345 = andr(_T_344) @[lib.scala 88:36] + node _T_346 = and(_T_345, _T_318) @[lib.scala 88:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 88:74] + node _T_348 = bits(lsu_match_data_1, 4, 4) @[lib.scala 88:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 88:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 88:23] + _T_315[4] <= _T_350 @[lib.scala 88:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 88:28] + node _T_352 = andr(_T_351) @[lib.scala 88:36] + node _T_353 = and(_T_352, _T_318) @[lib.scala 88:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 88:74] + node _T_355 = bits(lsu_match_data_1, 5, 5) @[lib.scala 88:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 88:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 88:23] + _T_315[5] <= _T_357 @[lib.scala 88:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 88:28] + node _T_359 = andr(_T_358) @[lib.scala 88:36] + node _T_360 = and(_T_359, _T_318) @[lib.scala 88:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 88:74] + node _T_362 = bits(lsu_match_data_1, 6, 6) @[lib.scala 88:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 88:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 88:23] + _T_315[6] <= _T_364 @[lib.scala 88:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 88:28] + node _T_366 = andr(_T_365) @[lib.scala 88:36] + node _T_367 = and(_T_366, _T_318) @[lib.scala 88:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 88:74] + node _T_369 = bits(lsu_match_data_1, 7, 7) @[lib.scala 88:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 88:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 88:23] + _T_315[7] <= _T_371 @[lib.scala 88:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 88:28] + node _T_373 = andr(_T_372) @[lib.scala 88:36] + node _T_374 = and(_T_373, _T_318) @[lib.scala 88:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 88:74] + node _T_376 = bits(lsu_match_data_1, 8, 8) @[lib.scala 88:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 88:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 88:23] + _T_315[8] <= _T_378 @[lib.scala 88:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 88:28] + node _T_380 = andr(_T_379) @[lib.scala 88:36] + node _T_381 = and(_T_380, _T_318) @[lib.scala 88:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 88:74] + node _T_383 = bits(lsu_match_data_1, 9, 9) @[lib.scala 88:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 88:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 88:23] + _T_315[9] <= _T_385 @[lib.scala 88:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 88:28] + node _T_387 = andr(_T_386) @[lib.scala 88:36] + node _T_388 = and(_T_387, _T_318) @[lib.scala 88:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 88:74] + node _T_390 = bits(lsu_match_data_1, 10, 10) @[lib.scala 88:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 88:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 88:23] + _T_315[10] <= _T_392 @[lib.scala 88:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 88:28] + node _T_394 = andr(_T_393) @[lib.scala 88:36] + node _T_395 = and(_T_394, _T_318) @[lib.scala 88:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 88:74] + node _T_397 = bits(lsu_match_data_1, 11, 11) @[lib.scala 88:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 88:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 88:23] + _T_315[11] <= _T_399 @[lib.scala 88:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 88:28] + node _T_401 = andr(_T_400) @[lib.scala 88:36] + node _T_402 = and(_T_401, _T_318) @[lib.scala 88:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 88:74] + node _T_404 = bits(lsu_match_data_1, 12, 12) @[lib.scala 88:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 88:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 88:23] + _T_315[12] <= _T_406 @[lib.scala 88:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 88:28] + node _T_408 = andr(_T_407) @[lib.scala 88:36] + node _T_409 = and(_T_408, _T_318) @[lib.scala 88:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 88:74] + node _T_411 = bits(lsu_match_data_1, 13, 13) @[lib.scala 88:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 88:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 88:23] + _T_315[13] <= _T_413 @[lib.scala 88:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 88:28] + node _T_415 = andr(_T_414) @[lib.scala 88:36] + node _T_416 = and(_T_415, _T_318) @[lib.scala 88:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 88:74] + node _T_418 = bits(lsu_match_data_1, 14, 14) @[lib.scala 88:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 88:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 88:23] + _T_315[14] <= _T_420 @[lib.scala 88:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 88:28] + node _T_422 = andr(_T_421) @[lib.scala 88:36] + node _T_423 = and(_T_422, _T_318) @[lib.scala 88:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 88:74] + node _T_425 = bits(lsu_match_data_1, 15, 15) @[lib.scala 88:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 88:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 88:23] + _T_315[15] <= _T_427 @[lib.scala 88:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 88:28] + node _T_429 = andr(_T_428) @[lib.scala 88:36] + node _T_430 = and(_T_429, _T_318) @[lib.scala 88:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 88:74] + node _T_432 = bits(lsu_match_data_1, 16, 16) @[lib.scala 88:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 88:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 88:23] + _T_315[16] <= _T_434 @[lib.scala 88:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 88:28] + node _T_436 = andr(_T_435) @[lib.scala 88:36] + node _T_437 = and(_T_436, _T_318) @[lib.scala 88:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 88:74] + node _T_439 = bits(lsu_match_data_1, 17, 17) @[lib.scala 88:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 88:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 88:23] + _T_315[17] <= _T_441 @[lib.scala 88:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 88:28] + node _T_443 = andr(_T_442) @[lib.scala 88:36] + node _T_444 = and(_T_443, _T_318) @[lib.scala 88:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 88:74] + node _T_446 = bits(lsu_match_data_1, 18, 18) @[lib.scala 88:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 88:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 88:23] + _T_315[18] <= _T_448 @[lib.scala 88:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 88:28] + node _T_450 = andr(_T_449) @[lib.scala 88:36] + node _T_451 = and(_T_450, _T_318) @[lib.scala 88:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 88:74] + node _T_453 = bits(lsu_match_data_1, 19, 19) @[lib.scala 88:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 88:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 88:23] + _T_315[19] <= _T_455 @[lib.scala 88:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 88:28] + node _T_457 = andr(_T_456) @[lib.scala 88:36] + node _T_458 = and(_T_457, _T_318) @[lib.scala 88:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 88:74] + node _T_460 = bits(lsu_match_data_1, 20, 20) @[lib.scala 88:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 88:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 88:23] + _T_315[20] <= _T_462 @[lib.scala 88:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 88:28] + node _T_464 = andr(_T_463) @[lib.scala 88:36] + node _T_465 = and(_T_464, _T_318) @[lib.scala 88:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 88:74] + node _T_467 = bits(lsu_match_data_1, 21, 21) @[lib.scala 88:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 88:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 88:23] + _T_315[21] <= _T_469 @[lib.scala 88:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 88:28] + node _T_471 = andr(_T_470) @[lib.scala 88:36] + node _T_472 = and(_T_471, _T_318) @[lib.scala 88:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 88:74] + node _T_474 = bits(lsu_match_data_1, 22, 22) @[lib.scala 88:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 88:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 88:23] + _T_315[22] <= _T_476 @[lib.scala 88:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 88:28] + node _T_478 = andr(_T_477) @[lib.scala 88:36] + node _T_479 = and(_T_478, _T_318) @[lib.scala 88:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 88:74] + node _T_481 = bits(lsu_match_data_1, 23, 23) @[lib.scala 88:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 88:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 88:23] + _T_315[23] <= _T_483 @[lib.scala 88:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 88:28] + node _T_485 = andr(_T_484) @[lib.scala 88:36] + node _T_486 = and(_T_485, _T_318) @[lib.scala 88:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 88:74] + node _T_488 = bits(lsu_match_data_1, 24, 24) @[lib.scala 88:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 88:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 88:23] + _T_315[24] <= _T_490 @[lib.scala 88:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 88:28] + node _T_492 = andr(_T_491) @[lib.scala 88:36] + node _T_493 = and(_T_492, _T_318) @[lib.scala 88:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 88:74] + node _T_495 = bits(lsu_match_data_1, 25, 25) @[lib.scala 88:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 88:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 88:23] + _T_315[25] <= _T_497 @[lib.scala 88:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 88:28] + node _T_499 = andr(_T_498) @[lib.scala 88:36] + node _T_500 = and(_T_499, _T_318) @[lib.scala 88:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 88:74] + node _T_502 = bits(lsu_match_data_1, 26, 26) @[lib.scala 88:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 88:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 88:23] + _T_315[26] <= _T_504 @[lib.scala 88:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 88:28] + node _T_506 = andr(_T_505) @[lib.scala 88:36] + node _T_507 = and(_T_506, _T_318) @[lib.scala 88:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 88:74] + node _T_509 = bits(lsu_match_data_1, 27, 27) @[lib.scala 88:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 88:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 88:23] + _T_315[27] <= _T_511 @[lib.scala 88:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 88:28] + node _T_513 = andr(_T_512) @[lib.scala 88:36] + node _T_514 = and(_T_513, _T_318) @[lib.scala 88:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 88:74] + node _T_516 = bits(lsu_match_data_1, 28, 28) @[lib.scala 88:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 88:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 88:23] + _T_315[28] <= _T_518 @[lib.scala 88:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 88:28] + node _T_520 = andr(_T_519) @[lib.scala 88:36] + node _T_521 = and(_T_520, _T_318) @[lib.scala 88:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 88:74] + node _T_523 = bits(lsu_match_data_1, 29, 29) @[lib.scala 88:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 88:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 88:23] + _T_315[29] <= _T_525 @[lib.scala 88:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 88:28] + node _T_527 = andr(_T_526) @[lib.scala 88:36] + node _T_528 = and(_T_527, _T_318) @[lib.scala 88:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 88:74] + node _T_530 = bits(lsu_match_data_1, 30, 30) @[lib.scala 88:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 88:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 88:23] + _T_315[30] <= _T_532 @[lib.scala 88:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 88:28] + node _T_534 = andr(_T_533) @[lib.scala 88:36] + node _T_535 = and(_T_534, _T_318) @[lib.scala 88:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 88:74] + node _T_537 = bits(lsu_match_data_1, 31, 31) @[lib.scala 88:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 88:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 88:23] + _T_315[31] <= _T_539 @[lib.scala 88:17] + node _T_540 = cat(_T_315[1], _T_315[0]) @[lib.scala 89:14] + node _T_541 = cat(_T_315[3], _T_315[2]) @[lib.scala 89:14] + node _T_542 = cat(_T_541, _T_540) @[lib.scala 89:14] + node _T_543 = cat(_T_315[5], _T_315[4]) @[lib.scala 89:14] + node _T_544 = cat(_T_315[7], _T_315[6]) @[lib.scala 89:14] + node _T_545 = cat(_T_544, _T_543) @[lib.scala 89:14] + node _T_546 = cat(_T_545, _T_542) @[lib.scala 89:14] + node _T_547 = cat(_T_315[9], _T_315[8]) @[lib.scala 89:14] + node _T_548 = cat(_T_315[11], _T_315[10]) @[lib.scala 89:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 89:14] + node _T_550 = cat(_T_315[13], _T_315[12]) @[lib.scala 89:14] + node _T_551 = cat(_T_315[15], _T_315[14]) @[lib.scala 89:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 89:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 89:14] + node _T_554 = cat(_T_553, _T_546) @[lib.scala 89:14] + node _T_555 = cat(_T_315[17], _T_315[16]) @[lib.scala 89:14] + node _T_556 = cat(_T_315[19], _T_315[18]) @[lib.scala 89:14] + node _T_557 = cat(_T_556, _T_555) @[lib.scala 89:14] + node _T_558 = cat(_T_315[21], _T_315[20]) @[lib.scala 89:14] + node _T_559 = cat(_T_315[23], _T_315[22]) @[lib.scala 89:14] + node _T_560 = cat(_T_559, _T_558) @[lib.scala 89:14] + node _T_561 = cat(_T_560, _T_557) @[lib.scala 89:14] + node _T_562 = cat(_T_315[25], _T_315[24]) @[lib.scala 89:14] + node _T_563 = cat(_T_315[27], _T_315[26]) @[lib.scala 89:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 89:14] + node _T_565 = cat(_T_315[29], _T_315[28]) @[lib.scala 89:14] + node _T_566 = cat(_T_315[31], _T_315[30]) @[lib.scala 89:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 89:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 89:14] + node _T_569 = cat(_T_568, _T_561) @[lib.scala 89:14] + node _T_570 = cat(_T_569, _T_554) @[lib.scala 89:14] + node _T_571 = andr(_T_570) @[lib.scala 89:25] + node _T_572 = and(_T_313, _T_571) @[lsu_trigger.scala 19:92] + node _T_573 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_574 = and(io.lsu_pkt_m.valid, _T_573) @[lsu_trigger.scala 18:69] + node _T_575 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_576 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_577 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_578 = and(_T_576, _T_577) @[lsu_trigger.scala 19:58] + node _T_579 = or(_T_575, _T_578) @[lsu_trigger.scala 18:152] + node _T_580 = and(_T_574, _T_579) @[lsu_trigger.scala 18:94] + node _T_581 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_582 : UInt<1>[32] @[lib.scala 84:24] + node _T_583 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 85:45] + node _T_584 = not(_T_583) @[lib.scala 85:39] + node _T_585 = and(_T_581, _T_584) @[lib.scala 85:37] + node _T_586 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 86:48] + node _T_587 = bits(lsu_match_data_2, 0, 0) @[lib.scala 86:60] + node _T_588 = eq(_T_586, _T_587) @[lib.scala 86:52] + node _T_589 = or(_T_585, _T_588) @[lib.scala 86:41] + _T_582[0] <= _T_589 @[lib.scala 86:18] + node _T_590 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 88:28] + node _T_591 = andr(_T_590) @[lib.scala 88:36] + node _T_592 = and(_T_591, _T_585) @[lib.scala 88:41] + node _T_593 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 88:74] + node _T_594 = bits(lsu_match_data_2, 1, 1) @[lib.scala 88:86] + node _T_595 = eq(_T_593, _T_594) @[lib.scala 88:78] + node _T_596 = mux(_T_592, UInt<1>("h01"), _T_595) @[lib.scala 88:23] + _T_582[1] <= _T_596 @[lib.scala 88:17] + node _T_597 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 88:28] + node _T_598 = andr(_T_597) @[lib.scala 88:36] + node _T_599 = and(_T_598, _T_585) @[lib.scala 88:41] + node _T_600 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 88:74] + node _T_601 = bits(lsu_match_data_2, 2, 2) @[lib.scala 88:86] + node _T_602 = eq(_T_600, _T_601) @[lib.scala 88:78] + node _T_603 = mux(_T_599, UInt<1>("h01"), _T_602) @[lib.scala 88:23] + _T_582[2] <= _T_603 @[lib.scala 88:17] + node _T_604 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 88:28] + node _T_605 = andr(_T_604) @[lib.scala 88:36] + node _T_606 = and(_T_605, _T_585) @[lib.scala 88:41] + node _T_607 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 88:74] + node _T_608 = bits(lsu_match_data_2, 3, 3) @[lib.scala 88:86] + node _T_609 = eq(_T_607, _T_608) @[lib.scala 88:78] + node _T_610 = mux(_T_606, UInt<1>("h01"), _T_609) @[lib.scala 88:23] + _T_582[3] <= _T_610 @[lib.scala 88:17] + node _T_611 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 88:28] + node _T_612 = andr(_T_611) @[lib.scala 88:36] + node _T_613 = and(_T_612, _T_585) @[lib.scala 88:41] + node _T_614 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 88:74] + node _T_615 = bits(lsu_match_data_2, 4, 4) @[lib.scala 88:86] + node _T_616 = eq(_T_614, _T_615) @[lib.scala 88:78] + node _T_617 = mux(_T_613, UInt<1>("h01"), _T_616) @[lib.scala 88:23] + _T_582[4] <= _T_617 @[lib.scala 88:17] + node _T_618 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 88:28] + node _T_619 = andr(_T_618) @[lib.scala 88:36] + node _T_620 = and(_T_619, _T_585) @[lib.scala 88:41] + node _T_621 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 88:74] + node _T_622 = bits(lsu_match_data_2, 5, 5) @[lib.scala 88:86] + node _T_623 = eq(_T_621, _T_622) @[lib.scala 88:78] + node _T_624 = mux(_T_620, UInt<1>("h01"), _T_623) @[lib.scala 88:23] + _T_582[5] <= _T_624 @[lib.scala 88:17] + node _T_625 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 88:28] + node _T_626 = andr(_T_625) @[lib.scala 88:36] + node _T_627 = and(_T_626, _T_585) @[lib.scala 88:41] + node _T_628 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 88:74] + node _T_629 = bits(lsu_match_data_2, 6, 6) @[lib.scala 88:86] + node _T_630 = eq(_T_628, _T_629) @[lib.scala 88:78] + node _T_631 = mux(_T_627, UInt<1>("h01"), _T_630) @[lib.scala 88:23] + _T_582[6] <= _T_631 @[lib.scala 88:17] + node _T_632 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 88:28] + node _T_633 = andr(_T_632) @[lib.scala 88:36] + node _T_634 = and(_T_633, _T_585) @[lib.scala 88:41] + node _T_635 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 88:74] + node _T_636 = bits(lsu_match_data_2, 7, 7) @[lib.scala 88:86] + node _T_637 = eq(_T_635, _T_636) @[lib.scala 88:78] + node _T_638 = mux(_T_634, UInt<1>("h01"), _T_637) @[lib.scala 88:23] + _T_582[7] <= _T_638 @[lib.scala 88:17] + node _T_639 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 88:28] + node _T_640 = andr(_T_639) @[lib.scala 88:36] + node _T_641 = and(_T_640, _T_585) @[lib.scala 88:41] + node _T_642 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 88:74] + node _T_643 = bits(lsu_match_data_2, 8, 8) @[lib.scala 88:86] + node _T_644 = eq(_T_642, _T_643) @[lib.scala 88:78] + node _T_645 = mux(_T_641, UInt<1>("h01"), _T_644) @[lib.scala 88:23] + _T_582[8] <= _T_645 @[lib.scala 88:17] + node _T_646 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 88:28] + node _T_647 = andr(_T_646) @[lib.scala 88:36] + node _T_648 = and(_T_647, _T_585) @[lib.scala 88:41] + node _T_649 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 88:74] + node _T_650 = bits(lsu_match_data_2, 9, 9) @[lib.scala 88:86] + node _T_651 = eq(_T_649, _T_650) @[lib.scala 88:78] + node _T_652 = mux(_T_648, UInt<1>("h01"), _T_651) @[lib.scala 88:23] + _T_582[9] <= _T_652 @[lib.scala 88:17] + node _T_653 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 88:28] + node _T_654 = andr(_T_653) @[lib.scala 88:36] + node _T_655 = and(_T_654, _T_585) @[lib.scala 88:41] + node _T_656 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 88:74] + node _T_657 = bits(lsu_match_data_2, 10, 10) @[lib.scala 88:86] + node _T_658 = eq(_T_656, _T_657) @[lib.scala 88:78] + node _T_659 = mux(_T_655, UInt<1>("h01"), _T_658) @[lib.scala 88:23] + _T_582[10] <= _T_659 @[lib.scala 88:17] + node _T_660 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 88:28] + node _T_661 = andr(_T_660) @[lib.scala 88:36] + node _T_662 = and(_T_661, _T_585) @[lib.scala 88:41] + node _T_663 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 88:74] + node _T_664 = bits(lsu_match_data_2, 11, 11) @[lib.scala 88:86] + node _T_665 = eq(_T_663, _T_664) @[lib.scala 88:78] + node _T_666 = mux(_T_662, UInt<1>("h01"), _T_665) @[lib.scala 88:23] + _T_582[11] <= _T_666 @[lib.scala 88:17] + node _T_667 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 88:28] + node _T_668 = andr(_T_667) @[lib.scala 88:36] + node _T_669 = and(_T_668, _T_585) @[lib.scala 88:41] + node _T_670 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 88:74] + node _T_671 = bits(lsu_match_data_2, 12, 12) @[lib.scala 88:86] + node _T_672 = eq(_T_670, _T_671) @[lib.scala 88:78] + node _T_673 = mux(_T_669, UInt<1>("h01"), _T_672) @[lib.scala 88:23] + _T_582[12] <= _T_673 @[lib.scala 88:17] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 88:28] + node _T_675 = andr(_T_674) @[lib.scala 88:36] + node _T_676 = and(_T_675, _T_585) @[lib.scala 88:41] + node _T_677 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 88:74] + node _T_678 = bits(lsu_match_data_2, 13, 13) @[lib.scala 88:86] + node _T_679 = eq(_T_677, _T_678) @[lib.scala 88:78] + node _T_680 = mux(_T_676, UInt<1>("h01"), _T_679) @[lib.scala 88:23] + _T_582[13] <= _T_680 @[lib.scala 88:17] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 88:28] + node _T_682 = andr(_T_681) @[lib.scala 88:36] + node _T_683 = and(_T_682, _T_585) @[lib.scala 88:41] + node _T_684 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 88:74] + node _T_685 = bits(lsu_match_data_2, 14, 14) @[lib.scala 88:86] + node _T_686 = eq(_T_684, _T_685) @[lib.scala 88:78] + node _T_687 = mux(_T_683, UInt<1>("h01"), _T_686) @[lib.scala 88:23] + _T_582[14] <= _T_687 @[lib.scala 88:17] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 88:28] + node _T_689 = andr(_T_688) @[lib.scala 88:36] + node _T_690 = and(_T_689, _T_585) @[lib.scala 88:41] + node _T_691 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 88:74] + node _T_692 = bits(lsu_match_data_2, 15, 15) @[lib.scala 88:86] + node _T_693 = eq(_T_691, _T_692) @[lib.scala 88:78] + node _T_694 = mux(_T_690, UInt<1>("h01"), _T_693) @[lib.scala 88:23] + _T_582[15] <= _T_694 @[lib.scala 88:17] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 88:28] + node _T_696 = andr(_T_695) @[lib.scala 88:36] + node _T_697 = and(_T_696, _T_585) @[lib.scala 88:41] + node _T_698 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 88:74] + node _T_699 = bits(lsu_match_data_2, 16, 16) @[lib.scala 88:86] + node _T_700 = eq(_T_698, _T_699) @[lib.scala 88:78] + node _T_701 = mux(_T_697, UInt<1>("h01"), _T_700) @[lib.scala 88:23] + _T_582[16] <= _T_701 @[lib.scala 88:17] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 88:28] + node _T_703 = andr(_T_702) @[lib.scala 88:36] + node _T_704 = and(_T_703, _T_585) @[lib.scala 88:41] + node _T_705 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 88:74] + node _T_706 = bits(lsu_match_data_2, 17, 17) @[lib.scala 88:86] + node _T_707 = eq(_T_705, _T_706) @[lib.scala 88:78] + node _T_708 = mux(_T_704, UInt<1>("h01"), _T_707) @[lib.scala 88:23] + _T_582[17] <= _T_708 @[lib.scala 88:17] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 88:28] + node _T_710 = andr(_T_709) @[lib.scala 88:36] + node _T_711 = and(_T_710, _T_585) @[lib.scala 88:41] + node _T_712 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 88:74] + node _T_713 = bits(lsu_match_data_2, 18, 18) @[lib.scala 88:86] + node _T_714 = eq(_T_712, _T_713) @[lib.scala 88:78] + node _T_715 = mux(_T_711, UInt<1>("h01"), _T_714) @[lib.scala 88:23] + _T_582[18] <= _T_715 @[lib.scala 88:17] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 88:28] + node _T_717 = andr(_T_716) @[lib.scala 88:36] + node _T_718 = and(_T_717, _T_585) @[lib.scala 88:41] + node _T_719 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 88:74] + node _T_720 = bits(lsu_match_data_2, 19, 19) @[lib.scala 88:86] + node _T_721 = eq(_T_719, _T_720) @[lib.scala 88:78] + node _T_722 = mux(_T_718, UInt<1>("h01"), _T_721) @[lib.scala 88:23] + _T_582[19] <= _T_722 @[lib.scala 88:17] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 88:28] + node _T_724 = andr(_T_723) @[lib.scala 88:36] + node _T_725 = and(_T_724, _T_585) @[lib.scala 88:41] + node _T_726 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 88:74] + node _T_727 = bits(lsu_match_data_2, 20, 20) @[lib.scala 88:86] + node _T_728 = eq(_T_726, _T_727) @[lib.scala 88:78] + node _T_729 = mux(_T_725, UInt<1>("h01"), _T_728) @[lib.scala 88:23] + _T_582[20] <= _T_729 @[lib.scala 88:17] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 88:28] + node _T_731 = andr(_T_730) @[lib.scala 88:36] + node _T_732 = and(_T_731, _T_585) @[lib.scala 88:41] + node _T_733 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 88:74] + node _T_734 = bits(lsu_match_data_2, 21, 21) @[lib.scala 88:86] + node _T_735 = eq(_T_733, _T_734) @[lib.scala 88:78] + node _T_736 = mux(_T_732, UInt<1>("h01"), _T_735) @[lib.scala 88:23] + _T_582[21] <= _T_736 @[lib.scala 88:17] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 88:28] + node _T_738 = andr(_T_737) @[lib.scala 88:36] + node _T_739 = and(_T_738, _T_585) @[lib.scala 88:41] + node _T_740 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 88:74] + node _T_741 = bits(lsu_match_data_2, 22, 22) @[lib.scala 88:86] + node _T_742 = eq(_T_740, _T_741) @[lib.scala 88:78] + node _T_743 = mux(_T_739, UInt<1>("h01"), _T_742) @[lib.scala 88:23] + _T_582[22] <= _T_743 @[lib.scala 88:17] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 88:28] + node _T_745 = andr(_T_744) @[lib.scala 88:36] + node _T_746 = and(_T_745, _T_585) @[lib.scala 88:41] + node _T_747 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 88:74] + node _T_748 = bits(lsu_match_data_2, 23, 23) @[lib.scala 88:86] + node _T_749 = eq(_T_747, _T_748) @[lib.scala 88:78] + node _T_750 = mux(_T_746, UInt<1>("h01"), _T_749) @[lib.scala 88:23] + _T_582[23] <= _T_750 @[lib.scala 88:17] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 88:28] + node _T_752 = andr(_T_751) @[lib.scala 88:36] + node _T_753 = and(_T_752, _T_585) @[lib.scala 88:41] + node _T_754 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 88:74] + node _T_755 = bits(lsu_match_data_2, 24, 24) @[lib.scala 88:86] + node _T_756 = eq(_T_754, _T_755) @[lib.scala 88:78] + node _T_757 = mux(_T_753, UInt<1>("h01"), _T_756) @[lib.scala 88:23] + _T_582[24] <= _T_757 @[lib.scala 88:17] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 88:28] + node _T_759 = andr(_T_758) @[lib.scala 88:36] + node _T_760 = and(_T_759, _T_585) @[lib.scala 88:41] + node _T_761 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 88:74] + node _T_762 = bits(lsu_match_data_2, 25, 25) @[lib.scala 88:86] + node _T_763 = eq(_T_761, _T_762) @[lib.scala 88:78] + node _T_764 = mux(_T_760, UInt<1>("h01"), _T_763) @[lib.scala 88:23] + _T_582[25] <= _T_764 @[lib.scala 88:17] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 88:28] + node _T_766 = andr(_T_765) @[lib.scala 88:36] + node _T_767 = and(_T_766, _T_585) @[lib.scala 88:41] + node _T_768 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 88:74] + node _T_769 = bits(lsu_match_data_2, 26, 26) @[lib.scala 88:86] + node _T_770 = eq(_T_768, _T_769) @[lib.scala 88:78] + node _T_771 = mux(_T_767, UInt<1>("h01"), _T_770) @[lib.scala 88:23] + _T_582[26] <= _T_771 @[lib.scala 88:17] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 88:28] + node _T_773 = andr(_T_772) @[lib.scala 88:36] + node _T_774 = and(_T_773, _T_585) @[lib.scala 88:41] + node _T_775 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 88:74] + node _T_776 = bits(lsu_match_data_2, 27, 27) @[lib.scala 88:86] + node _T_777 = eq(_T_775, _T_776) @[lib.scala 88:78] + node _T_778 = mux(_T_774, UInt<1>("h01"), _T_777) @[lib.scala 88:23] + _T_582[27] <= _T_778 @[lib.scala 88:17] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 88:28] + node _T_780 = andr(_T_779) @[lib.scala 88:36] + node _T_781 = and(_T_780, _T_585) @[lib.scala 88:41] + node _T_782 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 88:74] + node _T_783 = bits(lsu_match_data_2, 28, 28) @[lib.scala 88:86] + node _T_784 = eq(_T_782, _T_783) @[lib.scala 88:78] + node _T_785 = mux(_T_781, UInt<1>("h01"), _T_784) @[lib.scala 88:23] + _T_582[28] <= _T_785 @[lib.scala 88:17] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 88:28] + node _T_787 = andr(_T_786) @[lib.scala 88:36] + node _T_788 = and(_T_787, _T_585) @[lib.scala 88:41] + node _T_789 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 88:74] + node _T_790 = bits(lsu_match_data_2, 29, 29) @[lib.scala 88:86] + node _T_791 = eq(_T_789, _T_790) @[lib.scala 88:78] + node _T_792 = mux(_T_788, UInt<1>("h01"), _T_791) @[lib.scala 88:23] + _T_582[29] <= _T_792 @[lib.scala 88:17] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 88:28] + node _T_794 = andr(_T_793) @[lib.scala 88:36] + node _T_795 = and(_T_794, _T_585) @[lib.scala 88:41] + node _T_796 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 88:74] + node _T_797 = bits(lsu_match_data_2, 30, 30) @[lib.scala 88:86] + node _T_798 = eq(_T_796, _T_797) @[lib.scala 88:78] + node _T_799 = mux(_T_795, UInt<1>("h01"), _T_798) @[lib.scala 88:23] + _T_582[30] <= _T_799 @[lib.scala 88:17] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 88:28] + node _T_801 = andr(_T_800) @[lib.scala 88:36] + node _T_802 = and(_T_801, _T_585) @[lib.scala 88:41] + node _T_803 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 88:74] + node _T_804 = bits(lsu_match_data_2, 31, 31) @[lib.scala 88:86] + node _T_805 = eq(_T_803, _T_804) @[lib.scala 88:78] + node _T_806 = mux(_T_802, UInt<1>("h01"), _T_805) @[lib.scala 88:23] + _T_582[31] <= _T_806 @[lib.scala 88:17] + node _T_807 = cat(_T_582[1], _T_582[0]) @[lib.scala 89:14] + node _T_808 = cat(_T_582[3], _T_582[2]) @[lib.scala 89:14] + node _T_809 = cat(_T_808, _T_807) @[lib.scala 89:14] + node _T_810 = cat(_T_582[5], _T_582[4]) @[lib.scala 89:14] + node _T_811 = cat(_T_582[7], _T_582[6]) @[lib.scala 89:14] + node _T_812 = cat(_T_811, _T_810) @[lib.scala 89:14] + node _T_813 = cat(_T_812, _T_809) @[lib.scala 89:14] + node _T_814 = cat(_T_582[9], _T_582[8]) @[lib.scala 89:14] + node _T_815 = cat(_T_582[11], _T_582[10]) @[lib.scala 89:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 89:14] + node _T_817 = cat(_T_582[13], _T_582[12]) @[lib.scala 89:14] + node _T_818 = cat(_T_582[15], _T_582[14]) @[lib.scala 89:14] + node _T_819 = cat(_T_818, _T_817) @[lib.scala 89:14] + node _T_820 = cat(_T_819, _T_816) @[lib.scala 89:14] + node _T_821 = cat(_T_820, _T_813) @[lib.scala 89:14] + node _T_822 = cat(_T_582[17], _T_582[16]) @[lib.scala 89:14] + node _T_823 = cat(_T_582[19], _T_582[18]) @[lib.scala 89:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 89:14] + node _T_825 = cat(_T_582[21], _T_582[20]) @[lib.scala 89:14] + node _T_826 = cat(_T_582[23], _T_582[22]) @[lib.scala 89:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 89:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 89:14] + node _T_829 = cat(_T_582[25], _T_582[24]) @[lib.scala 89:14] + node _T_830 = cat(_T_582[27], _T_582[26]) @[lib.scala 89:14] + node _T_831 = cat(_T_830, _T_829) @[lib.scala 89:14] + node _T_832 = cat(_T_582[29], _T_582[28]) @[lib.scala 89:14] + node _T_833 = cat(_T_582[31], _T_582[30]) @[lib.scala 89:14] + node _T_834 = cat(_T_833, _T_832) @[lib.scala 89:14] + node _T_835 = cat(_T_834, _T_831) @[lib.scala 89:14] + node _T_836 = cat(_T_835, _T_828) @[lib.scala 89:14] + node _T_837 = cat(_T_836, _T_821) @[lib.scala 89:14] + node _T_838 = andr(_T_837) @[lib.scala 89:25] + node _T_839 = and(_T_580, _T_838) @[lsu_trigger.scala 19:92] + node _T_840 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] + node _T_841 = and(io.lsu_pkt_m.valid, _T_840) @[lsu_trigger.scala 18:69] + node _T_842 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.bits.store) @[lsu_trigger.scala 18:126] + node _T_843 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.bits.load) @[lsu_trigger.scala 19:33] + node _T_844 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[lsu_trigger.scala 19:60] + node _T_845 = and(_T_843, _T_844) @[lsu_trigger.scala 19:58] + node _T_846 = or(_T_842, _T_845) @[lsu_trigger.scala 18:152] + node _T_847 = and(_T_841, _T_846) @[lsu_trigger.scala 18:94] + node _T_848 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] + wire _T_849 : UInt<1>[32] @[lib.scala 84:24] + node _T_850 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 85:45] + node _T_851 = not(_T_850) @[lib.scala 85:39] + node _T_852 = and(_T_848, _T_851) @[lib.scala 85:37] + node _T_853 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 86:48] + node _T_854 = bits(lsu_match_data_3, 0, 0) @[lib.scala 86:60] + node _T_855 = eq(_T_853, _T_854) @[lib.scala 86:52] + node _T_856 = or(_T_852, _T_855) @[lib.scala 86:41] + _T_849[0] <= _T_856 @[lib.scala 86:18] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 88:28] + node _T_858 = andr(_T_857) @[lib.scala 88:36] + node _T_859 = and(_T_858, _T_852) @[lib.scala 88:41] + node _T_860 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 88:74] + node _T_861 = bits(lsu_match_data_3, 1, 1) @[lib.scala 88:86] + node _T_862 = eq(_T_860, _T_861) @[lib.scala 88:78] + node _T_863 = mux(_T_859, UInt<1>("h01"), _T_862) @[lib.scala 88:23] + _T_849[1] <= _T_863 @[lib.scala 88:17] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 88:28] + node _T_865 = andr(_T_864) @[lib.scala 88:36] + node _T_866 = and(_T_865, _T_852) @[lib.scala 88:41] + node _T_867 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 88:74] + node _T_868 = bits(lsu_match_data_3, 2, 2) @[lib.scala 88:86] + node _T_869 = eq(_T_867, _T_868) @[lib.scala 88:78] + node _T_870 = mux(_T_866, UInt<1>("h01"), _T_869) @[lib.scala 88:23] + _T_849[2] <= _T_870 @[lib.scala 88:17] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 88:28] + node _T_872 = andr(_T_871) @[lib.scala 88:36] + node _T_873 = and(_T_872, _T_852) @[lib.scala 88:41] + node _T_874 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 88:74] + node _T_875 = bits(lsu_match_data_3, 3, 3) @[lib.scala 88:86] + node _T_876 = eq(_T_874, _T_875) @[lib.scala 88:78] + node _T_877 = mux(_T_873, UInt<1>("h01"), _T_876) @[lib.scala 88:23] + _T_849[3] <= _T_877 @[lib.scala 88:17] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 88:28] + node _T_879 = andr(_T_878) @[lib.scala 88:36] + node _T_880 = and(_T_879, _T_852) @[lib.scala 88:41] + node _T_881 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 88:74] + node _T_882 = bits(lsu_match_data_3, 4, 4) @[lib.scala 88:86] + node _T_883 = eq(_T_881, _T_882) @[lib.scala 88:78] + node _T_884 = mux(_T_880, UInt<1>("h01"), _T_883) @[lib.scala 88:23] + _T_849[4] <= _T_884 @[lib.scala 88:17] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 88:28] + node _T_886 = andr(_T_885) @[lib.scala 88:36] + node _T_887 = and(_T_886, _T_852) @[lib.scala 88:41] + node _T_888 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 88:74] + node _T_889 = bits(lsu_match_data_3, 5, 5) @[lib.scala 88:86] + node _T_890 = eq(_T_888, _T_889) @[lib.scala 88:78] + node _T_891 = mux(_T_887, UInt<1>("h01"), _T_890) @[lib.scala 88:23] + _T_849[5] <= _T_891 @[lib.scala 88:17] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 88:28] + node _T_893 = andr(_T_892) @[lib.scala 88:36] + node _T_894 = and(_T_893, _T_852) @[lib.scala 88:41] + node _T_895 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 88:74] + node _T_896 = bits(lsu_match_data_3, 6, 6) @[lib.scala 88:86] + node _T_897 = eq(_T_895, _T_896) @[lib.scala 88:78] + node _T_898 = mux(_T_894, UInt<1>("h01"), _T_897) @[lib.scala 88:23] + _T_849[6] <= _T_898 @[lib.scala 88:17] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 88:28] + node _T_900 = andr(_T_899) @[lib.scala 88:36] + node _T_901 = and(_T_900, _T_852) @[lib.scala 88:41] + node _T_902 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 88:74] + node _T_903 = bits(lsu_match_data_3, 7, 7) @[lib.scala 88:86] + node _T_904 = eq(_T_902, _T_903) @[lib.scala 88:78] + node _T_905 = mux(_T_901, UInt<1>("h01"), _T_904) @[lib.scala 88:23] + _T_849[7] <= _T_905 @[lib.scala 88:17] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 88:28] + node _T_907 = andr(_T_906) @[lib.scala 88:36] + node _T_908 = and(_T_907, _T_852) @[lib.scala 88:41] + node _T_909 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 88:74] + node _T_910 = bits(lsu_match_data_3, 8, 8) @[lib.scala 88:86] + node _T_911 = eq(_T_909, _T_910) @[lib.scala 88:78] + node _T_912 = mux(_T_908, UInt<1>("h01"), _T_911) @[lib.scala 88:23] + _T_849[8] <= _T_912 @[lib.scala 88:17] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 88:28] + node _T_914 = andr(_T_913) @[lib.scala 88:36] + node _T_915 = and(_T_914, _T_852) @[lib.scala 88:41] + node _T_916 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 88:74] + node _T_917 = bits(lsu_match_data_3, 9, 9) @[lib.scala 88:86] + node _T_918 = eq(_T_916, _T_917) @[lib.scala 88:78] + node _T_919 = mux(_T_915, UInt<1>("h01"), _T_918) @[lib.scala 88:23] + _T_849[9] <= _T_919 @[lib.scala 88:17] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 88:28] + node _T_921 = andr(_T_920) @[lib.scala 88:36] + node _T_922 = and(_T_921, _T_852) @[lib.scala 88:41] + node _T_923 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 88:74] + node _T_924 = bits(lsu_match_data_3, 10, 10) @[lib.scala 88:86] + node _T_925 = eq(_T_923, _T_924) @[lib.scala 88:78] + node _T_926 = mux(_T_922, UInt<1>("h01"), _T_925) @[lib.scala 88:23] + _T_849[10] <= _T_926 @[lib.scala 88:17] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 88:28] + node _T_928 = andr(_T_927) @[lib.scala 88:36] + node _T_929 = and(_T_928, _T_852) @[lib.scala 88:41] + node _T_930 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 88:74] + node _T_931 = bits(lsu_match_data_3, 11, 11) @[lib.scala 88:86] + node _T_932 = eq(_T_930, _T_931) @[lib.scala 88:78] + node _T_933 = mux(_T_929, UInt<1>("h01"), _T_932) @[lib.scala 88:23] + _T_849[11] <= _T_933 @[lib.scala 88:17] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 88:28] + node _T_935 = andr(_T_934) @[lib.scala 88:36] + node _T_936 = and(_T_935, _T_852) @[lib.scala 88:41] + node _T_937 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 88:74] + node _T_938 = bits(lsu_match_data_3, 12, 12) @[lib.scala 88:86] + node _T_939 = eq(_T_937, _T_938) @[lib.scala 88:78] + node _T_940 = mux(_T_936, UInt<1>("h01"), _T_939) @[lib.scala 88:23] + _T_849[12] <= _T_940 @[lib.scala 88:17] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 88:28] + node _T_942 = andr(_T_941) @[lib.scala 88:36] + node _T_943 = and(_T_942, _T_852) @[lib.scala 88:41] + node _T_944 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 88:74] + node _T_945 = bits(lsu_match_data_3, 13, 13) @[lib.scala 88:86] + node _T_946 = eq(_T_944, _T_945) @[lib.scala 88:78] + node _T_947 = mux(_T_943, UInt<1>("h01"), _T_946) @[lib.scala 88:23] + _T_849[13] <= _T_947 @[lib.scala 88:17] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 88:28] + node _T_949 = andr(_T_948) @[lib.scala 88:36] + node _T_950 = and(_T_949, _T_852) @[lib.scala 88:41] + node _T_951 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 88:74] + node _T_952 = bits(lsu_match_data_3, 14, 14) @[lib.scala 88:86] + node _T_953 = eq(_T_951, _T_952) @[lib.scala 88:78] + node _T_954 = mux(_T_950, UInt<1>("h01"), _T_953) @[lib.scala 88:23] + _T_849[14] <= _T_954 @[lib.scala 88:17] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 88:28] + node _T_956 = andr(_T_955) @[lib.scala 88:36] + node _T_957 = and(_T_956, _T_852) @[lib.scala 88:41] + node _T_958 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 88:74] + node _T_959 = bits(lsu_match_data_3, 15, 15) @[lib.scala 88:86] + node _T_960 = eq(_T_958, _T_959) @[lib.scala 88:78] + node _T_961 = mux(_T_957, UInt<1>("h01"), _T_960) @[lib.scala 88:23] + _T_849[15] <= _T_961 @[lib.scala 88:17] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 88:28] + node _T_963 = andr(_T_962) @[lib.scala 88:36] + node _T_964 = and(_T_963, _T_852) @[lib.scala 88:41] + node _T_965 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 88:74] + node _T_966 = bits(lsu_match_data_3, 16, 16) @[lib.scala 88:86] + node _T_967 = eq(_T_965, _T_966) @[lib.scala 88:78] + node _T_968 = mux(_T_964, UInt<1>("h01"), _T_967) @[lib.scala 88:23] + _T_849[16] <= _T_968 @[lib.scala 88:17] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 88:28] + node _T_970 = andr(_T_969) @[lib.scala 88:36] + node _T_971 = and(_T_970, _T_852) @[lib.scala 88:41] + node _T_972 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 88:74] + node _T_973 = bits(lsu_match_data_3, 17, 17) @[lib.scala 88:86] + node _T_974 = eq(_T_972, _T_973) @[lib.scala 88:78] + node _T_975 = mux(_T_971, UInt<1>("h01"), _T_974) @[lib.scala 88:23] + _T_849[17] <= _T_975 @[lib.scala 88:17] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 88:28] + node _T_977 = andr(_T_976) @[lib.scala 88:36] + node _T_978 = and(_T_977, _T_852) @[lib.scala 88:41] + node _T_979 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 88:74] + node _T_980 = bits(lsu_match_data_3, 18, 18) @[lib.scala 88:86] + node _T_981 = eq(_T_979, _T_980) @[lib.scala 88:78] + node _T_982 = mux(_T_978, UInt<1>("h01"), _T_981) @[lib.scala 88:23] + _T_849[18] <= _T_982 @[lib.scala 88:17] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 88:28] + node _T_984 = andr(_T_983) @[lib.scala 88:36] + node _T_985 = and(_T_984, _T_852) @[lib.scala 88:41] + node _T_986 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 88:74] + node _T_987 = bits(lsu_match_data_3, 19, 19) @[lib.scala 88:86] + node _T_988 = eq(_T_986, _T_987) @[lib.scala 88:78] + node _T_989 = mux(_T_985, UInt<1>("h01"), _T_988) @[lib.scala 88:23] + _T_849[19] <= _T_989 @[lib.scala 88:17] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 88:28] + node _T_991 = andr(_T_990) @[lib.scala 88:36] + node _T_992 = and(_T_991, _T_852) @[lib.scala 88:41] + node _T_993 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 88:74] + node _T_994 = bits(lsu_match_data_3, 20, 20) @[lib.scala 88:86] + node _T_995 = eq(_T_993, _T_994) @[lib.scala 88:78] + node _T_996 = mux(_T_992, UInt<1>("h01"), _T_995) @[lib.scala 88:23] + _T_849[20] <= _T_996 @[lib.scala 88:17] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 88:28] + node _T_998 = andr(_T_997) @[lib.scala 88:36] + node _T_999 = and(_T_998, _T_852) @[lib.scala 88:41] + node _T_1000 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 88:74] + node _T_1001 = bits(lsu_match_data_3, 21, 21) @[lib.scala 88:86] + node _T_1002 = eq(_T_1000, _T_1001) @[lib.scala 88:78] + node _T_1003 = mux(_T_999, UInt<1>("h01"), _T_1002) @[lib.scala 88:23] + _T_849[21] <= _T_1003 @[lib.scala 88:17] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 88:28] + node _T_1005 = andr(_T_1004) @[lib.scala 88:36] + node _T_1006 = and(_T_1005, _T_852) @[lib.scala 88:41] + node _T_1007 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 88:74] + node _T_1008 = bits(lsu_match_data_3, 22, 22) @[lib.scala 88:86] + node _T_1009 = eq(_T_1007, _T_1008) @[lib.scala 88:78] + node _T_1010 = mux(_T_1006, UInt<1>("h01"), _T_1009) @[lib.scala 88:23] + _T_849[22] <= _T_1010 @[lib.scala 88:17] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 88:28] + node _T_1012 = andr(_T_1011) @[lib.scala 88:36] + node _T_1013 = and(_T_1012, _T_852) @[lib.scala 88:41] + node _T_1014 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 88:74] + node _T_1015 = bits(lsu_match_data_3, 23, 23) @[lib.scala 88:86] + node _T_1016 = eq(_T_1014, _T_1015) @[lib.scala 88:78] + node _T_1017 = mux(_T_1013, UInt<1>("h01"), _T_1016) @[lib.scala 88:23] + _T_849[23] <= _T_1017 @[lib.scala 88:17] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 88:28] + node _T_1019 = andr(_T_1018) @[lib.scala 88:36] + node _T_1020 = and(_T_1019, _T_852) @[lib.scala 88:41] + node _T_1021 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 88:74] + node _T_1022 = bits(lsu_match_data_3, 24, 24) @[lib.scala 88:86] + node _T_1023 = eq(_T_1021, _T_1022) @[lib.scala 88:78] + node _T_1024 = mux(_T_1020, UInt<1>("h01"), _T_1023) @[lib.scala 88:23] + _T_849[24] <= _T_1024 @[lib.scala 88:17] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 88:28] + node _T_1026 = andr(_T_1025) @[lib.scala 88:36] + node _T_1027 = and(_T_1026, _T_852) @[lib.scala 88:41] + node _T_1028 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 88:74] + node _T_1029 = bits(lsu_match_data_3, 25, 25) @[lib.scala 88:86] + node _T_1030 = eq(_T_1028, _T_1029) @[lib.scala 88:78] + node _T_1031 = mux(_T_1027, UInt<1>("h01"), _T_1030) @[lib.scala 88:23] + _T_849[25] <= _T_1031 @[lib.scala 88:17] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 88:28] + node _T_1033 = andr(_T_1032) @[lib.scala 88:36] + node _T_1034 = and(_T_1033, _T_852) @[lib.scala 88:41] + node _T_1035 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 88:74] + node _T_1036 = bits(lsu_match_data_3, 26, 26) @[lib.scala 88:86] + node _T_1037 = eq(_T_1035, _T_1036) @[lib.scala 88:78] + node _T_1038 = mux(_T_1034, UInt<1>("h01"), _T_1037) @[lib.scala 88:23] + _T_849[26] <= _T_1038 @[lib.scala 88:17] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 88:28] + node _T_1040 = andr(_T_1039) @[lib.scala 88:36] + node _T_1041 = and(_T_1040, _T_852) @[lib.scala 88:41] + node _T_1042 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 88:74] + node _T_1043 = bits(lsu_match_data_3, 27, 27) @[lib.scala 88:86] + node _T_1044 = eq(_T_1042, _T_1043) @[lib.scala 88:78] + node _T_1045 = mux(_T_1041, UInt<1>("h01"), _T_1044) @[lib.scala 88:23] + _T_849[27] <= _T_1045 @[lib.scala 88:17] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 88:28] + node _T_1047 = andr(_T_1046) @[lib.scala 88:36] + node _T_1048 = and(_T_1047, _T_852) @[lib.scala 88:41] + node _T_1049 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 88:74] + node _T_1050 = bits(lsu_match_data_3, 28, 28) @[lib.scala 88:86] + node _T_1051 = eq(_T_1049, _T_1050) @[lib.scala 88:78] + node _T_1052 = mux(_T_1048, UInt<1>("h01"), _T_1051) @[lib.scala 88:23] + _T_849[28] <= _T_1052 @[lib.scala 88:17] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 88:28] + node _T_1054 = andr(_T_1053) @[lib.scala 88:36] + node _T_1055 = and(_T_1054, _T_852) @[lib.scala 88:41] + node _T_1056 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 88:74] + node _T_1057 = bits(lsu_match_data_3, 29, 29) @[lib.scala 88:86] + node _T_1058 = eq(_T_1056, _T_1057) @[lib.scala 88:78] + node _T_1059 = mux(_T_1055, UInt<1>("h01"), _T_1058) @[lib.scala 88:23] + _T_849[29] <= _T_1059 @[lib.scala 88:17] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 88:28] + node _T_1061 = andr(_T_1060) @[lib.scala 88:36] + node _T_1062 = and(_T_1061, _T_852) @[lib.scala 88:41] + node _T_1063 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 88:74] + node _T_1064 = bits(lsu_match_data_3, 30, 30) @[lib.scala 88:86] + node _T_1065 = eq(_T_1063, _T_1064) @[lib.scala 88:78] + node _T_1066 = mux(_T_1062, UInt<1>("h01"), _T_1065) @[lib.scala 88:23] + _T_849[30] <= _T_1066 @[lib.scala 88:17] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 88:28] + node _T_1068 = andr(_T_1067) @[lib.scala 88:36] + node _T_1069 = and(_T_1068, _T_852) @[lib.scala 88:41] + node _T_1070 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 88:74] + node _T_1071 = bits(lsu_match_data_3, 31, 31) @[lib.scala 88:86] + node _T_1072 = eq(_T_1070, _T_1071) @[lib.scala 88:78] + node _T_1073 = mux(_T_1069, UInt<1>("h01"), _T_1072) @[lib.scala 88:23] + _T_849[31] <= _T_1073 @[lib.scala 88:17] + node _T_1074 = cat(_T_849[1], _T_849[0]) @[lib.scala 89:14] + node _T_1075 = cat(_T_849[3], _T_849[2]) @[lib.scala 89:14] node _T_1076 = cat(_T_1075, _T_1074) @[lib.scala 89:14] - node _T_1077 = cat(_T_1076, _T_1073) @[lib.scala 89:14] - node _T_1078 = cat(_T_846[9], _T_846[8]) @[lib.scala 89:14] - node _T_1079 = cat(_T_846[11], _T_846[10]) @[lib.scala 89:14] - node _T_1080 = cat(_T_1079, _T_1078) @[lib.scala 89:14] - node _T_1081 = cat(_T_846[13], _T_846[12]) @[lib.scala 89:14] - node _T_1082 = cat(_T_846[15], _T_846[14]) @[lib.scala 89:14] + node _T_1077 = cat(_T_849[5], _T_849[4]) @[lib.scala 89:14] + node _T_1078 = cat(_T_849[7], _T_849[6]) @[lib.scala 89:14] + node _T_1079 = cat(_T_1078, _T_1077) @[lib.scala 89:14] + node _T_1080 = cat(_T_1079, _T_1076) @[lib.scala 89:14] + node _T_1081 = cat(_T_849[9], _T_849[8]) @[lib.scala 89:14] + node _T_1082 = cat(_T_849[11], _T_849[10]) @[lib.scala 89:14] node _T_1083 = cat(_T_1082, _T_1081) @[lib.scala 89:14] - node _T_1084 = cat(_T_1083, _T_1080) @[lib.scala 89:14] - node _T_1085 = cat(_T_1084, _T_1077) @[lib.scala 89:14] - node _T_1086 = cat(_T_846[17], _T_846[16]) @[lib.scala 89:14] - node _T_1087 = cat(_T_846[19], _T_846[18]) @[lib.scala 89:14] - node _T_1088 = cat(_T_1087, _T_1086) @[lib.scala 89:14] - node _T_1089 = cat(_T_846[21], _T_846[20]) @[lib.scala 89:14] - node _T_1090 = cat(_T_846[23], _T_846[22]) @[lib.scala 89:14] + node _T_1084 = cat(_T_849[13], _T_849[12]) @[lib.scala 89:14] + node _T_1085 = cat(_T_849[15], _T_849[14]) @[lib.scala 89:14] + node _T_1086 = cat(_T_1085, _T_1084) @[lib.scala 89:14] + node _T_1087 = cat(_T_1086, _T_1083) @[lib.scala 89:14] + node _T_1088 = cat(_T_1087, _T_1080) @[lib.scala 89:14] + node _T_1089 = cat(_T_849[17], _T_849[16]) @[lib.scala 89:14] + node _T_1090 = cat(_T_849[19], _T_849[18]) @[lib.scala 89:14] node _T_1091 = cat(_T_1090, _T_1089) @[lib.scala 89:14] - node _T_1092 = cat(_T_1091, _T_1088) @[lib.scala 89:14] - node _T_1093 = cat(_T_846[25], _T_846[24]) @[lib.scala 89:14] - node _T_1094 = cat(_T_846[27], _T_846[26]) @[lib.scala 89:14] - node _T_1095 = cat(_T_1094, _T_1093) @[lib.scala 89:14] - node _T_1096 = cat(_T_846[29], _T_846[28]) @[lib.scala 89:14] - node _T_1097 = cat(_T_846[31], _T_846[30]) @[lib.scala 89:14] + node _T_1092 = cat(_T_849[21], _T_849[20]) @[lib.scala 89:14] + node _T_1093 = cat(_T_849[23], _T_849[22]) @[lib.scala 89:14] + node _T_1094 = cat(_T_1093, _T_1092) @[lib.scala 89:14] + node _T_1095 = cat(_T_1094, _T_1091) @[lib.scala 89:14] + node _T_1096 = cat(_T_849[25], _T_849[24]) @[lib.scala 89:14] + node _T_1097 = cat(_T_849[27], _T_849[26]) @[lib.scala 89:14] node _T_1098 = cat(_T_1097, _T_1096) @[lib.scala 89:14] - node _T_1099 = cat(_T_1098, _T_1095) @[lib.scala 89:14] - node _T_1100 = cat(_T_1099, _T_1092) @[lib.scala 89:14] - node _T_1101 = cat(_T_1100, _T_1085) @[lib.scala 89:14] - node _T_1102 = and(_T_844, _T_1101) @[lsu_trigger.scala 19:92] - node _T_1103 = cat(_T_1102, _T_836) @[Cat.scala 29:58] - node _T_1104 = cat(_T_1103, _T_570) @[Cat.scala 29:58] - node _T_1105 = cat(_T_1104, _T_304) @[Cat.scala 29:58] - io.lsu_trigger_match_m <= _T_1105 @[lsu_trigger.scala 18:26] + node _T_1099 = cat(_T_849[29], _T_849[28]) @[lib.scala 89:14] + node _T_1100 = cat(_T_849[31], _T_849[30]) @[lib.scala 89:14] + node _T_1101 = cat(_T_1100, _T_1099) @[lib.scala 89:14] + node _T_1102 = cat(_T_1101, _T_1098) @[lib.scala 89:14] + node _T_1103 = cat(_T_1102, _T_1095) @[lib.scala 89:14] + node _T_1104 = cat(_T_1103, _T_1088) @[lib.scala 89:14] + node _T_1105 = andr(_T_1104) @[lib.scala 89:25] + node _T_1106 = and(_T_847, _T_1105) @[lsu_trigger.scala 19:92] + node _T_1107 = cat(_T_1106, _T_839) @[Cat.scala 29:58] + node _T_1108 = cat(_T_1107, _T_572) @[Cat.scala 29:58] + node _T_1109 = cat(_T_1108, _T_305) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1109 @[lsu_trigger.scala 18:26] extmodule gated_latch_800 : output Q : Clock @@ -107065,7 +107073,7 @@ circuit quasar_wrapper : module dma_ctrl : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, flip iccm_ready : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} + output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, flip iccm_ready : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} wire fifo_error : UInt<2>[5] @[dma_ctrl.scala 36:24] wire fifo_error_bus : UInt<5> @@ -109243,29 +109251,29 @@ circuit quasar_wrapper : module axi4_to_ahb : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -109300,8 +109308,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -109410,141 +109418,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_847 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -109553,193 +109561,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -109748,39 +109756,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -109789,83 +109797,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -109874,62 +109882,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -109938,35 +109946,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -109975,268 +109983,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_849 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -110245,8 +110253,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_850 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -110255,37 +110263,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_851 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -110294,30 +110302,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_852 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -110326,98 +110334,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_853 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_854 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_855 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_856 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_857 : output Q : Clock @@ -110662,29 +110670,29 @@ circuit quasar_wrapper : module axi4_to_ahb_1 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -110719,8 +110727,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -110829,141 +110837,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_857 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_858 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -110972,193 +110980,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -111167,39 +111175,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -111208,83 +111216,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -111293,62 +111301,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -111357,35 +111365,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -111394,268 +111402,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_859 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -111664,8 +111672,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_860 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -111674,37 +111682,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_861 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -111713,30 +111721,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_862 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -111745,98 +111753,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_863 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_864 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_865 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_866 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_867 : output Q : Clock @@ -112081,29 +112089,29 @@ circuit quasar_wrapper : module axi4_to_ahb_2 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire buf_rst : UInt<1> buf_rst <= UInt<1>("h00") - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 61:11] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 55:11] wire buf_state_en : UInt<1> buf_state_en <= UInt<1>("h00") - wire ahbm_clk : Clock @[axi4_to_ahb.scala 63:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 64:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 65:27] + wire ahbm_clk : Clock @[axi4_to_ahb.scala 57:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 58:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 59:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") - node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:70] - node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:50] - node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:108] + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 63:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 63:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 63:108] node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 69:98] - reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:45] - _T_6 <= _T_5 @[axi4_to_ahb.scala 69:45] - buf_state <= _T_6 @[axi4_to_ahb.scala 69:13] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 63:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 63:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 63:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 63:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -112138,8 +112146,8 @@ circuit quasar_wrapper : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 89:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 90:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 83:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -112248,141 +112256,141 @@ circuit quasar_wrapper : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 178:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 178:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 179:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 179:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 180:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 180:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 180:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 180:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 181:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 181:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 182:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 182:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 182:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 182:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 183:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 183:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 183:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 183:21] - master_size <= _T_22 @[axi4_to_ahb.scala 183:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 184:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 184:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 185:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 185:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 188:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 188:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 188:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 188:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 189:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 189:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 189:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 189:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 189:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 190:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 190:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 192:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 192:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 192:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 192:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 192:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 193:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 193:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 193:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 193:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 193:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 194:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 194:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 195:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 195:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 196:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 196:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 199:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 199:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 199:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 199:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 199:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 151:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 172:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 172:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 173:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 173:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 174:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 174:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 174:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 174:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 174:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 175:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 175:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 175:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 176:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 176:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 176:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 176:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 176:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 177:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 177:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 177:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 177:21] + master_size <= _T_22 @[axi4_to_ahb.scala 177:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 178:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 178:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 179:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 179:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 182:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 182:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 182:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 182:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 183:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 183:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 183:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 183:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 183:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 184:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 184:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 186:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 186:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 186:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 186:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 186:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 187:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 187:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 187:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 187:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 187:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 188:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 188:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 189:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 189:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 190:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 190:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 193:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 193:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20] inst rvclkhdr of rvclkhdr_867 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 201:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 202:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59] inst rvclkhdr_1 of rvclkhdr_868 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_48 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 202:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 205:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 207:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 208:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 216:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 217:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 218:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 220:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 221:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 196:17] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 199:21] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 200:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 201:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 202:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 204:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 205:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 207:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 208:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 210:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 211:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 212:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 213:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 214:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 215:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 226:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 227:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 228:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 228:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 230:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 230:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 219:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 220:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 220:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 220:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 221:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 221:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 221:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 222:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 222:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 223:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 224:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 224:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 224:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 227:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 168:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 169:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 169:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 169:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 169:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 169:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 169:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 169:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 169:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 169:48] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] @@ -112391,193 +112399,193 @@ circuit quasar_wrapper : node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 227:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 227:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 229:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 229:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 229:22] node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 230:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 230:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 234:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 234:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 234:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 234:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 234:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 234:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 235:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 235:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 235:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 235:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 235:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 236:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 236:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 236:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 237:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 238:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 238:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 238:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 238:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 238:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 238:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 238:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 238:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 238:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 238:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 238:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 238:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 238:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 239:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 240:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 240:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 241:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 241:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 241:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 241:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 241:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 242:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 242:62] node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 242:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 242:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = not(_T_141) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 246:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 246:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 246:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 246:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 246:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 246:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 246:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 247:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 247:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 247:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 247:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 248:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 248:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 248:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 248:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 248:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 248:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 248:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 248:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 249:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 249:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 250:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 251:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 252:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 253:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 253:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 253:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 254:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 254:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 254:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 255:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 255:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 255:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 255:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 255:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 256:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 256:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 256:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 256:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 256:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 257:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 257:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 257:47] node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 257:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 257:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 258:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_175 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 262:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 263:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 263:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 264:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 266:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 266:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 267:51] node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 267:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 267:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 271:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 272:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 272:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 273:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 274:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 275:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_188 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 280:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 281:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 281:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 281:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 281:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 281:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 282:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 283:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 284:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 285:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 285:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 285:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 168:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 168:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 169:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 169:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 169:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 169:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 169:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 169:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 169:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 169:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 169:48] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] @@ -112586,39 +112594,39 @@ circuit quasar_wrapper : node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 285:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 285:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 286:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 286:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 286:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 286:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 168:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 168:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 169:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 169:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 169:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 169:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 169:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 169:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 169:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 169:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 169:48] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] @@ -112627,83 +112635,83 @@ circuit quasar_wrapper : node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 286:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 286:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 286:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 286:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 286:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 286:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 287:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 287:36] node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 287:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 287:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:38] - node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 298:36] - node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 298:51] - master_ready <= _T_286 @[axi4_to_ahb.scala 298:20] - node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 299:40] - node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 299:80] - node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:111] - node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 299:117] - node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 299:132] - node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:99] - node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 299:65] - node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 299:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:33] - node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 302:39] - buf_write_in <= _T_297 @[axi4_to_ahb.scala 302:20] - node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 303:62] - node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_301 @[axi4_to_ahb.scala 303:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:65] - node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 305:71] - node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 305:50] - node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:29] - node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:85] - node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:101] - node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 174:52] - node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 174:24] - node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 175:48] - node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 291:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 291:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 291:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 292:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 292:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 292:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 292:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 293:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 293:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 293:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 293:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 293:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 293:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 293:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 293:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 293:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 293:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 296:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 296:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 296:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 297:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 297:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 297:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 297:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 297:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 298:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 299:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 299:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 299:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 300:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 300:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 300:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 168:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 168:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 169:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 169:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 169:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 169:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 169:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 169:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 169:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 169:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 169:48] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] @@ -112712,62 +112720,62 @@ circuit quasar_wrapper : node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] - node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] - node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] - node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 306:38] - node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 305:80] - node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 305:34] - cmd_done <= _T_348 @[axi4_to_ahb.scala 305:16] - node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 307:33] - node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 307:64] - node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 307:48] - bypass_en <= _T_351 @[axi4_to_ahb.scala 307:17] - node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 308:44] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 308:33] - node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 308:57] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 300:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 300:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 300:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 300:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 299:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 299:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 299:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 301:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 301:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 301:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 301:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 302:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 302:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 302:61] node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 308:71] - io.ahb_htrans <= _T_357 @[axi4_to_ahb.scala 308:21] - node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 309:55] - node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 309:39] - slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 309:23] - node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 310:33] - node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 310:63] - node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 310:69] - node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 310:48] - trxn_done <= _T_363 @[axi4_to_ahb.scala 310:17] - node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 311:40] - buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 311:27] - node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:79] - node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 174:52] - node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 175:48] - node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 302:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 302:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 303:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 303:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 303:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 304:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 304:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 304:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 304:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 305:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 305:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 306:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 168:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 168:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 169:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 169:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 169:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 169:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 169:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 169:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 169:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 169:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 169:48] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] @@ -112776,35 +112784,35 @@ circuit quasar_wrapper : node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] - node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] - node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] - node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 174:52] - node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 174:24] - node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 175:48] - node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 168:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 168:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 168:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 169:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 169:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 169:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 169:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 169:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 169:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 169:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 169:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 169:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 169:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 169:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 169:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 169:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 169:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 169:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 169:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 169:48] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] @@ -112813,268 +112821,268 @@ circuit quasar_wrapper : node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] - node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 306:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 306:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 306:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_440 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 334:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 335:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 336:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 328:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 329:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 330:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 331:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16] - node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33] - node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73] - node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80] - node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 342:60] - node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 342:100] - node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132] - node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 166:70] - node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 335:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 336:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 336:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 336:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 336:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 336:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 336:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 160:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 160:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 160:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 160:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 160:106] node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 166:29] - node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 160:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 161:42] node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 167:15] - node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 166:146] - node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 168:56] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 161:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 160:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 162:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 162:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 162:56] node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 168:15] - node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 167:63] - node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:42] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 162:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 161:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 163:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:42] node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 169:15] - node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 168:96] - node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 170:33] - node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:40] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 163:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 162:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 164:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 164:40] node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 170:13] - node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152] - node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 342:43] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 164:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 336:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 336:43] node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] - buf_addr_in <= _T_486 @[axi4_to_ahb.scala 342:15] - node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27] - buf_tag_in <= _T_487 @[axi4_to_ahb.scala 343:14] - node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32] - buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 344:17] - node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33] - node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59] - node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80] - node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 345:21] - buf_data_in <= _T_492 @[axi4_to_ahb.scala 345:15] - node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52] - node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 346:38] - node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84] - node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91] - node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 346:71] - node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 346:111] - node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142] - node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 160:42] - node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:49] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 336:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 337:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 337:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 338:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 338:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 339:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 339:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 339:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 339:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 339:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 340:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 340:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 340:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 340:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 340:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 340:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 154:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 154:49] node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 160:25] - node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 161:55] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 154:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 155:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 155:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 155:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 155:55] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 161:16] - node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 160:64] - node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 162:60] - node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:89] - node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:123] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 155:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 154:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 156:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 156:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 156:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 156:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 156:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 156:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 156:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 156:123] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 162:21] - node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 161:93] - node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161] - node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 346:21] - buf_size_in <= _T_531 @[axi4_to_ahb.scala 346:15] - node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39] - node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 347:48] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47] - node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 348:33] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86] - node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 348:72] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55] - node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62] - node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90] - node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97] - node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 349:74] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125] - node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 349:109] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161] - node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 349:145] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21] - node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 349:181] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56] - node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 350:40] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92] - node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 350:76] - node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 349:38] - node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 348:106] - buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 347:18] - node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39] - node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58] - node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 156:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 155:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 340:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 340:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 340:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 341:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 341:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 342:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 341:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 342:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 342:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 342:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 342:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 342:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 343:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 343:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 343:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 343:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 343:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 343:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 343:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 343:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 344:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 343:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 344:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 344:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 344:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 344:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 343:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 342:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 341:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 346:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 346:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:87] node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] - node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 346:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 346:133] node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 352:22] - io.ahb_haddr <= _T_574 @[axi4_to_ahb.scala 352:16] - node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 346:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 346:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 347:43] node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90] - node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 353:77] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 347:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 347:81] node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 353:134] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 347:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 347:138] node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 353:22] - io.ahb_hsize <= _T_586 @[axi4_to_ahb.scala 353:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20] - node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47] - node _T_588 = not(_T_587) @[axi4_to_ahb.scala 357:33] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 347:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 347:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 349:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 350:24] + node _T_587 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 351:51] + node _T_588 = not(_T_587) @[axi4_to_ahb.scala 351:37] node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] - io.ahb_hprot <= _T_589 @[axi4_to_ahb.scala 357:16] - node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40] - node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55] - node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62] - node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 358:23] - io.ahb_hwrite <= _T_593 @[axi4_to_ahb.scala 358:17] - node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28] - io.ahb_hwdata <= _T_594 @[axi4_to_ahb.scala 359:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15] - node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 351:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 352:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 352:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 352:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 352:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 353:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 353:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 355:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 356:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 356:23] node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 356:88] node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] - slave_opc <= _T_600 @[axi4_to_ahb.scala 362:13] - node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41] - node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66] + slave_opc <= _T_600 @[axi4_to_ahb.scala 356:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 357:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 357:66] node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] - node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91] - node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110] - node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131] - node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 363:79] - node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 363:21] - slave_rdata <= _T_608 @[axi4_to_ahb.scala 363:15] - node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26] - slave_tag <= _T_609 @[axi4_to_ahb.scala 364:13] - node _T_610 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33] - node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40] - node _T_612 = and(_T_611, io.ahb_hready) @[axi4_to_ahb.scala 366:52] - node _T_613 = and(_T_612, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68] - last_addr_en <= _T_613 @[axi4_to_ahb.scala 366:16] - node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 368:47] - wrbuf_en <= _T_615 @[axi4_to_ahb.scala 368:12] - node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34] - node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 369:50] - wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 369:17] - node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34] - node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62] - node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69] - node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 370:49] - wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 370:18] - node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33] - node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 371:31] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 371:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 373:33] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 373:52] - io.axi_awready <= _T_627 @[axi4_to_ahb.scala 373:18] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 374:37] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 374:56] - io.axi_wready <= _T_631 @[axi4_to_ahb.scala 374:17] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 375:51] - io.axi_arready <= _T_634 @[axi4_to_ahb.scala 375:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 378:71] - node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 378:55] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 378:91] - node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 378:89] - reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:51] - _T_639 <= _T_638 @[axi4_to_ahb.scala 378:51] - wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 378:21] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 379:76] - node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 379:55] - node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:102] - node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 379:100] - reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:51] - _T_644 <= _T_643 @[axi4_to_ahb.scala 379:51] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 379:21] - node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 380:65] - node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:99] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 357:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 357:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 357:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 357:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 357:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 357:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 358:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 358:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 360:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 360:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 360:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 360:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 360:16] + node _T_614 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 362:30] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 362:47] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 362:12] + node _T_616 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 363:34] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 363:50] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 363:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 364:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 364:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 364:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 364:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 364:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 365:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 365:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 365:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 367:35] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 367:33] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 367:21] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 367:52] + io.axi_awready <= _T_627 @[axi4_to_ahb.scala 367:18] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 368:39] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 368:37] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 368:20] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 368:56] + io.axi_wready <= _T_631 @[axi4_to_ahb.scala 368:17] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 369:33] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 369:21] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 369:51] + io.axi_arready <= _T_634 @[axi4_to_ahb.scala 369:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 370:16] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 372:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 372:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 372:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 372:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 372:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 372:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 372:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 373:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 373:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 373:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 373:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 373:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 373:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 373:21] + node _T_645 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 374:65] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_646 : @[Reg.scala 28:19] _T_647 <= _T_645 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 380:21] - node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 381:67] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:95] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 374:21] + node _T_648 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 375:67] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 375:95] reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_649 : @[Reg.scala 28:19] _T_650 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_650 @[axi4_to_ahb.scala 381:21] - node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:55] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55] inst rvclkhdr_2 of rvclkhdr_869 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -113083,8 +113091,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_652 <= io.axi_awaddr @[lib.scala 358:16] - wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 382:21] - node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:59] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59] inst rvclkhdr_3 of rvclkhdr_870 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113093,37 +113101,37 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_654 <= io.axi_wdata @[lib.scala 358:16] - wrbuf_data <= _T_654 @[axi4_to_ahb.scala 383:21] - node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 384:66] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 384:99] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 377:21] + node _T_655 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 378:66] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 378:99] reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_656 : @[Reg.scala 28:19] _T_657 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 384:21] - node _T_658 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 385:67] - node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 385:100] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 378:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 379:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 379:104] reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_659 : @[Reg.scala 28:19] _T_660 <= _T_658 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_660 @[axi4_to_ahb.scala 385:21] - node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 386:89] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 379:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 380:89] reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_661 : @[Reg.scala 28:19] _T_662 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_662 @[axi4_to_ahb.scala 386:21] - node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 387:64] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:99] + buf_write <= _T_662 @[axi4_to_ahb.scala 380:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 381:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:99] reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_664 : @[Reg.scala 28:19] _T_665 <= _T_663 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_665 @[axi4_to_ahb.scala 387:21] - node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 388:42] - node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 388:61] - node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 388:78] + buf_tag <= _T_665 @[axi4_to_ahb.scala 381:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78] inst rvclkhdr_4 of rvclkhdr_871 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113132,30 +113140,30 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_669 <= _T_666 @[lib.scala 358:16] - buf_addr <= _T_669 @[axi4_to_ahb.scala 388:21] - node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 389:65] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 389:94] + buf_addr <= _T_669 @[axi4_to_ahb.scala 382:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 383:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 383:94] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_670 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_672 @[axi4_to_ahb.scala 389:21] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 390:91] + buf_size <= _T_672 @[axi4_to_ahb.scala 383:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:91] reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_673 : @[Reg.scala 28:19] _T_674 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_674 @[axi4_to_ahb.scala 390:21] - node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 391:67] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 391:96] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 384:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 385:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:96] reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= _T_675 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_677 @[axi4_to_ahb.scala 391:21] - node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 392:42] - node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 392:66] - node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 392:89] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 385:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89] inst rvclkhdr_5 of rvclkhdr_872 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -113164,98 +113172,98 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_681 <= _T_678 @[lib.scala 358:16] - buf_data <= _T_681 @[axi4_to_ahb.scala 392:21] - node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:89] + buf_data <= _T_681 @[axi4_to_ahb.scala 386:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:89] reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_682 : @[Reg.scala 28:19] _T_683 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_683 @[axi4_to_ahb.scala 393:21] - node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 394:61] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:99] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 387:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 388:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:99] reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_685 : @[Reg.scala 28:19] _T_686 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 394:21] - node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 395:99] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 388:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 389:99] reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_687 : @[Reg.scala 28:19] _T_688 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_688 @[axi4_to_ahb.scala 395:21] - node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 396:72] - node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 396:56] - node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 396:92] - node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 396:90] - reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:52] - _T_693 <= _T_692 @[axi4_to_ahb.scala 396:52] - cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 396:21] - node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 397:71] - node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 397:110] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 389:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 390:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 390:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 390:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 390:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 390:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 390:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 390:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 391:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 391:110] reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_695 : @[Reg.scala 28:19] _T_696 <= _T_694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 397:21] - reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 398:52] - _T_697 <= io.ahb_hready @[axi4_to_ahb.scala 398:52] - ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 398:21] - node _T_698 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 399:66] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 399:52] - _T_699 <= _T_698 @[axi4_to_ahb.scala 399:52] - ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 399:21] - reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 400:57] - _T_700 <= io.ahb_hwrite @[axi4_to_ahb.scala 400:57] - ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 400:21] - reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 401:52] - _T_701 <= io.ahb_hresp @[axi4_to_ahb.scala 401:52] - ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 401:21] - node _T_702 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 402:71] - reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 402:57] - _T_703 <= _T_702 @[axi4_to_ahb.scala 402:57] - ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 402:21] - node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 404:43] - node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 404:58] - node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 404:30] - buf_clken <= _T_706 @[axi4_to_ahb.scala 404:13] - node _T_707 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 405:69] - node _T_708 = and(io.ahb_hready, _T_707) @[axi4_to_ahb.scala 405:54] - node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 405:74] - node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 405:36] - ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 405:19] - node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 406:50] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 406:60] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 406:36] - ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 406:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 391:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 392:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 392:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 392:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 393:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 393:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 393:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 394:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 394:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 394:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 395:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 395:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 395:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 396:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 396:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 396:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 396:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 398:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 398:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 398:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 398:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 399:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 399:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 399:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 399:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 399:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 400:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19] inst rvclkhdr_6 of rvclkhdr_873 @[lib.scala 327:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 328:17] rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 409:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12] inst rvclkhdr_7 of rvclkhdr_874 @[lib.scala 327:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 328:17] rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 410:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12] inst rvclkhdr_8 of rvclkhdr_875 @[lib.scala 327:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 328:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 411:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17] inst rvclkhdr_9 of rvclkhdr_876 @[lib.scala 327:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 328:17] rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 329:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 412:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17] extmodule gated_latch_877 : output Q : Clock @@ -113404,7 +113412,7 @@ circuit quasar_wrapper : module ahb_to_axi4 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_haddr : UInt<32>, flip ahb_hburst : UInt<3>, flip ahb_hmastlock : UInt<1>, flip ahb_hprot : UInt<4>, flip ahb_hsize : UInt<3>, flip ahb_htrans : UInt<2>, flip ahb_hwrite : UInt<1>, flip ahb_hwdata : UInt<64>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb_hrdata : UInt<64>, ahb_hreadyout : UInt<1>, ahb_hresp : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, flip ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} wire master_wstrb : UInt<8> master_wstrb <= UInt<8>("h00") @@ -113440,9 +113448,9 @@ circuit quasar_wrapper : ahb_bus_addr_clk_en <= UInt<1>("h00") wire buf_rdata_clk_en : UInt<1> buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 85:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 86:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 87:33] + wire ahb_clk : Clock @[ahb_to_axi4.scala 86:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 87:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 88:33] wire cmdbuf_wr_en : UInt<1> cmdbuf_wr_en <= UInt<1>("h00") wire cmdbuf_rst : UInt<1> @@ -113461,7 +113469,7 @@ circuit quasar_wrapper : cmdbuf_addr <= UInt<32>("h00") wire cmdbuf_wdata : UInt<64> cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 99:33] + wire bus_clk : Clock @[ahb_to_axi4.scala 100:33] node _T = bits(ahb_haddr_q, 31, 28) @[lib.scala 68:25] node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[lib.scala 68:47] node _T_1 = bits(ahb_haddr_q, 31, 16) @[lib.scala 71:14] @@ -113478,260 +113486,260 @@ circuit quasar_wrapper : buf_state <= UInt<2>("h00") wire buf_nxtstate : UInt<2> buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 109:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 110:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 111:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 112:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 113:31] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 110:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 111:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 112:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 113:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 114:31] node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] when _T_6 : @[Conditional.scala 40:58] - node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 117:26] - buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 117:20] - node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 118:49] - node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 118:34] - node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 118:53] - buf_state_en <= _T_10 @[ahb_to_axi4.scala 118:20] + node _T_7 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 118:26] + buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 118:20] + node _T_8 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 119:53] + node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 119:34] + node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 119:57] + buf_state_en <= _T_10 @[ahb_to_axi4.scala 119:20] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] when _T_11 : @[Conditional.scala 39:67] - node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 121:57] - node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 121:64] - node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 121:41] - node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 121:78] - node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 121:76] - node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 121:92] - node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 121:109] - node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 121:26] - buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 121:20] - node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 122:24] - node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 122:37] - buf_state_en <= _T_21 @[ahb_to_axi4.scala 122:20] - node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 123:23] - node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 123:70] - node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 123:77] - node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 123:95] - node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 123:53] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 123:38] - node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 123:36] - cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 123:20] + node _T_12 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 122:64] + node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 122:71] + node _T_14 = or(io.ahb.in.hresp, _T_13) @[ahb_to_axi4.scala 122:44] + node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 122:85] + node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 122:83] + node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 122:99] + node _T_18 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 122:116] + node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 122:26] + buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 122:20] + node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 123:24] + node _T_21 = or(_T_20, io.ahb.in.hresp) @[ahb_to_axi4.scala 123:37] + buf_state_en <= _T_21 @[ahb_to_axi4.scala 123:20] + node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 124:23] + node _T_23 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 124:77] + node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 124:84] + node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 124:102] + node _T_26 = or(io.ahb.in.hresp, _T_25) @[ahb_to_axi4.scala 124:56] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 124:38] + node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 124:36] + cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 124:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] when _T_29 : @[Conditional.scala 39:67] - node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 126:26] - buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 126:20] - node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 127:24] - node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 127:37] - buf_state_en <= _T_32 @[ahb_to_axi4.scala 127:20] - node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 128:23] - node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 128:39] - node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 128:37] - cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 128:20] + node _T_30 = mux(io.ahb.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 127:26] + buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 127:20] + node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 128:24] + node _T_32 = or(_T_31, io.ahb.in.hresp) @[ahb_to_axi4.scala 128:37] + buf_state_en <= _T_32 @[ahb_to_axi4.scala 128:20] + node _T_33 = eq(io.ahb.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 129:23] + node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 129:42] + node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 129:40] + cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 129:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] when _T_36 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 131:20] - node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 132:39] - node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 132:37] - buf_state_en <= _T_38 @[ahb_to_axi4.scala 132:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 133:20] - node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 134:55] - node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 134:62] - node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 134:41] - buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 134:25] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 132:20] + node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 133:39] + node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 133:37] + buf_state_en <= _T_38 @[ahb_to_axi4.scala 133:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 134:20] + node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 135:55] + node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 135:62] + node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 135:41] + buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 135:25] skip @[Conditional.scala 39:67] - node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 137:99] + node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 138:99] reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_42 : @[Reg.scala 28:19] _T_43 <= buf_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state <= _T_43 @[ahb_to_axi4.scala 137:31] - node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 139:54] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 139:60] + buf_state <= _T_43 @[ahb_to_axi4.scala 138:31] + node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 140:54] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 140:60] node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15] node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 139:92] - node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 139:78] - node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 139:70] - node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 140:24] - node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 140:30] + node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 140:92] + node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 140:78] + node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 140:70] + node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 141:24] + node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 141:30] node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15] node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 140:62] - node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 140:48] - node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 140:40] - node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 139:109] - node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 141:24] - node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 141:30] + node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 141:62] + node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 141:48] + node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 141:40] + node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 140:109] + node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 142:24] + node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 142:30] node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 141:62] - node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 141:48] - node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 141:40] - node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 140:79] - node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 142:24] - node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 142:30] + node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 142:62] + node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 142:48] + node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 142:40] + node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 141:79] + node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 143:24] + node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 143:30] node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15] node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 142:40] - node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 141:79] - master_wstrb <= _T_72 @[ahb_to_axi4.scala 139:31] - node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 145:66] - node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 145:64] - node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 145:84] - node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 145:110] - node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 145:97] - node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 145:135] - node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 145:154] - node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 145:142] - node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 145:123] - node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 145:121] - node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 145:167] - node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 145:165] - node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 145:37] - io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 145:31] - node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 146:51] - ahb_hready <= _T_86 @[ahb_to_axi4.scala 146:31] + node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 143:40] + node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 142:79] + master_wstrb <= _T_72 @[ahb_to_axi4.scala 140:31] + node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 146:72] + node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 146:70] + node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 146:90] + node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 146:116] + node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 146:103] + node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 146:141] + node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 146:160] + node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 146:148] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 146:129] + node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 146:127] + node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 146:173] + node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 146:171] + node _T_85 = mux(io.ahb.in.hresp, _T_74, _T_84) @[ahb_to_axi4.scala 146:40] + io.ahb.in.hready <= _T_85 @[ahb_to_axi4.scala 146:34] + node _T_86 = and(io.ahb.in.hready, io.ahb_hreadyin) @[ahb_to_axi4.scala 147:51] + ahb_hready <= _T_86 @[ahb_to_axi4.scala 147:31] node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15] node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 147:69] - node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 147:54] - ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 147:31] - node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 148:43] - io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 148:31] - node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 149:48] - node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 149:54] - node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 149:76] - node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 149:63] - node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 150:26] - node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 150:7] - node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 151:46] - node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 151:26] - node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 151:80] - node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 151:86] - node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 151:109] - node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 151:115] - node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 151:95] - node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 151:66] - node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 151:64] - node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 150:47] - node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 152:20] - node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 152:26] - node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 152:48] - node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 152:35] - node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 151:126] - node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 153:20] - node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 153:26] - node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 153:49] - node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 153:56] - node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 153:35] - node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 152:55] - node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 154:20] - node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 154:26] - node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 154:49] - node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 154:56] - node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 154:35] - node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 153:61] - node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 149:87] - node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 154:63] - node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 156:20] - node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 156:18] - node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 155:20] - io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 149:31] - reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 159:66] - _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 159:66] - buf_rdata <= _T_130 @[ahb_to_axi4.scala 159:31] - reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 160:60] - _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 160:60] - buf_read_error <= _T_131 @[ahb_to_axi4.scala 160:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 163:60] - _T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 163:60] - ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 163:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60] - _T_133 <= ahb_hready @[ahb_to_axi4.scala 164:60] - ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 164:31] - reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 165:60] - _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 165:60] - ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 165:31] - reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 166:65] - _T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 166:65] - ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 166:31] - reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:65] - _T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 167:65] - ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 167:31] - reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:65] - _T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 168:65] - ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 168:31] - node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 171:77] - node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 171:62] - node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 171:48] - ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 171:31] - node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 172:48] - buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 172:31] + node _T_89 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 148:73] + node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 148:54] + ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 148:31] + node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 149:46] + io.ahb.in.hrdata <= _T_91 @[ahb_to_axi4.scala 149:34] + node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 150:51] + node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 150:57] + node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 150:79] + node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 150:66] + node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 151:26] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 151:7] + node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 152:46] + node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 152:26] + node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:80] + node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 152:86] + node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:109] + node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 152:115] + node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 152:95] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 152:66] + node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 152:64] + node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 151:47] + node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 153:20] + node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 153:26] + node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 153:48] + node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 153:35] + node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 152:126] + node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 154:20] + node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 154:26] + node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 154:49] + node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 154:56] + node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 154:35] + node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 153:55] + node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 155:20] + node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 155:26] + node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 155:49] + node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 155:56] + node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 155:35] + node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 154:61] + node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 150:90] + node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 155:63] + node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 157:20] + node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 157:18] + node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 156:20] + io.ahb.in.hresp <= _T_129 @[ahb_to_axi4.scala 150:34] + reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 160:66] + _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 160:66] + buf_rdata <= _T_130 @[ahb_to_axi4.scala 160:31] + reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 161:60] + _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 161:60] + buf_read_error <= _T_131 @[ahb_to_axi4.scala 161:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60] + _T_132 <= io.ahb.in.hresp @[ahb_to_axi4.scala 164:60] + ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 164:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 165:60] + _T_133 <= ahb_hready @[ahb_to_axi4.scala 165:60] + ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 165:31] + reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 166:60] + _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 166:60] + ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 166:31] + reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:65] + _T_135 <= io.ahb.out.hsize @[ahb_to_axi4.scala 167:65] + ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 167:31] + reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:65] + _T_136 <= io.ahb.out.hwrite @[ahb_to_axi4.scala 168:65] + ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 168:31] + reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:65] + _T_137 <= io.ahb.out.haddr @[ahb_to_axi4.scala 169:65] + ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 169:31] + node _T_138 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 172:81] + node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 172:62] + node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 172:48] + ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 172:31] + node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 173:48] + buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 173:31] inst rvclkhdr of rvclkhdr_877 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 174:31] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 175:31] inst rvclkhdr_1 of rvclkhdr_878 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 175:31] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 176:31] inst rvclkhdr_2 of rvclkhdr_879 @[lib.scala 327:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 328:17] rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 329:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 176:31] - node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 178:52] - node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 178:88] - node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 178:70] - node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 178:109] - node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 178:107] - node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 178:142] - node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 178:140] - node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 178:124] - cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 178:31] - node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 179:66] - node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 179:102] - node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 179:84] - node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 179:48] - node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 179:46] - cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 179:31] - node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 181:86] - node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 181:66] - node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 181:110] - node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 181:108] - reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 181:61] - _T_159 <= _T_158 @[ahb_to_axi4.scala 181:61] - cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 181:31] - node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 185:53] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 177:31] + node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 179:52] + node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 179:88] + node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 179:70] + node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 179:109] + node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 179:107] + node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 179:145] + node _T_148 = and(io.ahb.in.hresp, _T_147) @[ahb_to_axi4.scala 179:143] + node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 179:124] + cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 179:31] + node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 180:66] + node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 180:102] + node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 180:84] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 180:48] + node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 180:46] + cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 180:31] + node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 182:86] + node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 182:66] + node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 182:110] + node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 182:108] + reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 182:61] + _T_159 <= _T_158 @[ahb_to_axi4.scala 182:61] + cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 182:31] + node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 186:53] reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_160 : @[Reg.scala 28:19] _T_161 <= ahb_hwrite_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 184:31] - node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 188:52] + cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 185:31] + node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 189:52] reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_162 : @[Reg.scala 28:19] _T_163 <= ahb_hsize_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 187:31] - node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 191:53] + cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 188:31] + node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 192:53] reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_164 : @[Reg.scala 28:19] _T_165 <= master_wstrb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 190:31] - node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 194:57] + cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 191:31] + node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:57] inst rvclkhdr_3 of rvclkhdr_880 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -113740,8 +113748,8 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_167 <= ahb_haddr_q @[lib.scala 358:16] - cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 194:15] - node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:60] + cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 195:15] + node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 196:64] inst rvclkhdr_4 of rvclkhdr_881 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -113749,953 +113757,986 @@ circuit quasar_wrapper : rvclkhdr_4.io.en <= _T_168 @[lib.scala 355:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_169 <= io.ahb_hwdata @[lib.scala 358:16] - cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 195:16] - node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 198:41] - io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 198:27] - io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 199:27] - io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 200:27] - node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 201:53] + _T_169 <= io.ahb.out.hwdata @[lib.scala 358:16] + cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 196:16] + node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 199:41] + io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 199:27] + io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 200:27] + io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 201:27] + node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 202:53] node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58] - io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 201:27] + io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 202:27] node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 202:27] + io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 203:27] node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 203:27] - io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 204:27] - node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 206:41] - io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 206:27] - io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 207:27] - io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 208:27] - io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 209:27] - io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 211:27] - node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 213:43] - node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 213:41] - io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 213:27] - io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 214:27] - io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 215:27] - node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 216:53] + io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 204:27] + io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 205:27] + node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 207:41] + io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 207:27] + io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 208:27] + io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 209:27] + io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 210:27] + io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 212:27] + node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 214:43] + node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 214:41] + io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 214:27] + io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 215:27] + io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 216:27] + node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 217:53] node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58] - io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 216:27] + io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 217:27] node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 217:27] + io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 218:27] node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 218:27] - io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 219:27] - io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 221:27] + io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 219:27] + io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 220:27] + io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 222:27] inst rvclkhdr_5 of rvclkhdr_882 @[lib.scala 327:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 328:17] rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 329:16] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 224:27] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 225:27] module quasar : input clock : Clock input reset : AsyncReset - output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} + output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip dma_hsel : UInt<1>, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of ifu @[quasar.scala 116:19] + inst ifu of ifu @[quasar.scala 122:19] ifu.clock <= clock ifu.reset <= reset - inst dec of dec @[quasar.scala 117:19] + inst dec of dec @[quasar.scala 123:19] dec.clock <= clock dec.reset <= reset - inst dbg of dbg @[quasar.scala 118:19] + inst dbg of dbg @[quasar.scala 124:19] dbg.clock <= clock dbg.reset <= reset - inst exu of exu @[quasar.scala 119:19] + inst exu of exu @[quasar.scala 125:19] exu.clock <= clock exu.reset <= reset - inst lsu of lsu @[quasar.scala 120:19] + inst lsu of lsu @[quasar.scala 126:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctrl_inst of pic_ctrl @[quasar.scala 121:29] + inst pic_ctrl_inst of pic_ctrl @[quasar.scala 127:29] pic_ctrl_inst.clock <= clock pic_ctrl_inst.reset <= reset - inst dma_ctrl of dma_ctrl @[quasar.scala 122:24] + inst dma_ctrl of dma_ctrl @[quasar.scala 128:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[quasar.scala 124:33] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 124:67] - node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 124:70] - node _T_3 = and(_T, _T_2) @[quasar.scala 124:36] - node _T_4 = asAsyncReset(_T_3) @[quasar.scala 124:99] - io.core_rst_l <= _T_4 @[quasar.scala 124:17] - node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 125:23] - node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 125:50] - node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 125:98] + node _T = asUInt(reset) @[quasar.scala 130:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 130:67] + node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 130:70] + node _T_3 = and(_T, _T_2) @[quasar.scala 130:36] + node _T_4 = asAsyncReset(_T_3) @[quasar.scala 130:99] + io.core_rst_l <= _T_4 @[quasar.scala 130:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 131:23] + node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 131:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 131:98] inst rvclkhdr of rvclkhdr_845 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_7 = bits(active_state, 0, 0) @[quasar.scala 127:49] + node _T_7 = bits(active_state, 0, 0) @[quasar.scala 133:49] inst rvclkhdr_1 of rvclkhdr_846 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 128:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 129:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 130:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 133:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 133:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 133:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 133:18] - ifu.reset <= io.core_rst_l @[quasar.scala 135:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 136:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 137:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 138:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 140:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 141:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 143:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 144:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 144:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 145:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 145:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 145:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 145:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 145:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 145:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 145:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 145:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 145:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 145:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 145:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 145:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 145:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 145:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 145:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 145:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 145:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 145:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 145:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 145:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 145:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 146:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 146:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 146:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 146:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 146:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 146:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 146:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 146:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 146:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 147:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 148:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 149:43] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 150:33] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 151:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 151:51] - dec.reset <= io.core_rst_l @[quasar.scala 154:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 155:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 156:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 157:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 158:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 159:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 160:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 161:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 162:24] - dec.io.core_id <= io.core_id @[quasar.scala 163:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 164:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 165:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 166:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 167:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 167:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 167:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 167:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 168:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 168:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 169:31] - dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 170:18] - dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 170:18] - dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 170:18] - dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 170:18] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 172:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 173:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 174:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 175:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 175:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 176:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 177:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 177:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 178:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 179:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 180:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 181:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 182:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 183:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 184:30] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 185:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 186:26] - dec.io.soft_int <= io.soft_int @[quasar.scala 188:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 189:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 190:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 191:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 192:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 193:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 196:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 196:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 196:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 196:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 196:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 196:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 196:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 196:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 196:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 196:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 196:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 196:18] - exu.reset <= io.core_rst_l @[quasar.scala 197:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 198:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 199:25] - lsu.reset <= io.core_rst_l @[quasar.scala 202:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 203:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 204:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 205:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 206:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 207:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 208:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 208:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 209:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 210:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 210:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 210:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 210:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 210:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 210:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 210:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 210:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 210:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 210:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 210:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 210:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 210:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 211:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 212:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 213:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 213:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 215:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 216:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 216:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 216:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 217:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 218:19] - dbg.reset <= io.core_rst_l @[quasar.scala 221:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 222:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 222:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 223:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 223:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 224:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 224:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 225:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 226:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 227:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 228:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 229:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 230:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 231:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 232:24] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 233:17] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 233:17] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 233:17] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 233:17] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 233:17] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 233:17] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 233:17] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 233:17] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 233:17] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 233:17] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 233:17] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 233:17] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 233:17] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 233:17] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 233:17] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 233:17] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 233:17] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 233:17] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 233:17] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 233:17] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 233:17] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 233:17] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 233:17] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 233:17] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 233:17] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 233:17] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 233:17] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 233:17] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 233:17] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 233:17] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 233:17] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 233:17] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 233:17] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 233:17] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 233:17] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 233:17] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 233:17] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 234:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 235:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 235:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 236:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 237:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 241:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 242:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 243:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 244:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 245:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 246:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 246:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 247:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 247:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 248:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 249:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 250:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 251:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 252:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 253:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 256:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 257:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 258:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 259:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 260:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 261:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 262:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 262:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 263:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 263:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 263:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 263:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 263:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 263:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 265:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 265:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 268:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 269:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 270:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 271:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 272:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 273:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 274:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 275:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 276:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 277:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 278:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 279:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 280:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 281:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 283:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 283:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 283:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 283:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 283:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 283:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 283:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 283:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 283:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 283:11] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 286:14] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 286:14] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 286:14] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 286:14] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 286:14] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 286:14] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 286:14] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 286:14] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 286:14] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 286:14] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 286:14] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 286:14] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 286:14] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 286:14] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 286:14] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 286:14] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 286:14] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 286:14] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 286:14] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 286:14] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 286:14] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 286:14] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 286:14] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 286:14] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 286:14] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 286:14] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 286:14] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 286:14] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 286:14] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 286:14] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 286:14] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 286:14] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 286:14] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 286:14] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 286:14] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 286:14] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 286:14] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 286:14] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 286:14] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 289:14] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 289:14] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 289:14] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 289:14] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 289:14] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 289:14] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 289:14] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 289:14] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 289:14] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 289:14] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 289:14] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 289:14] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 289:14] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 289:14] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 289:14] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 289:14] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 289:14] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 289:14] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 289:14] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 289:14] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 289:14] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 289:14] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 289:14] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 289:14] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 289:14] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 289:14] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 289:14] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 289:14] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 289:14] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 289:14] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 289:14] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 289:14] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 289:14] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 289:14] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 289:14] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 289:14] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 289:14] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 289:14] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 289:14] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 290:14] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 290:14] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 290:14] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 290:14] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 290:14] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 290:14] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 290:14] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 290:14] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 290:14] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 290:14] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 290:14] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 290:14] - when UInt<1>("h00") : @[quasar.scala 296:26] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 297:33] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 134:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 135:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 136:28] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 139:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 139:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 139:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 139:18] + ifu.reset <= io.core_rst_l @[quasar.scala 141:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 142:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 143:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 144:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 146:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 147:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 149:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 150:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 150:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 151:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 151:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 151:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 151:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 151:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 151:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 151:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 151:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 151:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 151:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 151:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 151:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 151:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 151:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 151:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 151:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 151:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 151:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 151:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 151:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 151:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 152:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 152:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 152:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 152:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 152:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 152:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 152:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 152:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 152:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 153:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 154:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 155:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 156:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 157:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 157:51] + dec.reset <= io.core_rst_l @[quasar.scala 160:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 161:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 162:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 163:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 164:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 165:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 166:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 167:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 168:24] + dec.io.core_id <= io.core_id @[quasar.scala 169:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 170:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 171:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 172:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 173:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 173:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 173:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 173:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 174:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 174:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 175:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 176:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 176:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 176:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 176:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 178:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 179:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 180:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 181:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 181:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 182:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 183:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 183:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 184:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 185:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 186:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 187:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 188:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 189:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 190:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 191:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 192:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 194:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 195:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 196:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 197:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 198:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 199:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 202:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 202:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 202:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 202:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 202:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 202:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 202:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 202:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 202:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 202:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 202:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 202:18] + exu.reset <= io.core_rst_l @[quasar.scala 203:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 204:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 205:25] + lsu.reset <= io.core_rst_l @[quasar.scala 208:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 209:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 210:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 211:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 212:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 213:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 214:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 214:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 215:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 216:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 216:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 216:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 216:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 216:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 216:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 216:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 216:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 216:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 216:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 216:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 216:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 216:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 217:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 218:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 219:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 219:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 221:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 222:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 222:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 222:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 223:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 224:19] + dbg.reset <= io.core_rst_l @[quasar.scala 227:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 228:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 228:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 229:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 229:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 230:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 230:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 231:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 232:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 233:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 234:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 235:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 236:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 237:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 238:24] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 239:17] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 239:17] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 239:17] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 239:17] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 239:17] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 239:17] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 239:17] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 239:17] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 239:17] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 239:17] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 239:17] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 239:17] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 239:17] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 239:17] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 239:17] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 239:17] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 239:17] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 239:17] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 239:17] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 239:17] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 239:17] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 239:17] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 239:17] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 239:17] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 239:17] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 239:17] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 239:17] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 239:17] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 239:17] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 239:17] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 239:17] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 239:17] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 239:17] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 239:17] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 239:17] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 239:17] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 239:17] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 240:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 241:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 241:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 242:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 243:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 247:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 248:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 249:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 250:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 251:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 252:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 252:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 253:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 253:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 254:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 255:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 256:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 257:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 258:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 259:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 262:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 263:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 264:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 265:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 266:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 267:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 268:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 268:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 269:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 269:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 269:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 269:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 269:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 269:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 271:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 271:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 274:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 275:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 276:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 277:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 278:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 279:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 280:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 281:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 282:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 283:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 284:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 285:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 286:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 287:23] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 289:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 289:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 289:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 289:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 289:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 289:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 289:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 289:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 289:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 289:11] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 292:14] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 292:14] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 292:14] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 292:14] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 292:14] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 292:14] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 292:14] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 292:14] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 292:14] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 292:14] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 292:14] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 292:14] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 292:14] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 292:14] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 292:14] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 292:14] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 292:14] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 292:14] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 292:14] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 292:14] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 292:14] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 292:14] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 292:14] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 292:14] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 292:14] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 292:14] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 292:14] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 292:14] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 292:14] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 292:14] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 292:14] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 292:14] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 292:14] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 292:14] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 292:14] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 292:14] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 292:14] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 292:14] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 292:14] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 295:14] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 295:14] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 295:14] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 295:14] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 295:14] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 295:14] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 295:14] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 295:14] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 295:14] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 295:14] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 295:14] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 295:14] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 295:14] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 295:14] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 295:14] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 295:14] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 295:14] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 295:14] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 295:14] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 295:14] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 295:14] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 295:14] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 295:14] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 295:14] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 295:14] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 295:14] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 295:14] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 295:14] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 295:14] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 295:14] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 295:14] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 295:14] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 295:14] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 295:14] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 295:14] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 295:14] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 295:14] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 295:14] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 295:14] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 296:14] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 296:14] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 296:14] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 296:14] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 296:14] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 296:14] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 296:14] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 296:14] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 296:14] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 296:14] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 296:14] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 296:14] + when UInt<1>("h00") : @[quasar.scala 302:26] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 303:33] axi4_to_ahb.clock <= clock axi4_to_ahb.reset <= reset - axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 298:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 299:34] - axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 300:35] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 301:37] - axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 302:33] - axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 303:35] - axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 304:35] - axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 305:35] - axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 307:35] - axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 308:34] - axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 309:34] - axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 310:34] - axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 311:35] - axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 313:36] - axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 314:33] - axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 315:35] - axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 316:35] - axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 317:35] - axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 319:35] - axi4_to_ahb.io.ahb_hrdata <= io.lsu_hrdata @[quasar.scala 320:35] - axi4_to_ahb.io.ahb_hready <= io.lsu_hready @[quasar.scala 321:35] - axi4_to_ahb.io.ahb_hresp <= io.lsu_hresp @[quasar.scala 322:34] - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 324:33] + axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 304:36] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 305:34] + axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 306:35] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 307:37] + axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 308:33] + axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 309:35] + axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 310:35] + axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 311:35] + axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 313:35] + axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 314:34] + axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 315:34] + axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 316:34] + axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 317:35] + axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 319:36] + axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 320:33] + axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 321:35] + axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 322:35] + axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 323:35] + axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 325:35] + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 330:33] axi4_to_ahb_1.clock <= clock axi4_to_ahb_1.reset <= reset - axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 325:36] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 326:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 327:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 328:37] - axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 329:33] - axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 330:35] - axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 331:35] - axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 332:35] - axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 334:35] - axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 335:34] - axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 336:34] - axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 337:34] - axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 338:35] - axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 340:36] - axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 341:33] - axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 342:35] - axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 343:35] - axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 344:35] - axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 346:35] - axi4_to_ahb_1.io.ahb_hrdata <= io.hrdata @[quasar.scala 348:35] - axi4_to_ahb_1.io.ahb_hready <= io.hready @[quasar.scala 349:35] - axi4_to_ahb_1.io.ahb_hresp <= io.hresp @[quasar.scala 350:34] - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 352:32] + axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 331:36] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 332:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 333:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 334:37] + axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 335:33] + axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 336:35] + axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 337:35] + axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 338:35] + axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 340:35] + axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 341:34] + axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 342:34] + axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 343:34] + axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 344:35] + axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 346:36] + axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 347:33] + axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 348:35] + axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 349:35] + axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 350:35] + axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 352:35] + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 358:32] axi4_to_ahb_2.clock <= clock axi4_to_ahb_2.reset <= reset - axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 353:35] - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 354:33] - axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 355:34] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 356:36] - axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 357:32] - axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 358:34] - axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 359:34] - axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 360:34] - axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 362:34] - axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 363:33] - axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 364:33] - axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 365:33] - axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 366:34] - axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 368:35] - axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 369:32] - axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 370:34] - axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 371:34] - axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 372:34] - axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 374:34] - axi4_to_ahb_2.io.ahb_hrdata <= io.sb_hrdata @[quasar.scala 375:34] - axi4_to_ahb_2.io.ahb_hready <= io.sb_hready @[quasar.scala 376:34] - axi4_to_ahb_2.io.ahb_hresp <= io.sb_hresp @[quasar.scala 377:33] - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 379:33] + axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 359:35] + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 360:33] + axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 361:34] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 362:36] + axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 363:32] + axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 364:34] + axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 365:34] + axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 366:34] + axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 368:34] + axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 369:33] + axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 370:33] + axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 371:33] + axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 372:34] + axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 374:35] + axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 375:32] + axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 376:34] + axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 377:34] + axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 378:34] + axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 380:34] + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 385:33] ahb_to_axi4.clock <= clock ahb_to_axi4.reset <= reset - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 380:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 381:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 382:37] - ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 383:36] - ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 384:35] - ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 385:35] - ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 386:34] - ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 387:32] - ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 390:36] - ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 391:35] - ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 392:32] - ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 393:34] - ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 394:34] - ahb_to_axi4.io.ahb_haddr <= io.dma_haddr @[quasar.scala 397:34] - ahb_to_axi4.io.ahb_hburst <= io.dma_hburst @[quasar.scala 398:35] - ahb_to_axi4.io.ahb_hmastlock <= io.dma_hmastlock @[quasar.scala 399:38] - ahb_to_axi4.io.ahb_hprot <= io.dma_hprot @[quasar.scala 400:34] - ahb_to_axi4.io.ahb_hsize <= io.dma_hsize @[quasar.scala 401:34] - ahb_to_axi4.io.ahb_htrans <= io.dma_htrans @[quasar.scala 402:35] - ahb_to_axi4.io.ahb_hwrite <= io.dma_hwrite @[quasar.scala 403:35] - ahb_to_axi4.io.ahb_hwdata <= io.dma_hwdata @[quasar.scala 404:35] - ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 405:33] - ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 406:37] - node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 409:31] - lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 409:25] - node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 410:30] - lsu.io.axi.w.ready <= _T_13 @[quasar.scala 410:24] - node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 411:30] - lsu.io.axi.b.valid <= _T_14 @[quasar.scala 411:24] - node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 412:34] - lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 412:28] - node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 413:32] - lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 413:26] - node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 414:31] - lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 414:25] - node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 415:30] - lsu.io.axi.r.valid <= _T_18 @[quasar.scala 415:24] - node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 416:32] - lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 416:26] - node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 417:34] - lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 417:28] - node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 418:34] - lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 418:28] - node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 419:34] - lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 419:28] - node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 421:31] - ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 421:25] - node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 422:30] - ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 422:24] - node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 423:31] - ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 423:25] - node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 424:30] - ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 424:24] - node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 425:32] - ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 425:26] - node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 426:34] - ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 426:28] - node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 427:34] - ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 427:28] - node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 428:34] - ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 428:28] - node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 430:34] - dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 430:28] - node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 431:33] - dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 431:27] - node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 432:33] - dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 432:27] - node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 433:37] - dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 433:31] - node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 434:34] - dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 434:28] - node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 435:33] - dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 435:27] - node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 436:35] - dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 436:29] - node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 437:37] - dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 437:31] - node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 438:37] - dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 438:31] - node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 440:40] - dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 440:34] - node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 441:42] - dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 441:36] - node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 442:44] - dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 442:38] - node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 443:44] - dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 443:38] - node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 444:39] - dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 444:33] - node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 445:43] - dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 445:37] - node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 446:43] - dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 446:37] - node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 447:39] - dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 447:33] - node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 448:40] - dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 448:34] - node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 449:42] - dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 449:36] - node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 450:44] - dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 450:38] - node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 451:44] - dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 451:38] - node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 452:39] - dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 452:33] - io.haddr <= axi4_to_ahb_1.io.ahb_haddr @[quasar.scala 456:14] - io.hburst <= axi4_to_ahb_1.io.ahb_hburst @[quasar.scala 457:15] - io.hmastlock <= axi4_to_ahb_1.io.ahb_hmastlock @[quasar.scala 458:18] - io.hprot <= axi4_to_ahb_1.io.ahb_hprot @[quasar.scala 459:14] - io.hsize <= axi4_to_ahb_1.io.ahb_hsize @[quasar.scala 460:14] - io.htrans <= axi4_to_ahb_1.io.ahb_htrans @[quasar.scala 461:15] - io.hwrite <= axi4_to_ahb_1.io.ahb_hwrite @[quasar.scala 462:15] - io.lsu_haddr <= axi4_to_ahb.io.ahb_haddr @[quasar.scala 465:18] - io.lsu_hburst <= axi4_to_ahb.io.ahb_hburst @[quasar.scala 466:19] - io.lsu_hmastlock <= axi4_to_ahb.io.ahb_hmastlock @[quasar.scala 467:22] - io.lsu_hprot <= axi4_to_ahb.io.ahb_hprot @[quasar.scala 468:18] - io.lsu_hsize <= axi4_to_ahb.io.ahb_hsize @[quasar.scala 469:18] - io.lsu_htrans <= axi4_to_ahb.io.ahb_htrans @[quasar.scala 470:19] - io.lsu_hwrite <= axi4_to_ahb.io.ahb_hwrite @[quasar.scala 471:19] - io.lsu_hwdata <= axi4_to_ahb.io.ahb_hwdata @[quasar.scala 472:19] - io.sb_haddr <= axi4_to_ahb_2.io.ahb_haddr @[quasar.scala 474:17] - io.sb_hburst <= axi4_to_ahb_2.io.ahb_hburst @[quasar.scala 475:18] - io.sb_hmastlock <= axi4_to_ahb_2.io.ahb_hmastlock @[quasar.scala 476:21] - io.sb_hprot <= axi4_to_ahb_2.io.ahb_hprot @[quasar.scala 477:17] - io.sb_hsize <= axi4_to_ahb_2.io.ahb_hsize @[quasar.scala 478:17] - io.sb_htrans <= axi4_to_ahb_2.io.ahb_htrans @[quasar.scala 479:18] - io.sb_hwrite <= axi4_to_ahb_2.io.ahb_hwrite @[quasar.scala 480:18] - io.sb_hwdata <= axi4_to_ahb_2.io.ahb_hwdata @[quasar.scala 481:18] - io.dma_hrdata <= ahb_to_axi4.io.ahb_hrdata @[quasar.scala 483:19] - io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 484:22] - io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 485:18] - skip @[quasar.scala 296:26] - else : @[quasar.scala 487:17] - io.haddr <= UInt<1>("h00") @[quasar.scala 489:18] - io.hburst <= UInt<1>("h00") @[quasar.scala 490:19] - io.hmastlock <= UInt<1>("h00") @[quasar.scala 491:22] - io.hprot <= UInt<1>("h00") @[quasar.scala 492:18] - io.hsize <= UInt<1>("h00") @[quasar.scala 493:18] - io.htrans <= UInt<1>("h00") @[quasar.scala 494:19] - io.hwrite <= UInt<1>("h00") @[quasar.scala 495:19] - io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 498:22] - io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 499:23] - io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 500:26] - io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 501:22] - io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 502:22] - io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 503:23] - io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 504:23] - io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 505:23] - io.sb_haddr <= UInt<1>("h00") @[quasar.scala 507:21] - io.sb_hburst <= UInt<1>("h00") @[quasar.scala 508:22] - io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 509:25] - io.sb_hprot <= UInt<1>("h00") @[quasar.scala 510:21] - io.sb_hsize <= UInt<1>("h00") @[quasar.scala 511:21] - io.sb_htrans <= UInt<1>("h00") @[quasar.scala 512:22] - io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 513:22] - io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 514:22] - io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 516:23] - io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 517:26] - io.dma_hresp <= UInt<1>("h00") @[quasar.scala 518:22] - skip @[quasar.scala 487:17] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 521:20] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 386:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 387:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 388:37] + ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 389:36] + ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 390:35] + ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 391:35] + ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 392:34] + ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 393:32] + ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 396:36] + ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 397:35] + ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 398:32] + ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 399:34] + ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 400:34] + ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 411:33] + ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 412:37] + node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 413:31] + lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 413:25] + node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 414:30] + lsu.io.axi.w.ready <= _T_13 @[quasar.scala 414:24] + node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 415:30] + lsu.io.axi.b.valid <= _T_14 @[quasar.scala 415:24] + node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 416:34] + lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 416:28] + node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 417:32] + lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 417:26] + node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 418:31] + lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 418:25] + node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 419:30] + lsu.io.axi.r.valid <= _T_18 @[quasar.scala 419:24] + node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 420:32] + lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 420:26] + node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 421:34] + lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 421:28] + node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 422:34] + lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 422:28] + node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 423:34] + lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 423:28] + node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 425:31] + ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 425:25] + node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 426:30] + ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 426:24] + node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 427:31] + ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 427:25] + node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 428:30] + ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 428:24] + node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 429:32] + ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 429:26] + node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 430:34] + ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 430:28] + node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 431:34] + ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 431:28] + node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 432:34] + ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 432:28] + node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 434:34] + dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 434:28] + node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 435:33] + dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 435:27] + node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 436:33] + dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 436:27] + node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 437:37] + dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 437:31] + node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 438:34] + dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 438:28] + node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 439:33] + dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 439:27] + node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 440:35] + dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 440:29] + node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 441:37] + dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 441:31] + node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 442:37] + dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 442:31] + node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 444:40] + dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 444:34] + node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 445:42] + dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 445:36] + node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 446:44] + dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 446:38] + node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 447:44] + dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 447:38] + node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 448:39] + dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 448:33] + node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 449:43] + dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 449:37] + node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 450:43] + dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 450:37] + node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 451:39] + dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 451:33] + node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 452:40] + dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 452:34] + node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 453:42] + dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 453:36] + node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 454:44] + dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 454:38] + node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 455:44] + dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 455:38] + node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 456:39] + dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 456:33] + io.ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 458:12] + io.ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 458:12] + io.ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 458:12] + io.ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 458:12] + io.ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 458:12] + io.ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 458:12] + io.ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 458:12] + io.ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ahb.in.hresp @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hready <= io.ahb.in.hready @[quasar.scala 458:12] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ahb.in.hrdata @[quasar.scala 458:12] + io.lsu_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 467:16] + io.lsu_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 467:16] + io.lsu_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 467:16] + io.lsu_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 467:16] + io.lsu_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 467:16] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 467:16] + io.lsu_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 467:16] + io.lsu_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 467:16] + axi4_to_ahb.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 467:16] + io.sb_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 477:15] + io.sb_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 477:15] + io.sb_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 477:15] + io.sb_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 477:15] + io.sb_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 477:15] + io.sb_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 477:15] + io.sb_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 477:15] + io.sb_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 477:15] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 477:15] + ahb_to_axi4.io.ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar.scala 487:16] + ahb_to_axi4.io.ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar.scala 487:16] + io.dma_ahb.in.hresp <= ahb_to_axi4.io.ahb.in.hresp @[quasar.scala 487:16] + io.dma_ahb.in.hready <= ahb_to_axi4.io.ahb.in.hready @[quasar.scala 487:16] + io.dma_ahb.in.hrdata <= ahb_to_axi4.io.ahb.in.hrdata @[quasar.scala 487:16] + skip @[quasar.scala 302:26] + else : @[quasar.scala 494:15] + wire _T_53 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 496:33] + _T_53.hwdata <= UInt<64>("h00") @[quasar.scala 496:33] + _T_53.hwrite <= UInt<1>("h00") @[quasar.scala 496:33] + _T_53.htrans <= UInt<2>("h00") @[quasar.scala 496:33] + _T_53.hsize <= UInt<3>("h00") @[quasar.scala 496:33] + _T_53.hprot <= UInt<4>("h00") @[quasar.scala 496:33] + _T_53.hmastlock <= UInt<1>("h00") @[quasar.scala 496:33] + _T_53.hburst <= UInt<3>("h00") @[quasar.scala 496:33] + _T_53.haddr <= UInt<32>("h00") @[quasar.scala 496:33] + io.ahb.out.hwdata <= _T_53.hwdata @[quasar.scala 496:18] + io.ahb.out.hwrite <= _T_53.hwrite @[quasar.scala 496:18] + io.ahb.out.htrans <= _T_53.htrans @[quasar.scala 496:18] + io.ahb.out.hsize <= _T_53.hsize @[quasar.scala 496:18] + io.ahb.out.hprot <= _T_53.hprot @[quasar.scala 496:18] + io.ahb.out.hmastlock <= _T_53.hmastlock @[quasar.scala 496:18] + io.ahb.out.hburst <= _T_53.hburst @[quasar.scala 496:18] + io.ahb.out.haddr <= _T_53.haddr @[quasar.scala 496:18] + wire _T_54 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 505:37] + _T_54.hwdata <= UInt<64>("h00") @[quasar.scala 505:37] + _T_54.hwrite <= UInt<1>("h00") @[quasar.scala 505:37] + _T_54.htrans <= UInt<2>("h00") @[quasar.scala 505:37] + _T_54.hsize <= UInt<3>("h00") @[quasar.scala 505:37] + _T_54.hprot <= UInt<4>("h00") @[quasar.scala 505:37] + _T_54.hmastlock <= UInt<1>("h00") @[quasar.scala 505:37] + _T_54.hburst <= UInt<3>("h00") @[quasar.scala 505:37] + _T_54.haddr <= UInt<32>("h00") @[quasar.scala 505:37] + io.lsu_ahb.out.hwdata <= _T_54.hwdata @[quasar.scala 505:22] + io.lsu_ahb.out.hwrite <= _T_54.hwrite @[quasar.scala 505:22] + io.lsu_ahb.out.htrans <= _T_54.htrans @[quasar.scala 505:22] + io.lsu_ahb.out.hsize <= _T_54.hsize @[quasar.scala 505:22] + io.lsu_ahb.out.hprot <= _T_54.hprot @[quasar.scala 505:22] + io.lsu_ahb.out.hmastlock <= _T_54.hmastlock @[quasar.scala 505:22] + io.lsu_ahb.out.hburst <= _T_54.hburst @[quasar.scala 505:22] + io.lsu_ahb.out.haddr <= _T_54.haddr @[quasar.scala 505:22] + wire _T_55 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 515:36] + _T_55.hwdata <= UInt<64>("h00") @[quasar.scala 515:36] + _T_55.hwrite <= UInt<1>("h00") @[quasar.scala 515:36] + _T_55.htrans <= UInt<2>("h00") @[quasar.scala 515:36] + _T_55.hsize <= UInt<3>("h00") @[quasar.scala 515:36] + _T_55.hprot <= UInt<4>("h00") @[quasar.scala 515:36] + _T_55.hmastlock <= UInt<1>("h00") @[quasar.scala 515:36] + _T_55.hburst <= UInt<3>("h00") @[quasar.scala 515:36] + _T_55.haddr <= UInt<32>("h00") @[quasar.scala 515:36] + io.sb_ahb.out.hwdata <= _T_55.hwdata @[quasar.scala 515:21] + io.sb_ahb.out.hwrite <= _T_55.hwrite @[quasar.scala 515:21] + io.sb_ahb.out.htrans <= _T_55.htrans @[quasar.scala 515:21] + io.sb_ahb.out.hsize <= _T_55.hsize @[quasar.scala 515:21] + io.sb_ahb.out.hprot <= _T_55.hprot @[quasar.scala 515:21] + io.sb_ahb.out.hmastlock <= _T_55.hmastlock @[quasar.scala 515:21] + io.sb_ahb.out.hburst <= _T_55.hburst @[quasar.scala 515:21] + io.sb_ahb.out.haddr <= _T_55.haddr @[quasar.scala 515:21] + wire _T_56 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar.scala 525:36] + _T_56.hresp <= UInt<1>("h00") @[quasar.scala 525:36] + _T_56.hready <= UInt<1>("h00") @[quasar.scala 525:36] + _T_56.hrdata <= UInt<64>("h00") @[quasar.scala 525:36] + io.dma_ahb.in.hresp <= _T_56.hresp @[quasar.scala 525:21] + io.dma_ahb.in.hready <= _T_56.hready @[quasar.scala 525:21] + io.dma_ahb.in.hrdata <= _T_56.hrdata @[quasar.scala 525:21] + skip @[quasar.scala 494:15] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 530:20] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} - inst mem of mem @[quasar_wrapper.scala 78:19] + inst mem of mem @[quasar_wrapper.scala 79:19] mem.scan_mode is invalid mem.ic is invalid mem.iccm is invalid @@ -114705,7 +114746,7 @@ circuit quasar_wrapper : mem.dccm_clk_override is invalid mem.rst_l is invalid mem.clk is invalid - inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 79:27] + inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 80:27] dmi_wrapper.dmi_hard_reset is invalid dmi_wrapper.reg_wr_en is invalid dmi_wrapper.reg_en is invalid @@ -114721,282 +114762,298 @@ circuit quasar_wrapper : dmi_wrapper.tms is invalid dmi_wrapper.tck is invalid dmi_wrapper.trst_n is invalid - inst core of quasar @[quasar_wrapper.scala 80:20] - core.clock <= clock - core.reset <= reset - dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25] - dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22] - dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22] - dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22] - dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27] - dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26] - dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26] - dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29] - core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:25] - core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:24] - core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:22] - core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:25] - core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:26] - io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15] - mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 99:28] - mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 100:27] - mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35] - core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15] - core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 102:15] - mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 102:15] - mem.rst_l <= reset @[quasar_wrapper.scala 103:16] - mem.clk <= clock @[quasar_wrapper.scala 104:14] - mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:21] - mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 108:14] - mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 108:14] - mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 108:14] - mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 108:14] - mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 108:14] - mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 108:14] - core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:14] - core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:14] - core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:14] - core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:14] - core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:14] - core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:14] - core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:14] - mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 108:14] - mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 108:14] - mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 108:14] - mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 108:14] - mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 108:14] - mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 108:14] - mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 108:14] - mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 108:14] - core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:16] - core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:16] - mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 109:16] - mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 109:16] - mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 109:16] - mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 109:16] - mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 109:16] - mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:16] - mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 109:16] - core.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:21] - core.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:18] - core.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:20] - core.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:22] - core.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:21] - core.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:22] - core.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:18] - core.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:17] - core.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:21] - core.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:21] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] - core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] - core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] - core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19] - core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26] - core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25] - core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19] - core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30] - core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29] - core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29] - core.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:19] - io.lsu_axi.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:19] - io.lsu_axi.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:19] - io.lsu_axi.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:19] - io.lsu_axi.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:19] - io.lsu_axi.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:19] - core.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:19] - core.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:19] - io.ifu_axi.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:19] - io.ifu_axi.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:19] - io.ifu_axi.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:19] - io.ifu_axi.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:19] - io.ifu_axi.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:19] - core.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:19] - core.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:18] - core.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:18] - io.sb_axi.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:18] - io.sb_axi.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:18] - core.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:18] - io.sb_axi.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:18] - io.sb_axi.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:18] - io.sb_axi.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:18] - io.sb_axi.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:18] - core.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:18] - io.dma_axi.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:19] - io.dma_axi.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:19] - io.dma_axi.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 148:19] - core.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:19] - core.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:19] - io.dma_axi.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:19] - io.dma_axi.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:19] - io.dma_axi.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 148:19] - core.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:19] - core.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:19] - core.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:19] - io.dma_axi.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:19] - core.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:20] - core.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:21] - core.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:22] - core.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:25] - core.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:21] - core.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:21] - core.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:22] - core.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:22] - core.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:22] - core.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:24] - core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 162:26] - core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 163:26] - core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 164:26] - core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 165:26] - core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 167:21] - core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 168:20] - core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 169:25] - io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 173:19] - io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 173:19] - io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 176:21] - io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 177:24] - io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 178:20] - io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 179:26] - io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 181:25] - io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 182:24] - io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 183:25] - io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 185:23] - io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 186:23] - io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 187:23] - io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 188:23] - io.dma_hrdata <= core.io.dma_hrdata @[quasar_wrapper.scala 195:17] - io.dma_hreadyout <= core.io.dma_hreadyout @[quasar_wrapper.scala 196:20] - io.dma_hresp <= core.io.dma_hresp @[quasar_wrapper.scala 197:16] + inst swerv of quasar @[quasar_wrapper.scala 81:21] + swerv.clock <= clock + swerv.reset <= reset + dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 82:25] + dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 83:22] + dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 84:22] + dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 85:22] + dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 86:27] + dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 87:26] + dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 88:26] + dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 91:29] + swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 92:26] + swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 93:25] + swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 94:23] + swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 95:26] + swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 96:27] + io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 97:15] + mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 100:28] + mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 101:27] + mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 102:35] + swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 103:15] + swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 103:15] + mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 103:15] + mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 103:15] + mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 103:15] + mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 103:15] + mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 103:15] + mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 103:15] + mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 103:15] + mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 103:15] + mem.rst_l <= reset @[quasar_wrapper.scala 104:16] + mem.clk <= clock @[quasar_wrapper.scala 105:14] + mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 106:20] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 108:22] + mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 109:15] + mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 109:15] + mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 109:15] + mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 109:15] + mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 109:15] + mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 109:15] + swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 109:15] + swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 109:15] + swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 109:15] + swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 109:15] + swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 109:15] + swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 109:15] + swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 109:15] + mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 109:15] + mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 109:15] + mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 109:15] + mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 109:15] + mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 109:15] + mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 109:15] + mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 109:15] + mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 109:15] + swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 110:17] + swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 110:17] + mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 110:17] + mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 110:17] + mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 110:17] + mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 110:17] + mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 110:17] + mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 110:17] + mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 110:17] + wire _T : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 112:39] + _T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:39] + _T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 112:39] + _T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 112:39] + swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 112:24] + swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 112:24] + swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 112:24] + wire _T_1 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 113:39] + _T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 113:39] + _T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 113:39] + _T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 113:39] + swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 113:24] + swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 113:24] + swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 113:24] + wire _T_2 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 114:39] + _T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:39] + _T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 114:39] + _T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 114:39] + swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 114:24] + swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 114:24] + swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 114:24] + wire _T_3 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 115:34] + _T_3.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 115:34] + _T_3.hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:34] + _T_3.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 115:34] + io.dma_ahb.in.hresp <= _T_3.hresp @[quasar_wrapper.scala 115:19] + io.dma_ahb.in.hready <= _T_3.hready @[quasar_wrapper.scala 115:19] + io.dma_ahb.in.hrdata <= _T_3.hrdata @[quasar_wrapper.scala 115:19] + swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 125:22] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 127:22] + swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 128:20] + swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 129:20] + swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 130:20] + swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 133:27] + swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 134:26] + swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 135:20] + swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 138:31] + swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 139:30] + swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 140:30] + swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 144:20] + io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 144:20] + io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 144:20] + io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 144:20] + io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 144:20] + io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 144:20] + swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 144:20] + swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 147:20] + io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 147:20] + io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 147:20] + io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 147:20] + io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 147:20] + io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 147:20] + swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 147:20] + swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 150:19] + io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 150:19] + io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 150:19] + io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 150:19] + io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 150:19] + io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 150:19] + io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 150:19] + swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 150:19] + io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 154:20] + io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 154:20] + io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 154:20] + io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 154:20] + io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 154:20] + io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 154:20] + swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 154:20] + io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 154:20] + swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 157:21] + swerv.io.dma_ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar_wrapper.scala 158:24] + swerv.io.dma_ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar_wrapper.scala 158:24] + swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 167:25] + swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 185:27] + swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 186:27] + swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 187:27] + swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 188:27] + swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 190:22] + swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 191:21] + swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 192:26] + io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 196:19] + io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 196:19] + io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 199:21] + io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 200:24] + io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 201:20] + io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 202:26] + io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 204:25] + io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 205:24] + io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 206:25] + io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 208:23] + io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 209:23] + io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 210:23] + io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 211:23] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 20146a6a..76a2e207 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -46148,7 +46148,7 @@ module dec_decode_ctl( input io_scan_mode, output io_dec_aln_dec_i0_decode_d, input [15:0] io_dec_aln_ifu_i0_cinst, - input [1:0] io_dbg_dctl_dbg_cmd_wrdata + input [31:0] io_dbg_dctl_dbg_cmd_wrdata ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -57392,418 +57392,418 @@ module dec_trigger( wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[lib.scala 89:14] wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[lib.scala 89:14] wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[lib.scala 89:14] - wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_406 = _GEN_0 & _T_405; // @[dec_trigger.scala 15:109] - wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] - wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] - wire _T_411 = ~_T_410; // @[lib.scala 85:39] - wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[lib.scala 85:37] - wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 86:52] - wire _T_416 = _T_412 | _T_415; // @[lib.scala 86:41] - wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] - wire _T_419 = _T_418 & _T_412; // @[lib.scala 88:41] - wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 88:78] - wire _T_423 = _T_419 | _T_422; // @[lib.scala 88:23] - wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_426 = _T_425 & _T_412; // @[lib.scala 88:41] - wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 88:78] - wire _T_430 = _T_426 | _T_429; // @[lib.scala 88:23] - wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_433 = _T_432 & _T_412; // @[lib.scala 88:41] - wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 88:78] - wire _T_437 = _T_433 | _T_436; // @[lib.scala 88:23] - wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_440 = _T_439 & _T_412; // @[lib.scala 88:41] - wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 88:78] - wire _T_444 = _T_440 | _T_443; // @[lib.scala 88:23] - wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_447 = _T_446 & _T_412; // @[lib.scala 88:41] - wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 88:78] - wire _T_451 = _T_447 | _T_450; // @[lib.scala 88:23] - wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_454 = _T_453 & _T_412; // @[lib.scala 88:41] - wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 88:78] - wire _T_458 = _T_454 | _T_457; // @[lib.scala 88:23] - wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_461 = _T_460 & _T_412; // @[lib.scala 88:41] - wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 88:78] - wire _T_465 = _T_461 | _T_464; // @[lib.scala 88:23] - wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_468 = _T_467 & _T_412; // @[lib.scala 88:41] - wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 88:78] - wire _T_472 = _T_468 | _T_471; // @[lib.scala 88:23] - wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_475 = _T_474 & _T_412; // @[lib.scala 88:41] - wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 88:78] - wire _T_479 = _T_475 | _T_478; // @[lib.scala 88:23] - wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_482 = _T_481 & _T_412; // @[lib.scala 88:41] - wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 88:78] - wire _T_486 = _T_482 | _T_485; // @[lib.scala 88:23] - wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_489 = _T_488 & _T_412; // @[lib.scala 88:41] - wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 88:78] - wire _T_493 = _T_489 | _T_492; // @[lib.scala 88:23] - wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_496 = _T_495 & _T_412; // @[lib.scala 88:41] - wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 88:78] - wire _T_500 = _T_496 | _T_499; // @[lib.scala 88:23] - wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_503 = _T_502 & _T_412; // @[lib.scala 88:41] - wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 88:78] - wire _T_507 = _T_503 | _T_506; // @[lib.scala 88:23] - wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_510 = _T_509 & _T_412; // @[lib.scala 88:41] - wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 88:78] - wire _T_514 = _T_510 | _T_513; // @[lib.scala 88:23] - wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_517 = _T_516 & _T_412; // @[lib.scala 88:41] - wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 88:78] - wire _T_521 = _T_517 | _T_520; // @[lib.scala 88:23] - wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_524 = _T_523 & _T_412; // @[lib.scala 88:41] - wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 88:78] - wire _T_528 = _T_524 | _T_527; // @[lib.scala 88:23] - wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_531 = _T_530 & _T_412; // @[lib.scala 88:41] - wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 88:78] - wire _T_535 = _T_531 | _T_534; // @[lib.scala 88:23] - wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_538 = _T_537 & _T_412; // @[lib.scala 88:41] - wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 88:78] - wire _T_542 = _T_538 | _T_541; // @[lib.scala 88:23] - wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_545 = _T_544 & _T_412; // @[lib.scala 88:41] - wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 88:78] - wire _T_549 = _T_545 | _T_548; // @[lib.scala 88:23] - wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_552 = _T_551 & _T_412; // @[lib.scala 88:41] - wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 88:78] - wire _T_556 = _T_552 | _T_555; // @[lib.scala 88:23] - wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_559 = _T_558 & _T_412; // @[lib.scala 88:41] - wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 88:78] - wire _T_563 = _T_559 | _T_562; // @[lib.scala 88:23] - wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_566 = _T_565 & _T_412; // @[lib.scala 88:41] - wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 88:78] - wire _T_570 = _T_566 | _T_569; // @[lib.scala 88:23] - wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_573 = _T_572 & _T_412; // @[lib.scala 88:41] - wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 88:78] - wire _T_577 = _T_573 | _T_576; // @[lib.scala 88:23] - wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_580 = _T_579 & _T_412; // @[lib.scala 88:41] - wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 88:78] - wire _T_584 = _T_580 | _T_583; // @[lib.scala 88:23] - wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_587 = _T_586 & _T_412; // @[lib.scala 88:41] - wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 88:78] - wire _T_591 = _T_587 | _T_590; // @[lib.scala 88:23] - wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_594 = _T_593 & _T_412; // @[lib.scala 88:41] - wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 88:78] - wire _T_598 = _T_594 | _T_597; // @[lib.scala 88:23] - wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_601 = _T_600 & _T_412; // @[lib.scala 88:41] - wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 88:78] - wire _T_605 = _T_601 | _T_604; // @[lib.scala 88:23] - wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_608 = _T_607 & _T_412; // @[lib.scala 88:41] - wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 88:78] - wire _T_612 = _T_608 | _T_611; // @[lib.scala 88:23] - wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_615 = _T_614 & _T_412; // @[lib.scala 88:41] - wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 88:78] - wire _T_619 = _T_615 | _T_618; // @[lib.scala 88:23] - wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_622 = _T_621 & _T_412; // @[lib.scala 88:41] - wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 88:78] - wire _T_626 = _T_622 | _T_625; // @[lib.scala 88:23] - wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_629 = _T_628 & _T_412; // @[lib.scala 88:41] - wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 88:78] - wire _T_633 = _T_629 | _T_632; // @[lib.scala 88:23] - wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[lib.scala 89:14] - wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[lib.scala 89:14] - wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[lib.scala 89:14] - wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[lib.scala 89:14] - wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_665 = _GEN_1 & _T_664; // @[dec_trigger.scala 15:109] - wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] - wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] - wire _T_670 = ~_T_669; // @[lib.scala 85:39] - wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[lib.scala 85:37] - wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 86:52] - wire _T_675 = _T_671 | _T_674; // @[lib.scala 86:41] - wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] - wire _T_678 = _T_677 & _T_671; // @[lib.scala 88:41] - wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 88:78] - wire _T_682 = _T_678 | _T_681; // @[lib.scala 88:23] - wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_685 = _T_684 & _T_671; // @[lib.scala 88:41] - wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 88:78] - wire _T_689 = _T_685 | _T_688; // @[lib.scala 88:23] - wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_692 = _T_691 & _T_671; // @[lib.scala 88:41] - wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 88:78] - wire _T_696 = _T_692 | _T_695; // @[lib.scala 88:23] - wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_699 = _T_698 & _T_671; // @[lib.scala 88:41] - wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 88:78] - wire _T_703 = _T_699 | _T_702; // @[lib.scala 88:23] - wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_706 = _T_705 & _T_671; // @[lib.scala 88:41] - wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 88:78] - wire _T_710 = _T_706 | _T_709; // @[lib.scala 88:23] - wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_713 = _T_712 & _T_671; // @[lib.scala 88:41] - wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 88:78] - wire _T_717 = _T_713 | _T_716; // @[lib.scala 88:23] - wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_720 = _T_719 & _T_671; // @[lib.scala 88:41] - wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 88:78] - wire _T_724 = _T_720 | _T_723; // @[lib.scala 88:23] - wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_727 = _T_726 & _T_671; // @[lib.scala 88:41] - wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 88:78] - wire _T_731 = _T_727 | _T_730; // @[lib.scala 88:23] - wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_734 = _T_733 & _T_671; // @[lib.scala 88:41] - wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 88:78] - wire _T_738 = _T_734 | _T_737; // @[lib.scala 88:23] - wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_741 = _T_740 & _T_671; // @[lib.scala 88:41] - wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 88:78] - wire _T_745 = _T_741 | _T_744; // @[lib.scala 88:23] - wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_748 = _T_747 & _T_671; // @[lib.scala 88:41] - wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 88:78] - wire _T_752 = _T_748 | _T_751; // @[lib.scala 88:23] - wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_755 = _T_754 & _T_671; // @[lib.scala 88:41] - wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 88:78] - wire _T_759 = _T_755 | _T_758; // @[lib.scala 88:23] - wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_762 = _T_761 & _T_671; // @[lib.scala 88:41] - wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 88:78] - wire _T_766 = _T_762 | _T_765; // @[lib.scala 88:23] - wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_769 = _T_768 & _T_671; // @[lib.scala 88:41] - wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 88:78] - wire _T_773 = _T_769 | _T_772; // @[lib.scala 88:23] - wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_776 = _T_775 & _T_671; // @[lib.scala 88:41] - wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 88:78] - wire _T_780 = _T_776 | _T_779; // @[lib.scala 88:23] - wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_783 = _T_782 & _T_671; // @[lib.scala 88:41] - wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 88:78] - wire _T_787 = _T_783 | _T_786; // @[lib.scala 88:23] - wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_790 = _T_789 & _T_671; // @[lib.scala 88:41] - wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 88:78] - wire _T_794 = _T_790 | _T_793; // @[lib.scala 88:23] - wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_797 = _T_796 & _T_671; // @[lib.scala 88:41] - wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 88:78] - wire _T_801 = _T_797 | _T_800; // @[lib.scala 88:23] - wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_804 = _T_803 & _T_671; // @[lib.scala 88:41] - wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 88:78] - wire _T_808 = _T_804 | _T_807; // @[lib.scala 88:23] - wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_811 = _T_810 & _T_671; // @[lib.scala 88:41] - wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 88:78] - wire _T_815 = _T_811 | _T_814; // @[lib.scala 88:23] - wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_818 = _T_817 & _T_671; // @[lib.scala 88:41] - wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 88:78] - wire _T_822 = _T_818 | _T_821; // @[lib.scala 88:23] - wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_825 = _T_824 & _T_671; // @[lib.scala 88:41] - wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 88:78] - wire _T_829 = _T_825 | _T_828; // @[lib.scala 88:23] - wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_832 = _T_831 & _T_671; // @[lib.scala 88:41] - wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 88:78] - wire _T_836 = _T_832 | _T_835; // @[lib.scala 88:23] - wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_839 = _T_838 & _T_671; // @[lib.scala 88:41] - wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 88:78] - wire _T_843 = _T_839 | _T_842; // @[lib.scala 88:23] - wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_846 = _T_845 & _T_671; // @[lib.scala 88:41] - wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 88:78] - wire _T_850 = _T_846 | _T_849; // @[lib.scala 88:23] - wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_853 = _T_852 & _T_671; // @[lib.scala 88:41] - wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 88:78] - wire _T_857 = _T_853 | _T_856; // @[lib.scala 88:23] - wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_860 = _T_859 & _T_671; // @[lib.scala 88:41] - wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 88:78] - wire _T_864 = _T_860 | _T_863; // @[lib.scala 88:23] - wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_867 = _T_866 & _T_671; // @[lib.scala 88:41] - wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 88:78] - wire _T_871 = _T_867 | _T_870; // @[lib.scala 88:23] - wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_874 = _T_873 & _T_671; // @[lib.scala 88:41] - wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 88:78] - wire _T_878 = _T_874 | _T_877; // @[lib.scala 88:23] - wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_881 = _T_880 & _T_671; // @[lib.scala 88:41] - wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 88:78] - wire _T_885 = _T_881 | _T_884; // @[lib.scala 88:23] - wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_888 = _T_887 & _T_671; // @[lib.scala 88:41] - wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 88:78] - wire _T_892 = _T_888 | _T_891; // @[lib.scala 88:23] - wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[lib.scala 89:14] - wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[lib.scala 89:14] - wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[lib.scala 89:14] - wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[lib.scala 89:14] - wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_924 = _GEN_2 & _T_923; // @[dec_trigger.scala 15:109] - wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] - wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] - wire _T_929 = ~_T_928; // @[lib.scala 85:39] - wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[lib.scala 85:37] - wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 86:52] - wire _T_934 = _T_930 | _T_933; // @[lib.scala 86:41] - wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] - wire _T_937 = _T_936 & _T_930; // @[lib.scala 88:41] - wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 88:78] - wire _T_941 = _T_937 | _T_940; // @[lib.scala 88:23] - wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_944 = _T_943 & _T_930; // @[lib.scala 88:41] - wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 88:78] - wire _T_948 = _T_944 | _T_947; // @[lib.scala 88:23] - wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_951 = _T_950 & _T_930; // @[lib.scala 88:41] - wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 88:78] - wire _T_955 = _T_951 | _T_954; // @[lib.scala 88:23] - wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_958 = _T_957 & _T_930; // @[lib.scala 88:41] - wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 88:78] - wire _T_962 = _T_958 | _T_961; // @[lib.scala 88:23] - wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_965 = _T_964 & _T_930; // @[lib.scala 88:41] - wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 88:78] - wire _T_969 = _T_965 | _T_968; // @[lib.scala 88:23] - wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_972 = _T_971 & _T_930; // @[lib.scala 88:41] - wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 88:78] - wire _T_976 = _T_972 | _T_975; // @[lib.scala 88:23] - wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_979 = _T_978 & _T_930; // @[lib.scala 88:41] - wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 88:78] - wire _T_983 = _T_979 | _T_982; // @[lib.scala 88:23] - wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_986 = _T_985 & _T_930; // @[lib.scala 88:41] - wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 88:78] - wire _T_990 = _T_986 | _T_989; // @[lib.scala 88:23] - wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_993 = _T_992 & _T_930; // @[lib.scala 88:41] - wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 88:78] - wire _T_997 = _T_993 | _T_996; // @[lib.scala 88:23] - wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_1000 = _T_999 & _T_930; // @[lib.scala 88:41] - wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 88:78] - wire _T_1004 = _T_1000 | _T_1003; // @[lib.scala 88:23] - wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_1007 = _T_1006 & _T_930; // @[lib.scala 88:41] - wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 88:78] - wire _T_1011 = _T_1007 | _T_1010; // @[lib.scala 88:23] - wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_1014 = _T_1013 & _T_930; // @[lib.scala 88:41] - wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 88:78] - wire _T_1018 = _T_1014 | _T_1017; // @[lib.scala 88:23] - wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_1021 = _T_1020 & _T_930; // @[lib.scala 88:41] - wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 88:78] - wire _T_1025 = _T_1021 | _T_1024; // @[lib.scala 88:23] - wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_1028 = _T_1027 & _T_930; // @[lib.scala 88:41] - wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 88:78] - wire _T_1032 = _T_1028 | _T_1031; // @[lib.scala 88:23] - wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_1035 = _T_1034 & _T_930; // @[lib.scala 88:41] - wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 88:78] - wire _T_1039 = _T_1035 | _T_1038; // @[lib.scala 88:23] - wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_1042 = _T_1041 & _T_930; // @[lib.scala 88:41] - wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 88:78] - wire _T_1046 = _T_1042 | _T_1045; // @[lib.scala 88:23] - wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_1049 = _T_1048 & _T_930; // @[lib.scala 88:41] - wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 88:78] - wire _T_1053 = _T_1049 | _T_1052; // @[lib.scala 88:23] - wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_1056 = _T_1055 & _T_930; // @[lib.scala 88:41] - wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 88:78] - wire _T_1060 = _T_1056 | _T_1059; // @[lib.scala 88:23] - wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_1063 = _T_1062 & _T_930; // @[lib.scala 88:41] - wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 88:78] - wire _T_1067 = _T_1063 | _T_1066; // @[lib.scala 88:23] - wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_1070 = _T_1069 & _T_930; // @[lib.scala 88:41] - wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 88:78] - wire _T_1074 = _T_1070 | _T_1073; // @[lib.scala 88:23] - wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_1077 = _T_1076 & _T_930; // @[lib.scala 88:41] - wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 88:78] - wire _T_1081 = _T_1077 | _T_1080; // @[lib.scala 88:23] - wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_1084 = _T_1083 & _T_930; // @[lib.scala 88:41] - wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 88:78] - wire _T_1088 = _T_1084 | _T_1087; // @[lib.scala 88:23] - wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_1091 = _T_1090 & _T_930; // @[lib.scala 88:41] - wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 88:78] - wire _T_1095 = _T_1091 | _T_1094; // @[lib.scala 88:23] - wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_1098 = _T_1097 & _T_930; // @[lib.scala 88:41] - wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 88:78] - wire _T_1102 = _T_1098 | _T_1101; // @[lib.scala 88:23] - wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_1105 = _T_1104 & _T_930; // @[lib.scala 88:41] - wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 88:78] - wire _T_1109 = _T_1105 | _T_1108; // @[lib.scala 88:23] - wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_1112 = _T_1111 & _T_930; // @[lib.scala 88:41] - wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 88:78] - wire _T_1116 = _T_1112 | _T_1115; // @[lib.scala 88:23] - wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_1119 = _T_1118 & _T_930; // @[lib.scala 88:41] - wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 88:78] - wire _T_1123 = _T_1119 | _T_1122; // @[lib.scala 88:23] - wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_1126 = _T_1125 & _T_930; // @[lib.scala 88:41] - wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 88:78] - wire _T_1130 = _T_1126 | _T_1129; // @[lib.scala 88:23] - wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_1133 = _T_1132 & _T_930; // @[lib.scala 88:41] - wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 88:78] - wire _T_1137 = _T_1133 | _T_1136; // @[lib.scala 88:23] - wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_1140 = _T_1139 & _T_930; // @[lib.scala 88:41] - wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 88:78] - wire _T_1144 = _T_1140 | _T_1143; // @[lib.scala 88:23] - wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_1147 = _T_1146 & _T_930; // @[lib.scala 88:41] - wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 88:78] - wire _T_1151 = _T_1147 | _T_1150; // @[lib.scala 88:23] - wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[lib.scala 89:14] - wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[lib.scala 89:14] - wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[lib.scala 89:14] - wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[lib.scala 89:14] - wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[dec_trigger.scala 15:109] - wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[dec_trigger.scala 15:109] - wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58] - assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[dec_trigger.scala 15:29] + wire _T_406 = &_T_405; // @[lib.scala 89:25] + wire _T_407 = _T_148 & _T_406; // @[dec_trigger.scala 15:109] + wire _T_408 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] + wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] + wire _T_412 = ~_T_411; // @[lib.scala 85:39] + wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[lib.scala 85:37] + wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 86:52] + wire _T_417 = _T_413 | _T_416; // @[lib.scala 86:41] + wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] + wire _T_420 = _T_419 & _T_413; // @[lib.scala 88:41] + wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 88:78] + wire _T_424 = _T_420 | _T_423; // @[lib.scala 88:23] + wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_427 = _T_426 & _T_413; // @[lib.scala 88:41] + wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 88:78] + wire _T_431 = _T_427 | _T_430; // @[lib.scala 88:23] + wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_434 = _T_433 & _T_413; // @[lib.scala 88:41] + wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 88:78] + wire _T_438 = _T_434 | _T_437; // @[lib.scala 88:23] + wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_441 = _T_440 & _T_413; // @[lib.scala 88:41] + wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 88:78] + wire _T_445 = _T_441 | _T_444; // @[lib.scala 88:23] + wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_448 = _T_447 & _T_413; // @[lib.scala 88:41] + wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 88:78] + wire _T_452 = _T_448 | _T_451; // @[lib.scala 88:23] + wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_455 = _T_454 & _T_413; // @[lib.scala 88:41] + wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 88:78] + wire _T_459 = _T_455 | _T_458; // @[lib.scala 88:23] + wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_462 = _T_461 & _T_413; // @[lib.scala 88:41] + wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 88:78] + wire _T_466 = _T_462 | _T_465; // @[lib.scala 88:23] + wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_469 = _T_468 & _T_413; // @[lib.scala 88:41] + wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 88:78] + wire _T_473 = _T_469 | _T_472; // @[lib.scala 88:23] + wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_476 = _T_475 & _T_413; // @[lib.scala 88:41] + wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 88:78] + wire _T_480 = _T_476 | _T_479; // @[lib.scala 88:23] + wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_483 = _T_482 & _T_413; // @[lib.scala 88:41] + wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 88:78] + wire _T_487 = _T_483 | _T_486; // @[lib.scala 88:23] + wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_490 = _T_489 & _T_413; // @[lib.scala 88:41] + wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 88:78] + wire _T_494 = _T_490 | _T_493; // @[lib.scala 88:23] + wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_497 = _T_496 & _T_413; // @[lib.scala 88:41] + wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 88:78] + wire _T_501 = _T_497 | _T_500; // @[lib.scala 88:23] + wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_504 = _T_503 & _T_413; // @[lib.scala 88:41] + wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 88:78] + wire _T_508 = _T_504 | _T_507; // @[lib.scala 88:23] + wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_511 = _T_510 & _T_413; // @[lib.scala 88:41] + wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 88:78] + wire _T_515 = _T_511 | _T_514; // @[lib.scala 88:23] + wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_518 = _T_517 & _T_413; // @[lib.scala 88:41] + wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 88:78] + wire _T_522 = _T_518 | _T_521; // @[lib.scala 88:23] + wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_525 = _T_524 & _T_413; // @[lib.scala 88:41] + wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 88:78] + wire _T_529 = _T_525 | _T_528; // @[lib.scala 88:23] + wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_532 = _T_531 & _T_413; // @[lib.scala 88:41] + wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 88:78] + wire _T_536 = _T_532 | _T_535; // @[lib.scala 88:23] + wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_539 = _T_538 & _T_413; // @[lib.scala 88:41] + wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 88:78] + wire _T_543 = _T_539 | _T_542; // @[lib.scala 88:23] + wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_546 = _T_545 & _T_413; // @[lib.scala 88:41] + wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 88:78] + wire _T_550 = _T_546 | _T_549; // @[lib.scala 88:23] + wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_553 = _T_552 & _T_413; // @[lib.scala 88:41] + wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 88:78] + wire _T_557 = _T_553 | _T_556; // @[lib.scala 88:23] + wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_560 = _T_559 & _T_413; // @[lib.scala 88:41] + wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 88:78] + wire _T_564 = _T_560 | _T_563; // @[lib.scala 88:23] + wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_567 = _T_566 & _T_413; // @[lib.scala 88:41] + wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 88:78] + wire _T_571 = _T_567 | _T_570; // @[lib.scala 88:23] + wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_574 = _T_573 & _T_413; // @[lib.scala 88:41] + wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 88:78] + wire _T_578 = _T_574 | _T_577; // @[lib.scala 88:23] + wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_581 = _T_580 & _T_413; // @[lib.scala 88:41] + wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 88:78] + wire _T_585 = _T_581 | _T_584; // @[lib.scala 88:23] + wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_588 = _T_587 & _T_413; // @[lib.scala 88:41] + wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 88:78] + wire _T_592 = _T_588 | _T_591; // @[lib.scala 88:23] + wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_595 = _T_594 & _T_413; // @[lib.scala 88:41] + wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 88:78] + wire _T_599 = _T_595 | _T_598; // @[lib.scala 88:23] + wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_602 = _T_601 & _T_413; // @[lib.scala 88:41] + wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 88:78] + wire _T_606 = _T_602 | _T_605; // @[lib.scala 88:23] + wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_609 = _T_608 & _T_413; // @[lib.scala 88:41] + wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 88:78] + wire _T_613 = _T_609 | _T_612; // @[lib.scala 88:23] + wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_616 = _T_615 & _T_413; // @[lib.scala 88:41] + wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 88:78] + wire _T_620 = _T_616 | _T_619; // @[lib.scala 88:23] + wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_623 = _T_622 & _T_413; // @[lib.scala 88:41] + wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 88:78] + wire _T_627 = _T_623 | _T_626; // @[lib.scala 88:23] + wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_630 = _T_629 & _T_413; // @[lib.scala 88:41] + wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 88:78] + wire _T_634 = _T_630 | _T_633; // @[lib.scala 88:23] + wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[lib.scala 89:14] + wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[lib.scala 89:14] + wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[lib.scala 89:14] + wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[lib.scala 89:14] + wire _T_666 = &_T_665; // @[lib.scala 89:25] + wire _T_667 = _T_408 & _T_666; // @[dec_trigger.scala 15:109] + wire _T_668 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] + wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] + wire _T_672 = ~_T_671; // @[lib.scala 85:39] + wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[lib.scala 85:37] + wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 86:52] + wire _T_677 = _T_673 | _T_676; // @[lib.scala 86:41] + wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] + wire _T_680 = _T_679 & _T_673; // @[lib.scala 88:41] + wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 88:78] + wire _T_684 = _T_680 | _T_683; // @[lib.scala 88:23] + wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_687 = _T_686 & _T_673; // @[lib.scala 88:41] + wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 88:78] + wire _T_691 = _T_687 | _T_690; // @[lib.scala 88:23] + wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_694 = _T_693 & _T_673; // @[lib.scala 88:41] + wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 88:78] + wire _T_698 = _T_694 | _T_697; // @[lib.scala 88:23] + wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_701 = _T_700 & _T_673; // @[lib.scala 88:41] + wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 88:78] + wire _T_705 = _T_701 | _T_704; // @[lib.scala 88:23] + wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_708 = _T_707 & _T_673; // @[lib.scala 88:41] + wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 88:78] + wire _T_712 = _T_708 | _T_711; // @[lib.scala 88:23] + wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_715 = _T_714 & _T_673; // @[lib.scala 88:41] + wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 88:78] + wire _T_719 = _T_715 | _T_718; // @[lib.scala 88:23] + wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_722 = _T_721 & _T_673; // @[lib.scala 88:41] + wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 88:78] + wire _T_726 = _T_722 | _T_725; // @[lib.scala 88:23] + wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_729 = _T_728 & _T_673; // @[lib.scala 88:41] + wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 88:78] + wire _T_733 = _T_729 | _T_732; // @[lib.scala 88:23] + wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_736 = _T_735 & _T_673; // @[lib.scala 88:41] + wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 88:78] + wire _T_740 = _T_736 | _T_739; // @[lib.scala 88:23] + wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_743 = _T_742 & _T_673; // @[lib.scala 88:41] + wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 88:78] + wire _T_747 = _T_743 | _T_746; // @[lib.scala 88:23] + wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_750 = _T_749 & _T_673; // @[lib.scala 88:41] + wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 88:78] + wire _T_754 = _T_750 | _T_753; // @[lib.scala 88:23] + wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_757 = _T_756 & _T_673; // @[lib.scala 88:41] + wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 88:78] + wire _T_761 = _T_757 | _T_760; // @[lib.scala 88:23] + wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_764 = _T_763 & _T_673; // @[lib.scala 88:41] + wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 88:78] + wire _T_768 = _T_764 | _T_767; // @[lib.scala 88:23] + wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_771 = _T_770 & _T_673; // @[lib.scala 88:41] + wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 88:78] + wire _T_775 = _T_771 | _T_774; // @[lib.scala 88:23] + wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_778 = _T_777 & _T_673; // @[lib.scala 88:41] + wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 88:78] + wire _T_782 = _T_778 | _T_781; // @[lib.scala 88:23] + wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_785 = _T_784 & _T_673; // @[lib.scala 88:41] + wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 88:78] + wire _T_789 = _T_785 | _T_788; // @[lib.scala 88:23] + wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_792 = _T_791 & _T_673; // @[lib.scala 88:41] + wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 88:78] + wire _T_796 = _T_792 | _T_795; // @[lib.scala 88:23] + wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_799 = _T_798 & _T_673; // @[lib.scala 88:41] + wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 88:78] + wire _T_803 = _T_799 | _T_802; // @[lib.scala 88:23] + wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_806 = _T_805 & _T_673; // @[lib.scala 88:41] + wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 88:78] + wire _T_810 = _T_806 | _T_809; // @[lib.scala 88:23] + wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_813 = _T_812 & _T_673; // @[lib.scala 88:41] + wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 88:78] + wire _T_817 = _T_813 | _T_816; // @[lib.scala 88:23] + wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_820 = _T_819 & _T_673; // @[lib.scala 88:41] + wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 88:78] + wire _T_824 = _T_820 | _T_823; // @[lib.scala 88:23] + wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_827 = _T_826 & _T_673; // @[lib.scala 88:41] + wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 88:78] + wire _T_831 = _T_827 | _T_830; // @[lib.scala 88:23] + wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_834 = _T_833 & _T_673; // @[lib.scala 88:41] + wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 88:78] + wire _T_838 = _T_834 | _T_837; // @[lib.scala 88:23] + wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_841 = _T_840 & _T_673; // @[lib.scala 88:41] + wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 88:78] + wire _T_845 = _T_841 | _T_844; // @[lib.scala 88:23] + wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_848 = _T_847 & _T_673; // @[lib.scala 88:41] + wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 88:78] + wire _T_852 = _T_848 | _T_851; // @[lib.scala 88:23] + wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_855 = _T_854 & _T_673; // @[lib.scala 88:41] + wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 88:78] + wire _T_859 = _T_855 | _T_858; // @[lib.scala 88:23] + wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_862 = _T_861 & _T_673; // @[lib.scala 88:41] + wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 88:78] + wire _T_866 = _T_862 | _T_865; // @[lib.scala 88:23] + wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_869 = _T_868 & _T_673; // @[lib.scala 88:41] + wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 88:78] + wire _T_873 = _T_869 | _T_872; // @[lib.scala 88:23] + wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_876 = _T_875 & _T_673; // @[lib.scala 88:41] + wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 88:78] + wire _T_880 = _T_876 | _T_879; // @[lib.scala 88:23] + wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_883 = _T_882 & _T_673; // @[lib.scala 88:41] + wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 88:78] + wire _T_887 = _T_883 | _T_886; // @[lib.scala 88:23] + wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_890 = _T_889 & _T_673; // @[lib.scala 88:41] + wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 88:78] + wire _T_894 = _T_890 | _T_893; // @[lib.scala 88:23] + wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[lib.scala 89:14] + wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[lib.scala 89:14] + wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[lib.scala 89:14] + wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[lib.scala 89:14] + wire _T_926 = &_T_925; // @[lib.scala 89:25] + wire _T_927 = _T_668 & _T_926; // @[dec_trigger.scala 15:109] + wire _T_928 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] + wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] + wire _T_932 = ~_T_931; // @[lib.scala 85:39] + wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[lib.scala 85:37] + wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 86:52] + wire _T_937 = _T_933 | _T_936; // @[lib.scala 86:41] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] + wire _T_940 = _T_939 & _T_933; // @[lib.scala 88:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 88:78] + wire _T_944 = _T_940 | _T_943; // @[lib.scala 88:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_947 = _T_946 & _T_933; // @[lib.scala 88:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 88:78] + wire _T_951 = _T_947 | _T_950; // @[lib.scala 88:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_954 = _T_953 & _T_933; // @[lib.scala 88:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 88:78] + wire _T_958 = _T_954 | _T_957; // @[lib.scala 88:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_961 = _T_960 & _T_933; // @[lib.scala 88:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 88:78] + wire _T_965 = _T_961 | _T_964; // @[lib.scala 88:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_968 = _T_967 & _T_933; // @[lib.scala 88:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 88:78] + wire _T_972 = _T_968 | _T_971; // @[lib.scala 88:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_975 = _T_974 & _T_933; // @[lib.scala 88:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 88:78] + wire _T_979 = _T_975 | _T_978; // @[lib.scala 88:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_982 = _T_981 & _T_933; // @[lib.scala 88:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 88:78] + wire _T_986 = _T_982 | _T_985; // @[lib.scala 88:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_989 = _T_988 & _T_933; // @[lib.scala 88:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 88:78] + wire _T_993 = _T_989 | _T_992; // @[lib.scala 88:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_996 = _T_995 & _T_933; // @[lib.scala 88:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 88:78] + wire _T_1000 = _T_996 | _T_999; // @[lib.scala 88:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_1003 = _T_1002 & _T_933; // @[lib.scala 88:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 88:78] + wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 88:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_1010 = _T_1009 & _T_933; // @[lib.scala 88:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 88:78] + wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 88:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_1017 = _T_1016 & _T_933; // @[lib.scala 88:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 88:78] + wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 88:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_1024 = _T_1023 & _T_933; // @[lib.scala 88:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 88:78] + wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 88:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_1031 = _T_1030 & _T_933; // @[lib.scala 88:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 88:78] + wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 88:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_1038 = _T_1037 & _T_933; // @[lib.scala 88:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 88:78] + wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 88:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_1045 = _T_1044 & _T_933; // @[lib.scala 88:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 88:78] + wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 88:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_1052 = _T_1051 & _T_933; // @[lib.scala 88:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 88:78] + wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 88:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_1059 = _T_1058 & _T_933; // @[lib.scala 88:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 88:78] + wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 88:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_1066 = _T_1065 & _T_933; // @[lib.scala 88:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 88:78] + wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 88:23] + wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_1073 = _T_1072 & _T_933; // @[lib.scala 88:41] + wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 88:78] + wire _T_1077 = _T_1073 | _T_1076; // @[lib.scala 88:23] + wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_1080 = _T_1079 & _T_933; // @[lib.scala 88:41] + wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 88:78] + wire _T_1084 = _T_1080 | _T_1083; // @[lib.scala 88:23] + wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_1087 = _T_1086 & _T_933; // @[lib.scala 88:41] + wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 88:78] + wire _T_1091 = _T_1087 | _T_1090; // @[lib.scala 88:23] + wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_1094 = _T_1093 & _T_933; // @[lib.scala 88:41] + wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 88:78] + wire _T_1098 = _T_1094 | _T_1097; // @[lib.scala 88:23] + wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_1101 = _T_1100 & _T_933; // @[lib.scala 88:41] + wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 88:78] + wire _T_1105 = _T_1101 | _T_1104; // @[lib.scala 88:23] + wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_1108 = _T_1107 & _T_933; // @[lib.scala 88:41] + wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 88:78] + wire _T_1112 = _T_1108 | _T_1111; // @[lib.scala 88:23] + wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_1115 = _T_1114 & _T_933; // @[lib.scala 88:41] + wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 88:78] + wire _T_1119 = _T_1115 | _T_1118; // @[lib.scala 88:23] + wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_1122 = _T_1121 & _T_933; // @[lib.scala 88:41] + wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 88:78] + wire _T_1126 = _T_1122 | _T_1125; // @[lib.scala 88:23] + wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_1129 = _T_1128 & _T_933; // @[lib.scala 88:41] + wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 88:78] + wire _T_1133 = _T_1129 | _T_1132; // @[lib.scala 88:23] + wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_1136 = _T_1135 & _T_933; // @[lib.scala 88:41] + wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 88:78] + wire _T_1140 = _T_1136 | _T_1139; // @[lib.scala 88:23] + wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_1143 = _T_1142 & _T_933; // @[lib.scala 88:41] + wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 88:78] + wire _T_1147 = _T_1143 | _T_1146; // @[lib.scala 88:23] + wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_1150 = _T_1149 & _T_933; // @[lib.scala 88:41] + wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 88:78] + wire _T_1154 = _T_1150 | _T_1153; // @[lib.scala 88:23] + wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[lib.scala 89:14] + wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[lib.scala 89:14] + wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[lib.scala 89:14] + wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[lib.scala 89:14] + wire _T_1186 = &_T_1185; // @[lib.scala 89:25] + wire _T_1187 = _T_928 & _T_1186; // @[dec_trigger.scala 15:109] + wire [2:0] _T_1189 = {_T_1187,_T_927,_T_667}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = {_T_1189,_T_407}; // @[dec_trigger.scala 15:29] endmodule module dec( input clock, @@ -58063,7 +58063,7 @@ module dec( input io_dec_dbg_dbg_ib_dbg_cmd_write, input [1:0] io_dec_dbg_dbg_ib_dbg_cmd_type, input [31:0] io_dec_dbg_dbg_ib_dbg_cmd_addr, - input [1:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, + input [31:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, input io_dec_dma_dctl_dma_dma_dccm_stall_any, input io_dec_dma_tlu_dma_dma_pmu_dccm_read, input io_dec_dma_tlu_dma_dma_pmu_dccm_write, @@ -58292,7 +58292,7 @@ module dec( wire decode_io_scan_mode; // @[dec.scala 118:22] wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] - wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] + wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire gpr_clock; // @[dec.scala 119:19] wire gpr_reset; // @[dec.scala 119:19] wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19] @@ -59408,12 +59408,12 @@ module dbg( output io_dbg_dec_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_dbg_ib_dbg_cmd_valid, output io_dbg_dma_dbg_ib_dbg_cmd_write, output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - output [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, output io_dbg_dma_io_dbg_dma_bubble, input io_dbg_dma_io_dma_dbg_ready, input io_dbg_bus_clk_en, @@ -59952,7 +59952,7 @@ module dbg( assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_504 ? 2'h2 : _T_524; // @[dbg.scala 328:34] assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_504 ? {{1'd0}, _T_506} : _T_508; // @[dbg.scala 324:34] - assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg[1:0]; // @[dbg.scala 325:38] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38] assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] @@ -67327,430 +67327,430 @@ module lsu_trigger( wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[lib.scala 89:14] wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[lib.scala 89:14] wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[lib.scala 89:14] - wire [31:0] _GEN_0 = {{31'd0}, _T_46}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_304 = _GEN_0 & _T_303; // @[lsu_trigger.scala 19:92] - wire _T_307 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_308 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_310 = _T_308 & _T_19; // @[lsu_trigger.scala 19:58] - wire _T_311 = _T_307 | _T_310; // @[lsu_trigger.scala 18:152] - wire _T_312 = _T_40 & _T_311; // @[lsu_trigger.scala 18:94] - wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] - wire _T_316 = ~_T_315; // @[lib.scala 85:39] - wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[lib.scala 85:37] - wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 86:52] - wire _T_321 = _T_317 | _T_320; // @[lib.scala 86:41] - wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] - wire _T_324 = _T_323 & _T_317; // @[lib.scala 88:41] - wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 88:78] - wire _T_328 = _T_324 | _T_327; // @[lib.scala 88:23] - wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_331 = _T_330 & _T_317; // @[lib.scala 88:41] - wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 88:78] - wire _T_335 = _T_331 | _T_334; // @[lib.scala 88:23] - wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_338 = _T_337 & _T_317; // @[lib.scala 88:41] - wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 88:78] - wire _T_342 = _T_338 | _T_341; // @[lib.scala 88:23] - wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_345 = _T_344 & _T_317; // @[lib.scala 88:41] - wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 88:78] - wire _T_349 = _T_345 | _T_348; // @[lib.scala 88:23] - wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_352 = _T_351 & _T_317; // @[lib.scala 88:41] - wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 88:78] - wire _T_356 = _T_352 | _T_355; // @[lib.scala 88:23] - wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_359 = _T_358 & _T_317; // @[lib.scala 88:41] - wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 88:78] - wire _T_363 = _T_359 | _T_362; // @[lib.scala 88:23] - wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_366 = _T_365 & _T_317; // @[lib.scala 88:41] - wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 88:78] - wire _T_370 = _T_366 | _T_369; // @[lib.scala 88:23] - wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_373 = _T_372 & _T_317; // @[lib.scala 88:41] - wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 88:78] - wire _T_377 = _T_373 | _T_376; // @[lib.scala 88:23] - wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_380 = _T_379 & _T_317; // @[lib.scala 88:41] - wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 88:78] - wire _T_384 = _T_380 | _T_383; // @[lib.scala 88:23] - wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_387 = _T_386 & _T_317; // @[lib.scala 88:41] - wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 88:78] - wire _T_391 = _T_387 | _T_390; // @[lib.scala 88:23] - wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_394 = _T_393 & _T_317; // @[lib.scala 88:41] - wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 88:78] - wire _T_398 = _T_394 | _T_397; // @[lib.scala 88:23] - wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_401 = _T_400 & _T_317; // @[lib.scala 88:41] - wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 88:78] - wire _T_405 = _T_401 | _T_404; // @[lib.scala 88:23] - wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_408 = _T_407 & _T_317; // @[lib.scala 88:41] - wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 88:78] - wire _T_412 = _T_408 | _T_411; // @[lib.scala 88:23] - wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_415 = _T_414 & _T_317; // @[lib.scala 88:41] - wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 88:78] - wire _T_419 = _T_415 | _T_418; // @[lib.scala 88:23] - wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_422 = _T_421 & _T_317; // @[lib.scala 88:41] - wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 88:78] - wire _T_426 = _T_422 | _T_425; // @[lib.scala 88:23] - wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_429 = _T_428 & _T_317; // @[lib.scala 88:41] - wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 88:78] - wire _T_433 = _T_429 | _T_432; // @[lib.scala 88:23] - wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_436 = _T_435 & _T_317; // @[lib.scala 88:41] - wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 88:78] - wire _T_440 = _T_436 | _T_439; // @[lib.scala 88:23] - wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_443 = _T_442 & _T_317; // @[lib.scala 88:41] - wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 88:78] - wire _T_447 = _T_443 | _T_446; // @[lib.scala 88:23] - wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_450 = _T_449 & _T_317; // @[lib.scala 88:41] - wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 88:78] - wire _T_454 = _T_450 | _T_453; // @[lib.scala 88:23] - wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_457 = _T_456 & _T_317; // @[lib.scala 88:41] - wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 88:78] - wire _T_461 = _T_457 | _T_460; // @[lib.scala 88:23] - wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_464 = _T_463 & _T_317; // @[lib.scala 88:41] - wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 88:78] - wire _T_468 = _T_464 | _T_467; // @[lib.scala 88:23] - wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_471 = _T_470 & _T_317; // @[lib.scala 88:41] - wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 88:78] - wire _T_475 = _T_471 | _T_474; // @[lib.scala 88:23] - wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_478 = _T_477 & _T_317; // @[lib.scala 88:41] - wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 88:78] - wire _T_482 = _T_478 | _T_481; // @[lib.scala 88:23] - wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_485 = _T_484 & _T_317; // @[lib.scala 88:41] - wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 88:78] - wire _T_489 = _T_485 | _T_488; // @[lib.scala 88:23] - wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_492 = _T_491 & _T_317; // @[lib.scala 88:41] - wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 88:78] - wire _T_496 = _T_492 | _T_495; // @[lib.scala 88:23] - wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_499 = _T_498 & _T_317; // @[lib.scala 88:41] - wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 88:78] - wire _T_503 = _T_499 | _T_502; // @[lib.scala 88:23] - wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_506 = _T_505 & _T_317; // @[lib.scala 88:41] - wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 88:78] - wire _T_510 = _T_506 | _T_509; // @[lib.scala 88:23] - wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_513 = _T_512 & _T_317; // @[lib.scala 88:41] - wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 88:78] - wire _T_517 = _T_513 | _T_516; // @[lib.scala 88:23] - wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_520 = _T_519 & _T_317; // @[lib.scala 88:41] - wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 88:78] - wire _T_524 = _T_520 | _T_523; // @[lib.scala 88:23] - wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_527 = _T_526 & _T_317; // @[lib.scala 88:41] - wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 88:78] - wire _T_531 = _T_527 | _T_530; // @[lib.scala 88:23] - wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_534 = _T_533 & _T_317; // @[lib.scala 88:41] - wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 88:78] - wire _T_538 = _T_534 | _T_537; // @[lib.scala 88:23] - wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[lib.scala 89:14] - wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[lib.scala 89:14] - wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[lib.scala 89:14] - wire [31:0] _T_569 = {_T_538,_T_531,_T_524,_T_517,_T_510,_T_503,_T_496,_T_489,_T_560,_T_553}; // @[lib.scala 89:14] - wire [31:0] _GEN_1 = {{31'd0}, _T_312}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_570 = _GEN_1 & _T_569; // @[lsu_trigger.scala 19:92] - wire _T_573 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_574 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_576 = _T_574 & _T_26; // @[lsu_trigger.scala 19:58] - wire _T_577 = _T_573 | _T_576; // @[lsu_trigger.scala 18:152] - wire _T_578 = _T_40 & _T_577; // @[lsu_trigger.scala 18:94] - wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] - wire _T_582 = ~_T_581; // @[lib.scala 85:39] - wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[lib.scala 85:37] - wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 86:52] - wire _T_587 = _T_583 | _T_586; // @[lib.scala 86:41] - wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] - wire _T_590 = _T_589 & _T_583; // @[lib.scala 88:41] - wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 88:78] - wire _T_594 = _T_590 | _T_593; // @[lib.scala 88:23] - wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_597 = _T_596 & _T_583; // @[lib.scala 88:41] - wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 88:78] - wire _T_601 = _T_597 | _T_600; // @[lib.scala 88:23] - wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_604 = _T_603 & _T_583; // @[lib.scala 88:41] - wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 88:78] - wire _T_608 = _T_604 | _T_607; // @[lib.scala 88:23] - wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_611 = _T_610 & _T_583; // @[lib.scala 88:41] - wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 88:78] - wire _T_615 = _T_611 | _T_614; // @[lib.scala 88:23] - wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_618 = _T_617 & _T_583; // @[lib.scala 88:41] - wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 88:78] - wire _T_622 = _T_618 | _T_621; // @[lib.scala 88:23] - wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_625 = _T_624 & _T_583; // @[lib.scala 88:41] - wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 88:78] - wire _T_629 = _T_625 | _T_628; // @[lib.scala 88:23] - wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_632 = _T_631 & _T_583; // @[lib.scala 88:41] - wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 88:78] - wire _T_636 = _T_632 | _T_635; // @[lib.scala 88:23] - wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_639 = _T_638 & _T_583; // @[lib.scala 88:41] - wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 88:78] - wire _T_643 = _T_639 | _T_642; // @[lib.scala 88:23] - wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_646 = _T_645 & _T_583; // @[lib.scala 88:41] - wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 88:78] - wire _T_650 = _T_646 | _T_649; // @[lib.scala 88:23] - wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_653 = _T_652 & _T_583; // @[lib.scala 88:41] - wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 88:78] - wire _T_657 = _T_653 | _T_656; // @[lib.scala 88:23] - wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_660 = _T_659 & _T_583; // @[lib.scala 88:41] - wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 88:78] - wire _T_664 = _T_660 | _T_663; // @[lib.scala 88:23] - wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_667 = _T_666 & _T_583; // @[lib.scala 88:41] - wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 88:78] - wire _T_671 = _T_667 | _T_670; // @[lib.scala 88:23] - wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_674 = _T_673 & _T_583; // @[lib.scala 88:41] - wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 88:78] - wire _T_678 = _T_674 | _T_677; // @[lib.scala 88:23] - wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_681 = _T_680 & _T_583; // @[lib.scala 88:41] - wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 88:78] - wire _T_685 = _T_681 | _T_684; // @[lib.scala 88:23] - wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_688 = _T_687 & _T_583; // @[lib.scala 88:41] - wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 88:78] - wire _T_692 = _T_688 | _T_691; // @[lib.scala 88:23] - wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_695 = _T_694 & _T_583; // @[lib.scala 88:41] - wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 88:78] - wire _T_699 = _T_695 | _T_698; // @[lib.scala 88:23] - wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_702 = _T_701 & _T_583; // @[lib.scala 88:41] - wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 88:78] - wire _T_706 = _T_702 | _T_705; // @[lib.scala 88:23] - wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_709 = _T_708 & _T_583; // @[lib.scala 88:41] - wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 88:78] - wire _T_713 = _T_709 | _T_712; // @[lib.scala 88:23] - wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_716 = _T_715 & _T_583; // @[lib.scala 88:41] - wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 88:78] - wire _T_720 = _T_716 | _T_719; // @[lib.scala 88:23] - wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_723 = _T_722 & _T_583; // @[lib.scala 88:41] - wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 88:78] - wire _T_727 = _T_723 | _T_726; // @[lib.scala 88:23] - wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_730 = _T_729 & _T_583; // @[lib.scala 88:41] - wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 88:78] - wire _T_734 = _T_730 | _T_733; // @[lib.scala 88:23] - wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_737 = _T_736 & _T_583; // @[lib.scala 88:41] - wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 88:78] - wire _T_741 = _T_737 | _T_740; // @[lib.scala 88:23] - wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_744 = _T_743 & _T_583; // @[lib.scala 88:41] - wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 88:78] - wire _T_748 = _T_744 | _T_747; // @[lib.scala 88:23] - wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_751 = _T_750 & _T_583; // @[lib.scala 88:41] - wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 88:78] - wire _T_755 = _T_751 | _T_754; // @[lib.scala 88:23] - wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_758 = _T_757 & _T_583; // @[lib.scala 88:41] - wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 88:78] - wire _T_762 = _T_758 | _T_761; // @[lib.scala 88:23] - wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_765 = _T_764 & _T_583; // @[lib.scala 88:41] - wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 88:78] - wire _T_769 = _T_765 | _T_768; // @[lib.scala 88:23] - wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_772 = _T_771 & _T_583; // @[lib.scala 88:41] - wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 88:78] - wire _T_776 = _T_772 | _T_775; // @[lib.scala 88:23] - wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_779 = _T_778 & _T_583; // @[lib.scala 88:41] - wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 88:78] - wire _T_783 = _T_779 | _T_782; // @[lib.scala 88:23] - wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_786 = _T_785 & _T_583; // @[lib.scala 88:41] - wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 88:78] - wire _T_790 = _T_786 | _T_789; // @[lib.scala 88:23] - wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_793 = _T_792 & _T_583; // @[lib.scala 88:41] - wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 88:78] - wire _T_797 = _T_793 | _T_796; // @[lib.scala 88:23] - wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_800 = _T_799 & _T_583; // @[lib.scala 88:41] - wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 88:78] - wire _T_804 = _T_800 | _T_803; // @[lib.scala 88:23] - wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[lib.scala 89:14] - wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[lib.scala 89:14] - wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[lib.scala 89:14] - wire [31:0] _T_835 = {_T_804,_T_797,_T_790,_T_783,_T_776,_T_769,_T_762,_T_755,_T_826,_T_819}; // @[lib.scala 89:14] - wire [31:0] _GEN_2 = {{31'd0}, _T_578}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_836 = _GEN_2 & _T_835; // @[lsu_trigger.scala 19:92] - wire _T_839 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] - wire _T_840 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] - wire _T_842 = _T_840 & _T_33; // @[lsu_trigger.scala 19:58] - wire _T_843 = _T_839 | _T_842; // @[lsu_trigger.scala 18:152] - wire _T_844 = _T_40 & _T_843; // @[lsu_trigger.scala 18:94] - wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] - wire _T_848 = ~_T_847; // @[lib.scala 85:39] - wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[lib.scala 85:37] - wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 86:52] - wire _T_853 = _T_849 | _T_852; // @[lib.scala 86:41] - wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] - wire _T_856 = _T_855 & _T_849; // @[lib.scala 88:41] - wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 88:78] - wire _T_860 = _T_856 | _T_859; // @[lib.scala 88:23] - wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] - wire _T_863 = _T_862 & _T_849; // @[lib.scala 88:41] - wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 88:78] - wire _T_867 = _T_863 | _T_866; // @[lib.scala 88:23] - wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] - wire _T_870 = _T_869 & _T_849; // @[lib.scala 88:41] - wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 88:78] - wire _T_874 = _T_870 | _T_873; // @[lib.scala 88:23] - wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] - wire _T_877 = _T_876 & _T_849; // @[lib.scala 88:41] - wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 88:78] - wire _T_881 = _T_877 | _T_880; // @[lib.scala 88:23] - wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] - wire _T_884 = _T_883 & _T_849; // @[lib.scala 88:41] - wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 88:78] - wire _T_888 = _T_884 | _T_887; // @[lib.scala 88:23] - wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] - wire _T_891 = _T_890 & _T_849; // @[lib.scala 88:41] - wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 88:78] - wire _T_895 = _T_891 | _T_894; // @[lib.scala 88:23] - wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] - wire _T_898 = _T_897 & _T_849; // @[lib.scala 88:41] - wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 88:78] - wire _T_902 = _T_898 | _T_901; // @[lib.scala 88:23] - wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] - wire _T_905 = _T_904 & _T_849; // @[lib.scala 88:41] - wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 88:78] - wire _T_909 = _T_905 | _T_908; // @[lib.scala 88:23] - wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] - wire _T_912 = _T_911 & _T_849; // @[lib.scala 88:41] - wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 88:78] - wire _T_916 = _T_912 | _T_915; // @[lib.scala 88:23] - wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] - wire _T_919 = _T_918 & _T_849; // @[lib.scala 88:41] - wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 88:78] - wire _T_923 = _T_919 | _T_922; // @[lib.scala 88:23] - wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] - wire _T_926 = _T_925 & _T_849; // @[lib.scala 88:41] - wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 88:78] - wire _T_930 = _T_926 | _T_929; // @[lib.scala 88:23] - wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] - wire _T_933 = _T_932 & _T_849; // @[lib.scala 88:41] - wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 88:78] - wire _T_937 = _T_933 | _T_936; // @[lib.scala 88:23] - wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] - wire _T_940 = _T_939 & _T_849; // @[lib.scala 88:41] - wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 88:78] - wire _T_944 = _T_940 | _T_943; // @[lib.scala 88:23] - wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] - wire _T_947 = _T_946 & _T_849; // @[lib.scala 88:41] - wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 88:78] - wire _T_951 = _T_947 | _T_950; // @[lib.scala 88:23] - wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] - wire _T_954 = _T_953 & _T_849; // @[lib.scala 88:41] - wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 88:78] - wire _T_958 = _T_954 | _T_957; // @[lib.scala 88:23] - wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] - wire _T_961 = _T_960 & _T_849; // @[lib.scala 88:41] - wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 88:78] - wire _T_965 = _T_961 | _T_964; // @[lib.scala 88:23] - wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] - wire _T_968 = _T_967 & _T_849; // @[lib.scala 88:41] - wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 88:78] - wire _T_972 = _T_968 | _T_971; // @[lib.scala 88:23] - wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] - wire _T_975 = _T_974 & _T_849; // @[lib.scala 88:41] - wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 88:78] - wire _T_979 = _T_975 | _T_978; // @[lib.scala 88:23] - wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] - wire _T_982 = _T_981 & _T_849; // @[lib.scala 88:41] - wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 88:78] - wire _T_986 = _T_982 | _T_985; // @[lib.scala 88:23] - wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] - wire _T_989 = _T_988 & _T_849; // @[lib.scala 88:41] - wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 88:78] - wire _T_993 = _T_989 | _T_992; // @[lib.scala 88:23] - wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] - wire _T_996 = _T_995 & _T_849; // @[lib.scala 88:41] - wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 88:78] - wire _T_1000 = _T_996 | _T_999; // @[lib.scala 88:23] - wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] - wire _T_1003 = _T_1002 & _T_849; // @[lib.scala 88:41] - wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 88:78] - wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 88:23] - wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] - wire _T_1010 = _T_1009 & _T_849; // @[lib.scala 88:41] - wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 88:78] - wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 88:23] - wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] - wire _T_1017 = _T_1016 & _T_849; // @[lib.scala 88:41] - wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 88:78] - wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 88:23] - wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] - wire _T_1024 = _T_1023 & _T_849; // @[lib.scala 88:41] - wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 88:78] - wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 88:23] - wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] - wire _T_1031 = _T_1030 & _T_849; // @[lib.scala 88:41] - wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 88:78] - wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 88:23] - wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] - wire _T_1038 = _T_1037 & _T_849; // @[lib.scala 88:41] - wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 88:78] - wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 88:23] - wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] - wire _T_1045 = _T_1044 & _T_849; // @[lib.scala 88:41] - wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 88:78] - wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 88:23] - wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] - wire _T_1052 = _T_1051 & _T_849; // @[lib.scala 88:41] - wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 88:78] - wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 88:23] - wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] - wire _T_1059 = _T_1058 & _T_849; // @[lib.scala 88:41] - wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 88:78] - wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 88:23] - wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] - wire _T_1066 = _T_1065 & _T_849; // @[lib.scala 88:41] - wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 88:78] - wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 88:23] - wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[lib.scala 89:14] - wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[lib.scala 89:14] - wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[lib.scala 89:14] - wire [31:0] _T_1101 = {_T_1070,_T_1063,_T_1056,_T_1049,_T_1042,_T_1035,_T_1028,_T_1021,_T_1092,_T_1085}; // @[lib.scala 89:14] - wire [31:0] _GEN_3 = {{31'd0}, _T_844}; // @[lsu_trigger.scala 19:92] - wire [31:0] _T_1102 = _GEN_3 & _T_1101; // @[lsu_trigger.scala 19:92] - wire [127:0] _T_1105 = {_T_1102,_T_836,_T_570,_T_304}; // @[Cat.scala 29:58] - assign io_lsu_trigger_match_m = _T_1105[3:0]; // @[lsu_trigger.scala 18:26] + wire _T_304 = &_T_303; // @[lib.scala 89:25] + wire _T_305 = _T_46 & _T_304; // @[lsu_trigger.scala 19:92] + wire _T_308 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_309 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_311 = _T_309 & _T_19; // @[lsu_trigger.scala 19:58] + wire _T_312 = _T_308 | _T_311; // @[lsu_trigger.scala 18:152] + wire _T_313 = _T_40 & _T_312; // @[lsu_trigger.scala 18:94] + wire _T_316 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 85:45] + wire _T_317 = ~_T_316; // @[lib.scala 85:39] + wire _T_318 = io_trigger_pkt_any_1_match_pkt & _T_317; // @[lib.scala 85:37] + wire _T_321 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 86:52] + wire _T_322 = _T_318 | _T_321; // @[lib.scala 86:41] + wire _T_324 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 88:36] + wire _T_325 = _T_324 & _T_318; // @[lib.scala 88:41] + wire _T_328 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 88:78] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 88:23] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_332 = _T_331 & _T_318; // @[lib.scala 88:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 88:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 88:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_339 = _T_338 & _T_318; // @[lib.scala 88:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 88:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 88:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_346 = _T_345 & _T_318; // @[lib.scala 88:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 88:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 88:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_353 = _T_352 & _T_318; // @[lib.scala 88:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 88:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 88:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_360 = _T_359 & _T_318; // @[lib.scala 88:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 88:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 88:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_367 = _T_366 & _T_318; // @[lib.scala 88:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 88:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 88:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_374 = _T_373 & _T_318; // @[lib.scala 88:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 88:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 88:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_381 = _T_380 & _T_318; // @[lib.scala 88:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 88:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 88:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_388 = _T_387 & _T_318; // @[lib.scala 88:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 88:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 88:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_395 = _T_394 & _T_318; // @[lib.scala 88:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 88:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 88:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_402 = _T_401 & _T_318; // @[lib.scala 88:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 88:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 88:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_409 = _T_408 & _T_318; // @[lib.scala 88:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 88:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 88:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_416 = _T_415 & _T_318; // @[lib.scala 88:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 88:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 88:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_423 = _T_422 & _T_318; // @[lib.scala 88:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 88:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 88:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_430 = _T_429 & _T_318; // @[lib.scala 88:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 88:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 88:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_437 = _T_436 & _T_318; // @[lib.scala 88:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 88:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 88:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_444 = _T_443 & _T_318; // @[lib.scala 88:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 88:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 88:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_451 = _T_450 & _T_318; // @[lib.scala 88:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 88:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 88:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_458 = _T_457 & _T_318; // @[lib.scala 88:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 88:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 88:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_465 = _T_464 & _T_318; // @[lib.scala 88:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 88:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 88:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_472 = _T_471 & _T_318; // @[lib.scala 88:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 88:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 88:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_479 = _T_478 & _T_318; // @[lib.scala 88:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 88:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 88:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_486 = _T_485 & _T_318; // @[lib.scala 88:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 88:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 88:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_493 = _T_492 & _T_318; // @[lib.scala 88:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 88:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 88:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_500 = _T_499 & _T_318; // @[lib.scala 88:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 88:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 88:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_507 = _T_506 & _T_318; // @[lib.scala 88:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 88:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 88:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_514 = _T_513 & _T_318; // @[lib.scala 88:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 88:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 88:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_521 = _T_520 & _T_318; // @[lib.scala 88:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 88:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 88:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_528 = _T_527 & _T_318; // @[lib.scala 88:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 88:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 88:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_535 = _T_534 & _T_318; // @[lib.scala 88:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 88:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 88:23] + wire [7:0] _T_546 = {_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329,_T_322}; // @[lib.scala 89:14] + wire [15:0] _T_554 = {_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_378,_T_546}; // @[lib.scala 89:14] + wire [7:0] _T_561 = {_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441,_T_434}; // @[lib.scala 89:14] + wire [31:0] _T_570 = {_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_490,_T_561,_T_554}; // @[lib.scala 89:14] + wire _T_571 = &_T_570; // @[lib.scala 89:25] + wire _T_572 = _T_313 & _T_571; // @[lsu_trigger.scala 19:92] + wire _T_575 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_576 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_578 = _T_576 & _T_26; // @[lsu_trigger.scala 19:58] + wire _T_579 = _T_575 | _T_578; // @[lsu_trigger.scala 18:152] + wire _T_580 = _T_40 & _T_579; // @[lsu_trigger.scala 18:94] + wire _T_583 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 85:45] + wire _T_584 = ~_T_583; // @[lib.scala 85:39] + wire _T_585 = io_trigger_pkt_any_2_match_pkt & _T_584; // @[lib.scala 85:37] + wire _T_588 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 86:52] + wire _T_589 = _T_585 | _T_588; // @[lib.scala 86:41] + wire _T_591 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 88:36] + wire _T_592 = _T_591 & _T_585; // @[lib.scala 88:41] + wire _T_595 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 88:78] + wire _T_596 = _T_592 | _T_595; // @[lib.scala 88:23] + wire _T_598 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_599 = _T_598 & _T_585; // @[lib.scala 88:41] + wire _T_602 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 88:78] + wire _T_603 = _T_599 | _T_602; // @[lib.scala 88:23] + wire _T_605 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_606 = _T_605 & _T_585; // @[lib.scala 88:41] + wire _T_609 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 88:78] + wire _T_610 = _T_606 | _T_609; // @[lib.scala 88:23] + wire _T_612 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_613 = _T_612 & _T_585; // @[lib.scala 88:41] + wire _T_616 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 88:78] + wire _T_617 = _T_613 | _T_616; // @[lib.scala 88:23] + wire _T_619 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_620 = _T_619 & _T_585; // @[lib.scala 88:41] + wire _T_623 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 88:78] + wire _T_624 = _T_620 | _T_623; // @[lib.scala 88:23] + wire _T_626 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_627 = _T_626 & _T_585; // @[lib.scala 88:41] + wire _T_630 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 88:78] + wire _T_631 = _T_627 | _T_630; // @[lib.scala 88:23] + wire _T_633 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_634 = _T_633 & _T_585; // @[lib.scala 88:41] + wire _T_637 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 88:78] + wire _T_638 = _T_634 | _T_637; // @[lib.scala 88:23] + wire _T_640 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_641 = _T_640 & _T_585; // @[lib.scala 88:41] + wire _T_644 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 88:78] + wire _T_645 = _T_641 | _T_644; // @[lib.scala 88:23] + wire _T_647 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_648 = _T_647 & _T_585; // @[lib.scala 88:41] + wire _T_651 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 88:78] + wire _T_652 = _T_648 | _T_651; // @[lib.scala 88:23] + wire _T_654 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_655 = _T_654 & _T_585; // @[lib.scala 88:41] + wire _T_658 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 88:78] + wire _T_659 = _T_655 | _T_658; // @[lib.scala 88:23] + wire _T_661 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_662 = _T_661 & _T_585; // @[lib.scala 88:41] + wire _T_665 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 88:78] + wire _T_666 = _T_662 | _T_665; // @[lib.scala 88:23] + wire _T_668 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_669 = _T_668 & _T_585; // @[lib.scala 88:41] + wire _T_672 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 88:78] + wire _T_673 = _T_669 | _T_672; // @[lib.scala 88:23] + wire _T_675 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_676 = _T_675 & _T_585; // @[lib.scala 88:41] + wire _T_679 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 88:78] + wire _T_680 = _T_676 | _T_679; // @[lib.scala 88:23] + wire _T_682 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_683 = _T_682 & _T_585; // @[lib.scala 88:41] + wire _T_686 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 88:78] + wire _T_687 = _T_683 | _T_686; // @[lib.scala 88:23] + wire _T_689 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_690 = _T_689 & _T_585; // @[lib.scala 88:41] + wire _T_693 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 88:78] + wire _T_694 = _T_690 | _T_693; // @[lib.scala 88:23] + wire _T_696 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_697 = _T_696 & _T_585; // @[lib.scala 88:41] + wire _T_700 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 88:78] + wire _T_701 = _T_697 | _T_700; // @[lib.scala 88:23] + wire _T_703 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_704 = _T_703 & _T_585; // @[lib.scala 88:41] + wire _T_707 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 88:78] + wire _T_708 = _T_704 | _T_707; // @[lib.scala 88:23] + wire _T_710 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_711 = _T_710 & _T_585; // @[lib.scala 88:41] + wire _T_714 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 88:78] + wire _T_715 = _T_711 | _T_714; // @[lib.scala 88:23] + wire _T_717 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_718 = _T_717 & _T_585; // @[lib.scala 88:41] + wire _T_721 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 88:78] + wire _T_722 = _T_718 | _T_721; // @[lib.scala 88:23] + wire _T_724 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_725 = _T_724 & _T_585; // @[lib.scala 88:41] + wire _T_728 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 88:78] + wire _T_729 = _T_725 | _T_728; // @[lib.scala 88:23] + wire _T_731 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_732 = _T_731 & _T_585; // @[lib.scala 88:41] + wire _T_735 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 88:78] + wire _T_736 = _T_732 | _T_735; // @[lib.scala 88:23] + wire _T_738 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_739 = _T_738 & _T_585; // @[lib.scala 88:41] + wire _T_742 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 88:78] + wire _T_743 = _T_739 | _T_742; // @[lib.scala 88:23] + wire _T_745 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_746 = _T_745 & _T_585; // @[lib.scala 88:41] + wire _T_749 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 88:78] + wire _T_750 = _T_746 | _T_749; // @[lib.scala 88:23] + wire _T_752 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_753 = _T_752 & _T_585; // @[lib.scala 88:41] + wire _T_756 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 88:78] + wire _T_757 = _T_753 | _T_756; // @[lib.scala 88:23] + wire _T_759 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_760 = _T_759 & _T_585; // @[lib.scala 88:41] + wire _T_763 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 88:78] + wire _T_764 = _T_760 | _T_763; // @[lib.scala 88:23] + wire _T_766 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_767 = _T_766 & _T_585; // @[lib.scala 88:41] + wire _T_770 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 88:78] + wire _T_771 = _T_767 | _T_770; // @[lib.scala 88:23] + wire _T_773 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_774 = _T_773 & _T_585; // @[lib.scala 88:41] + wire _T_777 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 88:78] + wire _T_778 = _T_774 | _T_777; // @[lib.scala 88:23] + wire _T_780 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_781 = _T_780 & _T_585; // @[lib.scala 88:41] + wire _T_784 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 88:78] + wire _T_785 = _T_781 | _T_784; // @[lib.scala 88:23] + wire _T_787 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_788 = _T_787 & _T_585; // @[lib.scala 88:41] + wire _T_791 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 88:78] + wire _T_792 = _T_788 | _T_791; // @[lib.scala 88:23] + wire _T_794 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_795 = _T_794 & _T_585; // @[lib.scala 88:41] + wire _T_798 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 88:78] + wire _T_799 = _T_795 | _T_798; // @[lib.scala 88:23] + wire _T_801 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_802 = _T_801 & _T_585; // @[lib.scala 88:41] + wire _T_805 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 88:78] + wire _T_806 = _T_802 | _T_805; // @[lib.scala 88:23] + wire [7:0] _T_813 = {_T_638,_T_631,_T_624,_T_617,_T_610,_T_603,_T_596,_T_589}; // @[lib.scala 89:14] + wire [15:0] _T_821 = {_T_694,_T_687,_T_680,_T_673,_T_666,_T_659,_T_652,_T_645,_T_813}; // @[lib.scala 89:14] + wire [7:0] _T_828 = {_T_750,_T_743,_T_736,_T_729,_T_722,_T_715,_T_708,_T_701}; // @[lib.scala 89:14] + wire [31:0] _T_837 = {_T_806,_T_799,_T_792,_T_785,_T_778,_T_771,_T_764,_T_757,_T_828,_T_821}; // @[lib.scala 89:14] + wire _T_838 = &_T_837; // @[lib.scala 89:25] + wire _T_839 = _T_580 & _T_838; // @[lsu_trigger.scala 19:92] + wire _T_842 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] + wire _T_843 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] + wire _T_845 = _T_843 & _T_33; // @[lsu_trigger.scala 19:58] + wire _T_846 = _T_842 | _T_845; // @[lsu_trigger.scala 18:152] + wire _T_847 = _T_40 & _T_846; // @[lsu_trigger.scala 18:94] + wire _T_850 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 85:45] + wire _T_851 = ~_T_850; // @[lib.scala 85:39] + wire _T_852 = io_trigger_pkt_any_3_match_pkt & _T_851; // @[lib.scala 85:37] + wire _T_855 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 86:52] + wire _T_856 = _T_852 | _T_855; // @[lib.scala 86:41] + wire _T_858 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 88:36] + wire _T_859 = _T_858 & _T_852; // @[lib.scala 88:41] + wire _T_862 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 88:78] + wire _T_863 = _T_859 | _T_862; // @[lib.scala 88:23] + wire _T_865 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 88:36] + wire _T_866 = _T_865 & _T_852; // @[lib.scala 88:41] + wire _T_869 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 88:78] + wire _T_870 = _T_866 | _T_869; // @[lib.scala 88:23] + wire _T_872 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 88:36] + wire _T_873 = _T_872 & _T_852; // @[lib.scala 88:41] + wire _T_876 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 88:78] + wire _T_877 = _T_873 | _T_876; // @[lib.scala 88:23] + wire _T_879 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 88:36] + wire _T_880 = _T_879 & _T_852; // @[lib.scala 88:41] + wire _T_883 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 88:78] + wire _T_884 = _T_880 | _T_883; // @[lib.scala 88:23] + wire _T_886 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 88:36] + wire _T_887 = _T_886 & _T_852; // @[lib.scala 88:41] + wire _T_890 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 88:78] + wire _T_891 = _T_887 | _T_890; // @[lib.scala 88:23] + wire _T_893 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 88:36] + wire _T_894 = _T_893 & _T_852; // @[lib.scala 88:41] + wire _T_897 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 88:78] + wire _T_898 = _T_894 | _T_897; // @[lib.scala 88:23] + wire _T_900 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 88:36] + wire _T_901 = _T_900 & _T_852; // @[lib.scala 88:41] + wire _T_904 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 88:78] + wire _T_905 = _T_901 | _T_904; // @[lib.scala 88:23] + wire _T_907 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 88:36] + wire _T_908 = _T_907 & _T_852; // @[lib.scala 88:41] + wire _T_911 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 88:78] + wire _T_912 = _T_908 | _T_911; // @[lib.scala 88:23] + wire _T_914 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 88:36] + wire _T_915 = _T_914 & _T_852; // @[lib.scala 88:41] + wire _T_918 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 88:78] + wire _T_919 = _T_915 | _T_918; // @[lib.scala 88:23] + wire _T_921 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 88:36] + wire _T_922 = _T_921 & _T_852; // @[lib.scala 88:41] + wire _T_925 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 88:78] + wire _T_926 = _T_922 | _T_925; // @[lib.scala 88:23] + wire _T_928 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 88:36] + wire _T_929 = _T_928 & _T_852; // @[lib.scala 88:41] + wire _T_932 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 88:78] + wire _T_933 = _T_929 | _T_932; // @[lib.scala 88:23] + wire _T_935 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 88:36] + wire _T_936 = _T_935 & _T_852; // @[lib.scala 88:41] + wire _T_939 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 88:78] + wire _T_940 = _T_936 | _T_939; // @[lib.scala 88:23] + wire _T_942 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 88:36] + wire _T_943 = _T_942 & _T_852; // @[lib.scala 88:41] + wire _T_946 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 88:78] + wire _T_947 = _T_943 | _T_946; // @[lib.scala 88:23] + wire _T_949 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 88:36] + wire _T_950 = _T_949 & _T_852; // @[lib.scala 88:41] + wire _T_953 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 88:78] + wire _T_954 = _T_950 | _T_953; // @[lib.scala 88:23] + wire _T_956 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 88:36] + wire _T_957 = _T_956 & _T_852; // @[lib.scala 88:41] + wire _T_960 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 88:78] + wire _T_961 = _T_957 | _T_960; // @[lib.scala 88:23] + wire _T_963 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 88:36] + wire _T_964 = _T_963 & _T_852; // @[lib.scala 88:41] + wire _T_967 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 88:78] + wire _T_968 = _T_964 | _T_967; // @[lib.scala 88:23] + wire _T_970 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 88:36] + wire _T_971 = _T_970 & _T_852; // @[lib.scala 88:41] + wire _T_974 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 88:78] + wire _T_975 = _T_971 | _T_974; // @[lib.scala 88:23] + wire _T_977 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 88:36] + wire _T_978 = _T_977 & _T_852; // @[lib.scala 88:41] + wire _T_981 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 88:78] + wire _T_982 = _T_978 | _T_981; // @[lib.scala 88:23] + wire _T_984 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 88:36] + wire _T_985 = _T_984 & _T_852; // @[lib.scala 88:41] + wire _T_988 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 88:78] + wire _T_989 = _T_985 | _T_988; // @[lib.scala 88:23] + wire _T_991 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 88:36] + wire _T_992 = _T_991 & _T_852; // @[lib.scala 88:41] + wire _T_995 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 88:78] + wire _T_996 = _T_992 | _T_995; // @[lib.scala 88:23] + wire _T_998 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 88:36] + wire _T_999 = _T_998 & _T_852; // @[lib.scala 88:41] + wire _T_1002 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 88:78] + wire _T_1003 = _T_999 | _T_1002; // @[lib.scala 88:23] + wire _T_1005 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 88:36] + wire _T_1006 = _T_1005 & _T_852; // @[lib.scala 88:41] + wire _T_1009 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 88:78] + wire _T_1010 = _T_1006 | _T_1009; // @[lib.scala 88:23] + wire _T_1012 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 88:36] + wire _T_1013 = _T_1012 & _T_852; // @[lib.scala 88:41] + wire _T_1016 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 88:78] + wire _T_1017 = _T_1013 | _T_1016; // @[lib.scala 88:23] + wire _T_1019 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 88:36] + wire _T_1020 = _T_1019 & _T_852; // @[lib.scala 88:41] + wire _T_1023 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 88:78] + wire _T_1024 = _T_1020 | _T_1023; // @[lib.scala 88:23] + wire _T_1026 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 88:36] + wire _T_1027 = _T_1026 & _T_852; // @[lib.scala 88:41] + wire _T_1030 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 88:78] + wire _T_1031 = _T_1027 | _T_1030; // @[lib.scala 88:23] + wire _T_1033 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 88:36] + wire _T_1034 = _T_1033 & _T_852; // @[lib.scala 88:41] + wire _T_1037 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 88:78] + wire _T_1038 = _T_1034 | _T_1037; // @[lib.scala 88:23] + wire _T_1040 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 88:36] + wire _T_1041 = _T_1040 & _T_852; // @[lib.scala 88:41] + wire _T_1044 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 88:78] + wire _T_1045 = _T_1041 | _T_1044; // @[lib.scala 88:23] + wire _T_1047 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 88:36] + wire _T_1048 = _T_1047 & _T_852; // @[lib.scala 88:41] + wire _T_1051 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 88:78] + wire _T_1052 = _T_1048 | _T_1051; // @[lib.scala 88:23] + wire _T_1054 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 88:36] + wire _T_1055 = _T_1054 & _T_852; // @[lib.scala 88:41] + wire _T_1058 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 88:78] + wire _T_1059 = _T_1055 | _T_1058; // @[lib.scala 88:23] + wire _T_1061 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 88:36] + wire _T_1062 = _T_1061 & _T_852; // @[lib.scala 88:41] + wire _T_1065 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 88:78] + wire _T_1066 = _T_1062 | _T_1065; // @[lib.scala 88:23] + wire _T_1068 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 88:36] + wire _T_1069 = _T_1068 & _T_852; // @[lib.scala 88:41] + wire _T_1072 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 88:78] + wire _T_1073 = _T_1069 | _T_1072; // @[lib.scala 88:23] + wire [7:0] _T_1080 = {_T_905,_T_898,_T_891,_T_884,_T_877,_T_870,_T_863,_T_856}; // @[lib.scala 89:14] + wire [15:0] _T_1088 = {_T_961,_T_954,_T_947,_T_940,_T_933,_T_926,_T_919,_T_912,_T_1080}; // @[lib.scala 89:14] + wire [7:0] _T_1095 = {_T_1017,_T_1010,_T_1003,_T_996,_T_989,_T_982,_T_975,_T_968}; // @[lib.scala 89:14] + wire [31:0] _T_1104 = {_T_1073,_T_1066,_T_1059,_T_1052,_T_1045,_T_1038,_T_1031,_T_1024,_T_1095,_T_1088}; // @[lib.scala 89:14] + wire _T_1105 = &_T_1104; // @[lib.scala 89:25] + wire _T_1106 = _T_847 & _T_1105; // @[lsu_trigger.scala 19:92] + wire [2:0] _T_1108 = {_T_1106,_T_839,_T_572}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = {_T_1108,_T_305}; // @[lsu_trigger.scala 18:26] endmodule module lsu_clkdomain( input clock, @@ -78412,7 +78412,7 @@ module dma_ctrl( input io_dbg_dma_dbg_ib_dbg_cmd_write, input [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, input [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, - input [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + input [31:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, input io_dbg_dma_io_dbg_dma_bubble, output io_dbg_dma_io_dma_dbg_ready, output io_dec_dma_dctl_dma_dma_dccm_stall_any, @@ -78952,9 +78952,9 @@ module dma_ctrl( wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58] wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] - wire [3:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] + wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] reg [63:0] wrbuf_data; // @[lib.scala 358:16] - wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? {{60'd0}, _T_498} : wrbuf_data; // @[dma_ctrl.scala 224:347] + wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347] wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77] @@ -80288,7 +80288,7 @@ end // initial end else if (_T_87) begin fifo_data_0 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_0 <= {{60'd0}, _T_498}; + fifo_data_0 <= _T_498; end else begin fifo_data_0 <= wrbuf_data; end @@ -80303,7 +80303,7 @@ end // initial end else if (_T_105) begin fifo_data_1 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_1 <= {{60'd0}, _T_498}; + fifo_data_1 <= _T_498; end else begin fifo_data_1 <= wrbuf_data; end @@ -80318,7 +80318,7 @@ end // initial end else if (_T_123) begin fifo_data_2 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_2 <= {{60'd0}, _T_498}; + fifo_data_2 <= _T_498; end else begin fifo_data_2 <= wrbuf_data; end @@ -80333,7 +80333,7 @@ end // initial end else if (_T_141) begin fifo_data_3 <= io_iccm_dma_rdata; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - fifo_data_3 <= {{60'd0}, _T_498}; + fifo_data_3 <= _T_498; end else begin fifo_data_3 <= wrbuf_data; end @@ -80496,14 +80496,14 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[lib.scala 327:22] wire rvclkhdr_9_io_en; // @[lib.scala 327:22] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 327:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 410:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:45] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 57:22 axi4_to_ahb.scala 404:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 63:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 201:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 378:51] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 379:51] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 178:27] - wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 179:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 195:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 372:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 373:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 172:27] + wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 173:30] wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] @@ -80511,7 +80511,7 @@ module axi4_to_ahb( wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 196:32] + wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 190:32] wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] @@ -80520,9 +80520,9 @@ module axi4_to_ahb( wire _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 181:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 181:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 226:41] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 175:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 175:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 220:41] wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -80530,11 +80530,11 @@ module axi4_to_ahb( wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 227:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 240:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 240:26] - wire _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 298:51] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 221:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 234:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 234:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 234:26] + wire _T_286 = buf_state_en & slave_ready; // @[axi4_to_ahb.scala 292:51] wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] @@ -80542,13 +80542,13 @@ module axi4_to_ahb( wire _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 254:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 254:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67] - wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] - wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:99] - wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 299:65] - wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 299:26] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 248:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 248:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 248:67] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 293:42] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 293:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 293:65] + wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 293:26] wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] @@ -80556,14 +80556,14 @@ module axi4_to_ahb( wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] - wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56] - wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] - wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62] - wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 303:33] + wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 193:56] + wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 193:91] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 193:74] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 224:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 224:38] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 229:51] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 297:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 297:33] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] @@ -80584,23 +80584,23 @@ module axi4_to_ahb( wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 368:47] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 369:50] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 370:49] - wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 371:31] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 373:33] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 373:21] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 374:37] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 374:20] - wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 378:55] - wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 378:91] - wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 379:55] - wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 404:43] - wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 404:58] - wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 406:50] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 406:60] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 362:47] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 363:50] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 364:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 365:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 365:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 367:35] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 367:33] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 367:21] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 368:37] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 368:20] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 372:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 372:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 373:55] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 398:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 398:58] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 400:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 400:60] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -80661,8 +80661,8 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 373:18] - assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 374:17] + assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 367:18] + assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 368:17] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -80819,16 +80819,16 @@ module ahb_to_axi4( input io_axi_arready, input io_axi_rvalid, input [1:0] io_axi_rresp, - input [31:0] io_ahb_haddr, - input [2:0] io_ahb_hsize, - input [1:0] io_ahb_htrans, - input io_ahb_hwrite, input io_ahb_hsel, input io_ahb_hreadyin, output io_axi_awvalid, output io_axi_arvalid, - output io_ahb_hreadyout, - output io_ahb_hresp + output io_ahb_in_hready, + output io_ahb_in_hresp, + input [31:0] io_ahb_out_haddr, + input [2:0] io_ahb_out_hsize, + input [1:0] io_ahb_out_htrans, + input io_ahb_out_hwrite ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -80866,48 +80866,48 @@ module ahb_to_axi4( wire rvclkhdr_5_io_clk; // @[lib.scala 327:22] wire rvclkhdr_5_io_en; // @[lib.scala 327:22] wire rvclkhdr_5_io_scan_mode; // @[lib.scala 327:22] - wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 86:33 ahb_to_axi4.scala 175:31] - reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 168:65] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 87:33 ahb_to_axi4.scala 176:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 169:65] wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 71:29] wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 71:29] - wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 85:33 ahb_to_axi4.scala 174:31] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 86:33 ahb_to_axi4.scala 175:31] reg [1:0] buf_state; // @[Reg.scala 27:20] wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30] - wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 146:51] - wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 118:34] - wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 118:53] + wire ahb_hready = io_ahb_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 147:51] + wire _T_9 = ahb_hready & io_ahb_out_htrans[1]; // @[ahb_to_axi4.scala 119:34] + wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 119:57] wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 121:64] - wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 121:41] - wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 121:78] - wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 121:76] - wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 99:33 ahb_to_axi4.scala 224:27] - reg cmdbuf_vld; // @[ahb_to_axi4.scala 181:61] - wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 179:66] - wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 179:102] - wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 179:84] - wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 179:48] - wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 179:46] - wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 122:24] - wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 122:37] - wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 123:77] - wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 123:95] - wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 123:53] - wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 123:38] - wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 123:36] + wire _T_13 = io_ahb_out_htrans == 2'h0; // @[ahb_to_axi4.scala 122:71] + wire _T_14 = io_ahb_in_hresp | _T_13; // @[ahb_to_axi4.scala 122:44] + wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 122:85] + wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 122:83] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 100:33 ahb_to_axi4.scala 225:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 182:61] + wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 180:66] + wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 180:102] + wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 180:84] + wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 180:48] + wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 180:46] + wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 123:24] + wire _T_21 = _T_20 | io_ahb_in_hresp; // @[ahb_to_axi4.scala 123:37] + wire _T_24 = io_ahb_out_htrans == 2'h1; // @[ahb_to_axi4.scala 124:84] + wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 124:102] + wire _T_26 = io_ahb_in_hresp | _T_25; // @[ahb_to_axi4.scala 124:56] + wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 124:38] + wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 124:36] wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 128:23] - wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 128:37] + wire _T_33 = ~io_ahb_in_hresp; // @[ahb_to_axi4.scala 129:23] + wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 129:40] wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30] reg cmdbuf_write; // @[Reg.scala 27:20] - wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 132:39] - wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 132:37] - wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 134:62] + wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 133:39] + wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 133:37] + wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 135:62] wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67] wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67] wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58] - wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 134:41] + wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 135:41] wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67] wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67] @@ -80916,56 +80916,56 @@ module ahb_to_axi4( wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] - reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 166:65] - wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 140:30] - wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 141:30] - wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 142:30] - reg ahb_hready_q; // @[ahb_to_axi4.scala 164:60] - wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 145:66] - reg ahb_hresp_q; // @[ahb_to_axi4.scala 163:60] - wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 145:64] - wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 145:110] - wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 145:97] - wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 145:135] - wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 145:154] - wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 145:142] - wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 145:123] - wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 145:121] - reg buf_read_error; // @[ahb_to_axi4.scala 160:60] - wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 145:167] - wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 145:165] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 167:65] + wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 141:30] + wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 142:30] + wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 143:30] + reg ahb_hready_q; // @[ahb_to_axi4.scala 165:60] + wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 146:72] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 164:60] + wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 146:70] + wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 146:116] + wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 146:103] + wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 146:141] + wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 146:160] + wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 146:148] + wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 146:129] + wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 146:127] + reg buf_read_error; // @[ahb_to_axi4.scala 161:60] + wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 146:173] + wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 146:171] wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 165:60] - wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 149:54] - wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 149:76] - wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 149:63] - wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 150:26] - wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 150:7] - reg ahb_hwrite_q; // @[ahb_to_axi4.scala 167:65] - wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 151:46] - wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 151:26] - wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 151:86] - wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 151:115] - wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 151:95] - wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 151:66] - wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 151:64] - wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 150:47] - wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 152:35] - wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 151:126] - wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 153:56] - wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 153:35] - wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 152:55] - wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 154:56] - wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 154:35] - wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 153:61] - wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 149:87] - wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 154:63] - wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 178:109] - wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 178:107] - wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 178:140] - wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 178:124] - wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 181:66] - wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 181:110] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 166:60] + wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 150:57] + wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 150:79] + wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 150:66] + wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 151:26] + wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 151:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 168:65] + wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 152:46] + wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 152:26] + wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 152:86] + wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 152:115] + wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 152:95] + wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 152:66] + wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 152:64] + wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 151:47] + wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 153:35] + wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 152:126] + wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 154:56] + wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 154:35] + wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 153:55] + wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 155:56] + wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 155:35] + wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 154:61] + wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 150:90] + wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 155:63] + wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 179:109] + wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 179:107] + wire _T_148 = io_ahb_in_hresp & _T_37; // @[ahb_to_axi4.scala 179:143] + wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 179:124] + wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 182:66] + wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 182:110] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -81002,10 +81002,10 @@ module ahb_to_axi4( .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 198:27] - assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 213:27] - assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 145:31] - assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 149:31] + assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 199:27] + assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 214:27] + assign io_ahb_in_hready = io_ahb_in_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 146:34] + assign io_ahb_in_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 150:34] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -81120,7 +81120,7 @@ end // initial if (reset) begin ahb_haddr_q <= 32'h0; end else begin - ahb_haddr_q <= io_ahb_haddr; + ahb_haddr_q <= io_ahb_out_haddr; end end always @(posedge ahb_clk or posedge reset) begin @@ -81128,7 +81128,7 @@ end // initial buf_state <= 2'h0; end else if (buf_state_en) begin if (_T_6) begin - if (io_ahb_hwrite) begin + if (io_ahb_out_hwrite) begin buf_state <= 2'h1; end else begin buf_state <= 2'h2; @@ -81136,13 +81136,13 @@ end // initial end else if (_T_11) begin if (_T_16) begin buf_state <= 2'h0; - end else if (io_ahb_hwrite) begin + end else if (io_ahb_out_hwrite) begin buf_state <= 2'h1; end else begin buf_state <= 2'h2; end end else if (_T_29) begin - if (io_ahb_hresp) begin + if (io_ahb_in_hresp) begin buf_state <= 2'h0; end else begin buf_state <= 2'h3; @@ -81170,21 +81170,21 @@ end // initial if (reset) begin ahb_hsize_q <= 3'h0; end else begin - ahb_hsize_q <= io_ahb_hsize; + ahb_hsize_q <= io_ahb_out_hsize; end end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_hready_q <= 1'h0; end else begin - ahb_hready_q <= io_ahb_hreadyout & io_ahb_hreadyin; + ahb_hready_q <= io_ahb_in_hready & io_ahb_hreadyin; end end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_hresp_q <= 1'h0; end else begin - ahb_hresp_q <= io_ahb_hresp; + ahb_hresp_q <= io_ahb_in_hresp; end end always @(posedge ahb_clk or posedge reset) begin @@ -81204,14 +81204,14 @@ end // initial if (reset) begin ahb_htrans_q <= 2'h0; end else begin - ahb_htrans_q <= _T_88 & io_ahb_htrans; + ahb_htrans_q <= _T_88 & io_ahb_out_htrans; end end always @(posedge ahb_addr_clk or posedge reset) begin if (reset) begin ahb_hwrite_q <= 1'h0; end else begin - ahb_hwrite_q <= io_ahb_hwrite; + ahb_hwrite_q <= io_ahb_out_hwrite; end end endmodule @@ -81302,6 +81302,10 @@ module quasar( output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, + input [31:0] io_dma_ahb_out_haddr, + input [2:0] io_dma_ahb_out_hsize, + input [1:0] io_dma_ahb_out_htrans, + input io_dma_ahb_out_hwrite, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -81374,10 +81378,6 @@ module quasar( input [63:0] io_iccm_rd_data, input [77:0] io_iccm_rd_data_ecc, input io_dma_hsel, - input [31:0] io_dma_haddr, - input [2:0] io_dma_hsize, - input [1:0] io_dma_htrans, - input io_dma_hwrite, input io_dma_hreadyin, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, @@ -81392,793 +81392,793 @@ module quasar( input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[quasar.scala 116:19] - wire ifu_reset; // @[quasar.scala 116:19] - wire ifu_io_exu_flush_final; // @[quasar.scala 116:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 116:19] - wire ifu_io_free_clk; // @[quasar.scala 116:19] - wire ifu_io_active_clk; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 116:19] - wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 116:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 116:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 116:19] - wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 116:19] - wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 116:19] - wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 116:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 116:19] - wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 116:19] - wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 116:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 116:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 116:19] - wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 116:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 116:19] - wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 116:19] - wire ifu_io_iccm_correction_state; // @[quasar.scala 116:19] - wire ifu_io_iccm_wren; // @[quasar.scala 116:19] - wire ifu_io_iccm_rden; // @[quasar.scala 116:19] - wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 116:19] - wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 116:19] - wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 116:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 116:19] - wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 116:19] - wire ifu_io_ic_rd_en; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 116:19] - wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 116:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 116:19] - wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 116:19] - wire ifu_io_ic_tag_perr; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_rd_en; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_wr_en; // @[quasar.scala 116:19] - wire ifu_io_ic_debug_tag_array; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 116:19] - wire ifu_io_ic_sel_premux_data; // @[quasar.scala 116:19] - wire ifu_io_ifu_ar_ready; // @[quasar.scala 116:19] - wire ifu_io_ifu_ar_valid; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 116:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 116:19] - wire ifu_io_ifu_r_valid; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 116:19] - wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 116:19] - wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 116:19] - wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 116:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 116:19] - wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 116:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 116:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 116:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 116:19] - wire ifu_io_iccm_ready; // @[quasar.scala 116:19] - wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 116:19] - wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 116:19] - wire ifu_io_scan_mode; // @[quasar.scala 116:19] - wire dec_clock; // @[quasar.scala 117:19] - wire dec_reset; // @[quasar.scala 117:19] - wire dec_io_free_clk; // @[quasar.scala 117:19] - wire dec_io_active_clk; // @[quasar.scala 117:19] - wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_pause_state_cg; // @[quasar.scala 117:19] - wire [30:0] dec_io_rst_vec; // @[quasar.scala 117:19] - wire dec_io_nmi_int; // @[quasar.scala 117:19] - wire [30:0] dec_io_nmi_vec; // @[quasar.scala 117:19] - wire dec_io_i_cpu_halt_req; // @[quasar.scala 117:19] - wire dec_io_i_cpu_run_req; // @[quasar.scala 117:19] - wire dec_io_o_cpu_halt_status; // @[quasar.scala 117:19] - wire dec_io_o_cpu_halt_ack; // @[quasar.scala 117:19] - wire dec_io_o_cpu_run_ack; // @[quasar.scala 117:19] - wire dec_io_o_debug_mode_status; // @[quasar.scala 117:19] - wire [27:0] dec_io_core_id; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_halt_req; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_run_req; // @[quasar.scala 117:19] - wire dec_io_mpc_reset_run_req; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 117:19] - wire dec_io_mpc_debug_run_ack; // @[quasar.scala 117:19] - wire dec_io_debug_brkpt_status; // @[quasar.scala 117:19] - wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 117:19] - wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 117:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 117:19] - wire dec_io_lsu_idle_any; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 117:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 117:19] - wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 117:19] - wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 117:19] - wire [31:0] dec_io_exu_div_result; // @[quasar.scala 117:19] - wire dec_io_exu_div_wren; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 117:19] - wire dec_io_lsu_load_stall_any; // @[quasar.scala 117:19] - wire dec_io_lsu_store_stall_any; // @[quasar.scala 117:19] - wire dec_io_iccm_dma_sb_error; // @[quasar.scala 117:19] - wire dec_io_exu_flush_final; // @[quasar.scala 117:19] - wire dec_io_timer_int; // @[quasar.scala 117:19] - wire dec_io_soft_int; // @[quasar.scala 117:19] - wire dec_io_dbg_halt_req; // @[quasar.scala 117:19] - wire dec_io_dbg_resume_req; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 117:19] - wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 117:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 117:19] - wire dec_io_exu_i0_br_way_r; // @[quasar.scala 117:19] - wire dec_io_lsu_p_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_by; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_half; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_word; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_load; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_store; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 117:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 117:19] - wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 117:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 117:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 117:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 117:19] - wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 117:19] - wire dec_io_scan_mode; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 117:19] - wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 117:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 117:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 117:19] - wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 117:19] - wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 117:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 117:19] - wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 117:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 117:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 117:19] - wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 117:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 117:19] - wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 117:19] - wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 117:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 117:19] - wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 117:19] - wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 117:19] - wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 117:19] - wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 117:19] - wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 117:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 117:19] - wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 117:19] - wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 117:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 117:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 117:19] - wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 117:19] - wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 117:19] - wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 117:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 117:19] - wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 117:19] - wire [1:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 117:19] - wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 117:19] - wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] - wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 117:19] - wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 117:19] - wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 117:19] - wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 117:19] - wire dec_io_dec_pic_mexintpend; // @[quasar.scala 117:19] - wire dbg_clock; // @[quasar.scala 118:19] - wire dbg_reset; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 118:19] - wire dbg_io_dbg_core_rst_l; // @[quasar.scala 118:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 118:19] - wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 118:19] - wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 118:19] - wire dbg_io_dbg_halt_req; // @[quasar.scala 118:19] - wire dbg_io_dbg_resume_req; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 118:19] - wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 118:19] - wire dbg_io_dmi_reg_en; // @[quasar.scala 118:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 118:19] - wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 118:19] - wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 118:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 118:19] - wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_w_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_w_valid; // @[quasar.scala 118:19] - wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 118:19] - wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_b_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_b_valid; // @[quasar.scala 118:19] - wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 118:19] - wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 118:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 118:19] - wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_r_ready; // @[quasar.scala 118:19] - wire dbg_io_sb_axi_r_valid; // @[quasar.scala 118:19] - wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 118:19] - wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 118:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] - wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] - wire [1:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 118:19] - wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 118:19] - wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 118:19] - wire dbg_io_dbg_rst_l; // @[quasar.scala 118:19] - wire dbg_io_clk_override; // @[quasar.scala 118:19] - wire dbg_io_scan_mode; // @[quasar.scala 118:19] - wire exu_clock; // @[quasar.scala 119:19] - wire exu_reset; // @[quasar.scala 119:19] - wire exu_io_scan_mode; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 119:19] - wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 119:19] - wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 119:19] - wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 119:19] - wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 119:19] - wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 119:19] - wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 119:19] - wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 119:19] - wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 119:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 119:19] - wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 119:19] - wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 119:19] - wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 119:19] - wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 119:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 119:19] - wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 119:19] - wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 119:19] - wire exu_io_exu_flush_final; // @[quasar.scala 119:19] - wire [31:0] exu_io_exu_div_result; // @[quasar.scala 119:19] - wire exu_io_exu_div_wren; // @[quasar.scala 119:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 119:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 119:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 119:19] - wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 119:19] - wire lsu_clock; // @[quasar.scala 120:19] - wire lsu_reset; // @[quasar.scala 120:19] - wire lsu_io_clk_override; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 120:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 120:19] - wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 120:19] - wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 120:19] - wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 120:19] - wire lsu_io_dccm_wren; // @[quasar.scala 120:19] - wire lsu_io_dccm_rden; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 120:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 120:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 120:19] - wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 120:19] - wire lsu_io_axi_aw_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_aw_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 120:19] - wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 120:19] - wire lsu_io_axi_w_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_w_valid; // @[quasar.scala 120:19] - wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 120:19] - wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 120:19] - wire lsu_io_axi_b_valid; // @[quasar.scala 120:19] - wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 120:19] - wire lsu_io_axi_ar_ready; // @[quasar.scala 120:19] - wire lsu_io_axi_ar_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 120:19] - wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 120:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 120:19] - wire lsu_io_axi_r_valid; // @[quasar.scala 120:19] - wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 120:19] - wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 120:19] - wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 120:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 120:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_by; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_half; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_word; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_load; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_store; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 120:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 120:19] - wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 120:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 120:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 120:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 120:19] - wire lsu_io_lsu_load_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_store_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 120:19] - wire lsu_io_lsu_idle_any; // @[quasar.scala 120:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 120:19] - wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 120:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 120:19] - wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 120:19] - wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 120:19] - wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 120:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 120:19] - wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 120:19] - wire lsu_io_scan_mode; // @[quasar.scala 120:19] - wire lsu_io_free_clk; // @[quasar.scala 120:19] - wire pic_ctrl_inst_clock; // @[quasar.scala 121:29] - wire pic_ctrl_inst_reset; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 121:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 121:29] - wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 121:29] - wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 121:29] - wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 121:29] - wire dma_ctrl_clock; // @[quasar.scala 122:24] - wire dma_ctrl_reset; // @[quasar.scala 122:24] - wire dma_ctrl_io_free_clk; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 122:24] - wire dma_ctrl_io_clk_override; // @[quasar.scala 122:24] - wire dma_ctrl_io_scan_mode; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 122:24] - wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_iccm_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 122:24] - wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 122:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 122:24] - wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 122:24] - wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:24] - wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:24] - wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:24] + wire ifu_clock; // @[quasar.scala 122:19] + wire ifu_reset; // @[quasar.scala 122:19] + wire ifu_io_exu_flush_final; // @[quasar.scala 122:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 122:19] + wire ifu_io_free_clk; // @[quasar.scala 122:19] + wire ifu_io_active_clk; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 122:19] + wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 122:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 122:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 122:19] + wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 122:19] + wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 122:19] + wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 122:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 122:19] + wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 122:19] + wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 122:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 122:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 122:19] + wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 122:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 122:19] + wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 122:19] + wire ifu_io_iccm_correction_state; // @[quasar.scala 122:19] + wire ifu_io_iccm_wren; // @[quasar.scala 122:19] + wire ifu_io_iccm_rden; // @[quasar.scala 122:19] + wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 122:19] + wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 122:19] + wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 122:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 122:19] + wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 122:19] + wire ifu_io_ic_rd_en; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 122:19] + wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 122:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 122:19] + wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 122:19] + wire ifu_io_ic_tag_perr; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_rd_en; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_wr_en; // @[quasar.scala 122:19] + wire ifu_io_ic_debug_tag_array; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 122:19] + wire ifu_io_ic_sel_premux_data; // @[quasar.scala 122:19] + wire ifu_io_ifu_ar_ready; // @[quasar.scala 122:19] + wire ifu_io_ifu_ar_valid; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 122:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 122:19] + wire ifu_io_ifu_r_valid; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 122:19] + wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 122:19] + wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:19] + wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:19] + wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 122:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 122:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 122:19] + wire ifu_io_iccm_ready; // @[quasar.scala 122:19] + wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 122:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 122:19] + wire ifu_io_scan_mode; // @[quasar.scala 122:19] + wire dec_clock; // @[quasar.scala 123:19] + wire dec_reset; // @[quasar.scala 123:19] + wire dec_io_free_clk; // @[quasar.scala 123:19] + wire dec_io_active_clk; // @[quasar.scala 123:19] + wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_pause_state_cg; // @[quasar.scala 123:19] + wire [30:0] dec_io_rst_vec; // @[quasar.scala 123:19] + wire dec_io_nmi_int; // @[quasar.scala 123:19] + wire [30:0] dec_io_nmi_vec; // @[quasar.scala 123:19] + wire dec_io_i_cpu_halt_req; // @[quasar.scala 123:19] + wire dec_io_i_cpu_run_req; // @[quasar.scala 123:19] + wire dec_io_o_cpu_halt_status; // @[quasar.scala 123:19] + wire dec_io_o_cpu_halt_ack; // @[quasar.scala 123:19] + wire dec_io_o_cpu_run_ack; // @[quasar.scala 123:19] + wire dec_io_o_debug_mode_status; // @[quasar.scala 123:19] + wire [27:0] dec_io_core_id; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_halt_req; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_run_req; // @[quasar.scala 123:19] + wire dec_io_mpc_reset_run_req; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 123:19] + wire dec_io_mpc_debug_run_ack; // @[quasar.scala 123:19] + wire dec_io_debug_brkpt_status; // @[quasar.scala 123:19] + wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 123:19] + wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 123:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 123:19] + wire dec_io_lsu_idle_any; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 123:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 123:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 123:19] + wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 123:19] + wire [31:0] dec_io_exu_div_result; // @[quasar.scala 123:19] + wire dec_io_exu_div_wren; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 123:19] + wire dec_io_lsu_load_stall_any; // @[quasar.scala 123:19] + wire dec_io_lsu_store_stall_any; // @[quasar.scala 123:19] + wire dec_io_iccm_dma_sb_error; // @[quasar.scala 123:19] + wire dec_io_exu_flush_final; // @[quasar.scala 123:19] + wire dec_io_timer_int; // @[quasar.scala 123:19] + wire dec_io_soft_int; // @[quasar.scala 123:19] + wire dec_io_dbg_halt_req; // @[quasar.scala 123:19] + wire dec_io_dbg_resume_req; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 123:19] + wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 123:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 123:19] + wire dec_io_exu_i0_br_way_r; // @[quasar.scala 123:19] + wire dec_io_lsu_p_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_by; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_half; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_word; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_load; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_store; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 123:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 123:19] + wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 123:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 123:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 123:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 123:19] + wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 123:19] + wire dec_io_scan_mode; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 123:19] + wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 123:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 123:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 123:19] + wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 123:19] + wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 123:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 123:19] + wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 123:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 123:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 123:19] + wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 123:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 123:19] + wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 123:19] + wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 123:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 123:19] + wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 123:19] + wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 123:19] + wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 123:19] + wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 123:19] + wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 123:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 123:19] + wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 123:19] + wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:19] + wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:19] + wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 123:19] + wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 123:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 123:19] + wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 123:19] + wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 123:19] + wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 123:19] + wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 123:19] + wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 123:19] + wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 123:19] + wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 123:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 123:19] + wire dec_io_dec_pic_mexintpend; // @[quasar.scala 123:19] + wire dbg_clock; // @[quasar.scala 124:19] + wire dbg_reset; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 124:19] + wire dbg_io_dbg_core_rst_l; // @[quasar.scala 124:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 124:19] + wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 124:19] + wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 124:19] + wire dbg_io_dbg_halt_req; // @[quasar.scala 124:19] + wire dbg_io_dbg_resume_req; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 124:19] + wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 124:19] + wire dbg_io_dmi_reg_en; // @[quasar.scala 124:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 124:19] + wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 124:19] + wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 124:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 124:19] + wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_w_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_w_valid; // @[quasar.scala 124:19] + wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 124:19] + wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_b_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_b_valid; // @[quasar.scala 124:19] + wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 124:19] + wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 124:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 124:19] + wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_r_ready; // @[quasar.scala 124:19] + wire dbg_io_sb_axi_r_valid; // @[quasar.scala 124:19] + wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 124:19] + wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 124:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] + wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] + wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 124:19] + wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 124:19] + wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 124:19] + wire dbg_io_dbg_rst_l; // @[quasar.scala 124:19] + wire dbg_io_clk_override; // @[quasar.scala 124:19] + wire dbg_io_scan_mode; // @[quasar.scala 124:19] + wire exu_clock; // @[quasar.scala 125:19] + wire exu_reset; // @[quasar.scala 125:19] + wire exu_io_scan_mode; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 125:19] + wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 125:19] + wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 125:19] + wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 125:19] + wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 125:19] + wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 125:19] + wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 125:19] + wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 125:19] + wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 125:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 125:19] + wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 125:19] + wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19] + wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19] + wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19] + wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 125:19] + wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 125:19] + wire exu_io_exu_flush_final; // @[quasar.scala 125:19] + wire [31:0] exu_io_exu_div_result; // @[quasar.scala 125:19] + wire exu_io_exu_div_wren; // @[quasar.scala 125:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 125:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 125:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 125:19] + wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 125:19] + wire lsu_clock; // @[quasar.scala 126:19] + wire lsu_reset; // @[quasar.scala 126:19] + wire lsu_io_clk_override; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 126:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 126:19] + wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 126:19] + wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 126:19] + wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19] + wire lsu_io_dccm_wren; // @[quasar.scala 126:19] + wire lsu_io_dccm_rden; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 126:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 126:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 126:19] + wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19] + wire lsu_io_axi_aw_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_aw_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 126:19] + wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 126:19] + wire lsu_io_axi_w_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_w_valid; // @[quasar.scala 126:19] + wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 126:19] + wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 126:19] + wire lsu_io_axi_b_valid; // @[quasar.scala 126:19] + wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 126:19] + wire lsu_io_axi_ar_ready; // @[quasar.scala 126:19] + wire lsu_io_axi_ar_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 126:19] + wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 126:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 126:19] + wire lsu_io_axi_r_valid; // @[quasar.scala 126:19] + wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 126:19] + wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 126:19] + wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 126:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_by; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_half; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_word; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_load; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_store; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19] + wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 126:19] + wire lsu_io_lsu_load_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_store_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 126:19] + wire lsu_io_lsu_idle_any; // @[quasar.scala 126:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 126:19] + wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19] + wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 126:19] + wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 126:19] + wire lsu_io_scan_mode; // @[quasar.scala 126:19] + wire lsu_io_free_clk; // @[quasar.scala 126:19] + wire pic_ctrl_inst_clock; // @[quasar.scala 127:29] + wire pic_ctrl_inst_reset; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 127:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 127:29] + wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 127:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 127:29] + wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 127:29] + wire dma_ctrl_clock; // @[quasar.scala 128:24] + wire dma_ctrl_reset; // @[quasar.scala 128:24] + wire dma_ctrl_io_free_clk; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 128:24] + wire dma_ctrl_io_clk_override; // @[quasar.scala 128:24] + wire dma_ctrl_io_scan_mode; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 128:24] + wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_iccm_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 128:24] + wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 128:24] + wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 128:24] + wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 128:24] + wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 128:24] + wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 128:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 128:24] + wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 128:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 128:24] wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] wire rvclkhdr_io_en; // @[lib.scala 327:22] @@ -82187,65 +82187,65 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 327:22] wire rvclkhdr_1_io_en; // @[lib.scala 327:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 327:22] - wire axi4_to_ahb_clock; // @[quasar.scala 297:33] - wire axi4_to_ahb_reset; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 297:33] - wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 297:33] - wire axi4_to_ahb_1_clock; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 324:33] - wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 324:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_reset; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 352:32] - wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 352:32] - wire ahb_to_axi4_clock; // @[quasar.scala 379:33] - wire ahb_to_axi4_reset; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 379:33] - wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 379:33] - wire [31:0] ahb_to_axi4_io_ahb_haddr; // @[quasar.scala 379:33] - wire [2:0] ahb_to_axi4_io_ahb_hsize; // @[quasar.scala 379:33] - wire [1:0] ahb_to_axi4_io_ahb_htrans; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hwrite; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 379:33] - wire ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 379:33] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 124:67] - wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 124:70] - wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 125:23] - wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:50] - ifu ifu ( // @[quasar.scala 116:19] + wire axi4_to_ahb_clock; // @[quasar.scala 303:33] + wire axi4_to_ahb_reset; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 303:33] + wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 303:33] + wire axi4_to_ahb_1_clock; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 330:33] + wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 330:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_reset; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 358:32] + wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 358:32] + wire ahb_to_axi4_clock; // @[quasar.scala 385:33] + wire ahb_to_axi4_reset; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 385:33] + wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_in_hready; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_in_hresp; // @[quasar.scala 385:33] + wire [31:0] ahb_to_axi4_io_ahb_out_haddr; // @[quasar.scala 385:33] + wire [2:0] ahb_to_axi4_io_ahb_out_hsize; // @[quasar.scala 385:33] + wire [1:0] ahb_to_axi4_io_ahb_out_htrans; // @[quasar.scala 385:33] + wire ahb_to_axi4_io_ahb_out_hwrite; // @[quasar.scala 385:33] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 130:67] + wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 130:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 131:23] + wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 131:50] + ifu ifu ( // @[quasar.scala 122:19] .clock(ifu_clock), .reset(ifu_reset), .io_exu_flush_final(ifu_io_exu_flush_final), @@ -82375,7 +82375,7 @@ module quasar( .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), .io_scan_mode(ifu_io_scan_mode) ); - dec dec ( // @[quasar.scala 117:19] + dec dec ( // @[quasar.scala 123:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -82649,7 +82649,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend) ); - dbg dbg ( // @[quasar.scala 118:19] + dbg dbg ( // @[quasar.scala 124:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_size(dbg_io_dbg_cmd_size), @@ -82705,7 +82705,7 @@ module quasar( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - exu exu ( // @[quasar.scala 119:19] + exu exu ( // @[quasar.scala 125:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -82810,7 +82810,7 @@ module quasar( .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d), .io_exu_flush_path_final(exu_io_exu_flush_path_final) ); - lsu lsu ( // @[quasar.scala 120:19] + lsu lsu ( // @[quasar.scala 126:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -82949,7 +82949,7 @@ module quasar( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - pic_ctrl pic_ctrl_inst ( // @[quasar.scala 121:29] + pic_ctrl pic_ctrl_inst ( // @[quasar.scala 127:29] .clock(pic_ctrl_inst_clock), .reset(pic_ctrl_inst_reset), .io_scan_mode(pic_ctrl_inst_io_scan_mode), @@ -82971,7 +82971,7 @@ module quasar( .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt), .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend) ); - dma_ctrl dma_ctrl ( // @[quasar.scala 122:24] + dma_ctrl dma_ctrl ( // @[quasar.scala 128:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -83058,7 +83058,7 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 297:33] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 303:33] .clock(axi4_to_ahb_clock), .reset(axi4_to_ahb_reset), .io_scan_mode(axi4_to_ahb_io_scan_mode), @@ -83072,7 +83072,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_io_axi_awready), .io_axi_wready(axi4_to_ahb_io_axi_wready) ); - axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 324:33] + axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 330:33] .clock(axi4_to_ahb_1_clock), .reset(axi4_to_ahb_1_reset), .io_scan_mode(axi4_to_ahb_1_io_scan_mode), @@ -83086,7 +83086,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_1_io_axi_awready), .io_axi_wready(axi4_to_ahb_1_io_axi_wready) ); - axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 352:32] + axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 358:32] .clock(axi4_to_ahb_2_clock), .reset(axi4_to_ahb_2_reset), .io_scan_mode(axi4_to_ahb_2_io_scan_mode), @@ -83100,7 +83100,7 @@ module quasar( .io_axi_awready(axi4_to_ahb_2_io_axi_awready), .io_axi_wready(axi4_to_ahb_2_io_axi_wready) ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 379:33] + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 385:33] .clock(ahb_to_axi4_clock), .reset(ahb_to_axi4_reset), .io_scan_mode(ahb_to_axi4_io_scan_mode), @@ -83109,513 +83109,513 @@ module quasar( .io_axi_arready(ahb_to_axi4_io_axi_arready), .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid), .io_axi_rresp(ahb_to_axi4_io_axi_rresp), - .io_ahb_haddr(ahb_to_axi4_io_ahb_haddr), - .io_ahb_hsize(ahb_to_axi4_io_ahb_hsize), - .io_ahb_htrans(ahb_to_axi4_io_ahb_htrans), - .io_ahb_hwrite(ahb_to_axi4_io_ahb_hwrite), .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin), .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid), .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid), - .io_ahb_hreadyout(ahb_to_axi4_io_ahb_hreadyout), - .io_ahb_hresp(ahb_to_axi4_io_ahb_hresp) + .io_ahb_in_hready(ahb_to_axi4_io_ahb_in_hready), + .io_ahb_in_hresp(ahb_to_axi4_io_ahb_in_hresp), + .io_ahb_out_haddr(ahb_to_axi4_io_ahb_out_haddr), + .io_ahb_out_hsize(ahb_to_axi4_io_ahb_out_hsize), + .io_ahb_out_htrans(ahb_to_axi4_io_ahb_out_htrans), + .io_ahb_out_hwrite(ahb_to_axi4_io_ahb_out_hwrite) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 286:14] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 286:14] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 286:14] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 286:14] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 286:14] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 286:14] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 286:14] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 289:14] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 289:14] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 289:14] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 233:17] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 233:17] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 233:17] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 233:17] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 233:17] - assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 233:17] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 233:17] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 233:17] - assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 233:17] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 290:14] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 290:14] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 290:14] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 290:14] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 290:14] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 290:14] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 290:14] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 290:14] - assign io_core_rst_l = reset & _T_2; // @[quasar.scala 124:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 265:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 265:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 268:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 269:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 270:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 271:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 272:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 273:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 274:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 275:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 276:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 277:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 278:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 279:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 280:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 281:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 283:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 283:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 283:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 283:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 283:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 283:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 283:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 283:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 145:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 145:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 145:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 145:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 145:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 145:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 145:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 145:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 145:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 145:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 145:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 145:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 145:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 145:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 146:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 146:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 146:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 146:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 146:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 146:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 146:15] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 292:14] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 292:14] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 292:14] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 292:14] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 292:14] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 292:14] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 292:14] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 295:14] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 295:14] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 295:14] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 239:17] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 239:17] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 239:17] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 239:17] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 239:17] + assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 239:17] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 239:17] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 239:17] + assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 239:17] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 296:14] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 296:14] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 296:14] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 296:14] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 296:14] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 296:14] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 296:14] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 296:14] + assign io_core_rst_l = reset & _T_2; // @[quasar.scala 130:17] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 271:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 271:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 274:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 275:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 276:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 277:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 278:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 279:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 280:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 281:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 282:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 283:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 284:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 285:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 286:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 287:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 289:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 289:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 289:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 289:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 289:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 289:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 289:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 289:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 151:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 151:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 151:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 151:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 151:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 151:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 151:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 151:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 151:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 151:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 151:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 151:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 151:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 151:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 152:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 152:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 152:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 152:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 152:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 152:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 152:15] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 135:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 140:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 141:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 137:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 138:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 133:18 quasar.scala 151:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 133:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 133:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 147:25 quasar.scala 149:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 147:25 quasar.scala 148:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 147:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 147:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 146:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 146:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 145:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 145:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 145:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 145:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 289:14 quasar.scala 423:25] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 289:14 quasar.scala 424:24] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 289:14 quasar.scala 425:26] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 289:14 quasar.scala 426:28] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 289:14 quasar.scala 427:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 143:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 144:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 144:18] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 150:33] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 136:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 141:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 146:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 147:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 143:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 144:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 139:18 quasar.scala 157:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 139:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 139:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 153:25 quasar.scala 155:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 153:25 quasar.scala 154:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 153:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 153:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 152:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 152:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 151:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 151:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 151:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 151:13] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 427:25] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 428:24] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 429:26] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 430:28] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 431:28] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 149:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 150:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 150:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 156:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 142:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 154:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 155:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 156:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 157:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 158:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 159:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 160:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 161:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 162:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 163:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 164:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 165:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 166:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 169:31] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 172:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 173:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 174:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 176:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 177:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 177:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 178:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 179:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 180:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 181:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 182:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 183:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 184:30] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 185:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 186:26] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 192:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 188:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 189:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 190:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 191:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 193:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 133:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 133:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 196:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 196:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 167:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 167:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 168:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 168:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 175:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 175:18] - assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 170:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 263:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 263:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 263:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 263:28] + assign dec_reset = io_core_rst_l; // @[quasar.scala 160:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 161:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 162:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 163:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 164:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 165:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 166:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 167:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 168:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 169:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 170:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 171:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 172:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 175:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 178:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 179:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 180:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 182:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 183:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 183:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 184:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 185:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 186:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 187:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 188:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 189:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 190:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 191:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 192:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 198:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 194:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 195:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 196:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 197:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 199:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 139:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 139:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 202:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 202:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 173:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 173:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 174:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 174:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 181:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 181:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 176:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 269:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 269:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 269:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 269:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 221:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 222:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 223:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 224:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 225:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 226:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 227:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 228:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 229:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 230:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 231:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 232:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 233:17 quasar.scala 430:28] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 233:17 quasar.scala 431:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 233:17 quasar.scala 432:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 233:17 quasar.scala 433:31] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 233:17 quasar.scala 434:28] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 233:17 quasar.scala 435:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 233:17 quasar.scala 437:31] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 233:17 quasar.scala 438:31] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 247:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 234:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 235:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 236:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 237:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 227:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 228:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 229:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 230:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 231:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 232:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 233:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 234:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 235:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 236:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 237:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 238:24] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 239:17 quasar.scala 434:28] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 239:17 quasar.scala 435:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 239:17 quasar.scala 436:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 239:17 quasar.scala 437:31] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 239:17 quasar.scala 438:28] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 239:17 quasar.scala 439:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 239:17 quasar.scala 441:31] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 239:17 quasar.scala 442:31] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 253:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 240:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 241:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 242:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 243:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 197:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 198:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 196:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 196:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 196:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 196:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 196:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 196:18] - assign exu_io_dbg_cmd_wrdata = {{30'd0}, dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata}; // @[quasar.scala 199:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 203:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 204:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 202:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 202:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 202:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 202:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 202:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 202:18] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 205:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 202:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 203:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 216:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 216:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 262:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 208:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 208:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 167:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 167:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 167:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 283:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 283:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 286:14 quasar.scala 409:25] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 286:14 quasar.scala 410:24] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 286:14 quasar.scala 411:24] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 286:14 quasar.scala 412:28] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 286:14 quasar.scala 413:26] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 286:14 quasar.scala 414:25] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 286:14 quasar.scala 415:24] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 286:14 quasar.scala 416:26] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 286:14 quasar.scala 417:28] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 286:14 quasar.scala 418:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 204:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 205:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 206:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 207:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 209:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 210:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 210:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 213:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 213:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 211:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 212:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 215:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 217:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 218:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 208:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 209:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 222:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 222:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 268:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 214:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 214:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 173:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 173:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 173:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 289:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 289:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 292:14 quasar.scala 413:25] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 292:14 quasar.scala 414:24] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 292:14 quasar.scala 415:24] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 292:14 quasar.scala 416:28] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 292:14 quasar.scala 417:26] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 292:14 quasar.scala 418:25] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 292:14 quasar.scala 419:24] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 292:14 quasar.scala 420:26] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 292:14 quasar.scala 421:28] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 292:14 quasar.scala 422:28] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 210:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 211:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 212:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 213:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 215:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 216:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 216:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 219:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 219:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 217:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 218:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 221:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 223:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 224:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 257:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 256:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 258:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 259:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 260:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 261:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 262:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 263:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 263:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 263:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 262:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 264:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 265:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 266:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 267:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 268:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 269:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 269:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 241:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 242:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 243:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 244:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 245:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 248:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 246:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 247:26] - assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 170:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 249:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 253:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 250:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 251:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 252:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 290:14 quasar.scala 440:34] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 290:14 quasar.scala 441:36] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 290:14 quasar.scala 442:38] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 290:14 quasar.scala 443:38] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 290:14 quasar.scala 444:33] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 290:14 quasar.scala 445:37] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 290:14 quasar.scala 446:37] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 290:14 quasar.scala 447:33] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 290:14 quasar.scala 448:34] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 290:14 quasar.scala 449:36] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 290:14 quasar.scala 450:38] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 290:14 quasar.scala 451:38] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 290:14 quasar.scala 452:33] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 216:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 216:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 247:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 248:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 249:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 250:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 251:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 254:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 252:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 253:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 176:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 255:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 259:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 256:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 257:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 258:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 296:14 quasar.scala 444:34] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 296:14 quasar.scala 445:36] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 296:14 quasar.scala 446:38] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 296:14 quasar.scala 447:38] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 296:14 quasar.scala 448:33] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 296:14 quasar.scala 449:37] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 296:14 quasar.scala 450:37] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 296:14 quasar.scala 451:33] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 296:14 quasar.scala 452:34] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 296:14 quasar.scala 453:36] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 296:14 quasar.scala 454:38] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 296:14 quasar.scala 455:38] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 296:14 quasar.scala 456:33] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 222:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 222:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -83624,48 +83624,48 @@ module quasar( assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] assign axi4_to_ahb_clock = clock; assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 299:34] - assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 300:35] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 301:37] - assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 298:36] - assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 307:35] - assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 311:35] - assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 313:36] - assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 319:35] + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 305:34] + assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 306:35] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 307:37] + assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 304:36] + assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 313:35] + assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 317:35] + assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 319:36] + assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 325:35] assign axi4_to_ahb_1_clock = clock; assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 326:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 327:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 328:37] - assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 325:36] - assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 334:35] - assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 338:35] - assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 340:36] - assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 346:35] + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 332:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 333:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 334:37] + assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 331:36] + assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 340:35] + assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 344:35] + assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 346:36] + assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 352:35] assign axi4_to_ahb_2_clock = clock; assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 354:33] - assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 355:34] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 356:36] - assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 353:35] - assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 362:34] - assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 366:34] - assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 368:35] - assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 374:34] + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 360:33] + assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 361:34] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 362:36] + assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 359:35] + assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 368:34] + assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 372:34] + assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 374:35] + assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 380:34] assign ahb_to_axi4_clock = clock; assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 380:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 381:35] - assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 383:36] - assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 390:36] - assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 391:35] - assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 394:34] - assign ahb_to_axi4_io_ahb_haddr = io_dma_haddr; // @[quasar.scala 397:34] - assign ahb_to_axi4_io_ahb_hsize = io_dma_hsize; // @[quasar.scala 401:34] - assign ahb_to_axi4_io_ahb_htrans = io_dma_htrans; // @[quasar.scala 402:35] - assign ahb_to_axi4_io_ahb_hwrite = io_dma_hwrite; // @[quasar.scala 403:35] - assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 405:33] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 406:37] + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 386:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 387:35] + assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 389:36] + assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 396:36] + assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 397:35] + assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 400:34] + assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 411:33] + assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 412:37] + assign ahb_to_axi4_io_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar.scala 487:16] + assign ahb_to_axi4_io_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar.scala 487:16] endmodule module quasar_wrapper( input clock, @@ -83832,18 +83832,18 @@ module quasar_wrapper( output [1:0] io_dma_axi_r_bits_resp, output io_dma_axi_r_bits_last, input io_dma_hsel, - input [31:0] io_dma_haddr, - input [2:0] io_dma_hburst, - input io_dma_hmastlock, - input [3:0] io_dma_hprot, - input [2:0] io_dma_hsize, - input [1:0] io_dma_htrans, - input io_dma_hwrite, - input [63:0] io_dma_hwdata, + output [63:0] io_dma_ahb_in_hrdata, + output io_dma_ahb_in_hready, + output io_dma_ahb_in_hresp, + input [31:0] io_dma_ahb_out_haddr, + input [2:0] io_dma_ahb_out_hburst, + input io_dma_ahb_out_hmastlock, + input [3:0] io_dma_ahb_out_hprot, + input [2:0] io_dma_ahb_out_hsize, + input [1:0] io_dma_ahb_out_htrans, + input io_dma_ahb_out_hwrite, + input [63:0] io_dma_ahb_out_hwdata, input io_dma_hreadyin, - output [63:0] io_dma_hrdata, - output io_dma_hreadyout, - output io_dma_hresp, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -83883,243 +83883,243 @@ module quasar_wrapper( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, input io_scan_mode ); - wire mem_clk; // @[quasar_wrapper.scala 78:19] - wire mem_rst_l; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_clk_override; // @[quasar_wrapper.scala 78:19] - wire mem_icm_clk_override; // @[quasar_wrapper.scala 78:19] - wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_wren; // @[quasar_wrapper.scala 78:19] - wire mem_dccm_rden; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 78:19] - wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 78:19] - wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 78:19] - wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_correction_state; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_wren; // @[quasar_wrapper.scala 78:19] - wire mem_iccm_rden; // @[quasar_wrapper.scala 78:19] - wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 78:19] - wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 78:19] - wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 78:19] - wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_rd_en; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 78:19] - wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 78:19] - wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 78:19] - wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 78:19] - wire mem_ic_tag_perr; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 78:19] - wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 78:19] - wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 78:19] - wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 78:19] - wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 78:19] - wire mem_scan_mode; // @[quasar_wrapper.scala 78:19] - wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tck; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tms; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 79:27] - wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 79:27] - wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 79:27] - wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 79:27] - wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 79:27] - wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 79:27] - wire core_clock; // @[quasar_wrapper.scala 80:20] - wire core_reset; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] - wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] - wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 80:20] - wire core_io_nmi_int; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_nmi_vec; // @[quasar_wrapper.scala 80:20] - wire core_io_core_rst_l; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 80:20] - wire [4:0] core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_clk_override; // @[quasar_wrapper.scala 80:20] - wire core_io_icm_clk_override; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 80:20] - wire core_io_i_cpu_halt_req; // @[quasar_wrapper.scala 80:20] - wire core_io_i_cpu_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 80:20] - wire core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_o_debug_mode_status; // @[quasar_wrapper.scala 80:20] - wire [27:0] core_io_core_id; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_reset_run_req; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 80:20] - wire core_io_debug_brkpt_status; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 80:20] - wire core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_wren; // @[quasar_wrapper.scala 80:20] - wire core_io_dccm_rden; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 80:20] - wire [15:0] core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 80:20] - wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_wr_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_rd_en; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_wr_data_0; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_wr_data_1; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 80:20] - wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 80:20] - wire [70:0] core_io_ic_debug_rd_data; // @[quasar_wrapper.scala 80:20] - wire [25:0] core_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_eccerr; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_rd_hit; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_tag_perr; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_ic_debug_way; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_ic_premux_data; // @[quasar_wrapper.scala 80:20] - wire core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 80:20] - wire [14:0] core_io_iccm_rw_addr; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_correction_state; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_wren; // @[quasar_wrapper.scala 80:20] - wire core_io_iccm_rden; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_iccm_wr_size; // @[quasar_wrapper.scala 80:20] - wire [77:0] core_io_iccm_wr_data; // @[quasar_wrapper.scala 80:20] - wire [63:0] core_io_iccm_rd_data; // @[quasar_wrapper.scala 80:20] - wire [77:0] core_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hsel; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dma_haddr; // @[quasar_wrapper.scala 80:20] - wire [2:0] core_io_dma_hsize; // @[quasar_wrapper.scala 80:20] - wire [1:0] core_io_dma_htrans; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hwrite; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_hreadyin; // @[quasar_wrapper.scala 80:20] - wire core_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dma_bus_clk_en; // @[quasar_wrapper.scala 80:20] - wire core_io_dmi_reg_en; // @[quasar_wrapper.scala 80:20] - wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 80:20] - wire core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 80:20] - wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 80:20] - wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 80:20] - wire core_io_timer_int; // @[quasar_wrapper.scala 80:20] - wire core_io_soft_int; // @[quasar_wrapper.scala 80:20] - wire core_io_scan_mode; // @[quasar_wrapper.scala 80:20] - mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 78:19] + wire mem_clk; // @[quasar_wrapper.scala 79:19] + wire mem_rst_l; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_clk_override; // @[quasar_wrapper.scala 79:19] + wire mem_icm_clk_override; // @[quasar_wrapper.scala 79:19] + wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_wren; // @[quasar_wrapper.scala 79:19] + wire mem_dccm_rden; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 79:19] + wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 79:19] + wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 79:19] + wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_correction_state; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_wren; // @[quasar_wrapper.scala 79:19] + wire mem_iccm_rden; // @[quasar_wrapper.scala 79:19] + wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 79:19] + wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 79:19] + wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 79:19] + wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_rd_en; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 79:19] + wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 79:19] + wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 79:19] + wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 79:19] + wire mem_ic_tag_perr; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 79:19] + wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 79:19] + wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 79:19] + wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 79:19] + wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 79:19] + wire mem_scan_mode; // @[quasar_wrapper.scala 79:19] + wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tck; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tms; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 80:27] + wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 80:27] + wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 80:27] + wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 80:27] + wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:27] + wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 80:27] + wire swerv_clock; // @[quasar_wrapper.scala 81:21] + wire swerv_reset; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 81:21] + wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 81:21] + wire swerv_io_nmi_int; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 81:21] + wire swerv_io_core_rst_l; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 81:21] + wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 81:21] + wire swerv_io_icm_clk_override; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 81:21] + wire swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 81:21] + wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 81:21] + wire swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_wren; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dccm_rden; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 81:21] + wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 81:21] + wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_rd_en; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 81:21] + wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 81:21] + wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 81:21] + wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 81:21] + wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 81:21] + wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_wren; // @[quasar_wrapper.scala 81:21] + wire swerv_io_iccm_rden; // @[quasar_wrapper.scala 81:21] + wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 81:21] + wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 81:21] + wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 81:21] + wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_hsel; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 81:21] + wire swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 81:21] + wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 81:21] + wire swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 81:21] + wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 81:21] + wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 81:21] + wire swerv_io_timer_int; // @[quasar_wrapper.scala 81:21] + wire swerv_io_soft_int; // @[quasar_wrapper.scala 81:21] + wire swerv_io_scan_mode; // @[quasar_wrapper.scala 81:21] + mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 79:19] .clk(mem_clk), .rst_l(mem_rst_l), .dccm_clk_override(mem_dccm_clk_override), @@ -84167,7 +84167,7 @@ module quasar_wrapper( .ic_sel_premux_data(mem_ic_sel_premux_data), .scan_mode(mem_scan_mode) ); - dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 79:27] + dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 80:27] .trst_n(dmi_wrapper_trst_n), .tck(dmi_wrapper_tck), .tms(dmi_wrapper_tms), @@ -84184,417 +84184,417 @@ module quasar_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - quasar core ( // @[quasar_wrapper.scala 80:20] - .clock(core_clock), - .reset(core_reset), - .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), - .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), - .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), - .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), - .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_ready(core_io_lsu_axi_b_ready), - .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), - .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), - .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), - .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), - .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_ready(core_io_lsu_axi_r_ready), - .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), - .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), - .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), - .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), - .io_ifu_axi_aw_valid(core_io_ifu_axi_aw_valid), - .io_ifu_axi_w_valid(core_io_ifu_axi_w_valid), - .io_ifu_axi_b_ready(core_io_ifu_axi_b_ready), - .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), - .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), - .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_ready(core_io_ifu_axi_r_ready), - .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), - .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), - .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), - .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), - .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), - .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), - .io_sb_axi_w_ready(core_io_sb_axi_w_ready), - .io_sb_axi_w_valid(core_io_sb_axi_w_valid), - .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), - .io_sb_axi_b_ready(core_io_sb_axi_b_ready), - .io_sb_axi_b_valid(core_io_sb_axi_b_valid), - .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), - .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), - .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), - .io_sb_axi_r_ready(core_io_sb_axi_r_ready), - .io_sb_axi_r_valid(core_io_sb_axi_r_valid), - .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), - .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), - .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), - .io_dma_axi_w_ready(core_io_dma_axi_w_ready), - .io_dma_axi_w_valid(core_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(core_io_dma_axi_b_ready), - .io_dma_axi_b_valid(core_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), - .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), - .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(core_io_dma_axi_r_ready), - .io_dma_axi_r_valid(core_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), - .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), - .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), - .io_dbg_rst_l(core_io_dbg_rst_l), - .io_rst_vec(core_io_rst_vec), - .io_nmi_int(core_io_nmi_int), - .io_nmi_vec(core_io_nmi_vec), - .io_core_rst_l(core_io_core_rst_l), - .io_rv_trace_pkt_rv_i_valid_ip(core_io_rv_trace_pkt_rv_i_valid_ip), - .io_rv_trace_pkt_rv_i_insn_ip(core_io_rv_trace_pkt_rv_i_insn_ip), - .io_rv_trace_pkt_rv_i_address_ip(core_io_rv_trace_pkt_rv_i_address_ip), - .io_rv_trace_pkt_rv_i_exception_ip(core_io_rv_trace_pkt_rv_i_exception_ip), - .io_rv_trace_pkt_rv_i_ecause_ip(core_io_rv_trace_pkt_rv_i_ecause_ip), - .io_rv_trace_pkt_rv_i_interrupt_ip(core_io_rv_trace_pkt_rv_i_interrupt_ip), - .io_rv_trace_pkt_rv_i_tval_ip(core_io_rv_trace_pkt_rv_i_tval_ip), - .io_dccm_clk_override(core_io_dccm_clk_override), - .io_icm_clk_override(core_io_icm_clk_override), - .io_dec_tlu_core_ecc_disable(core_io_dec_tlu_core_ecc_disable), - .io_i_cpu_halt_req(core_io_i_cpu_halt_req), - .io_i_cpu_run_req(core_io_i_cpu_run_req), - .io_o_cpu_halt_ack(core_io_o_cpu_halt_ack), - .io_o_cpu_halt_status(core_io_o_cpu_halt_status), - .io_o_cpu_run_ack(core_io_o_cpu_run_ack), - .io_o_debug_mode_status(core_io_o_debug_mode_status), - .io_core_id(core_io_core_id), - .io_mpc_debug_halt_req(core_io_mpc_debug_halt_req), - .io_mpc_debug_run_req(core_io_mpc_debug_run_req), - .io_mpc_reset_run_req(core_io_mpc_reset_run_req), - .io_mpc_debug_halt_ack(core_io_mpc_debug_halt_ack), - .io_mpc_debug_run_ack(core_io_mpc_debug_run_ack), - .io_debug_brkpt_status(core_io_debug_brkpt_status), - .io_dec_tlu_perfcnt0(core_io_dec_tlu_perfcnt0), - .io_dec_tlu_perfcnt1(core_io_dec_tlu_perfcnt1), - .io_dec_tlu_perfcnt2(core_io_dec_tlu_perfcnt2), - .io_dec_tlu_perfcnt3(core_io_dec_tlu_perfcnt3), - .io_dccm_wren(core_io_dccm_wren), - .io_dccm_rden(core_io_dccm_rden), - .io_dccm_wr_addr_lo(core_io_dccm_wr_addr_lo), - .io_dccm_wr_addr_hi(core_io_dccm_wr_addr_hi), - .io_dccm_rd_addr_lo(core_io_dccm_rd_addr_lo), - .io_dccm_rd_addr_hi(core_io_dccm_rd_addr_hi), - .io_dccm_wr_data_lo(core_io_dccm_wr_data_lo), - .io_dccm_wr_data_hi(core_io_dccm_wr_data_hi), - .io_dccm_rd_data_lo(core_io_dccm_rd_data_lo), - .io_dccm_rd_data_hi(core_io_dccm_rd_data_hi), - .io_ic_rw_addr(core_io_ic_rw_addr), - .io_ic_tag_valid(core_io_ic_tag_valid), - .io_ic_wr_en(core_io_ic_wr_en), - .io_ic_rd_en(core_io_ic_rd_en), - .io_ic_wr_data_0(core_io_ic_wr_data_0), - .io_ic_wr_data_1(core_io_ic_wr_data_1), - .io_ic_debug_wr_data(core_io_ic_debug_wr_data), - .io_ic_debug_addr(core_io_ic_debug_addr), - .io_ic_rd_data(core_io_ic_rd_data), - .io_ic_debug_rd_data(core_io_ic_debug_rd_data), - .io_ic_tag_debug_rd_data(core_io_ic_tag_debug_rd_data), - .io_ic_eccerr(core_io_ic_eccerr), - .io_ic_rd_hit(core_io_ic_rd_hit), - .io_ic_tag_perr(core_io_ic_tag_perr), - .io_ic_debug_rd_en(core_io_ic_debug_rd_en), - .io_ic_debug_wr_en(core_io_ic_debug_wr_en), - .io_ic_debug_tag_array(core_io_ic_debug_tag_array), - .io_ic_debug_way(core_io_ic_debug_way), - .io_ic_premux_data(core_io_ic_premux_data), - .io_ic_sel_premux_data(core_io_ic_sel_premux_data), - .io_iccm_rw_addr(core_io_iccm_rw_addr), - .io_iccm_buf_correct_ecc(core_io_iccm_buf_correct_ecc), - .io_iccm_correction_state(core_io_iccm_correction_state), - .io_iccm_wren(core_io_iccm_wren), - .io_iccm_rden(core_io_iccm_rden), - .io_iccm_wr_size(core_io_iccm_wr_size), - .io_iccm_wr_data(core_io_iccm_wr_data), - .io_iccm_rd_data(core_io_iccm_rd_data), - .io_iccm_rd_data_ecc(core_io_iccm_rd_data_ecc), - .io_dma_hsel(core_io_dma_hsel), - .io_dma_haddr(core_io_dma_haddr), - .io_dma_hsize(core_io_dma_hsize), - .io_dma_htrans(core_io_dma_htrans), - .io_dma_hwrite(core_io_dma_hwrite), - .io_dma_hreadyin(core_io_dma_hreadyin), - .io_lsu_bus_clk_en(core_io_lsu_bus_clk_en), - .io_ifu_bus_clk_en(core_io_ifu_bus_clk_en), - .io_dbg_bus_clk_en(core_io_dbg_bus_clk_en), - .io_dma_bus_clk_en(core_io_dma_bus_clk_en), - .io_dmi_reg_en(core_io_dmi_reg_en), - .io_dmi_reg_addr(core_io_dmi_reg_addr), - .io_dmi_reg_wr_en(core_io_dmi_reg_wr_en), - .io_dmi_reg_wdata(core_io_dmi_reg_wdata), - .io_extintsrc_req(core_io_extintsrc_req), - .io_timer_int(core_io_timer_int), - .io_soft_int(core_io_soft_int), - .io_scan_mode(core_io_scan_mode) + quasar swerv ( // @[quasar_wrapper.scala 81:21] + .clock(swerv_clock), + .reset(swerv_reset), + .io_lsu_axi_aw_ready(swerv_io_lsu_axi_aw_ready), + .io_lsu_axi_aw_valid(swerv_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(swerv_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(swerv_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(swerv_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(swerv_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(swerv_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_ready(swerv_io_lsu_axi_w_ready), + .io_lsu_axi_w_valid(swerv_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(swerv_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(swerv_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(swerv_io_lsu_axi_b_ready), + .io_lsu_axi_b_valid(swerv_io_lsu_axi_b_valid), + .io_lsu_axi_b_bits_resp(swerv_io_lsu_axi_b_bits_resp), + .io_lsu_axi_b_bits_id(swerv_io_lsu_axi_b_bits_id), + .io_lsu_axi_ar_ready(swerv_io_lsu_axi_ar_ready), + .io_lsu_axi_ar_valid(swerv_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(swerv_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(swerv_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(swerv_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(swerv_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(swerv_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(swerv_io_lsu_axi_r_ready), + .io_lsu_axi_r_valid(swerv_io_lsu_axi_r_valid), + .io_lsu_axi_r_bits_id(swerv_io_lsu_axi_r_bits_id), + .io_lsu_axi_r_bits_data(swerv_io_lsu_axi_r_bits_data), + .io_lsu_axi_r_bits_resp(swerv_io_lsu_axi_r_bits_resp), + .io_ifu_axi_aw_valid(swerv_io_ifu_axi_aw_valid), + .io_ifu_axi_w_valid(swerv_io_ifu_axi_w_valid), + .io_ifu_axi_b_ready(swerv_io_ifu_axi_b_ready), + .io_ifu_axi_ar_ready(swerv_io_ifu_axi_ar_ready), + .io_ifu_axi_ar_valid(swerv_io_ifu_axi_ar_valid), + .io_ifu_axi_ar_bits_id(swerv_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(swerv_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(swerv_io_ifu_axi_ar_bits_region), + .io_ifu_axi_r_ready(swerv_io_ifu_axi_r_ready), + .io_ifu_axi_r_valid(swerv_io_ifu_axi_r_valid), + .io_ifu_axi_r_bits_id(swerv_io_ifu_axi_r_bits_id), + .io_ifu_axi_r_bits_data(swerv_io_ifu_axi_r_bits_data), + .io_ifu_axi_r_bits_resp(swerv_io_ifu_axi_r_bits_resp), + .io_sb_axi_aw_ready(swerv_io_sb_axi_aw_ready), + .io_sb_axi_aw_valid(swerv_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_addr(swerv_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(swerv_io_sb_axi_aw_bits_region), + .io_sb_axi_aw_bits_size(swerv_io_sb_axi_aw_bits_size), + .io_sb_axi_w_ready(swerv_io_sb_axi_w_ready), + .io_sb_axi_w_valid(swerv_io_sb_axi_w_valid), + .io_sb_axi_w_bits_data(swerv_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(swerv_io_sb_axi_w_bits_strb), + .io_sb_axi_b_ready(swerv_io_sb_axi_b_ready), + .io_sb_axi_b_valid(swerv_io_sb_axi_b_valid), + .io_sb_axi_b_bits_resp(swerv_io_sb_axi_b_bits_resp), + .io_sb_axi_ar_ready(swerv_io_sb_axi_ar_ready), + .io_sb_axi_ar_valid(swerv_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_addr(swerv_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(swerv_io_sb_axi_ar_bits_region), + .io_sb_axi_ar_bits_size(swerv_io_sb_axi_ar_bits_size), + .io_sb_axi_r_ready(swerv_io_sb_axi_r_ready), + .io_sb_axi_r_valid(swerv_io_sb_axi_r_valid), + .io_sb_axi_r_bits_data(swerv_io_sb_axi_r_bits_data), + .io_sb_axi_r_bits_resp(swerv_io_sb_axi_r_bits_resp), + .io_dma_axi_aw_ready(swerv_io_dma_axi_aw_ready), + .io_dma_axi_aw_valid(swerv_io_dma_axi_aw_valid), + .io_dma_axi_aw_bits_id(swerv_io_dma_axi_aw_bits_id), + .io_dma_axi_aw_bits_addr(swerv_io_dma_axi_aw_bits_addr), + .io_dma_axi_aw_bits_size(swerv_io_dma_axi_aw_bits_size), + .io_dma_axi_w_ready(swerv_io_dma_axi_w_ready), + .io_dma_axi_w_valid(swerv_io_dma_axi_w_valid), + .io_dma_axi_w_bits_data(swerv_io_dma_axi_w_bits_data), + .io_dma_axi_w_bits_strb(swerv_io_dma_axi_w_bits_strb), + .io_dma_axi_b_ready(swerv_io_dma_axi_b_ready), + .io_dma_axi_b_valid(swerv_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(swerv_io_dma_axi_b_bits_resp), + .io_dma_axi_b_bits_id(swerv_io_dma_axi_b_bits_id), + .io_dma_axi_ar_ready(swerv_io_dma_axi_ar_ready), + .io_dma_axi_ar_valid(swerv_io_dma_axi_ar_valid), + .io_dma_axi_ar_bits_id(swerv_io_dma_axi_ar_bits_id), + .io_dma_axi_ar_bits_addr(swerv_io_dma_axi_ar_bits_addr), + .io_dma_axi_ar_bits_size(swerv_io_dma_axi_ar_bits_size), + .io_dma_axi_r_ready(swerv_io_dma_axi_r_ready), + .io_dma_axi_r_valid(swerv_io_dma_axi_r_valid), + .io_dma_axi_r_bits_id(swerv_io_dma_axi_r_bits_id), + .io_dma_axi_r_bits_data(swerv_io_dma_axi_r_bits_data), + .io_dma_axi_r_bits_resp(swerv_io_dma_axi_r_bits_resp), + .io_dma_ahb_out_haddr(swerv_io_dma_ahb_out_haddr), + .io_dma_ahb_out_hsize(swerv_io_dma_ahb_out_hsize), + .io_dma_ahb_out_htrans(swerv_io_dma_ahb_out_htrans), + .io_dma_ahb_out_hwrite(swerv_io_dma_ahb_out_hwrite), + .io_dbg_rst_l(swerv_io_dbg_rst_l), + .io_rst_vec(swerv_io_rst_vec), + .io_nmi_int(swerv_io_nmi_int), + .io_nmi_vec(swerv_io_nmi_vec), + .io_core_rst_l(swerv_io_core_rst_l), + .io_rv_trace_pkt_rv_i_valid_ip(swerv_io_rv_trace_pkt_rv_i_valid_ip), + .io_rv_trace_pkt_rv_i_insn_ip(swerv_io_rv_trace_pkt_rv_i_insn_ip), + .io_rv_trace_pkt_rv_i_address_ip(swerv_io_rv_trace_pkt_rv_i_address_ip), + .io_rv_trace_pkt_rv_i_exception_ip(swerv_io_rv_trace_pkt_rv_i_exception_ip), + .io_rv_trace_pkt_rv_i_ecause_ip(swerv_io_rv_trace_pkt_rv_i_ecause_ip), + .io_rv_trace_pkt_rv_i_interrupt_ip(swerv_io_rv_trace_pkt_rv_i_interrupt_ip), + .io_rv_trace_pkt_rv_i_tval_ip(swerv_io_rv_trace_pkt_rv_i_tval_ip), + .io_dccm_clk_override(swerv_io_dccm_clk_override), + .io_icm_clk_override(swerv_io_icm_clk_override), + .io_dec_tlu_core_ecc_disable(swerv_io_dec_tlu_core_ecc_disable), + .io_i_cpu_halt_req(swerv_io_i_cpu_halt_req), + .io_i_cpu_run_req(swerv_io_i_cpu_run_req), + .io_o_cpu_halt_ack(swerv_io_o_cpu_halt_ack), + .io_o_cpu_halt_status(swerv_io_o_cpu_halt_status), + .io_o_cpu_run_ack(swerv_io_o_cpu_run_ack), + .io_o_debug_mode_status(swerv_io_o_debug_mode_status), + .io_core_id(swerv_io_core_id), + .io_mpc_debug_halt_req(swerv_io_mpc_debug_halt_req), + .io_mpc_debug_run_req(swerv_io_mpc_debug_run_req), + .io_mpc_reset_run_req(swerv_io_mpc_reset_run_req), + .io_mpc_debug_halt_ack(swerv_io_mpc_debug_halt_ack), + .io_mpc_debug_run_ack(swerv_io_mpc_debug_run_ack), + .io_debug_brkpt_status(swerv_io_debug_brkpt_status), + .io_dec_tlu_perfcnt0(swerv_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(swerv_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(swerv_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(swerv_io_dec_tlu_perfcnt3), + .io_dccm_wren(swerv_io_dccm_wren), + .io_dccm_rden(swerv_io_dccm_rden), + .io_dccm_wr_addr_lo(swerv_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(swerv_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(swerv_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(swerv_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(swerv_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(swerv_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(swerv_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(swerv_io_dccm_rd_data_hi), + .io_ic_rw_addr(swerv_io_ic_rw_addr), + .io_ic_tag_valid(swerv_io_ic_tag_valid), + .io_ic_wr_en(swerv_io_ic_wr_en), + .io_ic_rd_en(swerv_io_ic_rd_en), + .io_ic_wr_data_0(swerv_io_ic_wr_data_0), + .io_ic_wr_data_1(swerv_io_ic_wr_data_1), + .io_ic_debug_wr_data(swerv_io_ic_debug_wr_data), + .io_ic_debug_addr(swerv_io_ic_debug_addr), + .io_ic_rd_data(swerv_io_ic_rd_data), + .io_ic_debug_rd_data(swerv_io_ic_debug_rd_data), + .io_ic_tag_debug_rd_data(swerv_io_ic_tag_debug_rd_data), + .io_ic_eccerr(swerv_io_ic_eccerr), + .io_ic_rd_hit(swerv_io_ic_rd_hit), + .io_ic_tag_perr(swerv_io_ic_tag_perr), + .io_ic_debug_rd_en(swerv_io_ic_debug_rd_en), + .io_ic_debug_wr_en(swerv_io_ic_debug_wr_en), + .io_ic_debug_tag_array(swerv_io_ic_debug_tag_array), + .io_ic_debug_way(swerv_io_ic_debug_way), + .io_ic_premux_data(swerv_io_ic_premux_data), + .io_ic_sel_premux_data(swerv_io_ic_sel_premux_data), + .io_iccm_rw_addr(swerv_io_iccm_rw_addr), + .io_iccm_buf_correct_ecc(swerv_io_iccm_buf_correct_ecc), + .io_iccm_correction_state(swerv_io_iccm_correction_state), + .io_iccm_wren(swerv_io_iccm_wren), + .io_iccm_rden(swerv_io_iccm_rden), + .io_iccm_wr_size(swerv_io_iccm_wr_size), + .io_iccm_wr_data(swerv_io_iccm_wr_data), + .io_iccm_rd_data(swerv_io_iccm_rd_data), + .io_iccm_rd_data_ecc(swerv_io_iccm_rd_data_ecc), + .io_dma_hsel(swerv_io_dma_hsel), + .io_dma_hreadyin(swerv_io_dma_hreadyin), + .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en), + .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en), + .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en), + .io_dma_bus_clk_en(swerv_io_dma_bus_clk_en), + .io_dmi_reg_en(swerv_io_dmi_reg_en), + .io_dmi_reg_addr(swerv_io_dmi_reg_addr), + .io_dmi_reg_wr_en(swerv_io_dmi_reg_wr_en), + .io_dmi_reg_wdata(swerv_io_dmi_reg_wdata), + .io_extintsrc_req(swerv_io_extintsrc_req), + .io_timer_int(swerv_io_timer_int), + .io_soft_int(swerv_io_soft_int), + .io_scan_mode(swerv_io_scan_mode) ); - assign io_lsu_axi_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 138:19] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 141:19] - assign io_sb_axi_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] - assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:18] - assign io_dma_axi_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 148:19] - assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 148:19] - assign io_dma_hrdata = 64'h0; // @[quasar_wrapper.scala 195:17] - assign io_dma_hreadyout = 1'h0; // @[quasar_wrapper.scala 196:20] - assign io_dma_hresp = 1'h0; // @[quasar_wrapper.scala 197:16] - assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 185:23] - assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 186:23] - assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 187:23] - assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 188:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 96:15] - assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 181:25] - assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 182:24] - assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 183:25] - assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 176:21] - assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 177:24] - assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 179:26] - assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 178:20] - assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 173:19] - assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 173:19] - assign mem_clk = clock; // @[quasar_wrapper.scala 104:14] - assign mem_rst_l = reset; // @[quasar_wrapper.scala 103:16] - assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 99:28] - assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 100:27] - assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 101:35] - assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 102:15] - assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 109:16] - assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 109:16] - assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 108:14] - assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 108:14] - assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 108:14] - assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 108:14] - assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 108:14] - assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 108:14] - assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 105:20] - assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 81:25] - assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 82:22] - assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 83:22] - assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 84:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 90:29] - assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 85:27] - assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 86:26] - assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 87:26] - assign core_clock = clock; - assign core_reset = reset; - assign core_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 138:19] - assign core_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 138:19] - assign core_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 141:19] - assign core_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 141:19] - assign core_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 144:18] - assign core_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 144:18] - assign core_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 148:19] - assign core_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 148:19] - assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 107:21 quasar_wrapper.scala 121:21] - assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] - assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] - assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:19] - assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:26] - assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:25] - assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:19] - assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:30] - assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:29] - assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:29] - assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 102:15] - assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 102:15] - assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 108:14] - assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 108:14] - assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 109:16] - assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 109:16] - assign core_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 151:20] - assign core_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 152:21] - assign core_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 156:21] - assign core_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 157:22] - assign core_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 158:22] - assign core_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 160:24] - assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 162:26] - assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 163:26] - assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 164:26] - assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 165:26] - assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 93:22] - assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 92:24] - assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 94:25] - assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 91:25] - assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 169:25] - assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 167:21] - assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 168:20] - assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 119:21] + assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:20] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 147:20] + assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19] + assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 150:19] + assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 154:20] + assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 154:20] + assign io_dma_ahb_in_hrdata = 64'h0; // @[quasar_wrapper.scala 115:19] + assign io_dma_ahb_in_hready = 1'h0; // @[quasar_wrapper.scala 115:19] + assign io_dma_ahb_in_hresp = 1'h0; // @[quasar_wrapper.scala 115:19] + assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 208:23] + assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 209:23] + assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 210:23] + assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 211:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 97:15] + assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 204:25] + assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 205:24] + assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 206:25] + assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 199:21] + assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 200:24] + assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 202:26] + assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 201:20] + assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 196:19] + assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 196:19] + assign mem_clk = clock; // @[quasar_wrapper.scala 105:14] + assign mem_rst_l = reset; // @[quasar_wrapper.scala 104:16] + assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 100:28] + assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 101:27] + assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 102:35] + assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 103:15] + assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 103:15] + assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 110:17] + assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 110:17] + assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 109:15] + assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 109:15] + assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 109:15] + assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 109:15] + assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 109:15] + assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 109:15] + assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 106:20] + assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 82:25] + assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 83:22] + assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 84:22] + assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 85:22] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 91:29] + assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 86:27] + assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 87:26] + assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 88:26] + assign swerv_clock = clock; + assign swerv_reset = reset; + assign swerv_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 144:20] + assign swerv_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 144:20] + assign swerv_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 147:20] + assign swerv_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 147:20] + assign swerv_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 150:19] + assign swerv_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 150:19] + assign swerv_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 154:20] + assign swerv_io_dma_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dma_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 158:24] + assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 108:22 quasar_wrapper.scala 127:22] + assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 128:20] + assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 129:20] + assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 130:20] + assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 133:27] + assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 134:26] + assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 135:20] + assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 138:31] + assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 139:30] + assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 140:30] + assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 103:15] + assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 103:15] + assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 109:15] + assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 109:15] + assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 110:17] + assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 110:17] + assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 157:21] + assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 167:25] + assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 185:27] + assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 186:27] + assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 187:27] + assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 188:27] + assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 94:23] + assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 93:25] + assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 95:26] + assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 92:26] + assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 192:26] + assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 190:22] + assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 191:21] + assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 125:22] endmodule diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index fc207b68..0f860ae7 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type } +object dbg extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) +} \ No newline at end of file diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 2be96902..662fd32d 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -34,7 +34,7 @@ class tlu_dma extends Bundle{ class dec_bp extends Bundle{ val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t)) -// val dec_tlu_flush_lower_wb = Input(Bool()) + // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_leak_one_wb = Input(Bool()) val dec_tlu_bpred_disable = Input(Bool()) } @@ -44,6 +44,25 @@ class dec_ifc extends Bundle{ val dec_tlu_mrac_ff = Input(UInt(32.W)) val ifu_pmu_fetch_stall = Output(Bool()) } +class ahb_in extends Bundle{ + val hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data + val hready = Input(Bool()) // slave ready to accept transaction + val hresp = Input(Bool()) // slave response (high indicates erro) +} +class ahb_out extends Bundle{ + val haddr = Output(UInt(32.W)) // [31:0] // ahb bus address + val hburst = Output(UInt(3.W)) // [2:0] // tied to 0 + val hmastlock = Output(Bool()) // tied to 0 + val hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 + val hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) + val htrans = Output(UInt(2.W)) + val hwrite = Output(Bool()) // ahb bus write + val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data +} +class ahb_channel extends Bundle{ + val in = Input(new ahb_in) + val out = Output(new ahb_out) +} class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ val aw = Decoupled(new write_addr(BUS_TAG)) val w = Decoupled(new write_data()) @@ -92,7 +111,7 @@ class write_resp(val TAG : Int=3) extends Bundle with lib{ // write_response } class dec_mem_ctrl extends Bundle with lib{ -// val dec_tlu_flush_lower_wb = Input(Bool()) + // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_err_wb = Input(Bool()) val dec_tlu_i0_commit_cmt = Input(Bool()) val dec_tlu_force_halt = Input(Bool()) @@ -288,7 +307,7 @@ class dbg_ib extends Bundle{ } class dbg_dctl extends Bundle{ - val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i + val dbg_cmd_wrdata = Input(UInt(32.W)) // command write data, for fence/fence_i } @@ -402,7 +421,7 @@ class rets_pkt_t extends Bundle { } class br_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val toffset = UInt(12.W) val hist = UInt(2.W) val br_error = UInt(1.W) @@ -415,7 +434,7 @@ class br_pkt_t extends Bundle { class br_tlu_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val hist = UInt(2.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) @@ -430,7 +449,7 @@ class predict_pkt_t extends Bundle { val pc4 = UInt(1.W) val hist = UInt(2.W) val toffset = UInt(12.W) - // val valid = UInt(1.W) + // val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) val prett = UInt(31.W) @@ -460,7 +479,7 @@ class dest_pkt_t extends Bundle { val i0store = UInt(1.W) val i0div = UInt(1.W) val i0v = UInt(1.W) - // val i0valid = UInt(1.W) + // val i0valid = UInt(1.W) val csrwen = UInt(1.W) val csrwonly = UInt(1.W) val csrwaddr = UInt(12.W) @@ -514,11 +533,11 @@ class lsu_pkt_t extends Bundle { val store_data_bypass_d = Bool() val load_ldst_bypass_d = Bool() val store_data_bypass_m = Bool() -// val valid = Bool() + // val valid = Bool() } class lsu_error_pkt_t extends Bundle { - // val exc_valid = UInt(1.W) + // val exc_valid = UInt(1.W) val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault @@ -580,7 +599,7 @@ class dec_pkt_t extends Bundle { } class mul_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val rs1_sign = UInt(1.W) val rs2_sign = UInt(1.W) val low = UInt(1.W) @@ -602,7 +621,7 @@ class mul_pkt_t extends Bundle { } class div_pkt_t extends Bundle { - // val valid = UInt(1.W) + // val valid = UInt(1.W) val unsign = UInt(1.W) val rem = UInt(1.W) } @@ -744,4 +763,4 @@ class dec_tlu_csr_pkt extends Bundle{ val presync =UInt(1.W) val postsync =UInt(1.W) val legal =UInt(1.W) -} +} \ No newline at end of file diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 2b75019d..63a820b7 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -20,14 +20,14 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val axi_rid = Input(UInt(TAG.W)) val axi_rdata = Input(UInt(64.W)) val axi_rresp = Input(UInt(2.W)) - val ahb_haddr = Input(UInt(32.W)) // ahb bus address - val ahb_hburst = Input(UInt(3.W)) // tied to 0 - val ahb_hmastlock = Input(Bool()) // tied to 0 - val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 - val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) - val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) - val ahb_hwrite = Input(Bool()) // ahb bus write - val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data + // val ahb_haddr = Input(UInt(32.W)) // ahb bus address + // val ahb_hburst = Input(UInt(3.W)) // tied to 0 + // val ahb_hmastlock = Input(Bool()) // tied to 0 + // val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 + // val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) + // val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) + // val ahb_hwrite = Input(Bool()) // ahb bus write + // val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data val ahb_hsel = Input(Bool()) // this slave was selected val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not // outputs @@ -51,9 +51,10 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val axi_arlen = Output(UInt(8.W)) val axi_arburst = Output(UInt(2.W)) val axi_rready = Output(Bool()) - val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data - val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction - val ahb_hresp = Output(Bool()) // slave response (high indicates erro) + val ahb = Flipped(new ahb_channel()) + // val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data + // val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction + // val ahb_hresp = Output(Bool()) // slave response (high indicates erro) }) val idle:: wr :: rd :: pend :: Nil = Enum(4) val TAG= 1 @@ -114,18 +115,18 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { switch(buf_state) { is(idle) { - buf_nxtstate := Mux(io.ahb_hwrite, wr, rd) - buf_state_en := ahb_hready & io.ahb_htrans(1) & io.ahb_hsel // only transition on a valid hrtans + buf_nxtstate := Mux(io.ahb.out.hwrite, wr, rd) + buf_state_en := ahb_hready & io.ahb.out.htrans(1) & io.ahb_hsel // only transition on a valid hrtans } is(wr) { // Write command recieved last cycle - buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd)) - buf_state_en := (!cmdbuf_full | io.ahb_hresp) - cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. + buf_nxtstate := Mux((io.ahb.in.hresp | (io.ahb.out.htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb.out.hwrite, wr, rd)) + buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) + cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.in.hresp | ((io.ahb.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. } is(rd) { // Read command recieved last cycle. - buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data - buf_state_en := (!cmdbuf_full | io.ahb_hresp) // only when command can go, or if its an error - cmdbuf_wr_en := !io.ahb_hresp & !cmdbuf_full // send command only when no error + buf_nxtstate := Mux(io.ahb.in.hresp, idle, pend) // If error go to idle, else wait for read data + buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) // only when command can go, or if its an error + cmdbuf_wr_en := !io.ahb.in.hresp & !cmdbuf_full // send command only when no error } is(pend) { // Read Command has been sent. Waiting on Data. buf_nxtstate := idle // go back for next command and present data next cycle @@ -142,11 +143,11 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { (Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U) // AHB signals - io.ahb_hreadyout := Mux(io.ahb_hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) - ahb_hready := io.ahb_hreadyout & io.ahb_hreadyin - ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb_htrans(1,0) - io.ahb_hrdata := buf_rdata(63,0) - io.ahb_hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & + io.ahb.in.hready := Mux(io.ahb.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error)) + ahb_hready := io.ahb.in.hready & io.ahb_hreadyin + ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb.out.htrans(1,0) + io.ahb.in.hrdata := buf_rdata(63,0) + io.ahb.in.hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) & ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned @@ -160,22 +161,22 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)} // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer. - ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb_hresp,0.U)} + ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.in.hresp,0.U)} ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)} ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)} - ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb_hsize,0.U)} - ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb_hwrite,0.U)} - ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb_haddr,0.U)} + ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hsize,0.U)} + ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.hwrite,0.U)} + ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.out.haddr,0.U)} // Clock header logic - ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb_htrans(1)) + ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.out.htrans(1)) buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en; ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode) buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode) - cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write) + cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.in.hresp & !cmdbuf_write) cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready))) //rvdffsc cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)} @@ -192,7 +193,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { //rvdffe cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) - cmdbuf_wdata := rvdffe(io.ahb_hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) + cmdbuf_wdata := rvdffe(io.ahb.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) // AXI Write Command Channel io.axi_awvalid := cmdbuf_vld & cmdbuf_write @@ -222,4 +223,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) -} \ No newline at end of file +} +object AHB_main extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))} \ No newline at end of file diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index d237bee7..81f42ba3 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -2,6 +2,7 @@ package lib import chisel3._ import chisel3.util._ +import include._ trait Config { val TAG = 1 @@ -28,9 +29,6 @@ class axi4_to_ahb_IO extends Bundle with Config { val axi_arsize = Input(UInt(3.W)) // [2:0] val axi_arprot = Input(UInt(3.W)) // [2:0] val axi_rready = Input(Bool()) - val ahb_hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data - val ahb_hready = Input(Bool()) // slave ready to accept transaction - val ahb_hresp = Input(Bool()) // slave response (high indicates erro) //----------------------------outputs--------------------------- val axi_awready = Output(Bool()) val axi_wready = Output(Bool()) @@ -45,16 +43,12 @@ class axi4_to_ahb_IO extends Bundle with Config { val axi_rresp = Output(UInt(2.W)) // 1:0] val axi_rlast = Output(Bool()) // AHB-Lite signals - val ahb_haddr = Output(UInt(32.W)) // [31:0] // ahb bus address - val ahb_hburst = Output(UInt(3.W)) // [2:0] // tied to 0 - val ahb_hmastlock = Output(Bool()) // tied to 0 - val ahb_hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 - val ahb_hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) - val ahb_htrans = Output(UInt(2.W)) - val ahb_hwrite = Output(Bool()) // ahb bus write - val ahb_hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data + val ahb = new ahb_channel } + + + class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) val buf_rst = WireInit(0.U(1.W)) @@ -202,7 +196,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode) //State machine - io.ahb_htrans := 0.U + io.ahb.out.htrans := 0.U master_ready := 0.U buf_state_en := false.B buf_nxtstate := idle @@ -233,7 +227,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B)), master_addr(2, 0)) bypass_en := buf_state_en rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd) - io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U + io.ahb.out.htrans := (Fill(2, bypass_en)) & "b10".U } is(cmd_rd) { @@ -245,7 +239,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { buf_wr_en := master_ready bypass_en := master_ready & master_valid buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) - io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) + io.ahb.out.htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) } is(stream_rd) { @@ -260,7 +254,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) - io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) + io.ahb.out.htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) slvbuf_wr_en := buf_wr_en// shifting the contents from the buf to slv_buf for streaming cases } @@ -270,7 +264,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slave_valid_pre := buf_state_en slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer buf_cmd_byte_ptr := buf_addr(2, 0) - io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en) + io.ahb.out.htrans := "b10".U(2.W) & Fill(2, !buf_state_en) } is(data_rd) { @@ -290,7 +284,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slvbuf_wr_en := buf_state_en buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)), buf_cmd_byte_ptrQ) cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U)) - io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U + io.ahb.out.htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U } is(data_wr) { @@ -305,7 +299,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1,0) =/= 0.U) & ((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)) === 0.U)))) bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) - io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U + io.ahb.out.htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U) buf_cmd_byte_ptr_en := trxn_done | bypass_en @@ -349,21 +343,21 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) | (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) // Generate the ahb signals - io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) - io.ahb_hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))) + io.ahb.out.haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) + io.ahb.out.hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))) - io.ahb_hburst := "b0".U - io.ahb_hmastlock := "b0".U - io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2)) - io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) - io.ahb_hwdata := buf_data(63, 0) + io.ahb.out.hburst := "b0".U + io.ahb.out.hmastlock := "b0".U + io.ahb.out.hprot := Cat("b001".U, ~io.axi_arprot(2)) + io.ahb.out.hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) + io.ahb.out.hwdata := buf_data(63, 0) slave_valid := slave_valid_pre slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U) slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0))) slave_tag := slvbuf_tag(TAG - 1, 0) - last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite + last_addr_en := (io.ahb.out.htrans(1, 0) =/= "b0".U) & io.ahb.in.hready & io.ahb.out.hwrite // Write buffer wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready @@ -382,7 +376,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,bus_clk,io.scan_mode) wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,bus_clk,io.scan_mode) wrbuf_byteen := withClock(bus_clk) {RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())} - last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())} + last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb.out.haddr(31, 0), 0.U, last_addr_en.asBool())} buf_write := withClock(buf_clk) {RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())} buf_tag := withClock(buf_clk) {RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())} buf_addr := rvdffe(buf_addr_in(31, 0),(buf_wr_en & io.bus_clk_en).asBool,clock,io.scan_mode) @@ -395,14 +389,14 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { slvbuf_error := withClock(ahbm_clk) {RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())} cmd_doneQ := withClock(ahbm_clk) {RegNext(Mux(cmd_done.asBool(),1.U,cmd_doneQ) & !cmd_done_rst, 0.U)} buf_cmd_byte_ptrQ := withClock(ahbm_clk) {RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())} - ahb_hready_q := withClock(ahbm_clk) {RegNext(io.ahb_hready, 0.U)} - ahb_htrans_q := withClock(ahbm_clk) {RegNext(io.ahb_htrans(1, 0), 0.U)} - ahb_hwrite_q := withClock(ahbm_addr_clk) {RegNext(io.ahb_hwrite, 0.U)} - ahb_hresp_q := withClock(ahbm_clk) {RegNext(io.ahb_hresp, 0.U)} - ahb_hrdata_q := withClock(ahbm_data_clk) {RegNext(io.ahb_hrdata(63, 0), 0.U)} + ahb_hready_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hready, 0.U)} + ahb_htrans_q := withClock(ahbm_clk) {RegNext(io.ahb.out.htrans(1, 0), 0.U)} + ahb_hwrite_q := withClock(ahbm_addr_clk) {RegNext(io.ahb.out.hwrite, 0.U)} + ahb_hresp_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hresp, 0.U)} + ahb_hrdata_q := withClock(ahbm_data_clk) {RegNext(io.ahb.in.hrdata(63, 0), 0.U)} buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) - ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override) + ahbm_addr_clken := io.bus_clk_en & ((io.ahb.in.hready & io.ahb.out.htrans(1)) | io.clk_override) ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) //Clkhdr @@ -410,4 +404,9 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) +} + +object AXImain extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) } \ No newline at end of file diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 365ee5ee..00235400 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -14,6 +14,11 @@ class quasar_bundle extends Bundle with lib{ val sb_axi = new axi_channels(SB_BUS_TAG) val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) + val ahb = new ahb_channel + val lsu_ahb = new ahb_channel + val sb_ahb = new ahb_channel + val dma_ahb = Flipped(new ahb_channel) + val dbg_rst_l = Input(AsyncReset()) val rst_vec = Input(UInt(31.W)) val nmi_int = Input(Bool()) @@ -44,58 +49,59 @@ class quasar_bundle extends Bundle with lib{ val ic = new ic_mem() val iccm = new iccm_mem() - // AHB Lite Bus - val haddr = Output(UInt(32.W)) - val hburst = Output(UInt(3.W)) - val hmastlock = Output(Bool()) - val hprot = Output(UInt(4.W)) - val hsize = Output(UInt(3.W)) - val htrans = Output(UInt(2.W)) - val hwrite = Output(Bool()) - val hrdata = Input(UInt(64.W)) - val hready = Input(Bool()) - val hresp = Input(Bool()) - - // AHB Master - val lsu_haddr = Output(UInt(32.W)) - val lsu_hburst = Output(UInt(3.W)) - val lsu_hmastlock = Output(Bool()) - val lsu_hprot = Output(UInt(4.W)) - val lsu_hsize = Output(UInt(3.W)) - val lsu_htrans = Output(UInt(2.W)) - val lsu_hwrite = Output(Bool()) - val lsu_hwdata = Output(UInt(64.W)) - val lsu_hrdata = Input(UInt(64.W)) - val lsu_hready = Input(Bool()) - val lsu_hresp = Input(Bool()) - - // System Bus Debug Master - val sb_haddr = Output(UInt(32.W)) - val sb_hburst = Output(UInt(3.W)) - val sb_hmastlock = Output(Bool()) - val sb_hprot = Output(UInt(4.W)) - val sb_hsize = Output(UInt(3.W)) - val sb_htrans = Output(UInt(2.W)) - val sb_hwrite = Output(Bool()) - val sb_hwdata = Output(UInt(64.W)) - val sb_hrdata = Input(UInt(64.W)) - val sb_hready = Input(Bool()) - val sb_hresp = Input(Bool()) - - // DMA slave + // // AHB Lite Bus + // val haddr = Output(UInt(32.W)) + // val hburst = Output(UInt(3.W)) + // val hmastlock = Output(Bool()) + // val hprot = Output(UInt(4.W)) + // val hsize = Output(UInt(3.W)) + // val htrans = Output(UInt(2.W)) + // val hwrite = Output(Bool()) + // val hrdata = Input(UInt(64.W)) + // val hready = Input(Bool()) + // val hresp = Input(Bool()) + // + // // AHB Master + // val lsu_haddr = Output(UInt(32.W)) + // val lsu_hburst = Output(UInt(3.W)) + // val lsu_hmastlock = Output(Bool()) + // val lsu_hprot = Output(UInt(4.W)) + // val lsu_hsize = Output(UInt(3.W)) + // val lsu_htrans = Output(UInt(2.W)) + // val lsu_hwrite = Output(Bool()) + // val lsu_hwdata = Output(UInt(64.W)) + // val lsu_hrdata = Input(UInt(64.W)) + // val lsu_hready = Input(Bool()) + // val lsu_hresp = Input(Bool()) + // + // // System Bus Debug Master + // val sb_haddr = Output(UInt(32.W)) + // val sb_hburst = Output(UInt(3.W)) + // val sb_hmastlock = Output(Bool()) + // val sb_hprot = Output(UInt(4.W)) + // val sb_hsize = Output(UInt(3.W)) + // val sb_htrans = Output(UInt(2.W)) + // val sb_hwrite = Output(Bool()) + // val sb_hwdata = Output(UInt(64.W)) + // val sb_hrdata = Input(UInt(64.W)) + // val sb_hready = Input(Bool()) + // val sb_hresp = Input(Bool()) + // + // // DMA slave val dma_hsel = Input(Bool()) - val dma_haddr = Input(UInt(32.W)) - val dma_hburst = Input(UInt(3.W)) - val dma_hmastlock = Input(Bool()) - val dma_hprot = Input(UInt(4.W)) - val dma_hsize = Input(UInt(3.W)) - val dma_htrans = Input(UInt(2.W)) - val dma_hwrite = Input(Bool()) - val dma_hwdata = Input(UInt(64.W)) + // val dma_haddr = Input(UInt(32.W)) + // val dma_hburst = Input(UInt(3.W)) + // val dma_hmastlock = Input(Bool()) + // val dma_hprot = Input(UInt(4.W)) + // val dma_hsize = Input(UInt(3.W)) + // val dma_htrans = Input(UInt(2.W)) + // val dma_hwrite = Input(Bool()) + // val dma_hwdata = Input(UInt(64.W)) val dma_hreadyin = Input(Bool()) - val dma_hrdata = Output(UInt(64.W)) - val dma_hreadyout = Output(Bool()) - val dma_hresp = Output(Bool()) + // val dma_hrdata = Output(UInt(64.W)) + // val dma_hreadyout = Output(Bool()) + // val dma_hresp = Output(Bool()) + val lsu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool()) val dbg_bus_clk_en = Input(Bool()) @@ -317,9 +323,9 @@ class quasar extends Module with RequireAsyncReset with lib { lsu_axi4_to_ahb.io.axi_arprot := io.lsu_axi.ar.bits.prot lsu_axi4_to_ahb.io.axi_rready := io.lsu_axi.r.ready - lsu_axi4_to_ahb.io.ahb_hrdata := io.lsu_hrdata - lsu_axi4_to_ahb.io.ahb_hready := io.lsu_hready - lsu_axi4_to_ahb.io.ahb_hresp := io.lsu_hresp + // lsu_axi4_to_ahb.io.ahb_hrdata := io.lsu_hrdata + // lsu_axi4_to_ahb.io.ahb_hready := io.lsu_hready + // lsu_axi4_to_ahb.io.ahb_hresp := io.lsu_hresp val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) ifu_axi4_to_ahb.io.axi_awvalid := io.ifu_axi.aw.valid @@ -345,9 +351,9 @@ class quasar extends Module with RequireAsyncReset with lib { ifu_axi4_to_ahb.io.axi_rready := io.ifu_axi.r.ready - ifu_axi4_to_ahb.io.ahb_hrdata := io.hrdata - ifu_axi4_to_ahb.io.ahb_hready := io.hready - ifu_axi4_to_ahb.io.ahb_hresp := io.hresp + // ifu_axi4_to_ahb.io.ahb_hrdata := io.hrdata + // ifu_axi4_to_ahb.io.ahb_hready := io.hready + // ifu_axi4_to_ahb.io.ahb_hresp := io.hresp val sb_axi4_to_ahb = Module(new axi4_to_ahb()) sb_axi4_to_ahb.io.axi_awvalid := io.sb_axi.aw.valid @@ -372,9 +378,9 @@ class quasar extends Module with RequireAsyncReset with lib { sb_axi4_to_ahb.io.axi_arprot := io.sb_axi.ar.bits.prot sb_axi4_to_ahb.io.axi_rready := io.sb_axi.r.ready - sb_axi4_to_ahb.io.ahb_hrdata := io.sb_hrdata - sb_axi4_to_ahb.io.ahb_hready := io.sb_hready - sb_axi4_to_ahb.io.ahb_hresp := io.sb_hresp + // sb_axi4_to_ahb.io.ahb_hrdata := io.sb_hrdata + // sb_axi4_to_ahb.io.ahb_hready := io.sb_hready + // sb_axi4_to_ahb.io.ahb_hresp := io.sb_hresp val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) dma_ahb_to_axi4.io.scan_mode := io.scan_mode @@ -394,18 +400,16 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ahb_to_axi4.io.axi_rresp := io.dma_axi.r.bits.resp // AHB-Lite signals - dma_ahb_to_axi4.io.ahb_haddr := io.dma_haddr - dma_ahb_to_axi4.io.ahb_hburst := io.dma_hburst - dma_ahb_to_axi4.io.ahb_hmastlock := io.dma_hmastlock - dma_ahb_to_axi4.io.ahb_hprot := io.dma_hprot - dma_ahb_to_axi4.io.ahb_hsize := io.dma_hsize - dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans - dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite - dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata + // dma_ahb_to_axi4.io.ahb_haddr := io.dma_haddr + // dma_ahb_to_axi4.io.ahb_hburst := io.dma_hburst + // dma_ahb_to_axi4.io.ahb_hmastlock := io.dma_hmastlock + // dma_ahb_to_axi4.io.ahb_hprot := io.dma_hprot + // dma_ahb_to_axi4.io.ahb_hsize := io.dma_hsize + // dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans + // dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite + // dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin - - // Mux for the axi-bridge lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @@ -450,77 +454,81 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) - - // AHB Signals - io.haddr := ifu_axi4_to_ahb.io.ahb_haddr - io.hburst := ifu_axi4_to_ahb.io.ahb_hburst - io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock - io.hprot := ifu_axi4_to_ahb.io.ahb_hprot - io.hsize := ifu_axi4_to_ahb.io.ahb_hsize - io.htrans := ifu_axi4_to_ahb.io.ahb_htrans - io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite + io.ahb <> ifu_axi4_to_ahb.io.ahb + // io.haddr := ifu_axi4_to_ahb.io.ahb_haddr + // io.hburst := ifu_axi4_to_ahb.io.ahb_hburst + // io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock + // io.hprot := ifu_axi4_to_ahb.io.ahb_hprot + // io.hsize := ifu_axi4_to_ahb.io.ahb_hsize + // io.htrans := ifu_axi4_to_ahb.io.ahb_htrans + // io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite + io.lsu_ahb <> lsu_axi4_to_ahb.io.ahb + // io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr + // io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst + // io.lsu_hmastlock := lsu_axi4_to_ahb.io.ahb_hmastlock + // io.lsu_hprot := lsu_axi4_to_ahb.io.ahb_hprot + // io.lsu_hsize := lsu_axi4_to_ahb.io.ahb_hsize + // io.lsu_htrans := lsu_axi4_to_ahb.io.ahb_htrans + // io.lsu_hwrite := lsu_axi4_to_ahb.io.ahb_hwrite + // io.lsu_hwdata := lsu_axi4_to_ahb.io.ahb_hwdata - io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr - io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst - io.lsu_hmastlock := lsu_axi4_to_ahb.io.ahb_hmastlock - io.lsu_hprot := lsu_axi4_to_ahb.io.ahb_hprot - io.lsu_hsize := lsu_axi4_to_ahb.io.ahb_hsize - io.lsu_htrans := lsu_axi4_to_ahb.io.ahb_htrans - io.lsu_hwrite := lsu_axi4_to_ahb.io.ahb_hwrite - io.lsu_hwdata := lsu_axi4_to_ahb.io.ahb_hwdata + io.sb_ahb <> sb_axi4_to_ahb.io.ahb + // io.sb_haddr := sb_axi4_to_ahb.io.ahb_haddr + // io.sb_hburst := sb_axi4_to_ahb.io.ahb_hburst + // io.sb_hmastlock := sb_axi4_to_ahb.io.ahb_hmastlock + // io.sb_hprot := sb_axi4_to_ahb.io.ahb_hprot + // io.sb_hsize := sb_axi4_to_ahb.io.ahb_hsize + // io.sb_htrans := sb_axi4_to_ahb.io.ahb_htrans + // io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite + // io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata - io.sb_haddr := sb_axi4_to_ahb.io.ahb_haddr - io.sb_hburst := sb_axi4_to_ahb.io.ahb_hburst - io.sb_hmastlock := sb_axi4_to_ahb.io.ahb_hmastlock - io.sb_hprot := sb_axi4_to_ahb.io.ahb_hprot - io.sb_hsize := sb_axi4_to_ahb.io.ahb_hsize - io.sb_htrans := sb_axi4_to_ahb.io.ahb_htrans - io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite - io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata - - io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata - io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout - io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp + io.dma_ahb <> dma_ahb_to_axi4.io.ahb + // io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata + // io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout + // io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp + // io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata + // io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata } - .otherwise{ - // AHB Signals - io.haddr := 0.U - io.hburst := 0.U - io.hmastlock := 0.U - io.hprot := 0.U - io.hsize := 0.U - io.htrans := 0.U - io.hwrite := 0.U + .otherwise{ + // AHB Signals + io.ahb.out <> 0.U.asTypeOf(io.ahb.out) + // io.haddr := 0.U + // io.hburst := 0.U + // io.hmastlock := 0.U + // io.hprot := 0.U + // io.hsize := 0.U + // io.htrans := 0.U + // io.hwrite := 0.U + io.lsu_ahb.out <> 0.U.asTypeOf(io.lsu_ahb.out) + // io.lsu_haddr := 0.U + // io.lsu_hburst := 0.U + // io.lsu_hmastlock := 0.U + // io.lsu_hprot := 0.U + // io.lsu_hsize := 0.U + // io.lsu_htrans := 0.U + // io.lsu_hwrite := 0.U + // io.lsu_hwdata := 0.U - io.lsu_haddr := 0.U - io.lsu_hburst := 0.U - io.lsu_hmastlock := 0.U - io.lsu_hprot := 0.U - io.lsu_hsize := 0.U - io.lsu_htrans := 0.U - io.lsu_hwrite := 0.U - io.lsu_hwdata := 0.U - - io.sb_haddr := 0.U - io.sb_hburst := 0.U - io.sb_hmastlock := 0.U - io.sb_hprot := 0.U - io.sb_hsize := 0.U - io.sb_htrans := 0.U - io.sb_hwrite := 0.U - io.sb_hwdata := 0.U - - io.dma_hrdata := 0.U - io.dma_hreadyout := 0.U - io.dma_hresp := 0.U - } + io.sb_ahb.out <> 0.U.asTypeOf(io.sb_ahb.out) + // io.sb_haddr := 0.U + // io.sb_hburst := 0.U + // io.sb_hmastlock := 0.U + // io.sb_hprot := 0.U + // io.sb_hsize := 0.U + // io.sb_htrans := 0.U + // io.sb_hwrite := 0.U + // io.sb_hwdata := 0.U + io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) + // io.dma_hrdata := 0.U + // io.dma_hreadyout := 0.U + // io.dma_hresp := 0.U + } io.dmi_reg_rdata := 0.U } - diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala index a694850d..4510af97 100644 --- a/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -20,18 +20,19 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { // DMA slave val dma_hsel = Input(Bool()) - val dma_haddr = Input(UInt(32.W)) - val dma_hburst = Input(UInt(3.W)) - val dma_hmastlock = Input(Bool()) - val dma_hprot = Input(UInt(4.W)) - val dma_hsize = Input(UInt(3.W)) - val dma_htrans = Input(UInt(2.W)) - val dma_hwrite = Input(Bool()) - val dma_hwdata = Input(UInt(64.W)) + val dma_ahb = Flipped(new ahb_channel()) + // val dma_haddr = Input(UInt(32.W)) + // val dma_hburst = Input(UInt(3.W)) + // val dma_hmastlock = Input(Bool()) + // val dma_hprot = Input(UInt(4.W)) + // val dma_hsize = Input(UInt(3.W)) + // val dma_htrans = Input(UInt(2.W)) + // val dma_hwrite = Input(Bool()) + // val dma_hwdata = Input(UInt(64.W)) val dma_hreadyin = Input(Bool()) - val dma_hrdata = Output(UInt(64.W)) - val dma_hreadyout = Output(Bool()) - val dma_hresp = Output(Bool()) + // val dma_hrdata = Output(UInt(64.W)) + // val dma_hreadyout = Output(Bool()) + // val dma_hresp = Output(Bool()) val lsu_bus_clk_en = Input(Bool()) val ifu_bus_clk_en = Input(Bool()) @@ -74,127 +75,149 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { val rv_trace_pkt = new trace_pkt_t() val scan_mode = Input(Bool()) -}) + }) val mem = Module(new quasar.mem()) val dmi_wrapper = Module(new dmi_wrapper()) - val core = Module(new quasar()) + val swerv = Module(new quasar()) dmi_wrapper.io.trst_n := io.jtag_trst_n dmi_wrapper.io.tck := io.jtag_tck dmi_wrapper.io.tms := io.jtag_tms dmi_wrapper.io.tdi := io.jtag_tdi dmi_wrapper.io.core_clk := clock dmi_wrapper.io.jtag_id := io.jtag_id - dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata + dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata dmi_wrapper.io.core_rst_n := io.dbg_rst_l - core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data - core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr - core.io.dmi_reg_en := dmi_wrapper.io.reg_en - core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en - core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset + swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data + swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr + swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en + swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en + swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset io.jtag_tdo := dmi_wrapper.io.tdo // Memory signals - mem.io.dccm_clk_override := core.io.dccm_clk_override - mem.io.icm_clk_override := core.io.icm_clk_override - mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable - mem.io.dccm <> core.io.dccm + mem.io.dccm_clk_override := swerv.io.dccm_clk_override + mem.io.icm_clk_override := swerv.io.icm_clk_override + mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable + mem.io.dccm <> swerv.io.dccm mem.io.rst_l := reset mem.io.clk := clock mem.io.scan_mode := io.scan_mode // Memory outputs - core.io.dbg_rst_l := io.dbg_rst_l - core.io.ic <> mem.io.ic - core.io.iccm <> mem.io.iccm - core.io.sb_hready := 0.U - core.io.hrdata := 0.U - core.io.sb_hresp := 0.U - core.io.lsu_hrdata := 0.U - core.io.lsu_hresp := 0.U - core.io.lsu_hready := 0.U - core.io.hready := 0.U - core.io.hresp := 0.U - core.io.sb_hrdata := 0.U - core.io.scan_mode := io.scan_mode + swerv.io.dbg_rst_l := io.dbg_rst_l + swerv.io.ic <> mem.io.ic + swerv.io.iccm <> mem.io.iccm + + swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in) + swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in) + swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in) + io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in) + // swerv.io.sb_hready := 0.U + // swerv.io.hrdata := 0.U + // swerv.io.sb_hresp := 0.U + // swerv.io.lsu_hrdata := 0.U + // swerv.io.lsu_hresp := 0.U + // swerv.io.lsu_hready := 0.U + // swerv.io.hready := 0.U + // swerv.io.hresp := 0.U + // swerv.io.sb_hrdata := 0.U + swerv.io.scan_mode := io.scan_mode // SweRV Inputs - core.io.dbg_rst_l := io.dbg_rst_l - core.io.rst_vec := io.rst_vec - core.io.nmi_int := io.nmi_int - core.io.nmi_vec := io.nmi_vec + swerv.io.dbg_rst_l := io.dbg_rst_l + swerv.io.rst_vec := io.rst_vec + swerv.io.nmi_int := io.nmi_int + swerv.io.nmi_vec := io.nmi_vec // external halt/run interface - core.io.i_cpu_halt_req := io.i_cpu_halt_req - core.io.i_cpu_run_req := io.i_cpu_run_req - core.io.core_id := io.core_id + swerv.io.i_cpu_halt_req := io.i_cpu_halt_req + swerv.io.i_cpu_run_req := io.i_cpu_run_req + swerv.io.core_id := io.core_id // external MPC halt/run interface - core.io.mpc_debug_halt_req := io.mpc_debug_halt_req - core.io.mpc_debug_run_req := io.mpc_debug_run_req - core.io.mpc_reset_run_req := io.mpc_reset_run_req + swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req + swerv.io.mpc_debug_run_req := io.mpc_debug_run_req + swerv.io.mpc_reset_run_req := io.mpc_reset_run_req //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels - core.io.lsu_axi <> io.lsu_axi + swerv.io.lsu_axi <> io.lsu_axi //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels - core.io.ifu_axi <> io.ifu_axi + swerv.io.ifu_axi <> io.ifu_axi //-------------------------- SB AXI signals-------------------------- // AXI Write Channels - core.io.sb_axi <> io.sb_axi + swerv.io.sb_axi <> io.sb_axi //-------------------------- DMA AXI signals-------------------------- // AXI Write Channels - core.io.dma_axi <> io.dma_axi + swerv.io.dma_axi <> io.dma_axi // DMA Slave - core.io.dma_hsel := io.dma_hsel - core.io.dma_haddr := io.dma_haddr - core.io.dma_hburst := io.dma_hburst - core.io.dma_hmastlock := io.dma_hmastlock - core.io.dma_hprot := io.dma_hprot - core.io.dma_hsize := io.dma_hsize - core.io.dma_htrans := io.dma_htrans - core.io.dma_hwrite := io.dma_hwrite - core.io.dma_hwdata := io.dma_hwdata - core.io.dma_hreadyin := io.dma_hreadyin + swerv.io.dma_hsel := io.dma_hsel + swerv.io.dma_ahb.out <> io.dma_ahb.out + // swerv.io.dma_haddr := io.dma_haddr + // swerv.io.dma_hburst := io.dma_hburst + // swerv.io.dma_hmastlock := io.dma_hmastlock + // swerv.io.dma_hprot := io.dma_hprot + // swerv.io.dma_hsize := io.dma_hsize + // swerv.io.dma_htrans := io.dma_htrans + // swerv.io.dma_hwrite := io.dma_hwrite + // swerv.io.dma_hwdata := io.dma_hwdata + swerv.io.dma_hreadyin := io.dma_hreadyin - core.io.lsu_bus_clk_en := io.lsu_bus_clk_en - core.io.ifu_bus_clk_en := io.ifu_bus_clk_en - core.io.dbg_bus_clk_en := io.dbg_bus_clk_en - core.io.dma_bus_clk_en := io.dma_bus_clk_en + swerv.io.lsu_bus_clk_en + swerv.io.ifu_bus_clk_en + swerv.io.dbg_bus_clk_en + swerv.io.dma_bus_clk_en - core.io.timer_int := io.timer_int - core.io.soft_int := io.soft_int - core.io.extintsrc_req := io.extintsrc_req + swerv.io.dmi_reg_en + swerv.io.dmi_reg_addr + swerv.io.dmi_reg_wr_en + swerv.io.dmi_reg_wdata + swerv.io.dmi_hard_reset + + swerv.io.extintsrc_req + swerv.io.timer_int + swerv.io.soft_int + swerv.io.scan_mode + + swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en + swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en + swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en + swerv.io.dma_bus_clk_en := io.dma_bus_clk_en + + swerv.io.timer_int := io.timer_int + swerv.io.soft_int := io.soft_int + swerv.io.extintsrc_req := io.extintsrc_req // Outputs - val core_rst_l = core.io.core_rst_l - io.rv_trace_pkt := core.io.rv_trace_pkt + val core_rst_l = swerv.io.core_rst_l + io.rv_trace_pkt := swerv.io.rv_trace_pkt // external halt/run interface - io.o_cpu_halt_ack := core.io.o_cpu_halt_ack - io.o_cpu_halt_status := core.io.o_cpu_halt_status - io.o_cpu_run_ack := core.io.o_cpu_run_ack - io.o_debug_mode_status := core.io.o_debug_mode_status + io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack + io.o_cpu_halt_status := swerv.io.o_cpu_halt_status + io.o_cpu_run_ack := swerv.io.o_cpu_run_ack + io.o_debug_mode_status := swerv.io.o_debug_mode_status - io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack - io.mpc_debug_run_ack := core.io.mpc_debug_run_ack - io.debug_brkpt_status := core.io.debug_brkpt_status + io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack + io.debug_brkpt_status := swerv.io.debug_brkpt_status - io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0 - io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1 - io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2 - io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3 + io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels // DMA Slave - io.dma_hrdata := core.io.dma_hrdata - io.dma_hreadyout := core.io.dma_hreadyout - io.dma_hresp := core.io.dma_hresp + // io.dma_hrdata := swerv.io.dma_hrdata + // io.dma_hreadyout := swerv.io.dma_hreadyout + // io.dma_hresp := swerv.io.dma_hresp } object QUASAR_Wrp extends App { diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 269d4e31dc280f4d2677e3f8cae4079247873cc3..a5fbfae2ed2dd9260440c2a1f588692c8d907a3e 100644 GIT binary patch delta 99 zcmbO%H(74O4KBv}lW%g_0!ag2@yUAJo={dlw-u0eirWTAvhzUXB`3%6SOEFcd0fG& iBqx94u>`YX7#~dT<@IHKz@W}>fAW3a3ZQ5N-);clOe3ZM delta 99 zcmbO%H(74O4KBtLlW%g_0!ag2@yUAJo={dlw-u0eirWTAvhzUXB`3%6SOEFcd0fG& iBqx94u>`YX7*9^_<@IGf$)L_~V)A|73ZQ5N-);b_k0N^j diff --git a/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class b/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class index 684eeb3ff21b69ace4dfe2ae9b7398dbc6366339..bf1fb1c5a51d9c54ae53a3ce62af121232e798b3 100644 GIT binary patch delta 19 Zcmcb~dXsg74HM)2$+k=ZK(dd?8vsdN2KxX2 delta 19 Zcmcb~dXsg74HM&u$+k=ZK(dd?8vsY`2F(Bf diff --git a/target/scala-2.12/classes/dbg/dbg$.class b/target/scala-2.12/classes/dbg/dbg$.class new file mode 100644 index 0000000000000000000000000000000000000000..2f69190bd6690205a49df69efca8bf20dc444465 GIT binary patch literal 3820 zcmbtX`F9gl6#ibfv?0*aQXqh`1xdpapg@sSgtj2Xw4k9?M8#?HQU<0oVKM=VinxLM zhWqj-c#aDc4n4=;|*T4S0_XmL8_(`C(Ffp0t zm54wHbez*JYH33=C)39#&dIzJL8CxhIjP}Bp z9Bsmo>8xIM1}ep(w7EK0k6gbmbfjXss&)hucExn`DVZLyF3Z9gjb{$%(?x%Eqt_+m)rX3;VGc+R@QQw0Fg@6rJjAH{l57 ziHYwAC?uhg=DI>^6F`~>ZqdQf?@u)M?f#We8!hovcXWCovYzGD! z$-5DCBiVL(e&nRBYlePBF-`=}32dlp@;NoDO-&RuGOJe9@{VOsM{tT{s2NUZPT+bn zlFWol$d4@?uD@VVGmM<>NP>47FGleKUSiNMvn;hz$sika z&DFu&)>HNsXr07kLZDkt>CQOOFf8tsENT_QNw6RbSfgMjRo9g06r9!DdV$d(SF65+!wg`lsWlwDFBrpl7|PHTv$4c};}~SB?(l{L z$dTqOl%h;7a!JdDie@M}S)KjYG-HC3a(20Q2D`j=s8KW_uJU$?A_c&afW%WDURPI#S&tU20 zDNXi;1NZYI$a7in#4=$ReQ?+#yrKv=&l4T0nuy>%o{0jI0A4c&$K4JxY%w}e|1sn<^hEH*$69S(xnw&mqYEH#whBtXV{$zAWmTZ~V99iHo$cy@fW@}TDEr8uUHf);G9yGLa zS#lW7Srt1kkLXHa$3TFgw~pW2bLyNoZ1O-Nhs~nJ(sgIBlY8AnXIpr0Qz^!R?Nlw3 z&j!^n-7)(SWxjCdx+&9!%V)H7WkYSA36o0$A_bCr@G{{ZZQYQ@TM(r?%Whk5WE=^>Rg-de%j#-4hE=?e$b=LXY-eLg-FrEi)*N@^)^2)0VB<;!QI!XJA)dRXhuEADjIu*iAiA ztU?(M?RBu``k2QJ=w>}uxJQlr7R5zeVr|f#pYILo-wEIILAREHc3l+WP@N*omAFNHU|6jr!YArzo)-IJ@prpW>&xnhj~ TvzxsL``mmIDgy+5q!#=GJN<}q literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class b/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class new file mode 100644 index 0000000000000000000000000000000000000000..6d36f6fc5e18645e81fdcf4eb6eff760af119da0 GIT binary patch literal 700 zcmZ`%+iuf96rAH+T&GEsmeL!S78+36N`y-A6odqbN|Bs`l(z3{d)vA=cI0dj`71zN zBp%=iA@Na&v71(+5)a<9XME1=oZ0>T=i7Gxk8oeG5_l(Ve$7BfYNCT~9Ga$=1QQz~ zSReT+Qtfmcn{c4p&%BXIm2dXOv2Vg8erTg0aM=DJFBFuU$=K*rP;oDaJA#rL4x@=+ zv9;x%skf>fsraP*$~)7(=~PjM?Z84sFmuslqbgXPYI+$5!z7GNGuKJ2yMjV%>!^x3 z)GMf=Az1!b>GR~B4h}hsjRisRaKC#%KKDOG)Ub%_4z6K|#pW~|3DzzLxatfCDnALy z{ZvqEU6yq+L2H?yB5soAMG|O1-3?>CKOT5GJy2dmWWh~n>XAyrET4k4zES?0o*GW` zMo*j5BzUb-HPAGaf-3!Focek%%t-3}>|(lcMD}icoY3PO!7hy~@^X1j<|}s=<}m|@ z$Zcki8HI6n`x9orVE!YP-{(c^T+7)n`H2ngtLJ4{!74NQfg7aCD0++*V`JwRO7dfS z=QG*9;?@UZ1>DJ3DdQ^P(s|RAknOoX!Cf|#XeogLHknu`p~*PM2WVyI@?F3Y+#`m+ DZ=sQ0 literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index 3bc2083cc98fd3ae9d4623be7f56679de3c5571c..a3be25add60a9881c3edb1b056aa47dfaa630f34 100644 GIT binary patch literal 275434 zcmcd!2Vk95_5a38-pEbbq%&;_gr<9BwM`e4mvp5~TAJ?p`jWh)p;^u7fKtE#iVFc* zil`_Kh71M7g`g;isE7;4-@khxD(?ONoqO&#^X23Hp9V3#=bU@)y}x_!x#QjMj;H?h z$fq<-TT=8+U5mE2c2?pqs_D8mqwPr7V5Ymava5F}Gtisvu58M5rrS<6_q7jqXQG-3 z{qC;TO8iB&JY6fb^jk8=hPwtb$-z^-Z7rF>%urN|>RKG}E*@-4cc*pjtR_iR4rDsI zGi^ha+ey5=tFt#fG(3=5rE7Vur-m|v`i%Mcdhx7ux<0wyoNg9ZPsodz1(9TNGTB}{ zE8bP8x9SNqeyY&SGxivIL2-Sut9Vv%SCr+YUzhSh$m21kPx2v_pMrdzl1u%Q zj(($C|Fomu<<@`nawkAM?n*eqfGFX4N`8tGjj|*4)OC0$;w|u!H zZ*Hd95R#=az4D@br`1s2@iB@$pihg@5tkZEB=X&e4blA)sZ(UIb|$T z#&R^I(k{3B97i5EUGY~q@yt_l8P8ltztJsU=*YX=@+wCjk8u1lo+XZao?E`$kvF>K zs~vfll9y7xE?_wfs5GAE!oSv$&vVN+I`T%hyvdPwDY?XXAi zIPo;P^$$4uU2gedM;=!_u}rt!kk2vy1SI-^kW;vCEyGM^WJ$k9tqf4BsM<;!E zj~;P)^ip?^9&vi~QmaRoIISLC7Lcolj;J1;h94aPLE#d?$IMok6!BT(IZZeUh3}A zBTkQAYW3(6zv|H?e$_)ux$4nLZuRI=u6lHmyLvA}rE%4xOPs1l zm-yZCBi!Li{BC)-Bkyv{K5-^(t-F( z7nr88IRCua$@)3{jl0@+H-n#>KP%s?Pwq1ZkCvC0FD}T-J2*M5*Il%3c6o92p5*?# z!t|6a=;O@G3gU|*hB2Sydy_l!))ntsba2&0naN^l<=M;IXH7=BhxF*FSwmBb&N^pO zUf!%|TQb?9FD)+K)}ou+&tG_MdHK=_@x10K#buGGxu8r3Z0MbNhsJa@(rD#+rrE`iA5&bI!!V;&XMQJwKgn-n-=RhGi8e zx(_bBWb-bhGehEBQHgwAls{{>UcX?|!Irh<=a#QFb|j*Wn3A3}SCr4`*;mz`+O+UQ z)4`R)YibDBc_`;gCs(JC@=?*aSvMO}=eJXOmpbX4s_rRU*|DZ%;)$NAD>IGx6;lh% zeB(@h^PJN12Hi}F;T}20L4ilcrX|;z_E8C}x zH}lPDd3L_b&3(1)Yg*cO6JCjHPj≪NG^@!9A(CdrB|-x1L$hS%mQCTH!Z{q_MB= zqBW?Go;}r>#!ZAH;ow+WzI*Zhs=>`?oj$(xU{%LKDv$M6yeo|9cD$=LE-GEsit_H7 zsmiq@Gp(@&D((h5B?wC+qnv}%8WnRisLPo|5^ z^OqKv7sv9=yc6+b<T9b{Z9g+Ty0~zBhaEm^3QLq-nzGHs4Kr>Phq1j zY&nI~qo|kZ8!Jm!b*z~@6rF{5_7|N-|FE)u@0kgEdiEio%gRn{DO)v|syRKoa^I42 zb4BUgMWwZw%;d7=HHLZ;$Xm1BsR+D`po#M_!SzX_rm2K;Gl}+v6vwCpz zO0?SltO(z!i*S03(6ES$6T;PSyWhbHc6KA=yq!f)O* z@#L0+RVOoqPvV`hyYFDtAoUB2l7!#kk?y3ExmVvRs!_yV{!H<>ie8+FhM2Kcw5$uy5g<%6%(4y7Eiwop4KA zQJ=_v?Qk-$*d^z7x@d1rx7l32yLZN_)~;P;CxL6|=(2@VdiE|WH_u zgg;koC^}S|ai=5pSNC*Hu0VMfw65DyF}HGW&F}_|FdOfqj?ja#p8Q`3gZeN|*vQ)Ooe%y+8cHfK@hoyZ2N4bS#Q(3H!aZD*+r*KbQIh0noxjbry)@+$LN0xU<6WSrt zK{W+pE@(Op{Cy_w=&3;fe2?pcI!eDC6gz)9s+ z3;VAH!a-Vv!|wKw~?quzv1xtX|fYLeQKAa-?;2F%6Zk{y(+xT8;N3sM}H#Qu`#K6 zVjb*}`-xp{Q2p?A;9i-sphCQ$f>k_zeAJp3v#dH4jLRDT?e-J!AmW?_-VkTRPeu(Ca3+wu3xXLHLJXntL z679${AHX~u`5YM!=NIzQl^qQwr#lzZyy8qjUC-Xyp-zfFNRIMD{M0{VUP5+rdUDU+ z8jSaX+HZh7GC{ZPZuQ_A{7zd0JEeIC+t-2jGzjLB;zLwwR<&8x8+|rt%u1%t@@DPt{i;^+Vd`8Y!cY5X}9hpt1=b*pt z*jt}S&vb`Z{e9=;_Gq+G_soA5PFp#c+H`tZ<+QpQbMGketw(>czPhcmW#ZJH(pBh} z7w~*`%fby?n)NB}`IIX@^vCl`n)j|8&g7SE=)*i%&3A|JyJuo@l=ylvt}Mu#SU2vh zm8~0EXr8Ucv4gceU3t}`#8(lSmGsQ_cs_GxI@U3!8;eGX@2Ea%Ii1*YP@g(VzWOs5 zPlL*r$J2mv;_*}V#F-~r{e%pUagXYS!}GXf&A$$|RxFplGu8ad<}v?5Kf>z?Sf|0fn#;4%UPqWc zj><*#D;SqfG?kqiiX0W2EukYw^e^i?V%;Bn0ZH}(xv%anst55P31IOFCj~;0sKy}Q=*LRx*9!I6U zqay=_Mfj9Ia9lE;80ZWB;2;#LWDJVcHKVH!rQ2i`OZ_lm#%Fu_#-AD-N)KgFinjMo zQ~^AN?U~B-y8Wr*;U61pwZaxyq|_{I?`iAn9UAECP7P!_5pu9K-QGTs862!)!T7<} zw!ze3YwPgfsnm%9ioIBgG6MsB14TKgz?_9PUNkc6GZ&1H-+&Fc&fgEBYhp?x9ROaHLxYhX&GZL&$?G z2NV3__AcaWoXSI6Pdo6X5qy$Ma$*2YCq;!5BA5Mm3il>JtID#;EE$1~QoxY?7*{5b?WtX&aURY1y{Z(B0Q|6vjao z;rL7S_MX(h;7|(19G59^#iKZEnC{9)ZTsXBuo%kp^uu)ES5t$^cd=v(E*4E-oWoYH zNL4TON|vOm5d(}9alrz*v7Lpgmo2fYyBnKlx>JK)7o%;U4r~kV>TN@9L5qq`8nm=T zBsW3^L@0Bwo~swj$)D1C2+MzVGUF})CVz@0-y+s&@!zKgtSxJ zbZv^=4DA-I;7$(kk&vArc26)Oh~op(M3*KFMv{V>JNgP$o<*+KEsJ!LOTc!Ey;sOW zpd7UsD2M$8%49X<2=oBp@lZtMOR~?j8l)Xsr$ssjh6}R_vQFq1T zLyDoH+i^4s*Cux)Q_bs|Q%#Lq*3l5g+t_vt_jhNOpqJX?5v*=<2JWq`7h$8@s@x>! z)9AP(-I?0mH-H{RZ$z0499N@pkKB%jw$tPc>&gqkpr@t*L3+vydWCBEx3r2~vB`M> zbPDP>?nouqu5C$e1OkU^+KP0fUrS4JZ))wj3wLZp;gDp*Mkpt@Z%m=mgeBPCxDSOF zBbLd6`W^M|h%JsICe9skA!*m|NNz~2-`cbm&~2V$n@Bu))ubA?tX;Q90#IsFP%ZJx zV2Y=N9KOcqUz76s*ZTZxrGJc)Wdud_I~$wUrji@$VJJJ0*Mt)6X+(<~Z!@Va$sLWm z;1ALE)P*fOsPNV&cQ)-nuP$vZ+0d|V`*vA2Xb2-@DAf@%^Z_GeX#XQ*Kr%vxc0WS4 zEI?KVb93Wcw|`JS!Ev;#+t9dmiv?+Wa&3!E z%cjf`NgN7%;o9b8s($Bst20P2zdhB61}iLvES}Pky4zD|(ioW6C%5lF!`-p2rDf-Z zJ5nv{);6}RYe0)AY-~t2Y+RSBp+W+-@rrkqS&>^ros>sFt+?2&p-Rpj(e~8tBrr{| z)Yc_kU7oE-QZ6woK3T4+=bNYkOBolhJ85?nB$O(u&B>ruWhKhfTWLzj@lqazk~D2e zZQthyTeMM;fQ8YDvYs9u$1>y{?u*2>rRhAnGTO(=gyfjcw{$@U$|9q6ez>sBc0 ziB-<6Vk420ajW7;N(Et63ZPt=Y}hOXUfV~OECJ;Z$y=-wYn+9$eIPqfu*!`&&Y{da z{5YJla;fdIa*m42f&<$YFIAPrGc7GX(YSsm>|5Eh#VC8WSZUA2jay*PzJA;c>Y)sUIIH1GQ!uiHMusmV{2;X_I0TXn|5vo zmT1%Voi*s?FcARd*p0;~yRlelH$}vejc%!@7%}hm3hZ8<#M?0;;(;yWcgP=2f><^LD{MJ?#vM~GKjhgybvhq`() zmGylmGwnMO$Ex!gR%>7TDWR{|H&8m8(CuYTX4-}+%I!nx0VHM4owrHoO?opaAfqL8 zK8BYCE7*ZCEt>1fwOqtqHP0onj?}O|X6@$53WSF)0BSWk-TJ2Bk1_VwY1(m=Xj*RF9R2wA*z|JqU2;{xglxZ_lR#;rcm(+yww zS^!avyY)Q@eV4v>T)vJWFfZNT-+cFDZh7y4m+8^wk- z!s))?bWW*dxOWHYw<4;y;gFO+0k?*;T{o)GM@H!`OrOCByT3f;bL?#FCG$ZE#1#8Fd-Q|0m{? z`Y9@%i!l>ISsv+YZ%DTt$-w5%_1Db^(?;`%au}#j8$EsM)_o<9pi>=@7jIO*BB=3V z1acz;s}ct_vZ>diVqtx~Df}eQ#PqAYf#ItHgBlqagP1!huu2=$NNo&nZf&qi8`MZ` z418{Fuu2=$NNo&>Zf&qi8`MZ`S}Jl?B3PvjYNYlGuQphv4Qc{a3AYNX@5D@@q&?G? z8tNWS(SkHDz{hkPd@OV&S`EFJvI>v^5y4odSP}K~x2cFyeZAeMV*2gA*r0611~MQv z)V?Qq@Kykj0Rd3so&eyj03ZVbP^DXV+cT}hoyw-}@kInZD2^ap)WK*NdxWIzD%}0l-@UKn4VWwGeMI&Pan#l-X{eW4wrA-#amKBJ*;7glnCMpFaJC~oT; z$VkhluSZyWN4N4-U&4+pQHX$qVHlo#IyO@iXfriFn<3sp8fY^$Fau8tj)jm{03?_} z!WvvNy)pfNd=WSnQxj-0H9m_W-hvotF*Ps&4@Ad0$ZI6TT9|+|G5Y+7MOS>*jOoAh zMnXC&RU!i-fhD+8t#yoq$bbMoBdK+agvfvZsB%vVjy2Q@5NHjxK5HP} z3J_=wwLWVg-U<+C4YjCZPad4wC$E4^`)a?|seK{?0{Cjb)~S6WM+R7e>J(J#efWSp z(1p<)8{#}5Nkip|$bcw(b-%=^dm;k@`09R%Q};v$1n|}U5~uEo3<%(>`z21@6B!Ty z6)ZOh$gj3BW4f;l98*{lXbMYwra-(^Xo04%1obUjo$U8is@QtrHV@LVA_+8)C9nZ( z3E(e7^szE#%=Ja#7z`-~WZY*kOB{nCa%6y|umR`i!T|La28mpg6jD*Ri42ItXE941 ziy<-~fX`x{C%vaOITLA)VdYP}L ziMIj-*7P!8O%rbg2(0O4zM3Z93J_S+%X~FWycHm@rkD9@ns_TfU`;Rc)im)|fWVqw z=BsJqtpI^Fz06nB#9ILZYr4)?)5NO)M2@WKI$uo_Zv_af={jFc6K@3wtm!&mO%rbg z2(0NkUriHl1qiI^I$uo_Zv_af={jFc6K@3wtm!&mO%rbg2(0NkUriHl1qiI^I$uo_ zZv_af>E*tfCSC;~a%4>}_tiA4l1uXYj0P$9UKnqyzvjF0)0D%^;+-CvATLA(sV7bo%h_?a+TEKFj z1rToq2(*9|J_{gT1t4;y1+4H{0P$9UKnqxb>U57x#9ILZYkGyRrir%#1lIHlUriHl z1qiI^6~3A#-U<*{(<^*6O}rH#u%=h|YMOW}KwwR;@YOW&R)D~oUg4{0;;jH6Ck8At zp+1XTQ?=?U2;$a)66l~Xs8Vkj2<$MRgTkOzy@c8%!l2^4VIZ)>fDQ_Sy7z{GzzzdCC=9CK8wLV9 z4CtURumEou2<$My=0VGgo-ib^!Vn#hPPN}WNMMHvHV?TO)oq3(u)_qKM>VS2i_K*R zv0sP@|d3G6Vzc2MoN z0}|L_g6)8o1wCa=0xJyB0p&)Ef!;7KJ0Q=XFsN#87?&N;x?xZlza7wGpp7lq4ruw$ zn~uv4$TKJ%za7x(pq);z9nd16HyxK9kY`XjsOoX{>gPba`~qjvQ4evOp~XP?O^-ez(Q%fTi9HD3lwHO{>Om>{jfa*D?UaL!hZYI*u^~TwvMXjD z_owMHBvK4Y6Ncf%>9QJHPz(y=w;Ebfv~dPo4Xqq{({Wi1c?PB9w;Ebaw9^T;8d^&9 zrsJ{_@(f6amJmH*NMNNybWj+-mCy>K9VXaHXid?Zj>{&IxagP&!BYtc0g;6b~?d!K&y=2bX;~oo5#w*Lv%nowA|jPAAw7XaUljj>`_nGbkOu9nhkroldYF&@!Yq9hV)D zXFxi%{OAco0xKP&gTnajfL15%Fu`^}>yF-ZTy{X7LFxGIfYu`Ibb{@GRv*3Txa@#D zgVOQa0j)^d=>*#WtwDOzaoGWR2BqV-16r4~(+Rc%T8Z?gmmQF2P#C`*&@!c+POu%&!lXAHmmQF2P&$4)pv6i%onSkl zB~8i4qv zLZ%Hg&?stX;nEFM3RDV!kpHWDG9VXByYN~ujAq93Act(4Uw(#u(ld-MYx_ZHR zWC0seV@d^^+^gr>DkGj_z<%+7;36_3a#n#Bi{K`a$Pk`>fO%LuyeAk&Wx$Y;-O zv;)g~9h|t-H4nH^T%)bic@zLh=FYW_lCBC5Dk5_ta|^Wm$UJ104%s#&o3IDj-otI5 zvfbws{ddpVs+57e)Io0TBUcziWO1aDprU~k;CYN1?2f0qOHfR68|PsMx^M{*Q=tsp{Y8$B)-SccARR%HSfhA+nJY z#;LDjcO0pXzV3E>;v6BX5RoPh(yWq|HwrM=B2u?`s9wmb+f=qXj|`}6E%cTBXho_r znNRW4Aruo)sC2E!klm%D)lF!$BCG6dcsImh_;9WF)&Z1S206>`>*$bIo+NA`bUQh6 zn1dKNK7c!HG78~2a~nrAay~*KTTTr+lJj3iWwl*K(tN#~JPA){{rE^;Op@|MUWBR{ zHQ~mCnwaO*#LFNPk^aarDt*L)66hXOC14H=V$?$Rl?2&8&e=bK(Q)8-PkQhuZZ_yi z54E8@R)*S*X9i_C)Q8-zWzT`yYOyn}k z@8xoBytkvPb9f+)LmsJ4WbCMu559uMj@dQh*s_3{3iI%xO0R;8wx12 zG0&TbTpf7>mGT=gE3?bQRfe(&W!l=X$*&CuJx~hr;tANXBZSGlm0RbvwmPFfS+$n)3sOqm!fi7a6qbd83g!I>o&;Z^C|Dt&qW6_*r`s}=%@nWY@;@}1=MCh zlwryF3P40|iM*Yv>K(GlImMr%btLLV?OK8ab#fcm$-8WI1}D|C><1*`5zRrRWk;7o ziw}xeMBW>DA7$_kiP-74Q`B?eT%k293@FD&Phn9%zWM*7A8Ha*?Z~nR53-D-X6i+ll%(dMNAK7F@i8S?tIgTZHxw z?N(C$G&C&bitdX~QCh=889K`eh9|-OJO#M)3A7JXoLi-?7KNZ@CnEJWU?quqhLc5Ep7ld{< zQ!fhb9;SXPv=1}&lF;sD>JLJ@kEuTi?S7{IBD4pX`kT-`!qh*6_EDz(CA0@6m8S{q zA*KwWJ!3GPiQ}8>VVLG!qg$5{gkQ0Li-t0twQ@bQ|&_g1ydbD`z2FH zg!U_@E)v=cOmz$G*G%;a?M0^gh4ve!288xoriO&}JEo2c?Ios83hnnyT`aUeFm+mJ ze`M;6(Eh~KB?H>&yw$QMcQLX?iccW6ik%amsn4 z`wpe-RjadCt;t@sHhWc7RM})}Y4))$%U-pPRp-Ax5PN!DnPV2;ULl&z94a>e87GFluxxy zRsFX&z6?I+y1SRbXWxSNGWht`FIF10glSR!yG<~vk=;krj3aljOj!ITq9AIXnTwTclg0i7*VXToiTC!SD- z+p0%ZQpO-#NU%90CdT9>Icj;%{{^(!tA z$*uabKb}S^hx~XNsT}g-X{53$-@wkxWebcsY?ibDqn2X?6VY#GIjSG}O*T z(6T;*x}|{oq8V9G<$JG@X1$=1*uGtwRf1~Vb?NlzCE?sfJvt`u71gX)g3ssHjtccc zn$T*sCHQ)t|6c5PaCyrO7eZUAEhEqOdp&sa#*y z&(sq_+rZQpgtn2Xr-atX)YC%S#MCoF+sxEggx18=vqEcT>N%lpVd@(~+sf3pgmxjL zdR}PTnEI~JTA2F2(6+PQ4}`XZsUOl-0;j-vW0%l&YP+b^ej>EpO#Mt~dpN`|gtnKd zUkPm=Q@s@|Ff~JHgG`+*v>~R-g*MC~W(w^%Q?rD2f~h$|JIT~M zp`GFo3xswtQ;URl2~(9qJIz$J&@N@FR%mB9>{6j!##EiqE@$5rLc4+~Y*={}Q|Afo z)l97s+H06f3hlK_H3;oWrq&7VDvoc1&|b$>qtIT@)MlYw&3es3djre13hj+dZ4=s? z*mt|o-ptfap}mEv-9o#D_4W$wtxW9~+O_O^P-xe&EG4w-nMw=oZA`TZ?FOc>ug`6r zawGpL5t$w-!ycX}c3-(WixzC{8)!!%)aKt#-q;$Mzq$(-$>SP(_m-qxBH9z}O=#88 zK5WKuE~DOYWT5W^?c|I`k0rDP(Y}PXm{g|7_a{4sdn=rG>}qOgM-g_q5J$i9GdMbJenpXZDl%Gq{ zzgdx4&u~Vgm!S~sSS+y&enmWbdGu9yG7}qfMrhb?b*fiGQEX+=*CY_)wK#{cQ$(+# zM5jlwuV7#P2PyfhJ-c+*Vy~^Uzs$?|w#`aUTo)gGV*>ek6Dq^X1r=2^`j%0OxVi#O zU@IqnExKiL~j-Pg}Ct^MROZ!#!=%}0;17(!~XcneO+7O zzP4RGBjCPYUWwdS!7Gu7-X48#LVs2CeF|B6co5BE3Oa2kN!xT+iRk;IA4o)Rihj^l z&h=eGgVE@n*bT~?$}b$qU`HQJ5PSW`soUO_Oj^!|Z3;ts`)DHiK=eUu0qpAGM|SC>G`KO4rKmrZI|^ERjd!(N9M|g9@c=wGGiO zOQ%hZ60pJZjId=qk4Hb7KwO{0LmU=7uVOTc?S`@TzLa{6VVmpd(CGC*nReQvH%3?I z#FL`vlhLOV(YvBw#8A$y>Pu+!Xg`Zw75K6Z2-{Edjt!@~5pG&Q7b&0mL=)Cu&5h)1 zy4K=8!|)&Hg=c@r%hxF{-#`v(6e75Ri0G+N>QpY|4)r^U=rvJHp3dho_&%z{&WG#0 zP=ts)9r+S9^#8?-g2Vm@a}W;p6C~P3&#j8+&+>mvTG*>|CFl8CCe9Cb z2EBpN{|&KX3%86FZjoI$y_pjfw4Z}wiqP}rzY|k8XwLq)lVxXBwuDTy|wBv1O{n;OcdXhO6Ufsw_#kl%P%)x@Q=cSXRm6 zcx+LuQrEhjGVsm>yxf1>;;orPtU7^&(aOChS%djB7bfP(r5zC4NUFC3oy0`I?8zOmiiPq?KEP0+%aMgzkCE2kIa(F8)UZ= z!>@^}ImUyY7J!MVd@Pt$uVK~0_*ufLt^TaSQm$jA41S%kQm4@0&xX-OF;jx_@!b?P&odOWTO?z?JRZ9&b_J00Yb_%7Y9s;CYY-=i@Tj_o zUCFYmbnW8N%+T9{z1)9nqTHUNPsU!KKsn$CM!W+3W?!#d@WM$YYk>IgB)dz*-WYom zwLol#uH&l4cIZ`H_Sg=6Hy1m$L*LKT4P@pQ&_8b$`bSxIi>qo0S2Xqx;HK%?AT?kS zdndP!+Y+%`V{az=!GO&61Hz!29hn1R(EW|ffiUQ1M&>|xTO_)%NLPC|8sD8OF2<5sLbc0ZNi16H0%{NL>?RYD()JxB%r5T%CSR|Z`{ z$%QkbOUJMnlXo{uqy8ip5T^EVdDRxZ5hr4gvh*_)=L6K5WHzu9{F7XYPf)u;r<^&) z{~ybuRKvj+Voy@$aCFFMt&YW>_Wep!KcJkS8P<<``svP|JNleo@8`yz!LRq&mlIk! zezfb4a<;HZ{c}t`M`ehT;xYtb&}Ey>SY-axgWBEBom9E~l?&0=KB~I(n+d9!0 z=F0gXQeEhyX<5fskTT4T3}T!o%hgpv{|bl0uK2Gr^)CuzwPqp=x}TF{0O5-PDa@O@ zFSz>10&wqvyZ%b!d8og5J|=7RA|9jeX=)rls*TpFSRB*dZ%GXCLQ2)@HHh$~S|jxD zux1HqT0II8K26~FNigicP1bXKs?fjBu}q^_tfohVFAT=d8#oMBLI-818ZU>I9FSU5 z_AnKni3vXsQ;w8Is`#vUydpju!x9+_9=aFtxrh+5d6sOTUBnl#Y#|o!Ig!O!jAg0{ z3$#oj^FLzPON9PYrj}v(n*ox|(_N!nVUn|209`HW%NW9?IaVy8wlbBZL*``X@dk#2 zSyg@;Y>p7FXVC_s|AJF)gm!CHb#*L`SyZGI_gTl{&A>qSkV*_h_)?{krU%Q2|4hS4D{UQI>Z*@^*}mBHqjLKB51C0URR$Ry!iX3!nyV@6W7xoHVUA zMubljKXU%YnwOBK)h>weY2vp*6KCaeq5qS^;6zn3%P=dVszL=_N%2^%h6rCgSc~7n zVcsANjpKO}g|XTQ5xy{#fx%Wee8;cl!nh6}k~o^TjZg>p>CW88zm!9(Y4Mv9S|olm zMmT(Qu9SyEqVcyQl?qz!u0RLLCvc??9#IwXTjTF6h`%F#8>nb6PUFVk?YWX9;I11P z=yqIe6MrvKjA6aJB7O%l+PKvdQclgBPEN8S{((3x8OJ|_VPJRHK!#t0o$6XLBk5Xo zsCbo#-xa@`I=_1`k+rZ5XtEAbx)$eqa0nEM(eoTVpPD*mBAq z|7cvB5XU*R15|wz;twMT{SuuSy2!q}t9|GQme|jZf1L9933T$ivGnLF5PN>s(KRqI z)Lp4U#6K1PbV55T{;00uk zciOv-W6C4qPs-^?{3&7Nv-Z=%h%@z!Fp8MMhsYHi!?VIDX4!Kh^0~+p6zezefsw8H zTf&&gzR%NIi;X;JQOov}^CBk~>RTl0<-7PC6aOB*S#sq6BaA5=`Tq)I8dE>Q8er@; zVVuqEPla(VQ$H8R9HubAFptzOkHudQ#zGdoD2z&`ek+V6OuZzGI;Q?0jFn9NNd{dJ zi~mI!=dlQjV~DLS7XODZE?^Pn2N1Q#5}Gg?q$puvCDN+36J0|`WS)|}?ea@jMKlr7 zwK6;ZBNb?XOytKCm>S?qtXy48;QQttSq_N;bRF`ChjTB6uI+LP+cuLCtM*y07CZ5- z5{be@5hl-xaUwb#J&xK=6pzbKl#I{6!_+h_O8@AXxbXto_RK&RrePP$uW5-XI2-7E zt5B~HH>G=8+tbaNp>#*OZK!YHR5VeFjtf6cT{2y}(*21*1%<+qzV?l{J*GP|Skcti zcXYUam22f%&755lPeA!-a=1Ak$}|(p*3L)rz0<&NVuR z#5pCJp1?#1SI$`V@3VdWm^mV_8-?`=2=UEKzz8Zt^sQX>vjJmH2`ZsnL~mfxe25m5 zXeNoCWzk}YDoeBoiJoUs4MepiS{_8&0ojrhnCTp3YB@gCGqn;Q>X}+Cw8KoDPv%`y z6-!)z-x%@7G2GDX2J@RlgB(7qK;eV(YS!KWW3X~A7joBkb$7$!F)MN|ba6bSrEiWW zHYJ)c$Q(f`TTqOViUcGVV)3%Is*2)oAy2qFScDNfv5Q1CvBVxJqFGjAABk#Xi322p z1foO2SkF!JurL~#Y86HkQ<&(qbDP46?+jB%gt3)HwvSjDJ+@vaxSkCMkmYgQMQe9 zc|8Vt8czDVhX+OC2KnPUaifU-i_^FnY1~qx#VC!7IP9&$=wS+-c0W_^7RDe`w+rJq zQ|}YTDW={pjMGegP#Bjnb*C_1#nj!xcr8;OCNm|&xK9|bW6=Y`;7=Nfk78>JccTx9 zSd`Iy4Co#y(c*-TKVKw1DPptP^V9Hrv_wl#dl}};K921jOkq4d!PMtPYyk&&5&@nn z(F!O)J(t**urG+IFJoU2Q(witAf~>CeL+lpT^RgvBk@gP+`!PkEsUF)`i?N(!PNJJ zaT`+@33&-S@xQ`&AIp9uj1MsN6JgxR)X#)*4^zKDlNg};5Jlow(N5~dUvPadl9m)r zyjYO<4F*%~QpWW=5nIBU`#m!EhZ0R7bFmdH`ZGj-DbWf^w24K3hv*+AS`kFXeVpvS zh4B$d73jivh$&N6)UsGXo-lYVs~{>xb+LlDFnD360E3)yWJ#=`P#BMLxN*XGoT*}A zJi*iiVLZvyBw;+w)D&TSnW<7?Jj>K{VSJOR8Nzs;sk4RgJ*I&72TaWr2LF;Qm?ey# zvTTkp_?KP5JYl@RGHl`5CM}>~5q|bi6TqrI{fUA~xnNsRC5+#&ZjCTrVrq#n{>T*i z-pgen7ohLGf+_U9uVM;)@2iBGvKMXW{EPC@gy{DLhd+BmAP-7MM$QA>$79wO~^oSmK61;o^DVf>vV-z$uN zF|}WqI#UOQ8DT0V%qUZ7VJ4Vr6R~}qLZmX$Fx4Z>$xQWO zqY(o*CbTzkCI+$5h^b*=ma^UnVU{sIz}!F6b3YNVGE>f8(77B9HI;09Ry_RJ9dfUvHLa(z1N>ao5*LI=M; z3T`U68Q&cXZo%e;5uYl(%FzO>OXp>J`iD+o`t`DrBkp$=+?FV~wcuU4R_{z&)^%rk zGQC6AXU(m0>x{*XhLnDCMtch0lPI{h;P&y6$3#s2fHVs3K&if;riy6$Lhf&<=xN(k zG1#wbH6v$K1H-*TT|JpfnmaD9++II|Xw!^x<#Ez^v z#CT7^hY9t)BK9Hr&1)3g56BOcXp;)=60uLP=s}1cD$ypB=({X>1fq|ZXj4e^cNTpL zqEDA-Qz42+So9b~kC$krBr0an6A*pAM4Lu=n8HFB-Bb0#s>4GoC3%*$Jj4*52PVsB)t=xv573MOQJtxc+OnpO`tC{+i>~_(SJTJ^O zEc&i6>zVq#FxN4KrC#&MlB!t253wPUw2Y&>U%e{1er6~9p zqKy5n;NL)qnPLoA%$NtHE;=eqP3XP&wxMp!w9pXTi^n8gB}AUc$I`OE@H5`;8x?W< zEU^}sPsoQ?zzlc!PwKauPO>=U@UG$TYQbYi~~(}c-WCQ;_fHC@~[=e;%v$_W;_BV#FHv9 zQp}=nkf!_`@$S}`m5q>)e{B}5tMB7+|-wp!5 z9nL1vUKTBbsIEjiheT~GS_#pr60Mv>!z?-g67QbiroMD< zZ>D=ND)2MGNDt62IA^6n_5^FOeRR0LJJa5{6&A5i>`#cj0>2=pdVa;Yw4&k=dRYG4 zAP!TJrbJqp7c+u3Ink1}O+P5$*CEVH*$*36jr0j2F5*Nm{9Vo-82(<(6uuzq&^X2# z1H!zL6`-OM|wS%k08-;lj$BHkWB~}P&$T0cA z{;0SnA>K-AZ)dgZg!xXUu>R=_KrK2dZWNI|iu@*VvoPPyx>({g@NGxj${z0&=6l%# zV^)OT)Dhx6>~*^^-_Ks}gIE7R-;faRXRi+k^F!=~<;lFZG_K$k;x6{P8BJ6FAs%48j|lT#_Iwa+uR8;uhuP<2!hC>zK2C8B<8D?V=#wNe@+sLn zRma4m!hDdG9)svu-=GkmWtGnf^JDDudEl12%EXgoJ~xS{g!u{fdRmyDX6l&{g~t{2 z6%jd25q?#mb8|?K>>T@t-#Ujd}{6~my%U^Edd6e^!j+po^&>iUj zfiZwTBMOWGk?u5Q>W2jDtKvt(IKqA|ZZBwfPKdy+ADL@T<)J zhFH|wbIiU(Eb5A<>*9~Z-Yra?vx~nFi(24`yZAe?D0-f~i+>UODPi&yzECF?CCl^p z!U(Y_O`gmbMuo|f`NFs`d8%GmKt}y6f8(y8Imnq934}ops4)k^ zpr_F!M}$ESpfLx+py$k(17XmkWz2yv=m|3BKp6Cr7;_*DdM}JQ5C**j#vBNP-t}UR zu+R%#%n=rPdrNXe81%vxbA*Ln$6}7K&>L9H5f=H}7432&!l3u5*pIN#D^$!87J5^P zIl@9OM=?iO=p88L2n)UNBsn4sddG=5!a}byF-KVF?Iq?23*CUr9ATmNl9(eb^!gEV zgoWNXVvexTi$%;47J8S6Il@A(3`vd%gWeBfj@l!a^_mFh^MEogU^0 z3%$m}9ATlib(kY8^nwm^goWP2VUDoSOE;1u!l3tTm?JFoIt_D#h2EfHj+GRzSc zdN+nS!a}dWFh^MEtrzA93%%UJ9ATmNS(qa%^xBH#h%o3K73K&Fy_UipVWGEAm?JFo z!U=PPh2AS+j}Fg8~mUiU$QAcoYu`JP;`!6nJ1#JSgx$rFe;twgNIwl!+nF<|RJb^rrkJ zKH9{jc!`g;F)3c+qm4|8m-uKalj0>l+P$NAiH~-oC|=^Dy(o&8_-GRf^F*1|v|mH< z5+7~dP`t!PyD=0m@zKT%#Y=p&Q$q0)AMJ-wyu?R48x$|`(LMpiOMJ9JK=BeEeY$6! zD6^Wr#w%XpqtEJ!m-y%_x8fx}`j)MDiI2WmD_-KGFVBjX_~@&$;w3)n#1${`Q8%u5 ziI4hk=7}<^sVi5!#7CXE;w3)n&J{25QHQR0iI2K;#Y=qDsViRMqi$XC5+8N!ikJAP zYgfF)M}0c;M48ppy(?bgqYhs25+8N(ikJAPZ&$p;N8P;QB|hrt6)*8oSFd=9k2-tB zOMKMbD_-KGex7-v%xdcL6)*8or>}U4kGg%uOMKMvD_-KGu3zyIA9enUm-wjrSG>eW z1AyWsJ{kfPFY!^|&pc6PH4Oubm-uKPP`t!PLxJKYJ{k-ZFY(cEpm>Ro1_Z@Rd^98| zUgD!cLGcnF4GW5w_-H&}o+z`Lh6cq;d^9*HUgD$SLGcnF4G@Z#_-Kewyu?R?gyJPW z8YUDk@zFq`c!`gO3dKu&G)6E_lvz!~h2kYX8ZZc!`e&4aG}*G;And;-i5> z@e&^m9g3IuXz)9!2_v}OjBq@)SQ7rS@i?GDmVLeYrTi~)J1EJIQ9Sv-7UMHHniyllFwYp@F; zlD)lsL-PD16vtzW#Snf3ru!KeMB}z2`gCJ&Hxj080az}R668fI*96`;7ia3Fixc(I#d&(^;xxT`FZK$^t^O&c3!$TIWJwDo0l$5%}W<&=B0}h^U}q6dFkS`ymWC^ zUb;9bFI}9Imo84pOBZM4rHj+>(#2VL>Ea~3ba4(|x;O6Hp7w6xli_`DY z#o2f1;^ez@aqeBZIQ1@FoOzcnPP|JO=iQ}?)9%v6S$FB;q`P!+&Rx1VEa~2ba9Sd zx;VuyU7TT;E>5sZ7w6Zdi_`1U#o2Y~;^ew?ac*6@IJGWaoLQGHPOM88=hdZ))9TX2 zS#{~+q`Gu*PF=bC(m7bm`(`x^!_aUAj1xE?t~Smo84E zOBd(SrHj+((#6vhnqKr)(1vz1+QBW_+d=99 zrrbxAi#KJc!Abn&Wzbn&Kvbn&8rbn%{nbn%*jbRSdhFJ%6&$;Usmo{l>1fXKC9fXDfc<$eqFiWQ0_OC`z_^uTe;6G7cUdY z{NP;z>Ecxa>EcZS>EcBK>Eb;C>Ebm4>Hbi;KT__GmHQLr{#3a?Q|`}|`wQj%Qn|lU z?hDHOwQ^rn?r)U)Tjl;vxi2aA_sac)a{s8@KPmUm%KeLS|Ek=-DHksb$o$}40qNpZ z0qNpR0qNpJ0dna*0qNp30qGjbHI*AtZk}@Ul^a!VOu2F8CX`#CT%p`TF-knIF6hAYHr)AYHr(AYHr&AYHr%AYHr$ zAl-A7J5#w8%AKX$*~*=x+_}n~r`-9yMs2$piO!+dRR(l0@9)XMUl>f`qsN86Q>&&6p+)Hn$V}@ zMUUtyO>0^JFs;oCpV0Ca-h02^Ie&uQwctU$=Rtk&LH$JYg82&{)Gyh+@LmKki{6HR z3pD+oT1iyj71du=bOQwWGFyX1H-bI~G3RM>_0#&LkQQj?>Sy%JB%noli+;J2;TDM+ z-)zPd)Cmu$*Vv$58wLs=jIsswx?D=?dJm}A+n}xv1BGo^V+!gf52!cVpxzV)3Y)&h z6x6#spx$DGx+V-1c7kOKDknq#pa;~oHmK{uKwbZef_j?`>V_~-H@>2vZn8n$90ux^ zF$Q&yr~2M*gL+38s9UoKbz3f7!V?})@3KL?I}8*yFlKA$@BPm~z0U@9M;Iu4JkAzW zPMzmJJtg%48`KBGK;g4>wxDt;DLw81b*ByLt}syeNS-aI59d&Qdcp(hUK`YXVW95M z9#l>x>XX@n%BlLM zctCy12KDJMP>*I0>akp^Z<+_x<2IE+jj4`Nc52)|jpuQId3J3SIZGAt;#io)TQ2%R# z`e7I-?8M3zR4%_}^nD&sKej>rBn%YxgN-Su{T@(1vqAkl3>0>yWee(8xl~`u1L_4E z)UU%py*S38G9FOBu|fSd4Ak$&7}QY@sF!R|zYhcThcO1#=K=Lc8`Ph|K>c})L3tO= z{$hjrYZ$1%jWHO1VQsc|-_@nN8fvj&x0NqIq)*q|naftr{#C_Sg8ptPr?CfT4Shk=?h#-Lg~ zpr+cOO2a@+%NmqXmW!dcc|gsuL7f!_>g=pR8q-BA1eC_mtEu z8`SJDP&gHvZ9g?H7f_x_o-yABwIB@C!mL5%)=zmsEwVu^4g*!0H7KL{KQE~o8&qu= zs3lp0%I(W&hsUOt+Mt$&fvU?MR8GT;7u0ea)QT`rE3*b=bzGJ z)cH23HDRDGctt@aZBX@Lpc=9Um7Ae=d8%)%4QgE&sP)-{%E{2L@_^c4gW4DdsxfO& zx%E?CP@8N}o5MggWe+N+*5?J)Y=hbo25M{8pmG~#uJ%;lg*K>dVW3*F29;a&c|mQr zLG1_wwKIEAIaQw*)Giy;?l4e$vIdn~m+&S}_3gDm?F$37e~dw0;{kQR26ZqD6s~y6 za*~&up}*Y&DrJK@90m%vO=SrxH$(S=YPCVNg@MAwSJ{Hf$N{eC>Iwse`zf*omDAXFy9d-!8&r1~C|rb*C8*qN$_uL32Gth^sy};BIoXsK z)G-^>Ko}_8xt3)~<<=#<*He8%HmKn+P{*?dm0R_BL7lKcoeTqYDtk~lRi78s#Wtu* z!a$wQ8dPr8_dZYcU2200+Yw9m^JQsMxmBMR)a5p)E5b_ZRoR2esrtO2UTuSVO&F-x zjxne^Jk@ul4eF{eP_N4xRBkrq1!eCYHp2D}(-n?mYExcN_TFJ5Z0|5#7?~}ooYp+= z_Eev}ci0HqJ50AoW((@NT-K)^@qoJCwyC#;+0+eV4C><^P&eA3ZVCf+bM~Ne>JmQT z0dg{2m-jOw^+$MQmP`BEk-Wdk!w(LRWG|BUVviA-fVS9(^^3!Y$J*S0OFR0t? zl6r4gNxd(7P&wJuCp|WGhYjleVW2*cHK^Qd$_wg)HmDDUfx0t$P&wI@7t~!gsJp{J z-IFz_+@>yGP#?BI-5Un#zN|szHXwh+V^jCrpdJVV^^vSW|NGI*e+|j-Zc0TW-eqls?Xso|mR~_o_AYB9Y?n3N@th^7+zkDz9z*|( zZBvhh+0^4%gUZd&y`Vm8gZf+;s3)=qm6J_*L4Do^^@T7{Pi74&w_(N$>M0x47sEh3 z{fdJ6k`3yaFi>C49#k${zqMyQhW-^B)K|kmJ)1Qs84fwKgan@#=71L_|(sDFlm!XqGAg38UN zyrBMVfikraQ1l*2mY{O8DGw;qutAw&pzt(GmY{O$JYR5EpP6Ta$`1n-eMLdVY*6tq zP>EL*RDlgjgn=r|9#l^2Q@`_6Uy%)JTo|bFS%b>W(7m9FZBQj)pzwT8mWG~NKjj5A z(FQds4AkVTLFqaD#Cpk7eN${uQ^P=&W)G?>m!DXF^njXXgPI-&sw`_z=2`zasIzTQ z=Y)a6%S~C@RBpq}-#jICt_^Bt7$`gs6T+qqBgS!D|2) znip15^Rot(+t~MaPxURZK`jgewJ3W~Ih}3K^MG1xgQ^SzRh2!coNkuL_kgOlLDhtT z!V^+sX;bTFQU!$7SVV^B*yCAHE9wJHqM>Q@xhc{Zr?!$7SW zV^GUHC3S%fDj5c<{uKq)V1rs425Q|HgR1kC)Os7#hA>bYUr|tvHmFTupf-;&sO6rL zYO+B!hk@Giih|l|gSs#b)V47OwZcs6T+qq9qSY`>z?8~M48a<%; zZJRn4W>W*%gUZRKHhDk|+MtHQKn-UP>O?Lj^;Qq4lQyVRVW2L4ML}I+gE}1s>e4X= zb*-nQ&e)(X3j=leD+=lg8`P`9K)rg5L0#u5sn^(`UKW!}`s5jZ5-W&$%En^JoZJv_4#s>A)Fi_XNqM)v`L0umP>TP2T>IP3q z-C%>dF$~mAuPCUSZBVy_fqMHGgSydEQtz-q-5Lf8ZyIMib;)T!_FQjo-e!Y(R~RTf zo;;?YZuXSadu&j*hk?Sw&0`Ac77wWR*`V$S1NHtf2IV>OYkt56^}#Su9~xs&@9>n= zoi?bu!a&_U#-MKXfV#&9_2Dp3_l_~BcX~kGXM?&w3>01iA5%lW%>(KqHmHw=fqHO^ zLA}cZ>LDA{!(pI4HpZad?E&?O4eH}zpgu9ipx)yF^+_Alr@}yedW=DNj***>+MqrY z2I{df2IV=PY1;Rrn_>5()2sDk+WPMFRG)o6x*2vqx|#j`=w?o{gu6VTp0um)sj%w% z;ux2d=OC;3v<>P@VW6HFV^E$~RLn2ipuQ3Y>Z@Z6>cgJud)5Z^wJ=c6jWMWuJ)rEJ z`)1hAeKY%=`?(qVeI8Ku&V4g%=f0W!&i&j#-R}Wq@7y=TcJ7o+ZK-oL@&9I&OX7)Sxa|89D2b8^Y-wfNi zZ)U%9KQ~Yhc|h4a_sy`K`)2k#_j3dFum_aAbKeZxxo>8_b3ZpwAM=2+ckY{EJNM1( zckbr~>Jbkpd*{9xwsYUie&>E}pgfm2nD)+nGi>L+nf=cF+(3D50Wj^I`)1hAeKY%= z`{qA$`8M-uPxbxFo+bP{WR?)ovYsX6_7TzpDxzDUB1RY}Giy+}mDHo|l8QuZPAFi`QVLFHCbpYfDb!Uk0k21;ZNDz}pIf-1B@6@`Hsmo=!|O6oCB zNsYHb6^DT;$r@B{CFKP*!3H%k4Ai8oLFHCbk9$gLvJGlV7^taPgUYR>yr4>LP}4>S zrAMYm%GBG$m3S1G-ayWq|8V3SdQ#YMy&ybWW>~O7q&#vi{PoDpNQGL6SckWT>D}V! z{OJoHj?51ZP7e@6MFl5{-i)R+qmkKojoy$iF2@as$3rk4DJ+OAR4KUORR_oKfyXb} zM;0NHnnJ~&IWHJk zP?XD1?EJvAit_x(nh{X~Wdl7Dog>P%k#!@Y1jqFj$ku~Dv<8Q&Zn<(B^-%B{gs zw)_WCZjbCx8FvhG0St3raGWCzb0_6o8s;vyVeW)s?vmxOf0PssXPd$SJB5Sp6b>MT zgEED5aIv%pCos~)WCE6nAzD~%W)#p}!Euf(7HJT&SUTLGVH%MRnZiYpqj-v(o;tq} zFPTT+#^z5iTl8>bFgS_%tYbH}SfodF39(2oC~B;+NFNe2RfF!9St>N4I36nF;YnE= z8YOEdgVPBEZwa>0 z>wnMn-vkwu4<=;E_!dv^)pLLe~o-g^s#UIGan5<1dD2a#T-22n&n5KioLlp;t% z7f`Vw3L>H+Al6S26%-T@`QFU6nZ380)kA6f)7;+ung5%aH}AbEJ39;C!aTOLlxH3j z1{5bGc0w{IBw+UREMB)4@IsiX+lsK2xB;!jg$5dsw`Mk9&1~+Pc@0RY2h?F**!lox zELXn3j<8K;Gh~j(!XR@?uf;OA^g82<-i*Nsy$%T(Zw`AI8B}b;`&+5k266_j`5kzf z&1jx1Lq-wX!gk>jrSkYk5o9@1scm6<%vEY{*sC6mGy#P&l{(9A3)}w|44Afuy}`b+ z!h}XY!9Ix+sWbF)ddyr2I~evRBJgduz(XML?Y}ATy|BZGzz^I4KLmjv{7r$!!anj? zpMTU?AC4X;@ z{1Qq&XO6r9C7(A(-iVTaHb>rsk}sGeW3hZ&*stcuFQYkMGDqHml7BZx-ing1m?OV} zlCPN~Z$rt~&5<)u@(pw3OpF|^m?LjT$)V=RJ5X}CIr2`FtePY5LdkY>BH%ERICC8W}??cJ4=E(a|axQb^11LGSIr3{LnVKWNj*|14Bfo)?3z#Dx zM9GEBk>5ngMa+@kLdnI5tiCCriELCK}ek>5qhWz3Neq2zMr$nT-#3g*a%QF0}7 z6?5bdP;xbMCA@vWk*dnj_m#@@jKrJ4#+_j_g3m z>&=lPQSwXX$WbVHqd9Uml)Tv-IT|HzF-Ojhl3y`LcB14AbL1G5yxkl*2TI;)jvR}U zcbg;UM9F*2k#nKsedfqr_7N{ zpyV^=$R$zoS##u4DETXM3R&G6yd5`yfQd;v&xlAu=Z}@_Y~?bKxR? z4nkxcF7iSUB6H&+e+@!p9$e(5AVgAJ5`@TnxX5ckh|G_RydH$e0=UQ< zL5M7fiVRnR5LpNp85)Gh!nnxrAVe0yMXEuFEQ*V?2O+W;E;2F*k;QS5*@6&R0vDM* z2$3amkugDtEQO1V4MJpTTx6~wM3%ut<_wtF2ts5HTx6vn zMApPbRtZ96JT9_Y5F%^gB5MR8vNkRM7G04rUfCgJuY%!5F$I^A_oT{G6feoGzgKYxX9r_i0p`qygvw$ zop6y41R=6BE^>4bBD>%s#|9y?D=u<;5F)$bA}0nRvO6wvau6bW;3B66A@V+4)L=M75J`se-!MMm}L5LiJi+nN&kwbBjPX!@z7%uXeAVdzwMLrjV z$Pu{67lIIZKQ3}*5F$t7B3B0?@&R1r+8{)Z!bPqRLgZ*%VqE08AVe;~MV=2r3R2$9Qhk-r8Z(uIq>6okkpago0VA#yn`@=6dQpTb363qs`6xX9~4hmiLge$f$nYRUzJQBVgAlm_7is_JB1yG~m7e2p{VyKa7O`4; zWN<0$y$Ga6#2SRWPD^f#lH()RBjlH~-@lTdPfl)PO_PDaTM&|>e@l3SqUhG@>awd9s4xe=Q4UM;y5 zN^XqiyiZGRjgp(7CBLpEw?)Z`DEXk4+zur-L&1l-va^_77TeKa|`RCI6@;r=jF-DETKX zc>qf8j<)kJTJm6&+yf$mr?TLXt8^0$yZVGVl?O8TJklNyaXlp)sPi} zlAl1y{k7y;D0wML9-t*7Yk}7Y8DqYKNS4U=q?JxKGS`tz2b=buN2j`O9BtN8e zzalRi3H_7gR!K-xRUIX+Wr%KroBH~G)EGu8K`g1+x9s6uRDTzOTO$GA$6kQ*c~2?6s`)#XG{Ro4x8$*A`?fD=`9 zh46;P(Y$W#m9lwBg!+Mc1gu&m`PHMOI&X#nm^wf7)%R24;Po9O*Y_j6`o=o53pE~Z zRO1u>QjNz;HU7j`<4-*`9)#8SGhdA#fEqLVZ0@e{=i#A3g(e$S=#*5UGu|eYmnS9* zw$>ag$rrwoY=MSi?}d#A$M_QdzJ|YV;qQC+^BUecq#@4lSI=jvzrbrwNiI^Hl=2x* zMP@vue8!?Ro^X{^RMmy5dR|q3ldWipPp758iY{=S<^(Ic=+S9BR+CG*HTfNCa79y- zYyVA6TvAQ`^ws3LQBD5RtBH-2&9sHcHL->LH#K=)tcfk$TN7J^K}~F`wSyN!@SDnQ6uFz={GEL3WTLwqk(6+pv|AND#1<^coz& zyG~na9cvT9ZVcIE6nCYr)8Al0cb%Jj4hCJPtqj)-be*=c9tXp^PFp!&eLF+f%{r0_ zTWysgN)+&$m1jT@Lo%FEV3D4IfUO!b^2y+3aF1~-VEV1@%TFFy*=qXpgWPL*%~spj0K>VaP+abGJ7zLv~=4K$9mdkb&FkdYocYsLpGwpOC5-gRczS5;fTs=z|p z;}-I+U?I)0f^_f|L}P%dlK4)z_%8+Vr~!8NiJ#>en00mgQ&(|d7DK*u7SXM#DvZp0 zM)56T6tZ)CE0nD(R`qVavT3T`L#ldDyy`y*;?b)2(i7iD65kIO|9e*A`}@Re2AZ}3 zU=D-8frWvlZHSJa-{gVjbzW*VU4en7Z7BB-7--std15X$(6kM=jc`vc!y7;+ZHI~Y z|DXmVx7x!)Wop%c5%7R;7^zEIk~XSKiB<|Ih2i?8@~d)Lb%h)W zIUDk|uV3FxY;5%GT`1AceZ$zq*EY)CU*CX%z1WlEy*umLS?_*>91a+Kdl}lnI?Mum ztZ#@-GnDtv2AX@v41Aof*vWCl5%R7Q$zx*=2yie9u&v;+u@1z>l`J+Yg<S`GC^UMs(`+P+mYl*H2{o}jyVGD`7-;a>oi+7MPV({WMxDk~ zpK)fF3dud!)0u2WI}`4-TLK-|>8xY2U`}Uw{gm4RT-@nwub*71vD4W^KP3zt{f_H& z_RvqcLr&RHKjk(#4=LG|@`}?t z?ttVGwq4A(l*-^+yP0n>!^iw%kJmr!5hR+qk@~aWKQy)(Yh*%!wi#>M1Y(UstQ3r6 z4f|{NXlb#u#G~Xia!_9C2(jIA8g&ekedRP5uG^$i=QNo5+Y)(9*~dR$lS{&8*7#bx zjg7Iq)s==)xeTkzbD7IOH;Q@X;xh@OyaacNHOfL7{KZPqL?`6MWf}7128}Zv^WuyQ zmW}Q-!_YXV{_2`dYWp~&frixfaYkOi$^bV}{E;Zm*-pRBUx(B^<<$N3Qy*mYlSYKO zopJifHPsuXpOOjIM26f>xY?#>s^DY38Od8{CnAq?b2}^Q3!5s|Kesc#eoCnoavPcK zL0>eElk63GKU*jGV-pq_F~Cen^3OcZy85{v63dy#sEhNDn)C4Lcn5|oceefzYdf52 zJCbQT>MJGXi`GIq-{SN!o#_$prTx{|Cl)TRGr?pv@*1_WG!oA1G?=RRN5XlX6tebK z}l`j=&K|KGP$Pe5OYn`Am;E@;S|pIPy77jX3gYM;xJH zox;+>2C1&_jPN(Y-%?!>(;^l|EcT5+dcj?RutCxYM7&=M(+-#qxNo_wxS@0jn0BzK zzzy;`I>GQw6B1zbL6lgsOUbFMS8|2qQes28DRCh^mAKHimE57fD{)~(l-yw#mAG(+ zk|%twLc?EH@+&er9yAKKo$wFUt2LrY&BS+VQrlt>!ciQQ2+C&#D z=xnX)f^6Z>-#-*|cGOL2JIiC#*ZlK4nN?q(#YYlS7G@_j1*K@|>D_&y{`G)RIbbKppI=&S)9p4I@i*JRs@hwCt3UjLJ zu$zasOq@~dL7uu)to zq?GXb6-bS+6XsWB0m*Mym|rP1iOn9u{7NZC3fe>6eiiaK;#c-CuV00H;#mx2w~0`{ zDs9%U(nY^2ZQ8F&OZLnC3dZ_jnRYeP?(mKD%Sfqw^AX>_m&Ioc_9)Gapg?kfZ zNG-R)Lx-@@XGN7HEAy|?#E7O{Im=ZVX|18M(YQ+*NL4oSG=IRaEESRme2)poqMeZ5 zG_i_l6Rz_2Ot^|^6Ru*~gsYe~;VPz0xQaOwt`ca%?~#+_v}D5MG;YG~n?99DQCNU} zOR3^DT}U2b&&f^q5SVT*kLlLJVs)JF*1l$A!boZ7z#??#fKr!d>E3gMZA`G|_KDvL zTfo>B)jE9diJgk#y^|SxKGeq89#!{VZ-vB>5~Q?GIpx?k)zXr3G;?Oy;|z0V_+Qvs zqcrkqsx)XSKi5<)&{P4prbr!3Qw6c5FYH6;IAnBRS^YtHd<_jnU=kpoZ8?{t>5cAOL;S|e}d)j zD_a+59-(aP-`Q??Z8zFgvSpU)4E((hf1aHZ_8Lh0^8KRG&M2|i-JG>_=ZESEIb|c= zl=2j{o6+V6|LR~jX|aq|;&WC3_iWN0kB)k=Ds(ppYjPF38*GlXHG+1i?bN8JyR(6A zrR5oXcZ2P*w%2{_+g)nk1zX^jRyid>fxT|ZkIFUWFQ3D)J#R`qU568ITJH)Nciw;- zU*gSjnELq~6ZW`4Z`_IWP&$)OlrH2Cr7KMMx+z~N-MO=}>0Ui>)&%CP&|BxX*I~}8 z`~}0(x`2f#=U`Y`4={G~`BTh+>w6tIq^o;aszA$n9k?NUZ7dpAPiGlj9owdIM^EIR zNivHqwVHAFo|4OX+}-CWEf7a>&-m;O#r%31_UhU?^>WtMFP%Rc^pc9^@nd^{hI$*_ zB=k$`9q3T*mD$h9z*l*ZM@(8D{+0C1@((8O`-c}ZCD|TVJ5TMXS@7?nAN(r z>sg543l2G8vj|aol1G$YN(rU6GFovT-%=Q?Yc*J5Ti#_n4p!LC-DN1BV;0x`Z&_S_ zvla)pEBp%TZ@Po&FEy*y;yRhMxU|1zacSl(E=?+$uEh;7XK@39vbce!EpFgVx48ab zacN+21Hj@2`UWY?;yU{*u8Wbyb@f`DVuQ^;Y`nFQ$2c}R>ER3aLnL*3hZ;SFj=Hyw zHHels)Le%;RLTrqdZCa?q&{in^Gg`N-5`y0{nFp3aMyIOXDyW>Fy?hX>c?EN5h$n+ zS5QT8$-Zs{k%gE`_VX#|6S&g=3Q~IeJApL#I#8_Q2xn#e=;IFmL)^h^Anyx?^G_H$ z`~7o-vzNXI?M;CZrk#0&q*ZSd22|jFqb(mWTJ&`|qf9jT{my3kRq>CY?w5+j8~g@r zxr>n+93Cdo+hB(__z3cb;(quN8XU+G_R+k-|AGb|F!~~y5Of>R{Nv0GuPAaokK?4N~nqoph zCrl6@l1wCk_plLn@&2h(6CBhd|{f#SqX|It&>hM>Z|=lpMvz4Y-sk7W_fdJV1E}(BzF(8CPA}ICJU4)hg?;)sS#j zrhT(}YokX2&c@<>5BoOQGno;w&YO~zSX8~U2_Im47P?sK^BEB@c~i52s@E)>P5FHu zAtlJ&=u5dh)4r4ILz158EC7QPFJ~8*zS+xhYY#}y!kPBHnf3#j_BXthXvTMsdWr5z zY%xP@?kp_i=qA1*5~cDbIg84vq4pWNsgwEb0HIKjdb^lfox^I=FrYRqv`Plm?G%Yp zp<428N6u!qnA)99pwe0)+3XdGQZ}uf#RKZTPd9ZNB=rH^)NK*HzOI|P9g_N>ZtC`Y z3$m=9w{%l?K$Q88Zt4{NFsm&4kZ$T!q$G!RQ+MRyOP2kCZt6}*>Z7`;J0m4IrklD8 zqVMCnskb7329N!*%~^{isaZWx=UECrj4p-CPt!rxsk&vf z@%g9sYzF%WdOK0YZOb5Vn1R5Ih_hUs37)6m>__#Uf@6=J+baq6?rro?IlHfNjL+?t zNEH2Lc&Pz;8?=;13wCN}kL}ryQ@ilko`X8PkL^iX=MvD1Qc-_R|>=--^^PI5iv1#;IS@Yyvf!Mr)}5bL&1k&CZj5O|uKh zoz&?|zClo8KZ8|I`!`^mi-qGIoc)Y8gYzBm2{AN=Xa60I5wg!gbNI3s9`^)+2K#=6 zUGR|5;Q6Vfsm4>!8tBnFrop4YC_JJWb?jYlKfA+DU< zG&dLiGtDgs&qMQgl_S}BnzM?2EfTpvN+}n3fl@(WUYb`&puw#|5QunqnzOfl8N?8q zW)$bZI(}s8<#$38^3i;}(7)1rLZS21{5}%rYQ8^mrLPLkWv^t z(IJ#`+1TW<>ntH{lYr1goDTl$H?cSCW?W)lW9z!3K|U zNhUnl=mw8i*uh4R`Uwx6ItM#j=+|mTM#L{=w>oTPGaU~26Sg2YhZsHmCI;If2K$j5 z&a%54Z~|ebqXeH5U)0HLgxSnSWR+PNe`dewWH!odW}~votb#wY%Q~5jGrIpLs&Sk_ z0Oe||;?L|4oy;bg&1_Ounbq)Tb`=6=Z8-G|x;;3AjLo+FGYJU3P8&bD3}ALNC0v~T zf99u;IpR~ghJ$g{PU#BE#*R8ET~)Z$OX@Yi6L#8vz2~f*#sm&DKoNGif?y?ca#uAW@M=p`M9JRrj;_o zv{Gi6R0?Ynqw#r0#Gf8p7n^;S;U3zIh`%6yv<5E>)aYyjd-pg=TdkACkl9AlyF;0d z_S}tAFrq=_w&@pA|BkY!kR7qS2I-rZuaKQFqQO}-;#mx!2LlT}s8^kIgU6*k)#(~o zs&u0PfUi2;F`~gdPOc94ioVJW>ZAX3yQe<)VZ}07DDl;&7e?%(Ur4Dw=|)laV1`QA z0B=}ADO!pT?)uPD!r-nnE$trMxp$#Kx-zs3PuGu@5z>{VAcUQ1EH4DbkcSNB`7Gvx z#B!7$k?csL{$;Spg!0sXO0s)q5HNUW(hZ(e6voXgr9tFQ%uqvEKyk12z}am6usPQ# zWILHW?mWTpe>klqw0vb+*`H3#{gJF&z6!0vCEib~2okH(s&0wi zWrx5CQw({;bjv?t*d`gOO{eAO{jHXtXPAq&<>wiNOsVDPWzq5u*76U)-)K?yk7m*G zQLHO;7G_2R{S4-x-2tb3O9QUQ3{HVz zvC^N-V+O-ln-u2eI}K*W5ayzNRer!*9?X7YHC)~F6 z*JP3DIxjL^=Y?6+*$H)i5E@yS;l_}~{JteVBajZ(ft32EO!3LtOg3LiXLDRN2bR?` z(^)OcDyxV6S><$xt#}>W=nX7h10tg@bIp9T7L|+O#%LH=ouP(k0LYe>$<9o-%SB zcZXGn*5MKt&^m&|y0ornH?Ue7u#^=;o^p23@3y55>nVfH{x%5tam?`-K?k%{EdA3) zYrqil^Z2}Ak=G0A(R#c#i)lTfHuY(Ju{M4?e#W4sz$4v`Z(r*6f+Y70+B-+i@4FcX zWe)S4{q1-n#W%4PtMaVDf`vnhkq_4&dhKx1>}^=Z7_`y))->Q zN@q{~CI-LB@78Z3P2{y)MH7WuHlxk_dgIz?PMh;|YiM&JT@p?5rGvq#-#b9IUTjsU=n!ZGncCDClm9 zmb4|W<%_hXP|H@dl~2R`sPKf=v^7t+fwmUXwV`eN>BMrbHr!>$+qNxj%O!52Z3T(# zXuGWSyV@v_NS40ZARw?fUf8XL_7slShQamAw7pQ44zz<@7RT1Wso)x;fwuc@P6|!o z(znqRL3%1p#dWvFAoO}BZ5?SxE-{mK6eM<{aEiCL_Z3@Xjo}{h47DiqOKfFyhjz5G z)~G|1dV#eD$NccfyT`Y>s}}cX2eGy@?ab@)D(x)Pr3>wX*JY!@;GJjmnm?nGW%-*k z9B)K~i|W{7u;HH%fTiVSc=M5aP5BM+A#k$ADAr7XG__nVT+v<#wIx(H*+-BqrQgd!I*z3Tx{GMOS;6k?X@=znn zS7Fe*)9zlaceD}62`ve!AvmS?KbL(-MZ^eyK~)rM!O5T>p^?qy4&qE+H#PgR&>Yw`{;dK z>gV)6L26G5uLJPB9*i%1VKIM?QCM`BxfkulrJts~1nIqLZ=duHQaIUTFnAO1*2a)M zSqvEu-9lgz}*A`=|C?1TRKpXK8OzTN#Edp$#0uuB;gHs{TWm zI~~7-k_@#vP(EalN3z|0Mr(DjKg@Aa?0xqcIlL5n_8ASWgzXkFWS>!ccsF0MWa9f8 z;2{OaNA3zaJ{C*3-{6K6JcTYyIQARe)@$qQMfL~edqk&)K45fUsid3(1_r}>=*#XN zTA1n{;5U7|Q(ad5k9CT1(CCC4sTcU<`+*NCsI|cL;G|4xVep9Ic#;R< z;dD3)0Fi_a7XrWtIsy*>M~r$YcUZrl-p?h5(EA06Bk4%LM4s~l^Z}kOj6NWw8%0OC z(|K<&99ix%%K%~RH2m|q=uO4xZ*H0;V^$~-? zuV(@_mX75`j-q3QB9EivG)0a^i~N#)L8RI1kr?9APpT=i!A3IZaTDAzdOM~#fvZEBP0WG*o$oh(S4LZ@gnhBWd~qvJ>= zg&j58xZp0wR63QHBaTiL%JCq5&{vKP&O**Sa_#hQ#$;6|2A#nbl9$d96f%>}^cx+IMziQFo-RL~C8V28XZzEMP4S_#x_*ry_xkSK(`h=F zT9Bp-Qs>Y)eyKe7hv-8*U19o=kZvxW>rW@4iW;FAgAlJ~~Tw%!$j%8s74c#pF<1W$7Y8 z;^Xvjp9WyBulVxn7;@ZTDC&+3*k--s2Der`d(juu#k?%#>0+TQOXw1zESi9M++g)W zKS~`pdP4=YU1UXh&dANZZNXc4dm1Y?-XFEr8`ESI1M^< zmb!@~JBBRP?{r`}tQor%411F!Yr_I23?Yz>z%k@gqiHR>+sg#h@d&`&`!l1NxpZ&# zQ=^?OY}*~ns-8D1WQXfX(^-9Hv~=Ums)0AFz~jlt=ccndX(p>io~$Ah0|)D;OlS4E znXH;XR(ufg6n%<2PjmW|;5<*$r+v=8LGvO7a@t^{JqxOSr#WqK^DQ!2PO1M^zsMGH zN`oEM?0j(Tiyxr8-E}=c4$r5J0>5OXr_3n1m00dGS-fG_ueCEq0euH=xWG!DG3x0~ z$ptZZK2WOUX=i_3#n}#Ks7e0YXY$^nvqr&E8i<`WSZ!vjHj(Z8w|83TW%rHI)>bLI zZwyAMJiAnXcCDB#$!jsO;#!RA*|-wfiQPr=-D4B)`h-KM>cVax`R?&Jz0Yx=H+jCt zwtzfCpWz(vwSIzkPM}r&O>Ivz7 zuXv{sx=pC%TDq3!*PpHx@>@sO3Hdpto5DXD+@gc*e0#Ps)OO&X0ox4E8;tAaZHDI! z?g?|>9K?Lnz0I(Ld!)LauIIHGLe~qmd6B;8H#J`Cm*`78-7xx+kZuFr;7=!-*99ZD zaWCF%q#L=!5p<&3r3INO0IFi*;PNfgKMO^ zb-bBw<~1EjHw!g=nZE4TozF?d_aTvs2JI==^P*9Q2lb2`C7sIzlJy^fk=`H(DGlBv zE%gi+4LTwgC_1rO!5H`(CtAvH1_K-$46eJd!8O|g9XZB3;MzjBaD7goTLgV>rCUYI z@ec+r8LirQ_gO}c^Gbh(zQUzXqOSVziQg~ul@t)ziQg~uV&%=J-vo&8{{>u-E=pv^<27J zsP!JYN36BqaIYC{McJ02!ojPN6_F0(PowkDC71ovV3f&i=25rJ2sa-8bY=s4_uhD1 z;Jt6g-a6@jQwIq=)k^IPgF*M(DgEgb&6XT~l8)xMvlt~rN(J{iZJqdlKs*{NMhVrP zTF2i?DIc8{qlEFLHE;1j7MS;5x|cW0V|1_3EU(g6z2|SFgY+OT{Rw(dDE*uCO}X^Q z#wMkPQP1Hny$#NF^y|Nd(Pj?0^f6?Peno}izeV5T#s8GPB^3W{`nFvB$ddtK9*S>p zLX)TXEEI6@Y0{6?+B%Tm%ghhec+vPrKSnxpB77B)3owy zI7gY%{ULgYm;MYrB$WO=`ktorfsBRLo%J3Mo;$%x<5=0^U|NC zhlSF=Pv6&+{;NRCiO*X1k>7}=k2kIRnkIGs0sVlN{yX}CQ2HbEh+O)>Q=np$c!S+9 zHn-iwaTLD0PfhdR>}5g^*hRP(YiwO&L<^ zHy0nhUV`xqoE+pIy#hrZy|O;`1UBXLFY0yrsZi9<=x4mBzSkB<5&ljEnDomxbCsr997O`Rt^&850L$PJ zvqSu`jL3@4LgAuqHFb8;^;Ukzz`YL-#?`S=A?_INUkHW86gYB&;%&2T^>?%LF ztt1+3=u=O5cbh^ocJioqy5i3E6g|bW%}!4V*`B7Sg={_VuJ)|_z9zOzGlQJjnLYtG zMwDh|@BTnagE5$Ra~@LaAMzosYe33m-FEeCu{cA|aE-*!GlE9GpkHu}M8)opip`9Q zla*lb6r>bnn#GX$`uY3zBSSHZ2`%NGSe~V4dAah?vqHJPq+iM{6_pPRL|&j%nj6K; z31U^68}%&y@-;`w_Z9t$m#+Z*N+{pg^lMG|-0$cM3@1tdD4Zl2hZ7bNih4$M{M4{m z?`vYA)`I(Im-gH$Ne1WIvVa56*?QhKD=II^slOf2b_fp|Nv4B_bX2(~XnaGz;W{r) zzY%o)E&Z13TwMsg6}N_5(v~14+2AMxAzmaSixS__?|632eo|D*pCy`zk81zHLg zEey_Dz=K7LtOCC;wzV+YOCtq~7Dnfyi3?gv3&W=)eRUL9*@0s)p%T~oA*I1%7*j>N zY7s*gn28!K#2w|fC%vm_;vxPqN-OC^ettf_IsocY*nOa~Pob^({c*9gU~hNOu7I_b z#uY43VQ+V6Cm9k;1qbc~$Z9XGT(MN2^HiE+{(L3uAmz>8Qn3_~nj){{dDg>@ZPl!Y zaV3@A6~#_bg!M4?vjY5N=Nx)|mW7|}Btp;6B=}j||1%YS*7N@y4nG_De~yHoiT3N>#V0vE2^C$X~nCCEW34f+P^VB2g&qC^7=r5YoQVAb7 z(!BrGGmmRu7GsCgpg=1Z=mnnVNP0oY^CG<{<~iD1!e8mHJoQ-mtC0FP`kN-TRKmrE zH}QNzMs`n!<&5Bi5DwN%0-MqQs@ zhf4xlnZG9};R?ON^L&tA5%RoBuZnq2_m=P)y~b0|q}PPhf6_lSsihJ=Va^VpkOC0| zE_*usx%GIRUg!DFrq_jh|Du11`GOwj?vHvTGituHkyTl0Fu0L+N;?Kn>+v6Ow2bP)zfm_`?13$Dzl<**Ku zbG(RQ@Vx7wyrm%5sCvp2B!}Ia*IUqPq zzDe?<0Et57Zvy$TQ7^lvMm|kGExt>|*HYO)N;aOuR`yNGAsUcqG=~gk1F&W!K1r=S zW3YWf(Bw1HE4;idnjP}W&daf#eUr-J1jLD!V;7>yXQf`xD?bKg#Blk0*f&Xj4nT6C z^5MV-(BuJ)CZ9t!84FTkc@D3$Z&D690m+Hx@Fr4&=g}JE0vWlu{I}URNq!t4aj1NV zD*=P?7bII_gK-uOa)XTAT>fG9O_HAnkUXM%_xJ^ij4OG z*Bl@W&ygP{R8|^2j?M1xu-xDPpUCr0Ra)R&X|UR@o?=8{VRNO?xfy)VlTL-k7>)p7 zeK_!BWT?_qT^7G(1yzEBZ=gomA1=X8mIRWf`$Sh~@*(r9IY-{?YXzsl&bE53w; zt&XoU+MelY&~RRR>F7>nm9vTY${U`BCf7ZNtkae2zPqhcdHrLM-RozLz*Co@5=Kvi zGo!RcLESHCR=-!lLA<(!v0Lf`p7>eB{Pe93N=(evVx`c@h3E<5P!byuRXJRii6 zd_2A!XWyjwk{^)#Xngs^s&!q~YDI1ct}~<7 zs8hOX6$`%3K&yNwvf+(Fq03umTC3|!Yjv$tKPVb#b$!-aMPliCQ(8Ua9<_=pTyMHQ z>x{O2`=i?$G`bal2v&ecx3lb<6x|8}QV@-9UxPou13hpuo5L49Uy|f|N2-NDMjmEz_2m3@=SQ5ulaXgPjE>iIG%zYNGI z!{uLQ-z52E0f7k;91a)dTm5#o(C>)+E$Ga!9LOlgCk5DUZsB*C7SYv9}s_ z^uG4oiq5esKwcGiIsRndq;gaQq#|05>qtFck^ItYkCi}1B`*I4`zFb+3`k{6el`N~ z1LxS=P)$|=DOFew+1OfL6)A_RfK)|ufVo6~#b=;3s0K2sartZotC}RgIv~|i`RtiP z?ai}H$&eH6GaUTryjCikBqU0;HBG z8P=pR$vd=?9piOpv^xzQnl&jl;@oL45BBU?G`qsR(_rYE%_;UGJDvI~+}UE8%A#1G4PSh3 z8Fw_61x(f-x=E9hod!c3_t+Vo+U?4EUW<&KcV#uN^(-*efrhKY8*dwIX+;!crkyOW}*d z*e~x}-x)(5)wdM=b&cIww?8t--)*w}>p>gW*hyhBYR9Xe*S+XJZ^Y}x<|U1! zdNl^5F|U`f<<=7po4~&{;XF1&Xd>~N0@75=^Oa*Czs>8NXL!qz2%JPNkIf4bC3(#N zX(q_?Y&PY6ZFBgy=A6gI`^_a@5+F%hp06DH(Q+gMCz;D*#Ud2IaMT9VfWkT$YBwzra(qb>YfTh3$S z<+c*99U$$rJYP9pL(9<~IPJMSHa>1I$?E_}2aUYKo^qtXzol><8}+70yi`C^wLD)r zUYE+TU<-LMd`9@f@WrYtqC!O7hz4+-5-~qwAzY6}d>QeL>QZN_i`AuY{Yw2!{atn0 z3fd~!s=~Fkt*5OIT;H>uvVEbt?8)|S_WM+q!|urIC;-<1j`5C3aNX{B+i^&BMGlLc z8aZ8cMdgbsA5{si!=k1}vET1ReHL{}b!BUtt#`J5sw=uubi?Q-sw+=ao&tFa!?k*z z#5_rGos(x-p5>}5Z$#eQdGo@xV%`RM8^d*a-bHzrsIL4``3vNS^!aZTa2AMFT?O|R ze81pPxPDXca=|OAt5AHQq(UuKSK;u&afPYsD)Lm34MjG?_4Ohj6*-~0ismX>vS=B& zUMm(=EW7F|R;*a{V)1Z&uGq`PUQu1e(~B=H{v=#C7Js$)0l3~M;Vc39l$clI=@QSu z_4^W6OI%l7CF_)IRkE$>Dy5dnQ!1b8Ds#TfUu6~5Rjy3AgmU%ZI<4Hoa-i>Wr^@|Q z?tv-6@+087q5R(R`&CzkkP5LC;^5l5!UGk?!1Z*6pDSEcT@@==Y*ewS>Z)3$ zYU8SjaGh0kN!4X=eW~i6s{2$|HG8$Z)j;pn_EbAu?TG5CKBjtl^|^3;y86cIFT?ex z>NjeHsID60YCKfq5!F?b)QqW_Q+371#21Y(0oU5`E#h0lbwT{|@hjoFJ^t-@Xt!GS zT6t@MTzGL)+1eH0I==SY+VkN0PVLWXpHf{3`4Y+}Kzk;vP1upJTXogVUbk@FVsIT^ z_rba|;JUBwk-EoJSA#zrW^3qFT}_^Cvbo7txc=ERTT}Smv`y1qP5Y{@#PGzpL}-`9 z$%&69E`aN~#6J^nsIF!^o4woYFkH_zyV&fK>S|uCdDG_2Raa7hq>4#ZR9Euw zpX5WypC_MDT`e+Oyw&1exSnqDa|_U0%gQYqwFJGjD%mQ&Rf6hjy|?xIt-&tZsBQAJ zf%a+hd7JZXeo9~{(IHcVR4659oDL@ zl=dloQ_@sdYWCE^sZh_OlJ&#JDD^Ey7=5$vE-a;I*c?o(Zz_jEqo`H1T3GO){p zE|XPP*Gt_Zy4h7%w_)9;b_2Wb{$Te7-5*z7J>q(l>QNT1nLXa>0p;#lwr8E5_2K$- z&y77_R$YCc?Yp@z=&SF0eNXlMLUr|P*sp!RRJe}lH?7}HxPIC1*M65(SAS>!BK?cQ zb$0(J`n%w|wg2n=-&9>`CDY>5px$YzX=!PL;QC(LsWgx?VD^9~20*%j(+55=5UztB z9rVJWRdD@w(6vE-sjk7z26rFa6Rz(M{%Y{Is%uEaAx(xfgX_W}tB0&pT|@H>tuVAQ zTqg{jKXf5nKO6eG-bWd%*SL1a*Q#bxmkBq0fZ=aNRKBz=Stc*Tm`*lP9)<>ynArYOZ+zGDFPJU%_CS3oT5<4YMbxr9qW%!hls%vV= zsdc8-S6vTYo93Jb{yP2I4Cf5E&b&G+`>Y(QYu1OezMJ)f>YDACU1)YuxOSU;|Ljq4 zeSG%X*)PKN%h|urzN)&?^QKoyuL{>8>C@6d@98Vjx2Nxd>%}?h94P;svU3{DX{@?P zX!H|Anf$PldLw)>2~pvHbvaQ~)pdh}`+mFe6*tIg66Q(bPo_#(DF65KstT!-NQ97D zWN2}b)r#0OERl)*o3D85hy$UDbiIEU3($o`=|~YJ8Kntld{Rz@K1g+|qAH0tkSWT| zDqW!LlEj&XY*D_Mv_6H7BRNcn7R8%Q@3tdQj$1!tNKTU(c{6LyO>8@f`x`tj_Xbh_ zHqWP%RFda!W+`U-Pq?CSCXu}VAa}6@|CBG5Vgt$l4@)7IBp4ZDY1WW}L6k-;QLu6} zR-Hr&2U#$&a5qDirhuuW=uIe~Sjd|tkB2!H9DE^SDk*-G$|{!kX37jK^9fS&CYD(& z_sy0o_>=u3Qu-#BS}gg$A=?+63z4$_Lea(I|6B5f1|Z3#{J&HSu_pg!9zt!D@ucFv zSR1iM|8_otnN|Lmt0Y$IzsO5yFfhNW|3U4<8va-L3AI#ak?Q|ZEybGtmwCEtyO0l* ze;_sg!`g~9{;%^DYOQ3DTK{pa#hTxWyoC^za0{v~R{vJzFE}}bvbwiO3!)}&Wf??m z93=H`p*BQ~-0E_OL1I2>c#E|nYUXw*ix5N_-v+7?)pNU)M|7)X()2dblBlWMsZ64_ zPLXD}k+wvQ-EQR)+%V}jQ<m2 z+uX*g6xDgVms2#*WYX?7*Q%)5JE5$ic4v_ecYt<94c{r{^@W9wB=rtav8d)dsm!85 zCzDQhkhVpQ-)ZF*wf;Kka))VM)cl=T_AsVzM>yY$vf@U_Dbno@Yyhzl?$q)NZlF{n zJ?_v}5L@C-u7l7Tq&4Yz2e*dUB6oT{gt1WXJG@E6X1N>cB09_%()TWC9kGS(mimaT zluY{HC9Nd3)ZJ7kv9(&00e4Yri7j@w)l2B42Hj;%CN|sMSU1t(#*!g-Ve5%4c(>M1 zY{g_U>@ICZu_f>3Itr~B`Ue?t7q_O^qIY{eg;s@4SR?Q9RuxN%a@M*58!kpWA2fL790Css&n82OfQmg_fVUQ?S8M-TjT7T$%K2X;l;+k7whg@ z)+j_K-GfapHvhd^e{oosOs3qURv=o!y{rS#8m5s4?_p~YE#h9+gJ=~q$n<;MDn!e$ zbg|rX6p;7K2E|5ZS_VQyBeC?coa;jvZO*n#gsVg}6H6ym|lbcGuJX1$z(*cv2-JwjW*yUlSeG;39uf~f-L<6T9C$y6qP(`SrKYQq9s{6 z!YzsE$k&~9B#&99q-#o|IazwrHz!Sif-M>gEvquLD$%kmT^UZhmv_wmX|I8AZ4&CEG zI9QvXtsVL#dDb$>e{7JVQCfQZ=SIo&D2x-Iw@fl9lN8O;(q(XF$#f}?BUf0~8MJkZ z7Ha7;cnj59=_azuveKJkrJ|);I=wlT>a$jxoxk8^I9X#^>rJy((PAyV-aLzCdbKe- zWmXHbr%kG@1pE&#oQ3zr4kYU=6TYb?ESj;U+nZ~~hNgUwyl9#7O*duHoGty{d~;^{ z^(`S3A{#6d{#Q&`G-FH0|Be|m9m`7&n=EVo*Q{BzXiLxko<(b|`Yd_bvg&`;szuAT zbp7vIHq*6t_@Oi>TP@T6*G*eAZ%g0*zIpotxcjxt9mzJ!%KsB97cJe=`F~^SOy}}m z3GyY$v<&_~GkDSHExrGDM$h!_9m$YFWQS$)|EbA~W^d{KzcqWNdwJnymu3C`x%G=4 zVCnzA_W-RIoF{uMFSsRMAbNt;2Dio&{NBK4y~<DEH}C3P2x2PXcHH66{}5d zy_ZO-h+8i z26@-=pxe%aL@%=1=l1g=+>_q3Jn6RdB+;9!Ho85%3HPY?EswfwJxcT{tDSCNufjd+ zh~-(gwP%UmWwq7q?OnKseQ0^uZSP^Cms#y~`+FJgX&+ghc1L)c=xtV;-5K77d)&vC z$K5d=CwiULZg-B?A)coUA)i>DcSm`i*ZbUC`c{z7toFO(+D~djC7pb3wc#DvhEh9{ z5#+Shj(2Q3N^Pmw$rn~z-qCI8ZBMpW(Q3;(Ym~~`PWu`wU2_C>l!vdhTVR-4`xZOZJ<*RIM?@~zdbcTKxWZA%7||5U9j+Ba~d$@Ful|Alym$|cB;mJ8qU&8cUO-p7ipHoo&+R&Uddzvvw9b=wB?CzN=kYbZe`v?{2qdZ7p}$7cK9;>%Cj_aI3xVeh=4l z;J;Zeeowf#=;l_N-y3co*r8vxy#1c>cG2UlcE5K#Uem$}S`&DtjCDIBIR*+C#ExAqH zQ22{ZEN8i=hm&4^V4a8CE?O%Q)?mW22_Y`{Z6igoS+-%>hF}{ke)#QUvf{Ap!?F*J zeaJSFqC{CXV%Z2{BeI=zRH7|AvFt?0PGnn|tT-)Ov24Y_R%ClgQF2)JV%bX;_9EL% zMBIQj|E$ZY;YoX*XKi$z$1$WjlYvc4Ygxq2#sf$FiTlX+M$;g{3I@ zEgQ0I=pWdSY)40xf|eawcJvSJNU|l8q7=4l$+D#&Y)Q7K7nGuwJz4e?q&>+t)mkZT z*_35dH^HW4yGl_?T6SgG)lIT1*|sJtr7hdCZ0jc4mTX@sN?FUkEc?32_NBG4@|KNR zHuf*rm~3a0m5P>~S$6g>*_mu>DN1F_)+}557i~?pw~k6x%ib(|`9r?tD9mfcx)_aE7vY}o@{>ylmyHEEc^S9?ayn2H%O#qf44yQ zO#k=#AG{}JA^(5H4drd6t`!CEd5gGJ9^pN<$+AH!D%~m@gyW*z(GWf%ApWYdxDnKfF4CFZ_@uN;4}|TA}hb z36FvgoEZekf^ER?guYI!a+_FupJNI^{x64)N)>~Mi(+ZupS?KhJPjC0$%Cb?* zMsGtK_1Y=x<}Dkwy7}9sd)Jl&x_kHAzM3d)tWau&(%UqYdc&!=+iz#ts%5LUv8{UT zm39A?tyhucYy@W$l6@X4fC#Ji-odW7_`MUuX@W~86J3F+?$A!(6)$bhH; zWMH-r$bjhLWN`FVG9-H!GBkUCxDF&EvL7V(XFm$pkH{!zRWjOHAFhqaIOlU@yz?cv zZX%OnqR8Z!JaElNrpCNarpJ6hrsa5)Opl#Frp3NMX5^etrsv#6X65{er04vZ%#Q0v z(sSF$?A+BzdY*9d5RD{r={w|MdV@TYFPzNF_d0nr-xV@He;4vt{(W%$kt{6Gk}N9l z3S7S+iwo8zOA02zwIx|ra4m5adSS5nIQ)MuDx5`+!&L@Yf>?iM6xk`>yA5M3ZRA9~X!1$D>*RF3zsRTc8<5ZHPlxM^|9-nyFz* zeClgTt&W|P_>R++TAk`EwL5(X*BeSgXGN*g`EjLg=V#%XsWj|TPifR88LoYlrd@wl z61xphn)Prh&3nA8B=sz=B==mZwCLSTY1R7yrFHMcO55H$m3F<)DDC@%D;@gOP*VDI zS5o_oQabjTq1@MJq0+Cw_9_qbc~2SJ=cF>R&kxG9K3A0VzIG+GZ#HFq z-;v5=eW$>6iL$6)P37@^pD2s_Pg0hoy%Xw ze5rSp){OgHd1-uIWyAO% zl#LUbDw`&(QZ`R4ue?0*QDw`-AC;|>#wf2$`bgO}xu%jad8v{)`LeQoN;_r8loyqq zQ#L6(ADpG^n%+g(IenJ0duC^4*UXv9o>>nmyJu}xcFuZN**Cj`vVZnx%7OI0%4_LA zD6h{MMM_35BP3g@(lLB7iO5zJqDn~kbdo_H#RC=|@eN?L0JBAW09b9nRCOs}34l4&>44P%%&z_pSY5!P)U$xq11!>3 z6|nk%MceWN)&Q_R46rzOqjHgK%>m2hm;_i7V0j$<0ZRrfx8o3CEda~w$N;P*U^H?%V66blA2|fD z)_~=UssvaYzzRlDz}f;ve3|NUgg#qgVSm`_tz`6ofDo+w%-2f|_rz&9G0V|VdIbb~i zE1zdJVD|x5E^l7IdIDB4Zx~>`0IQIcjVzGF@CIFUHtO#He0c&3D6~HC| z)}q)mfK3K0x%iWSO#!S`@mYXP1*~Q91AsjUSexQ60X7Y=)+Lw@rUTZlIMcxlz}l90 z4zQVkbtv&LV6y;gU*bAovjIyj@f~34fTfgd3)mdMI+d&q*h7GIER_$ixqx*k6%N?L zfORgb0QLxA-O8K;Y#v};%hdzyQNVhXD+Snmz`B=P4A^6U^(;3PumynKSMCB}3jyn0 z?j&G~0P9tL1YnN?*0+2Yz!n46r~H1vmH^hj{EL7+0a(8ZaeyraY(ND9*fPM?yzoS8NK{(|`@DSP`&i02^905wK?g8&S0qV9xfYRp$x12(!EM3HQ302^0r z7hr1v8(V!YVCw*zP<<3&>j4{I{bj&j1Z-0E<$%2e*u)wkfNcP5O7$NB+X&d?8jk?B z39tuii~(#jU{h=61ngzNrq}ojuq}X1i!TA#R={S)X9w&Rz-Gj^25cK(v*Y6d%K&Uv z{7S$w0h<#)AF%C!rN^^avIDTW@hq0?1ni+&tZusidjw7@Dw1tCU=P=>0N5VD9<7}l zu)ToIt33~}R{?vh_E^C70XDz(DZusvwy^eFfE@sAK>~|IuL1UW0*gbh1GXq(H(+l7 zwj^OSU^xw*TeH~t6JW2lX0h{U!1lIb@!%K0_P1g2 z-~wR#+WZ38MZjKb^BG{j0(PM7Ccu6J?2WcAz%Bvydb?qOT?XvUcAWtG9k7G#%K`QW zU~jk21=tn9-fI6nU{?WqxBW4|t^xK=hqZwH3D|ob76Eo0utO|pC z4wwqq@y{R#10doTOMfWLy#Q=7uM_Isf0QO~%oPfmwcD4t!Wpqx!zU~2S8J!ET zuX@%8EDo@5dzJ<)H(=lNd>ODjfc>xMa=<8H-}ME%kIoC&4}HPzqw@jwecvwt%MaL( zecuJF0AT0(r2?-izYDOEfL-oC6R=W%UF!cPV5I^3qyNi*l>zMcG_bYkvVdJp16zwO z2iTRgL4cJ9?9a3gfK>qOS{f^JMZo?_V`Z)c*!2M}5*1xpJ))2SGf9c)DuCS>$grw_ zg$$fR%0*Wr)fHvXD!{4(7B*-uU^M^>9rPDqH35ql^d(^NfQ1k430N(_Y=avERvR#N z@V9^^0OlC{E?{*4vkz$oSY5!PhLi=Y9$=9})&W)@u;?L=0@eVqY(pyp)(|k~(42rZ z0xbK`g@82%EXU9>fHeUuX6Qx0ngW({=*NI10v0>017OVniyKxGu;zf}8nzX%B*5|v zTMAe*V7Z6C3Rnxk@(y1CSWCd@sDgmC0xbWi5WrdkmT%mjfVBav;J7aUYYSL`@jU=* z2Uy|p4FPKpSfL3Hz&Zd{bo@_%r2tlBLVv(g0V_Ts39ycU6`Sw|V4VOfIbj`OodGK` zu@zul04qJQGGJW+D>ZQgVBG*KJ8>ak-2p2zDGIP2fR&&43t;yFR&LS~zPRG7_*sfYq9k3fN%4;-}UJYzSZpQ;PyN6tLRUVgVZlSltJI2W&WCb!ISZ z1Yq^2GwgoA>dndl*hs({&b$oR1AsM{^#fp|0Bbz!eZWQo)@XK7z{UX9ban(_V*zV2 zdlX>f0Bbh86JX;3OPu{8U=sjKn*A7H69H>J`zm0Q0BbS(G+>hfOHQu}*c8B8rN;p_ z6|k1+GXZ-Lur}!f0GkF_>-1fKO$V%9`m=z|0IcmC*1j_V>yXaccNSpn=QIXvHeji9 zN&=P+SPCI?Mu!y%D@usd5j`jRA)-V-4r@iRM1lVZQOoX%UP#Ex@Rg8=Xcv5TBatMU zI7tk#L$X}3sAMO3;7Z||53c#)S`e;<;93N(Md4bU^J8EMsx&M>QBsaXkn)g0MYvXi zYZbUwg{+^1bRonZy&SHQfIHwXax|3sDMCVvk}^tnqA013Lc|82v5uUMT#h(L9{9`Y z!Ac`oc?7GBVAT<927=8+u%{4gH-a5NutNxT3Bj%)*!4gxvMqw8AlN_zn~GrbG+0FB z>d1BQx1Q_15MjT!X@2j}{NAJaym(D05V*Smx;Yq!d_jX-9cSWk+?#498r@Q;yw^ z1CB$EOO7j!>yd3EQz8dOPK}%g`ra0~BXUpV{>V2X-;Vq(@@iE1sLD~*qiRLfjcORx zG%6{oRaCpE)aa*SbtFw8AscO-)p3fg1N-R4K62DM+^4RpM4C6 zf3UsCKK8JW&*4M;0{%h0#6CV_A0M)hrR-x7`xwhUhKIdI$ciusJ}cSBD)zCOeXL<0 zYuU#-_OYIQyvROYVjmmW$42(CiG6HlA1||yE$m|}`*?+YY-1l8>?4zXY-b-k*vC%x zv5S4|W*>Xl$NxLH^JuH4I1b?F+`GL<^E{`4G!L)oHET|3PNg&{@e*m&q?A%hX(kGp zS>|c6WGF={LS&xjSwy7RpZCvaeSdqOb?!d*x7Rvn-Fw&Fj_2?^Ucigkft`2>yRaKC z;}z_|tJsTu*pJunIu2k{XpkgtNN?gT9K_pr2Z!)3-oyL&03YHbe2h=c6=N}?1>qYTQT9Ll2tDxwl9qYA2`8mi+o)Id$tLT#LmGf)R- zqAu#8J{m+q{n*g7p|TMgqY0X#8FJAaEzlCJ&>DGY6G=8>dCpx)vJ5?Q?oE;&xJJ29 zx(bW17*}HnmSRCXE_4VTlh7}8OTwTqI0;>)-jQU5v#i9m@!+s1EKZW^m20rt39iE` ztTQ$MYn8(=BSY(E_cMGo+bli|NL$kT#&ZvNPskF3vL1MVf=z=!UMiGR}r( zAvZ~Kb8e3m%1^>u;b0Qp35SxL!Z;O0P!z>b93@Z^rBE7WP!{D-9u-g#l~5T~P!-is z9jBoNYN8fu<8+*XIye(`Q4jUe01eRyjnM>6(G0n0juvQ%R%nepv_V_6Lwj^UM|8qj z=!`Dtif-tR9_Wc)I2*muAAN8R`l25OU?2uzFoxh<48<@E$9WimkvJctFdAbp7UOUM z#$y65#6(<#i;<5>xCE1NDK5hlT#l)jhUu7rnV5wuFdK6)7xOS5S7HGc;wmh{VqA?S zSc+?~49jsXR$wKr!z!%C^;m)dopB(n$m@H*baA-s=|@F~8)*O7Fa^c{Z0FF1@NIErI95y_?qk@Rk<5DKFx zN}x2#p(3iF25Lvr`=mOkhlXf^T(m?U+My#lN74tRZs>{L=!*dujNurG(HIv=AC)E| zACoZ^GcX79u@H-~G?G3cEyqf%##(H^4Y&zgaU1T4q|ZnN?@Pf|7OeSUV~^oUJdJ1Z zJa$CV?b0s1g1vYRZ{Q$wFsp-E9n9)r`huj5S#8YfU{(jSI+)eLtPW;%Fsp+hiKMPF z^=cuD9Grq8D2`GniwcqWH@cDiIDohDEW6_Cf?*he zQ5cKyuzfPNPr6>RhcZ(z4Kpzt^RNJmumsB@=_aY*0t=Q~@ZuYd-H4lU3%21-+!IMR zOZVeJJc7sZ6rO>dld%snJFzxh>r#j#RrkFJv^6&7oFeCB#|Y(lQh%v~G#0~=Z|o9Ws2q<8n1)Fv oCgWn|L|lZ+F%`4S&X>kWqcIBSV`L<>4tYtjE%7so_=}k2f5A{rPyhe` literal 274944 zcmcd!34C2e)xXP2-jYe$q$O>-04eFdWNVWqh2l%PrA<@1H{D)el9x0zOPi$&7EnYK zP(eXJR8&AjKtNv@a9Y zOz8LZc2wdos^#fgnWeuib8NJCD3csMHPE>&Gn^TTYEfN_Bi&`go$0=`uASK`iOQi& zcVDJ+q;flnxA*o8q(?@FGOKhgujAB6W>}x~P`+Nc^l-W<*=$ZSi?^2K#mr01WN|W? zE}k22DAYUjgc)xsH1mvYhF(zIl?QZ#MM}EpJZ*t^imj6)wu5;wJUy*#HBX3vwvR>L)PW5uiEmwX> z^0FevFZFjh`VC4h{cx`6bki6bvF z9Q=_|mZKe&HMr$79C^Ev6aL7VPCBRD`g0upGSij*JV)N(mM?PT?QZ!pM}EpJuW{sM z5m)+kj=Vw1CC)~c!_H;xZux3Qe#$Lxa^z)sF8i-@d&S9Revt=t8}DX_2(qF`g18){W;0q{dvUc&&#a-T ze;#rA^D=jT9&!5fGOItA^{)DJS--CSJmU1{W$ykw;`HZb?*2UD^yg*muKquw`g4ij zE$?vQSN*muSGOZ?aLZ-?-;_L>S6Dv3e@4D(PARC?XVe^y>SaTEGP%LrUCtiCTWC}?l^1W_mE1cs9zV6o zG>n@3vgERvHHmoM&eCJ0Mx=e-)Tr5%JYb$UQeK{32>EDf^%+LV+)}Zpa%N+<+17e^ zplnfhPie*Uq;b}T2j*2Aj^!K1nx?Yitz~*qUf%38lF1cE7suo6n^B&&{LMYdrX20an(!9Kj8E11V%GqF4B+9ogp0aYZcwxMuvV3{7 zF(t3K_@F+iC2{VFzV?;Fn=YBMa?-)7e!?{gxEk|UOoyFMn(L<|lUr9FZKwQFPJU+< zo}OR1w<@#t%+vEG&8Y3@&0kYKC%xKeOGH~RjvY1EmYrxjP?%pY#!3vl{b5?Ctj_J2meY&DBhIa zg9oa*+LxW)wRslOUFAG4m+7+K!_M*fj-3nF*X%#hH|yN)%*NLBO9|&DSG?xNuI9$m zy9Q>}cAIn2U+t|L>CLa$vsBL~f2^ByuzGZpkw_ZkPi?UC!CKU_*y`mYQ}pJ>PW9ZF zvU%!>zS*lfdP^fy(vFTXM-ukXoW5t5OS@nl9rRPpVIS1CS z9$CNTz{>vfH!e9**rHGBNr?4@Ga9>l+9D(5FXnk=3znAEW-_I-R!-VX{)PP4Hg>LW zJ6*S>tmb%6_vzzX4%7~!-7e^FZ#>kKKzliG-l4&bOL~f0^pc*$top${jh&k|PCeOn zpz36%bYxo6ir-#4oLN2fWZ#*MgiqpKyKC0T*4flAh^>U*;gRpU#?I!F3iKb1Bk7B! zKg#sxCksZ_=2xuWe4uuur|BZuJ}CcXg~jLx`s&H9N7`h&F=l%Caue-tfb55S#lGqj zn>H?~ubi>UnD6N2FDpZRmd@H!cxJIN*O9AsD(d_9=~G+kW^Je}TXnpL+R1@c1Do<^ z)ua5yj(qW9q|>pzMiiTS>t(&ezm6ZsUp{^5%=&UO>ELKRuxjwYypa=2lkvdu~RQ>XWrt?B|^cYRH5PR!b{eKUcJ$vHmrN_1QEV)B>+Lyrc>A^`Czg<3EoX{pLX9F_}N?(~~$o zZ|T9tLz%Y7N%(aK>|^6>CB4$AXcvvfIaazGXT=8hNdJt@)#Db9;hrXiBR_88o;NtV zfpMdput$CWfvSjl*RF16Yr+B@1I`8)Lkl&@@`+<(=gozxyef3$n^etj~%Pg~KhH(fGw{lLCj zq}y8!yZ2;Dmz?M;tM5a9ktVxs-ne8p#smGkOGlz}^(ggA-Dp?c=NEO=FUvQ~E{t=E zr#B5xDK2iPOfNJG3Oi2>wAZ0sQNO)>cvI==y2AZ+<>pfK2M%wPkzK9)XHvVA{rtfB z8)t18oL;Zu*IInJIhXqr*^c%6k+twg)lY1Ne>wJ4_G3N4db4ZbPpx}4&u%=Lxn$LX z${8!m&8?pP3H|fw`GeDIFFcUH5cP=m(KdBH{Np0kPodt>-$Yh*?`uLoN6$BwOfC2F z5!h#RQ(fd_pTsj|>indakGANAy`_Co>i?*oqMP+150C!otgTCS7m>f9d`mXZKGeB0 zp_>P52h#8t>Q6f}7nRO0^63@MJk;6Z)7yGc>3XC$oBaU&O4qc387sS6@=u|jfq&P? zw8H%>4j(A3h|W#IpDDkY_5GX96zd1}G+sDbD$3ceo7NZYuRYvcbGoi_=IZWb9>uTD zw4h%coLzQkd*iJ6mDC=b{D)4WYYd(gjZ;rgU@IwoCNE*ihIm(ly} zg!GrD1eJ^8Pjkh`NYcV90md?cZ z+Qx}~6zzVR;yW*v{c53|Zb>V>FNNDKOZDi;S~(t*_cAGJo?_^v|`!o7!f@T=p>*2Fvlj^p6Kl%W{rQhsz5&`l0Gfs!@(B4mB6e+TDMk zk;bJ6}2^u90;xW^H-BS-3%OvCR8 zdcVMbT=6jeuB35ZX$AMI`N^iG`x{4_w=G#Yh~FvwrBgAEsU78ZTx=|L@Hpe4gH^*A zU%JcD+q`!P>b0@Emwp#wyj0Bn8|f7r(ta#2E2rN}_?^S!HDjiiFE<KG6yyKt6^D+J%KEG|r z`emE-Y2&0q9wHtD(FbNQ!S<3!a@BxQWO_h_8M@#T95cH;5Z%2U1k zJ5!CnY`)xFYtJXln?(57o>T03gpKljsQMMWmo6EOPCh965BXj?zj4imLH=Ee52H2K zx6rjGkM{L;_Kq|U_8;x-%WOG1(mOaXT;XM#`_jY1QLPXkM#JMpwMn`*B_Oh{ongg1 zn(jQ3?#Wa%4G#8IM70uKo8)^G)u!SLt9-6&6~2cR-9v-@^emGe*fH4Ji%-AlzNj`$ z*QN$N(Y3RK5@;D1aYde?Ym+ImTk0ySh1gcv-P<*CII7LowIZ)f*UkybZTrYj??8_$ z!?R%}is^d*Q>YKz6&2}$!GVhEsCJI7&Al*vJYCtB9_YcR?&E_;GL@S%BZmjOHlzo- z`ZB{6t%HL{Mvq3dxxgH*8rA0OT0ZORTCw^%UNLmMv+u~^t|3&%B76w9S>SP0y1KhF zP*{qu>O;pR<4J)&rVkH8p-QHpSY0!E2Vvb-%PdW!gc)DZ>2rH(cqBcNffen?J5dFA zDC~!+%z*njRXm=@hC8gd1r{ka3%mL|2M0!m2K!P&nI6O(?nrla4P}Oht5`63xTAA8 zHQdoLI(#a1Vu(^NR-(+%(BP1g38V^@)KFJ?1nU8&dXte#)daJjNQ*qWmQsN3E?w`gc|U;yqy&R`{fINdjr=>m>)$MDEdx^o0&aFt++ zU){BJObw+k8qw# z^{)QZ(C|nKW{%68xZ+_B8>YMRQQJPb1T01}{YT+Ccve$`%6GBk3oaH-V3NaDH>9dp zcqPkI)kp!(iL~GWeOOsS)ytmP+t-J6EPbir-iy#SPzSaL_YQQTwxC6(lMXFC5!sEA z0TFEO)w9*4)qPPNnG@BKNvm>d(iX5WSD%|xP0W5K>och70Pqx7v7o1#U5QUBQ->e@8B z8QLva!7UAVA|X3b?4Dpu6z2(C6J45g7)c6h?&vF&J&RneTblF?mw^2i%b-w%KsjnN zP!9hKl-G_UUp|f;o?RM*XAqw1?yg)dzX1BO24pKJbhxV2N;IU-!Tx@{*_6QwES5dZ z;-n!adHowE@JUekBCifrx@1kvyHbo-6-xqU+ll_o5~_LjXcUW`~K z3z~K`xf8ZHPMA1%!iA*Wv?IAbwQfu68bG&sPHigj^r$A)(za&p9tl9HNkO&5FQX}* zGIIDD-}9Q3_j#@Fd98dNqih*LQPa+r)-|c*h9)@54wN;a1bbT0;wIZnsx7&rWfz`9 zv^{mfwjE@=b;+HrJJ733UrRPOuid^~+6E0_j0{#CBSRlBMuzr3Mg}BfWN7zeWOV_u zdbpb#-`cihQ|nqF43Gk2fD|YLq`(;<1=0X1um(thHb4rzo^owYZr|j$C&~QwB$?ly zB=g&oWPW>+%x_PU`Rz$E;450w+`Ku}lx*9SYHHcB9bFm=Bt41g_8n_eyIa;!>tczl z10~@E);2d=Dg`nUR}EZDa_ihNI1O$ioF}Kzwv&MX1gEiW?fRB2Z5E{M$u-+-S~g`) zNa9f73)gH;rkZxHvpRzW^V?G`Xt2U!$m1ywsk=ReCXE;Ky5#m9Xt+DpZrir=f*q-C zYuB`FTic8lQP|R)Y~HXoRYOJsw#kZj*{sMdqE5;qpjKS$)=-vnC$v4aI|)ovEVZ>s zSC?lil9VlGr6=vGdcLVDvXrrT-C4V6qcH#G)RQvQN1e3mbO-u)+*Qb=C(DdR@mQB;110~vVBK#2YM zY$S3DZdDvf$q-hh0Llf)=1o%I^?ek{5>N?|y~R4I##t!a2Z{p)%WlkZ31#8&jN>UU zm)b5b=cL#c9NG4Gsj57lY3cEamUTPf-^!mYM)|YFN`EeHX@fue`f9d~6ETkB^m7Kkk-N z-%0(rU*@+b>G|zRGQT}Z=C>!w{PrZ7-<~8Re63rOYf?M5q;_s!o4TNN=XPL;wr<~9 zgI*2;0Z@+LSd8);i&2OTN9;-akp1s_wpp(jsX$BC?vPT)$ka|0|>`1m! z$Bmk!By8TYLeaLh81U^ti&w*>IKftJs6f$diiG0W5<6NpuichvUArFXuf=Pqgm!T7 zY*_^du<_CbuCcY8+g!EKC9yVrus#N}=E(}gn!3QPqz37e_0^bRRGURc2S$4PGnJUs z8|}nCk#t{ky033Lrdgu;%kUQL7#zg!hoSUQUAxweAY@L@{Udx%JB8U-6#B(Vhsf*o4JDfVu@UL+9q1DJCjDGW ztyR}%`l8cLnr)*4J7B4bsE#U%Zr-wHXY1MuZ0PZ4<<>Z>0q+Nu&l3ru3F`K7WyuIHzC`D-ro7i#S`2*UWxIZ%m`P!uD#4% zOUnFXlXRQa=Q={)uOCS0`}Bi&ab^aFv3Dpbr!RUt`ZBs!=T6@jH8j;jdO86^big$+ zC!%ZX-3f6)T_yidQtr|-WSwpd6=2K5gI&$(&chja{~UkajB#=_lqko6`i$}Or+&|8 zc|@J=h`e~CdVf$eMi=cy2v%hdYHXuN=N*S14y5p#H51d}9q!0@sv?6L8yUU4TN|v> z1~pb2{l8lqtkMQGRvT{yw>DU%4Qi}5-WhIfuu2=$SZ$h1aaAH%r44GVc7sSkX;(6bT( z8ITbC!ILw1D+0)X2;?i4sWJIiU2Yo z0=%V&K=M>6!+f7F5$ITn1Ugp@JjIZKkqjDuOAQ5Ym7e2)?>s?$kYz0TFz4zuc*N zA_F4$>VCOX_e2InKn2S$=<>5>%!vAI;JCu_Kv!7qa|PlpqXoLca@4nMb+X@6xlZ!s z>bM7~2cU)z;F~!Q-RWyy%$Vv+!f}}8fey3W=P<-uzylp-1$@ByxiCb%g)z&UDXFM5 zh#ZT1h0kM%w;}|3%nF~!5N|~Y^q3Vsk0IWQ5a=;0d>%u*6(P`LR=^M3ZJBs0LZFMR z@VN-_R)jzoS%EtDwPs%ycHp^rt5t*O}rH$u%_#MHBGz~A+VwPs%ycHp^rt5t* zO}rH$u%_#MHBGz~A+V-b`f8eZ6@kdHHNDbT)5Kd50&99Ds?+|Br+&y_*;dTB#M_&Y zo|RCb2dwmY0P$9YKo3~y^8n(l2!S53(&quhTM+_1V5QFkh_@mHdcaDb2M}*X2=suJ zJ`W(?iV)}lD}5e7ycHqP0~&lDK)i}T5dv$v!B^A7TM+_ly1`e|#9I*pYr4T# z)5Kd5Ku!&qW_?}9MC~=Q0v|}5ZG}*2gO0fd*eW0#{nG_2X*g_1A!d} zbWj{rzc&s9b{x<_ao_>oI1t!zg586r7d>%EV8tOiAfIZ#dyv466YL&xwWiw*Nnpnb zc8_XQwHKSq59nbKHoqTKyZnIYpg4X%pv9&(wqQS~_WJ<|>^Q-GQ0?~v64-Hq{h-?K z2PClL1p7g?-w#M&#|icWnillfngmuHq66$klY!niE~aoz7?6*gFmyLw5?J{V9Tdm!95gFv#|d^0ng{e? zBY_P3)9P}^<2U_=*`FF z2lOx~AHN^aJfWRWupiLOpf?|vAJD^~d{EW)Y?$2K5;L*Z#G8!EHE8xQC>g(N(EOnd zH`q1g45GUklE97=>>4x&=*8x84SE=a4Yi+;AA|bSsoueuNz2GQ`MO+%rVj(splLu) z91>Vqi4Kb6cNLl?wBrQ33e5}3Z+i3*iS~QMOsqlh=InAFQV+`6?>sbnXy+X4JTzaJ zj}`0blf5w$3kke=x*UlVgYtx9c;mRdhUON7;`qIWrW9?Q!Cpf%hu(Z#UPBLq^6`5O z%_iFU1bYolC3^F5c?mrX$cLs7J#k22*V4t9wMQ=VXKcI&}`S|^SW*hB%g8hKz7rpto{D2+?<>U7Qnsc=C3HAe;W%TCb z@&kGpl#kyJXy(z*C)f{Yg3*%?39L9o2joN3jovseKcI&}ar}NjQ;>E(!G1uKj^2D+ zen1a{^6~otO+?!H1p5I^J$mzT`2jr)%E#{qG#zQ@6YK{x0qM=hfP85B(G!ORRz5@r#qs+A%}&~Jg8hKz9liOu{D2+?<>U7Qnv1ma z3HAe;ee~wz@&kGpl#kyJXhzb`C)f{Y4$_;C%Ma*bP(FS?pm|9pnUv(KvR}>KEZxKla$_kTz)_ggYrRD^Kzm7bjX8>6g5>or;q|WPM}lN zRQa4j3hX$6PEk|ka|$W2;{-ZIO_k3nq`;07=oB?oKBtfZJ5Hce)KvMLLJI6Sco^+J zvW>UrmtujlbvA)>ApjPn#*_-yC08%7RmNN$fR*C`(M2R4NfcF9 zp}Px^c4R1X6noLnTF_!gmIog=X{mD%Xo;_m^9S-M0+1|NVC}VB6&_VYrbMO|X!(&d zP*~c9+ML8%?8)|OZhIT*UZ3cHyAf684CG}Fa%)Ao!XP3uA~OjpR%I06Du)`Zlc&Qy zV5S8v3-NPExP(Zl&`Al8Mda*AImMm>6OUS&I0(b3GoNYI5fTYo8EMXU(j2cwWHb?( z7nx7FEx@m*^l;xG9n(NCH^R)!`w?ywktLC(6lWQV(lOGJ8o}<|!|CC}VIWog8%H}) zV0WbKz{=<%QX5%L8KYqpyVFQ@5B7E86XzINg@~-=DComvwsOlogDoO;n}_PTta_d* zR?p!fRjegG+mB~bRmglwpAM`rk%Y?EN({waF<#w-CMzP%ku_9!Y-T7KI-WU>z5LiA z&^vMp>)GiDjwsDrrYPGu%OyQ!tSU;nk(0vqv&o+4J@WVvzX%c9*ff}Vz+oyKL$F!~ zCCeY|?v`hQBy1scw{zk+&2{#_p#6qVgUIdwl?2jBE>to{sEYLTsEMN`|Qg~p-x(foua+|Xb%0E-kuYkBSU?uql102O~|2%B^<&28Tnn7 z1by&>$-WZ7Xd?keoA9!U$nnStvhqoc%50msY$%&hrn3`^{5rAG16GhHGr*4>Azbca zZk<@offh$kuxwnaZ*VFq%mV_R`QB-|cG>?ZDW?So;2E`UgFHT;N=W@&bU1^R z>U7SGG6)wNwYfE*HUp9j%g$#25xFAr8mg+-$|mQSKSlFM)Qj4+1PSWoYOa&l+3E~V zs%O~`NW^2BgUZWJE{7H$l(2|g8+juY@J$l2({HD!=fVy{Yg8Cu#}<#Vs2|_-pXi6W z1XVkV?7@Q~W2>1u@?+J1f=onijNC+}d<#Z!{#3g%-RaT3kqZ1iFc&Pu-s>6TY5;+7 z5G-sFk+(-~p>*FN-v%Qm28VI5%TWvfhmKneoZ?n?ira*CqjpnVGa~O6+RfTqiFyxu zDC=AkoJ@mJ?ARksg!VS=?WBA+G%V$czKc##UZW!!+SLi8iHgWWoZQ1`e0)|47A1KQ@-Znwd#Cm;O6qZ1w8Uqsc@z2& zCxne9b5Ohr`b%L1flZF73VAkwb-+xjB6AF*yak>^WmYZRrEB}Vvj5@uo>HGZ29|a9 z3?rhk@h+j=%9ZvBq20#RQ$o9)sZR^--AsK}Xm>F6d7-_BsV@rcPNu#rwD&UgRiWL* z)YpY}H&fpf+C5A?EwuMB^^DN&W$L>^yN{{w3+;ZUekio}GxcMkJ;2mYh4ulaekQaB znfis$9%AZOLVK90-w5pyrhX^1N16JA&>myzIiWqy)Sra*L8ksJv=1@$SD}5FslN;D z38wxjw2v_LFQGjtsXR?+A7#oA+Q*oR2<_ucNQ%8mNH>QS!_IIX6g!T`n zjtlLdOq~?k3rt-kw0|*mT4?`f>Jp)AOua(rI#ZVk-C*i+p_@!yA@m4SuN8V8Q&$N+ zpQ+agJ<8M@gdSt+TA|08dXvx-OkFSZ0;X;dx?t)ip%*fBv(Sr}dYjNEF?Ea3Co}a< zp%*iCtI$iBx?Si~n7TvgQ<=I`=w~o>m(WX@x<}~Kn7UW!)0w(o=w(bjAoLkbJt*{< zOg$|0Sxh}D^w~^3F7z{*`jF7iV(JN@pUu>hLN90PV?v+9)F*^~4pUDFy@IJv3w%F4poDJvUir>v};owBm?i&Zooq*Rq%?U8Dh{!6M^`Y)+w z>A$3!rT>y@mi|ksS^6)jD!T^tTYPSyb*La4_3R)&r+H#JLW)&_Udz5C2wz0eIpmHN z#|38}Sjc)o?_Jk9hO89StNM>Od=Y%kd2la+&psyZMey;lSgbUzg=td$#Z>G;%D9!_ z9JI)31-)+hOhtA6BC7?xudJgNTh_2n(D2F9p`*E2E3lHBLmXLYS%903bG9Q#2r7m; zrm#jH`N(QPm9Nz7lOS0$$miUe*2v+-^sJ#nP{-v?kLyKF+PnxzdCDY%4C*?qL|unZ zzIfTKGbvd!1gmVC^1wz`4H_vb1X7ioN)|@&xA`E4QwdY6mxc%^HLZKK-g8gHOL| z$l%kj8Z!9wtA-3d{i-29p4_T0`r~P=a>$RTvC1Jop2jLG`v!JiE?;2GAwQnRrX2F) zX{>U{kEgN9AwQnn%Jh36zI># zxnDRlU@U@Tcjy~wbx-?5Cyi2pR=#?p75JCMuDN(o2hX=D>&^XVh z=NiEVy#h#E9W~5J2ECi4l5+wvD+YDDV-6-})gbFR=M}R~&`82_j4`VP&GlKQ8;2)k zA9@^)$^AMUFEi&=Hy&!|q-0s2LETcofy#_5sPet%EVEwFo7g^nnN@;n+;uAR_?B=E zYaSny_Y7y&E5YY;Yej{+LQH72+H!n7&%YKc9$b&*f(xOo(CX;nb>4@(ic_oCR?@>8 zgx0`nHwmqgWj70L70ccxv~!udMQG>o({~DOHB+|=?RRzF(W$J#Rtz+r|p{-}?L7{D6>S3X^F!iX=HZt|N&^9skA)&Q0^@Pwi zGxem<+L-#7(6%u3387uUsGbtqR;E5Jv~5g%R%qK<@AE?2!PFONDS=~fUf3nHo!Tz4 z+E;|Oo2jn}Z4bxzhS1uX`j*i4GWBht?c+SYBeeZYeNSiynEHXx4l?y4p{1DmiO>!) z^?yQ3b1FX zQ}sf-iuD?Vb~VeeDCTucohP){^V9Q%_6DYsLc4~kW}#indTWLDMyA#a?M?i&MQGQt zY?IKgXKJ(1-pte%q20jLRH@&p{A=j(Zmh{U zw|Ag-WVLrm(k>BgkM2!q)zN)ejN=?ez2orE;0apE8I2xDXp5u!6529SnI>eGc za4veQsi74`Sm|!9^mm$&?3A#Mzk)XdOtbp3(UIQ1%59mRwF8t#MKs!l1ni#9_mqx6 zk9NnSnP?B1R{oo)JiX}Oti-H)Dx*;>04=dovBWZZe>~b3#bUs@SeP?L!@kT?U8@PR z&59mPAO;o}={rSqm@=Ii#kzvM`ERD|k9$_>uEAPcXMLHM^DUc|4{>mO^kf3%Ifcrw zN78HKdM5C|9x-e+Tlht`Cmy@JAS3dfh=xYe*$T}A9v|l@VtuAD3%+>x&~9~UWTo% ztwZD20~Ok7kKPnr8<%)c6n!ZAa3XqB^bx$uxm7)eMvwNh)a6qz+JLb9H1F7Gx)1SY z1ay(|E=)9GeUKXo&dS>6-ox-;mxV`vD9cBwEFVJ&Y7`=bfr#iXPU=)H;12auiRkGl z22ZQm2A@Th*yV6tsEHVnML;nIs6dduI&zZLpL9QF5zioHlO zD#8*ws=9`gI_qK!rF{1_r$^8s{Rw@p-5_nbY=VD|N1u=WMd%lE4u2E+E13F+&|k&W z3y2-it45>$Mm?Osbu8O5-N~V$G`gO17X&C;i?urkaW88py)!ENM@Q&&UAY^vk7l}L z>{TMB#|(5xF;mx;JGDvO>?+lrx{}zQIp%7CR>j5g64B>l`4~P*+r?tASe>#MLLFNd zrS%Z%*qSP7gp>B!=8-8yW0SE%!f)Ob-iAWILRuv@1t~PB6cEmIDSPifrAo0!7#OLv zVM|FxG&bEm!mz|tC9xUtSXpeQuJt)K@Qwt$+<)ETt&v1*b^;ln>32!2CcTJ_iE;8N zrq1yz)e8Mew#z)Bzk#U*P(p``>v@Mxr7AkGF-zAjaLV*wn?6D<>+GY-fw{0)Sj}SH=yl;|Y8H`}N zG9uPM<@k225kFd3>s)vL;@t5n``Qhxg5L=1nZg-F(`^@YlyM;}^(n8BeM)SNJ4LMF zm$$^?7FJTZnpN;?;wnxN`w?6%00UEbn=Ywd%c@x9dkw3$`HPBQJJ+$&R{T0)rR_q$ zjvZqsSq*O!wi5`iozPCP*TMb?fR(}5b6Wdc{r=|BlW0T-5Z7+GB$5p%6^|W^VR>+p zqjk^==@Fsdz`0|XCmp3DJtSg1T#wjsLZ=8-%G+sE)I2Ywl-(kka$h`lB!=sBu;Y^M z6Bn^TWC0OeE=nTYIxb>EEF0Ffi^g+9ZwvNv|Fw&9dyYO78%@9t$FYI10{!OTfSmBc zP9^IF@xRG-mx!H=ouU?q<$FKOkGB9zJ&g{Na*ik*%hv; zC0xKMT{gN~qNQClPFp%D?gho$eMG~Yq3 zNfrYu!QabPe1O^&I_1nU{(mA(sa^*U#vY==J&eM2RL5eE`hF#Y zsE65~OWDId107gtaA=!|eU9H|pNH|u&U7!1h<%aG{3Rtkk?w`wBU zTyWnv+LfuqZaunNCmQ=ErHzYydOLVp$5xOsjJckUeLE5RR_qy6zxP=*_Fas5DJ}sy zp6=^KfA@Vf@YwfaKM?w3oav9Kkk&ho2!l@XmC!%L@vtiXqfGsZ;#jSj z2!qb&oQa}z17wiqLKJoyZd*H6Wve>g!f6rmC)+AzoqV8#W?0MwTQ5B0}*!u~_ z@HfiU>NSY)fCBm00S(*|gGpyzW&lmbLoFGO{1|3eykwN$(Q`v@wk4iM_I5GxFEsVWI=-=aH zHc>K`>l5Ki2F-mV$H7LZO-yZ5NfWLeob*m?;bf@ts0b0?&GJ2tybJF~5#P)5eM0{s z1Hf3wpaW029Ao^j25s*rtck9`pd(LNb4(kn!H=Auu_i|B1|4q7njpM|s=;rARxV1P z(0|Esu%l`-%Z_qYp@N1e9jnz4;Y$be71fCRvRJ07l#Tk+#z4z@k`hk zm*PVbC-cfN>Ht5}8T8-Km$NRoiFZe*luaIj7MTI3kRe0fFuO((ahfuY-+R4UP0wsu=OR;&&&sGvoK@TBYL?!OBi8@DM6G z9LHAYneqFC{(E-R_v2eB{0}wr0eWHbaHp&HIEFkT{*WAw#IgPDIo8JZx96F{_P4(? zg%6PpoB~D`FR<)M5qW>)0ZJ8fY1`SWKOqc_pFTx%Ew(*_CbjH`a$Mw;LVb%wy?h#< zW8$B|H%m_ZbHXq=@h=D?pQ$fl4ls7LFbbIcsxXR}`noWtF!fDr0Y6;3G8TVY7}Htw zj4)<0^<80{&D8gWaSl^I6vjNJek`Ll#Ns~{#zGchatx_;#^S#a#u64`d;n2bEdCo| zRI=!In2EGJ`b6)@VOgf+K$rZIRS}K*U5r1EFR^Tg zzo6@oKRldsF?4O0V{F?^#?0DhIa}EF0s|o&Ib+qo&-eLb=9tLt&pOs8 zAfz`b5q~x@Swt_EwojA*#*`AxNEC|bWh^R%Xj+M8lIRH*&46fTi54NzQ!F|YqO(f0 zJczXYvLz=lLOQ@y1wPa>H4h)^nOcAk^-L`y_pYgmC6?efM*Kd!ZfJCa@lB#qzCNo! zVb0}T*2ZhS#45R*$X(al*H;lu;O*ud=;AyePfygx6Lkq1m>otgjWA+Q$N1EvlNV+}vWl+O8Vh7Mt@ zXIYoaAk@-T7m(<78^n1a4RSc1=t=a7=;yiej-c}TO0;}(EZ4mAf96Sp38Z;cM1RC- z4k69q5-kdcFg7yMB`eIdav~P4+BrcOb zt`n~k(O+>MuSOnMlxQ)^V;9H0QW)(_q0`>a)a!+jV(J=UbTIWsVPu%PP8f%odb2Q& zFmybDWPWH*|)O+^35=-v%@lnhV(Nof z7sS+uu`YL8Qy&!uf80oXTo{)z^iK-o)l7X#7_VjOGs3uBcqdc86~=8${a#j7 zT`cjeFnBI2@kc4Dk0qWL22ac+@RBnQFOMbuCJdg_Nc=+>_i+j@2;%{!{w<7$Bvqgb z<58weVSJFOJYhV+R8$xrXDTj?rUBMZ` zc$)RFglDVtfPymo?4c%rS$+Bw1vBM@ZNV&Ie1~<<6vp?NI$Ib&VhVllE2NPN(D%NQ zDfGRUF@?VORZK0yG9IRuU>Ofn%jB<0^uGmF!uTntS3|S&m^eFKu$<1z^}_fqQ!T>y z15=xX@kgdM3**mBZ4t3`oW)jTv8_ZaCZG5lKinyde=@aO82@IfU6=+_`>@c60UW?W zBQ8V=3yqjc3p0=PI)xcy3e!)UII|vPcDO_Wv!PQJpnqu=g4+&qY75+_HZ1sB5?cp%h< z*@B8_!KG+p>P;^t)VUYDGG6eCg3I9X+cWrebPj$Da2(gC!`^=D`y+Jl`=j9Uf>-0a zW5E?z-0&jG(E`j%=Vkhjj^O9%oEJ?TXp+n4Fj42)QxHMhv6 zGZr@{6)_|fa(zQZf9I}>Vf_BC89SmH z8XXwv?ax%wuxw@JMtgvz;sEju1vi#xQwwfFMbg2mFB=!P9oO|Gc5KZd#hVM>N~qr^ zVmHulUZda^Kz>Jwc1FQXB6cT>ZiVQ!60MX(pJve=5WS~Fn?|Cav*<2}?k>@$ljsjD zx)-ARO0+T(y}+UeAo@UwHiODAjjPlucGKX=OxI5QbdDB0jHbS`tz`$T7#l|k*dHx; zEMD+P!Q;X_i~SV8*51f%=m}xYVcCsJPsnZ;9m!L|T+E_R3v(G$pA}{` zQ<&;C4==BZ6?_p35;@&33v)R?{HiePnfkgg8=3kh7F)93)51KDWzS&QCCk1m;s!Ui z@52Z`DA8t8V|y8^{aD0Je)v;7{J#=y7Cl_c4}ZZQ!Q^x=onI*meuX4s-z)ev5Mo#u zEBLK2H?S_=GBKJO?&=)r!$=Da!996QQdsWUg6A-`T!7clWdGA>!Snc8VoffekQb?l zg1;cYfEK2o60+2yfJ%)KkAQ`EP$eb_ z^Pq$yiWPc7&@tM9wG2W`;q0f1ctU!iz;6eE-ww0knDIp{!fywG-wtPz=sXtTw}ZfM zhqFkumPKOtoqf_nzRSzVyIA zrf)bZ@H4?kW0r50Yw|_*1Z%K-bo6LnrmJPkDk0Vh{DxaA@C#zP=U0qND=Idkhvm-= zf+iQmCb3zV-Hc$19B9ef-pbFm3A2}yeAnVXLz#0dI zImGfq!W?C)0~$j@bg@Q8m?v4@Bg~gG)hi;!{1k7$OIX$~%vUmnw_l_KD^}q1E>rMa zm^dbes5p37Y?+Zk zF{!idSTwck1#!%*O|r&)xz_hx|<|-YU$u zu-e=4OBYKIuo_5+cd*_&h50sqcq`goUj|QZ=O^zL<~#Vwdnm0@oXsi(eUe1ZcgfzV zIwtNB=B=!BFGR-%hlRMGRo*Ymck`1E0JmIKCLSX9xm-Lf%sctfqr$wKsmI3{k1Oay zB664#{IEdBe=qCe17Ku$WT-=kkMX0AQ=fwoD<)BfuF+9haYD4 zJH(>io@Dm>#G|2D%V|MXVVo?h`a2G!(7N+OXyZ9BccL|e+@Zz_`!m>P$ z7k?lY*5tvw_@gj+FfX1LCJ)ucU&yJS;BVX&GzLKp{he*|53DgGtM#BgU{S0U3h@Fz z|Cca%lwYX90bo7Yuh0-C5BLisSOP1BDSm?Porms)F=6sJyD%Zl-$)}A3Ss`9sUl%M z$JAtDKF?H%F#pQbRAK&usZwG7i>c`%qBAu^L?TShLdDXRYy6c2gh3amF$cn+tI;G! zgh3aeF$cn+>&%z~VbG;z%z-fI3Nq$E7<7{ub07@5FN`@52Hgb490-H%^NgoSR$VvexT9azi}7J1zjt#Ts5p!=!#8DXJYsF))xbf*+^goSR7 zVvexTJy6UM7P{d{azq$(j}vo*g>GeHjLp?jHdijOFU%1Zy19ip!b116Fh^MEwiU?{VbDD)%n=s4ErmJ4LU*4qM_A~F6XpmD z-B-dKVWC?|m?JE7#|U$Tg)R(Xj|7eAW}Ri@W7;aP~d?|@e&^`1!SHm6R$j*m-uMWn|dzs(IO_r zOMJA9N%0aNEo4%>#79e+6fg17>K(;Pe6$ip@e&`cMNz!OM~hIHC(5j*^%{zo_-N^d z;w3&>jiGpnj}~SqUgD#b5{j4jXg!4DB|ci&pm>Ro)(I$H;-i%UikJB4(>?Pc~-o{M_-i{FY!?)u6T)$x^cxzeAIt4 zPn20rUAf{VKI+UBFY!@#u6T)$I&{TLeAJ~YUgD!pUGWkhb?b_k_^4x7yu?RcyW%B2 z>eHDg%B-gDUGWkhb?}Op_^69lyu?R+yW%B2>gE+M@li*wc!`g?dc{k8)Y&Uu;-l_f z@e&{P^UM=vR#TU+c!`fXeZ@V4f(mnqC)*m-y&~p?HapUKxs)_~@mfc!`f*8;Y0s=*6LU ziH}|#ikJB4<)L_qk6s^&Cw%gjD9K9-yoFCv;4OTT0&n4y6nG1tq`+JFBn95WCn@k2 zK1off=)xxg{)C(1549D#Rv+*w*80$!>0&iZuQ?x4)#poluF{&=V%0TH7SW;+UArzI z`TzBoUe9-6{($U3te!icef6fI!;#S?wDBI(wI#I2UWV9C zFGFmmmm#*&%McssWr%I`GQ=i&8Da~)46%V;hS)wYLu{UxA-2xT5F6)Zh;8#S#HM)} zV#~Y?v0+|@*e)+aY?hZHw#v&88|7t)ZSpe2CV3fRi@Xf6L0*Q~9xp>|j+Y^}#>)^J z<7J3#@iN2)co|~*y9}}UU542DE<@vg#b{S&(x(u;-U541YE<7E$K4EhIAQXJGu<98C{0hiY`NJM3*79q011P&}E1%=rY6xbQ$6{ z3QaG%7__0i1?}Kw?X94j=(-6R;)Vzr;(7;!C3O9P3~y86?J9h?3hz+idsKL*3g4^3 zyHt3$3hz?pLR@Ab%Ymy5 zWQdClWQc1FWQa=)WQZ#aWQYq4WcV=^eq4p0P~j(4_>>AirNU3E@G~m>tO`G;!q2Pl z3o87g3csYnFRSn?D*UPnzox>ktMD5t{H6-OrNXCG_-z$Fqe5IpAj^ZR2xN$h2xN$B z2xN#$2xN#W2xN#02xRzU75+qpKULxXsqkki{J9E$p~7FP@K-AQwF-Zu!r!X!cPjk7 z3jd(OXI1!|3je6WKdJC}75-U;e^KFIRrog*{#}K*OhA?gR|&`v7YWD^*9gcEmk3Zu zR|v=u7YNAEP@$>9hzj#mn6JX93S%mat1zL$0u>4s7OJpFg_Be`S%t+aEK%VU6;4&* z87eGQ;WQOaS7Dh7XQ&XD0m$;;DgYVcA^;iU8UPvM5&#+E3IG}60stA#QQYo96)sa@r3$N5Sgpbu71pY7xe8aPuug^bDqN|;1{F3^ zXxxkK{HyeHHKXVflErrFO>14e=wW^H<|R*Qc}wnpK;OP-ioSF4!+QI} zdg@`lbMxXwOCHvHb}zXf5zL}X@o#~qzo3;w^<-2ZD0&41`Is5iwBe#x;@`88a-Oz8 zKdkpcTA21EO(>{$dO*G026Z|N6xLj23o0i^f3FAB zB{rx_!$7^_B?a|L8`NcCpkDQog1X!W_3AKCS4=Rddp*_n8XMGW!$4h`J*ca5=@Opu zfO?$`>h)ouuv9QxN5A&J2lYl9)SJRU;WKTvpmORwU+`G!dK=W6!$9E!akijxv6LS7 zfV$BJbyFB9e2&f*)LV0?K0V<9^)?&S+rvQJl0B%LEae6D4ja@v!$7?&dr-IKVyOa; zrEa%Dy*mul9TN;{vIo?AY*2TGfqHNDpmM6dX&z8_*`V$Y19eaKpzh73`et}Q-DiWk zKMWMsKV;kba`LH}9#9Y1pgs@=3M((N1@&+)mO9G=>Jb~%qhX*P%N|rtmO9%5>Tw&? z2g5*pD0@&(l^_0jA>_*BvZ>I*igFNT4_nx||*J)nMMgZgn8sGm$QDDR}%Pi;{D7Y6EQ6Aa2bY4&p))Gxw7{c?gq zz1&lMzp_F7It&z+T~271@JbJ;-`b#l7X}I|K(hsv%WFpS_EUebK|LD=3X4&*1(nkT zhZoczZBTy-1BG?5*@F5@4n4ZhQh&8U{VfdC-?ImmQ}rG4_|!jaQ2z`A^+NWbaSQ@(l8fQXAB? zFi_L82BqiJPkBL=*`Q{Gftr~$C}Z}2Z>ckFP-lgKIy-AnxqTV!_V`q}4QfspsB^Lh zl~eV3K~>nG=7xcqmo=!|9KFY5srfdj1!15TzNDZQ*`OAOfm-sCf?8^WS{4SXGHXz| zIeM?B`l@VD)nTA&vImuuqrb)js@4XzJPg!|tU=}0PkBMr*`VsfK&{LkR8FrMFQ^6^ zRAU&Z|6o~3PStmnr~1ydL7f){YIXLO%IP)Z1$Dj+>SbY|lG%gGsrtO2nru+bVW8Gz z4Jx-T;q{*CTWf<_7Y1tm1cSQP18Rc}swE5*4pYia8A7n`}_6VW4oXQ!-Y++H6o;!a(7Oscb>z%7^se{LFHC`UQnGjsID+jne0L3RDE7h-8QJ6Fi?lH29;a&z1vfLy*8+@6|r;@ zUY0(UTlINC_1U2M!z?wBJ*b?j&kJhM26Z$H)UgQ$b%&?=hHOy7VW38`29=vnc|qB0 zhmEkc!*p2Ug!+^hl)ZM?2wOW$M>A#%DyKQm_j#(%UOQ}rtsSQG8nXp;X)g0qk9$D9 z!uF|GhWXTG6AbEu9#F5cL0ujO>ebnU%Bf5EkO$NiHmKKxfqHG$pmH1Jc|l!igSsjV z)YaL8%4v}21!b=tHp12p(=nsjI(kmOkiDR;u`P9Nn5EvBJ*b>~>cbwNdXo+6x-d}J zXALShpYnowvkmHoFi=%Bl5vLD{RUjj&bLbdYei{nY;el)cK@ z2wP=MM;X6_pzKxFM%XHAI!!rCP`Nq!S3HjXKHI164fCn{vIdo#qkBQ!Z-aV&7^nxb z2bGggc|m=^2K8VVsE4u!mD_8^3+iDT)FWY_9(_qcJ!XS?JPgzavj>&S(r@jn9!LL> z4eG;Tpq|JYl<{OPKODTEK5B#dSQw~}XALU1F5zn)OMSuy^~o?$Ph|}%w=Tg8>QgqT zPlti}O!lC1>Jq%5K5K*eTo|a&PcW#jd#cY~k8XsmN2g=-C-gPr1!b>CH^SDV(~16B zg38UOyrAs$=tkIjbh=z1OHjG>=-=>E-#2Za`c{}vJ^hk``nC<~nJ`e_$r@B{%SyiG zvD9~MP~Qs!_5G|t<<@z6LH)o6^}{ewKgt?ZZjSB+^kgS%S*Vr@WwkZG-wv7%1HQktL|ye98;zcQ&Zs zhk?Q+Bw2#Wt@Heir~00?K|L1+>W?oes6W}Do(}`{=a&@JUu;l+4FmPJ>_O!;KlQAq z`u=W%`bQY3e`XCTH%Iq^dcg+uuP{)!C?`ut&#j;GfHE};l&Ob+qC0!C1f}Qn6YDv5 z^_iv(DiQ`NFMCisbNPw&ya!ai4JsN2DwZ`UGx6VpDzHI`Fi^N7DckDHsrCKcW2qt= z)TA&_xUMNnP`R}}FDQHEz8SW1pKgxI7F15Z`@Ep0+Lk&a%u=OUgUapQ_YY6?O|wBw z4+B+}J*b@aw&!_3&9Fhu3M!$vYPLbG2?Mn@YfySl2NjBkbgW4DdYSRRRTIT`PYJ=Jw2C6M_>>ovy>j0STe(kHDrPyJ%FUOh!J9n2n7PCm8K11e>M zIur&fojs_|TrBlQ52!91R3;2m_e%<@#|Cvc3{>v~gL;$4QWx5wj)Z~gdr3j{+n@%* zKn+eXsOvnII%5#xDDz=7^sskDX3F6sEfity?lZ} zz1d@_(>AD!!$4i~l7hO_2K9dG)sxIH-Ap-WCLWY6*T=G8W+*M)(?HN_JO>Mb5iy}<@`O&BO#kvyTGZuWqB zqYdg!VW6&?U{IbdzvlHes5gg!x?zGrz0G5(8*NZGg@Jm@1cQ3J2h`0rsJDiJdfNnp zy2S(P?KY@e!a(8P?Fn`CcX&X((+2gfFi^KnFsOHWK;348x;+fkyC)dbyF8%outB{i z4Ah+y4C+=7sQ22S?g|5S_XLCTY$G@Cu|d5r4Ai|749c@T)3nb=H^a_Hr~Bb2wDsNX zsXqIBbTjOHbh?>-LP6c*0rikweGi9K-y;(Y%CnKxeAEW@SQx0sCm59H78Ub@HmDDU zf%@8_a^K8pIQ)JOD0}6;8MboY%zov5 zZlE6UfU;Nan_(;W&Fok1=LYHn9#HnmeKTz3zM1{X{oFu3=mBM~+&9Bk?wi@K+|Lcv zLmp7}%6&6z<-VEy%Kh9xJ?sHxuiQ7oR_>eGuiVcK)FU2H_R4)TY~{Y0{mT8^Kt1XK zWv|>f!&dH_*{|Hs4b)>EQ1;4wGi>F)nf=QB+(13<0cEe;H-8xRn#q3Uer}*Vhd7w_ z%6&6z<-VEy%Kh9xc}@W^?Unmx*vfq~`<46VFLU`e^AS(={mLFC{5q`qev|bmA-9i^ zUQoZaLH#Za)bFzfm7ArW^jPW-HmGOAKs}c=sN5{&1@%W8)StpYJ)bqG+${A`kEQ-> zgZfJtsJ~_nDmP1cLH*4J_4hDP|Hv9tZkGC($5Q{aLA?+L>R(xd%FR+A0Lz+iAG|$be*mquEeFlbXjoTqDLcw zt`s(0Hwe#@1s1FjDU1~1xgMDmnXG>Euf^TMbZ>EV(aa@}MoNRD(*?v(QPGK_tE4H< zXru&}z#H-c;_1;PFNBkuoH5X5=iDNF%O0rVEer7tMS$ za?U-V#ul=aHEfjmj8a{WOxTcQMP%-nBo{v#Sr`l~D9JjQo$p&#NiK>k9+MoA;3OOWizHVCC%O8+Nb>y1%T&P~$6O4@To;_?SjS9K z$)#g9xg9eJ$83^zSU*kc4(ZUbp_`;wrFX)K0HNB+eOPnx|L5k zMO(ZCMe7gFVrlfia6NrGGWOV4R`X zWaZ|1sty%KMyA*W!mFcf21( z%wp7~pQqgfKo^sCg$nOb^{H5$7-x(PBE7?VUZ(!uFWf%Fbz{uao zF7n-hk-wE)=O#?+c9lo$Mmt8yNX}*+srDF!B$wi+un8vv(cvQ50Q#Hf^tj zuptmKp(K>h5=tNt2)!f_Afbc~(nBv&qy?lM#R7t$U`3^?R85d3AR>YdL_S0TK?Oyy zfQpJJ-?JB8#wjgj9JlK(PB-X$boH%8tqA_q&x$a{q3Kx5>$gydjjfQ2kZd(Z z-X|p6jgj9Gk_#9k?-!B_8Y90eB!?R#9}towjFArt$wiEj-xHFH8Y90iBx7Ub4}|1m z#>gKE$t8@DKN6B-jFArs$)${u4-3f}yQg3(0ZDNi)dlDiut{~#paXN>%# zklf1{`6nT{k1_HkA-SJ1@?{}8+Zg$0A$g!N@-IU2U}NN8h2){e$XA5q;l{|n3CSak zk$)GGM;RmkAtaA6M!qT}KVXdfr;t3}82OrzJkc2WFCjU{82N7@d5SUebs>4GA+m&o znA9@^WM3 zLPGLNW8?@Sd9^WeVIg^~F>(+BMd4n->l#sm17#R!6uNfmp3(2|0 z$i;-@Eyl>jh2*Wq$R&j2?Z(I@h2)*a$T33lE@R|aA$gB6aw#EsuQ76IA$gxMav33c zzcF%IA^CtYa-5L-o-uMcA^8Ji|0Wi> z-w%<$i$xyrL*yS~k?;8-@~T+m2Y!hBQ!Mf$KSW*=i#+Uy$iKuQkN6?-Z?VXueu%s- z7J2O7iwr?xk;nZIDTzgX?uW<#vB;Bthzt~q{K5~BL1K|-{16!|7WtJQB16O?&-x)! z7K{AG50MtJ$n$=Pw2DPu@I$0cEb@ClMB2q7fAm9Ss95ABKSUM~i~QLSkzrzyzxpAv zpjhN@euz}WBLDD1WVl%5pMHoeBo_IXA0i{fBCq=)vanEOu;hoxB4Uw&eu#_|iwyQd zWKpq5*$yB{K>#Ucy%A+nfQWI;bf78i>Q_d{d}vB(HNM3xkbEaHdA z7_rEreu#_}i^P72EF~6M%ny;J#Ue}iA+n5EWQ-po%Zf#o@Ni4FmA0p$$BCGl#GC?dd(GQW8#Ug9?A+m~CWKBOr zRuzj(_CsVfvB)}ph)fiVtm}u!>SB@g{SaA0EV7{=B9p`-8~Y)$rdVWCKSb6Ni%j)H zWU^Rfb3a7Z7K=>xLu4JX$X0%cOc9IB@Iz!>vB)-lh^!|T+0GA<^~EBy{1DkdEV82? zA{&ZDcJ@PLBeBS?eu!)=7TMhokxj%R@AE@sQ?bZieu!))7TL!Sk*Q*l{rnJ_CKj3P zhsfq)kpuk@*+MLGupc7R#Uh9LA+n`d4(VHVv(c#5SbwsImQo>nPQO- z_#v{5Smby=M79-+oal$hc4Cn^eu!)@7CFTaky&DqQ~eOxK`e5*A0j)7Mb7j?WGAu6 zS$>G@EEYM(50PEOA|LWYWLL4sNBj`kO)PSrA0oSpMLy<-$R1*m3;hszpIGD~KScHv zi+sWlk-fwsm-r#Fw^-y;eu(TN7Ws@HBKwL(KIezXeqxc!{1Dk+Eb>J^L}rUcF84#^ z0I|rGeux|>7P;CFk%Pn{*ZLuHuvp|Peux|*7P-z3kwe8IH~1lPm{{Z{KST}}i+s%w zkt4(+bNvuGQY>A0o$yMeg!LU zBYuc{P%QGOA0nrUMIQ4**oE*AN@A0lUnMV|CS;1FZ>Yc5Q{wHhsarC zkze^Ca<*9HSwBS15sUoB50P`lBG3CF@*%Ov3x0@vSS<2;KSVwv7WtzeA|DltyyS<- zd18@2`yq0^Smdw&UL>j!@|f#!xZW2JydJVp{m9_*qW2=8njw!1$cxqFCPH#@$P)tc z5;eK0kX%Pt@>6PZGa)%eSn@M!a;lJAS6K3MYI2&8Tu(?|rY1KRlIshr{i2%OLP%~P zBrjK!(}m=Q!fLNnlUoYOjf5qyR+C!^$&H02uT_&<3&~A{CBLF3X9&qnh2(W=a;A{n zOi13KCbtoiQ-$PBYI0j4IZa4@O-*hmBsUk5bJgVbLUIcsd5fByB_yW{$y?Rr4nlHE zA(=kMn|%OxMO< zgygnDm)x%=cNdb|3CRc4~UJ|X$Enmj^C?kOaHsV0vWl6wisU#rREgyh~r@;Nnml91d-*j3-E$#cbA;qQ2+2P0 z*jp(ij}?-`)FrPHk{=K%Oi`0p3(4bz)@t&fLh@oEIa5WJkdXX@ zkgR^ir&L==eo{zouP#}z2dFd-lI1L)#dn^p@gh)etWp}I8Zx|5QuWf{Jh_XiWF&fN zaG{`eLF--QYZYuivmDcW4#~ zuhb(&Rv|_9&JEgrV~SL;+(+)~dMjQUsEfQ~u=r+qP^CP1$YyzDV4gfWPksQtjn9)O z?UpC2J8LLoW5wluKacWE7; zCqMj#{AhgOPI-Qw{P=2Q%}B_TpWFql*ex$r3U8L5+b%Eb8X>=+j8S5?$jkHO)w|`j z0B@Gp=gFJt*VpspH@J#!b5~SC7BH@8+2JxSc(e0$6paGFykvPcl4RL&9bPi({tjTa zEYD}&&^U&+Efy*rjY8z@@(!?S85Ngzq9oc414Qb4)6?GL$VS^ch;Q$1t@cJJ1(_C) z*K6_Ko7Cd*T#MiKw0NJZ#e+mGe#g_|QP5&ypUs^uem6LfX;6+{gAQ;Fde7a3{2L{6 z7+Y&Ds>%DFnrwoOBJYJw2FLgi{tm(4$MAO){@jLlOwbX>cgx4~j6`iCyEeuw4%B9m}QA^Hfw&W{l!C6&H zzWHxjvXpDdx1N@q*K5glnk~5qt@uIJlAr#Ymb}2V+-YlxsjLl})KYam@Kg`=0LA(3};mp~yF8#N>w zDsHh;LmH1PmQcWgP=8d?QUI_(^dVqjfQ6tpP$^46z~F7zQaM2ouoQ9|91;(mmckm= z#)RE)v|canazm%L!~7mP*LxfchE7WnsuvhKEs-t<6Ahh~qMr74hM}7bB$YQ?idV|B zSiNTDnh=DeTqP7N(lrsV#0X|SxwH<>Ic{ZWN@dRey_^P|yQjCj$+ z$`a=mFHM7)4|(VLKH402u&|UDbRQXjyk2jqDD-;BG@13zca%6y@3d6rbC%K0ndoh{ zN6qgD)EwZMSjD3hRNv#q;G6mrEDNTNSe)}$w-d5{9VnBmFqX2@v3ID#iN6q=s_wC= z8q}uhgI^_4U#kSZR+IV~Xk66qwcH(p?swT)8lA9MYO|_3s1(#zRb8*Dz(VSaE#x3$ zA!(wDH1JeJWq^%1@lC|yzhuM<4X~+4{7l!xtgF+XQrU@FI69}4(rl^B%*;GSaZX?q zymOpm>ef}%^fXW1R84QeHNB;{=|3>yg-vgzB|d`_-$pF{xBSGn^@vwZG%fAH96Epl zGZRfqCk;Qp!4u8DXsyX|1tyx7&eT6(qG{>kin*eRrlqT;n{#m)+zY0hp_0j zQK)QT$mt#*a-cO+;BTrD!-}&h<+R1o7CC2Mmgz>~uw+vzYl~y!Fyz!}eWI`GZAzB5 z@L-+(M+_Uzs$QLlYr&vCMB>FFG=ufxQi9m&O`I~m%^=zbl2;4}GlGt`rHSOs`k zXOTrUm3OZOn!D!=be=9*(NW13a8R<-*w_OC9IOH?^J#3X3$gJr5*wvhm^&;Wa|fva z%pDezxr1~Cu*U%lkxs)reGy>60bc{Q7%)q~hk!i+7_0&VzZH#dPrBo3pbT*pwju(a z1FLbxRo-F3bZw2sz^7dCkm>X=#b_i9qq zW1I!KN>a~t4JOYB2NUYFM5U^Tt|)a4R!mV6v~#}T&<(xj1_pLBAM=B^KNQ!&j z0og+=tB7w&)xft_6W=0+FY=EyZvU``pfKV_@{eBsP}ydLo(cKdW`toAh|mkMTriH% z9j~3UrK#K&k5pLCL20c+*nTUlH!yJaRaj@bZsBTOSZC>PNu)956`HQ+YeH7m;=OhY znPa(|%T1+<=r)&@GM1)Kv1JvZD+#@_7n8UK0)?{5-d)Qbk+XV7@`cwR3X4P*l%kH+iCQ zBxkQM`dOO5A6c-#i~&|coPS0s^|VXh!qziNZ;12Gnxhob9QVYKluq^^A}m|;EIaZn zJ3Y0;bkmy2=iZ#Q?9x~s(NWslj91voMJp)=n-Q(o%iK&jTG3gmcxS@V3T7HSk6RS& z(OMK~%{YqbIT~l(#q_$vcg9i7@QkCF;TcCU!!wRziqRQIF~!h~qnLWe5g61dC_8A7 z>cemi)->?g|7A;$|T1{aRRdz?PBl;Qg>vAoov$f?tOv1-XA37_tbkcK{0s znF7m){eZ!yu>7NFdi1V)dK7dYR1mTSZgd6%vMs|$*OG>o4}^D6u_+eT1xqR!nl4B- z{=DNuNu{G^PRj>0MjfK*5uVjRn?+|5ToFbWG$pxc=^EWVq5i0EsJ9&3Z8?@_`8>~Z zTBL>;rMYG`c{Ri+Z8UR&8kp9^D9PG6VH-x(i7`rF?d)6-iP75$@~)?1I33aTlxr*N zOTAbvSW(3qj&HI5EWX7Wj&HGs<6ErZ_!et8zQr1gZ?Wq579f>|HB}O9r!)y@7tp~I z*XqM<5-CYDuE8Bjx-}wUVMO!Zgp^83Sc(a#FU8VG1knVfhFHF$3$RiUiM}S0D4+vG zowFno1vG|8bdE$K5>7->=Nos_2_&1r5Oo3`2TK)hT9h#qbztgpi1msxdeb3p249A= zU$u{)_w{kvdFM>!S7i+wZ&^L#_4-v=u3oHPUHFH76=%3=ae7troj1f8_NzFHhFC5V zze10JUwu#fN~#5Z^#k!MsSNnlk50b|cwFRHKe_!X;8WLT-~cVZs$kTwMzMZX!LVOd z;Ov+B70mVF=*G`^mMfl_enl>qXFcNi_evTohTl~yhIropXP+0~0A5nrkR#$OSw zlPaMPq3vG;?QFWg6mQW;$Llr#Ai6_TYD{#tDt(oDBGpw26f97b7)Yzk`3ZN+q)l?DC zl+~#zR9B=ao7>3)*SKbjaB|5SN_U5?VVkWHdDcjpV%9-B(Y+U)9bZp)=%hrzn#jG~ z1mVG24F1C4uLLWwv)*PathB7$Hg#vc4OFk!cjn3_UO%0b@2OiCC5ovV`FC8>=?Y&5@u@2+z^*0RCVzume1 zh3CcxNbypN1ZUl(i_)Lc-yVk}XWpdxnhwX_wBF`3@4OB-zSx`Pu=MjdCY*7D(YO=p zA$3Nd!tU1ZQdd~;b(6l5x>IK*%f0&GtmTNa!f0LGTAnzo^f$6tD*zTGT|gzR6#*kR zpO1?ixRTp}1G+k=rP2vduFHWF;A0imuzD&LHFazmOdUOurb#@DY_%G3_nw@~x!m33 zD76HR;#~1r6WH>4>5l5^HuX~KXxGjg4SI1^bNR8=M?<~!ZW4N>_4airXUv3#jEu0> zcFv*c=M?v6?@nAFrKEP1xg~TTwGB&X5v*iZdTf{eAZDee?YcH1=!QcfI4pvsp6Fqz zmlP-Umc~fV$G60Sb*%&|tV@TC$H5BgIfo4CgvjFR|09d*Z`9)8c7<0#{S6N={kd*c zTU--^7MJ~xEH2xa#bt9<)3mq&#w>1tUlupeu*D6$;TG2)EG`=?ZU9)^K+hzFSX@(& z#WmBjxKy{rNftQ#L*`oxXpAGXlNO$EKZH}ad#cfr8K_%pSOaT$LyZlnL%G7>r56&a ziW;EC9>0Y7+jZ1f(=WYa3Uy5z`K_fi1m?WXpZXD(Yzzv@pbDx2E}7|65LzH|$u=GZ zeF}FPKtWP(?;y|)K4!5^9HCUxjy}%t-^m%wvglaQm8LLt_WI`trI)q{^-X~hhMjo? zr&V_s`ZQpq-jNS_Jkq(kv-UL5;Ukqa?WTBVP$Rjj(GI^3NAAM84u>C;XdSQ>}GwSq=$o&i`XpGLB&*D|k z7_P7zg2r)mb}J~02^oV7C}_Mf1&!wlyFm&X2MY53 z;FBn5utz~d^b|DIqoCQ&m@0*MVyd@OCvkOlD`+^Qppga?lw&NW=5U3%$ID_+EpDH5 zvffzjt@>oacuA&aV^rIlQ+&reeRT}yJrH^J(CP{&vd=Tw^yOlxxzHNXNIxvnPISdX5NhMnFif69lB=*bdU2f zZ|(s%$J0HN^}1(@r+bQl_mE$?o$+|jG*A4U&1sBwk6?pg4wsAQb-EzeTuu)p7ul=` zRPFgcq~5Hs&VYKwDGEDyKdjf^{XMmRn7=>ZeO|M3k9juea1LrA%|#=mhtOh)efrxO zkx9?=?3(eLaA6)&9|g%JHp^QjkUZOXxe0J^#!>JWhEq6n!YLbJzI za_&2AvCgjahV@bSn-6~rE5QRE%EAL4tc&ujOLoh%b3+zF#*ul}XPieHT?$Z|u=hQz zFTk0}+>piYoNCo8P3Z*Nwb4a#AI}Y0;?7Mbs&2DTn$i0_Oiqydlqcu%JnKrIj#W~X z5->?|b5>F5&$u~G?Ey)N&9kn}v#!gtZge*yjh-HL6P=BC&Iqx&63dk6Brao#?9C>n zg;JW&4XuAsGj}?@9l%ryaxZ6d%cDta8u_%QrCQ0Lx|J-Et5hpG?C`~`W^+4>@l{%D zK{0DtB3Dd?Qr4&KuW07Z6y#o~nY)cZuNyRTw-w~xq?x-NJ%Y@u=QYjT?FGur)y$nm zf6U6u-lCbigP7~>F zZxZh{TA72fkWuGnf8=o16i#Y>Kd5tUg>MyZh4a6rgQ7cV*3m-OpYEUMS+{GQL}iaH zgTP@r0&_z?pz2I<{R+;yQ|ni7;0&l+*jE}*Y?vmiuN`<*8#nCddj5* zD~88MJp6`r54JKt+p}St`)7Nc7J4h4bhYpiXu-M{3=4jjYu!f-EX9uPw1EBC&J+-e zL%jv$Sr6uhe9Thcr_=(t0HuD23oz6$9Hydv;?#XXT##lzgbOm+6|8u&FJ+Y2PiNQD zdKipzY9N!8tNer+wJg(lUSF-77EsjQ(EmS#0aZxJ#b6k`W9)+Xa%HeE0 zTS?SzMIsf5F{T1fV$2AP#?cxAb#4`cK!Jy6E4{Vrz=qgty*LNf@hMR+y%U;J48yz~ zJpBt?jHz^ST->ALrAj2zn*(%y|3IDv=H6;l2I&57K-j(kItP5M&Q2?VOVH|`!6lgL zmc%86Iv${R>cQD*F*t?_{0he~0%LKkr~OV7JL_X&1L=}Y*ThQUQdIaixD+G2G%l?Y zeqJD4=Ohi=)dTem-8rO{!DVPIF5oguEy`kew2JF-Z_XxuFQ|piFFN>IG}E?BHf{}2 z#%X6{eoX@A(?mPt;M|bUye1rn<7oSS#Bogf%HeXJ_VFe>SmzW1XTpQ^Zt$>`9jy0L zKjufL%3!6XcB@w8hMcIh+4>9k#ufPcopGiidcS^SgY6KV^GMcfmA2X72N!v^aJnWw zrBT=jqlJygudpKC!cJ=xHri-mqw^~adkgzgqp)#$_y1Tmj?)RCRE;IPg?+72*d(Kc zP0FvZQr^POfnmhKQ_o=7gNKlj)wXvf0rsL;=#$F;4s`yj;{9j(^f6nRtggY8@@#Qg zU18hURz9n%43~;oT`h2l&+4kc&tgYL*eXLPfDel7TBg{lz(0}ai$&O~IseJx{g>VD z=a0GfE~ao#sL26Og`KPjg*jQMOr@(Naqy&1y@{|@_X$T+^@bD}A8bkN%)XqRFg&KB(|g=rv4|$x@sp0M-IK^-IhFCed@*yMMRy( zy`Wu5?K{e@N;VdiHAvgMJe6!JBI-PghJ6+T=t0MVH)%Czmd?+mUCl}Lt<@~O34o_L z%|%3=bsXOu@D**9>9j}t*X^$Mq>HMhvr*z{Pb(3zk9H-w_RP|Yx|?!CE|Ljemz46j zJel0tGH`ija#sOYa8B-=r_dl@MO=~QYlAB?`6^)$LMFNVMo>7KqqEK@F&`wxWBQ0> zTRZIC2D7ImVDD3sozrHY$vcs*^Gii$-b`}pL~dBA{XhbWbFT-U&E^f8bM-x|j0 zy(+khw?}C|RmD|l&v(UDnVzqPt9kRWr9Yg1&nMzUDzQ6GWF%I{)twSO+YUYprf~GI z;huk3w@-3Ie$nXpNB&XIKcZWTy5}F!3z=NcKax++Um-nzAN=)Vb^mBSJ^woy3YA!5 zG%!xl-mQUa(7xz{YcPG0gp=65@cP9(y=@vYhEeGqsdQUEC5D@D&DVJf42hNAV&>~i zUoBjio2Tfkj3LZj^)&fDcav-4nzYH;xF*x&TDX?D$qNiMxtF`i4V757B?}F=d7c4!Rx(bey*C~wGrd-t1hlfCFbC| zjKq4l9&0zSTk5lw6^@=!+G`Kn+<^6r&S8H`Vy+xO9DfRQ?hLl}&nh~5z=Lz;AdeSJ zaeG013=ejNfqyEl&$OliZosz2>ygjt^b~lc)A6k{oL&Hjt8yaXxO!NNk3ivGyRg?&UgLM;6Yymn%BY%y4c6FfYakN6QtRWel^&Kyvof z?qcv8i&MX;IF+_?0ZwIFnTFH6dZXHCj+@hbkK^V{z81KJCm&2sz231x@8B)_Y*e%& z|DH(4>9p*{IGriGC2pze3Bkm8h2c1}LO0Gpe2HUU*bxr(9;~fjt|wOL9f5|PusM68 z6>dda`6O<|w6ZmB?a?rORCr1T&Y=00;tVEVCeHNcV|!wy?kPLkw{0*y85ttq)3^;I zu`OXHkopEQ{mX~p7rY&7?7jawG=}g{fLF>H*6@v32@a7EL#t``B zt2az+(mC)?C&1kHGQ9c7xu?7_h!>*s9OnM8{mhKK(VmglxgWien~!hOn@55qvUR=L zJ4)xug~<(i0AKeEVw;t4ZV;olSA4tkbv6dW4--`7%Je49B)h)trr#{CZ*S3WbU)v9ryz)t zKsWPU^B?vW0eM8#NO(I5xwGKj{I_oO>e!>$Hxz|aEI5esOc48+IkZi0*6NG_U2#`x ztE(z|Kr zgt>1NL|T#Vw(E_=PTh6K-Kp;0!QC0%^}s#Ey4$Yk9XZIAqn$DTK71dQ`YyhYk=hgY zbV_w^e~4oK4!yAGtaC5ii%LI;doj{``{KT0h3(LL@S1bc)erZh5WIHe=UjG+QtCGZgFQ9WaDfq^$^Zxqz=FX zJW8T_kD@Nvska^A?1F)KAeH_x9>_=^ga>(~FI9@OA$_OL14{Wm*qP4+8v0-`9!yLB z1P^9PAA*O7HMTSVJ{XFJQi=b=Lm7#~@Gvcj`h8Fm`oPAV$_htsYX1mxtL;P}%9Y8U z)te;paJIWkZ?6u{huKcCTHdAS@LcfOr8l)=j$4GIU3&fDK72*8vF~e`1vT64Y>@3O zwuZZPZb-qe(3zRUZoS)jbv>iVZl7{@XpGQ%^d4BsDQAz4!O#)A z(BGcTlDE85gj~6__w=!AD&c!&U~J+^0M#x z=#Vl*dnj-Q>M?i>mHrDJ!$=>C$Eu`X5lDx75jx^oUp=IZ*Urg#^&y?fuWJGJ0Dgd0 z`FH#PQ{{1ZoT|!Kg;jnc#1DGvu~dmsqWIQn-;5_um2tlym*+gF-E&T}pNgl_ngrpg zOiiZYX*x9tM^9^trB#Wr3GUk;hK)H*8oxCNS?6eH&?fOek6a_cnCj4C5GXL7>N(#hn*5V(N*9YM-02h zk$hZ3_1JrKL~rHSpKqbgbA>rOIFgSYBshEG5&Q_%hk_qr^zkTuG=F`3qWA0wr`yfL z^QiPfcpf8tKAtb`zfW|I(YgkM$M9oRVqyFkBXI#n!>ryolB%3NK>nvKTLB>Y@smM|E~Dw4>Bf zy*E@q-`S)2gM&vE?Ked5_py)a%|W<>gGY59?r&!w2?zQ%_$CMRNj_Fz#cB0V;3ue_ zWAGD$!A~&~pTIs-b%U6qp^ zj-J#WbYMHII=K}LH$3feuz?9v2*E+%aCBU6SxfHr5&`910z~fpncm8ryEl7W@1zSk zc1Mb;=q^fd!u4~*MSZ5Xb>l87-d&XMK$$6iaV<_ zOQpp%@)k!P;(Un;3YA?4SL{v5T_n%x7WS?W+*qK}v zdCrTDfINqvqaK=upJP1qdHlS`L!HC1U{ZcT@5iOiN$4`Xj7o2Tmod^`z%Pgg&kMRs z7#dMt#4l2bE%A$t#Fy|(S`u{*?7>Reb*p9+Yr+@w43k@jU(lIGk=yPm&Kt9^O}-p2 zr`2wamowE~fme9c?6VxdsIx6h1EJGI#I_Mcm9-MDq@`x!l}xFt@G7QM)%^OR&JAvP zFL%F}z0(N8CbV)jUQNqui&rz{t-))U@)Yi-@I{?lbWoh<%vP>kPjvS0d!2bbf6VZE zoqNL6H#-pDq{j^92F{u4TD+FFrW0PvwB}{}ve(pTt6#yd(0pC+D@?vu@vGi^ta)A1 za~tR8%{sh}O6-Q$F%s9~^&UMsol>yvc1frI_$`o2db`dVu5n54C%BwzTvEDfM|W_I zMot}Xz#C{wd*BUBOE=<;Ufp?|lzkr(x~$Wmd^<1e4S3K_dr$7UOdwhNCotR_1R%GwE|4a2{wvz|@$z`* zzoIjzq|QIY>-;U8hM9|VX;X*cT&AgcIFB_<2zguZ7MgDa-ooU21Ha+T$9Cz}{GER* z-by9jkGC=sx8ZH9l1E0^NBd6WuNrp#tN+6JuNrp#tNA#8OSj=#I=D@1JKj!PJr-|g zTD=4BU|a1q+&}e>qP&nRw+3H|7M!uYruRH_&SkIZ%rdFXOmNx^bK~)vQUL7Ted965 zecz0{b<+E$4&?h(D>)M;gU+{8dh~r$$^S0O*I3HgG^ZBQsPwdapuVdlsi{7uJ;Ok27*Y)sq zt@rB@_`1&f^$>i82kp5DSJi?b|!MjTh9j2k)Vc+KKltjd}~e#ab#KgRgx!nyuYXruzHwep>x~ct2D9ck#P?_3it8!aP)8=Lt=&>i6TT zuf2uL{lE!CYyTR@!qol%K0s>^SElv{@j<@!Hs4)bsg?od!^+sJ{91;UUsD-vNcZpI z_h{|m%GCaS{JyI8zKdR{z1~AqoQB_%uf5JT2WL99^nTsP=>7xz0j)h;nc9DdKjdp~ z|H#*JlJnQS{V-emWW&0zWl;AY;g4wTkKm7(+8@G)_}cqE1u9%h);axRaoRn3oQBtO zlJ#!ga=K5}n-4L%Ka3C4+8@P-nc9DhKUUS=_g7g`?fi8QKMP`NU)!+mla=9y?EVNo zLTi5vA7N_$3I0S?d*9!BK<)Fld-jwa5RBS=ZG(1y6d$Fv{~RA>YX3j{KUM90f54_lf26&UDRwbse$z0)Ig@@)!Ps(a33hnrg&;eYgF3UT6TX z1f5?&azQ379L>`%-*X-rs#%8VDd)oS3_e5Z6&i%kF!lNpf64b$DEul&wLvE}*Nd6` z*`_qt8(F;dYc8nYSNJPhKP&!5N= zSX{4(g;q1}UywUF`6?~S_ z`8j-!>Rg@-qZPG=BHWQ6DP8AL228w27i>y=gTJ9A7Q){!C4P&)Wxb<_X9t=K7AuVBxjq`qO1Yaw9zjlSMmAzkkz}H0Y*B0=# zruSI`f~R7JOY`&`iZkVTI;VKZlrgk16v)qR=c%4zm}hNC zCo1Rhc^Uzl;`2-d_zr(ZBS2{C?$Fe{(Db}e*rJ7L%>{gc=5C8GFu5<{i>ln*i@p}> z+{k6#+_X?_R@Qd3%qR*NcSe5 z$B7pC)R4X;DdkuED=o7h{*@{73ckXYIlx`R-|%lV_aOWmllyo4yDB$V!^L_-pI3*A zeR_EU?d3o4AGFLN_z$MctN1Eg<}h~+|HOaN+#~RxOzvy=nkqL}!zYZ{;S*dSg1}`R z1%FOG{)PXd<=&6~V#@s+|IL;QdK|kubX;EOMD8G~^rX(@hC3+*Ia9Sq2yXa$GN1ct zR;PBapn)aM(VojY;>#Yu5){on`l3& zH_!LJ4fRQN&&ge&jS{p`qOG4sK5^|203?8IzcY@wo>A9`9k!R~J^u#QMlMcQo}+Uk zf}1|*J(`L8EuyqU?~t>1PQOI;vp0y|po>6gZy?ph4DyN7MGzoCDqVmrIPyYg!#+%s zC&nygU$o(zxq{?iUR|)KCalL3f_6S5ly3(ab}D}f z`NYW&1te4`|7nmP5&EoiY2?x5v+TQ6JUvwaq!gefJWoDxC4>PICM@AaVgs;e#Qu_6 zdQRu~1f$94xL0_&d$b^wRgl(WIr+rZLjgn))?<}Glh1Rbo?Cu6$OxzM*N{(~{6c^f z63T}MK7c0IsWiDvsL2SB5H)AG&SCM-KU}PZ4XClH03()Zfi7N`!UGQ{WF{IQfYF3g?H9Z@B$9<{K>QKd7b}RILFV3lNh2H71O`cJAxiFR& zgBVhb#+N1~HrO)6^y1XO2;WBt+uJAi;B*-d2SS z{@j!6L6Y`%KEEJXrSs^B(EV&=TBT$5&T~5u{Crihnof1a&suevryw$|HuR8lV%NMX z=shjaMi5)`)q0PVf$-qkoF?7k-mw;2<7%DrC%m#&>z)8)E4NA+s_7L@uNSIyP5x>X z+z?!2M6IC*G}X#he2tD)=}Bb$8-?C`d20-7b&X-Iu2!^zqK;PA=C4&jEM03ztM55y zt*i>y8g9=Ty<^|r=(b82-AX_ND?y{%2jmkM-AV#dQW)J1fjW%c%|&VfUVcP{y=aFtyOYE+8W_7n1nt8HmO zN~>xMbIJeZg&yNp+3UC&yL(Mj2H0h&y>OKs2QuQQ z{1fC8C%+sZ<%IH2ilXucW2@{9!giL2vdYtXd_g{O^{4v0oQz zG7+RC(h`0kpSTjL15#aB!jFO$Pjd+^VwkNJ_g0;$Z|F646xph1?{J4+Cn^giV>W#7yk*>0g%^;cJ$2(2 zCtG!PUu2bs)QqNGQZqwN-a&{_g z6_ULa+Ns>Ue4EZscKB7wHk~u&e5Y>Hc`CKDQwzX-b)8P#ruW+cu2Z+^#D4zV`qpst zsJ5kO?`v$&zyAf3{Otz&zdrPFecJ!z_CS5E{~G|(z)=5h&$s_!`se9?)_u0?bU*h~ zMrpg@?%$q&_shE7zg=%R#&!R8!`;6v-`8o0cPV$|-~EEs$PR!g_`H7$8KRg(t(ps<&irg>72ZlfV5=fxlW(bdbEOnYejkF zPDd+_*BX%4YM!Sad$@YI=UN%S$)NJcosA4mUM3)!ygYKYlGdXQ{97B!BX|BIk9NRmN9B=SzjmCw_JFik$qRMWBMbg5i}J{NI*a3V0HlMO=c&hDt{yp? z(96NogBJuZk{uzHL+XVzgzMyxc_9nndN}0Ekh8Kwo*^%ipM>jI@-Omlvcpo+Qq@u& zt{Ik|mOgNO-*VD&T6S2|t=+8m$qt*<7Hum5*8#Tiwn=c^Vtd#2p6sv>vrn;4lO3VO zLK8x(!gW~alu+{hKSc!}bWzxeeMN{I;BQF3R=4@(|~>)Dc5 zO8y}`Vv=K8#I%wfvB9yCu~>GLdZyH?r8dBIZ>dj89g`iUiv{nlJ*c zuO{qF*eyFM2UL!z90}Lnl}A+`3)fSXf2@32c2ucWrE!&JvZH!p^(NI*;X1SW;_6G_ z`bza3)pyB`8rB-oH9+q*cGUQw#v$2}G&X5g(pQW8?2KT}qxypgh9cGN3aFScG8xDK!PV7=*Z-Bs^Uy(6-t z;k8Bu8Y!})>GMrDG~Eo>Yt0HYgYV5UoAqkeS9YWZr$(kizoh1*KAQR%TrZ?vOT8{T z(zd1@O#1+?XVNaG{VF?}*J$3Xd2`v(qC|@-EfQr%`tbAz)1jR7_tH+X33y z;e!sRI-HRm9UtlVY)7zzPU)Sxb-GV>bl%bVgU*L!N0)(JCUnV>9bJFz7ShcsJGu?) zHl-WbefI~uKi2(m+0i4iNBJI=;F{NCe-Eg4&q_V(_G|#xXM3*exlwlXeZKDoc-VoX z@B4jE_B|~-`Zem;u3rbZj_5bF-we2Z+3)9mS7b+jrGKgZW#Q`R|3v?#aNXR0Z~u2> zM|QdF_KpSKl@}h$Qj@m@WcSfH*ng(CkDcG(4&K19JB(i=LY>b=x^CE zIBjtE!9C&n;oz?ZpOYO!stjp5Bn_?$hO8X2Ms^I18d`a1HMmX~I&bI#xPCVD$DyF_ zVJXAf3~LY9r-yAA2K64kYWViyZ_19*A)||pE-5?4eLe1vao1$W_-5m~j_(22%M;`Y zHrX+u^@KhX`os0r3412IEjuPAO-!HI8m@~cuATTQTz{ElofIlNCQY8Sa1!|Yq!W`a zP5MQ4AUhuXbE+~G{B_!& z)0OFPopE($!I_0*$IOpselzns+2OD`VjQL6+RZW2F&eIqJ61bhhU=G(-yBzE$E@gC zRcBR)>yTMfXMx^ly)Buq_C3o@&pq;ikIcnvg}kvbrhx}la-raK4018kdlvVR=$zE9)*rW zg$#&h#T(7;$rk%>xU6xu zK+*rAbhZZnme1DWRaE?6)`G2xKQh?btU@LIs0~{qf90sGx&?~$vtn%JZiFmV1v{Y9 zH=u%SC2y2G8sTLCImVBlIP&!JuNv&X8ax=?dS|g1|Rc>Ny*cRRFau_qKc9WaLHtWAA zi|H^hzv}-%>)00lSLHFSlxCu&|EQI0OaIFI4>h{Q zT46PFJJf{Rn`nvE)a_I!R$C`g+HIsQR%5qYy%;xaahs`( zRom@YH`d_Bpq96x_E-(xuJvQJcoMa~O|{5s@^-ExVqjb_aF<+X;7S{TVlqYM>r>XfLomaVNKd=?#>Ddfvgk z!S=|V-VSCi)cX$a61H3JhPJQ{GZyu|3wnp`p}VC$Y%isw{&z_)u|0J+wTbPm3^d>_ z>Mgd%?zVO@gVdnAtjpMLyBpiaI@|+j$X(cbY!BY8?PGf}9Syrndy(zQySa@_ZwCI3 zM%=}{$@b{o-cF`h;SkpScX_X}J$o;-mF?XaH2NOsUABksmG;uDWA6`eI-;@nNJq1s zeJ{1y_XkWbqjC38pR@gbueDp{>>JR8d#vNx&c7Gi?%CFeL6h#mu4lXdUTr@+txHFf z?@=pYE#Y3)0c#CY(S!G}HLwSH$52Q%Arm?lD1!kUSx6Q`LFovgf;)+|k3`e&9zm;5~PCDS_nwocYUO?~=rp=v8#k5-sgdPA&~ zwNz85H^x%E*7_@b!OL*8%Cy!SX05EnntHu)7EAPMp>_&Z3#+H6WlK2x4=n(_@dW!9Wc{oZ(UCi?YkA;h3pO%uK;Cd`_#spFet z#ze>bmcx3}ns1slvleaY`Q}-)+N#f>jiy!KRI6q!+tl^VwQQnm_w++*jy9X7ebY^w zHE&bjH{ZOy0o?go=8ouf)5`x7D`zd;)cJp7=|t!JSqbzd$}p&^q||$gIF&z`{(xaBC#jE zZ+g;g=}D|NnSFG7dXw0rJ~Tb*w)H61tIU47eZ5NTS%*x|x~)Bn^)9ooZg1}rd)UXO zhu!ub#(J6AU$?)Pi9PKT)6?z{GU&g{24$Lj>1Ck;WL znx1z@d7j(*oJaazLZ6xacgOV~*N4(9bi(YzJF*YCencbCDYGB%*nZ^tQnI4cW?$aX zed+E`a#qpo%R6h9O8QRy7bwfe>HqNb$j8u^rg!>iNUgCu;X64O>72LNF5jZAOE8HX5)I!L);WHzKH`!UhRWQ^HOCds`#-di$NH zckHGun0^3nLv{UN4Su!;zghcPa=sU-Zhs(yhtn=H zq!4p5VcG-}7reHSC0R_{Fl~de4H7@R_K_pmO#3kHLuDVljburorj3|3BCrwOPC80q zrk$8}qG2bzt>j3GX)C6!=-3KxFIiF{(_Tz_$;V!Jo9QSOHf_eV83Q)M+f9}fY1)lx zHwNuSZ97q>?U=Un4{V3GpX*YzX+Ng@{6qWUY$zy8DsI}4X+!_QhIl(VER{6v$h4z> zX-Awbp)4uZv?bG){IDh7o?etnoAzYdlb`m)+f;^B*0d?prfz^u@phFZl{4+iw5uCr zSG;ZINEJ-mGHvSy+7@qLSyCm_zD)bN!S{k`OdGoiHpbgoj#S08Gt*nToAzef+fBAN-sZBTB-7?hoBI!JPHlI!OuIAf?mx0S-u5!2 z+NSN9w)Y>}9&dkpq!iQsO#Azf?ayt4*OA?{zgwVtqW^pS58jh9nf^cjy7aD8&y0fi zyhYq9k8nS>$+ST;D%~m@gvUiWqamaa5Py~$m;uoYh_`T>;0}tW9hyP$Rs}^;t|~BI zmKvFX(F}~YFfbCMbO%S%7R}&zD}$qNfJE;}P0Rpk2FP0+Al*UI`9RBfshMe$rcK@k zHtDuYvhi)&q&axs>cQJxKD;`BZv3F8Qkoem%}{xpgi3d~bPwY#OxrYV^ER?gw|$b~ z+_X(|ICl@Hx673o)?1pP(+r)rS?F|!PxtWN+O$#AMsGtKb=xT!=1m(lhxyxOcvsg0 zhI{ARzM4vzW+*j7>1`TH-Qmy*jC;4N``;aR?XpGJ?!3Y-vh97)fY1SGV1bX&fUvS?aM)Eeq+k~`v|xX@ z4n!jg?n5IB9){~DXtYutjZqrFwJ{o}EJNd!SKzuHO$rZ1IpI-oErzCqe~6}qe}twM zdK68In1H56yojb3o`qWGnL@Ttg#A|RpjTV)xhZdJ?0oPV&Ny*h{Y01~% znunf=*@2#oxs0BRZHJzZ{Te-2DjY2xA$5Uq@JpjG7_Mytzx zht`z40@pv#y7F0QefeH+?Ta>5sDn0F=!#yiuodN2*az2l(Hj*vqivObK-=RdpdAT+ zqMcQyqBpC&hIUn*hIUu|9qp;s9lcd;AY7-Sebv51?^OE%?Mn$K%X@%f=)E-gg$RL4V`Sb2R>gwry7?-CmXj#Uo^3!Q%!24GfkGFFPp4@ z>uPkisf^Awjeu(;I^T2&y3p)TbTO?t`aW$r`XOxtTsNajEh5q7^s?xe^ls?amd((W zmM@^+TD}U`4d`m?2=r&`2hg?FpP;{5pN8x263QqeNg1h9K*mrhFk_(mOd|oP@xlSsdxkIXw`9A#nA*pueVJWF?hE%id87Zk< zs8qAvL8(^zo>I;BbER5YX;O05XHu;WK~i#ux1`z~J4wkMr%AOtHIV9b`WUX)rIgN+ zRJZfvQoYX4!!=K8)TO@ExJx=*`$)~Y{wSq(8z80iP^9KPHcBmemX*?bJ}I^AohG&J zJxa>xy+~@)d#lv8_ZL#TKEYD^J~gGRKHa4beMU$5=W*JqhDxX*fNc%Plp zs6OvY5A^w5n%L(%X=TAW>6 zdLsKx>B)f;q$PtK($Ybvq^AZqke(j=j`Ylsa?-Oy=1R{ERix*K-Y+d1`myxFu?URv|O zL22~^zesDxJuR&n_qMcZ+zIKG@%5xv$A2fSo6t;JKVgNmVPb-`apI%WrimA&&6CDT zuTAl$-OUl$Ucw+A_JV^v2|urLB|KOIshDDQ%n9McO)TrnG%VXKCAv8PblK zbENGvH%nV*9+Y-D+Dp3~pGkXW^_AY5^_{eL_GnZtY&t>(I!GOZ7om^>CFLC`Ab1)o zULXb~At|IGvJ{8~EGQ%al`K#Su)vT7fRzR;BxDjQRiF%D!69b>D+`z< z0V@ZXO`Zl=dBCjlZ-7+*EL1)NSVh3>mg<020xZl@9I$x63RwC8mH?PyX$4qizzSMU z16BpFLY9MoRRt{EdLLlb04r>54p<^!5w;S5RR=5*-l$xvKn=i(*d_s%1Xz@MdBwu~N zVnR;>)&Q{5q5A=A2w15C{QzqOSlI#@@U1amWx|>Q)&#I}VU+=E3RqlJEMUz5s}N-a zEETZwQ7r&V1FTY1b-nz*+#75aj?Y9kBT5Xuw(mRwX(JuvUOoj&1^2Yrv{S zCjgcKSk>sofMo(!J^Dew+5nbVoRr%Zu%zOo+;)J~C=mfzd%$WH{|m4zz-pE}3|I%i zYM0y&SVzE;Oa1{^C%{rleg#-(!0N=b0;~&Q^1gtw?^-FC4 ztOsC?N<9VGeSkGAbquhcfHf(#2e4j%H7;Edu-18g8*>1Ce+Y!G0r%gzLBFkr39?g4BFV3}oK z0c8F54h!vJermgrzOU~S@-0X71#_HhpZHWILQaeo1JKVTi=z5#3$U|Hqb05%%1 zPUY$VHU_Yc<%Oj1#sk(hzCK_R0P7K79J z*d)Mu#!mq(2eA9%F99|gu-@^X12zS)UI`-rdl0a`30(l23Rs_n-GEI4tbfAGfK3Oi zU*$-^W&k#zG6HNSVA++&0_Fg0Q01P0%>ry-<;#H025d;>6M)SDY;cukfXxMLSd}V( zJp|a$>ZyP|4A_Y3RRMbhu;JC00QM+g_g9||*gU{SR^J8Ke85ImUklh{fQ_m_e02d} zV`~s!T?p8i8ixRT9I$aUwgI*Xum_Un0=5{i2}z>?djhcWNgDxs60k{0PXo3Du!%JT z09y*!}9~_*LeW2R{)z==OkdS0=A&ee!$iN_E-vu zL+b&1JcY!e4S+37*$&u7z!s;h1Z)#vi|UmDY%^d_)++$mYk)mbZ#rPF1Gco@P{48l zTT<@`V0nN&U2i8~TL62ikpkEofIZvrDqvdyd#34Tz_tPQeA8zE+YZ=s%}Bl-fW6R^ zI|$hN=81s42iUq6 ziGaNi*v1yc0Q&&24e3M&9|E>Ho#@~rz&53S0oWnHUQa&&*kQn4Yk3f`j{(bT`8r@n z0LyJjeBl$o-e^gD;V58RS`lCPA7I;B5nnh4*w)r5fPD(sj@D%XI}X_P3=%s(1MJNV z5<5Q!Y-c8k2PXjAok`-sNx*hx{sh=5z~0LI46rW%+tX$}V5b3lyUkL-&H%Qz?J&T; z1nix*odEj^uzl^~0s9)TciR;K>?~mW+nopO9AF3A9Rchczz(!u4cNDUz2ANzVCMmQ zFDo0c?*RKSs|{cm0Q;Z=v7w8A9qK@A=zG9E>Tm|I9{~Hf!+U`J2-x9{Bqsg@*e4xH zOuPixkxuskb{Vk$b!raS&ww56d{yo^z^(xHS(j|Uego`yH!EPj z19qb8&w%{_*yr8ISbG()Q{Bi|`zK&0yFU)tHNZ}HpA6VvfPK-U5@3G=_GOR4fL#ad zOb_VGFa+4wJ)kecB*4Dv*#NKrz|Qro09YVkXM1i0EC{e~dp-?VFks*G1-lOm0qncJ zVE6Dw^(1t@?`gm+fL-i+5HKrX7y5Mo%m&yG{Tcvf2kiTPGXM((?5BRi04o64kNvIy z76#bmey0H|2-v0mWdTzF`=x&vVBvuM+nJW`nJT6$R{%>_LD<0d_6BJzyBHKeI`lqXGLno7A}&V1Er*ibBJR%R3}A zU3ju+4xa0TwmvNx*6XR&@BAfYkyldiYC#B?E>>mjtXfV8urV09FUEV&kp>mI7GG zai;;R3s{NqJpii*SnT*lfYk>qW`Yf{27r|w{{vtR0V_43KVXdjD?6bDV2uGQGvRH( zngCXA!WzJu0v0#1HDJvEt1z(|V5xwWpZF?ZX@FIlxB#%`fK{9n3Rnxk5+?oxSUOi}5o$sGXe2w3uz27q+}EM-b*z&Zm~XKDmsT>z{1 z;BSC+1+4CLf^`F|!8C$(2dw_gLV)!EtkH}sfZYdJ!= zSTjcmV0{2<>KF}JU%=8FodD|xSgPY?!1@E$!Z9DPY`~g3t^zgyu$GQffDHsJeO7hA z1_9Q3RwQ790c$mD24F(~%bYa;u%Uou%-ROnFu>Z*dLFRhfVG)T`ga6i?Prnx9SK;w z*-ZeuAFvLy%KFJ|Ywn zHWSir$d1C0g2Is%vK4_%B`b=8D~4+^xE6=S!?i5shrhn$$LumFQaicdaRK=@#>0&KVd8!N!(2(Z-xY@GnxBEZfFu(JZ}yf0?2E5I5G zuq**KSb&XJVIlT~_Qmk`1l7GAk?$|4zOPVyU!(f|s_Oej)%Vw#@6gxw)2ccU?3@aN zdW1$XJo3G`>U*r}ds)@@3aal3s_)fQ-;-3|YpcH3W4=S3LmRPm4x5O|gB2IHMcInm zVr|21V{LP6t8MFSTWn`+XKm;0b?pu9S@yy9@u2S)>?`bR?62B4+F!Sywx0`)3N0QQ z8(KEBLTEy0wa}!{+M)GA8->k*-H~hw1+23)m0?G$0ZGzG(h3s!XY#2KNs5xM-;qz> zSh`7;pGfi-B-Q}Htbru4k*}3VQlBKLBxwVQC6@eaAM$koNrsYS97(2-WF`?BN0M43 zX-kr>@DG+JNwS6{??NKK5C0&aA;~)=d6OhFNHT>aeMr(ZXgxwN1wD(-plVl%B-XY0;lDtcj10*>}lJ`jRK1n_x$%iEQ zh$M$dvLq-9p~K|U$0RvIl21r-lqCNn$uW|AN|NIw`HUo=ljH9dc7f5oEB;S+d2a^0qlAlO&i6oav@-s<(A<3^K zxk8fPNb);L{vgR!lKe@MYb5!LB!83SIwTSziA0hBk_3_@h$O)z2_cD05(`PJB(agi zPLfcP6d*|$NeYrgAxSt%3Xvp&B!x**gd~w9DN2$kl39ZvLuNkNjZ{~CrJg8R3u3ylEjlF0g|Ai(4kUg^0f*{s* z-@$#yW>tl80KWIThk_zQQ3OFjmMqy&XxV%3y;sZLn=)EvDNr^>oM3{1zWKV+pz-6xh3-*kC1s~XyWM3EO45tN;;hbagSvPa^-v!T&=8IA z2pXdanxYw+<59FgOSD33v_V_6Lwj^UHaeptIw1$S=z^~3hVJNrp6G?%=!3rKhyECV zff$6r7=ob~hT#~2kr;*17=y7Ghw+$ziI{}Rn1ZR8hUu7rnV5yy$U{EnU@qoiJ{Djh z7GW`#U@4YiIaXjLR$(>PU@g{RJqoY^8?gzSQHUaJ!B%X;cI?1T6k``kup4`@7o{no ze5l|bS&fR~+_-ZT?@Gy>#W}o%cW?igzu-6gfxlAX zL()IEjH|eT+bKx~CmHl=yL}HQFH?Ip~7!=!5n4CG@T7GepOr^LslRalDxY(f#XVJAwk7yDD<6O!*GDSOJYH9x6* z2G8LIyoi@^DkVNCoyO~U18?GOT!aoLI+*BSqJ!}(k~SvVnCM`lgNY6%I+*BSqJxPJ zCcme|o-!``v_Fmgjel_k*KsQ)#0V*|RmJCV0q@}he1uP68FATeD*OJdCH@-U;(Ppv zpYbco)?x**6~t>`8SypTOvyw@kcEn<4BIDDBPCuh)k0m=MITQ19tL6hFg6Ln3A9Vo(S;@*p(~-#7icJ{3AD^dxNKBKHxM0b#Lt<}3 z+K<|%wUt(B>gWA}{hDdV4q+rhtt|Q8^YWbYoO92;fB*aEUjQE91tDd-EhlJOMf0Tj zL+iwJUCU8Ggz46a-M5^z;&$M+9ZP{oh&7}Aa=&FdCSkr7ZHhhXwPUsXVm(yX?PJ&U zgPv6)$jvj~>J$E%AbHg=wk4X&7Icv+l+SJ)h}0xayf17E(`1PGQ?Vl5Bvq;Elu+X& zu&+2T-&2*n!BsCATU#{&P zkyL*orA%Y}N4udONU|{ZG_Rkw1!1zXF#D5pR0>4>>{Vi3C#(+JwEJ_{v0JuZ@j6}G zvG%*Z?YaHjs915#eqVvgz56&$!4#j(6<~s3yM&qA<#V%LZno$JK0zNbu!=3o#lnb| z-D8+WLWO`7LGt;e33DSp=cB;r)EGL98N&?p5dIlqV$*hQe~Sq$78-}w;TlVPXt>V*ad3JZ{On3FAK*DSV18ld z^3w0fzD52W7I}B?J&K3#aDSkCi-#Xje1loGJb8~zwmcnLwmx9<4bs1HhymwhRPYuw z=9c3sw)p#>fBBrhjBQ3}oLb|`;!shEBFNa`b&B<2?Mfe$*kuLZYwlRcI%--}Jf5>b Hl!5;M`EXEXNdHeTJkAV}V`Ey-nA(uIiMY(B zHKDM3cl@yT-EBqG&sB|^`t&|jIGAU`v&@t9=FUJ5caQveP2vW{B-@TG<*cszAytz3 zh^4E>W;ZYIZ<&2Ztb6xWbfotvsq$fMHt{xTRLE&K>>tu zTLy;-2EnCTC7*PA9TU72=0^-*4C5Xw8bGA3-KF!NT8`zeGVrl@mSLiCy&F;`VU9t1 zy|ccb-iR`&&70lezY@TG%*(ik1v)F^maV+Y@TlcUHvl`Nm0~?WQlVIj3}dn8(e17) z@oWGwJX9dyipQkcz;TZ*J;2SOy zo->60gY-d~j2BpAn2zaJiEIGd3x)hgv96H+1_L`Fep`sL9M>#6hMhRJ%4OG1_~k~3 zO?;(b1UglWQ7YL~N{K6OI)kq6;a6b*TSzPPwAWs0ny*-=id|{0uCv@U_-dNO<~T*y@TU-k z_ouk-*mR2S92Xh78*?2h^^HJ34IUw{`$!9U?c_^pCXxauI_}W-TUsSZGLqulZR_B6d9Kki8vz9DPme7@_OMFPLT58HDwS(Bu7Y&lKkLD7bysyaL%LU*oURCIGLo~l}TQ|Ez2kg}dXUCC*thA^_}IdNM*Huann-*cz;j1x<9 zsy@L2>5cOGAT^DgmiR}b1jdzu0nZqoKtjwmEK2+K987>`|K!MN57#2bb zgO?RHDi3E^bw=fwSV~hRRG7#in@tTM7Z?{*f#WsAE;$tzde#|bP)XyuGNbUggJLLk zriC!gL^y?G0|~@nMiaP8rznTyQM@G&&IB-~atF%t8Q<8)u(ywOHIUsAfBb%WB-zF8 z2xrRBQvPs1dQe2{<8YZtW9Zrtml++!Zl))+)^EL@E1rzYYLsVqZr^zndNs#{&Nfb_ zhm!YW+OnH`ObWRSD0mImkPOM>>@~=+Bhmyzau=;lUb)x!&5edJlr+1}( zjY+)A1fv5X0b#b@73=THrjaw8bg5W2OntlT7$vI`y*NypTBX7R@kaii$3quF#D|P< zxy~$Wxl`>#kETi`Gs;6Z^=;b{553fL-ntL(dB$>x7a@q}wrr{%`q(ZN3H7XWVC0pww`45{%a7612rt!!n$E2<${`AK`kv03CXPhh+r* z>Gs<5&2`$b()gJUc-ndrRs~pryOe9sv5g!RYN4eH9f&@CL$U6|1Ce5>2tyN%)EA-2 z*uDgdkQN~TYc2h>U3JP;w^<|Vp0=UH!?j|F%H8HE1EYQ2ZN-tsU{1n7fJI)!?G zI)sNUgzy(kkMy+w+pvQ$Hj!zbew}!+7YRQAdm`bVA>aX3xTREv<> zbu=;d;Xs6bctIVgmCNRPgm|+${-owUyiS+k8+a+wuf1{)r|}nS)U(OPsJ+gO1rO$i z_*SF}9?_dpuZ|m>2kQGTYwAhbD^E^<9>}}=Ns+wc7QPGOp+M3|m-3{e9+HN>RV`+9 z`72Ko|^}a7T)=pmVC0~O{ z3eleVb~|~|mptN|dAgmv)vAq0z`4hW^5jRjcMhpvVV%56eG@PZ z3$R1?_!}zVPp}Lh=-U6A-jaV{6?+NO&;`n$b-_WA*rOy;krWdmne~87B6V+U87`CU zCp$pa@-lKzBHKlW;%berkh04(F++zWP~s)9U5s=o<$8T=K^x9g@7Ph+=wLNv5Lx3Dg5M6 z;}X!~PzYyI(<$xH{zxsYW=bh4#srjGq?xk!ec^e=f8P1L@AJINcXxo@?di7Z>9%S1 z^fGkmD|}|?tG&F1&Na-`&v`u~ROs!dJ9xV&Iq6~EFDV77)lv61P1kKrqp94z^3eH7 zldIUR@Nv|KOeUo$u~z#8E6>m;`T7cl`(}#us&9-~-TgL+wcf8xtkvRPbD*7`;4h~* z&b!g=Z)TbSx7#IaptGTQcv>|A*(r1tq%Gvvz*mx zcF;Y7K$rd9qORZ3pR=~sVJ(P`h{`~K`(?Vq%KpFR-xxb?WQhJ52z)f zxUqRm@>$4<2AC`eLno1{r*2VChNBlvRZzcDGb7MjMHNw3sL2-eyp>WdnC(j>MXOO+ zN@Y=>QiIgOH*q70YM}n6o_Y(t7^;%GK{-Xr-pWXfrmMYt0k2Y1*5I*B)L!Z<$`FO# zGHMHTiW;JxkH(E;s*$>_G%W_Rt&Ksuin>Y7T8lJ{IzW9-*~X&hL*-ImQ#NtvEvK@n z(@O1en9Y41+9^~M)kzuS(Tk<3sWxi%di27nV(JHK>IU?DsXV2Y4VZ1*+vu#Iwo+%P zVd{l{+C|MIR+chSSCZXd;}_@yY0|q_$C?QTM4u zDY%hFouIlY*Hqavr((7mwU>Vjzf+H;;jt`KDRrHimX4l3RX|;$CTv9SRcbqRmKsrV z&cJNx8MxO>-J#qzA&sYMsdj2^=4j7ew`9sUhv;lK{dlJOcQ0gk7Yd<{QU6eWo6)PH z2BL#@y59u!IC(1P+X*P95sjt9If1*I9QW?~xG0E9vlJp)r=PCR5 zaTZUVp{9I*G>U4a9@&R9f@-85P(l0AtE28KITvEKib8byD9<9Cl~SG5QXT1j>Q8F% z0i=1<4eGgKq&uk}DVGwNnoBU-Wwn>DpmQniZKN(zv&xVrQeRNh4ZM+*Kw3iGrj}G9-ADaFEviDAtJG43*`BRN zVx_KA#v@3xsPCx9YmlZ>-%w7qNE4{fDZ4tPanvcL_BzZKc@&)%YWy*rg;Dj?zf|By z=+!96PwGQL-Rje@`^QGZ9i&ycPS8*;R+)~P3=CjJiqT<{(M delta 3457 zcmYk5($_g)o}&tbIX*^$)8vOvgY30AA4e$ygn zwOJf>uMjzZRESls*>3s`wXa#`sLu{HiZiK5s)A~#oWjrxql&1D)cB?7`BK}dbJRm> z!7|*~Fe3RZOuavzdD>0g`_VNX6r6#VzW0|O()HjqN z61_##M(PB0k9si*HW#&09&6A}rkbb$${2@U3{^vQQ#0107eSR!KT(s`p=YM@m73RKw$bmR<4xsI zr>OhXOYh-E3U!3~opOywFP1t$U880uptoGfmVntVGkH7_odBwUI!}#BLT?GRiTZ+i zKzSzPMk;lb8l>D(WY3a<*=p5Z{w?%SPo(0ptW+6wg_@j(ULaLSU7*IMqxU+snL14k zDY;}|wzLe~J4XFMxvxhWN7Yfi)U3?mo`Y`9ly44E+3xz0O!eDrf5+*}LoWa&Rw~`jv9ugfxe0rDktNx}N%; znz;pO5_OJpv>{!qRAj?!c3Y7|QOBuq+mKqRCa5?UVJLNw8lueG(W|2VqTbwrv|Q=z z4ve;FCz2wnpL#hDX#v$m&CN%;jrxUhD?pk}T~fMJ=&nCiC{w8n>cWWRY%)pw0G+dx z!-qJFqfSv1KSCNwwNQ`kLb{wfOg*GRcB5BMJy3Ef!fcgA=-i=vig8v(4Nwbpq`Rr> z)cie2^Qlhig%YG&sh=s=QkhyxG22D8m#?5p8SbT1=c(!CNE4{9s407quAxp+6ZRop zMSVt%-H$Xv$+jP}{l~=eF*Gt)RVPH)2Qz#=Q^bE)R&ZfJ!kW?Oj>on~sxA)JL%4b;C> z@F(ciD#=gk_k^yhPs1Lc8V&7A$wD1UO+uYY143O&#s;IITPa59no^BWk5ac#uhNW0 zqoGeJLg>0uiBP}zR*@xsPrVMOinUR$Ewh?V8$8=Id+n+=M{CytwGJ&#>(sVrU0RdY ktzFixX+v6%!Cvb%%-8x1R_(eWP3t%0YHcl(jz*6AAAbMU2LJ#7 diff --git a/target/scala-2.12/classes/include/alu_pkt_t.class b/target/scala-2.12/classes/include/alu_pkt_t.class index 44a35edb465d7d593f15f5b758bd1044a80163f3..36b9e9c2c5e10c298b3be9b3dec625fabde86304 100644 GIT binary patch delta 289 zcmW;GtqwtP7{~GF_jq@_Oc0p~&P=mWBt;Nxs^Ag?7a-Uu;@P+WiNYq@BtrZ z{6sZo(lECQ%ut>US(%9meaeoZUpX@jC{Kn#WhyQVDO-kN!_6eVK>J2f+$oC(mElqY xPwK#<9$qxWo2K~C5?|WkM@J^QFvydc1pAO@KdKx+lY{7T2z?G?jGHq`?*H0XPPza9 delta 289 zcmW;AtxiI57{KB8M}s3egHgu}oH3gl788YFaHA5u1OgXeV8cQ@n_d733T#F<6NT!y z0LI7R>+lU5Bl-T{_U!4Vx~cXRvj=%Gh^Y8*eX^8)MONYy5KD8GDX<<8@MbFupn-9lvYI28Dqn z7|Iu%#lTYT-WFfyq^2bs_R&r*|B^&P9^2Cl8_PlYR%#jZULG`Nh E4^H%5umAu6 diff --git a/target/scala-2.12/classes/include/axi_channels$.class b/target/scala-2.12/classes/include/axi_channels$.class index 16e420af405638e70c872183616d97464df79959..eff83ce3408501cb77c1ed1674836d3f30b2e0ea 100644 GIT binary patch delta 19 Zcmey${FQk_EhD4T3;;<727mwn delta 19 Zcmey${FQk_EhD4;3;;*h23i0B diff --git a/target/scala-2.12/classes/include/axi_channels.class b/target/scala-2.12/classes/include/axi_channels.class index 50a7e066bad193794a1dce657bd3e1e9c66af29e..2a1d0d6da0f008f3e160c65fb1cac76a66aa7ab7 100644 GIT binary patch delta 3377 zcmYM$X;9Q<90%}SsxizL$stfPDy4CIR8B#daS6L1>~bi@jY!C$A_xm5mmpdk!lQ@? z8j5k)Orn(a!h=$qOlhc?M4BnA&|V}`QZsqf|9RN&w>Qsxp6C00{`-TSo!!X^o5=~A z6Bk4Efnv}&Py7&S(B#_dEM5)s(PXyF6Yd5F(Guov-Hn9#^Bfv7*oy{(hxL5O@c+4k zSYedsgGMJ&WHc(Js-BbZ4VOLns&(NJnnuHmWfGCDtpgE7+Um8YRi0R!#Mqiunx2lV z=H6ahj`Y-a(~(=WH8X0Pw)UGG#Z=VHr1FlP2r|i?{ClcR-l}2JRvWWiW7OJZUa8q^ zaS`{-0ZJYsGg{u7iggrS(Qa0aQ}bhRmO!;qBa~e%dQnsz^`%wve;{8eC=Trk>J0S{ z_0n4O3aNhTHs!Sry)5b&b%RpAKKrfi8q|Q?JsFxFP zV;gmnnxwoF(c7rhl!)1WX0k8|og}J_`krz~M$b$&P+w7xr=S-?RZ-`t`;>30ypfiQ z*-ojwe0T3qK52MrHq}l2Lb;}+mrNa`u2GKb(Tk=UsVkIihU_iRz-&9zUe0!&dO-PY zz*CE<0cwg`l8Igp)kFPCJ@Y1dDO5W(s-(}tY%y7A@1d?zvo|6QrK+hx>LK+?Hf~s` zkElPWr8(&3QoTyUIhgI)Ty#>Y4(dAPl!sm{)kFWvYH<;I>C|DRev^Y3E1LO&@)S#pXTBmlMHMwdxm#w^Xzk--ws?vm>)uni zmf&6?^#%1*DbhUZJZ1kD(oE`8YR=n8Q>c^FW80C&D^+gCY!8{3%h2hf{-%uONIR%I zR8R%d7V0<3zY=L9b%R<_g>;uve-&n1vI9va^&RC_jkJ`yN-eBGT0mW*Ty`SOrOr`y zwMaKmpD2yjVz%U6==4*M?#9_Vs*id=nchL~DD@X*co%6qHK{bW-ctnD$y90|b;~L_ zn@k$&(HW;+Y`|G9b)E8QL|Q?8OFg#-X$f_OTF``aD|L}_ZkB04GiE!h_HxR(0{1eg z)70#}NRy}&)Fb%6+iEXo3uwi?z0^(0?*P(z>L==j zHl#bLQOf%u(sJq>YH>SKi&AGhW}DxEB%iuKIUPcpO`V~hJdAWb^)Y4p9@0eWL&~NT zX&lv~G~9{VB9EZcN!_JFk0NcOey3jRLMo^U%J&%3I_gL2`S+35P}h|7-I%Sc8=YZl zQI9+`TRcROlKcrX(Bq~L(thT79D_zhOs$|=jCZBNJUX=Bv oST$wUC6_>*lP*Z-p$pde=|Xe~y4AWoU8t@>7kFyf2difN2Nh7qPyhe` delta 3377 zcmYM$X;9Q<90%}SsxizL$stfP9;I>1=@f(+VFL>YyBtb!BNB3`$hA;%31Y<|Jc@{* zp%{nFBuZH?JServl!l5)q?y7B?L{IbHIqmEpNIW^d-KfadA{H0zdzX7*`1!Unx3*c zaWPcyC5FQni624@nwIrDikHGXHJQwdgp0vWw1v4?c4J{dJcmXMwxY@4YB?V<{C{pI zR)x#+;cy305+1IUrg{z{AVT)!t2RVLY8sCyl}TiVwhl#>Xsi3Wc6nlU5EJXxXnH!T zmU~-qIm%7j%|>n0)~x7aZ5=e)i<#)TN#z|I5n_}(`S;WsJygS}tyU(v#;Uc)v|6*t z>?H1)f|XoFR*bwg6K5}aVw^3Sq!!2GERkxb#weRO^rEQ->Pw5{|3JP{NIcqA)EVj@ z>iPBP6;XrKZOVNEdfC)5>IStW0lg&ZfYNXRX0v?_9V699U8d%}j^0|TnmS9}qh3hF zjbiE~HBEUWp|@G7B?+_r%w%aYI>}TA^*v>mf}V+LqQ0UYPet!ls)jm8-KPT5KbLg5xp3ynYuz*XUd*WCT82I_HwrK)B`GT z6P{X14N)`H$}IG9sXppg>X|ptOQkxgaV32=W{b^6dk=M$n!g!oC{;@hQxB;Zb8y2< zeMJ31dF7&)NA)X>=3=&I^Uz77x~S`vLq2+OR0}miJ+TG7FshFFjQW=f+KL-xO5IyA z+n-Flx1p0y4Ny0!^&RD0i?p1&N-eEJT1Z`@oOU72qs~z_ z^+-2SpD0b%W44st=nPVizKydD)ByE>GQNY}QR*+s@GjC$YFcSwqnmi8L8emss9P4v z*<{kxh|VPC--NSz>N@4wjI@gSmU?av(lY7_wWI~XgSktS0os7Ll8T~GB>_o?VM^o~%oRM>u*7VO7tx7A+G7Tk_|d#RgL-~ptK)K8RO z2hv^CIOTB=X(jaywW1TLS*g1dvn}pIQb1jx91bDPq0UfG9!9#6`k1nQ4`~whA!XH# zG@j~H8tukxQAg0}rtVUqN0D|=zf&*wAQjXU6>tn`1N9^2`##b->Y9?i7qeCLqBBY@ z?~`XHv#Tgkl0RXF`keLN+RuC^G27>^_tCUg@2mEe{qA}{r3;$;m8=KSgz zW|?!SGj0I0N;uA|E@$9kT*)BMxQfA;aW#WG;~Iu&#VAftBYc`nm3&@%S zW|?!SGtLFGN;uA|PGR6;oW>x}IGw?maR!4s<4lHV##s#cjI$Y980Rp|V4TaahH=W| H49;EvG=M5I diff --git a/target/scala-2.12/classes/include/br_tlu_pkt_t.class b/target/scala-2.12/classes/include/br_tlu_pkt_t.class index b3b06e2cd066cdfa3759b95dec114f8e9971cde7..6101bed8e4f8980a67daa459d356950c3ed94f66 100644 GIT binary patch delta 83 zcmdlZut#767aQZY$^Y3zCo8b2Gj0d7Vu7q3VAd=kYbTg>9mv`RWG$22!obD2jX{oa aJA)D94hA>IoeWWoyBP8qw@lv0UIzffCLA*W delta 83 zcmdlZut#767aQZ^$^Y3zCo8b2GcEzMVu7rsVAd=kYZ;hz9mrY^WG$0i$iT(8m_d$l a34;;iQU*81Weib_%Ng<*7f#;CUIzfB=o?P} diff --git a/target/scala-2.12/classes/include/cache_debug_pkt_t.class b/target/scala-2.12/classes/include/cache_debug_pkt_t.class index 319d049581ebf243b4704cb749ccdfc3cdfd12f0..9cab16ffabd09c99304aed507f42f8733cf11c56 100644 GIT binary patch delta 69 zcmbOvFiBv81smh0$sgE6C;PFfGj0a6x`C`MVAcsBYb%g7MRX$r7tH)H8CQ!T?ZraFdI PO!W-=m`W!f=bQup^e8No delta 139 zcmca9a#Li(em2JB$sgH8Ctqb#XG{UJgxJ*?Q^72MAS)fr>H)Gcz^s!%Rwj^T!NRUtz5ie8IrQ_>w`6@fCv+<7);t#ut;5*-8MY CZxGG^ delta 47 zcmcc4d!2VfBrD^!$x*B}jMpbm2a-1?Utz5iyvo4Ec#T1h@j8PM;|&Hk#;cQ)*-8MM CLl8Cq diff --git a/target/scala-2.12/classes/include/dbg_dctl.class b/target/scala-2.12/classes/include/dbg_dctl.class index 96fcdafe973f766308f0e423076937cc9f99850d..ab0e4c9cf9a2fe2e20e84df3a9dc99846d1bf00d 100644 GIT binary patch delta 75 zcmcc5^MGeV8!MyPqYDSO_RgKEkRY ZYRbUHXvUz&Xv*LXRLKKTKbes&4gjV_4*CE9 delta 74 zcmaFBbDw8J8!MyoqYDSg=k$%Bmr% Y#K6U<%%IDt#NZ87$OBP6nTah90E_YtfB*mh diff --git a/target/scala-2.12/classes/include/dbg_ib.class b/target/scala-2.12/classes/include/dbg_ib.class index faf7a7acdd95142821851e1d26b6560f12af1e44..5f6d07cf25561490e374e2090416715f5c592f02 100644 GIT binary patch delta 57 zcmZ1?v_xowG&`gIWEplFMuW+bK+TI>7Nzvx$L=shL5JsfEFasg=Qvsf{6ushuH@se_@3sgq$EQy0T3 Prf!CPOihzdaZUmN#eycg delta 139 zcmca3az|vtAvVT>$%Y)FlW(x8GZunbqU`F7MPODCkW~z3^#fTYVAdHRs}#)Q7NzGoOKrsenO_sgS{lsffXishA;(se~bqsg$9Ksf=M7Q#r#b PrV56AO!<>faZUmNbGRix diff --git a/target/scala-2.12/classes/include/dctl_busbuff.class b/target/scala-2.12/classes/include/dctl_busbuff.class index fa090c82559a40896649aea7bc7867313bf58a3c..00c7a6616062b6bdf2201c0b365be62baed03479 100644 GIT binary patch delta 3405 zcmYk;X;76_90u_Bl13j;lto698cK(4n!*;-av@3J3fy~H5>NvX1x*22OBO*PWHE&U zv6LbT5(=h~QyMB;gZiN~vi#tJMGTobQ8pmWRPQ<5=b46?Grx15=e+lShk<*?hHb`% zZB7oYG<1r=z**w&m4Uj-Os*o%-$R#AfR{LJ)od~5zet^hs?|k22yhVX0iN8wMmdV` zKzTkG=pw2EjY_fl>T3*Bo+XYOgLI7>v-CA(Rh+&Ktjg3^V^FQW`Wjt?+2kPXf}hiO zi-QaQcQz92t?!&dQuMVbBts?VqIk>KWj2%dR>>B*{oJ)QEZlTx|yBD zb+der21~SDvpq$TMecngoJFt2eNvU7R){6k4(bc)A>|W>8%fl0YJ{2}j$RzqK;58b zM@;tQn~)u&hp{BisXBnwts*f_PMsF#VO?^rIMJ1wKqx=Kx7gWf7?5A`)=vlhK&R1S4U>CRfr_ToCUQ>b?8F6I6QSuQ|cb&nJ9afM9g+X?d4y^AmzFl z&x)pMsPCznThI%k%BYLf)OXN(gW5@TQje6}wqmxlt+;oRx=(p+Lz+M}QFo}PlF(a2 z)l%0ehh+3jR5^7?X*3zLtw=#TpE^fPPz$%Cmrk9c9#Gz?=p|Ck)KApYY3Qw`>Xf?E zFq>mKI%aAwb(ylwK+lgVpw3(6BqlQC2ZJHoON3;qfA_i?sfUz*7Sej^KDGQ^q=Fiz z7QKhGoVrad*nzZ&x^9*HD3!D2WutSInwNvKEb21lnu|1r>ZNAoA>B-MQuaHM#!;uK zC-PsJ)!hP=I^kR0}mh1@A)d5cMauayQaC>K?VM5NRd#3-xM|OxG7-wp(g1 zXY+X<_X?>WDX(IrxzrWv**!=zsY}${5~Rsg59M5nG*PLd6thh)L$Y3}d!Lv1oU$#K zsXU9O+M&w52*aqO)FUeB1N0iGKd3kNA+5DajwWAn>3$>?)DX3>0%<9AlX{^N>2B%= z%2OcCp}wV_sY04TT~r#a!fZ*^=yX#~AL1;5I!jHfK^jYSP>b9)33Y>d{vgs_)HTYZL8g`l%=V4i%ipfs zA>2!+`l&gMNVid4l;dHfo2WCC-4UcQ)MwPxCZv%{1x=XkA10P&begC!%6Js%0qS>Z zMT<=3H}z^==hWBXffjeed8HYjxEn4g1?%ckD%I7k)UT^YX-ccRp;yUQSD!9Nk<%KZ zKiPE5S&X)>Q%W^-cJv(cGtBSQ9JF(qw{~8$Xcx3CT9>w8>(*Me9{s0R8`1gga!Ru%um<%*X=M4q1&bImb)sxgnyKD%yw5XzIrBT`dCq(PckaNwQ{#41 z<92;x0S2oW4W1|d4hYs&VOk`T13h*526>AUHq94Pfy>lcgj(IioggRC6XeC+%apT- z3YO=i!ET~1*r=4KuYSfz<$0pZ7^>@@F;`zRLX!1$BxI+)8bcfO)z9cA%qAz{5cagb zTOL;Yzq5%jAARQ%o}sTL;W;vib`g#y`FaoTE!S0H^0y^prdM>io6Tx<6{Ti5r@Prz zTsF)1Xt2b|HP1_wSmfR>+Etvfcsx)|gbiW^wTt?Mx=Z;+;>LEWi<+PoN1>NYHB(op z`Oy!0@=eImgl+FCE>N>x$Fq!7DfJa)Sc~3DDv$b<`ioi;gB$5oH}$L1+*r)EAr|cx z>MFG$4(VE|mbysIUWZ-?wV(Q$vWrJ=6_rn&RJsw5*`8aEb_Uf$-K0F;Kre-ArLIwr zCZHEX)luJ3j)~}nQe{g0iJ0x7By?6&yQx#u6!m;EZtS3XsoyBi4d`v8j!@UBg(>L8 zDix(*wh<)s)9O8&3qHRSE)VJY3ja``&P`BwH5dJsN0nHHl(Rk8+C(vY&&}E zs0Qj1<&=(|iK?W|DNUwhwlx`O7gC>7)6~)(=w(y=)E&wv6TLL5o%)G-JPW;es!?e$ z3$rfgPtR_ZPln2WTDx=pQq3#p*S zsby~?t)#9~OLieGp)T7bze?q71$pRPq@K#hSuS;+TC^K!26cv-SAcXgb((VAgEW~s zK|N9^Q{O_&)~oh%N<$IuMNu8pG!?cNy%y?EDqtVdM(P%|su*bv^$YbdE~`cT(r5g=I+7sUga>9BGMkN=0p$?H?wVc68dPDav>Z=^^TO zYE6esFU?zEb^@h z`jbtau42-)YU*kzRuWtuJs%fhlE7ZDS2xfBWtOSOQAVuC0s z!X79^9UYN$j%lw^`0OuIl+XiZHE?K$l8^ySR&ywCH0`42P9%fPVD zz_8Eh(P*t(j74XAPFqZ@=hQg^Me=fgaV{ppdvnJu=5xpr>o5A3qakm8vH#zec=}_} zdeI)6pcE)3m2^(Mu*b=Fw8!OmPOZ7jo9{PU)m<;f&2pF2_ye9(_D3uai9pMI&n?DM z!)Nj*Xw7;Nm5}LGZ^Al{j5dD}lo-k0Y*Cmf_p-%=h%<@d-o|L6+`(W?_MDaK9JIYTwMG|8kCDH@XGq|p{229u^H1H^ROl;pfjc6#pt;#0~^En0!OGOCaIoq94Ey+Z03 zb&Gm@C3@LZ8+A=dn}Xd^Q_yatzNGw8k(#L*>N9GBdM*tU<#4)kFs08xFO6!VzM}45jb1!eOP!}Csl}O?s8H(4#BSqEo?e5_Ch7!rn+kgY zJv-G-eMbeYMK7IlQD0LJWT9tKa%5q*3rJk+P+3B4q57%2lrb9{JJj6u=;cry z)O9M@E_)_BRuk$j|0pg~59Z)q2~-_*k<#X(_dHceeL&r#7UW@~n0kl$NlBNF-E#BM z?xen_9)1yN2GvXrQ8QjbFOk|!U7~yn&|6Avr9M=;S%BRZZa}+)I!XOZg>OVJkLsds zP>&R%x0-69u23_J(6dr|l+F}kH{VU@ETgKZkEp+>sLhygP^YM0sEA_p@~LiWgql-= zUZ&EH66|)B$t(vtNmM;G;FZ7dEuH!>7(_!(71Au~H08Su=_=|t^)IzzJ9^#JJu1FhrjBatHm2@!H`5NxHB+~# zMXw>K7v|OpH7P~#V3yFieNa^d4Zlpe;X6;6rOTAA` z--C25^)BU8k2GCrsNNusc_nv~ciZc-Bh^LSrObPgwo;?ivVBMe^&|Cc1Jb?J2(@58 z(pu_UC2b>i+t!HA5Ea&hXJynEREP^{33Y)A6i7EvA5$}%k>*fmsry=FYHY!7r_^2k z-n4IEE{%GN`iDw-6TMDqoQgYu^dR*swe%oT7j=tzrd6i)R_t~|-Q{k^Lzt_fzM%|l zNUNyJROn%(PU>@NPCL?K>O2+DfwVxWsRO&s=tN?t`lxALNY_v&Ay+rTRO%@8H)ZXS zJ)JXBw0kt6{ujUA6Rw?93O+K=N2?L0Bc+~FpE|>PrCWO|bZ*UT&4eaIGpUKtYBVN| L`@OKEq0{~Yu2NVU delta 3343 zcmYM$YfzL`90u@R_+V10YrsND%>)YU*kzRuWtuJs%d*RgTtrO7Cp(K<1U>dik(3+aa_8j(k`f}!X-skzh{D&FlrEk!y zZ_w-XSfqAXj7Mg;PkU6f`_wu8MZ$7laV{#%bDNA>%;%6L+E?^0M?>CxqW`}wareg~ z^}-b$r{pj0E9sni;fRs%aK&W0Pp!GclkYd%)Lkzo%yO5c*aPlU_J=Hw2!G3b_btj& z#b@#-Xw7;N5trsscicL+jCNlUU=3$)w#c)}z3fpz;*2%a(-^bL9SpVv_gSvaew%!w z&KW3z<4sE8qAp%e8ts0fKYnV`PfWK@NzTh;r|0e`KBp$BMJq5@LiJF;QBNnJmq#6= zZc$IJL@$GCrLHMy6R}%TBHH!T*OX5ZQZrRWeL?+8y^xHFQtB-AJM~Nodim6GrGXUe z7Q70b_0(Z%kkY53mrONK-%t;(MlY7Crp{CMsl{oSC{yZ4!)_Byo?U~^Ch7!rn+kae zJqP8YexL%@qL)H7Qr}V!rK4w2DoV$07mzfrLuCoIh3cj5QpOBSY^L6&?oe~rqnAmw zQP-(JhwPagSWT$A{G+%`J)DVm#ZfiXMM|56-iuT@^$~TCT9A#20_r{L7bRT|cFW2^ zyPf)xdh}(asZSJXPC#Xp(;Z>wv)E|`PHKeW7uTGinNltO3f=nT1NF#Pi#S2OkJV^%4KRQ$8P7; zUFS3i-B!$HQ@xZ=1=4itH08Yw=_=|t^$)dTJ9?eeJu0?RrbU(5ZCu^uZl)cWYocyb zi{3!GkNSyPxD)9v>KZk_3h8$03N^PHX{l02HFkS^7m_0CBBifEx{>;fnzb8g7WE-D zeGk&L)ccfIEz%UFfm(w&=8@b@-tBM7j#LMAmoo1~+Cq&{%l07^)X&uObx8M8L)3!( zNUN#um9+KPZCgD$15`)@o|RBvQ9+GJ3#ki~zd*Wy`jnd4gfx>nOFhsmQ)4rBJEiXO z_ojUdbIH^@)ZbM6+vv4Z6I9Frqz9={YUx3wjnpmbxfYo^TCm#DH^-$9~kglOlLXDjWlc=NAUzDv& z_H@p0;c{z4{V#sKD^xqG6nJEwmu5_ujug8~J?aeYmTu`T(+z88YeqCdno&)dW=vz! L41W-EG$Vxi}jEPh<~P delta 69 zcmeAc?iSuq&d#VgS)W66axc3&qZXKT3dqt1v)DP*8FhfHW1<=iT#T9wx{O*3Zj9Ot PS&TXieT*8Dxi}jEI}Q$* diff --git a/target/scala-2.12/classes/include/dec_dbg.class b/target/scala-2.12/classes/include/dec_dbg.class index b165e855c7bdf92eb63ad1f5d55c2d7c1a03b183..588d5ca20e7fcba7d231c1aec14dd449c9a9aced 100644 GIT binary patch delta 41 vcmX@gb(Cv^GYg~EgctCJNB|D?jgctCJNB|D@3X=7>WFNyjztuUH6^l5tnuMqdZyW3pAqFRc2QBa z51rkKnlE;9qYK2^5^a-7f~W3dmVa;ZUXW0yImD4nm|qbJu*9j=sJB|=oBLR+YV$(XGu8TSUM>y&9Z z(zR4Cb%mO_0=-pK8}&2gz7oAys-8NdbbBRcTbhD)HFc7@OTD}by-n0%>IOAG6}?=l zkNTDJNkcD{YF9dyhS@yQ(TSrPsI!!F26`dXW@?D~k6M(88#d}=>L#@y3%xw0rYy`h z#$;ADI%!k~H9~o=MlYUfq`swGa?lH$x@?CL@@_z$Q&8PaQ z->BJZ(MzW~sSA`b7rg{(Cv}dRnkRb!d6;dB+RNEKr|wfh`FLsxb(FeIJ+}_Mb<_Yg zPCdOIy$q_0x~QaWz-);d(B4ITN4dUc(~H#Sz0hH5$|jsGr#_(WQ*k!*dZ>S> z$YP{j)JXEv&(8H`HFv z7Q6-bc2j>)LA6L5sLRyCtw^^~7pVo?kXBJYQqR;OwJUYkVYZoXBPpc5qP*Tgnopgi zrfo;Mn)*a(xZb2s-62z{RO%4rRF8BSHQyei>WizjJ-%VQeRNUZlt+NP2HI7@qI|LsH2o~57HFsL#VkI zVWN`!sop14tbPuU_4;ZhO0)WWHM>%pP^nUfP?^$*P`QwY?!G@mylmF}RVkk^PKl}YL8Yvm(yWQBLH$4)QGReOYRuH>oWp&d@ynUtInQ%m{@j_n92#{vH0m%o zu~f6_w?n4uPXvVvb(%eOThKhAz+jVp#;#{{$6$YT7N=GZ{b8`1J`_CJle@)_oM(mj zh@E_9Z%Cw4x>#dFLd`->VP#^i4zr4NEUZ+lN#Si`jScnC)6K5>j0j(`i-@Rw z1Q$O*DP{& zm#8GUmiy=}QF0#}XVfo5dD}HD8nRH^sIRFhG3W(SmDCC9F7-+*ZrG^9)OE@yZn7u; z3prbleQ(sSP@eI4Rua`p{Y1GWpch4Lr@o;cUxwZis){;E{i`%P5wjI1;@%*2gEB2g znoIRkSE-pR&|5{dQ9o0zE76Ol>Z!9zcUEGyrAcU4Q>UnV)T^t|TTdOKZc_7;(aWRy zs9!0s6!em*cBRuPn9VH}ofxWtI!8ICp%+ALq=u;fs72|xQ9^x8-J%v`pqH=Il!4jC zn9Q=GlR|Y+Bb0k4da+a^^)2O;gV)@PBQf|^yi`D17&=G3NdYmn%KA;{@F(v5rQ2$Wj zrAWJ|Thx*=q%G7nyX1GNoUO4OovYN#8*o-fU8a2BMp{i>pq_sR=?3aN<@GL78+C?y zxkXBJYQqR>PEm!KU!)!CRA}ON2qCDP1T0otm zrfox-NqwR;TyN5+ZkMT4GIf}8s7Jbt8n8>wChtWxpwmrFP@#=TJE$Afn>&!|)bEu4 zPNenJFVss-NHMUINum-J>k+=a!KIz~D6AWfn^gqnL1 z#w*F6>U~0)>gVuSueX+^G^@{B%T`Je%2DbN%2gT>$`f+aT@R#*m(6y-Cf0GauIR7# kv>IHsOoOMEWtgXB8y0FghS#-RL%5b_NYJcDwE>gk{|r5?K>z>% diff --git a/target/scala-2.12/classes/include/dec_mem_ctrl.class b/target/scala-2.12/classes/include/dec_mem_ctrl.class index a09da399bed84530691d6f0cdb7f713536b8d555..1e5cc3fcbd9d65d625d8ca5f5d3e323d323835dd 100644 GIT binary patch delta 3522 zcmYk;drXyO90%~{B{qd>C0E^2Ax-2U7S)y_%}`7MxgBnr+>wx5a=0B19PS{N+#fMO zH1WnoLlm*vydYK+!;D%(ajQp%> zeTjaGj>iT#@B%+yA?whE+~l`h$YgZjPX1nIWkXK>c6{7_rs2p3H`{Xe&9irOX`kIrW_Ix08ja0CC9~m|?{{r3` z<}J=lMptebuAVtZ*zb82R(o^k(4GwM`o@Tp)#3_L~(NG&S2H7Q2 zF9fQCzJlg%r``sr9J&NOfmSD}H{z3Mwtl%+KY71H?(fo5Q=v}i7sxr8dNI&`=q6;p zgL+!19vXqHQq-PD3e8p__v&ne&@|+kN>9~8XQ4@GWg7L;pf2bx^kO>oVxe~EmXwk~ zvxR0*y8*fmS-(f=MyL|H4E+nO*-1C@p#kU*=;ci6r9<6PqnR|@5*>Bopaal2xP*>_Zse0K+1-`gccN1nhsrpY>bp9 zL7$qX6~6{1qlU*6QRg&dSxje1(#6o2=o`^TS{p=Gy$zEqqG_NRcc;2%~n@V z9TW6=1)WtxiZ=(DQpKO@z)tR?U<~ zL8l;#eUyenT~ed_Xtux)snY>Hf;P5L+6Fy<-fE?kL-(N7ZIsqPKSHnWr?d*XDW$a2 zY{l)=8HJV}pff#m4O)1R(oEX8S?z)!95c>0Tu?25Gt|ErPy* zmUL5^2Mt3n^iaAJ8j@1KrrVuZu4KzE-r5r`N{&>$P_ER7P@a_4Nf$-WJx+Ql`Ep+& z_6Dgzp#rICp+YIok6jd_lwPPv>a0+))TB^})XH8LrBo_Ss7$I$s9eaF-|3AN@7DTL zSzuKlik_mmAfX2Y_X8_QunESE*IJn^Gv4J@B^GXoo91?)B}WRI9pd6pF^%UH3p amX#=5SgB%UWlA$ES9+PQKkQ7-oc{q1+6J-! delta 3522 zcmYk;c~I1490u_BN6aWxQ*!D|Dx`@lVo}YcNMk6bfLzO^$+axka^J9qf*exG{fYsi zi5G{4C}K6^fmn?gX4Et&&QzPJ{gD!3&16!&znA?!!$0qQ-uHRl-+pIj7xwCu#nmZ` zKE0n3!(#&+_;x>EA?whE+~l`h$W-FMo&3Gb%7dKz?fAI=Ov8~6Znov_n`iIJX6@A5 zu>p?UE@0+W;^fmD`B(rYZh`*dtSGQZtP_FpV$}u}igh@sMXaV0M}9+V!}kQci`{3z zm9x&0L)^rUhh&S@Qd=Na=LkDqr*%cgQ^-2h$DHUx)z_R1wdVt&YovnB`^d1F`4{lk zFmG{YDsknO;p&-lggsvu?qXIcbRPQKEcMxHJ1>ITeb56)6G>?@bQCf{i?&d28`J`Q z57}&`UJz6R4NFaKrP~N*g(jhuY1B)Dx}dwzi|N#hh1#K8Qc4ER z7Melr2Ix9uok{6Ns1mvi{R^$hq8r7~0Q3j+ayIqSp>CK85%BLGfsg8V_Z3@XN1=PuadZ7Ez(n9L#po7qDXnqm(!l5SU z2J}oZ^?aprifOhhlr$Ns@}^mK+-RKn$DrZYjWd7lHQZ@CDG&M*TJSEV>Ch#}ri9W& z=u@+_;%i_k(eRiZ)Hw}V?xeFws0W&cf=j7)1o{i|Eu*v@nt;~rqO=+MRcc;2%~n@V z9TW6=1)WtxA0G$;<*Pw+5Db0qiKn@>KYJko|&mE#P9vXn=cBrXG2hG+i_v$B4IZXG$ zpiby96mW!khoC9w?W2^oLcc+4k5SqL-Gx>iS5w__n(YUc^|LYY!sLRmt#{7!GIc(>M{ z$`$K5b?tZUyQgf3VKyv|xiKB{Veu@Q=~*F5U=1vhb+aTk#FE)ttEKBKSG5uj@^5^^yrC{px diff --git a/target/scala-2.12/classes/include/dec_pkt_t.class b/target/scala-2.12/classes/include/dec_pkt_t.class index 665f84d7ba6c43c7ce541c79103c6beabe9c21a1..4b0db307d1767d8b8efa6054e95db5b388d37ab1 100644 GIT binary patch delta 653 zcmW;9PizZd9LDkA?}>{EHrluCnk+G!cbH9!Ve6*Y+OFHWuI(yuK*T{pCULPKk@&M- zB*vRK2;t!1Uu4N9b`r+HVFU*W*};W~6EYWx@pw<4@3)eyBq#nZcVhwLg4NbNr-f>J zC1~6wZYQ0kC+XrE>mJh-ou}t$%oz8Sj?h2!K5buN-B)^oHinFwq6g^@dXu)Sv~G?b zp^>n0cW9Y@rjFJJtb0TE)1?vPuG1|2Kr7S)t$RU>RBMeJr(N_FJw>aGb<;FWf6?5d6WZs0b;N4F zuLGAUeQ1+KIy2vQzHer9bS`?VOdTsL9cwD+wvZ?zXwd~)1eJ?6Sp-2B z-2|BjT0}*Q7G)5Ec3DN)riB%>2)ZoVWYMaNt03*+tbYIhNOhz-u~4f?S5Aa3th1W( zwTBh>y2=WD&9IEG#R;nstD>?0i~O{&=d6scf2^#po}|@!U#D3OzNT0?U%yz5zS>h( zn|vK-<$c{_6?}bV6@3)~t0iBD0_zrPjk`%Jb;f<5XQ&CSdrbGzKXjCKCX9PcPtqD= z-8kJ&ztKyylr-)IJwoT{ZQ2`I_lXYCIAz=;x{v;*W3(f-?kzn*mj=e&r#tB^9j3*! zbua1Rv>gkLyT$FJAL&^dWvqKb2k0EVM$5*yH*}CL$y)b-?x5f4W!fB>$?0q!=Mz$c zqy$Jw4uP~Hlr9*lAd+o}WjE4t02w)otPG-FhR`4vkdrHDlQD?A8-=nHuuvvd#i_T%I&Lc57k=w8T0S_&s AM*si- diff --git a/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class b/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class index e239f8e058e13f3b796051998d1fc281a1c1c492..eed2f3127e3390e354a96b081d7fb7c3788ca285 100644 GIT binary patch delta 878 zcmW;9TTG5|0LSs?|9hU-MaW_Epf{cC|JJ)1FLPnZ;i8elg%P?ia#%BRxUk8g%_ix> zR)4y%30>HPX4+CAbVBGz=t$^%(CO`rpXciH{U*mH$32R+t0rGl9kom4KR0(FF%>IpqW zhiN8V9xPQ0ji=sWrn*n}&<>hTgF~dMrLlCb(^R+UR@z8Y=wc~Fw^}d5MUSesFHnl# zYgHAi&#KuDDf+F7V*R%2GHbx964szqB2skcU`<%n$(mI2oZ({1`U6fWrvF#YZD*=2F;DYAzUG4h&4s60B%Wz8c&^2xP`ij1 zS~^~8S$L%tqDZSjvDStXZ33mj6J;U*uf;075m9(6_M%*z!aI?K_u>XVh-_4dB26`z$7nzq8d*)~L$eOF=qA4DVfd~` zpjF?FANpbZ)D!Sazlt_J6YY8~I`ndM>dolV2hnZJK#$>tUSlcxj1A~FqVd}}f&t?K x28}cf8Fw*k6kx=tfZJ%rs9|?w%;te{n-3;zE=<}YF=dOvv@ITaIZ>`c@ekg)Fu4E# delta 878 zcmW;9T};hk0LStF^ZWmgizu7TAD!y-dLC*sj?IN7n~TO_E{wyvFv_eMWiD*WwAoZ# z*y_QBP0H5W>Alm-DTLk-dPC?9p|=Ycs0$bP?Ya7VzlE8FnTmsG7*L8^1psR@0sB4hbq-$lA6wSK!umZZS zvRZU?vs!iiW3}l@c1h8$>mnTlLTkmt7n$RVjBT zouWB3Jla<6^a%Y;Z_=#^QjO3o8Wv-#8oH0p(?Xiyma31YQ^eZp9^FMJ=_R^BO4UJq zbeSr;EzVZM^c)S{C{-Qx(nVT8WxTC==}9U!NmWKu=rqlx&IDTp=~22wZ&6R8RHHPT zu6En1mhPtu^cr<1N!3p?s44A0X;P6RuiOYhg%O2H!-Fa#71c%>{6-dPj4P-$Zllid zqu%I3gE5LmV-`)uA2f?F1Vk)a#CEg_FWSU0w2SiyihOj4JLnYkcp$p*P>kV`SVWij zi^o`lCvf8_cAy&v(1UdJ;zAz!a2@?9!80`DIqL<+F@PUDPM6%}e7aa6QFa>;=?ZdjHJE}e2$WZ1O=hFus|1vjil5K&8Et^($U zp`vUmL%E#OQM9zprA~WlR#NGyb6iTT6WI6N`+MKhKi~7*`@EO$!XLx5cUjxJtOu*- zig+0k-bc2~ohd(V4Upk6{?Zl}Wb9Uk1F2QX=Z2-Q^E4Qx!+WYIZgd{z;6nqD~1&&PC-3{&se*p)l=$;5}2fqXRrs^IAR)Xh1|1{lafUCii;C(PO zUC%88-vw`jqcU{Q1{=U%!66HEcY!;=@4(+T9xEwqT z{t1R;>$x1T5&R8&Do6Jua3^>X49wL%29)3hut%Qmv%odr`=H3zeG<3=JOcg&jxNx1 zxnL7`4IH{i_hhgZyae`Nta~iD3H%J~S*ZJLupImVv=-?;87u~mf_K2Dm*}}Xuo=7# z+L!8{0`3AYg9Dc79tUm)KL;OMuKOHtEqEI2wnFzQ;7afqco%%8SkL7v+GKOF{y=m{ zu~L6DJ7g4FJ=;HQb6=&oTDIG4(_W*xh3$8?$*)uOvURYH_2_E;6LEPQ@-o&A8M2Db zm9l-!<|v`MlI;T9;8LnZY#*^bv6^Zw+etQC8PyDBm1T6do@=PM*xK0q%Be13YbNuq zr5MS!m+f!1IqPU{C)+Kysq3lMC~IF&SDW+(l}fg&%5GLTN*Q*#=cmEoA!;X5P(wXHF%}w6pd0(q1~-F}5C(Y9gDD?V(Ln=d(4j-Diu~ zOmlnK?kO8sMR(g#MKd?qUaY3QYPRca6Kkkeu>H*T>=vqP*)Fn;e2eNTwlCR&wwl$s zmF{*IKom3OpTG<|~r5dNqQ%iU2;^N#z zGrQUDvdwy%>UOppY%kPNtzx^z7P_12Mz){W#_XY5uI$hry4#4oR6J~7u-WUWE@wN- z_T)aQi`Y)H1@5QnW;@Q-tAT1N+Yx0yHqhPT8)@bc+XGFs7t7Yb*2xy$OmlT?ca*t2 z!E#1Rko5EQmZdGhB2l{HZ1Pl#UARp19vtkuF^aLq&#K`;7HMWj74VR5tvOU1TZCG|a86-mq+CR}ITi?;O%POyo*uYpBRm zrLNU3@|9gNtiZ4UIlz~ozI?me9+n&a=b}yR``m5!tkLn7ULwIVMkHF|gv(MOk}O`4 zY&jxQEFB_M_=_|#LZl0)$Pk5Mq1Yla#d{)4ToG<-H<4`}DsrsTM6NYc`~Da#1v5wlt<%Zrct!ArhGN_R!2*xbZW*&Wi^4_bJ*|qpSz!PzTb224`$$QTZg%= z!+fM7Rz%APdoS4-JKa!}>vtW&MmIrEKcyK}p7RsDwe35I@; zFXlQ}?nR2q!ljp+{-SzaUJYd*L?SQ zmHEQtIrk*3a5>tee+rN4dOe}C#bXKRE;TF(dzn-%b(89!j9x0WllqPdor#{4Dy6=p zo=j1_h!o6Lq}OW7Q&c-Ob{6isoNA@+QNvTwTSy(CZczi$&`YCsQQvEcbj%i?j&>P! zj(W!Z zT`OlHW;=t#zX+A_Q~`CA`h$vCj1xQCyWr8tpA9inb)J)4W!=H#MXOE<@_3wosR-9(m|R zQzg_VlsO;02~;6=S#sV#p=!%lvO5BwbZ{<>|5wnQxB-AZzJ77 z{YFiA2dSUBMUD1#rs`Gd^;zY$z}hM!*5F(*^(|#BLb{r|NDVATnooUBJ+~HV7Im5m zU59jmR{1*2)?+;qFV#wQDM6Y{H9-Ci2;-^!)IU_rM)Y=5_o*qHkZ#v%+l0}g-bGSQ z-PF2QW|gnKr&6Vj)KzNaW~4>bH&l2j(n9J2HJ}V>9`#v3YBu%ECFSU}Q6YZpWl$%m z?hhxqbPe@2HDsqs9Xm1GdA(M@!T!5&ZW(o!>RX9)F?EUxu0lGWI!<-ljWmsFrXH_G z>e2F5W3~<^jy>q?qaIQ-K0sPY-KAdNi*y@xn~L0rw3PaZ8dZa|M60O=vkl*m#7AAG zEVW1rsB_c{2ax7cpHg85kuIW6Qa$UC&ZCZL-KfKCsrBeIQI8$Mo|~$p+9`VjdV8tA zw7kA>IjwPsh>ckNbiwIk*L=##@eNI*N|IlSd&F~v@#7PY1JA^*1BnErhew2=Aj}*I+`QJES>Ca zw#al(FL~Yg%x(;k{aVu0fBx2BxtS8J#$JoJH7F=C+SF6Tm_~_MlSkN0OGTW?FYKmc z!eP24oT96U7sEw@aEL^aCtPBOaEp(GM_d<4<{*)5eo@RcPZcTVOfkz`BvQ?_BF+4T LaqHtpOS=3IYNi{r diff --git a/target/scala-2.12/classes/include/dest_pkt_t.class b/target/scala-2.12/classes/include/dest_pkt_t.class index bc468020989dc12c8f6191909d87e60dbd03e496..b783e7e18af6d4578110c2635e6a344904046e32 100644 GIT binary patch delta 125 zcmew^{9Sm%Ha5n)lMUHLC!b+cXS@eyak8s3-UqU57$1Q7%|QM`FzW!2^%%_h3uHY3 zv#dDO8J~h#Wgzj87P*F+OEj&3I>W H7H2O2FsvyT delta 125 zcmew^{9Sm%Ha5mnlMUHLC!b+cXFLsNak8s3o&mCK7|(+F%|QM+FzW!2bpg!!3uIjc zv#dDO883lZZo??(=Jk4Olc!t4^@hn3W<2i;r#tRHhj29WEFyx;j730J7H>WS7gHgF98(d45mWx;YpnSI?b-^= delta 41 vcmX@gbChR;A}eFuyx;jPXEL7HTA~2tcQ=M@!m}L)SEdjG?IN!<6 mW8h+#&!ES!fFX!sAwxF9B8C=*#SF_CmN1-Vm^Znds~Z54IVBjl7$q5$86_rvXGsD8aE%8Y delta 27 jcmcb~b(3quBo;=t$&*>4IawLF7}*$<8CfTPXGsD8Z6gNJ diff --git a/target/scala-2.12/classes/include/dma_lsc_ctl.class b/target/scala-2.12/classes/include/dma_lsc_ctl.class index df6b371e01b0cc1b473e41ab26bb7c8c622f6395..97ec79e76444fca78171640ea23bbdf1ae5b6060 100644 GIT binary patch delta 83 zcmaDW{8o5F6+7dM$@v_jlP9pNGtLCF&H`Dpz$`8fb;j9XmOGF&2gtfFIh}!vVFrUT b!%PNuhFJ_*46_-U8Rjr7XP7=YowE%9T5}mJ delta 83 zcmaDW{8o5F6+2_=xx0Ut;V4RPH0wBQ|~$4=b65o`JMAT=j9I<=3WLz9R^1o z`f7u;Vo?{gL0`v%R_m+H>?UppyNKjqAN#H)*pKJXSctQT5An61%U#d^cK-T#U67mb z4-K=cE!3pC?m{!kX9Sp1_0?+1x93lXg{!^05MgqbiLfSpwVB;TNrbaF6+U0z{TN=s zGx-&)CU-F$k!aWI$YfnZF)pG%a&j(t*GWu|lHbR8kf(@=^0qf>qvQ-1qoVb7cC=hG zqvaEAW)CqC9jN3h7RJb%Lou!*GiLIptLU*y-j~UfYmjWDTBs|O`-|wsQU|Hesp+xk zg;15$N7TQRUmR|jm8@}?ZGy=&@#t)$da3Kwyae=8s8;G5YSvox;;4G+3+kan^g@-g z6EWKWlKOS1_)~?{Y3dHO=q23PPQ6XtpuESxOPW%SZ1EA>4!dlPzVsYdD&HDfb+;Z%*1Z8K(@ zvIU(LR5A4)b&p!Q6*sb}ak4p5|zp_G23M(Gq<4=LG7hJp{8y} zFOafO?^AzJ%XZ*K4t0XMN%>~UUQ8Bd>r{LBw{VT}%*M0UQHQBv$}tDMNNOMTDRo~i zdMl|C>MZrA(i1x|TkcNW>!WT_#yq5(>~ayEd6RDpMsY81^3BaCOs_&M)NSg8e58k{ zG0Lw1=>h5oYMB{nwOwoUpRLVo6blQHlu^T!_b#M`)MwP(BBZ(0$CO7g(oE_c$*STI|12|6}vYAMbVs9x$HD!L54PU?3mv>fSC>Q`#zZlsOW4JF44%vM){&Iq-% z5@%J^6>7mAq@~nl>ZvNEW@?anyc%f^b%B~yBh$bd%=V$$%U9QNFYcvNr>O_`Ax%=s zt}}{0YRZ0@%CmT?hx(g}sztAZx=V%BO{Q`-`K)pK-Y5bO;9diDoqGN?q_xyFYRN&Q zd#JCe`SnOks7sWWKw6+=6_{;K1Cng&JmubqbSw1%HS-YCH0l)fz+t58sS}h#6Vf=U zTWP2Xvqd(eW2Np;!AFoDp>9ztUPmgZQR=y)NcU4$sl_cwE2*!Pv{uY!X+>v)NViaDsTmzeQ>l~Gv`(2W>cniv)n5MQX>Z_OEY(H*MMb=cUOP2G z1-*r|nYyWDGy95wE+5UJK8zQ2d21y~XLOZ{kuE>2Ow8$CrIoAGf^KhZx6(;n6-vM9 zs?_By7WC-8&wpS)$gsL0`v=tMt`j^Afj0Jw!_A9Ote%G>GTWXqdZ52n%qY%U$>Xc1!j1TBDa( z8Xnc9>8ssTacl>@+fz4GIFlI`!TYT zXYwo9P2OTCD#@u;(J8tH<2*!P^u%29uA7(|BfpO^qpygI@pm?AV&n`LVq*1mW~^Mz zvGR!yn~&&^4N(dZ^W)^r!8lK0j+?mYDY~7K_hs_LY9t$}X6iEK{Q`Pxr~}mJ)YLWT zg;7=1N7TPmP&{tflL@j;`)lOZZ9xb)33E1z2P+&Vt!G)L#BAT%~-ic-A`V5H&=(=A#!)?WI1Y?kPZT z1yxR+q5f2Qd@E)v*ou3-)J-a|5a}kTJVZy~#2Z7PxLY{!<`yVSFGJ1LE$aCqqz9={ zDySIge(DEmi4AGBQ>*o#t-}^5=9eI;poS>_ZAeR~>rkrq%NQ$E{~nyIstTN%7#^((dFRiq8nbtTtI%vM{8&M>vO z3TL~h%hbG`NOw?|s3&(JwNV4qqt!_Bsq@r~-7*c?joCg_d->|R?!mnb>J)YVUZlxN z*4jYPOHJA*Q+bv^byI&+F*WG5Q+KGa+KE)oCZ9Ft+y{z~{kT_8U8A0R4QUN^m0ENF z=}zivYHl6Ua_S=GCy*8^*#%~sRgc6pIo;pssG$M_s zx|9YRFtkzP3e&7f)31fOzq`wp7sXrt)V)pzo@7;(QBi| zDdSs6o2VN~4qJc-?wq4#s}JL)o&K6x>9npKG29uX<%(HdE44gzTHNKYS(HxbvMT+i zD_@tpnAffU<5Ab+DcZY}CGxebcMEzfnqQW|P0Kbc)69lUEyqx;C6bln0*JK%%Xf8%h1};V}1{Frm$&D;g0AUaXdjJ3c delta 29 lcmcc3d7E>C6blo>_sKFW(OeAQ7`Pa|GpI0po7~6}1ptg-2`c~q diff --git a/target/scala-2.12/classes/include/gpr_exu.class b/target/scala-2.12/classes/include/gpr_exu.class index 600b6535289887d45e79369bd0ea2c5b8db9d7b5..b7ee6b2f2fedb729067b14c5fb6531afeb61e447 100644 GIT binary patch delta 41 wcmbQnH;r$@C054h$pUPmlV7l^GsXZ}UA$2YT#V5SdWo=4Gw3l!Fa$D&P2S6v4*=c?3WNXv delta 37 tcmZ3(w}x-SOIAjg$*)*#7+oi;vvu-1GjK7wFz7M5G6XU@Pu|Ox4*=Hb3K9SS diff --git a/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class index 501f234f00f47d2ebbd8d3a8e842cb3e47bfb65a..17d2546d8917d6555b7f37a12b56abeb84346460 100644 GIT binary patch delta 139 zcmaDR@=RpI88*fVlMk|sPJYCu&Nvawl4n+;kjFHYp^0f4!!)Mp R46B%CFzjRMpL~UL5&*`UEV%#x delta 139 zcmaDR@=RpI88*h+$p_g*CqH6SXRHIW%puTAgck)nh9hz0$DbUO<=w-hdN_3 zm=yqIwSZZ@KvpZ5b&BJmW(@-uQ!RrWQyqg5Q$2$lQv*X3QzJtjQxiiIQ!~RfrWS@( POsx$2m}(|p;hY2jbT}(L diff --git a/target/scala-2.12/classes/include/ic_mem.class b/target/scala-2.12/classes/include/ic_mem.class index 42041ad3cba5fac74f90cd55445cfca6d985f522..28187f79b10f11b7e1f7813780b8771eb75162f8 100644 GIT binary patch delta 3301 zcmX|>c~F&A7>CdIsj1bB3j#VRYKy=Po6*SBY!Wj|;lhOr;sP4(TPdiZ1&Fw%;sQr- zqY`n)Sk$O7w`s93n{q)G6}Sk9lS_@2W;)aNo%4I&f6nuq^StMB?!eIW&}@2WmX?n( zDy7TmBYzn)T6#*nLqph_ia)GtRMlH5p?JYe~`i+4y*d2iHF;JCqxBZjuyIs~gGTL5qqu;bvPihZ& zJ32&Jpp1>NZ~4gF7=Oi!V5hNq9|o=k&w_1Ybsr9neb)OFI z2J69|6LcRB=7E>M&J%Tag6qH^!M1U_hk)teH{e6?wRk<31eSoe!N5tn&j1U-2C&y; z-6w!s!OLKm_jL~k*MmQS?Gkh!0WJeifd7Jnrs%naU@3S9bWGKKCb$RmfPT|-p9pRP zE5WYQb&mkEzzXoG8M?m>W`HNbN8sx-_1q$`47>}zJWKak;9js1>^)oeIB+|71@xMu zy9?X^o&(#@)qNzm96Sa72M(U6=N5xUz=>86v37!TYgF_PaTrzkR`~&Qtr28CjKiCBJU8wsca3@#|dN0yF3fu&q2Rkm- zeH6F?JOe%fhbHT}6z~}MC-_Q=?sLHdU^Dpq65S_*`Ctv`vs8CCxLMI#o?mMJAM~U; zWS@`h|H-y3WIM~&<72Ax*iN%`O{F@W?Q2*RK6O$W&6KgVO{cS1wnJ=B*j&qKu8{2? zw$T|>^V#mPjaW`Km#tM;O;lI2)vyI^rn-#nBHK&ZRF^0# z$fmdXK8RTG)o{pqj;2&o*!;)m3cO%8Yz^TY5gtTwr_gQ#wmwJIB`RGpY;N zzGL(Goa$`06KtJ!QJuo}C0mCAyACLzw-u|s{g-F#rhCzB``I3`ISXlS7u$WdQG2Lv zXS>bz)?TVPY|U(g_t`aJAHA(k?d`V>*iZLXvQ@D;4p2>F`;F~|gH)5*D%g4+qB@`L zTQ=_^yLwUs<;RkCcXw`?r(H>#EOKJ0JQD2ubKR>r%#%lyMZ##MDz zXPsSB_S_f##&u=mEUQzNYgxUris0J-c$9@%)~IZ)WjAD5@i3!F?c0?28_mjw zTh^j1&9a-yj$78M?15#sEc22BOD9|3C8spWTHBS`>yoloqxNXR5kE7gQgjtp#2`^6 z;zYH`6g6U}s1r!Gj1$82}p}qZrF@QrDPMBEeaRz<+8W{hDwM_3d&Z1hzp@C z!VzVw1jRkzicw>3A&V?7ET;Ac3aL4hOOBOhI@39a`#%31e&;;T`R>aOH=pP?pXhZB zbG1fpHaYY2bLR*}T3xxf|74*;i!&b|FqUue_q6X?{Ac2PP%iw8Xk-Qq_T}zf)fhaV zWRf?{rf9Xg@HUftg+hx9HwMc4W|Irg2=o_f4@|c2=LgAsbx@L6CzwmbT4*uy>t-*Z z7cHCAK18gyEo;OY9-JsvTbLv74<4M-lY3j`G?CWX_N2ioU+a<8EY{f}axD&dPptiE ziIz#&`;14=&eY)kpR^~cOlOx z*|S8^YIFjEpmWf$XzI;^)WAExQg0zt0$qm2#858?%7xmL9>&mYAACmbOz0%^6nZC?dg~w?bRT+s z8TFPy)zARs9!I?hs8s3aIGSzja_X3&Jg6NSzJhwQp$*U}=s#%sO1hB<9fcl1UaP1V zr&PF#X8R4v#LuY{36()tAjj3zvq1S!2jsAZdLKer&}rxyG$UT#h>oY(>eXI;FZ>Bj zNuZ}LhxS7^A&<4xi-O9btB}(=>IFjuP$x7ZQTC=L(rg>mUe0y~dJg#{(NmM5W6(qB zjb!SrfDS;npqEpqw+O0$t|@7$G@CV*+S~1NzJeS9EVF z^aJ!l4yBP$ol<ifMAoL6h+D5%9=x^wg+`&}NCZBcRzBh8eJi507`W^Dg zr!)_`0lis3=@#f3mt(8%4CE{48`94cixwUTD5QG5B7r&ZCt z5NJR26f*6h-frj-^wC~QOQE~a`_+^dLARjk`(zruk7nyrdpX5zYF2VTV$fQYB7|DSe*xoo z#St&0BJDs>B;R~lJk&@Lzi2whal5xT@}H8Zs?wI5Pz z(7Kg;g?g0Ig?g2a*BW?Tm@|JY-WD8oqmR1jp^a<| zJImf?O)P>nvnsHpIuVlS?5xcB6uwV3xtg*iL*!JQ71OIH_8vppcUNjAnglN;GZC*NmNXPgUW$*`+4&I7X|fvovJmJQjF{#zxG~LVh+pcUNjApL$&Kuylkc;sGj@SlGVJP%-C$NEkktcZ*)aBk`ImwGJ}^swL!Gf7 z%<=`YCV*L8K-NSs>o~_l%?<`GrcMSqrY;5}rfvo|rXGeUre20Trap!yrhbNLOcNMZ PF->IH$J8GIV7cQk<(85|KoCJB5s0Hg;1Q*Q z1q2DaM#BcAnUvCOkQ-}8(;6x!wLc0wtY*~S_i4Z1>7Qpl&-490`~G%jXLrrBR_0l& z<6VBbVbLDAM110BP!(i)Sh)DRs+#k67X=nMi+=wX7A|L%FI3No#;BwZ$NRWqhAxjKq~P;Jf`lcQ)3 z)!yS!XuP%-xe328ZLf=R6y;%hi_TEDDX(y(h15xEj#?3cUIx`e%~CFr=p|4s)Fq3w zccIM|8HIK|HA-1WBMqP`s3GbOwfa@u*iL;+-K18=pqEMYN=?RKw#Q=8Nu*k-%al_b zdQnsZHAdYZk6s{ENqt7$rM%bUMv+v`1+Ndj(bBfmUO~GhF z?zIoz1Z9(o*D_L7)LBZGhMo_#gBqazpq|-;8(XL&)O9J_bj+5Lj&?hBm0I>X(imzl zHAyXc1HB-snmR{WZAR}Us)RZvHM1GBJ)41c4t12eLFqHmOQkxfZ>a~f(2J#-s441! zZ1jSu8mSZ6m~Gw`bY7-*QiIejYE=$yZQs=4p`RMslr4~7e!F=t9VW`MmEGm#+_o|YplhlH3NaLxaP-7v&NUEFqn+o2J zUK@3j@+(5xY?1a$s*UDTjHH43k$PbV(pu^&Y9|T8MD=y(V3xEwc)Iax=eYrBi%(! zQ%`mvEuu!KM-Cv(qs~!FJGIoe6SI9P_u41VwhQ-Csea1(Akq!gacW+-mTLdhqg7py z|As}kUN<5&p=wmh=0m-1Ov3d%N7b|{dr{Prpg!YLPoBC4 z_o{2(>E1M*+puD%Tu{7}5hYR?RWg+^rBWGJ%*uo^q)aNa%9QRtWm@N<4EKc`4qxyu Dxe+`& delta 3415 zcmYk;X;76_90u_BMazlAWD~KPk`|T*rLvk3DN2@mFZ&XUDZ7*`0)hx4i9jqB0!Nez zE+9zYHWD^$%2JwrP|>tzG_9dxQu|QYVl|`ozNh;<)0Z>9bDrni_kU;Z+6 zyd%g-!~_|olC)JdL`g3anTB9ZLxv)4^)jYtt1xcXR%=s>wyFjvu`tw5oHluCyMIiT z|2yjqeoEV249?Y7|BymGiFOcEA^P+FyXURR6uR1ybcgzAnhp(@tD^`E)90KHbrdaO z`g@!VOVHP1ci|td@6~8WQ4#KH(FApy@{T}SL>;AOsb!JqWm3J=4CNAqULw^>U9w1j z7y4{b(P%eNXDI6!q=8f=HA&r}R=$QCTc}T{o7D1H^s=Zvsq?Xz?Xfs?lBhQ7GUXJH zUNqH6ou%$iKre`@qCTbWQa)>NqgbkQ4QBg|iP!7sWK;X8pQy*zqL)mWsc)#o>(Gm# zny4viej<7Xsk}tY_8F3{Dd?q8?bH>@IaTlZrD8N8 z_xcC#9A%S+*D_Mo)Co#WN6(kqN)1teP|vK#jg8bn>bjI|24+jmK)ZvwN-cQe+#&t{^XOC6$aP_9|%rBR*Kx735#=*3aZ)R)u) zIp_sbwNm{#m~GBRbY7;mQ6tnXYDF$?{v*rw&qgsmKcS_ECRHEv>|C=1O#Csnu0D+e6); zR=th1f%<`Zz8YyQb%k19gLDV=73Ef|rxCT7?X29F*L#Sib$X(!fI3Ajc?W4WH9^_G zi*!9TOwE4}X(IJ8bx%FgIE(bz^f~S@iP(uwH+73LHXv=Iex+V*M7o>0PWdz;-AR2< zJtvUXNc9WMwrm%Ya_S=G+KjY>Izv6W8|fzMbIN%S(kyD6vTH$_P7O&-w_vt)@1xUC z&HVspvDAL*HWmIMdR^3?l%W-AEAY9|T8MD=!(V3=JwBxLrx=eX?Al*(~ zpq}hRT1=g$9@&dDpE^k`?$T4gF3dJ2_xdN#wj1}-s6onlAJVnd5o%74p6dV9V>AuP zf5W23RUMW(r)fmW<|9{iRLZF7m{hf<<5DLyjY+A!uIjjyucir2_M*5qQG3Rv-h6Eh z?$g$R@xFA`eNeGeh7@mQScy_blq_XbsZx$9X63jtsf;Nz%D8%;GNF1Zg99N4BIf-I DFNh(Q diff --git a/target/scala-2.12/classes/include/ifu_dec.class b/target/scala-2.12/classes/include/ifu_dec.class index 16130b61c2b0d35ccb8bc8414b748f66394613a3..6e6b7a013caa560a02958e5b9d140ac9f0aad09d 100644 GIT binary patch delta 74 zcmX@YcZ6@ld{!n#mdOiQt(h2Eft2Xv&#Y=pjBH@00UMCX4rb=EMTjvnGjK7oFo-g; VGAJ;zF=#WgGng?lPrl8T2>_tx4=exx delta 74 zcmX@YcZ6@ld{!ogkCPX&S~D?x0#c%rKeMVaF?*Nj|`#= WpBNMvJ~L=Dd|@zS_%Qi4TP6Up%NS$; diff --git a/target/scala-2.12/classes/include/ifu_dma.class b/target/scala-2.12/classes/include/ifu_dma.class index 60ba3af06bd73ee36dd438c48cda7fc9c23c971f..a79d8c1b9b5ddd1041ed10094b37b7efeefa5642 100644 GIT binary patch delta 44 ycmaFF^@wXjJPQ*e@8m=lYbHiMASF6^Gm8@+BM$=?BQJv}BOikTBhO@J)_4Hy0SH$B delta 44 zcmaFF^@wXjJPQ-UugQrl)=Uh)ft2Xv%`8rQ3_lsT7=AH`GW=#xVE8$inKd2&POc5# diff --git a/target/scala-2.12/classes/include/inst_pkt_t$.class b/target/scala-2.12/classes/include/inst_pkt_t$.class index 26879d07386d57a658bb3fe5d9838da808b4b0e8..66ab955fc0585ba388c251eac9f1cde6c7ea2043 100644 GIT binary patch delta 238 zcmW;9s|vz!6bIn*6XqO784D)UiU@*fSdA8a2b0}skl}8+%YPR|@EHUJlVGzLjJ|@= z2M|1*_I(fQVVztJp6ctSI%qb0(VG>B%({(GG+{-en6(i-SzD2z+lX01B=QwM72R2x z=*Lnbr(q)(Em(!f+ayT%QpH8tQ-2R=CnXo`^Lh{(l;j@Z%_F};w`2PtaE W(1yYQImRe3Ly09S?66k7=Kc@phd{sp delta 238 zcmW;AtqQ_$6o&Eh3Ui84#)8T8FCqx0VKrLx9!$pRzTEeg4J(S^H3$kO!M0*BdJ9G` zK=5$d?|EvoHqWJobv4qB>ZmDfL~oWOGMWmmXwLFPJC-kcvI0?CSJ<*92&HrGNc3RE zq8}>}SuKTBF>o=gW)Njq!=S*hYO)4vJOJOa3fKSu delta 37 tcmZqYZs*?6%ECBfavO^c0Fj8O-{?Q7_uhz{N0uL6l)4g95`O Q21|y?3^5G-lUq0&0k9MkD*ylh delta 69 zcmZn_X%*R^%)wYYIgvwjvL%N)V;zuX!&ndIZwB%kz^o4(^`bQlTnx1gq6~Em3JmoO PmJAIHF$^`6TR0m5nK$?k0GjB-Gh4Wm4me-Ox50JHu9S&CqmHTxtK ZIR+ypc?LHo1%@alMTUGP>B-O7>i~c{6EXk* delta 83 zcmaDN@I+vPAsZvtK$?k0GjNCw$4I>Yje-Oy$1+)GES$trYHTxt<4hAkJE(SR! ZZU!SJ9tJliUWO*s1>i}XH5>5aB diff --git a/target/scala-2.12/classes/include/lsu_exu.class b/target/scala-2.12/classes/include/lsu_exu.class index 56bb70c47f5667fcd8bd284a8fbf964804151578..5baae7781dab0f307c0661408eb8ab2745e1722f 100644 GIT binary patch delta 37 vcmV+=0NVeZ4xJ9L*#!ZoliCG50jQG~28s=)015!704@Ni08#*^ldcAD@}LX` delta 37 vcmV+=0NVeZ4xJ9L*#!ZVliCG50hN;%28s=n015z<04@NP08#*xldcAD>wpWC diff --git a/target/scala-2.12/classes/include/lsu_pic.class b/target/scala-2.12/classes/include/lsu_pic.class index 34d99b89b6f75ef2990cc9e1bb23eacbd3b25cde..92b9c22681b5d1ab2732174a1aa9590b3b137177 100644 GIT binary patch delta 112 zcmaDU_EKzv4hLh~WJONV$xa;VjO}1nJ&@G_X6*s8I>D@;Kvox!Wy9DF<`;9SGxmU3 wn>TQBFeTQBFe(-?a4{4!C^M8W*f5kbgff&dR5Fw^%w?!xI0$4tWhk0_lWPJ1uah0| diff --git a/target/scala-2.12/classes/include/lsu_pkt_t.class b/target/scala-2.12/classes/include/lsu_pkt_t.class index 1a65baf8a1d0306c33e6406f87ef3992a7321567..38f0a8889f1afada130d0cf310eaeffa3cb4f80e 100644 GIT binary patch delta 189 zcmW;AD-yym6a~T2w}zGNO%>72TX#(I^~f%?xwq=viRN5(6u&S!2rvdukkLaH7STEv`()M|}SSrynLi delta 189 zcmW;AD-Oay6a~dY?VL9PB{xLd*#k?u*?aKZrm=z|hF=vB}Etc$%v&WhPwgT*hIEdgR9?s(9%F;aI`yY0@G(i9W diff --git a/target/scala-2.12/classes/include/lsu_tlu.class b/target/scala-2.12/classes/include/lsu_tlu.class index df380e50e4111fc2a72e057da89890ea2075f6ca..9f8a47202fb86be44ab898bb642361de1db21dad 100644 GIT binary patch delta 41 wcmX@XbAo4s5-a2J$qB5YlPy@)8BYLNCA`NNxEPKzC^MX3uwghh`5|jM01^@m@&Et; delta 41 wcmX@XbAo4s5-a1D$qB5YlPy@)8MgviCA^y%xEQuDC^KwjuwmFd`5|jM01BoIfB*mh diff --git a/target/scala-2.12/classes/include/mul_pkt_t.class b/target/scala-2.12/classes/include/mul_pkt_t.class index ab9ae0159bec90621599e4dc4d10dd3aaa81cb66..dd5462d6544ebf73eed62a89134e7e676d946516 100644 GIT binary patch delta 266 zcmW;9xeftg6b8_HKb5gnS`p2!7EvigK_c|lv5svf5_*k7qMq;&3L!cL@8BUc9zddU z-R_)ia+^FCgWU2jR@|=#4YyT$QAhO@*{YajxT~s)da9kMFUs>k9|##9stTf!YAte9 zH_=%25lvLtu;Hm{DVnKHqPglVa#iVwVehZ26WMdEK^9t+K$|k?Pzg3Q(WM1?v_YQ^ l7|;pX*RW9?M6K#B w>i&AX-33=6Tt=8N#+(VZOyM)bo;i*zaAt`sDh4~)`AAOHXW delta 196 zcmW;9s|vzk7zW_?P0nEu!Lnfey9N<#g4Mo@FnIw3t8KwMFzoF9or++!dl4qVDhqyo z?Rf$(@QQxGIQ%%%aN-yys+}lRokW@HA<9K-7W&Q5uv7&itGbCQ)mK!jmabu=I*3}; xRn+}u-|m8|2rgsHm|)HnTW0W?W6uIdmN?TQW`#RzJlWvI7Ck$T8HN7n@&oE7L<|4` diff --git a/target/scala-2.12/classes/include/read_addr$.class b/target/scala-2.12/classes/include/read_addr$.class index d3ac88c10c54dd678ec8c3988d6b2e15af88c80f..3592902efc5ae9f7f8677c522e8412640c8c93f8 100644 GIT binary patch delta 19 ZcmaFQ{GNG3IU}RzI#2Hb8dx5(GF3BPxDu~4@U=q7au^(3i z3&jNbAc$>K>NP9I0vjuav}Ot|s1KsH=u~38=Ww6r%bDMKpXdMH|1fuekztRKVUI4q z2!mO;Ow+`Y2(zw!>!YGAVva6@Wt!L>=`C(Y1h{XDBE$H6Tt>0Lns+jUvP>Kfz!ziYBw1cbSZ0)EuoVG^)UTzYrzwKG9qCvpV{Kei|%+!WI*x zYkN$ky2t6~N=uf0_FD4w)7LpwIIQDa28cGR+@{~U!kzfp|}M|e8?-C9PKP#;r&yCvT)=W?Bx>!Pkxfw4$8Qf<@_H8T#qwbTJ> zfSMAIo{g%eE-2lK$8O74qFqXzrv9OxTZLX8)lH33b62Cci8@AIrDm-`FM&F!bZ!lH z^L`N>J5@t{K}}eT-U_OWIz#7zq^2gL z=b&n-FR2ICq4xq+PMxLhQXwgFA|(a8^{Bi2=G~-%U&326sN>Ynly53}Nz@_gJIZH0 zdQPg2>Z82UWN%>_cB@c#xtog`qe3^}tp(I6>J~L`BYK;ucIp@Eu}$bDQ_a+6B||!P zi%mznp6aJ2W+08EDyehSJ!3s zQIqn}Gb?51VYl;08uQ01Q$<+5{Da^q3>5YG@>jdmHEPjTJljqEK+P{eT22j6a|*{( zr~9oJ-S#>zZ=h1QJvHnWq%#LqttE6{07oy>ISu} z8tGo@SEb1{*sZn(ogwO(T0GlHU7>>Okd{*4P=57Di>N+oRs+%;>N9G3qfEmavD+DS zmp{SD0(0xB_o<0{kS0=H)O~xAuB1AsyOeDodPk_gDARtKX79&tqv|eq3qOFlJ=6#l zdJt(1^%M1U6Ve^jWh&?p(h}-x>d9uLg-Wf>*llJDl5FZz%6J%Q26dWx_)Vm#)O(cI zTSybA6O>0Q(s-&}=~63pvmQaGmHLy4Jc_i5x=t-^Ln^3YD&!c_YU)Soskf0eSDkk2)VR1e-OZ7NyPAqP3-3j25R^v~B!FL9=Uz WG>3LVb86?cSZz=<_uP3WYr_A$7^DIK delta 3432 zcmX}uYfzL`90u@rDaJ5oN)cC^Nu>)2;;jqUML`XARW6Hwnp`AA1);dDE+!!eBE|i9 zMX*pzpbv`JZAx9UaxAd1Vn}PI(1Q9PVi%oCtoI!DdA^+ao%ebE@BW9`0fq)$h6Y_u zdPNxgg~L2Wghp6&^+rD~+9GD@GDJ-gRgv!EPK1y1<{xR|^D!C4e6zb4i5%<8TZn3m zJ>O@RlMZv5I*lU8B0s?pWfV;oIqxtV#js_$uHa=`o%c)2&q|Mp)z8!Fbd3$w zZM9DmNwMKdKH_4mobrtG5Uy5lrxsHs)W_7{PRX~+xq>*%ouqD3zAKS#q}r$fYI;0+ zYpDZNA2lffy%?&Rx}<3QWR;jXFi$qWqH4%T#Je#%?#5%uGQinQEf? zsmZD6S*cp;OX{I@=)FLdQRk?8R8X3nNK3Nxc?<(ZCN3U!G3 zj`CQKUK~|N^-yjZvbP`uyX{nWxtoI;rGhu$ty`(n)NN|+M)WpQ?bI*S6PwUWrJAX$ zN`_4AwlWj#da9QipM^A%DyPm<_odP}eBq z%jm^Z4b)}o;aAWzQx()F)PIyI7ZXKFt-09k4<_^T(8-}XsUhmAeDu<&!_@cG)B^Mp zs7C55YC<7;7NxvG>~;Z3qiw7*S(t3{4}#V1E9!0XSG&{=%6|) z_OUe1`PR$MyRYyp!dxMBk$P+!(j3Y`xxb2Z1N9*_VLQ@P>J;T#jC8e9X)$)Y&&2u~ zI&IWlYFP==7HWiAvIFTp>Nm<%inNZpPCZ|SbhlDh8Frhy6GMnN+KY+PC z)DRVX5NQqd6ZLEp(p}V5%I^@;66$N}>1L#MrPgNbHoXN&9`z|@Jd8ApIzv7BCen23 zJ<9DZq)F5X%B2-)0@bc`r4_qHA3>*;`jd)0inNKkNrkl`71SUVbPQ=V^&|Dn+ej;v ztacyKuO$Dm@Hp;m2vGlc$LR`Gs?!yu)T1j{$*tYn5F!?|n+zs(->Kh2l^nVjDvjz| zq!irYZ3xrlE^HmC`nRXABVRwwo%-4RQRgFuIsTea3(#h3fm)arq{VB&TBa7F6>BD~ aK?~ImX$!Rz+9K_Op7v}0-FM%~9rr&mONk@^ diff --git a/target/scala-2.12/classes/include/read_data$.class b/target/scala-2.12/classes/include/read_data$.class index 287dae8433b2f52ab101332cbb202f9727fdda14..fa936f217196930ec97a652ac7f9d6f3c4aa0b58 100644 GIT binary patch delta 19 ZcmaFQ{GNG3IU{4}Q04PPR)ecj5U?L=j=YumovX}p69&pe}-8W+-@JY z+vnX=k$Rgr9hsx80cNwd>Mcg`WR#z1HqZC&&YKtW+#{1{jPj%=G455e*0EU}+IrHG ztF11lQG`Y>(Nq+jr>&#WmD*~F@z^LvV&ppmV>`4}c8B8p#6;{<+RitwfoBn#Mx%|w zC*JN=MSQjA7hTmni>LI7^~hsIRE0N$8oWI_hKUA1d7HxglqiZy)yV4dM^# z>0~^$kQ$&SsK6BTvZ;gAIAyS*XQg&i=c#F_vKN+$+3M9^PWcJ-FZE&?o?1yArzWXq z($QN_4N}*rId=4Ns4nU|C4B~FOU^*MmHL{x|0Sdrs(~7z{-YLW;zkv9g1SY8W}#O^ zy{R;oh1uq2qmxS=qQ0k$Iq0QOZPW$ofn4;WsYdDyb&p!&z>R7pmjkoiX0k93onq=J zb%P4ZN6$fZQ$J9TtwzsAwNsQ7T`9+0G(qe;JhsYBP0`x$?qy%cJI`kP944ZU9KHWjrU=>a82lS%wWE!!bedDc!{qh4t8q;fXdx$51UMA%N; zYoIPsrq_{fr7lu)n~`p!zMukjAuXlOP=*$y>y+ABFx!mXNF3C0YDz283~C5!Z$p?& z^;3UQ@$KmKP`4Ge7A^VZmP@~kG4x}5Y z&y^-SFk8t1bVexuPMoc!KBT4}M4C$tQ}=ZtwNuBadzAGMdVSPgrNC~?*4>THBo*0% zv;EXfDxw!@EA=z=oC|3ab(so%18E)g4K@F;Op^{{whL-6KNNvSaL-A7M$PJzsmmE6 zij?Hn?$N$reX9D4`G%%6rJ(*`eY%oElU(gtn)X<(nhrZehN ZbqjQ9y5+ibU5d`G%huV3cMV#n{13hmqv_Dach;0Yxb;DTW9f zFNg@N$|aL(2F*&FLT$R4$cK_j-KkK^shLolv8J;3oZaX7a^`o=^PKnn&oIk^+ih^W z4ey?c)JKTZky+a6Z?R~r-ewX{T75;MWwv*B-ZGEp9+^eG)svdVs8>l^C&lK_)|0ku zZFMK--Ufg6=dE(d12&16mvI)&6x z>IM~L>JAmU1~-bRx2RvJ zS!>bDp}MHc)YLrLTbzf{gxbrG!bNIwKAsgrZKKXn`gQ0npf*$QQ-4x(3vi>DI!67f z*atqP!rmj%aijc0Lc2gtNlw$N^sqNIKl%WK@g;W*wfzpp9nC-bzv`eS~>LwMm z9=%nRi@HiZUWVREYL8cbVx-LT*nGQIjf=rc>`whDxLNNFGEz%t71U0cvrlED1?QOM} zKW%+I?j=)w)ZbM6>*#e;w<+s3r2CZ|4QBBhwQ##kMctw-0%@DlkicjQb|Yz_#;6zeAl*S-q2}yGT1$OP1@A*zMGaFk+K_Ib zK35uV!)!(S(HWxr+Htmq`jDD@0BJTgNZr?gG?h9=-J|RW(d(h^Dg|_6w$4s;#;M3I zob97-QsLc5o2j3v=Uqq}sLNEyA*40bH`MIIGEF>;*)FKP{7?iO!96GS88xj(rY>i& zC{U7LyGMJ1^h?xV%r`VeDh2ii=`BhQO;%05qN7*-hf&;T6h3_!O6#@tr@p<$2%Sl{ aME8^~QnyHF(IxAwx=dZf;Ld*gg#Q6L|B8VC diff --git a/target/scala-2.12/classes/include/reg_pkt_t.class b/target/scala-2.12/classes/include/reg_pkt_t.class index 2dcf69371e65cc44dcf199e91d097b80e14780a0..068a5a0ccb525bab0074312daf1fae91a0105620 100644 GIT binary patch delta 47 zcmX@bdy0314=dyQ$-b;Mj2|X<0m+Y(kF(YZzGL8Ge9s`q_<_NQ@gsv9Jc$dM5@g9R4*-sS2WaN00zh!NK8Q=w@9!-KF-fd$pA>K!4kZ=3 ztX?HjyPMg$ePX4FDpYM$sq#@DRTpK9l|JgC8dSNA@o)XKs7$Sd1^%3#yT16b4-eV1TYc!W8(Pz4rRANl>Jc0Z3SbCHQ*odFE`+ z9;-wucQZS;Pps5Yg(^gqswV2AYNL#?(nVcVy(*U>{;eMum8q3!!SkG+qb7sFHe>KjqO*N%u;yQvvk%5_=^;@hI&!Z0q6oW zXC3ucLssY$=pQN1Seh+2mhSaIzd=56l%_-N&=|C6J@w+D2IxBE98WzXbP)PdYAT*) zTeE@MCD5nPztAfQ)XRhVp$TYNBK5XF9nfvaBZ+z&phl_TB$`c|OdS(c4PAsBQ>YgL zl|tvB|Dab>=|(?`TMLyz zgU}4LGF{wANvGKc@~CHlY|s_x$$aYRpgque z=n)jSlWr7AweFGh)aUVJw^_t3pO=nH7UUP`w?Ly&eKrJJFT zpr|V{Q?D6Q(6n% zhWu+Nt+Y$bCf-_6OGzno4f3j^bQg3PT5O{<7y2A>e}~d6Xb^H%DNTbulp0fMw!}l! z>4zRaOlRw$9_RsNIzqiR=r2fLPiYf$A6nf&>0#(+DW^u7t)`JWW6;Y->1-c#6Y@Pq zX$kZV^ga3AM{u&r7=)9 zGy@q=Qtu@6C!}i=>5evw~7m2nxQ2D!qeX1F4xR`z(YNHwJ=kVVP;0N)#>Cb>*f zzVCW5MJj{KEY-;sEp>;>!lhL`dgXsBy*d2rW$krU9Zx5)(1Enm!45&88fO-!31B)+ z9MfxdGlS*?3)g(cA~Zj;NTy{`EPxqV95b AuK)l5 delta 3483 zcmX}vX;9Tw7zXfrC_}A2z=a5B6tO9UM5bYfi+B~M%OZD?5JXl*6i|{yz_81vLdtUc ztAGNEKrG=1QqwXeU_+UyjHQ)MA4IgpDTJDe3bk_%_kF&c`JMAT=kNl<0Hc#OqmwrM z&N}9;EYcHGCD#C;B1|w4W z>KK_K6DOr6Qrx{1nZ{Sos6xJWM$Oqtaak{BFt2aqtHtD`ctwYD?Ndlnb4Oeudm)=6d2|h!@(edq?FqwD>i8YZKG}U5D&qsTU0$f-XYy zHd1d5WQIP0{*iKxquKJ}=w3hc8{`pBX$I5*jYCT|Q7-{%gl<6g3Dna=hoLW}rW0tk zwVSD33VjOw3;8EfFCQ9!CZU&;sJ9*Jgzi8t$<*5nHA#&m(`@P#>KLFJ=n`a`O1&_s z3_1_}2L+_jjRNQ#^Z;71g?c-rEL&){2_#FmQYR5Q4t)nXq*Kob)k0rE^S4oN9aIht zL9(2bQf~nLA@mC1oS=Rm`OboR0my#7G#OuD_JyK zh1`qThM|X0P&U0<2)zeQLo0VuFAM61?m^3TQ7;*4hHgr+9GY!I4z=r{E6~E%DSZ{H zghrr8Q1EWLQ3SmY{SJBMQZF0ok-C;kv%Qc7X}1R8^u6;oOOU9`$%eQVcV z>Wn}RZ_rr=^fB~o38g8}AoSEeO5>qE=rLq^lX{)djFhXHW@|N5XBrACrLzX;J`_?$ zX+1On`IS>z4gCOlRZv)OsjW(AvWy6=%nwUm#5lrFGC9 z$hVf#Dyzh7;;of+l$1f&A-8%;_d-{or4~x_pwA)aw<*nrh9G-|(sbxUsd0s7OFBZG z0qDu2bhZ)dg&snNW7KPh{({0AC~bxwKx-N)JqrCSW!FTr)izOQ9P&9%X9uBMkmm_X zOQCO|mzpUphAu-cEtKX$qtNrMBGtCiZ0F@(e0S|m(!H(F2hhS(lqN#`&=YNx#zH;N zETlh8z0=U2kgi>%yW45DNx2uZX*=lN5$Go1z{SYLpv%b35Xi{GP|C>5FoThgVK*Z`!#zd;MkYqi$=zHX0Ck=gIsgCw diff --git a/target/scala-2.12/classes/include/trap_pkt_t.class b/target/scala-2.12/classes/include/trap_pkt_t.class index 6d01a38e6855bed69a10cef6ac9af6fbac409f4d..0b752e619cad5be6df4862dcde7ffdcdb8169822 100644 GIT binary patch delta 153 zcmW;9D-Oay6a~S{+}u%PK4SOgkPx`Ro;qN%~*ny>)UcKY8&lUl;dbLZr7 z9>3lJEB7!P_YEv-Rk*VBs#MgdGEuAgh&t6z)T{Q!a!_4Fqv*g%KbvJ+B4mYxHFoqk ZvcZWh&g^hyj~fR(IilbM&(cNf`yVc;HE93< delta 153 zcmW;9D-Oay6a~S{+}u%KZNETS6Su!Bj!qN%}Q+G(dhhv`yCY6&mTol~Y| z`g%vK-NS6$C$jXaB(`i+CsC`qih?SLI@M3qtMh-o^58`BJiD5jYVc}%kynwVxYOlO)h`7%cb0IrNBcmMzZ diff --git a/target/scala-2.12/classes/include/write_addr$.class b/target/scala-2.12/classes/include/write_addr$.class index 825b86d5b9145219c2705e844997e5f1f4e60f19..48788efe3c831da44558938d3018124312d83201 100644 GIT binary patch delta 19 Zcmey!{E>M>B_m_>M>B_pH9m$c4-UmQm-{p-XcE2PgQNiR>!<7a;Yjq zm|he|rbxMqpCYw0wzxSWDayWetU5Obdy3zqyc~&dwD!9B(J|`vguKp-S*?1c#6wtO zj8fj>Y>f6**y84jnX&ehb44gsM}0{BO9jN?M5#mCD{9ZW!DQL<=oCJbGqo zAN3tIF9E#-s*O5FJ(!4|Ny?gt-A0kLC84sKDx;23H>u^xII*5OOkJTCr=Vw{_EXF7O6l~c#5TaJ#doLiB>DYU(8Qx76cS>{e{WxnXLW@+m^PhB`n^QVWXFOQX7| zFR9rZ(Tk>B6 zHF|y2ZOXI-X*cy76;y+?gSsN+T8rIw)}k{>t$YRd>ZxxjzpY5OQ0J*9>X4RFpHq)* zLs~?gq2|?Vsj*($%~ta^8+Kks6@xP|-Wk>!of{ zp-oz9ZNhHX<*aRKY{t2E>N54rPNdD$C2B zsQYYMy4;4{j>uX2dDHdcTs(D%`iF|_L$8OrK?NT`x|_O21-_27jry5->Y$dI4{E!O zlz58?Icx8P^ACCH(&Y#2WK|hb9jY>=##LoWx%7MKvZW$anWY+4S;R1QaAV zfT*M_m;#ot(fDK(*%SdEu1qf_5GyYJIK-~8V1dCs>l46w`OM8M=k zz)+N4W#G~JRm!zV|EzMYwuSQMgb;pPAK{;36Jl}SCpB*{gz#Gl^W}ZtWHkIgiPo4= z&BqKTzv7HWf4AG{OS6?(YjXSZvnI2g)jY;5c4;+tD%WaT1W&R=E2^<<@y`pb3lwQh zYF=zjmkQ-SS;ZNTa|Tbf`L<3}<|chO|J|nXCsB6sy7_j8ay>4uQyt3`d);9?+o6++ z;Ab4-tME8y@~MfwlQX#is)as;{)J+lbfUyB@rvSE*O4rIjyeU<0CWkOn?$`VXfN~~ zG%J~U$xthF7P>!$dPXT%3hg#bNoy)qmO-V^QRoJ=D2-06gAPHLp?T@l%ZBzr-$P*; zqNmHC)wrC+H}DJSf#vip6I2JCf>bN0_Y7199fNK{F)QiBdgu-4id1kW?Us{C?QUoc zdT14;sZbj<0zLRV^~_K`bQ%iCqFx+S4!t8ao<+MY&Zc%D^d|HRq{*RPF64oJfM(}X zFAZvkMxmfQ>RF%$DQ_O_7We{nv`__f9QqSlvYJk~pu^Cw(EJyvmk0Gg7odmpsh2KQ zolm=+Lo#g*b*#`f=woQgOVrarmC(D;U(nLEbfO3vgswsn1)`T&K)dzIS^O?sgu>U+ zvofHa(0M3$J@stRcIXr6u0ra?LsifT=x?dVT(n!Ui_Q%}lTc(4rK_R+&^R=wn0m{h zPUuT$`UdLRp+@LasXsROcALTDH;Oj|uRD@=Y!rXmg|0xcFVnqd=tpR&o6>r}oc<>~ zv5Asu=sct;p|lh_13g+wX)*K>6jny*TId64dO4+e&@rj;a@sAkf;wJkN+sP(g$AHI zkfVxvz0fVlxS7%}=r<_7n$mXYvQ%&l?Y5(aI^)oiSLj|H^eq&31&u=US}5Hl27Ee z((a;^Lle+byD4piE0Tk4P7JXt%?17C&#Q9y*r<9fbaYti9ChhOR^U{gm#4u0nCIQ`!ps3_W>3 zq*({VZeDi;ACt3qC!BpyqcX}5*lCJPQtgV&QlpA2QbBzhl~u~3$R^dG$j-feu_}k0 z1N$|qL@BKzr=k#E)-V38I5`l)uR&P@%Dp2e2ZB`52Bv04wt$(KmYG=+v#@+-WfjcE aT9}>fVGcIP64@|wvaguo$elxlcmD@kFw)Tg diff --git a/target/scala-2.12/classes/include/write_data.class b/target/scala-2.12/classes/include/write_data.class index 6647951f8efe571ba8d2d6e16a426256a680e568..5852c659164f1aef15da259db5417927bf2f09d3 100644 GIT binary patch delta 3324 zcmX}vYfzL`9LMp+P|B&9xDDE53NHdSwVX6dv4*>V$O5Jya#L}+c!>o<4Uq*3MdZ>^ zK}Ah2-Nq@9nulRwVv~^|L>bKpL2e{^F05V9WFaCG+|(9 zLeHfL54*Y?k!`GDk+B17D}>yZmNAD2~iM~$aeHRe{T(J710HP(yK zImYU81gNB#FhdP7tBrLerrcQVvEvR5}UCWm}~zM{X~~zs`5?@ zHx;TX67@}|&0qB=j^FfGx6s_Ba#oDqLBFGrB5qjiGs|a>Ie%Mb}a2GTlpFCbM;#dp+fkXxj7gtd*!0ok!lwrMDFA zLTAv#71E19+tDZJZ&QJ3GFwTS-0MMqAZxm$cGQK2(IYFRmx0>Q1>}<#ctI#U4*mPx<*=$Yw^H2uXG{s9e%AbjH+Zxy-h4vvgd@Z;PDSQ9pWMtE4%o4^4VW(sXnT{fAO2q}Pqc zOa*R}*$!`$&M1nil(Sa!8(Oqo(q?oOJyj*?PIMVP?v%6|T|gn#I!&&Y*}gLO`qK`q zk$a`+G|0|MaqvL2|oup}|oOLqWU6SM-(&<9CQ2b7v_BL46 zA#@W()=Rn%{ffeNN!o<2pm`0F?r=-brr$JswlD0h<%doMZcKxZk5>@ zTctCM=C;XM9U4Nj_DfoY&Y?#SNV)}`Mbi&T>Oh~NDeXE9Z*!u!r Hf70uJLJ8@) delta 3324 zcmX}vX;76_9LMpCp_EfIu?^Z}3NKfQ_ z@8wXJWOXGp$5?}{;l}D4?xS7^^Hj&J0nXhG>tfC)6r_5>Cek1^?o^V|DGSdt)=S~J z#_F*7sJMt=LyZxujCC}k+*k`DC+wp}BK12%mbM$K?hZwHD%Ysl#%^9zEoVy%jYjw= zzvv97RCKl>d%TyL5)(+zLuJJ1iGr;&)X^A!XXA2=e*d&(@y1$ct^>>T6CJkc$~`v3 zRG_Me)i>?&-fAFr;-s~^#%+_V@^^`xN87cCt6{rneK<=s1TaI?2 zvuJXf^g_`N^a=XglyADsR+29FdeI*!C_~Z$)Qv{aV=JVWiQ3Uc13gU=o0eEmtF#DLSLf$*GexORijhr z4tlOY-^eSF+4{}B{#m$%=B$&au19a6>&UlIdfDg@`WAVwmtG=jM(5B2MY=byNM@@s z_j+n);%ok*F3q z&^@%cSZ-`V?>ptC#)>EYIs~b3oBsXoum!1hrxKm}=Sw7MMc2{7Qb`-o_vooINo&wI zDDWjoE6~@-uUyhHbk@{Zxy-g{i*y{wYpa|UpaJyIHc4|)KbrEgq#5Wq`VS>mNUsNt zoATW*vmMzkoiP+vDQ9iyH?(Ajq%G(gdZtR!o#+aB(k^K=x`+a*b(&Buvwdam^{4Gy zBlk+t8T3f4q#My`WHb}Z3{fdHjN!pCAq6LkT);pzV({Gx)TM|3Efc%>z-G+wHtY%3|(C27+i=-RS zDdf>AX+HYU)JUt$mc2(heaKbGSsHp9-9_z*RzFm%DuhlXSAqGrw&`7YBZE$ z{--?HM>B_m_bM>B_m_x diff --git a/target/scala-2.12/classes/include/write_resp.class b/target/scala-2.12/classes/include/write_resp.class index 028eaf8d5b9eacbb0dd092d66f7189b06762808a..639ca9346363b8b03c4a47a224ef1d5f1e423e20 100644 GIT binary patch delta 3320 zcmX}vYfzL`90u@3QOePoU}4ZE)8#|3>!qC0EX54i1w?KOd0FLZAfO8g3xP(+0wp3> zj|wWNanWp?0;#E})csJJL48oOlBQ6bZYJ)Bl1i=joZaX7a^`o=^PKnn&v0279-TBi zI;sC!l#gAEMrCSixY?quhUj3i(xMlq%wgW$E%S1odt?;77Na^di3y9Rm#Xc{qO-O2 zYIK&ix*WkGDJEP~W6UOP9giv3*1TAcgT+{^d}qX}4sDg)kvP5ZjhnCS7RA-^Y=x%r zm|zjI+UAv5ouSET4HQ%3I-<^m3_g>IdpED|$As;ZZ10M)FJ9B6}TBaE7eSWK|Pd* zo`tHR&QkZNXY=Ka?0n2NsP^(_;SRN+08iaQouF<~hArr2P=~2+sGzOrrBE%@F!iuq z_7>SOTdms5+0Ie-sbz(DYB}{T<)#)Ep|_QKllqAYc?rEts+0Ow$!8m8OWlTcD>Xt* zD@Gba)ln|$0kymYH!7(2yb2WV63?fDNmv~6_q)qs5*=Qpc=ykhB59*;QcKH_Hc;PF zPrZz^min49mLsjCzM?`Zkd{#wl-w1Vt!O(sE-G*b&hn@sYQ`%_v#3F8Y9&$|b&C3r zN_iE%K59bAP=(o!RH5Uh%sX+`PW?u$s7BgK-JqU!BHc}mQcu<(t)Z?^VYM=~)?&6V z)n0zJ4RyFzN}Z=3eGO?Lb&k@%j&w8iAvJv$(oE_!HKksr&U%wr@0FZQ?jJC*?nbAV zx=Y11Anl^=P*Ho39-w}u!W)scP}iv?O-SpN2AVM2!e%5+>M|ADf^-KpLd|VO>YzTO zX0;);Q)j7wy-0JZ50u9CVzvx{&H&}R4`=JBx2XG6@_zJssK2OH2atAB<5Xlj(*4vg zO8y;~t+@l8F>3Kaob95%qZS-OT1{P|o;ZwjJ2gzr=|oyWeM-&jl4(R2W;>(y@;lG} z2=3)j?^Dx`B2B0IsmaHXuBA>=_o$>d(CeoDq++{eTHKAkIWM(xexWee(Z_?!FRj4LUB@`s3v@?7CoGp>Ce8NVigF LADn*TdB6VwS7PDU delta 3320 zcmX}vYfzL`90u@3QOePoU}4ZEQ}__SwwCNd0Fll2q>Dc5NL!fP$F{m zsGx${vS>C=fz(t~>V7EApgyQsNmHmzHxv0#QmOTxv-><>&iu}Kp7Xx{87>P$Ba??-SSt2wwSvF|vn59Bn3t~ME7NfE9osp|LwN-Y9d<18`t9H`)4L3Yip5O2NUEI-S%0+ zKQU6tAgU7OO@}o|3?_PR28p}W;v}4vP;XPeQ{l zHlSys9Ml==U+S3`aig3%O^s3W^Uy0&YR|)LH<--LM<K^rMp}dh>h}j0zUj8iHp%xV3shg-1)J-a66M9+HVd@(yXft{#R4X+^JzOk% zi;6K@o!ZOU&QbTNWn1vn3hG^IoLaaQz0K5{)K66COXy`&UDUTqKHD%`>Nd37s9|ba z2~rDHPr0cF)bdi?sHEQWDo~7Njr6uT3U{@k@}u` z>Sd&L)Yp`u0%;ZX6%|^Ew4A!2G+v3>wr)qqO$F}2SphXj&3FZA4mChctwL&}PEr3+ zDX*f}OHC++RAaUy)#!{2of@H&}V>oD7w zYA?UqA@#UdMxCb~eGTar>Kvti9qC5uLu&diq}kMIYD$Al9SugY-YYqq+&^Gq-Hncm zx=Y11BJHN`P|^%}5)R`kOJ^!WJYB>M|A9igX7xOwDaWYNtM< zX0;9p}TT3T8qtxPqINL>iM=dynw1&DwJ#iT6c4~;4(}lE@`jnd4Ez`(u%yvfY<#(R{ z5!}n8-lwJ=MVd+VQIn4$T}z#$?oml^py#Ciq+*>iEpcMD+iEXoi|oO@ebmp?GM7x< zc7teAlAmoCU12_H>ThPh-Y}nZO?na4EB~Kx_LgdE&~dpo9Iu#R(*^6&bn|rSx|KTH K!1NQ(`~45=1IQ@= diff --git a/target/scala-2.12/classes/lib/AHB_main$.class b/target/scala-2.12/classes/lib/AHB_main$.class new file mode 100644 index 0000000000000000000000000000000000000000..0d0a32952ed05d7b653ebc0ba2af75d279db4b1a GIT binary patch literal 3903 zcmbtX33n4!7`?As+7L)-*$M~o4#e7Zwkk;}7s}sDH!beKV70+D6PdrYAF*H{bh~`|fw&>+gSG{|&%4d@r!jwu8UpG3 ztaNh%i`0}V)qKl!3cmDw0dbHO1PK|;)iB1SH&GSne=^?)S@1o}nc(dHn4#rZ{*YT% ztRo-RT5@fh<I-S3wP^CW&r!a6w>JJ zA=>w(uo!*%*EYft<4ZuSF+-i#ISCmH4zi{I^~LMIle(lV@3$MoC^a0%%h$v zt8pshel0(<#&Rhv#7GYgKx@u^RT z%T1&{7t1x$+}OyhiN~fZDi`m}Iz;m)3`yHASiU0s62&B*MTte1+3m7Yu_-c|3Sr4J zjH2y0Ci;lSNiKz&wESq53@)y$*}lO(KZVsA=F|UTu~lFNJ&#+S=iBBU$8mibY&_}= z-A}^NlU*uk%)P+jdJ8miiI-W2rK#8WT1SQ{oPnnUQL4Mn)TFJIXI1`Rsly(iI^7do zS-`U9=_k>F0nO$`T0fqn>!9bU(2MHn2U`dQ`31bFW%4C~TW0OWabee5pTH|*US`gQ zttEX0UQ6Otyq>~(Y|xy2lS{^Rs7Cx$AqyFNdlR13S**&TSuPGzL>g`^;riEwGBh1- zgh=2bk2FQs^{c)oD*~6Aglcwr`9GANMfmVgG%Ne)eT?7l;=Lr^!TaR*2iyVepgm({ zr0@|g^g-ZbR#UJh9O>6Qo?tq{gG@SaIqGn2vZ%acy6d?hd6&nyQAs7>b2OM7RuxZ` zs9kKL-mvPU(vy>l`v!TI8gVFXL$<6|6(5rYx8{}9K1)079js#*&g1)ZL7x;y9G+s- zh%?TP=nO`%g=^ixWV?9n(PU#g_UV0=_cp!D2G88YX!A)hwv;wKScc^s`IIC5yz5Wm z2HLJ+CFC$bwBb)8$RQ;D;WF(pYwMrG{CJve5xQeFdyxGC#~DG zb#~LQ*r=V)pS>)!h-Pcgw;@Z9VZH{w;4I)veml7fvowKCxRaCS1=!qbfK>!W)LpI$ zT&9U-h=@toVZoQN^#_KXpYq&-7dJucGVW~+t^1l4a|QRdTFmx%G24S;`mrOzr?GmM zk!vNN5cT_sz%D#619Cg`#@Cfydj(rt&r2^=v~D`D#n_Dp>1fWnT|usOmklC66m#7> zpf~Gi{njyS{pr4e;S<-eS63}!oc)W5?3>~LMRf8H*!(jd?mKi9kMMp21x`GczYYsH zwCO7B!@N{>c5J%yu7QrL@M+dac~OAPpXkP4FcEgdHu~(tO4M+cu~)GFwv*Fs{NEsr zb9~dz9!X*f)9e$*j=0~Z{~w8}7z+9t7|343`Rp%vp6&N?_6A-(!GSlf;;lvk^ILHs zbl983+qe)p)QzrboycCtB|xLXj>1>GCi$WV3)sg4_?pjcNZ=dZSM!%*U86XGC-5Ym z!ZZ9nfe&ea0^ic&AwezE*y|#f2eKhFxPb;xx4^BG%}SxgY5_8x`x1DxB)5cSgTQz6 Gf`0&1Wv3DV literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class b/target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class new file mode 100644 index 0000000000000000000000000000000000000000..6641b9eb45f4905249241107c65367a2e645ccb4 GIT binary patch literal 738 zcmZ`%U279T6g@XzYtp3ou(noh>&Gf-3&uiyiU_S(3?x-Z+t)C=JDRDRnXs9a=3lA! z0ez^Cf`7yRA>Q2vAq8LN&OLkYx#ympUw_Uo0PNxsVJ%c%Ywy+mU?h}w0~v~`3_4m_ z*E7M?0TDJPz6eDtinUcE+1m3aHWI!)h_!E((N7#?33V~_2G$J3nc97vHV_J~iLHzX z)$ZJsHX$#@<8Vq?YHoH<#Rt&}g?`t1?VU>Bw#z8MDI$Xsp)%L$piEewseGw}u~FK( zT;l#)VTX`yZl08}h-wKH)Ceo{3+$US865M94jP2q@nPqPu-g4k5vy6kjUujNnTzdE zP1uq7eXhF3`xTxk9`KydXwKKR6KS^+X*t|s!WSlxi9t%s!+7M$=ty`WBaNwODpwF9QpDmEq8OY)RCmH17 Sa$MvWnn~tTqMz`PG5iHm#Gcv! literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lib/AHB_main.class b/target/scala-2.12/classes/lib/AHB_main.class new file mode 100644 index 0000000000000000000000000000000000000000..c7c3d801271d36cc223c66c75b0a0e71f6d981a3 GIT binary patch literal 781 zcmZuvZBNrs6n;*-t}B#59fFe=-PjWF0~G^CGo$Gk_>v)v1rovsyj!oMq_n2HGvF`q z&-g(<@WBuM0DqM6bO>s+$<1@mxzBld&gu6bU%vrZMU`NOLC5u8)Q?U@5Sbvt#EEz> z+)zY4ce`^UyUK)4aKv%vNX19uELdIccSR@&^UdMKP2}5Hg3&ow zvQPM!rGv*ULAs^Qt+Yxyb9VrwYa^j8Vg>AkV$nCrWOyIzjd}%5=6b)(mub7q{khP{W+G337cSUZ8!Fs8x_KM z^RL&MjXcIJjA6otg^>}y-5`wmG8E_1e;EaeFuC|^Set{WtAaSXKP>0|<9>2A)Ip?z zQ|Z>@GwJVfj@r}920O8TZetQR(>k{Zd3h$ggEVDZiG)k(i%YL;+{R2wm}N=pu`hYA zTT&gz{*Fk*sZ=symDcsL2qO*oE|FcKq|Zh>9wc448H5~I+`VjNKj;UYPmYjKrAx0_WZZ3ZGL7?(i{qMwnnKYvIuUkc*e(yG+(F wg%aa+==3m@RdV(;w7`_~Gr7(M<~|J#9c4xh1{N4cnVRKe_K`z{9l8Ph1R)lmjQ{`u literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lib/AXImain$.class b/target/scala-2.12/classes/lib/AXImain$.class new file mode 100644 index 0000000000000000000000000000000000000000..def2ec76fade659740c792b08ad2df64f0097853 GIT binary patch literal 3898 zcmbtX2Xhlg7=7y|TL^4yn!yA@EAV9cj9ycn{?89 zucZ8f%%so;X7U5_qcVAW#X4g_G!tulr`!AXD{tTTcJ=o^H~s>!4ZjGaEVG#1_w?Ab zG;JdRA<%PLo|9Qi+Edx1#nY74?1-PtsOq(DbtFOWEVbo4}izag+BAI~<& z0X3saHP3YHf+t;1KpbKLem(|MHH-=APE`f^p3T=I7ChIqr#QPWW@y@`H{z5P%g6_% zmK@7s_4J*cu6eR(schb?dc(EJN#$~Op&7f~q0xbw?Yr6%4Y)PiGpAK{*qKq~6AYf) z!;e7c?vkZ**(1=J9vmkOyZy%$R$*llE$A0$3yNBv9&A`vyM9fy)~CbZL?YM7G=;Ue zYY{rIjy}CpCV^U1R+gMqgXfwxUy>CD~%$nc%v}k52Gb zpcpBI`>;{xmnPvByr)-9T7ebm1~BNT?LMgm?vBT4Xq&=jJfI_Geb^7B(2brhqP;bR zrRde)wh@jPUwmRs80su1%oq;}Y)lV^DgGC6PBdp3VLFF>G|-qjDfD5PPIMP3Tu*eO zsyt7*%yeF-1ev#`4{4k-4b1C9M${U?oOA@{oy*jI$D1;Z%4)Js?YP^JwqsA$Y{ORP zjUl4nM@+Rg#AJ!h)P2iP0wYO`>K0lXGI76Mt~jRc8MHJa8Kl3(e*M{Ft}3fZ>f%8< z3zs(>%cZawV_kR*T5=95Te;Fx>&KOATFz7_@)WKLg~qc;(dFrw{sgM(^ZN*nCh6gr zK!1t-r>voD)ss^yJK{f4)TUGdPbN{&NiSoObr}oY^x#Aa`!KAv;i>KpJl%ugR;qhK zUnu9jK_vy|B`x!U*0BVh7uZnu6smPzP8Z9Pnk^?~$#dM<1STl4((+ zV!4Kr8ylH7@%U^-<>HMQL9}qfh_tMN=_$f5QB2}Rlvs3`%`PhyiyEVu5R^PeDB4b9 zs+V}2;!>z-(+gM0;Nr@fo-|$8v$Fea+wr8o@2InMKMh+? zb||1R_X0tQtufm&2 zT*O-`Y`{I5vF~ufxC+&fohslUL+@z7vWUZ~9GK_Q@Xgx#%AMiL+ zbR4hhxw0bgWrI+SPA>n4(DUdX9Ej#+AHI*V`y+gu#E1BV?EaKsT7GlJ%1GgJyx$9f zFIY{%oU)}?b9sDe3r;cJdDB)$YSTsK9@jljA;>#C!i`Jn0H4FbezwW|1-EI2i{qz;(cVb5@cVK9&Hy9@f1IA-$*qsHt>_Cvcr zf(NsbFAzqH^RUOV)l_#WT#dnz!%-F|#(Ansv4+WRhAw`l9krt28g z&KJ&J5mFJtIehFzHQtpzV_fYxPfZw{@88WnQ|+nX(BN4%IFeldO68RAo4z01folTU#9 z!$e>=9+?BV6?)t2$gI19q2}|_OBJr0&TA?5;88ldW!6T`2PXg`2n{4fya9fU&Rx=-$a2EkLPc|1P*Vy3hM|j zm0fL{?%&+sb`>7Y>M1YL*oYta`|A?Vxj{#4qt9NfMh)i}dlma{2RYrs9|qkx&o`~? zktAj?%RXW3koztA$4FSkh~L*hf94u4Wd6jA@^@e?if3Tm0gUKhF2mkpu8^)-OH1#YBlRthZ!1juymOW5giOK3I-{7f(S7hl7n Aq5uE@ literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class b/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class new file mode 100644 index 0000000000000000000000000000000000000000..039a3a10fcd43fd79d1043461754d6d5b8ec748f GIT binary patch literal 732 zcmZ`%+iuf95IvKNLsB=FQd$bVa4{%tB}}FA6oga|l`JI%DQ(4DwYC?s#o3LV4Qf7x zzW~HV;sG9!_$b6U4N_Bymz|yCnKNh3`uCsjKLG6FK4CRcp}+Sk=nJL2SSDgD<3KCx zg(e=CK!lB9Bog7LBW+b*`g`HfrXsTYBOO^~^urSJgoZd%yC>G1h+g<$(m-%LGqN%z zRNEJav7D&7e{5&Dh)B0QCmZMkqzDkFyq!M)g6f=gJNYJ9Hafl=Ce zT;cuGzeC73H;-LZQLA7cb;9zj`lseh#z(wg2@8b6(Lr!XSZV*Kh_x)@S{YZd#KpF! zhJ^K*WiC6$%Q=q~^FLuvnlq)XOxTS~SOKd{_sqnSP-`nK4@Uh^riUU-7+Gi=HvCwm zD$A$feAkNTZAT2IdA%cT&%`f9D*BR5W?_}C8KsfjR~bpIn>|{f6J`(eYr~#T5bUtA z1%7;p0l=e9m$?kgIfu>4_Cw85v7eWLfc#dr6-4A-&38S!Q} znJS~`aLjS6Z~sD(er|1lVYY8r`^Z=xwrz@N7XuHz z`rr7V4}0*zKfpiAcnWSV(Iz+No^!wRhq(sc(d28k+`rxv+dIu(PTr_>O>Ut zviQt=X_@=0+nNzy)MPr?sFT#PI8e3fzEj&)vQ;9d#GK5w);BL&Rn@2-h{DrdwXCUo z10hE$u)+9ux?q zns*;73Z&qk3=5D}K!#)zZ;L3Z!#p}+&Y|ye0-53;p&BFK=5FA>m^Rb@3BS4#bmVil z&-7|AW=PJd6OVNT?P#40qaM z{4#Lf(2({SXCZQwZx=-%S!W+YW>d}_bj)BB+N|Mvn3#Jz8|B0ux|YWb-w!yA`eB8{ z&Ay=wF_^<23P3;+PzLnZ(957DXcON+-MogSuMq^+@rbAqq!Ef-F!ev++zk8(!7*3? w4ef1ecAAPTv3iucgplZyu+KH*zf2tgHqgdEgvV&-5gNxM4Iu#q33yXaY11pc5*kcPnv|BF=|!8~=Wp%PKcT<$>33&zd6-R#ANGB<^L}RDIrcld z^YVW$y#!!A{vog+=cQB5SbDTv7yt?*U&trd#vladWX8Obn_HLKK9SGn+!&$) zZ4JSzOBpBU2(%cL#4tl(pbGCgSGuQYnU+0*har ziyDliLf0Tr!5)%+M%`p+%rsm0P%jL-{hfc7`aoA*pKBNBzP$ zqecpcy=-|bhIt&V>GuTU9G?8>cp>YuaJZU5(CDB*B0W(W&E$@cx_JQ^IE53g?|VV; zEY8HJGwHid_C7`izoz|2pKx+smJI|YY2Pgs8yg5xW&<%*7=-ES{Ko41N)0NAjaKUN zvrd`wsp@5XQ18rOzQ?!BJDmgpWgc5<>IvB^@|Pgn3sE}JUAfl%XB>F%_=R2OyYeq&yKV_tq^ zUVcMfeq&zMag1^_xORrUd?q)Mb=5{V-o$^^CVVl z@3=%td*c#obS(vmwff#$B?h!tl31rpCnS|hjohTf2JPJ^u~EmpP2vXayV*7Z?=g*~;Vr-!mX5|88K2{hr!2K^t(7bgNm{3MrI4b?YQlAn&_Q}_&r zvsPHuNhPr==BYU5;Iouer&!E!0-wf~1n+!4=ur*ZN&OkD{W6oQ6{xVFiZ3SE@RtGs zt?pD**BG9$rJ|%^bLQo_Sn^ITb=33yaxSGd5E2*htpw)d+XAWjc-VvM?N=W3r}099 zUHVSLKm;W*yd)4E*|vw*p57se%lKXbF?_#aL)QVI zIMB5r+nw`@MK{Yu@p9vkRc|Zu=W+ZDzuGaDne2haBGvepha`?sdy!h3tOEcg9_gHnmm`QJ8)8 zmf`Ye%Py*Rq2%R{=}_)D2MQB@#@)>~6c!%{UTlW)IW{+xKU(0bRd=XU5k4BAVzvi* zPOm+XYGoZ>fZS6M2r zveaE=sk+KibCspyDx0cUs;&A>tyPvvt1NX^S*onE)L3Pyu*yAZG{(E;ag33jul>Ph4-3pixuv~Z5%dpwD+5Es}){qg>N_E zHY>c$n)ZkZw_D*ZD}2a=JFIZhn)V$gJl6_$Tj9G*c%BtrZiVkQ;rUj0g|*N3m~f{R z?ycJ=nsApDUTKAonsCwzud>2pCfsd>`>pW3CcNAVueQQD z6JBA3Q&u={!aY`ajdiMuCfsX<*IHZlO}Nhr4_M){39q!m>#S*?FyU2Jc)b-qX~O+h zc!L!_Wx}hi@J4H&Pn&Sc3g2Lb?>FH!R`^CM{GbW1wZb=9;fG9kzzW}Ng&#KIbyj%L z3O{1P>#gu6>r|aJ;SE-JGaj{UbdQ!)hI(z+lR zGV6FSildgTN3|}wCT|^cv>r1fBxLNhL+-7Iw9X8vCRdNSc7${?c^%TYK6QVKb=EQi z8ulAv!g45wHE<%V;AB|Asd{s-G6kpWQK3_Ce?2B_3Lbpzkca9ap;Pd1Jtk}l9?>D! zPQh6g{PG1{z4IbosXm;)y^O0D@Yr*;@0}-ktOmr9;9nPJ@gPd#AZ8=agOD?5!8x?z z3fk~*o;^pa!v zwIEi$!6=P*0>7iy{)uJH0#CHIQZxU|AAPiOc0lqvhe@~5cF@kHolm=fmfFgHZTJhX zO+0k~{>uLml7FLpQ3!q`QjGiGN&G6~}*flIb+l+h*y$FPXMU+9qw&4N^+mbPJ{nbQ1yNB$+ltCo|#Aq-jA! zKr9stVnswmHlcv1rP83NSi!Az!Ci6RMFsIMP=D{+;^|B}wk!grFs`d7nN6gcn>O~RyHkk> z$`qIH6ZTRKOsh9*WW8C0R^ z174<=R(mr0lij(V2qw~7!|y3n&^_sn-b{CbmF&!c2fZLPvG5{TJ)+O)OVdFBcwBzzh$K{od z%PSq1S28ZIbX>*t@|~Vv8S8X2fK308qwPvn)zuH*WExX2wE`iuDU|2 zzxNi6Y1VkV#&oOg)RW zcWT6J?YlJQTdh-Lfz`S-7Fz9qMxE7qH0mvTtww{rm(o~dwY0`!tMzFtv38zDqrI2Y zXtMVXYb>?e5shV5yIy0twR^Wlv(?_C863?#-m9_FYPV>tvfBGJR$J};8f$DTw`*Kv z?|neyVyk^nqs7+Vsj=2-AJVwQY9H2EXYD?sajDfls$TCMg; zjZL*LR1bK5l7@MzD zU>siHc@XdGOC8lXhiy^b`IvDaww&?nnQ^G0USNf^SMg zG3SsO%C{>p9_Kli0#z7o1m97p8S18R+d$u|z<2R|h1$BdVvs0U3_rJMKN&xW(*B1E zYCo5{WX+OkZkBXB)pQ`~dAU@RIsHid7(a<(5`L=CRP={zTC64fG zBKW03*`5tsd9AB&)A%)h6Ga5SEji71_UG){{+2$&~&o2oUD>tXRQkiTrebAcn(Ab^n_qq~W`0T^#-Tos}TRO$=+R_Iy+*0Na!%>L) z77SW7e%Pi~<40s88IO%*G&Yj4*hofVBN=p!WXLs=0oO=|TO%24jbx}bl7ZGphFK#S zWQ}BqHIf0=NQPG<8C;EIXf=|7)kua_BNE<8qrr;G3|7uF&? zLxitz;jtn-Q-t@p@Hi2kCBpk$xKe~?W53|-D_yusgy)LzRW4jD!t=yoU*p0xB3vuN z9WFdxgk$2c<1Rcwgy)NJmkUo6;RPa`aN$WJyikM>y6|KXt`p&;3r`W@dePg5TzIMo zH;6s=y6`j+UL?X97oIM{i$(Z47oH))OT;;6U3jJlH;O&?yYMU#ZW4PQaN*e^yi|mb zy6_wkUM9jfxbQp?UM|l0Mi;IX;bsxO$%SJgyh4O;cH#LVyi$a3b>Rgfyh?;`bK!*| zyjp~hxp18buMwB(xC_^d@I_+Jcerqa2wyD1CtP@u2)BsCzRQIdi||?zzT1VDi0~yM zeA0y*MR=V!=X+eZNrW#I;d@8nFwzX;rm^9xd?9*;Rjr}S%h0f_(2z5 zA;O!)rFz(fSBmgvvFAr!c$Elm5qo~jg;$I4RuMks!fQnM2|UTiTR!!UI*Bkfgdc4< zgVTd}_BlL9?aOEI)j_;yZw=xb=kTqwxGbn*M^MGCpo%MkD)t0b?6VaY&fw+nAbvE6 zpAF)blJWiOEUqk?EE>e`0<5kI>fxH8ijM!Q-FVTeYJEW8T}7LqNhFFURdWKGIastA z6=0IICLjzW07WN@)#=d z5UTJJ{1@RG6~cHm9TU_BeyK`elDZv})zg@wUdB}QDyD_TV0x$#GeVbRX6RbX3f+m> zp;MR>I){0oS5O=JFJfi2m|wO93(AsMSat$+Wv5YJb{-97uVYbpH5QjQU`cr^8q2Rn zQ~51eTK+hem7mA*^4HKDuEL6NGggM%u`1k$)#2k<6Mlqa_wy-}?9r3Yr|=NMQ}`W_H)IS=$5{S}-xqRNGXWl6Aotj43w7G_$rBv*3mcrXA@$B)Rln zE`{_<2sosZa_Rlj+ok7{++C8(rCr+hBu(Abj_16|_e+ePH1GZO^z>9lBWa)fHKvM1Yj&QpW*dPnO@f!p&r&dTSUJ^Q7ki;#;TY|%c zA~8eS67Wc3x*#N{6$XX05k6HEY6ZW?H%5f?p)4Jz<@nT8p-d1JiSTU(K3^ZkS0({p zy-4LpLi!kM`bIOo%$nY4rbn#lt!BC}!0=U~-!7KE6YwKiI?eac(S|^pPtX+dcqC5} zQ@mf=h_o@*bg!9SW=+RtdPGl$f_VZg9SWA_(+pEa@cWwlW31@|%=9uno!|^MaU$0A zVP?9|V;a1KMFHGQU;98)nE&#U1R{th#Jj5U3mnO?@ynSFMVbYh>Jw1`)4 zSYqLk#9w_Dy}iu8i656))3Kfo@;+039`O167QOnK?PH8JeSn^xlUC+8Eq^27%0Q@q~XH4f>e)Go*7)1<56C(n_QxPwDniL2>xjwdwUMQarLaS_)^XnMH!9 z(wA1dHn(=|?#*4PtMd9u(s;2>m?cgap{8w_JKf{+?d(b&EG2syd}W0>K}nQGqz65@ zTN`!{Ds5gpX~Wv#OVYNK22-S@5x&gKWKm72pVqu`de?&aeFp%Z?=Yz;JuQh2C}l?k z<=QPHclB!;n!lkaz1&+^6ddNsOG`-`E{NIElC+eXDeGIH9#U4#0=bk7Lr$P_BNwjA zX{t;w&Kw>}7YF*3vb11uglB|LnY4ORUAW(1??hP?%Y&*gDYLI%k!H152%hB``B@~N zY(1a((hQnU$;d1P(#PrP*-|x4FPh(X<#;u32eiWKk(mk^Ak)(33du#axn_D9#S5q7(upeAZ;@ZOUq)t8&i2aP8KWnz%HKlr8D-|=JJgRBHl=cO3R{u$Zrh|PJ_BHHd*wxT)rm07em1|vjDXI5edc9}(Gl#3Q zHqDV|4oDf8*A9AYAFb;#pOtr9^~{dSP2-523Qas#PetpJMz;(u06m5rrt2{xC~5UO zjrv8-QeFQHvAO--3A)s`EQZxw7?g>Gh}@{&-Rl%6%J57>8-thFn{zI~@p95j0a;Hl$GJnBz?woUrf5u$cV9<`{tpuJ%!X$O<^c5s+y3~dMP;eNPu{NW&{ zV9maV^$!JeA|=by(zd8R$&-P%k57VjlAV^eWR>8p%pY7jVQAilj5MEbLMYDz^)#w! zWp1P>zhgzp8X;**x*X-? zFJrfca>td95w=0ESwUq?w6Di49;x#q|6xIr%dobd&mh6$;_OGRu?qPq5aXM4dMB_MokQQ3I525t8&6~`t=3> z&(HLXNL#UJ)ui?^IcvapL8j09tjg&u5=r}-Qa5Kf>rXsv+>5aKNfT8|dv0AhLmXs} zXL_d4aWWE_j~kkaKJu2dltH=cmn`i&VBwnl^_BTaU=OI*-9@E~*5`oq#X^(qH zK)o-l5BFf%<( z3H6;ZqDb`2pVfCsC~aD6=>#m$`b({!2DmAtUmi#8K*l{G)fOL=CJyqA+t@T9pY&5* zjq0>U&kWNqpglFM5dFd0>SYVX|^Qb?y3@OO; zj8|8r4kY%yqMUphW0*RM|ROZ>8{I-S(BhP!fR zd*xDSm-aZ=+2AMreSecbe^V#4Uo)<^I|GljL#upkS$bdaGyQo^xNN>np4i8lKke5? z1e5AESJ3(r(|qHm(|Q*DIl|!?d6}8M85NnC;y7u1x+oUHIMg>JEHBtn-LG%oU@7tc z>=F{=!H6s2}y`ksV!lRc`%i*_Te*8S}R( zEpyTbPa6;RRYF;LiX@3E{nBAM^MfNj5$ZpryxYbNn!dg=b?}Pj0r?vijoj7HJYagg zr^)$wP!jCm^C6ImD%|V%cp_AnfXQO6B;>~^m7|4 zXLod!ugT5y%(CkP&-)7{Hv7pFR|6mG&%pn(R%-nj>rcUdX@8hsJP-V_Hqs9-vB#5O zMI%>V#3Mx3p~TY*o+^pq?|U zf<_2PX8Z!`AGPw8l@)4kY0k<~&}dk)(w4Wf+P2m;Zr)hm2Gx=+AfFM{R?dJ8Sn4-y z2m`}-SQgVFHUzR7*4_>blPH1~h5By}HGvU|T40rJTSrz?sIILgD@Q<+%5{qw>u-#6 zVue)zswUjFAyh|J%fv_vRG1-G*hy>y>7H!_FjZS@tLkiR3{QsSqzF7F>3T-X0F1zN zwZT7a^}x{@Zic{96)Y7HykjHW6l#b3YP#Ax+G-(M+qt2py(82St_e3=k%%7xQW|;Q z77o?dgxlI$+G-+%$({zrpb7P%4ps z6v7A*@Cn19MU5?Wo52oL8yx^jVv~l)bxrjosjH2G`?Y9Wdk1K)MK*LcHiCV$*w#j< z7E=sLX>t-1SRS&P(qV`amWRyh3Mn5|9XusB%2RSd|AC}zRR2hGO?_Qm6I5yg^oKRg zb>MK(52?fDMM*`Rq{u@mH5rzXt#GZ8I%`&aqMm8aLp=~mMQqr-twW2Z6bGwTusG>cczoI;;7if^5}hl}f<}8B;7Kl=S5*@%E?!zQ589|1D_;cp&}U1R2CHj| zOBPqngW4r2rSpI}SUImI2kfRNRFkZz_(T-Xn6~V&t63~#73OaI9K}$|5 z=*dY1O*yHcD<>7S<)nhXwz4h^RxXIPCrOL8CrOL8CrOL8CrOL8CrOL8CrOL8CrJbS zQj3d<7S0$SW+vs7ym>7;B4q!p)GIW)^zfhucO1VN_^ovkEj>GBLllFBTm<59b6Jzrl< zn5HrFTC=uRfnQ^VYBLL{S6RCD&|Ya;BEuzR#9B&uMNQ=@(=4MOW3YL?O z8)}X~7;)VSsY^>>!dC??UYjQQh}v2kO4ev*3cnU(mZ&OQShBRHyrdNHOJEpEC;K?q zdwCWMz{cZ8Tjte8WWl6hj3q_i`oZ{NGTV2w^|3ZJ4+sHRu+TP(bT)THn!*!dji9p* z_KAcVi$aZ!mGBOv2X0y@i@x5K)Db?OhW@H%cyu?bdfZw)&?w5qR( z>IxQMp|5b5U&s*p^^t}Cu$U8SZEb{C-7F|{Po)E4RT!9#kT3||%r``u>#;CI=tIzk z3TRN2IN3?Fw6nPiES04Qu&$ykTvWWQyd(=Y_C#l8<%L{^3rF~bOaVAO@V@00M#4bQ z8fptQh2hnol)s(U(rQaBvUa5*NG(~`m}PgBH@4Ilh3Ynjp^XfWu8|nmhK8Xq8DJk6KY!BCMOhw1 z2bf8AeHCF2uh~MEY}F8=TIN8-Hgf2!z2wDwBkUIQ3ea;|W#OSF3skHuSlP-AQH>j@ zSZ?UfO77~;ABkQ@Q1e47Bobpftlle9EenH~80M{>ap|ULt!I5UKaHidEghPkmdPXkP zx7E-jt_yHoAr~sxCScY*dBibvRNd#Abx%l+Kvdo5nsraeSb;pKV86CZ3yZ{F;Yz!T zsz|15 zI1k+XWxUP~1{=g9Qp7G%*1k-m2Z>$cJ!67sRO^3(r2!uhi10gvGQO+~jbRI%- z1fra0vgtg8vVu`T}{x$pPxuCSX?mWNy_@AvMb!n2f1^w~N!KY!oMCY<^Rqa_OKP z>LOo%yuv@D08Bq1tQ-KSYz=^XmhuY!jsh_KVhYzUra2rEYe za0WW8hq@X`zxh*?yy-SmxNb8Ad_!x%wVm)q4z@E#A((zdcsUw?v(O@FeTXPW0hoR@ zh3i*SzlFi0@}}2K;dh^8m_Tum;antDt zBPTz@>Ds82-vaqXBr520-0jjJAO3bW^!b zHx)dIxqTaPdl8~G1x%kKoE!zfle95Ib9;D=v>}*YHTs2{Ah=zAW_Q%X=kuf_sPA3389mYDNQ zuzn_T)+P)OO!3>zAOw4#SLdCEc5jTsk(uUf0B_q`OGc0|luT~fumO%jLZ4_P0`K_@`~omz+g8}w)DYG*95%Wv zrjfH1UfOcVrkvS5u*@`UMBUdOqq|nfw>kC+%}Yu81ucnGGt`7tAE=2jW=-^<85XY) zuO!yLidvwtU9*6vtsO=&D87~g#lMyn|2kM;Zrci5%QnMqzNSz|9W;-8M?bO`CZ_95 zB3RHk+4d%x#7J$yo*Qc>P^u!cR0bsV%s4S>$*AnGc#C)|Des>lhq{*L4Uq=;C;@BG zH4R+?+H97C?FKWDEhCSS#;GZ%XHl9!D`LC2=+3cp*iHz2VtX6eLbauaY(0YJ&=ig| zbk%jVHP*DYG}1N!#y1l?V0oX8nuMzn{2&ljA~0G9$7sKM*|2z*csH@~J>-iUXZWQ} zC|p+ut0Q%=oB+0{Ck-6@*h~bMJH%S&g9dwjn6b|@E6T|OIM1TSGyxs^8$p>Zn3Jnv z1I{zjx<%sgGATPTgVG+Zuc;5$8wO#;hT2@hsZ9=~Q+81Xz~U3)lccJiqD{^;e+`-J zl3vuPB}jofd6w15a|Sz8jN|2wga)?f6)w!Z-{S_QoaQs2R;6)MwB`>Dw$}12xQIV|Q3$)PhE_JAlt9A=vF0tYimtb7^atLqiy?J3&t!L&}w_y zZ#cgv=tE-E(zn4fjmQ*!IYynd(%?8B+R7*&MqP|b#%LR(QZU-is6H6&U{o4LI~kRM z(Jn?EhS47w)gPnXj8ZW=icy0wI+{^KFgk`&hhuasqcSl%j!{QobUdR*U~~ebMqzX! zqsCx#5~IdqbTXsHV{{6mCSr6dqjE4hjZt|RozAE!80}%yG>pz*)C`QyWK;o0XEACP zMt@|~9E{FpR1l+c7*&MPxr{2o=sZT1Vst*E$}qZsQ427-kWmXUx`d2&1bRRfo|vj0$6PEu$JR zx{gs1jP^2WGe*}lstKbT7}bK&jf~oY(M^nM$LMB8bz*c2qq;DQRiWFAEPe7=zd0BgwX?xx&)&`jJgb?2N`t*Mh`LSDvTax)YTY0!l-L8 z`U|7>V)Q7ZZoudrF_F?xwnf5GTwMm>hnD~x&qqgNUA6h^Nx>KTk) zXVh~Ty}_s#FnW_wf5qr6M!k&D+l+b@qjwnfI!1qE)SDQ+%c!?8dXG_m!{~iRy@$~U zjQRkh4;l3lMjtWi6O2A))TbDI!l=(N`a7fkiP5Kw`U0cR81)rKpEK%fjQ+u>Z!r2N zqrSuFUyS+zqc0fsBSv2`>Sv6;V$`n~{hLxr0!Cjm%7f8=7$sr!4Wkr{zGajTqwg4% zjM4XuO2Oy{M)kqyzl=)5=to9nVDuBC4#VhYM)k+&7e=WV{mQ68SU`*#0@uMX>ToQG zjLO7X@gQNod_d=X+m>SCI?r0axkLDBI-Dw^!;p5(6f2&+r~C9E#}m$16@U&89r ze+jEg|0S$0{g<$6cIEY3>==`N#)%nq7|+kiIx*SN&RBTEa@2{a9vICtH;gf^a>n^7 z#>X3XEyt=D6R%f|K5f;5e&+F%9`rL#t@NND+ojK#;#!z2%J;-#Oj6=jf_d(XVey7r zcEn3N4#wDc>8oxVV*Mo+)EY6F6=b=cpMI;1xqVHI++GpfNUH zK^d*LCWkma}j@mt8+1$2c8y zrA?EbA7iY%nWClvWo1ppg%P6LJkQ}YVAATTp&Tlmjkk<#49A%?D9d3z#>;Cr8ZRq~ zUhh0-*BI&1J_hGdm9%dlC;ocOm~fJVfQ*sXezc6qnYbSFHI5DT2xrb}9V}=$WY}ZY z-I$MYFo}UxMn=e+jEg|0S$0{g<%1^k2g2(tio7gI!||7PEd~C}%DLr+~?MW5&Si z(#SDkcJ!9<@VYde$GJ<>xyX=72MAujPnbxz&(1P4KHfYpiqA5Ghh;3$Mm4hs5Js!aO@3Unl#Ka>kbnpU?Fj6|kX+ z{T6}qU1%8P!7m%Y_lUp3mM4q2b|o4{Q_xiM_!ZbNVR=mVYhW}3<&%f-U8;al@Lg&q zqu{&LEJne1soCsH2Yi=0lBIoMhhy7DQ4kdpIM~Th#3$Fe+i9|G;Q2OZyi_ zrHuL#qj~Jn~lBKXCtgXHPoFwUG@)$PQ%QGX* zk&fB+oh-|-G)!JNj&2^YuG-kv(nU4^DpG+Tjg@Bj(FDShO79lj(Ak{T9PT3f zPx`WLG34yD_QM-=*M^kEc8`xWA@x(+WpMXlU5H#oSrux7!}KNF>caG9N<}J!!X~{& z^eqN8_4cx`b6b`o&4tX3CPb3RDSv66Pb!tjT|7E7YaNQT0Jg#aI6dpmcCVP4umkW| zS}0ZcrE+Nz7E<930?2g<_`b=;?rl({O0XTf1VKPEtOx0}iyf>d{D4b48ONoo<$NWB`2KCZo`v#l;1Y2MH>v67OY zDmc{^FY=MXTgtB8pHN0N+<;Sd_@y?f6Sh}Hn%FI-rQ)RvpyRR7(#PN04*3DpcgL(s6#k zIv&n^=<3-S73oB9se1U?8+H-L4s$b}eJ^e?911tL&)H+~D~wpjl(J`SIYmO@uynF? ziXWQfsh0LjMkGZ#9d=S@)wRHp13L1`lUV6Sr`Susi8fe4FeLR z&c#BIwejWJ80ONDQ)QtHG-S~;|--D z6kr1-r6IJB54jjFT%|oL>?;?^9$qq$v35t1X7KRarG2EUx&y@R&lKqZK*L?C?X6h4 zlXO(w(m^bgGt9dMwA6ZjAYp^CsT0)Oy`)+MS1|rV0en2Ok4beKIxG3 z5R|ial2>{pYN*gUH*=Dri*jxXhEaRC^r#=u9s}bp!_pI^JI<7z1Vp|;DEo#; zTU$rtM0&Y2c>I?V?AIMC!G7I|97EZd&HOd@d_wvU@rG}(u#PGG9pnp}(rFWfP=L7} zr6CliYBYqxG>wLk+}}faAQWI)M`;Mf95`es(>4x-m;)`H#elFkZP+dqqS?!Sc%7i8 zmoXOVSz0O<8WsF!&(?$rnRe$bhIn-5q>#~v}74vrloBumPb-Al1GuO!9Xl)AjBLn5sLv~R|Fns za;CY4W6+9$*^J&>baq4 z^kiCw**LMtS*9eiWW{(-oCT8~dKTSrUXeEA73SJ$=9PoNp zy+GIt8j~;`3)@*C;LNF*18sy!0%4Z~oAt535KV&DUDg)*ddw&oye(6e-*~vuy0$CjR_Nm8EisBsfpr3=Mn}xE zsj!;BOx_jqY#JjYHn$M@ceF@O`l8IgxHoROF+;SXtz~IScBZ z^#Sw=yyRl}82Q*_`Dpn#prq+=8bm(9b|jW_=9&t@u}-fH$2yH)KQP?Acsp4Vs$-Yq zS9ZXUDL{*Zsq{#r^KfFNt?+c8e44xm4x+Snwr|uf^uEqe$Z;`CkuQOxjKBgOIGytjXPJc> zGbQt_Sbu|-FOx4%mM@jBfIdjipZ2CD&7DnPsjIBV>dXh!E?4{HKgrjSTMCWSOYky6 zez6l4A|^(fnmRj3XFahz(hhIW&~sep2Z6nCw3@vEbD6dG8TwYE$TvU{H^K!uSiVUJ z_~jero1q#y8nZ(5MnAGxas*5b9N<{q@~!fpiS%voKI*_+5rJRWkoS@I(H^*H`S<(e zJLCi4&0#XSx0BOB7NhI0(yOq1r+m;aRmpcj_swwGF?U72haU5asg+n1H!1WTU%t;T z-z&pqLIIZ3LUL@jg#5~aA|HyQA#JG-`Q-=YhcTK)PgTi(0T-^x!SZ9o?Dxu#dl7V? zVoffVpJFLbdl9_5h&6dwevYL)??o_@i8Yh4{8yIpk{8W_BVbIEHtl}S!j^5}cI^sE zMSc}*Qrohvs-+B8a2v>p=zheTOp|Eo1z3Jve#0-nCco)Lu;AwJY}Uo%l&TEN@5p~6 z67RyR{0jKx*)r&J;L=0OT#}>~Ye&`~hxg?V$Q0m1G6nbs9A9q`RyIZc#MW#7UZd=% ze);e6XI^w9Ib*%b>^ZD2Ib`x-{aF{7#i%lwH_K$+T!`f_Ne4eb{>qDjUR2~o#a>hb zlPaU@)4>Q3UHp^3^Pvp+duXggGDH3^(PFL_!T+URG|!95ylB1`E%2gpFIwnD6<)N+ zixzv)5?I%=nk!3DU@^-4$qQmanuC(;Q~U~su3u-TYsS~+GoRP9BpylAx-t?{C@UbN1OYT*2k z_&4Zv6<99*GoxU+xSS4Y$`~wOBwkFOj1hlYgG3w?mjdsx@_s*XoU* zG%Y0uWRzTt)}s(Co-32RsMd?>;4BTxeL5CHVlBxtAI`|Iw3%>5hEcOIs%LUXdQsSm zHo&%G~thD%*CZ!ch40AXv7y=8Sh|(f(@xNOS2|Q!CzgFI z=_p7#IvsgP(g2op93&l|j*^Hf{bL8E`eiUaD9TAN2-6`2W`<@_ z%m=h6SNW7H6<7sT#Y#U=Fc(ZAt7-7dTkZ58tXxN5KNOhsu@xrrR`S~}WwG}hbqEXRGwLBMT*N3?rG(7t;q4qNk3#nfnLP$yb6H3G1Qsr3 zY)`?LTbA~WW;9rWtdDGkWk{?%N0$hd=iwVCQ{zSWvdOq#f@L@57WhZr0$*O42fc>n z0_H()fCs&qj%4LxEYD|2??BSu(vd=v7OD{zv=5dzsTy7%7H(u*$ym6BQ7HnN z8RPzXKSLL3j9w>d$%Zu*@L?~ks*m*s{K^3M+#&2^xEWYDz^KEpaF9{`v2Y)wR4hEi zs6kkGj8SmJ@@YoFBHD9|f+LnMG764ZzRV~%V)+`QVER$RN;U?|5o$W`*gmp%Tslf6 z)@)}<6Cr6*I_g8Lxte-|7bf3Z*~2ODaB4aVkcVs7!x>oK&K?%P!n>3AOIUW?yrP%335Cv;@9zdtq|2j^#NI3-7R;=95N3 zuPwx0GV_w^y$iAM9(xGijz47762Dwb>f#d?t%9u;bi(6Zj)i})w3S%+icxSYSemX7 z?WT%CFstycfseUH)f?%g_wugudDnVj`jEjHEER7EM!_!lxqzkN4Z*gy5X?$uj^;4x zU9x3vp}+U80O{6nJ(VuN-a2nR%!R!0x^C&H3t>rB@24#gmEkRxLC`R0gC8{Bh=p%i zkvC!CM@BVb5izP6ixQ(+vFK-18y5R8ssoFC8MPIQDxJhK=OBDt=a#t0#jyO>!F2$5X0%wj|ra*HyH5nafg z$Sg*5A$K3M7}14XY|LUr7jiQ(ixFMOEyFBEbRjnevl!8Z-2O{rgb>NqzAQ#`A@}yO z7}14X%FALz7jok+ixFMOb-FA@bRl=;vKY~YT!hPFL>F?)EsGId$Q8CMMsy)J($W|q zL~^|>ixFMOU9l`ibRieNvKY~YT;s}OL>F=;D~l0b$o;A;Msy*!rLq{&h1`A0Vni2m zlPQZ4UC6bhG)4%K+&Ri(L>F>}D2owY$bFzJMsy+f9kCeEh1}H1Vni2m?!z#-k+h{%c>8zYcDck_PPQqveT?>NqbGu zUw6XwjE&b=j7;?x0>)ZwW&sNV0y>8S|69NB*xrWNFTvV0j(PbJ`uaS6pXf{K18)y7 zj5N}BH;d}nr}$7hO80qT9$Oh{XbwUD108u%5xr6@g{~_v47FB~7ecb^0UL5EI-6?Y zcTreMdO7URYFrK%tC6^t7+?iotpA2eJB&DGuo0<^Zl)qXr{ZV(dtfFGs46U)kzcr3 z9-%*F5^Qd6fuC3k z!lp$U!uCWO!sbL8!q!9@!p1}zuFyi*lt|;SC6R`(A(4i#9g&8x8Igvt6_JLp5s`+l z4UyUhR&r<@HY3sywj$DWSgE0L*pNs=*p5ikVReSaVN)UvVM`(nVM8JfVLKuX;Yuqc z`20YNs0r$$ncBCI+*t)_h2)wk8p0h>l)qE6|5h#R(!y<8xLpf(XyHyR+@*zo(8AqX zc$5|%t%b*E;jvnHoE9Fhg(qm?iCTD)7M`qyr)c4+T6mfkp00&^wD1fqg!_P%&J6iZREqqrC-_yePweSNi{7?%&(!!6m z@DnZkyB2<`g`a8R=UVs=E&Qhz{!0ttJ|S8zxJ`(LaF-Ab;U*y(!aYJXgjC5R ztA*cb;rCkjgBJc*3xCwYpS192E&N3be`O)e%qc#M*DMsZ(4&P(S}19utc8jedbQA} zg?=qe)DI^r$f_Gar7J>)A{^;Ufdm;ranM#@D*QVP zkR|vD_k5uMQj^heVWuz(`dY{hO%rA#{Cq!jF=bgNXa9NliI8bhh|PD;W4O1Db&s-HT_R(-XGQgu#B)&I^)9c@!8 zY$&zCNvVe4S*c@eN^LZhia03+dsp37Ut@2^z7uRpH5p1ZJ1N!TUa2j;QR*a{Qf-D( z?M_O;j#0Ok+S(hXuCyuDWhk}HNh#O?>Q<>>vGImD+1l>JNre zyPcGRjj6w@QrFv*I@(a`7$>D*5A5%%)D1SJjx&@x-bpF=#{0V}b+%2Z6Ah(Ka#9Mu zE&o3%b&8?XsZL74hwR@~sdH?WI^9rekCRgHP2H_hXZ5C^vMcpRL#eZ!l!DLuZk6iQ z)a6{8rOq{!I?qWd*lFNasa|!ScBL*bl)BJKDcJPzyDD{_%~BT|N?qcl6l}5hU6nfD zrqpGIQkOd^1-l;HDs@$F9Q|gSQhzd(y4p#pYuqc` zQr8Mw>;k2)#!n0uw3NL;BW4W*uPQVO=7xwTZUdUU%_J!2^Ktdml( z3(l=ly>j&ZHb;NnQ0fIIrC>vzTcvvC=ys+4YAE%RlTxrZ(5+Iva&)^=uNX?b>ZBBG zQ*^6TuN>X3)a!;)Z#XFhdlua))vK}ZVVh6AWhnKwlTxs~(XCRwYJHE`l=_>Y)Voef z!L~}bO7+T8cBS4ol={F)sSn*N)vGSyF`K16GL-t*NvTiVEA?q_di2L_N_}Q1^|_N$ zu+i0R_5G_iNI*}uFP)TvJ-2R^`noqtJ!wf4u-YE67O{rfDrG9l#itH73sgx-8MyY44N{Jp_DKW`ODcH8`Rw<=7 zNL>dDK*$oYKW6ku-o3HQbMmLd9T=%I^0ldn3Gbl z@!zFV;t{>E)T=h7vJ9n0I4K2Z5Zo#?x;IL_W>ad6p;We$Qg9r?ty1HAqtxp*r6w3k zO>|NUPG-1ODz`UEyOJ~@LUj=ij|s~ zOJI8eDk{6hkeyZMmE zBmjA=c$`*n(=o?_W1hmtjCIW8Ny({Wo?vy%;2Pq2GzYkX1a>o%?qo4+ zhE9Uen>}do_=Dn~_*rB#9;2~&MRLG_Sl%m=BMxMPvsb(vGV^E+`Vv~C6b~>4fF%GA zNzty3Q?$MOd}E7tjZq)AqFrMY?RxPB&8N(wjU5L?yN#bkY|(Divha#G5$n;S-3(`A zJbICCgv@S&znf{1ZWs4y8FnBA{zE7=8!}XrR7sT&iudxfoyRyu)<=Vkcn2K)Ar?&) z_lx(@Y*WPpBwL!+4HT)TRPj!rBuX6wN~TJwGKdGn{qT1H{<`7sPWU@W6}+GCp%3vD zi}lb4h&^-v0M7_Lz@lnmpevxEA%fk~K@cF}|*642@84kdW~^;@>!viVyhX zt!>l>;Sc$i|Aeoz8_T0c&MacT_$eRJrjI#`K+T*&?H50HSEzr8|I{o}1O_E04P@^Z zzjzEO*>{Rx6Ot&y&VhK4kQ`^~6%h5Q7hEyH0sM{u{ucnh`yT<}P6ZC&FBH%t0N^kG z8=yyon}^s?V9vV69uPmh9SRydwT!7pdXiH+QRqq1dI@^EMes--S!+oq^q>Rc=kB3l zjIlwYPG0SLysl~&ZRHC4-3fPbg|R!~ZCv40cf#Ab!U1=}JGjE>?u2)8h5Nb_-o+K} z=T7(!T;T!kgm-g=2f7nJiYq+Wo$%3I;i2w?kKqarb0>T(S9rKP;p4c%S?+|7=L(N> zCwu}|c(gm=6S>0K?u1X`3XgLqd@@&ff;-_;xWbd%37^Up&UGhz8drF-JK@v0!c*M| z@8JqhcP9+@xoBgaxw^35lkZOWOs?=ucfx0Jg=f1H{v%iTNO!_#bA=1t37^9iE_Nq; zE?0Q2JK^)V!t>k-pU)MZ?@ssvu5h_K;S0IK74C#D;tDTzCwwtic&R(#OSr;S?u0Mp z3NLpjd>L1Gr90uvxx%a5317h#UgJ*qO0Muacfwb3h1a_i{u5WY)}8RxT;Y0m!q;$x zPIxa@xY3>P^<3d*cfvPtgTgSGdES z@XcJ|t?q=T+|3m})t&I2T;bE*2_NJNpW#mUF0Sxd?u75=3ZLyx_#UqC zx$cDT`wRruJEPqgb#6rFLx*WAXoTGcft>Gh5zJE_+hT_ zHSUBT;R;{pPWUfe;p^QAKgt!p(Vg&PT;ZGD2|vyizSW)Z6I|ij+zCI)72fAg_$jXN zes{u8bA`Lz2|vRXKIl&PS+4Ni?u4J?3g7Ea_<64I{qBTc;0hmdC;TE;_#t<~f8`24 z;!YTTbb&LWdDNZo%Ut2d-3hY?e=@#a3}mXZq9GH6MmN~{Ej=}_qf9Ex)Xk% zEBwAY;SadNAG#C%kSqMLJK>MG!hd%s{4rPfGk3zDaE1TjPWbO!;eWXk{*){Hr90uz zxWfN-C;T~A_&@H1|G^dh)}8P_xx(MO6aE)h_`mLizu*f0-L_*<^9-<|MxTw&}^_D?HMju*4M}?M_(c3TL|$R=C3B+zETR!V}yH`?$iB+zI=+!ny8* zlexl^-3eo^@KkrgDO};{u7s0jaQ88JyuIJYl$6hh^d|sWz=y;MK+fbtrX~P6iw_w{ z0CF}TGCcvvIef^z2|ymnhwPUCWRMRzAOXliKIFgzAdC2rgA;%(=0grm0J4M+IV=Il zxqQgs2|$+eA+r*IoX3Y8nE+%NA98d8kn{PF*$F@{;6si}0J5A9IUxbag?z|K2|!lx zA#)ReT*QZ*oB-rvKIGH{AeZnVrzZfplnjd3K(6FN&P@Qanh!ZI0mxN+$oUCCuI59QCjhyI4_T1_iidgb%qf0mw~!$V~}AZstQaCIH#Uhipy&vWXAbngC=oAF?e0$QC|i zM*@(oe8{Z{KyKkfZc6~NjSsma0mybful|DFKkjeN+@5`esk5BZM-AaCYF{wo2nEz`JV(JZ{tILn*ikPe8}$;fZWH2{BHt~ckm&9N&s>{AM%$3AP;aMlTZSX-F!$f z0mwV~kVy$Z9^^yH2|(V(hx8@@c{d-@p8(`Nd`O%CW01Rx*hLyk-U@(DiV=ma32QOl3wEozu``} zfGhl#JK>pJ;dk5#&*BQd>rQw!_Y{rGL)b@hbN&cURQIM$AH*>vKX<2g3AfDubSFHQn=`$EI`(4b=rWgbg}-u_^E|HFU%L}7;|hP{PIx|7m|l|I zbD0-#%lw18oXfd6|L9J5Ay@ckcfu81wSRRdyoe_(3GRd!bA>(bgqLuIC3nJ0B{{Y| zOI~-vRa{}eJK<$qVeC$LIk(KI?u1uxg#+${S8|2Z-3eE7h5Nb_Ud0ve=T3MvuVF|7 z+zGGY3J-KAyp}6G*q!h?uJBNI!ZlnE8|F^9mTT?d?u6^O!ddQw!`w2DbSJ!lD?Hkr z@J6oM+3tiRT;XxN={t6O{6=`O?fq9trD;VkG_i?j?U&0_+jwM;nIv{@cn`QZH+$`a@GDwyaNS3n? zh`;!@* zsarbjkhI5S>mTbEMQ{rcPnT>IH ze8#Iu?)j1`(fqGfC5r;GDl-MHI3!(R1DxRisF$`YU@h%+x5Li{VKfL0m5R{G=mK=H zR3s?E0AUcs+0V6{j^tm_P$YuWDpENT6shP}_)Q``?op&Yid3pdRllN6l%#Q)oQf?C zxUZo91NSy0Tez(f(dniX{oNQpZG2nNPSizzwvYTI)KDZ#d!_5)NirHN-GHV-)4LdX zr5hnF37rJxy9v@f!XQYy8Pa4yLYdMnkOn`(By5s`j*MTG_wSP)&XE4nEj`{XJ!KOrjW6_^ zjd5Ij#usg#_flNX+hYS<79a368)IdB#usgjb@3VB1Qp-bdWU>PRcIUeo2ppah*$MS zHBw#|u_MqCKNr$P*fet4o$RnRFugl@&jPhGFd%-m?^FBxR39zXhpNv~D!=NtmWp_o z4R%C)*cbKoztg7Pb&%V~@Ml$TSD=4<9Hw5fnoQOEyP9lK534v@JzAI)HHC72rlwf9 zQ`J-}H}v8cCt2ITuE4_hYOpr&4`>6>7@(8Fd{Y<0#SljA#c>^VI4tu&tyx^#*p<4@^fIUQ1PCdgVL|) ze1zkmSdpA~tY{-pssox8u_r#T85?eyvCl+-9)PXjZg?e21|$zUKBv;3BHSV7p`GxP zfV=1zeKQQ8WQ_j77^DA7$LLZRkAI|N^kf*Le zdX%kMbHpden#r@p)iXMAL zYZtKDb+-tU@~DP)6iked76zhYtdnCo9h{v`j^zw+b^$#C4WKWik)1U|<-;J&BTR?1 zevl>$!=X|1hcq%d{)E>k1{jT^9vTH8 z8B7{FDKIUr>hcI{Ax{d-j?X#T&N(J7r(_oLq<{)+`b#am=80$wnvM#_ucDKvLy{k~EkLq7hC1YE zG+5524*4xO-&pF9AAm!SBMwQtisyXe3;M&(5X~m_JwFJPmuyck^7LBj(X+$o^B`pE@HRyq0@_E$c3Yff% znjE2WUa96ArCI^`6PWR|RPr#6+E)c;#;9%o0o1E3RvgdEZ-J5D!dV@2x# zqSv`$%WF7FC2Y%UY__a0Y`I9Yu#^D?p7Ifx7w-h*7Q`ibq-~d8aQRU z{`V-`^|rFr7-d`URJKr0Wvg>2o4kQjwi|wrvfW@STZ2)yjZS5Y=w%aBn46IP>kH^l z*n-i=)-jkz&QXEC@>q(LA@f6t^Uy(z-u*e}tMUWs()4#{Ge2W6;4+u>dkj?7) zPI-6sLHT(2I}!d)$=)ZQ(JlY+K+;Ru;C$!6mzpu~rA9ulTfQhmzW6TrN)I|Dl^;lY z6&SBoy5;N1=Y)+E_;KcQ~V zhgCrOe7%}Xo|EN2_B@49x97tOAALScO(oCCavOUdAk^*oY5U}EHLY8|`y$l;9{JvC zRZ;zFiW<06ejq<-FB-fT_1TLseD8s;X?v099{Is)Rk~AtkPFLcWvX&wPV09KvpQl$K`HWvxZqAw+S>-;=J{)dVEVGPI@-SWS6$=T78Uu%+A z97y`aQ8E}U`5#mAQ%A|dXvuF($@tqYTjxEb<@;_xLqG^jCtn!8}0>fgIm~R95JVWuAO8m$NiS>#F(I81C z$j?@gI3+2!$wNsbvn0Q|kgtrEmkoJIa3Nn6Ew7mJ9vAY{lzmEix6)Vd z0hR|c&5>O>EJNwXM3eysBrjiNMYM=&ium~=E2BjQnj+Xm!B$5XY>-*7R2TAVqU8sh z@&Om}Yoq0dnDXf^jfcx{$AlmOtE-?`M@anpkXiv)+aQEo_*EvFCs^fQ!Ky zYC_QOqrEVTi4b2OmJKq>NcbBK zfAIgf{B$+_Q8ZG8)-n;+4D&MxHHlDt?@=aHs~KwFJC(eOy(pkh9MZ|eVf+DQ3e7%y zzcK|xGnA>CVpklHhFhLY%21}6PqJwKGrE<6ix8<%WfuI+(Nx)shLSAVFh*9MObS%U zKTJK0D0&!GbWeUiLV==t^7~Uo`>FkbYoSHa!-%5e4k$rgogh`T(6r!4%M(zv$b2%I zDhjKxN~xw@{s46V$$x-mD3wsuPy=cHsyYzzFSq1BfaE{+fKsOCQbzNiZ<>Q-0u#*r z3Os@Q7no1R(I;R4m=(eMg1!_SXrwFk<|IfdH+7y6N2V!SW}zuF3Bavu&4K2?;bu=M z(WPcq4c2)@i;amc{Khi1#xQBCURIAadL?RH`tw%OP+SAbKfvNFdpvaeYZAsPoK6^S{I*RiG{9LzkEr=!Q zE3ry;bcSmjGt~ER5!EWz@)g@*ln~YupmCC%|?41KA4e32s8K715NQUZ;fNk zGkUV7#LQyN=nNOu4D^X-&NEz_^9 z4zUOfRfpOI$d)|iPWZEIoJvDy2j;~!x@23NJ3A1+?~ur*P1^_RvjeLfa7hPFdVg!J zob9wD&9aA&=-dz=8#eJ#Y|DOFkVr#&;)}qRC?aCrqd-NjbP%y=o`%ki&uZEBL{X24 z&l+X#qvCUdy_I{SbhsrxyB#=14HXV7rL( z4_6PT&Uv4DxWze#sWAICw=olM28pTpnQA8Gen8E%a1U39^R}g>p>qOx4h1oEJIB__ z$mFLII%kRIc!YWc&GA9?2uqGxYL=1X9vIOn>j-rOWqnv3VPPGqjKK~s)9M&Yw%ID^WUXD=^*n3eAaK4@-Nl)Cogaw5&0BdvYxuTK<$R}p z_yubNI-h=njx(zx&F!!7_p(*u0*7r($}4tGCBB7UBe)Eod~-0T7Z*C!i>;Yn=%mT5 zWY%l9{e^+W@%16L=gdJaboyWfJ!otm@h3-Q68A7?V7@TW9$zop5O86jCO)UF$Gy<0 zUTyv2g$_H+iIyzP{*tEpqp1vtveehs1vMH7&@!7I`hqeCGlOz*4^Ih^!9D*Zf|z#!p-fC zH`@vgHu8FCp(m;n$z04UsS_=8u}SJARuFA}=}>DaZgH36Ezvo`vRk(o7Nfm>nsbht zLvzMzjwR<@HP@OmOj7gIJj$1<=2`eAtCLN>Zf}~=s{U-v)|(Es`-PdUR?}0|DHO7= zI>iDxRh`O*ye$UubrVvv<1}>|h3uzJvp`N)r}H6ikA{?6s8MF9Gbqdeb%q5dU(GjR zC|`kEK=}r$1s1-U>P(Z*T4i@Q?f4*X;ZyTxsk12JV0D%Sake_!M5KIk)H#%Is5-~O zcccp6G|1$gIE+2#mGNEP=E!$AtrU<$cDBtlcQ~w~*;gR$2yAxHfR-t!25FgwsXNr)_0_#KgI{Q4IjXIW_;EtOYDlzsh>+rLw8txh`v0(2l_S95*4XM zv_!+zB1?&i)nc=jC|`+MLiw`P5)0p4b*{;0t2H=EB#p(h}4VSCsW({|HOAX^a9OwgHudf9Wean~v0JTtENTC*} z3oTF;Y6XMRkF|R%qE&sw;qA<#>LPU!#b2y0vfwXP7xPtpBoMHx3Mwv9mr#hM>JkgY zQgx{gAs4gOY41TE3%EL+@K|7wnWMLo+P6}zq&Y5AD=j%zsZ}gTx@%s6M(JGv?~2+N zDOi;<4E{I=bD6q~VpglmESSsHQde0tQm&Ty zW_pSPxLRFJ0h`p-7Qi*?8XI81%SU{ggSb{*OA%YtwHCy6DqPn52eY4eyukr%SKBGz32M6qutV*z0mkb_-sB*5 zs+|<^B(>9mxK)Ln_j*I59dC3u@)ifHOYNdqr>I>PtZnKxhDEv&z=B0c%N~w2^iDJq znGIN8`?jmwDe7tJb_?nbb%%~h4m84ex>Mar`Sz$gEquGwT_&IPweLM!w&`SRxA&~1 zD-pZ^%I9Qw&%VohzKCFJ)Bm-1-tkS<>mPq|+TG_m;G<} z-_p7R8U=I?=!Q5lU~0g0ts8%w6cOk`oEEq^FiGnU2@iQG1kVVDG!E$!(p~E|1{+<* zl8A}MWyY0=JB-JSC$(;qpDD~_LF{50Xc~gJ%Cyb26Y&#Mis_2h9cl?J8(I#rUTC|} zj#_tEXjtj6GKfE#z0DXv#vEjJnoA(|HjgroL43=+)VxCLwhXqsW|@Sz+wzI!jMi-p zvp#Pvi`dmV$T}49to5q(n${ie2(J)c8L@Bp=`c|VT`#(7yD(saYl>@uYcb+R*M8T*jK}p} z`b7q&;u-b=c<3Gvp@^#gMb)k3CoN*zsslvIvB_0W!xJ}5w1Cdv#kJ+$L^ zX7g~5^5BVbi-bMYbUagf_($>_y&+bLJ@m{xvwJj0OB;YkU4#(=Fm6wnSRYA>o@qY1 zBjRN8u9}u-?Idd zuLoHMj@l(9A6qdz3-Wk-@!;C%FQp%AIXp}9_seu=)XWtX_N;R5>2a1DMIEV~Yl`hz@Z8nwEJZg;RIVzz zXW?^S&$ABWovJx6b#q<)JxBnXks$(&mZFE^~%;q}>ylVdgB|(&35CGIOS}(&>rL zG;_9*(&dTIHfzS+o{Ee!XYH1lrzY#HnfG|AGS8fSg7kXovd>(BXzBA*Rv>c~BBkF` zTZPP(cwOS2>Plp;Mr|4J)K?>OMe4|)XBGMN^Z9R|Qr$A-Syeo~wfLzy%6L>J zSk>cYne;;@QQMr9_?=(6j1zUOXA?tbck~j?+LYcVs)BDAY?qyzne| zl&}BDO^AfEX_oG=mW*N=3~!#A8xPa|aXu8lYtKnD?OjoIzS3OhK&&J!bnOuPOKaT% z#AIosyM%Z{+NvRVs;?Bjgu{BZzqD7eUQNc=RbL|BmX7*xJPul3I_Y~Mz9OCV$%uQU zi#`SMrgS${64l^Fj6!US*ab08VhmRhuOt2_s*g@$e4axLl31Vah`kVzug?U;DTs@t zm(PcYr=+*fZBc!_q>pcy^!2SJ{d{{#f8Xg6=etSbeUHjO-%n+z?-d#4drQXUQ6xT( zPA29lBa`!#lgZDul_`10$mG1MWNNr^&LSJ7sy%?_@~QnpLj3&U7Qhwt-w(GC&g8!q zZV{Z({}$Y0xG?`qaBstf26Tga2d-E^1GpqObHH@CC2-b&;c!dgEP*b#WpK8@zrihs z3lB_!TLBjlI2CRsoINBGZWWv}!~*v&oFk+=+-kVuAr0Z)gTs^NaBJX78jHZKg)3oP z36~64+BgGl9b75nNx1cJFBrGMZGd~;WP#fVSJspdZWCM?(-64La4(rU!EJ$i(XwYO%9*afeE?U%bOLT0Tx4iDxb1M2Ld|eH;3|f8gxd*MB{Ujt7hL7AGH@Tl zRSPr1?S`vrR^j%*RS&xXw-?TBE&;a>uBN##+=9xMOe)tR}eQa4%bj!kvI?WbF)h z60V{38r&yvO{}NkPQf(}uMBq@u35Mp?hIVh@NsZw;aY_EhC2t>+!hFT9pJM~u4{&{*ZQyRe#W`!j-GuA! zTn+al+yLiHxLa`X&Q!SDaD$v*!`*=!=!%B>32ulB6VL1K!VPvUhWi)XFxMowdvHTt z2jT9+jc~1p`x$OH=lN3_C=EsO`{+{*mSg%N`ggAqdzjfkO$VTi@VD&g3|p0*!9+^Tfq!~u#UmOw0p zSQ>}+!+J#wxJgOcjGCNu**9MD82r((IPupM5{<@Bjl-mF&lR|8<&!eyPA!=o{hVijk}YLyZ3vicV**BW#eAV z##Qum2A%k!f+N*2>UdP*qIy|PQLn1k)tl-a^`73PFQtD`U(paCVu;42a6wyHTScS8 ztiKu^rsCD;FlVhshsj+vI?RHq(P3gwjSiD)YIK;;Qlov38ykp11m@A!=rD)1Mu#b% zH9E}0tkGe@;`B);WuWr8$RJ`cF@zXO3?qgUBZ!g2DB=}jG%8zjd`?^@z97CN{z0S=UlIQ#t`Jv=uZeGnYs7WpTjD$7d*TP;262=4 zk+?6RKxu^&su8p_8bTqw2ya45=m?e269&SE@Fns9 zQi-kS*y=+x(dtAxdt^@*2>21G-m5z&}vLNq0s5zUDfL`$L-(VA#O zv?baR?THRVN1_wandm}vCAtyai5Mc5=t1-(dJ(;eK15%lAJLzPBjSkx#6V&YF_;)a z3?+sUuMoqD5yVJh6fv3@LyRTH5w8;Ci3!BtiPwnNiHXD{Vlpv>m`c1sOe3ZfZxRW_ z4B{;!k(f!$B4!hFh`Gc(Vm`5eSV$})787q1?+{7E5@IQ_j95;rAXXBqhCSo(Og?OLXN_;?UBeoMeh@HeP;zMFLv4_}8>?8IQ2Z)b|gTx`? zFmZ%9N_?Z0E2Z$rY zG2$d~nm9*XATAMK5Gh1m;tFw{xIx?@?gNStTEd6OM+5+xm)R;zgb<;Gm2eOxi84fa zqB4<|RwK4*0h*>n3obTN8jCW6x5Hb?ZH;nQxuH?+D?e+LRJQggdqp{+oD^jTZV6{j+iJ z-MANQWZZjq9LJ7(iS5{q<2ZI~$1N^=@6Bwzn_D)zHa66bk8G^1X>X~C>}Z&%5J4bE)NO2Ni#FzuZ)k3hwl+r^$CpJnMCv-r zTk1O+qYCi}L_t0HQ-~xG&5&Ob-P+O68V$E~HrFkQwnf_&q6j2p!yngH7io+LWKbE6 zjBkyuZ;aNpkFUh!%7zWik@k+(=yZWdwVmzJHX&3l3#q*~2x4xn5Gr0A87xTR*5a+< zAwrRuDQykroj`HIy`A&O!o|Uep*vdQE!kK1I zFR;?9?dh|u^iCrk^DVUDOE&yDmi#n(`g|+B+DJ#73Ja&xp1#CN*JPW0mRaf3?CC45 z^lFwKYLEecJ*JC=6R^G%io?=3S?SgG^kyr)lclGYBF|O}U-R4eY_rm*+0%Dg>DBi1 zJyv?BJzZpeOZ_2L$H#h?O@9tev!@5F^lE#04=cUXo}OW)YXO@b`d~WRCpR=LV6-c- zupIrB$+7YeW%`s~n$8dHGTcZ9{WME|Dd<-la#)UWR{ov#^gJUyH>9bSKIT74wdFI_ z$Y)rn)Sf=WN^daIF~6e>++m^AbR7rNi}iGAY^qXGJ)xs!Pnt4ez<@Mgs+udTo>Zp@ zTA>imZ*M6KMbeM(`xZ`a&k|Nm?%^9&l@(ri;N%K2mZHmsT1GI##yDdYQ3hy3Pm7&l=0>`_vKzet!a z_?B+%J9hP?mW4fbZRoK!zq27@Q{N`7U`uI9&d{tZA(SemhZYwqK4046a8^VV15$2e zT=kSqYX(*2W<`8kd|9Qa*S1Ek?<*FD{l2tNq^K&lxw2r!l!k#*I~LSt_nSX(`ub>p zb;{V4LfGb{o7*`eEDqhaCZm3NI(YX;DVn8a z6$!q|)KKl3yxKK;HgE5-GQW=`jTP&Jnc}!%T4?K>slL?IUE6yMl+t_~QcDYS!;&Zs z%Lx1Owr$umU~coO3G3GkT^!mvH=Hh|3`@<*N)xs8`YFvTrfy#_zgIuNOYJQ+WrR}b zcv5;~SgzeVe0QIwK?UoJGRpjgMd2a7{7`yms37J@i$m!(lh(CBJ*2Ok33}<7rk+6c zhL^9+ZK}*D&KerY5c{VprJ-fG@f*l%ILuwQ0YQEq4Dp3ITsR~Br=d`1}g%ohSh zLwjvkSLH@a=VLhsTIC!?+f75svR+er4#N5{@iMZCa~n$b6fGZDUC>cIYv7a~P`^8j z`ppc4hH8`QW)Dpn*)niC)<-YHuEWAo?c%_0xp~c`T??=t7a8@KDfX6%M>O@D)De~2 zr}PB86xsBbEQU8@fCVy(4W@yHu(z@^QX0wqG-n)I}fO@G1W6_OEY?5 z{Vy_j%-8*_Xzjp$6*Y*L-p9f-{Bv4c%@X91WAHHithOa@%m(B?#^9eB$Q`Q9+%#LB zF>>sng7yZq<1)jJX=ulO%`0YXFUl*Mi|uZrr3du_dTX=$rmxM#a#=i}UZ9<9YdKc2{osZ@r;6AL|9$UD15Tugu~H^^E1} z)i1q&ejC`gb8M`AwSxA_O=Ga0H(7YB9T&|v{B4cN1N{x#fB6wpXupxW+9+41*q4?o zx6SnL*{acAGQwti$&I$5J=R!yx}Ua{%Gv$Uz8ekxm8pyEepR!K+H0G^Ge?5ZRwuTBNnci+BSQ5d*85> zx2=3nCiZXZpnu*`v1Y=iHDVxASUr8iZ0a`?)<@^>9x*=bNBrUASLQ}%_vr=wMnRTu zSZMjel@q9)#|kpN-*aVdN0AuN`vcZ~vAx3h-Vp7h&K)~ABxNr9T4u zcdDO4?LKd;HobOspZ304&TC~@IDq_zk6l}^t|%iL>OHS%Io7L?#!ZL%4bl2NBEPml z-aR>e_2hL63e->$tw-9Qtecy+di$9EQ?qI9O)NQBE3>a6p6n2nY|WA zLQ}TP9j6Mko%E=m0=Vhee~+Pd!0}z^;kX_U5(lJ?+1S*t0Q>jtjoOq(-!#iFnvk~` z2-j9mi6XzoK?TTbvGW?*Nl{*NX@KIiH^|kwV+ZC_e}eul%QseA-lIR-D}Q;brUJ+s0^sUu>di4s=MgLEmo8BMW!|pjv)p^a(Ubl~3 zHMM1S!N9%|_xsRaq@o}7q5eF)eY?6cuYQ%Bnt}Zv^S4PYvoi)x84LDRBH8(hB#Eto zrrx>p!^3?I)PJzNJH`x{x~{Uvz~#;T3f3LZepW9eDt9^Uf>bxx9OeY_>-&ZJc z*iRn63glRS2L6}5LhsL5e+vFf`@@3bdEk$=4Sm$b&g&FdxXCltYD#u&X>6!#XfJAM z+S1S%UAU#ap{2Pk+j&{k7-?%$NIERoxa%pTr$90}$^z+aXl{wrZH{b+W*4@!G-fL# z16H46ZYiV}to+dX0?CfKnZ3TXr3vpvBh6JUWeu=26=_sRUxD=E-4VzT9zbbxyG^;j zK!T`jPqmfRU~GykZ>VqIsE{KB(!-f1kRy4yRkpV_G;gqFI0USOnlU#7GHg?1TV#A= zqh|J^#(l=&-FFQNZ z+|rz#tB{efGN-TNWw&mtYuvoCz7?t^MD!=13D5p{NBG6L+*{H%01NTe5QnGNH_{n7PczB*$0S6`*ROt?MIoxF{$# zv_OTKdW9Wm8%X!h+n8=-v=qP)W_v6A(^?M_TcXVn_^QHl z1p;dcL~V++L4Gyc+uB=e;j*@4eN9_?q&->_ZMGw!9|BSc@3%%H^)=Df)|S?q1{89p zfiY-8eWV@MJp;HFx)C)x0o}T&*(#89dfDC@X>OxH>^8fG+iCQ6Tf@#M3bUKrTcH`? zCA%4^uWz;8#4N3wtbl?kAAhS5vs*fgHl?OXad_!R#OHH zlCa%mR#&imlsb4yUW}*Y0ssD3Hp;)Dxu(9Zt_do21N4VA&2`{#u{Wv1<;Q3>xM|@{ zsx=W-%k6Mm8tUv>^^CcvI}i0hC>7eUc}Kf`nO+>O3fGjEl-HD%R+I>2g~R`6lv&-x z!rD!+$UeP$DYL*n{;J4^n&mCnWO}x4)0=h^eH{QDTA9_2=(j)xS9aiZlrDt6qGry*vSOfaUNf{_c#XI6YDz1L zOIA<|{-OgX8*m6Hl=IjO+c zQP%Qs<$_pyVp^;{F)h}fm=NzL-oVr*S3h1P+d!T?H&iVTr7s>G@WT#R1Lv1>34)<#&K45MNxBLXBC z#*&h`r3)(zN|oW_C1#v9Wd=lf=;YIj%fmH=OXnD!L4aLX)|5hnRgDYuc+7*!R@Ttr zzwexIWfe5ss*)v3mM*HQSyED5x}>BCT10wjQMhPcNlhLa3AhFIYn#n_*psl6awK3Y z4%sDi%h`b{YnF$BQ>GzS61H`DrXZ#=iy3&-u6obcOIN08%)Iuj?Nt!aMWNcP0vc78 zq2F{?nx4pTv5cyoQdUt@xzaKVtwkUTmg=cXU=kD$>s3!#SWyP0HOf_4R8d@02KKiE zSchgXsjLcDK~KesZfIdote4y{8zxx=H!2QO(GW(Z0F_1Iq6IX;>HAP5BLPbY*&CM@ zYAQ>l?E{Jf0*2k#6)PbvJltb?x|dUFo0l^vW(%fldOQ`?J)Xs>#|KL1ECv78{n@zC z{n@yr{v0Z;0Dq3@$79p5--%7bekV39pOc3DPOKdEJF#il@5H8IKWP6VqbtiD|L+#I#s@ zVjA)*TNo~`sajaGw6dgTQQ6W;;G&dOF3p2p4kiK+v;4-m(EY}^q<+%_uh2&;3K0<= zubl~IFOSKUFdv&=E-HhIbi61G16!Qh!Mu!K zQ#5)Dy5gGU3zrl_uR-;Ura|Rc_dw;U7FLDJu;YfBLkRQQutJX|B{1Quf)=k&lTwkk z-iFfjI5R~+zhaiCDlIQrQd3qk7w}797|OuyD(tyDn+0Iwu_JBs>LOe)nLf&vV(f5X z@-Uh0HPU`tpPC1SAS_tudty48+Z&pq<6(`UqYk#iL>h}Cjg6J?45SDd_(ags0*?T# zku3r_+n%?}x`BP_53uk!ZclM2R&{QPy5F?Z*HsOI(^a9D&^sVx3VnLYLSIniQ0T*z4wN;ae+D7K0C+NA-_TsI3P%V%5p9q_2E?f2hM^@L%~fEjY(;=|6{UP( z@zS!AY}mgPo0VM_av3TdnJQ!nAjuxb=~J{{7!KpXmPl))DGDn9XofagS*vW7$*NZs zMhc^l7Oa)@w4So)O+^?3RkR`6&gxqrN7<`Lw|zXM-KH@fqYC4M@d0710R2rc+S~^F zqr!D{(YCgRT3p?jY{!pLbw$k+@&jN6=yiPXNZB9sSJ&+m^crI_MtEx5bvKjf9&pJEDx&vtRyF2MVQTNz0fl=51@-IexcCG z7;fuiAQs>Dp%3@t^ZG{EE9Vzr0m)ukxT)(xEM6C^o=SCbRmLxrIhEnAt_-nwWf&Cf zS;3_)4Y7D>7%uG6aH&f}EM6K061y~9>e3L4myW4oxYVT~7B4-`i4B*!G{iEo!dROz zx>oS_bi4n+wO{uQh;kIbWgH4{Z74vLqX5$XT^L%m;Ui2;E71^`4k08p!`6o7eFdyGEZHuNFN(T93w`nYuF z7ohKU6aa1;`Vi&lL(MxB;M!1tC`SP*pEU(s*YgX<#puIrL!av=c`Vw3{_K4H%>-*Oj>aum>A zY~5JCXF(aWaf? zjC{*6Fv?MY+E2qyDY9Mf)}D&V((;siuBYTf_3H?&`0~UrJRgH#xeCg1IDkJe1fy&H zLkxoDJNaDSnFtP{Bj_CdE#OPaY zgpwQr;46BAuI+#qfqt=P41(oXlem6037m%(LGM$Xy@?ASXZ5=~}7Vi%_o) z0L$qnbDeH7xDxZ)R_68vF#wj=p(uv|5i*Y543Pv#SO2NNJ63fei$MN0yo(bi0Rzsqg-Pqa8$mtr!w20Hcv3jW^EI-Bnew zUW}#@SzHf=#@FseVR&v2nk!r8zLS+PN&nqf@p{g{T(g)Pt7|$3RopB#B30ORkOtdp z@?gyn_f3JBMwX6(cQvXl5s=a?B)F}LTg6t?22-bY7?QB@$f~;-)9Tw{0;Vuvj<7Hj z)d*En#qHt_%&il)Ek)WITbeg8n)AWT>^hd=d{sPJ+=DvDKv8Pj;rJr#PuLh~+vrBp z*!{Bw_H?A%mAsLq>Z*96coJrOGI*gKqh@^zZdu8QOUqWpQ<=(XdbZg2>12DLxOokt zXEITEo}|Uvu+fkl6Jz^CCe;fmqcLzdk`EyCd<`%t?xaL@;|i;a=ZWWI;V;0|oo&%= z(dHUhFl}h>gyp?D*chbXKuY&6rLuGy&x{v^l3vQ7E`t{2xW556T7_bhK;cSenybJk zTesEX2oi;o$t~;G!$DK%6U{`By^euj4`yuL1{`#P`aW*K}X$ll!fX_UUWOTlV}ny~YMniyr(#9^4J;%(yXX#G2=1sdCQ3;0^w zV6cYb>nTwDyIJw?fd%c>ZLp(lGi)MkinP~3^C)ojBWGday3Q2Dg2su}45r5`tS#8; zW6uOiRb-XQgruIC;EGx@COcJpKztC(`w-+%*V4ScVFSDifi>@%4ci5>*(wLygk~b! zMjkVbQ&VpDVwgZHVw=b4hP4dX#Rz?3TPyC|+FFAd{Xk8twmej%W0@$J+ z`xWqGD-m4oCDuCOnHpLg-l>l=@p)E7xp@HRUd)&#kmLVLP*w}(;(5TT_@Vd_7Vs~WvDI(aV9y2bSq=B(*s;`MEbPY@ z{3r6RE`ik!MRxFkBEy?EedFWw|Ad(;ekT46OZhp>;9^nhqw6CbjqTa+_~RQn3Z4!6 zCzJpNs>NVbsVaUceucRIq@zLm_LjCf*xL^iz}9WX1vtgG%qjk*l14H$m5Ac^DrqLO zG4><$P{!^~*tZR{*!Yc|Drq5GQ1};+Fod%kcXnc49qm!vhz-n_sp4sGe*GRpEdfg@f-&$ZW?bJli-Jvdy9@X(R0jm4?qgY|pwA zD4hZIfY*^wylnidff)qu`p%|1q>LT4HQCXvFclf;*j77z)G~pra;E(k=l6(yL>w(+ z_bp?DQ}|^n>7bS7>#dS)EY?>g+gVIg$qp79pps4&J3=KpS!}RMcClENN_Ml@kt#Ww z#fGV54~vaZ$uTT8N+rj#*l3j;$6{kuay*NTSIG%1maCEzSu9^AC$ZQhm7L6CQ&jRh z7MrG$Q&?=eN={|5nJPJr#b&GIbQTM%l5-Rml}Bwm~IVvRH#ku41vxD!H1)npAQPi?yiaS{B=?lIvKkO(oZ} zScgh(V6p8g*~em?D!GxxcB$kh7CTxcH?!C=D!GNlj#J64EOvrQZey{NRB}6u{Z1u! zu-K_8xs%0CSIJ#0cBV@9v)KQsz+&gCq>IHaRLQ+8cCkthve>06 zxsSyzSIPY>cBM)lV6m%J@*s;{tCELU?0S_v%wqdg@(7FFq>@Kj>=ufJ&ZYv4>RhJc~V|k{4L)F_pZ? zVo#{#_bm35N?u~IXH@bB7JE)5FSFPSD)}Re{az)nu-G3|@+yn{Q6+z3u~${{8jHQA zlGj=64VApXVsEMBO%{7cC2z6Vdn$RG#r~|4cUbI0mAuPhe^JSMEcS^?-eZ&mUMi+!h(Pg(2-mHd^(ep1P2EcUZX z{>Eazs^oJPJEW4o(^!h2k}p`yr;>lLn52>~SxiyMS1gvQl7F&Tno7QAv2>Mu!(u&E z@-2&nRPrwt%T&pCEY@2k-?La>mHfbBno53Tu>mUiiN%gk$-h}_uu6Vru`HGR!eU3N zxMRzJ$BNsgd!A?l9QGyO` ziG<1)GNIu()bNC?V-HMlSOP)om<5wN(nSup>@lgq38X9uE_*zWao8dnLas$bq1YnQ znLw;9K+rt!!MMAMSp^u)D{TD?&`Y(!l^j{S9=)WlH(SK1?w=1vTVyCB!qgBkP zLwJ6U>%_Q`o{8{=<(Pw5hY_@n`Y^$SyZAzrT|~jK3XO^J#w+6hT4^zp;Z2_m89boC zq_~x29c5!e<2Y`X;Dj4f;1xqZtd&O(zA-Ug^SaoH2FabzF8l zRxfnX<}f7bSvy9O*L518wj+3lFS~Ivk4d_4rA?C_TVtZUnWD~sin6BS!3eQ!p675n zFt&PXD3?lS<1G^##c?Jb%63MO$@1EbF3XBy)H~1FbwPTfkiofBCG8vVpy6RNMoBz> z$OL)qN6#3K;vF_$^R(h&;jCG$iv?|G8xNZ`o@BK7j*IuAq|KcU&4|8db`ngHQ zk}rqjm~*`2SF<5!I0N54hLp1)y#Ae@G_yufeiZ|p-K!G{>CQk~2;ZFniE*;BOlXgo zAuJ(#%l8rzJKQK|9vWp;lrSsHFS(tBdBl{#aBEPPaUYdz2T~anw_l7sr|MnQW%6l1 znTe|gE|bq#QJ2YQtf4t_Shp{? z^RoE@+6 z+u8KQmavYjC+6fl$l$tHGpx=J>)*i2_B=|1r3s<=X| zhOHmcQBEgW0z1N5>p^)^%3tty5p3m{(a_w`KFhh2Wtl3KNOJ-tSAsLunbwi+s*SBJ z+i?S+B9#WnXlZVMj6;zg^pl3`JDRhbquX)+NiVi72G3~fKWjpFZAjT{_xNZF(l{kv z3ZGo8i{KY9t0Jv%c)w&vU6g(hQ;`-yVN*UuzDt0n(O$|sc4RA36=ZHUAxy%L3rNdS zrKQqxxMc{l)}ct%uoVWt>DhX=d&OeH4&1BKDrt2nRH;s?4+uv|xHl1*MLOCb+7}$x%F;CZbXD3Q zZ45|@r3RZNurVsqW@yvQN=?wFS*!&%#j(A$i&~?wu?Y+Y`)PXW+iCPPYO%Idsa1kK zyu%HPncY!aOGj&6w4r%@%lJwfEo*3o`rqa!smRktQ~$I=DejE{|LF`!+oheb6RM$! zediRvLNVN~;AWQH($N8+w8s;rQedY@$HLhIgMNZ>S$cd@a3DQYW z$yls9FwJCJXOcjX^YvAzvfoLk1OV$)IG$n9a|$Zb=}`Oi@cTdPQyn|4eRIxjv&FFM z*V^gkyh>bQXdO$-nYHb}2Zd9mGo`Zv(0cyQ=3qE@DAGBw={dWu1x^RhK^k^f8m0N~ z5CNw-S2`~s?Ul|~NjT+OYse~jN!k)@bOTFV z8IZ1!V7t2lb(0;zoqTJpQah{Wzm@4V(zOApQMyhQ=CI=4fS2dPff?vl$J$!kVLMLP zGAV8Ch%|zpkf+BX6kuZ`O^49gZ|AAP0+#1ps<4Q~?iR=r`)>TCi^(P;VA}&|+b-x@ z4KFf2^{Yq+Vbn5f(@3U`^8QrmKIsA20$e-6FTt*KN5`x8Kh}_MsB%8{3uE9=>5%}S zJqjjSs!ESzkC`Ps0nUY$9o@?QchtCZ(`(YE(B14Q>1lNOXLL8KjkK!LbIc2#SA|Me z4=+Mx0k4kcNNZU`H>0r-wEi2n9HrNaGL+ll3@+0vs5m=@8=AcW4|!VVWL?P|TeG zqY7=A5D{~seX=WvI2$BvVT#i1W!StmlbT+ZRAD1aQ&eFyi@`uF=0ekEFc1-Qp>eY- zh={qsm|a1{nZ-m^Xl5W8FsY>#CijAAHH-Cui9L(;Q-wAr*B`LJH(FYksPaJSF7gqW z2UvpT0TD45Y{9M|;>;0lXK`kSrU%d(fSHBSEp)UuG>%^q-B8ku6VGf#9tNAXP3f4s z*h$DEQsvR9^c%fYn<$~oX#^5_5=fbHM5FW)(^Ij?BzwH$|yo`NQi3qbDU zV@nNYFgrRZOa*?2Talrvtd7n|re&CzD(B0vacu`PI=GW+7zA@tWN@TL%dMT%oL6T1 zh?~j%M-u}m+VlXBnt{~|d|35D#96&@2~$Dgc9|1K1WP|r$pxU z^WyHoM!#bj>;i-ZWd<9M0>j!#OmY!O;umSCBt~NLgZ6d`lU$0DM#IENj3l%pu{PH) zuY_kp)<9On6C;bQ{a=n5djE8dybk(l8JOE8&c;W{Y^Yb(zUdu!?o;Kha%-Br zMQ($bGzShy$Q_PTqMT#MRB1b$IhJ?Weuuzx<>F3UC8=YdsjqB@pEZEi1kW17&5prM zl(w+lsq!xQXgHg(rK4@5{%L$wJ|^XZ0Hhxa%PbHhqI^6)%2Wi%DEUOF^U{S5;s4<^q`S^09?2xSC#KYv)?Ko^b_bV#hN@-et@Ms=qK>lAlBro z@*^zeQ9r>Rzh$qrhg1lkzp>Y*0$`ZYAJ<9%?)@+ zxDR@hWfDDox+*^>KOc~vm0$1^Sc3|5G#hFON>!@LFUfyEjhEq(c{%*lZ7K9Q@ZCY% zgb-7U^;2As!z=QuIK2M}hxaeR@r?#y7gOXn9KH7cY6N{NAipWU?I%a!vE!9i&tZR3 z!HI?a2UcK)qRH=J5#EQ1WT7g5fE|24`9nVm`$>_X6#GdDOqk5B&j3Rpx*jI~HI-z_ zpFv|q%}n`oWHG}}=J?56KbhwzrG7HsPZsz|nV*#VNrj&*^piz?vKZEn?B;@Y^b-sn zW=?2Amc!4f^1o#`kY=v9(dAZ<{|%hhlxK<9%oLI;A5sLMB=rhF%ohNCFw7ELj#OGv z6hEo*lcj#L%ukm4$qGNI_LG%5!&q zs<=fS)qJFX-jxw-2Fd>&&42J6sOlGQ| zZ1j@`KiT9bo1y6$RYH62%Iyu%8R!F;qRfIdVpeMKu{735D_WXi;;g{@D_!pbX$q}} z;#8$b0r&A$;t~GC^t&Jf)ve4`=E2&WQtICCqOhXC>`aO_ZE5d>Llf?uI>-Zdxl$2O z$`lx93$0m5Nn^Ar3O^j9vuD4QWL$9v90a3Xr?NPp%vP2J#Y3u8jsv-P%Y5+r z+dljUPLpIXGgU@g8zPMjJLv+q0-xv@YB_`cmEE#PQ*C{uJlY$)!_7z zM*P^UktUFn?L&sH3IZEre@w{!m0x{0x4D}`k$x2TFl)-Xg7qn2Wvx;ZP}V5xpu{j& zRO$L+c2nK5?6xiRK?f&rjzxOi!bZ1_2ADd2{+y0xI{Z)2b)lZ>l==)JC@@VC@p~}v zja|blV=BwkwJkNqJ1!t@P&Q&!HK@{^te!Rl>&6VIu&64FEU5*Owqy_=CWTm18zi-7 zkQAiSH-1p6Ukc-cqHKpL$I^<@DtvZKAOsXTm7S@|4rP~Z+61j@qu!S(Fk7?^=vy~v zJ31y+*`vU;aS8NiK>2u8K2pxc*onaJq+rUY=xYj2tKz<#V@!1{OF_4&oSH!-1wL3Z z(XuS%VYs~|Z68>T86W_h5dcPK+KNK0KBu7(rb7zM46UMAH)v7LNmb5P_ToBF7Z4F6 z0k}LL`VL$dgCD|bqyMPNh4dLjxyV>6!bg+;?xGZX*ikM~E(J2mWw0#9vb;hS&ZN(2 z%2lecm&LAuw}SM+N4XB(GP2kW@HUdgZVbo;u&gYc&xCJLg^O71HdVNs#qLmrt5^(H zKd)smm^qcO&h&sP+{n`Ig%_4A?LOTmuvS>#unpD=RpkK**YcDH;ng0?_+faV$D|*H z^)clNwCYt5lOyofk-5rKs+`MQBS79U{aVR{Q;6*&LDnF zn!}P_g`_`akW@^X%aY!Jq&G820Fp=*%jg|dp3iQ+2RGl(AZaMSkR^QxNgrhp6_cu1 z(kGDgX$DD0h()Y8e^Z59m>K@A3U{&?ye?kM?tY~TceAvwRiEhdq5FRe{eK<)MwP03 z$7p=73SCUAC=BNx3!kcT@%`vJk)fd2<@DrSWWjtU#qtvn?Z97h*nOAy0;;^qZ7iFzZ z(ENGucGnMYq}Q@MVKwS=mJ=MK{EEfk809xC20h1jEH)Fi56~HmAC6J}o29`q%0ny$ zube|h#OQVlb@N6-I0H8s(+3j7JxE2qo3lR55wAa_!9q;==yMLYXqhl zGe&X*jXu^kSuh@CmxK0}Xg$@QuKLUTxl{v8AfW-YNT+t70Zgt5(H+EVfD&@nic?scTemD2vso;s_RtsNxtFt5e1C zEEZM8i7d836{oRSgDTEqvCXPj#9~dVIFH3zRI!}JwyNS17Hd<*r7Q-^GBSKrZ$tY= z)xRC;P~PQ-D3 z)KnnL?6V?cc5V2Ax8)JAwlya+#ybD8{^OA9@h}&`k3F;HJ&1_-C1-X85fMMr%&s6J z;un|M6+}e*vNF4Zh=|`xW>*jq@x#aL3L+wY)tFsDM8r=N(<_XK`2Asa1rZTHF3hfw z3w}A6T_G3z4luhyF8GmOc71{z(kqOJ_z6{Zg4;Kxnb6>`B(m9i`3f}b5_SI7mwATUjW6_$to19QgnC1B~PGhW*H@gK^x`jL^&fMZo`e z|36?ngoT_?BYhaNQCI!{^#3h`Wca^^Ica6XhUN(LKk!(PQq+Q<%}S>W#pRJLRrrL5 z>lm<;rJ|#$7Jh4lrDT-B9;C))@bNIb))RxQ;ERmkC24~Zr?j~_+DbPJ;ZKwV*v1%` zS_7&Et6=!!G0Ph0&x3@Un_J-5OYxU|p;Ls(3;W?1h6zbMEAgjMN}C&j3%-wmRV|tV z^hp*GNecYQ#1G%O$iSU{@DP!KTl@$KX5gwGy@p+VG=x2UG=v>}G=%+pG=$xJG=#l; zG=yz?G=xoiG=wdCG=vR%G=%MXG=$B1G=!~sG=zG=xohG=wdBG=vR$G=%MW zG=$B0G=!~rG=z(=rwG-qakd&qakd% zqakd$qal2@i3t90Auf_8sE=l9-$MK@6QmX5r<7<2-$A1C9lHIu>EU)g+@Xh^dbm>$ zcj@77Jv>?u_vqm){D{c%mMjq=zT#;qUbD6g@mu4^Pv>)AjHSJv>tn z&(cHq<_|3weDQ~d@Vy@z!q){o8c%>d*rH5DR;Wc`AtsY*dhu7=j4SKjw4{y}NoAmHzJ-kH^Z`H%w^ze2)gm3oH za={mSXb9iyp&@*&hlcR29vZ@zdT4k+54-g6UOhahhxh5>{d)L-9zLjt59#5EYvg_=FxlsfSPL;nRBfj2=F#htKKZ^LqG#9=@oDzt_W;^bo$eL(2tU+@T?S zZ-<8PwH+G5w{~afw8O_`V+gSr0$Z!w>cF zBR%|!9)7HcpXlMIdiYm8{7eu3riY*F;otS}3qAaY9)78Z@XZ`rF8E>&4dHt^G=#6^ z&=9_rLqqsd4h_H4!|(O*2R-~z4}a3bf9v7TdiaYT{;G$+>ER(3!pxlF!wMz~MLqQC zVTv9~dMN9mqKAGxOx44H9;WG`s)y+q3h%;(Pk4HP$CH0SsdmH2giBgu?-vFVQZ_oL zOBh@}=4m30xpTiTEGJVKF}h2D|8u*9N#&z+#&ikOmXEm;6ny^g;NLVN{7NzuAyW~K z@_!ErGJ)cd4*w7E?+`$i;MdU$gz1o)MurMAgqhISLT+S=Fbf_?euTILvmg=#Qm`-3 zE2*OHklN-TRcw+faU%u0_q>vtmprLblhk}SQn0)8!6cP=#^Br9NkH3ok=R1UP*P!r}j9iZ@o!sgBvN>cKJUgb&P{lgGp+W8!6ZU`adOgtb6znMV zN@`1YhM5x`q_&!*THQ#sc_-D;9a1MdNNqDoZFeID+dI8lYG-#yUFjgT%OthijTCIx z^h&B*t?ya~sXZpCW86r=W>2rAj_;18Zg7w~!6bE}8!6aV>XlTt2IPGXQYV|Fe&N$MdtQm{ehe@f~Ohov4dNj>UD z3ij&!Pf6YBAoaLO>IpYeux-dIsi(VBefu4xo-s*1>qZK8FnJ~QLh__uG)ev5jTCIA z@=EIE*dQ zpO~aRbt46P6TOn^*4X#B!>2woN&U@@6l`PkO6rU5bO}#5Nd3bk^`#pr*iq?~RJSbU zB=t{|)YopLU~{KeQr+qjo_1L3Ta(nk+(^MbQ?I0c=uY)L;~@2;N$MvzQn1n0E2&?) zL+V)vsb5V}zqyfuJ+~f7iTJJ-{{PQj*FI+_C5i?q(dR-6cg1=oC3lC^^A1vqNy_g= z3O49^C6(44QZG12sV1p(H&Wi;wu`~;kb2QUDrAz%a3huJ-BP`~L+T|5sXivDzHX#o z2esGg>)#zxe{hf*V3Hc>MhZ4_dnGlvJEUHAkQ!o=%5ozG`^vqN%I*%SKRQSaGf541 zBL!RBy^y2+2W62tp1U#RfeGJH2K;zJngyi!N>g5cueT4gz`5 zJ(F_IfP-TDt=vNPVG<@wnX%OOS0Xon>=3ubL5@Bs?&K5WK^B17*_KTma+kO}4iZ=% zdt3Ke9w#0j2MH{H=auCNP$?$M6KKIt;X|ID1mqcf$p1?M@@(-Oz2KH(jt0lPkdGPf zn0vA0)G^PsJLX<+%yX$7E=rKYm$&297-_-pS7*hsl_Y z%`f7C1GKzf#3Ki|!Pzg~3Yq!z27MDPQo0WWgCG)wn^?5F5)|zKKi~MG?KkVgQMCPL z(YnNYb)T||HhK&c?O}cv@kKkRXWiz%<=}rKj~%;h?oJIIUv3UF)VLDd>vvbx-Y#-GY_SJN)UvDAQl7x z^rv_DWqY4b!c*D)EPlXuppW^W@eX8^%x{*=&q`)EkgXh0hEK##;~L}WF-IH}|L!$I zY%K^e{d!hU-QRX$EXd;-|#K}9iOuo%acaVEaD#V z2R@>Mk2Q-R&74BrBmU&AQ2!Qx)-6&521SzwbM6s;eTFDG_xc2kA{llL#7Bg*1XHh| z?&bo1N+KT6Cow>O&OJWqKLmttCvX5&2G|n-)&CGM=nLuIXU)1s9}s`I3kn)PwT!Dr zdXiH=QRvIidkK2FMet?%dg(36f*x={{K-2sj4=*K(!r};Ums7kOSW;9`*~A_j|%99 zx2CxF`1*TO-oaHK=uNqkt31e?@=mVu5O2!6xXMGlDevYgXM0mVnyWnAoAMs6@Nl~;IEzL2ZD z(wp){T;P`7Nu5yA^RmW2mJOEwKRo><;=Nq`nJG?3H z<0|j;rhFq;dAB#^o4Cq*yeZ$zRX*06@-1BD zQ-)6-bCgf>rhF$?`3!H$cX5@^@}|6>t9-UM<-57cd%Y>&!&N@doALp!@&(?MySU01 zc~icZt9*$!<%3-1%e*Py$5p<!UKg(5q(3|peT;+$oDL>Cue$<=t3tZ*Ly(z!QResW&^6$CIPkU2-iL3mq zH|0NYm7n*f{4!VhMQ_S~Z+laIldJr$H|4ju%I|wqhTo^)So;HS%J7pG9OaL^DZk5A{@9!HdtBvD zy(z!XRsPJI@}IfNpLf<9R=p{I%~kH#DgVG#?(a?cN3QZfZ^}P$l?QoK{x?^7h&Sb*xynPmDgVM%&i1DKD_42A zH|5{B$|JogAL1(Kcv6P1v~wmjDPz1T3tZ)K-jqeI@&s?nKCW_}H{}$r@cI3CQ_;$bm^fF5p8BN&>Qs4>=?W$Z|g9&?F!$_>kF2 zKrZA%4o?Dd5g&475|E4ekU2>}F5yFtNdmHx4>>Lg$SOYMgd`xB@*(q*fLz9hoR|dU zaz5nbBp_GtA*Ut*SilUfZWW7T$==BBOh{I5|B-N$l4?zoB5FSNkF#nA=f7X zxrGn8F$u`6e8^2nK(_KB8!)j2OqLE3CL}H$o3>4xAP&lB>}mE z54j@=$WA`w&Lkjr@*#I80lAA0xhDz8-F(PnlYl&$4|#kNkbC%$Cnf=T3?K63Bp{FF zL!OcZ&2CJD&1_>k8n0r`J?$QzP? zJev=BV-k?(@F8zb0&*`O^426E&*ekjo&@B1e8@YKfIOcMxjzZW3;2-tBmsFLAF?Y6 z$cy-p2a|xjm=Ae>5|EehAsB4 z1msnG$Y+y)yqXXBd=ik?@F8DJ0`giu3KIHpJK;FuS{2&R)+xU{OmAM)cQAn)Kq zewqa2oqWj8l7PI65BYf#ko)h4lARp&Ls!2dT!H4XT1mu%^$Y2tXPw^o$l7M`g57{dT$Y=PF zeUgBDmJiu43CQR8ko}W@e4YhB=fP9e;IV1_l-}51dCIR^pA2K@$$UpEQ zhbIB~G9Pke5|Dr7L*^s_`3fI$OcIc<@*&410r@9Bi-bfP9w^c~laR@9`lElYo4m4_TZ9n@>4#DKf#^yk%vzP!^f>ArTm4X{E0W^X(^v_lt1&PJe{ljxi{q*T;(skDbM68 zf9Xwm7WWj5$3xghadZC0Th8H>Z#mXZ@UiLGkC+v4mA!md8l0q?;G;hikT-xd0loxW9dwNq|#8nP?Q(nwf&h)0dMCujao~1tCl&iSP{k$nJ=7HXnmvfZ|c~f4&RUYC^xtgmy)SL23u5z|FSss*wVR40ozir_BL9Z?;>`9qSk_tJ>#U7MNhWML!NLP-+FUsKWt_;bk zE_b7fgdvNMAD0{OyZ$;`@d4Rft%uNb?g7 z%tQ2F!N~B*iL%6B!oVy?W0ngJ_@w_@mgxzzgx|`*EXQG%We0rfe<#bJCY4JS?B_1T zR+5H4?<1_u>5?k>{nG7_CX=5? zmUIWC!4EG9Yo&$wGk^Neq(}>cL2$)84OdiNAU#Nkkd#xQR$^Rne_~fO{N|p-e&e%M zUuSSy;_AD1zw}_H^l+E-SeNvqL+Pl*O3yk3My0srU_EK4l- zf3t>jE`M`gNw&*qtnrxjBev? z8`REVzr@+TLoJ`GrPA`er={A;6VL)yc^rVl5(B5mPnQB1Q|4uBB7Czi8<;xgJ^%CP({7yRYvG&Pkj#^Yu@_*TLzb1N^K@ z`l3tv%4UIG!SclF&r(J`wVssG*IG{-qo5YFm^%P#5(8fE5OnEd?asU_I6N`pI}XI` z#DdowwYke#n|Bev*=vs{vq%_v>-Wi5R1!Q4upQis ztYpgo^PppI5Bk%BonjW*2|wMqi;lmy!r+MG?>FZ7`z;-R!!XwVi;lnJVEp|K$6xXd zq_2&1n=v4m6HTgd(7A?PG~3&Vv`Mkh#4^*+VD z=&+rjy|veQ?g3$L9n;44!2I?YA&nespX17D;Ma7HE34qw0(l60Jsr|g$jxMs+yl~l z!YD}V32CyB3H~31G@RqU!t?)->HqcM|0s4j`ak@=t`9vSa)QI0hO6q&Vsd7}#v%8% z{4YdK^jym)daLCV9kjq#<-S1sB9rz>arZU64}bc^Tpqw}II)wJ5IH$GC9#9TY{huk zM9EnRCFMa*NtgM!<;o`qH2^f8O5tfuB%{bwG96s^WAZKe-gMzgl5&VlH=oL4pVD;q zIz;aI5B!&Q_!;0@gq%QzkQ2$hY^3xOZxgly*Qmq$SbLI3-puS*`&C6C1_v)k>|U|m8BOMmK; zC%`;Db_wTHN|?RenZqNJYZ8IxL_XPvtoI-bdvEi>K*!R|X5M8k1*I zIs%~fCH>9H8b)AYrN2vM$@#{3D^t5%NlSn~NoKINHwNF1^ZT#j(8n!e)L6tXRacVk6&**K+72ZN+OHRxCEHSmI{I zIcBMxR+KK`Sn)azZKoBlJDe5gCdf}N<>Yt$Ve`BGaQV$Q^Gi@`Wt>_|;QKcO!*NcO zbgkXssI_vl)+*d;ZQ$1RE1d%C(#}dmuOy6!aloA0V84!~t8I{fgJq))^Kf&Vf^oTKU1~ zJlmpIp0=!Ha1us+N zle*+nGv(9nlh5{%N2QeqQa%B}^OY|7B77V0n0(2_AGhv&VY~BGru?*Z z=SzAg<)Hjxru=)Fd{F-5fs}vJWblP9`8C}mAPB;OFGBgULqjDK1fJ}w5lhl_Eaxv>~uTNsiZBY`dFIrPDn-eJIIyR!P!5=r4)Y|K8H?=|R6TR{sY}KjcBb zDpvnTOFxt8%fIed#4aVp=mC}nv#gO_kunvTsVM#fQXjs`vRIW=OQj!QWqGVhz*6b& zpvcL;IDs|GO!>+%Xpd$*D|`4!LTk}kcqJ&80+~ro>hJk9PGF&ItctDz9yE7zH8DZVYqxp~OQbu1)u-z%J zilmI!sq7hcW>a)_1^u*sn14UrP#VUlq59MOHLXA7UuMg{ALc*$ zfHKXGLR+0e4=A&% zp;E&8l{xTW*rm+xQWo8-&{E{wudFAeOW6d)YKDtu<6;Y3wCWeK3>Vwz#q#~i?&S>Y zI0#OF8>i!qvtaGZTsJ(`kv*71-n?HqH|U4RM#=W>JVZ_pPEPm$rJTnK#vI#Pm_D5@ z6eV~7ezr@w0Mt^96<4KyY=((9W?+W)Y!Yt@Q7(2$HY6^@V;klA;&NDrm^Gwg?Jkzr|&-850GlB~f8a|;p z&pMnrbuY7<^DGbM43R_e^>CKwvYhE!7PF%|J+`BQjfw-b0l3>nxmp`w+if#Y8))pd z!B-_Kpt~$CI6^yuie9T7VG|vs4KhS=8>a&MAC-Of@}EOrt0d^a91C*i1YNeo;l4`S z9;gsGCs>uR0wvf4rG!BPHlA56=$xR-(x7e29b!ikW5b?1if!Ah3K}8uyTmHbG8OxV z1FCX~i;9DJh@6#J)V6yGsqacG8Ds9w#FAKzH^orcmss2h93s~z7PW24LbfjZ0$^uf zqv^co*qv9o8S0kq@GTgu4W?dst2Wr?l|wX`aN9N)7Z+q{Syb+JEz2f1R2yo^*^9e3 znD0^qlhs~3D+y;hrO*>gw7ndu9Z7S%Q#;a@W44xU=C~JzZz?)W8%9O5lA59#gO z(RZ95OuQFXdC2ZL=LcseEWd=!>Jj*Z4U$&Bbb-s(Bjs_Yq>>mLw&y61F?@WTVBudF z9G6(j(Ht*yV{#=CdU`K)Tx96Q-4Quy2!0L zJz;mNi-JccBrnCd)t-cs3Uw>zW6Q;dD<;RSE|sxHYV{ba>?N=!f6DT9M&REt6$>TBA0l!$R(aFaxs0mn!vTMwENxp!Q~0-LwOP$ z+A(jr#HBk%OUF-GFLSZAAY;TMvtv2Uuf3$jI@F= zn)Boun~09p=wUPEOU=GHahx{Jm@PR@n}x_NZbu<($IVbO@!mwIo898lc}v#b#9JK2 zMeF>N7I(Zhp3c9%(Z<{6UlX(m#{3JP@Z`Ss#(1l@9B+-w@dU{AU-0(>%{f=gr8)nk z<=S%2)AH;&!!u~UmQUq=*79v~6Saw!T$l2j*`98l1zLdxL*=Gx z)2W=IO}EL-&}LY2_A1-&wv7WHvx^I6YBMQfsy5SxI7^#lAyT>7+H5M9rp>m=9i_pG z3gh9+nez&d{pEhQV@7!B&9OsfzuWmRM~}TfxY>mPEmK$v(=w%NVOyCBwL+^*&z(%Zmq4J}KNRz%CvQ!BESrC2Mrmj&v( zL@S|kA+5wFH%FUe$=R9R?KTx=9yC{*OA#}*xi-Xk+B^%9GAz|fsa$WZ)FwAyn{UZE zb6%g=CXPAh-EPZ6j*0!P{(wUqhBp5QOMG;k_``AHuw?G1ui&7*9Iftgw_~qx>Jy5KeaQlC z0j=R&ZGo+Z%d|49hP(U|P2)Wt>)Ksn9234U|Feq3i*&9pp z3AfiL7RiO$LW*3VEwmvo(iZVaJ`oH$NdmdW+F}YZLtAWvSfVX4AaL;l+oiMbcsl6m zIKk7w0alLsa!I9DNpqZ~RoZf_(y9z|z}l^HE?Dm<>(vshIGLt?hJ(3OTS_qtwWT)9 zW!f?e69C7W7|(JrmTSu?MzOZshOt6hVPWj|4a>Au zHo(=|Y6oD@&qsWLgSbXpLlIYKYix*XwY4@xwAd$I^dz}i+!r}mHCheDTB+68u-0ko z7#8l9=DFfa-dyn|PL2^RLUUZLMQl0NYVfHCoCx4fW~kc9ChI?NFzU2Aim_I!vtiV0 z^$v^?CdSJgjHni+80)mC4P(8w-YPlzow3{4#QGx#YlF6dV%2IJY*-t$jfcT{m4nrw zHBhX2t-*%1N!w&$@oMBXm$g*qqv&hi>h3iTx6RsS%5A;2*~YC=Yqad{+Ks%>UP{b`-hYfL?w#|mf>qg$;U~Sj7 zQ><2PyA5lHwu52mhc4iKylpc^h`bkzg!2H~qh6=hNm1LiP8;e@ZKr`szXnrWuuFq& z|Io#5({|b9c5AyWIs2pD2aaqH;T~;&XUbJ11KQOInf_h(`Hv9^>`{UnbRSHY|Aggt zk=)?N!S8}UN{d51LqkGGN{chE&+N*)55nJPzMuJ_w7A#oUWb(!(-#Np~8NiJ|uZl9mz%Vl~WVYP|ToN}#RNQeT+(2C*^)7(e_cg@Vb zG!-?MH1~Zs(_9MIF4bMS*EYkF=ko!vfq3q#=P4D`KX`x7`OI+6`F+pKAR}{r#vhHj zx@c1!Q*%=kYN{#SgiE%VmYX)4wxZ_xy8BkpMf;k4pYnYc^#`+RcGE?hcbQL_&!B#7 zzG=Rti}nlii}GuY+RHE5FGUw^X=3SU>5Q6gS!h{;`ghCEmONc_z~ce+18_V63j(qN z)}wxB)maU?XzO#<2x|+}L)Ht{Y+ba?+vc#=cwR2OXzvWMC0qYkpC z+Q*=-v+uF*N6ibY6zHjo4vY-!8rTChC-6q#O9W22f!RTLbhv2@!{ZK~+PYKQ_{CwSWw6eF4@gI3jt+`g=pk|w6Rwjbxw+}*w0`3SgC z%y)G-&O^HUdvdFx7a8HKlJj{EyN1RN)s^*V0 zO>FmUq=lm`c;$+hzdlYvb8%gryeQk$xOYZ-XxTq>Fg%(8llffuY-}mM?H>h+Rjn1h_1s6(d zF3*;VJ~{WQ^c+!1{d%s{^vk(trR%7E+qZfWQmXpq+`H0uWOrWUjS^Ps+UDH4(s^{w zzXe4|y;9jh=Ps7sBXsVhQ5uxmPC9q9bRT80f72cozPtJ7zNy7#{Fz^c7q>0_N9z1= z-7SqueP^8?wq@gJojYulCS{_-&Rs4$M_lZMB0`##nPxjTylfqHv8EfPd6{aubK}e2 zkr%(jcAn;(v?z1^cRmMY^XT(0ACEU4`POq{;TtLqrDd5s70#!l?2Z6Gb~99-61=q) zEv?J!nQ%TEWqTAQK1o8PO_@G5g{P#N%=fD1z8ZIf1y5jV%#jl--l2;ye#;G%f z&nEt5@uSYL8_r+9`4i6Jj~+b5TIBoydej}~2T$R0@jpGR!+9H(A22m2X0(?oc;Z>` zQNr4&^(9237ZsC=hG-r`wV*msnKwa=L5)QnDxsQ}P$x>5W-ID(sjK+`lk&Ps1LXRF?|U%q0}Hr9`-- zqGn2Sm%XTGB~quu6QioM(KSZxByDwLQD;dz9d6g1mG-(DqUznHgFXngo^;fAM@^E> z`uV6?(nX(*`X9W#=z~x7)s}85Zda4=W*lx;v!sW51@(K0HCXX+&=7gSkcc`;;tW}+ zd!(n~8tQfF<62Kt*KpM4sNGO|p$?J0t~sdxK>b!!H@)1AQQfsNz}+kZ-J8lF_e2@&o-Rr58)S(4QF+n*yrj72$O!lE}gk$E-h$=n+8GQCEsyj^3pEU1w!i)xma#WllZNzMMUwB{UHR`Z}NuX#gO_~gh+ zV~ngao{-fhKUrfMCTq>>Wu1Q$`M^I}HuSSl~6l7u-+L&QyDWt!B%lIr@HcuSl#6i?S0n8vy%mb_fIAnT1=tGMn()(1;} zaSKHjk6Wv`HAa?zrRtS#h{5nWCb_Fo>5BLo#$u8?Zx26YePnLQ69n}p2Qt1Yt0$o#$PB1=Q&=QR@9o5%vZ;*m{3W~uCjY$`IF z*DYk}$gGveBFjJ)Sa}e#Ok{SSD#)fGbNC3d>Bxe78X}v4>~S9lvYE(&jhI;5Fbmle zKA2eBFdJDd<0xcvkUeQkKsFayZR0Xz^N>AlOh@(>vZsu>$mSz^)_4us+sK|VMIl>& z>^ak4k-dZLucm3p79tBVjYPHxSsl|>WQ&o7nU*43f-Kax0X~jJTZXKz@3Y93 zBWvJmLiR4Q`erv|?;&gG`yH|s$euT!LADZEBl8Yq?;{I0-$J$uSrhY@$W|k3?AIFE z8f4Ay6|&99S_QDrA0lfLz&>w579Fr2*;Zuj0_G$82w7XJ0ogWW9RjW++m5WgwFR;r z$U0f^s4(nA*3p`cY!|Z5)&t0PBa5-sLbeB4S6ek?dy#dqjYhT)S$A81Wc!hIvmHft z09mYUBeH|Ydf4kDJA^FGZbx<)*$ehD$c`ZEWgmd-D6*dR{m70X>toMCb{tvnKu=^R zkj2}7L3R>Z-@qQoK1S9rFap^rWC?*ck$r+JG4Kmyr;+s!YK80!vVlQ$kbR15Ku{*K zv&aSqjX-t|*&v4n*?D9`92JpWK$hefhU_zBFFIn8eU5CX;{dX3WWyY5kzGWV9L(p( zC1fcMK0huadnvddvMb1532uk%DzcY@Gmu?FHavJZvM-Rm$_e|F?n)1lN^XWP4PO;Z z<|m$*my$D6s<`&nbrH@mETT931UqBW$_jXy@xTvRPpOO_xUNzawHm57Y7JB$R3oY{ zsu|T^0>p}Y*z>pJftM=1IIx4qQEQ>rMtu^y&c*GDxEgMva%xP@lI%WI${BvfoXSJQ zQ&Uwm8V@xN(~P%MJL0R88l!f(y*{AWdQ!3VWT$llwlYqALmi+0{V`aI6J`fX$c~nf zoh%_cT|#!QgzRDo+0_!VoZn`K>Lp}8C1n03WP#3^;T!Ql2M4H0YBD-;P(7-iR8Ont z)Qjp>HOElh;A8MN1R8!3agD@7;eswo*HWX$WW5?aX3*8>G2yI6kNH_OdQ4}k(PM^A zjUKaOYV??yQlneLJ1Ybeu50v|_*$dKq|+LG1A>W@HG0f5tjV7}Qj(Q_iVPz!kreVW zd4;@6hLaIwBpF3g$!PK#8ADztW63!31{qH#kcngxnM~5in`8=^O43ON$t2UrbTWg? zB(unDGKb71^T=CdK6#rgAn%ZcWD!YJ5=0hrX$e_MmXYP;UGg4TK~|FY$ttp%tRY!s zEm=p_lMl!SvW09Uo5*JJA=yekBHPGzvV-g-yU1>`hwLT$$bNEw93+RxVRD2VCCA8d za)O*BACpt$6LOlIA)k`7D-uWgxcp6|H%Z`XJZVkZ@O~|LLldqxB`ryF zX3aL3vdfF3M!(HBqK2>7tD0(s&^Kd6&kdJvSQ7t+XPINI2=oTc77r58kC4 zS37aFBk97`7%p|^QU@+|CS9?rY*%)O)Zx+~Ww6LIE?0rBp=c{{iJWEz=HW{{a=7MV@vkhx?Yd5g>^Z<7V&9kP%t zB8$lqvXm?%%gMXsJ+gwVB=3_|WHnhsvdCJpj;tpikPT!b*+e#z56Kp?m3&0Dk?mv$ z*-3Vh-DD5hOZJidlh9IY~Yyr^qMdG&w^)C1=Swa-LiupOMc= zHn|9-0iPP3lo+6^FY=VjC6T&(9)$r-1x-cK^dNDhH;E_x$v`rcq>vFLl{`ANJvN{A%Q@EKNgT#6u)VNr>a%FGO@oq9*_9_|EP`N4&IiZ(GCacxSvTL_(BgbKdgywx&dL zh-6WcZ!2$7XG5$dM#=Chk(t~PZ)%A*bWN_|9Bc@d=9iXk%pa9ChtYbP9n7j^K|N3wpgH+vrCWd=&6V_`T%cD= zdLz*HDtcBP&^Jo@F+kstC;1bc-X!Texcojg`Y{%LgPq=H(u=e9_Mw$D5Yo9GdjX$_ z*z|bxB*_Sh$)9e~i|q8-7QIr@MY;2A z^6m7aEP9qM(p0LwbTJ$W#rhl!Zi}tnC*IV>TJAIQyPuS^O zEqYeSCcn|57b&`^*EUHP_E+=-Z$C+zeo7ClQvHX&!aMK7|`XIu12JAIx- zPbj*m*HMzr>y>4Tgu#Uty~q|hgG($qm3ICri$7tfue9h{Dx!*VYb|<_oxa|pSK8^D zEPBFD-)hmbR0J0C8!dW~oxaVYS1P)&XN#nB$4%JjJ1lyZEpi9DEP9cmi*ona=xPMubo&UPStCHy903Hs8UZ-JeFV^~5g=+G0W@m_h?*mSkfTNbp}#G1 zYia}#@@*r4W{m(*`v{;}BS17^mt&0pQTqs>StCHyJ_2ag2oN<#fCO(ZH3IC&9~OlX zpqz$AlhOLj{^Fr0mXd-1)~PA^^=E`GzF`x zwzWmaH8l??3=90x%SuPaCIt3m6&ELl&Tg(5&SG@sjP{zvxVW>|$GHZ!JH(-|h)DV*{a4`$D5iwTA73_l<5J zHg|xo50m=zt%7o<1^Q)=Ts6M$?C#*m{BI~-1-H1jk6{}Jy&J7>}DH_yUR})vbb$XejpSp z>_0z{vwY~l+)c$$kJdq}Mg&4d zYqcel1`i8ljVfF`X(Kgi3L4ktR?^VonT5NnhD{6f$!%HOI;bRGsuvee96D`l`%<RX~?udba~^zRSiwTQqsYbW1MOCwEJ6QZDGfcyg52SC&&(Hk8-5wS41*-7Q1sG?wb6 zJ68}X%jRkAi9mL~!g2o(^jG)e)rHW0s=Pt-S}ToJs=R4SxE+QmzDlET zP^-AV*P&1ARM8Hy{6TZ;S0wRA3~B|uSx)ol+VvAl4W(zvG2H{SzNO{!IxE&r-#sBZ zEgm;ED7iU{a|eT;6wMjCV#D0#1>9~MC~IHZkM~RNM^N98DsSqsi2)P9Ue0UifB6+_ zhwcG?J0>we^e=9={PGQRyTD%u5uHqJJ@3#_vPF0(_ne9~hQ3 zVRrlad7U+@p}nHBT1xfUs!1D4x|c28*EBgg>zGO-;k*uHmma>UxGOQB-=3Vu5Gdp5=JkFSUDf`l}dB34^^@MfH zhvoMW01V@RuE&W5rd2UCkC%11P zd!*14;#BMU8STM|f*<$|1j9^vP6EPd4dox&cX ze@)pFm*ZBXdFpf#Hfo5{xk=>G#_(2p17 z@$muT2l#zG9~TNBzKd~`t#V$&xLVHR)DdDF=qtvRX*)JUJQ!)wR|kut>++z#*Og2d zm;>=Pv2@|Kwn3bajSLJg*}GZdN5TdTj|+`Q7wj87aRiLhWiXzUW{Giu>&N}7b!!Kwl}52lVZ2o1h>RyE1YumH`D&cm4SoUkozuCD$Cc=eh6RWBTR$;6?brp2Ag(yB zwZ1VvuQ;K6%;b$FJK=tkzjfH0tqn;$*eN=@%fg%2&^~;gaYFg-6`NF!l|YTrDm=&96cS8T+s$HwBE~)NOVJPcd=BDYf9YSX z>%_R8)EDM|Vw^Me7uTSFM9wpL92Vmo@2>^UdE*2gza-xv(O!JMY4OSaZ^{dc_yOaa zng@${XX(P}O$imR7l?SCqX+v8%`#wpQmY@SMN46x8O=pc*>kG%4{kM;y2bSdN(^oAoo1Q;1 z8XXfGRvOTU4Wt!Qcg2@NeZZbD4((nwC$mbb(@J42)oY#n>!LL{G(z6h9- z{w8uqtYLesIbK-S-riCeBK=@r+;uBN2EZP)xKBx;>t&G^ zB2h~EVRtAw3=>e<)@1_^r6j_^cB-werp8H@b&1BVZ6Pv(k~}Akk|VIvYPvcSZOyg< z4+kr8r0WJHqmGH~icM~bwKc=@fL-m|SQckc+1QJ|hT zYlw`Y#E|^(7(hKjDD2qP(6W77V+UA%93@%FOZ9XD*np+6sVNQ&6XDT=x^PI~PaHZs zfnkb}pe`vHBp)lR?1(qUn+i)iI@))ac6PQm0OvGHnEh^u%%CL4#zILT(GG1`#TB(Z zv#6_F0S_cX_1#T%9i3fZ@G8^5YoN8@7UQ=%yJB7Ox_F!YKKBv0ABG1lt#wdos9_RY z-qPN%9d71|o3X~m4#^>}8)IEDc^%wSSj=Tg)oZ(Vw8UovOiMsxfOQ*M8|yk6Rc3bw z=qaF_By*gmHMX|_b5>_pM?BUl_;Xc0-q9hhvyydC^=aGFC8`8A>THSair4LmwIo2Q zx&lFsd$~w)uPfGU-Qfx(@3ik|00Zpq;NrP)a%EO1DU2nrc{MuYZD8FjNf4G+`CTng zZk`P&2d?TDeoTgX1O` zr8U+G9o;m8d8zD>t?o)gs0*oq$+=tVkfUxYUDcH^Q?9x&^$T;ONg*ODA)=*()=)dn zVY254_7-@E76*F?ge+3HuCxUBH8hU&6&2fvaxyEg@5`HA^=ZZ`2-O{y0V}bwk9$_k>F8erQ6K9YVQ3b^#oD1@l z1ZztdQvy#wN$$eZ+S0n^70c_YDyu78(Q7(Hul4qDHho@|HIA&PKL(x$&;8#h^LenX z1@~Up&I4edj$LYCXcbSgp|wS9mm`e21rXqa3h)sL<5RbQFISC3CRe^qni#KuC#P&l zZC&ZYg{$k9fFZ1_sufU4v(66)S6(fMGag@e*Jztyxl63=LosYAQE^;llh< zW^>AF%j|;9D=C;?*#+lv?lNeQxT$7tXMA;P;7!wEc6#J zb0Ppxy_pXRzhP23OjVx$UT(7F2#{B{H zg{zZ!(Uqkjp@&jFcj5BVy0SHk%wUi$uWRZmp~Eusf_pqKL-5wri5NR@QE5#rbllpC z)vMR6tgTyJv9NM=MLG0{+{*IO@+B2@Q@N2qw}`s7*(}da;z7zm;JrBC&Y>)47gSTX zt`v0YYqC|8+CpBEkyE9`OnJhtD)RMHU_q1SwHIw~f^5YK&1O~5Y_bA%)7fZ>DCP1x zGDWGXuB+K-nMJfBC<>P9qc}JTs>j<^QC3t}L2b=?)s$B+tg8b1TMROwnVQtpmexX~ zl2tcRJQAy#n`YxAtKw$EaVj^2*(jjO%F^;>g5dOhsFF$GHH6~LOG|2&B#Qn4)d2?6 zZt_ajP*fi7Nu2U>!EN($DN5Qxf|DLESe3`iyzuz!%0+9yzm-3m7s{W_OX1J?mDS+S zt~lB73&6?JQB zD(Y5Nt*HTBLRB?urb3j1i2&p*zcDYA-O(myFHMoHuB0Vu zE0LAzMvSdY79ciFESYK#1&&h@3fl%c2Y^On$C{Jtx!zC) z3y!5Z#Gnu(Lww0mURnjw8Y*quG2v^DjV{vv?W#kS44OwR&0RV$x{|Kqs>0MD2hQ3~ zt(SXHsP$cbD36cKV>JGLFO1sX1W#; zFh)1g&AhZNu(uTJY-w+U9UiXcQZTc;c5AqlpEYaXm`12deOJBMY1kI)+~%dEYX1P= zC(5;h{3$Eoj3($YykJ;`=G$e|HMR4-qk)(yof-i{Uz{Y#wJ%UIS}~WCb4= z)oR{ma!zpBKAlNbB@Hg0FW-Y8LX~R@gX+#m*EXJF8Qn{d<&{4UD%!CtzAN5Vw<89- zT6-I|#T&pPavzWvn%0>C z0(|x(Cn;f(6>}6#?t#F{-qHtJqR48AUNmF$LV6Lm{>8!qEuG2&!H!NC)S&u`0@c4< zR{zH^m+ROCTYcMML%lWD)d1b2#M6(Ql}QPm8kYr~lkdua>G_q|s&N(qwJNu2l@uvF zGtHH-q^mea_tWcmeXoaEV}m&4-`x?bZ;976@1|tCRS&tpos?`Fd6G1wrM&LBG=W|u zx1GdRaY1}f7sSNQj)uC9_|7`MxdYvyHJ)hR-O$z1Qn#bMMf3?UzD4ZXyCcrWLBZ7m zej9Ps2#nT+814Ug-59-{-odSWC!f=pj~i?@6kRCZ&;UDn4egCkiC`n|;NZs=5nS$G z**ot`vNy&h`x2|6ygUH8=Ni)}IpzOIl+}ZgQj<17?(yCo;2v-Ax^pvxI^(d1%y+?+ zL1eX|HCG|6iHP(n&Sd~be@-9fP4x(L2)p^~W=@w;G}%f(fi`(ew#hG(>{28yL5`@8M&PNIEw`6KPVZ(_o?N3RE6+xtcyQ=D&+eE zh4GzoF1D7DE6A0c{hy3nErG8>Kr{Ef;gL5?diku}x#i8sHRM_jdjmL3=E9a^_j1*` zyW;$bBUE%Pqi@l-vw`m&Ayn>!yM>zj7s}{|Qrt(-SLI$htb-gH z%58K;t|vd?qW%r{)uy{s(C1Rn7nB^%tH%G5CK7u`=EDbRto*Ug)j-i&N{)8Y{tuS} zT>7vSwan)dTq8zqkgfGCBR9(2_l*2h{*%;ht3m(2BLjC`NuJb7L5JQ09slc}V8QGxBqpo5;w+GB=r#M`W&;kzdH%G)5kk zxfzT+CUdhG`K8RwVdQa{o6E=(GIt~+zmmBHjQm>WN*Q@l=E@oQjm%Xr@>`i(%*azR zSINllWNsNFzn8h?jQm07Rxt8MnOnukpJc9vk*8&D4I_V+xpj>EMdmgz@{G(K&B$M6 zZZji)les!Zo|U;6BhSfP10#Qzxi}-w%Um-fFUVYik$=eCc1B*5xmHGAlDT$9UY0rV zrhm#@CnK-OTsI@H%G_>7{v~sJ8F@|Sj$`C?nLD15H)QTaM&6XUlNotS=1yhgZJGN4 zBk#!E8H~Iub7wK~p3MD_k@scpTt+^SxgRldNaikJ?$E?h-~mmbuFq`9$V^ z%*dxQcO@hLmbt4L`Ap`nW#n_2yN;1BWbP-7d?|A`GV+zo-NeX$WbPJ5zLvS$82Lu# z?qK9wnY)XT?_};CM!uK1dl@A%cR##hBXb8C4anTj7!AtYLyT%N_b{Wn%>9B)Sxtm9|K+Sc{g<=)^k2^E(|S0FO1gd z2g#ULx#UR}$%l=*wgWDb35%-kb1%Kb>sf zVI|4wp{wYc;v|n`#b%011Hmf0iVq{W`#k1wN-*#B!cZQKF2`HRR)jc{5@kC!C3&%a zqj+Ui%y!3|T``J7R#KctQ;OKY&tCOfFz4h)vLqwce^kNzbW*S7CJ%7+D$bhKdRWkQ z+^g53`R1+7cRak8b2?qeqpdl!>0ut-Q5_|dTH<_s9CMC$cr%-PrZeF7F}a)-!Q#6( zd}EEEcoTy-yH}@WQqCZH2=2}xN$O-3nbsbzAuO%-mhYuithZ4vd5%stQQD#`zeIyX z^3-FYpKex< z$)}suWAS8X?RD{#%IvXtN@ey~Jf$)#`=Y_i<_l71kHu4}WRJyDDznGpDV5n{@nmP_ z>j96&lbhA2|8l85{g<=)^k2^E(|*sHgo2-1*?v;G}STFP?_lwGm%qDZ- z(RuKWMqxZ{fCjYGWQK5 z>tyabM%Ig*Mi|*3q-X&~Hp-mF$k8%qFtSPJ!i;Q|xok$ZNGxNdPS{1uV`Qt$MHq?6 zy9JEYOGH0L8f0z&BaJdQh>^I=4Q8ZC=7uuTEOWyd*(P&`F_MtE!x=e7<_a0vF3T9r zNQ)Tsf={U+;m1dWo{-TT~f+yM!IFLgppnH z?mR|zOWJ%!_Q>2(jO>-UGDeP-xrK}zCv%G!*(Y;L7&%_%mNIgJ%vCXRqLf_C$VoD{ zl97{TZZ#vPNWNM|PL;W}jGQKO>lyih%xz@kbeY@4$Qcs5g^@EQZ7U;ZNm@N4XG>Zm zBR`b6CPvPYcegQeuB08q$ayl?!pM(gu8ooNWo`!}7sy-(BNs|+7b6!*+Ac;embpEQ zTq1MFGIFWR?PKIJ=_Mz?>BQ!EmwG2%zV2=C7nAwvwusr4&2K@3v{U$z_Z17*R8_#S zqk?2#HyP$K?KJHNS=y=E>2RK>zPLE7ok_`@v9_0M<<}oaw7M`$yFj}L&gaQvzUq4o zA?*@4W2TPkD4JluEK9poyPT5IW;t-wQ+}zsv%R~cA)aV!YM)#qvQ>$;cu2bA=%?P~3sZ0$b9g^R z)RbwD&_&tc!oT3h>p_g|qkARmn zlD4&XXK1h5cJbX9=*c6s-|?Od69KvoT+QY)Nt-n#Iy$;qCM$&YN9|A9Fqu}Nj2kh+TXLaXSL^< z_MEgNoU#noPl34j5;tH2Sn{7dGYv9ujuK4T5Y}E3nQ37S4ohk>CfkCve19M;gLGXS zP9kpu@Vh*n8rI(D>GZI6h^I5d+D8!Hcz}0&f+Et;-O&NxK1qJ80=kr7f+OuVgDvmg z13~pO7$TCb%Sj>#e37Mnu6+sL?(uAU^`#jqq4W|xZExeU6_h{Q)Wc*ct@>okt4Sc@`EHgqs zEL$J0j|9sc?g&wcp-rTVNlTMQ2Kh+bGgh&~G1U)l(5`pUM(_?~!U4U9b@eGI&& z=;bFiX5o=VS^8Lg9PiSxwzBR-OXDK={uY1P$kfMHB)o71ZPYNi+{OyEoS;w41|gFu zIm|;#;h-TMd^y+}+d)Z{sisxoRK3v>u{n=ERiBov7whnP!zd3WtlEckcn>)F@ij3M zgveDM>x3_S>9b*Wmh1+Od%|WVS^69uPWn%`dX9`ZDJ4Uj*yau@jy$3tnGFJ93J4#+ zigk3!&jV>)aXwy;Ni~Ai$u0Gvbo+W(yjDAx(Ie@6-W3-@r?QQntKkKkjz$QvvxC3k zw--Zm+ujG@GfurSn-uFy;b^1wyZm&#;stjZ?i^`+Tl5@*RvMwPbsZhkC(q!ecR zJejT1!qs7pQYc@@O|BSL$D6Am!hyAG?CS)REDXISORv>oAvG`fN3QpJuo$1$b@JFx z$x6%o8Hac|80#DLqhT=CVRg2guOk9Ftj?-r4pwI+GFJ~K05!VXVjX+y3hN>8GQE)l z@6}~ZVslR+geVp;y4!BWp7Rnb0_L2 zWrHD3c6WfOu%tvf0Jv?v^p_ui+ZI9?ZEq91f$+MQxm@|baf!7|KSMv0n-NaGcgd~- zr{9}p>F08Xh8v6I<@vA~CUY0U_K#$~m`^|-haD4n38&xp$Q+!0KSk!Qg#8Z*yPD6> zo`DS+dAXmD6&tO|wS98W+t~g&N{B#1bXc06s>9NhmNETCE_|^5Q>J}Fuj1Y9X4rI+ za&LtV4O#TLOTbH?(v&#wYWSpfzlZwY9}tV2nDT z-W`fRhyZ^;|5>(vP=64n%C4Is9Ts55Ht~HmrauD8 z>ksR&0&@mQcu7mEpE6}iSpOw#Ey@}`0b7tV_iNZ7k~RDdYzs-+Q!qQP2Yy%#z&@AEz2z=rhMO=Gc37pj_uRK;!8WYC zbqF@yq`;40t4-2Afz3mi`!{SJ%DbO)n-;?clKv&k&81CX1@Wx*bJ)L=EZ@3Ifvv(7 z;+8>Rdss*`0&b=`V31@i6+_$<*tL}~1NLQQE)09MGMAmgUkrP@@?I|N-pX8`6fOuH z1Iqq5O2%jj#sd^-%oZe475qLCQ`p+fpS#vpiM zkHXqEU<`J=#qEqX&MOg)tzK*nF2>MoC=R$keH@gDp#$mx2Rxxgg@3+(KeSE3ylhhO~xW{W9Pk)v4n>v7(W~LGGi$eXH*)?Qi_9b-?)^6>94U( zd;*dgyt_batW0473+N!ba|bhc-vH6IZk}miK`6fw*5=Gu2gU&=n8OXR20-^V8=s0A z8?%XK91V`cW4(BNB4lg^Nriml6gHLf?kUG5*-fJ})93S^U zz8)h$arjh>!GC{H%9C%kDuLT_NVbsxZQz|w=u+FE0V-EGq>3)$?lDHI(Z-z+W=r99 z@GFFspfSuvY;$o=U8r8&g~r=ybijCMbiy3M3Sen}MZ?TjqrbmL53+@G@{cXl@5LBnKmf;D8E3%$Y=DZ*q$TX!pn{ZYzB zzqlbpUyx;-Z(Io9(B?Z+DQh-sxmA_ugu!2X#JD&c0GGhx%!66Y@WebXWLyS=(>CaM zd~S%XSB)PVS7aNP8&|@7ysM=!*3b}#Pe;Ri{0Lz8C`GDdTy0##(bvMRy$5r30v>r7 z*YREZUbuu=ev)NeZ`=UQ;hr6bjGsdHgWuJRwSc4cx9_f)+aMd6akFttwsDhjD=aQ$ zY4W?!A>(#REe*-vV+>@rJB1GMrZ5%M} zW2B6f!}DhYW{-ioVrD$R8}$z3XZ&(1GaizcFhLB|O=HF*@)9P8fx79;cuZdYl3&hX z#uM`LSNw7&GoF-}zu}j&nDLan{2jlX&5S?D%Rkzje|Ms5o7tzHwmZLdL$vZ=vW!0) zFn^y9{R&k7Tg146=_~bB{NnF@4CDDo5K1XTRy4|q%>9}vqHDZZK&bJOV=qK#F*k)9 z>ju!b{+SK>ykgr^=0PcB{0kn@@<0k)KJX$h-VoqTA*MVTt@o&lc89d;Y3}3(_cA5Js$tveM zUrW|+;JLSC_zs@8i(CjMm2sI1z|(k{(-gd3Y9BI$_Ms3Q9T4>kWx?S9$(o}kOZ8${ z4dnt=zbBLjk0W^f>!C^^XdF(Eu!#>NbZC%-MU^OSozM_T z8)|Yk@?knOTvA8C*#%hu%<05b50v8bh|m$TfI_oeMIJ55W8lPrtX2^)s1KLJ2Vq!f zykwYQw&reSk4cg~IZ0OnizOYVY@&FReYzyW97&QD_bf?re@!@6q?ce?l-F z(;N7Q?O90rd}skw89IDh9egx7&O)UUTSmz|+ss6K3O_k8iTSbf${PEn!^1!kS_u1O zp^9wdJig-IDm8&g*kH#9RRcY;VH-?0x?uk+6j};3m*J-xzA#=G3RS@5&AaMPt{N34OiF4 z2yNxh2!aqD#3Rna)`qo(ojb&;#Yv2gwll>X!_k5uu{pGjYoB2HV^a0)pn6LI35H-P{emR518GMA(KzWHN$Lbr zR{_yE>0L?M4WvB<#Neb4BP--=(I#x zJ3Jj&12fT3=nM#jYpN?@rXF>fE6D`aIV*H_R_M$S>>=%xF#sl6`3@H@k8z)YIac3f zpAd%Obm6WSWQEQTUC6YzX)|xii-8k)dJ+m<3QfBk9)zuqH^Dw$47_jNScK7RT$>M> z55DAMv_^pj-7gRQnEU({juELW(bb8#p>ua$Y*h13d{s8+4j*~wl$D2%Je(zS*D>uR zSs&QH3T&Ge4&BJphH&U6o;HO;x9~-g7$!ou0Y-l~1iM$qNc5e2F;w3TUj}2LyX8%o zV`OdPKd>Of)4e=YjM>0m8tAOMJiGD&qsHknGE?~GGn5= z`5(CXbpeTR{z;Pb9gw~+Ao-kBEJ)!%A0r$rAO)N>U6KqSg$hVtPMRf2*+9xEApJOL zwj|{NsZRl{#(*?ek_v#-w}1@br1_FG07wH1$Ush7AW4IPG^BtG;-oT38V;lp1tiKz z<&tzbkd7!IgE?urB#j2rm;y2cNaQF{+weGMRLh$a;O4{vGL-YLmZT{_DlQ=sd2=S*oK--E^P3k5j|-RZnIQb|N&7DN(TM~M&td-XN53b0B%D%{EDPY2n#`4Y zk8FIg6bhHa_?sFKJ6CtN)xyL3P`Cp8tGlhfeNSyWJby?t>#taoRhuLxY$Qou#v+PSC^{Ci<|5S zd|NeGcwKl!0T~g7EuyR%_{Er5S2zE46Rli)Ot23>L|5J2S|9JI<$I*u`0Wj`mbLH+ zMSiV_5&6SVEBUuf;_%!E2Kd~XF8FP&<*^-#g;l~sfsS(i<6UvMoh{Gk!2v;#83niC zXFAp_7^M?A#z9)%QAq}rv@~LRkpQ&Zv5B}EI$MV)F&fJfM_I0 z3=$^U@co|xehM09GX?y>vq<4=vq<3-vq<3#vq<3tGa-=zzPc3GaE@7|aEe)^aE4i= zaDrK+aDG{&aC%v!aCTXwaB^9saBf+oaB5kkaAsMgaAH}ca9&xYa9UZUa8_BQa8g;M za86mIa7tOEa7J0Aa6(z6a6Vb2a5`C}a5h<_a57n>a4uP-a4K1(a3)!#a3Wcxa2{Et za2i>pa28pla1vRha1L3da0*$Za0XeVZ~|GRaQ;}NaQaxJaQ0ZFaPnBBaPC;7aOzm3 zaOPN~aN<~`aNby?aN1a;aMoC)aMD<$aL!nyaLQPuaK>1qaKc!maK2ciaJpEeaJE>a zaI#pWaIRRSaH?3OaHd$KaH3eGaGqGCaGF@8aF$r4aFST0aE@4{aEe%@aE4f!gu3D3SW&ADSR_dr0~T!kv^f)U#axhDt%I=zftLL zRr-`lf2Y#ltMm^l{i90%q|&EV`e&8?MWxTE^sg%Yn@XQm>2oUmyGox|=?g0The}^m z=}RhwZ@-Cp!I$4e3g3MbDSY)!r0~r*k-`_>MEbf)-%#nBDt$|(Z>#hjmA8C3Fw@N=#>E|l_LZx4-^edJAN2On@^c$6at5W!Oo2VCj zxs9j%yKN$cueOO4zS$;H_+pz#HI?crHB=f>X;`IMD$Q1Dj!KzIb5)wB(mpDUs5D=t z1uE^U(taxKuhIc39jMYlDvhdiuu6xhbf`*)sT97wCh7%WUK1&NcTJ@5)isgAH`hc8 zUtAMup-M-obhJvxsC2AKi&Q#JrQ=mPL8TK_I!UFIRXRnb#VVbu(rGH4uF@GQovG4U zDxIy;IVvqt>0Fi0<0*X(&M?BcD~NnYL#-wgINAWIKJEcpb~j`K;Z5+bA&Aq%n<396 z11+Zu;fm43`Ai@X-U9io0FWa< zh(HO;X|*cBu3il;-=Ut2=5z%JsikX_kP?XR0Vu;5H{=1j;daQSR&s#kNNQekrb+}@f$hly4Ufra~tu&S*610rp@xN=?M4MAYf|f0QwdB*2q?X%6 z#anTaJ2DWt6BpT)fyi#UOI6%*%<z@E6oG3~-6*tT2cmb&{CJHcJ48(%ho{>iBAL24o%_1B^nB`2n(%>5O zOi{u)^js1Y5n&}PAv9nOj~g;{;sf*&yohm{m1zv7y)hPxI!0{(KZjfX1zcx8mgk4cQuMixzUWV%m*~r?*=)0i`{|4KfL(md9$@td za~$R6Z~@Lmu0Uor_t97I8anJ_&1%TiXr=z;uTrnk*Of)eK_A}4k#YCYH=l$F+(G&- z&vIpg;X3{=p*d-$f)Um2D1T&$2s|VOehdN+{g(n^4;>NsnH2aX2>k576!;bWkLnFp zJC47fzT&?fuLOm}9s&K@(Vp}h+(rK7Uv!F#+<><3cfMMe+=zh##2@&lC^+B`d=m=R z{DE&q!G=HZEhsqb4}2>M&h`hs4FxlQ;M-Afoe z{v`@7@dth!1<&&begXy0_XqwJ3O>po_}3`7%pdqk6ui(M_%|qckw5TnQScIf;HOaV zQh(szq2MZi;NPR*YJcEApx~AMz<)%+tNnrhgo11RfuBafYyE+-wcmY#_5Q$rK}+7~ z5Bv-Y-sBJbR}{R(ANX%5c&k6~vnaUUANV;G+~^PdcNE;@5Bxj|-sTVd0t!CHANU_A zxWym%MHJlT5Bw4e-r*1YG79eS2mU7t?(zqI1qJW&2YwX=@9_uz7YaVsANVyCyw4x_ zbrgJpKkyqU_#}VeH&O5@{=jdc;M4qp-$ucw`vbp&g3t5^eisFw?GOAO3O>gl_1CK<(U-|C4;5Cwnd4?GG32Z=xMXcQdq2OfihHGkl-DA@1^ zE<(X!f8cQ_INKk1JPKz1z!Ok#o^QSfMg;5jIGtUquG3LfVV zJQoE|@CTlUf+zU`2Pfm_n7;ep&oKq3pdte#1ChnJ$Up`nr{W^D3`9=DMH(51oQ{hO zXCQJ0E;2g|ygB3$Hz3`8!*MNY~<dR*kn3`B0gMXt_3x~ zKn5bu#YH}tfync4kw4EsW#w3`Aazi+nl*kw3;o{v`vESKuQ5nt{kGagonv zAo40)1Ch7mBEQT)58xsr8HoHDF0vp4kq_b``(+^V zAzb8u3`G7M7da>ckq_e{2WKGi5nSZZ3`G6{7dbowk&ogc56eL0W4Oq}GZ6VpTx4Me zA|J;^j?O^j6S&B+8HoH9E^=H3B7cpGoRERYCvlOJ{&$gNcJMdqbGX(IA>0>y%KgdU z8QAYMkdol<5bz(|;F%~Ge#Hy{r+h+sHVTH{Ek(f3xJ#acg5g)%5b)pJ;1U!JKiP(W zpL2ufqTq$7!Jc=6=b_*V6#Nf=;6*6-C4b<>DEOcLz)Mi@tNy^1DEKvh;H4<|4S(Qe zDEKXZ;3^dSjvIU=+Rn>S@Oy6Xd=v~np^Uia2X1gF3SNPNKXil3P%!-bGE(x#Zg4pY zhM!hOz@NIo3sErqSTq6_-|@D8NWB6D*PwO&!d>zr6kLmfzjA{YqhR<&QAF*p-QXoC zcr6P4)(x&i!Rt`)_ipe~6uce-Yw!yY&d=5_L&5N?VaM z8v*CL!L=wjhN|7y4PJ|a>rsRCcZ1iV;06>t&<$RXf*VnA)D7N%g5ihm5rYkJgEyk! zCKNo(4L%wLH>2PYZtx})ybT49bb~je-~jg1>;~^b!TV5fr5n5(1s{)sm$|`v zQ1A&Tc)1(A7X_b)I>`z*_*fKt5(-}B1|NrlPe#EtZty-7dqXXK- z`uIpFctHE{L)w)a`f69@lPe*v>P7PehTyh+HF1BUE=bd9_^q&|I9?&QN`&| z5BF$~I*W*=XMREy@oTe)R0Xe$9FZO^75t5fwiLY5t6C4cjc{e;sNTwW3d#UgBjFzH z4?WtSd$hmWt9WH(ae4s{J2_{i=X}9sxho@)^vqy6tG-uw)!;>8iK_EnL|=}{@xzA93Yo?DjjFRYBJ^eBgkuZqk|&-sG8?XQZ|r{|X1yzbfd zS49%(1-KO3ke)MDv3zn`dUmPVo8Fq`lOLv+;8N|l^qg+DyeiT^J+s3tuZ(O?&-vo= z307De48Ph<$Q9%|awYu-xgwyGtF#VsrFJ#BT7)|I^;->o%vO6#{-~#Rt@-Pz+O^ur z{3k!v&l|!8{9L8>wiyZaH)SN$&lH{DJ!vq*-U$r1OYDzKO|P{yJQ5T4N9LqQrF4S* zkyYurWf|TfXMbdUdI65M-5*($o-@Vm_D8zYbNlhS{gHj?1-KMDCOxOy>Gns4rDv9- z$OmTBxHzRruj_pj@$TimEx(_N6OQ4`*DctBTLf@a5%*Ek=f}v-41cRZzEq9S&&|=wDHI3ZTyqoT?ZKw zfAZh>%TIh)<@(50kE$#eG0vkdH$+CJhs(A^>T-kEq`*DfyCIUBzKAE**+Twkk_91u zKYfW@7dVUT58Owt4;~`dX@kg5w4agdwb#iF`sw7xWcYuL+(7xSJHyXo>t~wbUq4fO z#~%LQ5#j$6^M}uA7ReSP%Z&%LuO^NM`)EDdH$B?7_Q})Dk?Cnw)(L>D{(5s{P2 z;ZV%p$;~7|ZXxH9TZIkgLq(d&k@`_kUyYnY2I-}GnfNL38%=AF8?{flHNdVnieZue zl=zL>zxhw6tKYo_h6o=dff$LD(j#^FHRbTpz-ArN=+RR))~2VfHzK8Ew!R1fFR`j& z2vra;DWGrBw-q=J)!~XBHf}@JFXeAK_ZjyPDc&&dpuX&W`sVn@Zz9I{$A57TNYltb zG8A~_?>y&{;5TGohy)gf^yT&kvi2emQ`RY6&jx6w)7wDUTxeoqf z4nX>OkZoF9#e5X#0O<}QHxjLp9r$ml2uPQI*|0d1va;R zM_)}B!tcUw0q@bNzB&>CTO9+xHy;r0{|eX&R?Ou31Nsiof80>368Yqo$b|H@=mgD% za?SKzj#zO^WPW` zYxbJF7&$y`P1JS*Ux$j#2rH_-7%57RdN`@Uiw+Hb1f|zWuZESmCG4fhq_o0>TVDXc zi=2qT=@HzolN!9_(16=u1N>cLS<5c=Wsk|3erZzX%MO{mR+n?R$@~9|ou=M2~2z}_jxTc zJZ&)|$R#WPnwSfi4a1$`4u^4GPieTj6c2AWhX=k9nU=OtXT!bWF&nit+#4wkx1>kE zzej(lM~A(+i*>Gu2)?j8`0LaT`DVmpfA5K;1>TJCoxP+5th1t%Aea*J4>Fp(2$PtX z=s5B+J%Rj_UPE393?{DzO2})$S>*NLI`T&F8Ssn8~p%Y#&?04kt5 z|0R$;&)M4Vdi4V_&D9@It@OK*BYif)yB_gMKhEw=??zUql_`SJuR!}Joe00d=v_zP zFoV%=LE!H+hx5PZts}X$i1LWV}PX%VHW54e)H0h3V-;W%YUPCK5zAtuXP4DOBKF7;V_Kpuy^g12xBkgm@ zWBnlqO&w{ULy@`ZwRE)4p~$H8oGI;dC{mf8+hM0e9=qPW8}JDy(mM}Dj!j#DsxHzy z59O1S)59Et+o4EnT25#81fiFvXXSI?l>T|hV;BhsQ!{&A!_y%8M)_{Y8n@Q+glaQh%>9~s4fX7M#-wc=XK4Mrw@@VGg=0KfKfb>9oj<^cJy(kk8Sc%xwTGFw4GQcnw{b0=H}a^M#kYrJetL z;q_e3VX-g#O%K0Fi5zOm=5U@b#VQ_u0xcrPtJX;3u*#PnexV~)`7+X$woTHHJ70P| z4{=!K%SbG}eAvFQ+VjhNa&}r){a?_aDZ|c}9=q^r@5LrR;&%@DWr_pxc~eRU|H`A= zYA+-Qp06Czl1tU({r{w_N?wQ3UQFKqIx-N9;B6qBG3zyt=8Q-0%F&FuzNgVWI>1_nreeSck7S9dnZJy^aewoceo@ zaZY=JTiSQ={O21~Nq5oyg3@D##X5dV3W8J+b z18$#dX5jR*W(GF) zp2TPVa;i1(ZX+O(~uxLS^+k9YJQKxcoqCKRn_+heM zgB;~@D}D@rd~RdkkD^hJ(Npw9=WZJCdz>anx0?nikA7+2tpQGtm1S~H0&MQb0(>6y zakBP<9ku5@+_7~}hoo%XJ6mmN3SN!TAKM0eI?QWa**p$P{nW9J2f&*2GlYY{|Cw{! z9{|lB0P*C-w(b9^Q#rrG_OO%?#3y*%UB2K|fKvMEU!`o3(&3TP^t#!nQNWr00iyN- zuQp<<;gJ*5i^ps=JfB?Pfp8ehZm8jrO=)5J*P`~R8;}%A`$>A(H_ie)=7ldfIny8W zvbMm$p8RC2InUzWZJ%d}?Hb;K-`Pcv@bFd5p~MKU!CB6h?7KtBg%=&+^$5Y5IgLm+ zt{hIngwR0{5u@ZgI+zZpL+E@uly0HJ0?X*|;5T%H6&baMu*mqm85wh4Ci#4P$>{<^ z@YwJj{QcH$kR!a-D|`;(7;TR5c#3DO0qGGbaf5F>y4Ps5(CY!DeXRtX-ZLeG+Ur#4 zH4U($XQ4w&J~o(J6XSZE0!Miq~eZ z4eQuqprcbJE6&Nxn3VgeryS^5k10bs>yP!=YS5Br96+>Pe;(MxX#nn^@MnM8Pm8=d zF?*vDt)3SK6X<#{fUUBb+Is)-^Y3#X{Hamy^AosW|%OWRD1Hi!_r{A~?G2o6?&k_nR#chl@suWI-Z9np#_v?;3ewu-SOl|hLXRN( zXdykEjtYEDM+b+{F~PZXZ15pkq+LYEY4_6c`f@tKIGK(&KA;mrm(fY#lj-E}w{%L@ z^Rzg744rCC`*XUGX}_VF(|+}?8Q9nm1nO;cO?BgmAcbj5hw1yv{!ee$)~-#BaLY}HOyY!z1pk0H+$uq_98dH z+ai2R_Sgf)0C4{$Jw_Coeu&oSSi0=;IsF8v!##I-t&ukO7{gOfuv7a-Nsh%Ddqh(C zYnAfdN#zfB?!E2yc!q4BHoNuS9jQy(CVCpZ?cYP`#`HcSsrP=R_pYSgqg{J|$41K1 zD&SJw;oryp4+gh?5oH&q_?V>PKUIqFGZmL7Y>jb|5e|Pj&Lb?j)SqDQX2(UgrLA^4 zyW79XvJX>#Vp9DbO8rGreV8qqFIa%+zb8$J*P?6oK`SJgQ2iQL@vm4XAIH~znO7jk>`83D5TY94JIN?42^S|MXglRe&% zOy{lkFY|O_=9`_=+GV~HhxwkfcbilHhi+s4P!DRpxk*J_-R4N7+nnaL%5!!bhvujK z58cN8l_0d+%uj0WG@<^w!-O#Bv}Wr+_#YIpe{l#k;Q~_;nlhi%|7I`!bg#$mj`@-E zNyF(L?=hR3p{34(JRZO}cEeAPY)m^Qp!1{C#o=l_!AgSb8y((${dR0B9WOY(W%sQZ?u?n%y z+2RuyUcPj;&6iN?toAIJH_IBN;2-u{WBVt!(1O<{3qDshOM|Uhc)=SY3mnt7bG*J= zU<;nfb~&e4^Vq-b)sWII@ZFND&DVu1KOp_c5JDD)U@wM$lj)$bY1{)wJ^VGoUo-q2 zGj7~N`aK&C8ZAA>jz{%-?hii2_icKNE@eST;4u(9x&3pGey!3nGSj{_XY7R~$Nj-S zK(}Z}F?(cIBnM)R+1zKF!i{}B#tDL3>@%B!XN$cO#ciDUsP^pr!KcR^FityQoYiCe z&}5rq-{?2adDJ-X{@^pIY$f)+DaH1;RJOSY+jGEn5xjeET)KS1W5(q_rZXlyYFu7D zvB$UyYFnZ~W`Btu)y2I5Q5|lU7*Rvr4)NUnl5jN4?~_lXVSYa=nx*b%^W6TDoM?`? z|8z8m-)B*#?&tE{{*t_Cp16NUG>_l!6YZn!M|f_3Nq#h6+&?>-&+ivR3)KC-Jh#83 zU$mdN-yH47@Ar@PSN8|--2Re*(ShRr!stMLe^7Lgx*z4a{Uw7B7&k@-_ZYYRm<)f& zxMM?9i-w}v(cEYx+BZ5N8a-&-U3C)~a}ybI6B%?9>3L2RrQE~N>x_Vq({Zn22T3o%Vu6`@7 zUQ<`U7guknt3QdWw@hC{UJW%J=}1S@OGkdk2X4N@PbKa>=m4<;#$RCy_3XF@jh6}O zFDsU@; z8)f3sIBm?~X3}NGn3$x?AhoMU%u-|m(-hX=XaZT-coSn4mfGfxNX;gu08s~xr%o}o z$^M|*kSZ3ZKoQ?gIO-`Ia9S!bHS8RNxXg@HV5)((BPGr#Q?)_G&{$w`PKZRibjGU63S_Xaw}(Vb+K#J6i4>+O^g zBA=Yha0Z=iD!En9m7os0C%_TE6}A%SpbZ=mxL^*T*Z(uk=8 z9-Q6c5SM1Bkaj<_TrN{~B*J#c~6!9-wly`x~fD-J;! zZ`g(1>2Y$BAGJ2#hdKyd?0+mE3e|ZA$(+531B;r1d3Ci-15vHlV<1>v1v8IAg z#)bMJG4TO0-^az;eCdIdpaMo6h&BI%UPhJ8uiMS|pvOz&;`tvM4j=S7Tw;Hlhdk)@ zK}>7>dl2)Q!I;-P2ez2>3+#%mt(?KKZ!UNbC>*Zka{*Zdswn!`Zm;jSR` zu-BX-`K~;9*sY^MW%nK>ld*Qkdc>=ptcHKY5pp41gvLo>6J-MDv3LNPW*7aK*9iyy z>L37S%4Cic=W(LQ@vWuDyq><=-#{XddA;~xRr4|T>E_T}s4ASA2^}RBRn;x;2`x%a zZXUNk0u3z&=1L31_rt9j(-U5P4f6?Z5{K+3>>ZBF{{LD#6Zk5MY!9D9a=SYVZ~@sN zi3(7S8j*FJD*HJyl)%(p`00B*Hp6EBE4sqH@4F=f$vZYw4{x zbr6y|=&m5pl2Ew~KP2_8B83q`*(pwkf;Am;VchExI~045T_}_ziWEX|?Boeay{E(* zQrK1Qj`vZIlw&_)D6C_iJIa0?Pgw7Jq~y%HN9wpoN;ai@Pcc<~BCyl3lq&^JRa^yYoOU`z9!aAkg5mH-yq)w}8e8n7ugSffd%~YwmWoBBL znZ3)zTsNxu9&?hs^)#o*?`y?!cctZRvCOEnd?uDzm6iiynOA9fNGwH_mh)mMuC$yJ z%W~V2x!qhPJ8+Dia*r=7%an(@>!Mk*-CQdoF9Z{v^CV8S7l)AsYDrM^-sl}8Wqu&$GbMzLl2I2-NNO)Yngd^lG7ntA({$5P=LAzEn?{Z`CIha9m=;WnC?B~YrfD`Ks|_(tvky^ih-sQ*^!^PoP1MwA zB41`cB}L)R{~Gj!#*bqXAzArLD?pm30+e@o&h;IqYa2^=z;H$(UGv}|TH1pG=Q1@lO z&=fLVU7pBHp>hRm$kH0KHRV`)wr-X>#(&X}t?NiI_bOjB$gNz58M1?!kt@!w@O-%Z zwr5;xmF!@?#<%Xa@&;Gq({bPMqX*8`Jd9GOjoHew5p(Ry95*GaJvlz=S~;#vAu88j zP`_og7p0pr8(M$${Zf}M(I9~x!;iw=30zZjyFcmXas(+qhW4UXT+mw&^k>n zEAi0jYL0eBM2Y+_)mJnsa)E4jrYqED#wZUFloH(O>tU>-nE+1;LPfq?Dlhz)dqRC| zs5!{fs=dy~)I3h}&QWLW#{$3Q#EzX)xxSuEk@nb_yQ~HCG80>)lu>>F`sQ z3CeOo?rO%{g)fcEnx)GyROdDmth zk!Iq48Z=2WSUDcxOmZE$C^K3*x~{-JwL_n*>2k^^Nsa*`l)TBhjs)7a?VhsYtYEl_ zOuqKZj|xoy(tA0*McxY#etXN4-Oob}(~gPh^B#t$XkHuHy2_S2V=zUd0WkYPfRAPWQfN_D+q{>Gg z^ESDyY?(5TIxEUFjplCk*3)#6biUBzX}Z1y`pJ}{ou+wa>8PsH+*v72*6bun3c8at zUGrE=P11BtU!p!foNmusBILU#Nz--RM!4=zch`L+>3Df5DI43k@E7NO;lGvlg}Rwu zIHHAqd4Ey{^62spF^0O?8J-?3#y)E&FJSkWf09>2&a-yVfP`nDl_NO1pI})06OZ^z zkNCN;_@^H6S&Fy}RL0L?@h?2$vpwP$rDj2AsFccA;#<-1Ge`5V3o}!^a)w8F4;bzCoBfd-#N6!Bg(8m7PuSvC3rT8gkNAU%I70s<9Qth@@s)0I^U3ni+ezr1JmRYqafyso z(MMuC4jSxfXKO9dtWIq``UA?WZmNgQkrzhJZA4t6ol1uWvl90t%BrZV<=clUb&E*E zD<8ASTE!WoHJazG>T{Gex{aZDuj)?h8r?H9C9!L?O4UP&UE|)1V)e3bYa+3-&Q(=< zm+B_><;y9xa7r~hCe%mIrN1n`rSAC35ERx1HBy>n8B+gR-!J}NR*@v%Ym0R@^-);J>hVp81IDr2ajNma!2iN2uD z97idfOkJv6qOMW5P`9W&>K?V0dPW_fUQz#`-qG!;k9?`CZ}hX&FZyHZAE-_P0=?<> zz-$^Ac!355&e9!50~%}$ry<5l8fxsPRO1Q_H`~w%GmFy9`zXWQL7C<^lw~!gky5X- zni#u^@?sCr{}EzPUegyvTp zLkp^{r-jwtrJ`zAXi@cKT3r23Dz5$*Evfz?Ee*!XF}gl-DsC=45Zoe%)xM^cH40@j;D1sH`4l=M`%MWrj503rWb3?rp>hu(w6JC($?BN zX?)n>OPlMU?O2awyYQrP6w^1W{t(1(dv=~Pk^I-N9#&LoYekCLX*S4j)#Qql?zByHeoNq^wFN!$2_q`llf>9EKg zVXwGU`#F;HOaYoA%oZj+l&TciDN45Tz$K0C0V{aYG<8HmcIc?5zZgM-GketpF zZ|lZ+ZFlmdb_P#wca^8KU(8cGL~(wH&$yuDNS@ZIB~R~kl?yv>;u)Qf^Svp=GgDgg ztdy}lJ7qP`N%=d^?J|Prbt&fgU0&h^T|VW7U8{3Z*Z26ou9taHw-&s(TQ(PWug6Qe z_vfYEXYsP`PxJEbC;9#!QT#xUWM0uDmmlm=$}4-k&Z~NS$0a=<=QX`na%t}rUfa8X z*Y$pq*Y`fj8~Pa3)>djYnqsQ7qGTFGDOA5oHA<&}VyeU6(Hy#6OtttZJxT+_6yz=R z8ub@bRW6~=sGpc(`EHJ;zG5lK(`p z&0DnGZ4KOQ-LXwMS-;U=0=@W5rxGN(6%P zQ!r3K!C8-dL)?^^*+?SXMebnb2(v}ga*%3LE%``UZK_N444dvQc zt_gBYlI!(yy-}_=$+ampqnoKdwUAi0lz>~wwY6N^$TeB6ZKbE_KrvRXgkOc?tnqS< z6Zd%et9lPrvnGgpDJ2DNBr8xOP$y7Nv@|scG?Kr1a5GLD9~mE4x{2vVGR(1NuKbO+ z<;v{^E_#{F&*%!O)%N%xzlX=<|C%Ap=<961^?Q@Ao z7VYC^`MAaVxCMROuJduL=i}DM$1Tan?Is_$W9(UxV!TS4nOtDe=!O0sUUnpv%^WUHe!ktilv z8p^4_6h6#oryNKP3}Zv|lCvSow%HI3(rkz(W;R5vF&m;Hm<>_1%Z4bqWkdAEvLX6c zIj|(KlnqgU%7*9@WkYm%vLR|Q*$|bKY>1vkHbieB8=^yy4bjoZhUm-Vz#H%;3hX!_ zALZtNeCUz`@*P1A$Y=04AYXi9=zlNQ9!F2{38JTgXMkscO~7-&^S}$hi@;`J3$PW~ z2D}7p2X+8|1a<;tz%F1n@G`Imcm;SB*bBS{ybkOG-T>YN-U9XmZv*cD2Y`dXyTBpf zFmMET4>$@O1KtOY11Eq-cnHx4Fr5TG1Wo~`fjKY+`? z72u!1Re{tz0RvTlC?FaL00v+J77zo(0&ze*P!*^KR0o1U4WK4a3%Cxb4b%bZ0`-9U zKm(v5&H^d6fE7_P*Gm}i+B=D1p>MYehYyDc$*32!#V@lhyd2Y?LJr+0mZN`hUsqL9$*gK z2E)`Dm;%fK?f|;r*J&_K2WG=M6}T4|hkN7zV_{tbEC3b)^MStb)=$7s@zX^8VI2V6 z4lEIo=nMQ9MSm$Nie7|d^?`62rxSGy^b9f3|jXCMXW0(1qs0o{QfKu@3-&>QFj^ac6>{ec0%?Z7}_5O4=D z7#IQ!1yX@wz;Iv$kOrg!89*kG1&jo;flwxvZ24ExbFz_G1Bfz7;W5Dl#$ASL@ zeh)kWJPG^(cnWwLcm{YD*aSQWJP*78ya;Rtwg6j!ZNN*wc3=naM_?yV2J8ZM11|%6 zfLDN5fxW zA(r4V1oG$n1@qq!z-ct%;fTR7U?`%I3eymnmICX5mB3tJHLwaIB``e*41#qaP$X8) qW?75O!w;k2HU>zCbu>(AFl7NFfD9lTKa2!2#cJir^gc>nar_Gp_O$T; literal 106852 zcmce<2Vfk<^*=syx4U;IjpUPD&s|0?a+4*w$_69JvMpPdi{v6>TRurA`D_(i#SLR> zXaN&SAoLQzbb_&EdQ3@3AR#0qKnNuC-aDcF-;}*=bE^&a{ryAanSJ{{Z{EClQ+D?4 z+!H_C_Ygv8YOn^QJ}vS3{OHd3)Vi+ry6C3*0KymzYuFU;jI|Wy$J@GM9c|H;{K{B! zv|-nh_Qvj(SOEDk3Q!#U1(1qSMCV@-+twZLh?R8iYHL^#>x^{;PynMe%3Idn))a3J zpb$n`rt&6tHbh&Z7!9vvnf#7eQ%kI&E5DkOtK-dW(XQ@}*ldi{`dwYIPTc=F4QEVh zjFy(n_P6`8mWS1#zrkOURZ_AxYjkK9!Sy)JAF3dJ)mQ4n=~<;E8-O0k;PkueCk8!kriTrB$Y+w@&!Fd->4OY0scj3NwA8L64i|Oflqy6qEd^20hPApJ~u51f7*T$0XlO zKh~g!R4$+K&ok(GX8J;dUSXzJ8uYlCzRaM9G?V@{oX*9k%IX8In3 z9yimEoMhYxg-jJtjE<3KrUwmrg_%wadfZG88}v|`Nq#?ro@b^HGUye8&I~t{)2ZR& zX8w@|e<0fBbsW9_b8vJoHeVIWIi4m2RTVv4k%=9$|y~0diXVBwj z`bL8u5+g8^-)PYD%=AqLy+Y8LJzF@PI&R!d-)hi9rjgs( zfbr`y05m{Ep8@C%Ma%${uFn9BE@l8qH_rfyF#|;O8G!MN8Gy+*jogYc14Q&0fbokN zfXNs9j4oyXN;l5{iZKI3^cjHhiy46On`Z#Um;oZ@89*^+fQUW=FgaodVEUUzZbi%h zOulIbP>dNMVx9pMV+M%C&2o$xAYz^Y6k`U6m}daRm;oaC3=pU7C1!xFS;HbQ1C-&w zh|+D*oB=rGkId4_6lDX>2}PrW`~%f_gEFh8bl2@o4^%}ozrQoB0I!?Y5WtaaUrEWa z{u$|!3DF5zAyw_ayl+tT2hw*{D1M)&OMK+EqiC%(AjhQhC=bY z5~XqZn4xPj)(uVzspb6(s&O!?4V^K$c4||9df)H&4bozxOG?LXtytB#dI?--YfDsr zX~|Om+$}jd(cyqo2W;!(Q)^zm(EP1AX*>g1)}&(F4eu{2|3n{;JANZISU! z%>#0S41e6>lAP#7-_B4$L44@U=IY@jikD4muU^qLudJlxxSWhoJgo%#tB;vDDkqu` z_3G}we2uF5PfVY+5C`kGjmhmI8)j}S8`W>e#OiUr!00`J(Ira5mce_*v=5s-Kvjov zefm~HIYqvHX*tU$^qtx5&&gW7bnTSR<`qg`tQ2lvvUkYB{K)L4xdXaZL%ExCvO;+i za;Ag+>j#4Vs(Q?x1(QnxRPOXX8w$D?@14+`S%E`P?&`KRg{`YsWo2y}8dCj>(?j`S zpGIxT=$z6~t#z5}2IiC%#LK7enVzw3dX9fuC{R^9V`Eu%?$~yU)3#-03@L1ztK}|O zvVKZq?PR5I&OF9He^O+2{oKsP8Iz%&%hOtRkhKNfWqXG#Xd9B{3q*7K!m7~MrNstq zt1W5t_aU<;MGJikwP6Fd)du|jEj3{OV|?jLh7QbFR{-^B9khIeFOauNSvYy{FkfhN z?t;l{u~wbkxH_W(2Nq1v-BCHL$k!*MWkKtp;#i4VP%vp|(Z=>gWLva$Mr`heenGHn ztZW5gd|6p!L4NI&&I(`JHq7*zJuV-s?0(De;v9cg&W@^eMZWZ`JD<@viXLxZ_+4McDmJBQ27|SNn`eCy>7i%p$CJrv{1b%2w z)v&v^JZIAIsT-SDK=~jy5}LTFb3Y;dcyUT`?ocdui>RSiw znV(-f)sPGI$=FbkkPG@R$dAza@^b1*htm4CmaUz*qh;u<#uBw;+tOjw-zGFqE>U;J z(m?+;MeQYOT+olA@-{9m20IKdruF82FrX_i8V3b`VOz!CA#0Wlo$VX3zTY@%588e$ z>xxa-sc1d4uM(R%pvbc|{AU9fk?M3N3d~E4#nTqEBlfYX@Hb zpxO0H6ZoSBwE|u*r+G}xnn@*^(6e}R_W-4DN!gsv@>NrJOpFx8Vp^?`o4z1pF!)K{ ztZ_?gXE)EKcB{pteNjK!FR33veFLJr!rk!!6Tx2AYv_Mj<*SD71b^EcAHez-wOdwM z?d&e_*Fl-k&I=0HfgjDx@ej*d-OlsCyZ0AYo@jPCoz8L zzk3E$L48=ctUhqP4re6%a_?d~o`XM3-BDS4bob%`T{|WYnMwTt#uu(<8^|kBYuWh2 z`U#a^kkE(n=ZNc_u`#)8Sozb~{ls;Nx{cw>3M+RkSyvRBJEm)3l+8cs3nm{owS956 zSx;(TL(i7=(~e)v^-QCBg5Ohr=k?vtZzuEfS%yC1{x)V0*1x9gjPZFZ+*~-7jT?&> z_1jsseoE7N4HxzqI){!obR6C)_|n@K?U_#J0qFk&qtK7%X43fq#t-oOdO9y;!}!kT zQL@~64fARl9jA_B^FUuVuM}-v592|OL0{p|i>%Is{$5u+abP-(xA8^uHnk0+d?d#= zym;4oj?aM&8aggC9+$mm%%l-8PnW`cQW9eG0@aWDRqLQx-7y&dp#L{>J!!k`(O`aA z;jfV3`)B#aGJmCdb_T-36a2nBIX%a}#3`p8#&7>}IlV;9i?*(t-Cm&;@D%1tF^}-^ zWUn9QMVuw(nH}I4VBcAti|M!$nbt6ORKGQoB1OCB&WCZua;@}@(sjk&va$JVi?_l3 z1b^$WSsNP?c(7AsW|x82uc3YDI%99yj-~6T!Fncr5LKSwQJdY&=gy=2i8l_-%51;31gS8pV{uhYt#ltHcQ z_5O17wz8_BdVg6+`!}q2Vcee^PA!A1d;&M$1<1HWYbkgn%o{OiyCt93P-*Ax1}`j5?Xy8i4M z^bhlOCLM>_JV*O$wsqY&k&a)SZxCxQy52PSc>mYs1=;uk^P5-)vvp_5ys1rbF<#GQ z<9WL3?=v){!ShLtdbAQLfpumiYhZXo5y;)PZPMV`us)>iKBc}QyWc`s&o>5&N^yO3 zpsxc5vbNRYkQnbbF4lH2{`K{_DI1zds}C&^|Gub+SwUEePHX@9Tz}Z81+ zdqc~XO^qF3`SBQq5|`rb1h4^1V^dQM7$(812XSGMK;JlYb^^l`CP7?cG>E@eSk@71 zj5Xz!bab@uDCz8MZvf6BjEMPe08PUv-Nb^CFWwGqSVA(;1;2`I=iA>vAS5B`9Ad#xF3WUEvX{ccWTh`Lvumx^ru$$4w#tzQG zuN$LXQGV^;nOi_*a@A|Px3sd@nz-OP5zaW_1&FyJ365MQd2Yapp`pCJ6LXlQCg#&(9v}>=$FC{Y2q$7 zgt*`u=$t#a4(Z~i&{bS9Gi8ViUB4hT8W+N{9Ku?PX$`fb96EbCV{d_%Xfd!CL+~P* z>vB6$7Rc4bq57PkIv%~sFhm)5Su@eQ%*DB>=w+s9P(WqJKGo=YsMyqr-rE8+6AqiMGK(p zItd_sbsBiKPBu|>64Oy_YVU3XBZ968*RR{!0nSCByVh-DtzNecY$z@}x6&(qv#TT8 z)@fXFt0nGsFk8?|VF%Ha`Xw_9w5+(xn$2o5)*cBk(>GMVYb(r;+~6Iw+U$~#5d@~r zF6Kw&(JPN=R}3x*5QOP)reYP`2U2z2vK2Mdc=JnE zR@Oi_XMR>vR#skJ&1?g!0S67N>Yx=$Xs|wT@PQ@{8mt-|wCNJs3~)EIe&tmqrIqEN zp@a%LN~oZvgbI2}sGzBY3c5q@;SW-JXdEDxkv>{epTtEran^*Re5n;QW&68tAw+k6rnK)0~CHrXuGOrnF7g+P08mYG9X&Mc_9ZgmOh)K_OKFEI^y2}Vlg z7SrW1yNZ#op8zu&H?O&9a}%TqR%kY(f_jr>i<{O)6GSeT){zKGWmR4ETEi@?6+uz3 zR3E`XNl-o7u7a|(suF6e*Q>g$YF=F>*xz8_1DdW$bxlbPj8wepI*N|OqUO5UD9Na} z-f)yk4WTy*sIsi2Y%wEPeIKf%6KD;gc>U6l8sbFOKcG6mpxcdK@fxzq!#$1@Ue35p zUd}~vTX1l~;~A^)c%Ek-pH?w{CHS}SXZ=F>vwq3^Ijf=y{Mj~++i7&%vD4_dW2Y5K zXms4M^U-m~PNUsD5m*Db4DSq-`bDyvr( z!YBs|0mvDCqhAQW(Jz_bWYR0@qgAC;B7JtZ5E7$2C0E0Oh))#ks>U?(W>qb%MTOo5rIV|{UpvQ}4Qi!T8`cS&ab5o>=D{hIJiY4VM>MF|@fc$cp zh61fySVSg91IFbgHXV#eO}bJREV&pJj7zXMVmfC_;RMgc$EKqoh6Yo*Abym#s%_&0 z%1}CDTU#(1F|Hy}0NXS%WQsi$2&Y0AwhdGY0FB0t(-+sX-Jt{?I2NTN4Z|22ppP77 zC6zE*L#0hSCiIzOt&Q}5`_v&y2F)Xe<~AJ&UWS)bRbgq64zad{^?VNz%rved52htz zB7&q0LlWF3cokkv(Q9B~(XDgBCY;fBHq(mjr?dn!$Q*0POx7X{M({eko|d)&_LicZ zE$wZv!$Z|v1ZL*fb`2NNShEI-X@siOch$3Rnx_V>|!q6{<0o3ac}a2#)@ z1;bNlmRUw!Q#;)|%68Cl32x(%c2O*S7_Q^WW>WUVHL!MYR`79Ft>#TS=R}+BlbKXh zQls+e-_W^0K zAx>v|G<}_{P}7sRsFR@wS?)K}hyN@)2>_>Y)BFsCcWkfk0IS8IW?Fkw6NH1qXqX@Z z?^#^<*wr&nyN###u}s?4ZWLL~FdBv;Imw&DoB2473- zdmXGA8(5HkcSp3oC05tG1EVcQJ^221Lb7S*Nzf!M<#x}e3G^bq?ZmcyL&Y;zh$r~Ds@GJ3G2)PxNr_h|3-QIFSX-KiM@oiW%$rn}(6AiUbpn#(1vDG}*b zoXr3PKY$;kP4y6T2($U?rcdRgXrh&X0&VgzZ<9w7>|8mkbMi~kpXSC^p84pp}3167{xt%dEH5&UQT z6s_f7Uf$c=5|Yq3=XU4|~F z?EfL?N)CJl1~h%&8(w+CqL;49ty|s%U4^cuus481XU=Wey^E^W-4&y69HFAC2!0E{ zod$gGFrj=W+%8n#A1CMv`fJz_cP)mO=K{X=i zdfr;!6LbU5{YcP_Ea$@n?dLf^K{xT7O3=+b7a-^so(mClE6=49bQ{lQ5Oh1w^&#jE zp35TWPM+&a&~JFIKS6i#+(3d3@LYtTyLoO1K?iwm7(s`4ZUjL+JeNbzVV*mRpnG_3 zG(q?B+*pF{%A5puh6mYJ&d8bF~CL!*jbu zb3Z5OeV#j)pbvQNJc2&tx$_D7i03XO=wqJyB|)F?+$98k%5#?z^cl}xPSEE(cO^kz z@Z8k|eaUmz67&_%{hFY!dF}>+zTvt31pSxiZYJnkp1YNx?|ANZg1+auI|=%M=k6lt zN1nTzV8nBW;1e63J4~>T=k6ug&vW+^tnl1}1gkvvTY@#7dzjz=&pk?Tkmr6!aERv~ zCpeAg{zz~-&pk;n;kiE(oWXN{Avlxg{z`Bko_mJiFwgyi;4Gedj^J#b`zOJDdG22X z_v5*j2=32w{~>q)&%HwMK%RSz;6Xh12Eh@YdyC+~JogU4LwN2zf`{_l2Lun}xsM1Q z&U2p-Jc8#wBX}gweL-*z&wWMkD4zR<;G=l%TY__W?t6kq^W2XFk6}4KCU`8*`3WA! zb1K1kJQpB%JkNy)p1^bI1W)9-41y=|Tpxlb^IR6e`8?N`;3+)UpWp(X8%S^=&qW9> z;<+INPvyB`1W)6+5d=@?xg3IL@Z3=Z&*Zt$1kd8Ru>=?MTpq!*d2Ry1b9fHonb?E{ z58}~QW6EMLhWSflK4G~sRW9XBW9S?slVrRJ=8U70FdA>3Ip0w(d~_F+bB##CWpGHf zr?04ct)kB4T1CoauOeFl*lhufiFe>!cULx}0uy9a1Znm+=I%n-`xN>j-4mN$U>C!3QdhIQ>E{LJ$SlnHAOL{#jCJFw<8c9QoYrsw z&N)sZlPws{Z=bxg7IkQ61z8AZe^XP~Fg<06vn`B{K zZ_L8J-k61jy)g?Ldt(+>_Qovi+*?D_H*8b9wH{^l=)aWJqyJJ?kN!(pJ^C+Y_2|Ep z)uaDXR$*7!xWxlX^k@@q)R8hjr~AqD-6Cg^P0O~}lwKH(=m*Z2RJlYX3+I!~yQTma z&LkUE?Qt)?=w}29^rBxPexMiq`1?}Ml+?m>^S(Eh#3ChWBN!1lT$XIQ<-s;0Fo(0r z<|{oWr(z!Gku9He9{SFfb4eS?i0uHwN6_C7CjI3bw!dS)n>M(6V_XUmf~lMrPJo8r8(ej|8!RrGe3IlEwFK~`Lx zOH;D3fyQ3-S}^6LAz7SJ)_+97G&-r*auWeuy^1qdwJsJkg?sf{G~K*4`HqYCQckPu zxU@B8);-LnJBm;;uBDuh&STd3PTtHqpY9BD`{-QOipa)y7JOsOpzxkMZtZ=$3{8Gb1pBoa|~T#U2@1&{lzWQx(_ zqNL-ZJ#^1ItIOik9IQrn4O|wVc2<|gr=8Vh@o8suS$x`AT^65qR+on-Gi$F8Pfli+ zhbJeq%fpkCS=d)Pc$s{G>+JIIDi%IeX7DXT~SrK}$Pm$JIp)e+*!$A#gNwFtyx(#TKFARE$Xz$OoZv zAS>sQtt2e*t(;A^*QbZQx(iA~!@BEao(_{0W=wU-v^GL$*@Q0}mL!q3Tr*kYTLW-8 zpKK;h#N~1pS&N&(b(34dh~iDIlQp=P^U<(g=u7qwl?j@OX2Gj-{~sYb0$B9eAr{#| zP%)ZKZ~n=8lSh1_Ip}D56Cxn8Oh_K=M9?v4F1`CVf{x|6zY|o#bI%eqj|+aDpmLsj zfuQ+3_aZ?Hc<$c>E#$eE398_^R|#6gbFUM$nCIRksFLU2CTI!Iy-QFP*YACTmh#+( z1TEutKPG57&wWbJ3ZDC%plZ(dB|$Yj_ccK)dG5ait>U@w2wKf^KM=HrFp2x{QD0R%Pj z+#rHtJU5u2CY~EgP&3aBCukGTjU*_}bE62_%yYQ}ZQ*5%A*hAZ#u3!YY2yiMXnJU5k~PM(`iP#2dnlb~*%D<)_=zdMJZ9h`OyK|6WwSb}!( zTq!}jd2Sv-$Mf8Lg7)y-LV`}{xi*4+!E;*)I-ln{2)ck{y9m0F)3y_I5zp-;=$AaVo1lw%ZVy41a4*>l z(TUBmF7Zt||J+-nA12f2wy@rn^|K%X$|*GDed)ZFmE{n2l%447I>T(DoTmINq@1dp z4)Hwo1qDInOpIoYGksjkPk%6l`0H57(GU=Ik*l1Y2I77WvHB~Ca<2c$G<1}*56aec z>+XuTy9p9eu2rr}1Kob@Nw*46Goai6-$Us2NOJZ` zK-rH`PNG4Ra52-|98zvlZh^Yerfle<0dU5sp9Cm59R+0Frre$evhILSMs)S8i~;30 z5Z$KVqcciCIRKGijc}Cs)~(cRE6h>a$=it9VRoW+)Q+K?=$Fl80^%&6R_+)q__0KQLQH6_YJczznV@Na2&J?IjpA$|Yv z)DV_IL%A}+rX@U6nvzSu&uc}LwnVEEdI=Wi&1wwgB`AZrasXUEQzF}@Tvr)cK{9NU4bfkF3ac5Pfa3pEWc*QHrCtd-NpHjL#|0rzy`W|0K$D+>#Jw>93yxKI z+g_Yh1g$?@`7dq#Z`05)I(*X}oV&H9yOStCaKrqF(Qc!at*tQ+zB4d-uk|YBmSWv{H9*JpwyxD3 z&~535DfA1b3ZjP8G#Is2m?FYdZc8qhI@Z<+=T1$bV?Rs{LUKcU3;lfpxRD=kZSC%& zUpnNkpr5YHCTfP7nFeL_2`kq@SWj-W4L*nHZp*bbaBe|vv@yE1i-w~gW7w4Sj6_TF zE5|Vyx*F`*pF$`yTkQ++xN1K*jjKPDDV?P(U(STpfqwY$hXDNtLfW$V&FWZ3JlYc9 zO{)`7hkzubXmRLMWwf=vF$zaNMVq1xUF{va0_rgEy=Y69iH6bXW))n{i!z_+Ar>8` z>C^(Ofv+-VA7{ENnSTYKEZWji4d?fOWk#qY)70T=4p?TCWr&g(S~u(b?l#u81>i6b zskzw*siUF&xs9YvU(wbW+Zk)DhPfx8j)l(@-TcJF%setLq>fX^(=HutEA5WAG|q?f zx9G=4x;~~N;e#t^qlWx46D!nmqBGl!K?5rIvcEOD6{AXBO{2n2y`?3} z);wyVT9l?1sPK8iXcr}n+6Pql4mff68e0j%$W<2YgcH8hnXo!bbOXyhX0zguI!lE} z|EWgL;UkWtWM~u9+ChvX52;6|fdE(n!r@oZjxK&YkkS>S^YvJ#5sXf5s1K!^pNH9J zwX+F68XrTu;ymb7rrC1^d|=bj2t({l{~ze>1<>54?*ZtFQ>{ot1?nOQZ8thy%_cah zjQ7UMG&Dh7l!hi#mdwPc(iYo6!}4>uFw^m5rb;tchc!wr{~$N<#IPdPTm>T>Si9Q% zoS>7Lp;v~~8WkR-=J=nYdanVC(RE!X9s4m_W|%+aA)Zgh>RRLlt%re^sErhOw+eG@i=mZu8nRxctZ~Abn$y5Y@YT!U zM6);sdzel6Vt}?*dcx`G72XU;;d9Ot>R2nZh0s(LK1p3}`d~U`^~LJvpt_CP4Q4_3 zpqIJ|QM;&>hpFA%%DK%QF*wAo1D4f9-NBZ;>Q16O%vMe6ZkS4q)AESAhdueIC%`nE z+Zu1{?lj=~WXig&;pAc*myPVaHz%gK6V;Q_zz`?fJ3t{kQc5}ixNSZ6m!E;#=E5-A z-o|zV;d3wjapnKUB~}sj4E0QEMu>jz;#~!z-cu<69*-U1sMyy)9tLxbnwDKOi)y%p$NI1Rp^^VI|Y z5!e-=>rt3u8{^xVFFwM35zKZbNBxc(8ors>!!Q2;dow)u1ni4(aqwhg9Xw$>>vYZp z8=QTNK?Rn7jWMGBl@CXMgH1>-;P14RVRSl|gPwyOEuQ-)>^AWnJU&>iq$A6CfRCLdCN0wbQl zSw69s0vmQq`K`}kla@>T(#|vs43Zep*hB;Sfz=%LU)UYxx$j`dl;?hM@E5=iE4!z` zmkeuo&hOxY?mJNLk8G-k8K}ICPJ6ilO@j~b61~-SmyV5EFr)>v5R9)d`PD^t#2bm0 z4i!@G(g=Juhv5m+r)65crMC8Y>lGUmjlQH0@me?yO38Al4*s0R%cYNiMC->(hDEr| za| zpy9Xkdt)5;X2C8lFD1`@uMifE)=~7tv+{6dK#%tc7r*j13BlN)Ba*D-!K!4uxf)jS+4Jld$6hlW-_JKk`TMSchF5Q}h zZQD#fpRqf$VMkJ1qE)49mD*CssTJ_$sJ7g4e1_zF76z(@!&tN$P@K!--;D}^tI|=L zwi>j7uO>n3S{P|7mRh7T_qX>3?Ko{6b*}Z$=T^h-{8fO)Fx#6}yOcUld>lKQXm#2~ zm~pfy%+h){H**BE2FoUowL_-7%t>_NSen+THJP6)^qG=&dbVStZ3?0OS{xqxs6Y1C zwg7}K>@v)H!=Tg#22Bh~v@RUIHKes`+o17ucJ`7C_&Z@oA;HgyZ0za|X#j)z%S7s-ae^0w|)5DSYe;}`(r1`~Z^NZYHO1gBKfy&uO@k?}xN z8Sm@@z(d+8X#hAC9)Dbz#TtsOqyieOs+3L83F+!f_C%y=qsi2)l_r-hRVrDr%r2Rs>0Gh+T{tRdrLHC1S zu8g)oYxOtpU+5bRYl(KTc1fD{OYK+i_{K})Coc!I%P_i7f^jZt|No@0HyPR$Y1-x5 zl~84_@e+ErNI5-aH=tdeq^4|$x;9O_M!SxnQd9VBiFQA~ zgx&Ro^Y4gvZPNP`EDR0jH*T<2J`&P?t36E6G0?9-^+&_nnM7TtE~gj2@1tpthy72| zu3>*w4iC-TNcxV*6xKDK$VONLfN8gZX))WuE$ar*xBi?4`aEUYwWWhnKzkZqg3^J; zr~M7O2wO*Vu=BKu_IEzz`~zMF^NAD|nzcOlPkpV^LDxF};#1CxY+((HK<(e~KAJPW ztS?UJ`8%+fc$Krh2CtAg!yE7to9Et2u<~`xJDl}hc(cqI-iJ5ZJoh2Ii{`nH;e9vH zeJbGfLi^9T_Furud0xM-;PpFa{YET=>iN|AEl^?Z`3^SxY5nVIm44u~AK^7V!vtW5 zlC83Yap0G+=#(E&gecf1hgmwHF<2lVL{aMmLY$VSb2idxIzTuz1EK?X0ey7+`I;h- z#S6&R%N68)oZKJY>9cAD1_FaP8XS&XA%O^I7_7JE4sMUYP);9~pbLQ`IDMojM`s_! z$*_83)!revM{_c~#;;?39T-ROd-#3upTKz7-f5sm$CJQBeh(I9A@Jq4Iyja%MgsX9 z3k#Mxrj-dhY(6nDv9+)D%9#7P!^1=oD1@D;Kv9~uhd$G8mZs1th zvk#QG&k~e55GVsH!4_ZFF1kmqcXiY5sxd19Kgcc*%ufr<3&3VwsbRG8mRKvimeKn@ z|6L0GDyc9w6bCBO0w;r%c=u$PFrtqrSkJGZhY7TcqC zVtCTuY|u$;X8xkYXeF?q`trbvY!F`!V<|m^@7SdJC$OdsL$;K#v>-@a8CXTNUrp3Q zT=iN|eQh@K2dats6eq0*(uQoLP|{1B6a`X!Hc~0+-<%W!Qd2h4DCreWiUVnLHVRPE zXPnduq_%7nq@=GoX&aC_vQdauYan+g-4dnku>ZaiR-%DGHw=X_PyB~6=xflKIMN{_o| zQ$^rXz`RLW1U8f7&+R+aD z*K__G*o+2mVFR$#;1AgyoZ)89080+>G{;Bv+c+7{a%h7bGzgsKa5j_xxw~LYfo-Q? z;BE-!;iN+lki*#yLs$>b-3wu0{O4#{sN?@vrz_+@Td4Qs`N8@ zwRf=TJMa%)zh^P3FnY7~HI{V*7i$#Vscl;u30HU?UMd7&QNi~oxGnjrBJd*726FxW z4f_2j8)Z_Jhj7xXKzc13^#KyPgiix+5-o?{d>d}Qla0cZe-tOZ52O#WQ5GeQ=A@5- z^hq|#rlfJ4^f{2e$VPoBX#yvG4Ww_fQ9nwW$VuM;>HBPWLIYAhBLzW`Ae?zIfRYM1 zNdc0YjRsOu5hn$K6v{?}C}}z;5g=t`qX;F<;G{5+va-=&N}A0{@NPBOKN}4J5;~UE zHaLiAbNJ1{aC1mD8cO+(<)q<28j+2LQT`InKZMfT^X*)aO$HpV)|E94k|QJjm> z4D(}=ctNYbXpS{f77lCuv}KwLO7ZULIS2r6`rR z&JwW}?H#Y6gU1F-(t>k?rO@WE0Lf}$Z_rKEAi?tB(b;H35Vnm%)$ltl(XMX#n<7dX zJHoFI4PC41Zmo}X)X+UqYW((wXv-=%xR728VwnFN(=vL3NDSWAbi#03-37mBwIsS# zu#k#2czaw%e=;iux6^oJ9E9b8%m}yzjigu=?~H@clD4*X_~jz{i(ByE2qOnKF)ss1 zeX2o&XhmBK=thHW;E{w;Kz)>hd`Lllq@f^6gHw01Y3wnqaI$HbF-sw$n57Uq%uX)Su z^UG3*_+=@?`?3_GeOU^zzAS}EUzS3gFH0fHm!%Nn%TkE&Whun>vJ|3wSqibeEQQEk zmO@-FOChS4r4ZB0Qi$kfDa7-#6ry=q3bDK_g-BkOLL4tkA&Qr!5W~w-h~Q-@#P6~c zqIX#evAZmV$X%8~+%8KYYL}%Dv&&M5*kvii>#`K0by*6rx-5lAU6w+eE=wUwm!%M+ z%TkEYWhunxvJ|3oSqibaEQQEimO@-EOMitfWhtDthj4Hq%|i`j|+6 zC(_@G^l_2?L8N~a=@TM-Qlx(p>7PaVlt}*~(x*lGSCRfrq|b=-?;`z&NS_tyb0U3S zr2iD@3nKlONM97`OCp66*I2#ayfv1>X=^Nnv({J&C#|s*&RJvW>mq$aq;HD!Es?%0 z(sxAqu1Mb#>H8x6K%^gv^dpgeEYeRz`l(1i6Y1w7{X(Q)iu5ayel5~(MEYNmek;=N zMEbo*;lwmnFE}raru4Klmcm(SEQOQOSPJK)u~ZSMDpF0P0g(np8WL%mNYh11M4BPe zOp*2xX;`FLBFz?QUy=3`X@8Lp5a~dX4iafZq=Q8|M5IGSI!vT+;u)(KoOi}jIPHw3 zaMl@1;iNN`!Z~Lw%@yfrk&Y4RSdoqsX`V>Oi*$lWCyI2ENGFRlU!+q+S|HLwkrs(` zsz|4abh=1qh;*h%XNj~}q_agjho<;Bh#Z7yCm8uEpjP<^0tz5i$KQiXe*+m`a1s2g zF=BCWG2{tnz-4$ITwz>}=K~i7m&0;_Zh{2H51Dumu9U+^auxvxX1oCOpk)RyT?zPt zm5>klfE)%w7)n@zt3(NA^{VCaE$Z>n94`eSHF%{EQVip}56aNS54i`|-Uc~mB?oYh zgq9lDlIf;msvC%0i;r`NoNy1WlPe|@IUCGQtD6wH5l0;&LCe_fKV8cv-0TnuTDExA zk}gjYT5e($Z>k#Um<+TsM>^yP_M}*Uq!9Qs&+N3Nd0=1u7tv_g1@U-m9ED(hyuG%0RBTLb37CnQ6g$Yy9eJX zFLoj4OjtA%-w2Cc>dTpUKmH9XHWS}Oi)FN%AxGOO6W;B>Y++!a{&YlMw@2klc&giD_;+## z`lDQ^(}DDw1rs$3@|x)mWU2?$;R*btqccvJIP4z$wATV@$D^)8yQS{2v|H+(@lSfe z&!I|E`w@blcZ{Rzm;B0T; zJEh=$-oU?+f(Lj5-z5bP@&-O21rPQHzFP_&>J5BQ3Lfqad`Jo&=?&Z?1&{IuJ}d?2 zdIR4h1&{FtzE=t!=M8+H6g=J=_dILW$1<&&a{(}@e z-y8UkQt(1=;3uTuMc%+qO2L)hz<-j0tGt2#ECny~27XEkUf~V=7b&>L8~AA{c$GJ> z?Ah<2Z;dzb-=rn4^#*=M3SQ?8{C6pMgE#O$q~ML-z|Ts-_1?hGNx_ZYz|Tv;P2Rx& zl!7;T1HT{zZ}tZMmlWLM4g8`M+~y7Zk`%nv8~EQ+aECYWf280pZ{U}u;O*YPuSmf= zy@6kqf_HlZza|Cm@dkcf3f}7t{Du^Kk~i?1Qt&C>z;8*xr+EXvEd`(M4g8K2e5N<> zyHfDk-oWok!RL4bzb^&v^9KGv3jT#R@P|_H1>V3PNx>I+1Ai<9U+fM1i4^=RZ{Sa* z;LE&$Ka+y5@CN=|3cku4_zNlc8gJk)rQqwlfxnW1ulEN2S_;0=8~7V3_$F`Q|4PBP zcmsbc1>fck{GAkhhd1!|Qt)rQfq#&K4|oIrC0$?FMUk2f%ug75JL_DR9_ zc?0{U;0L^c6)E^3Z(vmlKH?3mNx_eJ0|%tw$Gm}qQtZ_6Dfn;RzcmrQjF5f%{6qFM0#_ zlY;;44cuP}e%Tv%fE4_yH}F6y_;qjKK~nIW-oOzl_-$|C!BX(M-oQho;P<_Ohf2X8 zdIJxWfJ2kT|p3LfJPJWC25=M7ve1&{Xzo-GAW^ah?I1yA+__UFsvn11-_aZLUxQjtEC zg2)27NM8yf3*{n}6hs!uMQSOCoGKR?OhM!{xyZB>L{68BBq@lTAs3mMg2M0X z&XSAFPC;a`Tx7o#M9!9r9FT&@IdYMMQV@BxT;$*sL>?m-IWz^4bLAq3ry%lJxyX?z zh%Awd9F>B|Qn|?76hxNEMUF{9 z@)s$H+$9%zK?)*w%SB$4g2?0LA}>xsLM4l)Yc~uG` zPm+tgCIyiv%SB$7g2+?kBCk(DM!+G`Yx|QV{twxyV~m5P7;> zjub?mDHr*h6hxjS7kMBBk!Qx&*dU}QV@BLT;x3|h&)#=^1c*A?vsmrAO(@< z$wfYtg2-RUMIK2(~=Ao3Qu$j?&{d8=IHmnn$6O)m256hz)G z7x~{5MBX76`CSSk@05%DAqA1Yk&5)A6hz)77wJnu)zB?Xap%SCD_h&(748B9Us zA-Tx36h!vOMUoUm9+r#DOhM#5a*^Q_MBXbGnVo{j`{W|~r6BTtxyS)2hV=sBG6b!%8CISD$4n9^2hM#PcfSdomL=fN z?BGRGF#LeD1kBFyHXo$ESPHI|*7+-Y$(2%YjTHQi9lS&ehF=twsQs-STqOmsl7hdt zgO^IdtEJ!{?ciln@ERFdfnR{I9$UX$3Wi@Qch*_)+rcZOVE9RL30Sp*tEFK0>2nD< zU2~lcDHwiFTmsIpgV#vG@N3`_a34FkRtkn6@RoqH z?BKOha8#;xUpsi66kIPgSbsZsy%gLa1rM}?H%P&aQgFl$u9JdeQt%Kvc%u~DBn1z% zgQHS#vlKkS4z8DiH%Y-cc5s6f9G8NRvV&t%F#IgE#KT70!A(-|7O97gwS$|b;1+4g zd3Nw7DY#Wy@&r3LE(OCcP)q7O$qwEu1-DDV`F8LYDR`?CTwn*cNx|?_=n}Py?BI4O zxI+q_W(RMTg5h__B_+?WgSSb+UDBqSWe0ai!QE2uY&*D93f?YN`)E73OA6j0EqSgT zyh94!DFv61$OWrDR_?*Tww>FAO)Ww1uwRP z_e#NgrQjuY@QG6JiBcz7Y6qVr1)n4ZFSmnFmV!@~f~)P|Q>5Tiq;+0t2cIehpDG2f zwu4WTf=`ozYwh6ErQn}Q!N=LbXGp=POTp{y;4`J*Go;q8vxCo)g3pwe9JPbbmV(cc zmfTCD*uj@d!52xvyX@f0 zq~Kpl!N=RdmrKDHOTj1D!BB z&goIkJD^;oP6!A52b4?iS1zyZt6Y(Vt_hDntX$KhTz^El5$Fe$TYHo{+2vh5%3+4S zS4W#s1<6ql_9#cJMMRP_KgNpqyNw=$l9 zGCRp7^LmACkhdMa1z zzn-dGt(;7M@>Bf0AzZ-ERVr`mBcb{x9|_enStodp8%#5I0?qCcH--z7Yt0QW853^| z&q|JRbb=eh%ae2SGTeup8^ddo3$V29jp6ypIUR0yW4Jpxw->LwF}x?a0Gnc)lXKdg z?#A%2BPe->VhX2>l^_c#;GyFWZ zdZs@7t7j_jn1}y&*zo_U{=?@ugwoi|a>D`Tn@JPEK1z@BU61m;dGT~dcxqCWRRkcT zzuplZl$_OnM7g_IIiLms;qOriEEd)9#E5dAItHNw>VzIOzek;RM4eHr9#H3iF5v)I zCZhJJa{+8jhivtZ?m%&LC)$U8!)$O2RHPXltsV>YRnR$TkXoXavY!&aLAM6FLHUeY z1MGSOn-=L$iQk}nPJcRG{O&a{gy|#+#BjI-AFaZ#DF-Wn%?Q%yQ5_p=#m?uAa0!~J z&X<4}8r9I4DiSct#&6-b1vm!Pp^AkUhBJrDUDgHa zdSI@Dzo-R}d|jkc=Z6PO4KNKBOiS_((`1=9K_Qo=IGy7Cyt{~pSKyxnvc)5-8n<*H z?s?@Vw|z%lf#<>R!dHU#s90SQ4uh>W!|%=enESsBwt^>Sblm}UE9gIds8NY5bZ2;C z@>+C)W<#lF>UPUmacB6L9^a$x)k{#m?@>>&b}v7=Qy(Fz_Uabs|MY*? zsV!n8xK3?_-*fkg{tpacxD^H>HNdIrY1{zH>9A0SfkT-JEqFQBqw1^SyyU0{6B@i~(cnBNy^eb|JeeE9UJFl7 zDvY`H`2f7oiWr<6LH#^Jiu1=6}0Tc{kOtHZ1=B{ zw8%Ry&r{GMU_IKgA<-Yp)T^PCYi&DK?}RrbRhhXKOu5(hsQY`=n*n{RYT4#`$L*m6 z7Cwgiyb~Utv=}zXB`W_8TMOt7L!IGvi*ep{G~Atnhc=wW1K$f5B`wt2aPPUSMokU( zo}=Lw_NWKx1|U^|4ZE-}_@mZNF8=nv9!&6`t%AmtjfItOA zxBn$%_gUNdW49i_7P#tRXQe+5AMMfnAG?fH>hWej`Z&BIsZ2Hu-3!{^Z$)?=hCa3o z8Tv5vAPD@eVsZOV-2950<6);cJ_#2mSKYF|^NHIKcRc9xdvgUp2`@}8_i-y{@+}LK zmw#fh105Rw2!CQoHoEkuE|ZdKDfiRx$mALt!{VoGUsm^iTJDpy+(hsA%%Ruma9`3s zpSwJH@aa;Ow9n_^*~zuEw9n_^(aAX-?elrKB00CkPM^E%chhe04OCasJ3kNaPFjGd zuB3NIei(}D_PuB{kCmin!$CN{-B4qFJ^Nbb@$bUPU)ZV7SS>OwxkZf0<2z{|rZ#}5E~Afr?>1>&4BWPr&-bp~ z3KrLWWhBM~;9tdVJuccmq`-!y__BrmqNbge_ zrtX6MZVPks+66dW2ChUm1va~0vb7~v+`6fyT*YOGH>P+HNZueU=H$;jruGY1 zmmZ)TedhU9q8|sXlu*9MTXIXvQ@Ld*_f(aUlGw?W^i5KENcoPoe zgE-6ZPhW-1KmV=!C!PfFIq4g@kDw~lKVMGRqQAwiX8*LzZ3EnDk(i0`0E;x|Ogylc znRt-H3#>D7#Bty1C4;Ty+pX9itT+I*;elu$9)#||5%d%uY*-O}B(vfxx)qgg`2&e^ zNLcZ;gcXNd%B5C(1ODiG#=QH4N4U(GtPfiE&Vb(~Y9QI(8K7Kxqlmjp3ZrTCN2|b|k`hrwiM2J(4VNU>&9ZdL zb=e|NXm@%?VyoQniOI#wY?YgZ&UZmrjAb@dZg^c%nEDZ`y>q(}LutQG4*S?zfXiC& z1uJLra4wVg=Q>uyruP`M?LIXN9qqF2Q7pxec3Jd@6_R-`$Z&5j50dej4}!Z z5yHb^EF6J;z$5W+oP&?SqwofNly5Q4^?!#)8)Kq!NH!*ZrjLo~&!a3lv!u6yA?T>^ zDg0U7G0*MkgswX*^Gu%0dphHZ59c{X47$PScp@9`_KMN+WHi3F)zKH`Mjr37Rx^3d zc#D>FR?s&hAZrmg!6j77vXg};xCKJd-u<$%ZDHPU1>myeJxJ`ATi>Juq&+Ew?OZqm znE>MwyJ>NZ32wo~YzM~vmK=mPBvnY?{{G6`P!n86P5br*NcXsX0i5Q=ENxiphQdV0 zGR3-#ndG?djAOu)T^0+;tUuXhV?jwoF@R{Z{&d2od-$~b(8ZzoeLl{2>yUJTLlNc| z$$)TqzO{HjzT1~95bFQqI?uL2jlvZWwh3FyIj<{}E+f{1iX^F$xAZDFtgbNPtLSlUdrE^WZB z`i3lfxHYRi&F$TZrAJP489Pm5%rwW?Eq&CR?q)8!?6HkD(|dc=lk}YFE^kg$OWme> z^PTAq-=Pn3w0`E-igNz!cXvh zizoVr;7R`3c(VU~oUdGnrzm&h0(A*4)K10)+6TBOa0#9oJRVOAeubxpp20KHa_~%J z!JpnHTkwCaFZj`;D8ROo&V`!O-u6|Zy{jy%3c4zyD~c}?_m^7k(^Ut|@%l4$f@_(h zf6>n)#FKY|Yq^!nutzq8XCqt%4>wEEv3MD3!serz&Xv{en?$hkKoP9`K_XcBTk}}5 z+huf8*E22Ihz2$L-imX1e@lZq0q~<0a9mRVvpx>&c6;3nLx3$_IScP*k1qO~0!hF! z-fj2-`aohY4JEgi<}+90_;B*?C9U?-6f5q3wAb zEo!e$z_rQeS*9g70C-fd{ z+xI&uT$)q?tKwGwKItbI+1gw{6mO}2EKC(YgFte?R z*Ja^touJh#%(Xw)CG;*?hc%z~BpvT&B$QqYFH-1oZVEguzz7G+xnjfN5|1kTdbN}J zl&C4PF=BS2$kWBhwoWfnJ!qX8&hxmINvL;Tuj-l4p;{+XZ%#rzr$y#UEb%I^88+FX+AJZTI9S$k!OfTSg$vNwjey$vM{^Aqr)az;euXGVm^~= zy`vT2ypb#Q&wMMcNBz(cgvuU*8JM1>bXZ$7{vK@^{H=h$mGHM_{P_FTyJ`<>YkRZ} zN7TCx`JbS(b&pmrYzGOv++oKIsaFdv!*jy)6eZDaS~EOO9PHfyRw7}04%kkHZ|1ermP~wDJN;5TZQ>E_^r}fc+SyRsVg)k$iq(k9?hS~j zaI;v8XySH&=Jpi_BSCr}eHIDQ`=Llk+)tyqeZ}dKbawygNIJbwB1GKJpt*g;nUPF( z|Mo~Gz27I&N8At7+`i(hNEW+)b|j15&yHk^`+aF{Uva-kKX$)4(vRNnAL%dd51_ey z#RDS)+5LHuf%N{M$RKe)LUa3y2OrQbj12D4F1-{DzhAq&HljoVk+eugBpm4*84!sa z)~>4DkH+ptL-wOV`%(Y>D0@HZvmcTDCpY|t&dbGbB(f+EJRn88h&9J0SzDP04}nW$u04j0|;kJ*oKhBk^;Zb zaY^b|$==IaZSqwwm?hy6#`vT05#^g+FjXud!&=U_ych+Vz8B0g3FgOMFw32~ zDOkt2xA6)~ajdBnzXNJ~_pCc^b$F=BgdC?jaN&`THm;EX15TjRsa8sWAtz8j|IV10 zRyq5nlCA@jc-0#A;?L6BN``Zms5QT8;**Ke$H}(VVq`WoDOtT}u+E}2^BtwHj!Cqs za~fW6!SROa@4!j>`v!@H2RfjVHm!5^cO~KkI@@%kMA;z@pws)Jk^+Z$z|~7?IKqKT zoS|s=P=jT};8x9X0-f$2vkXrhc$5REM-&?cHc4=!bzBmsZML`>cbTy|CgC!Y+HI1U zB~J$?DJ*Vj0$$hz9b**cZ1c^MnoV*5r4G8qxx`fRy+PX~RV;8oCBEHmsV8s1A}7!} z>}-{|%rqy^X`pSA5@+bZB(2e5=}5daX7z&Ul*}5lbxfiKot>{sqTkUvE{T3SB(6EP z7tBtHekHwNcCi=h)^WS67tC&pYjE3@_k!6YvG;;rFeg|XpO;h73udpxZi{=toG8I8 z(J{%}H4B|&ne@1;FZBXEnSEKITb%=!djX!pJ{+(Dt978 zC7-goH_+)4Z>sGLbcVz=j_VC{rln8uIUHX%gb|&yUKYAUGJAFF$YdtGR8p}Wy@4*1 z=(wvl(B+cGI=(m16%x=1j@3GZ_efUtCxWLv0}u1?vdR*UfDW)a%g-Y+0>gkU(|BG| zX?P2KP|qa7#_+SIZE18jvxi)u5pxJ^w$E@ic%ShNm1!1s&?P96Mp0`JdTb9dKnGm{ z*jY#vsQi)?mpr0_Zp0_zDxm}#Vl1yCds87EGqZrxY&RM$s1 zY7e-?+Nzya&dEu=$uyEZV5v48$v{(xXrp7#f6ebX(1UK8Leb_Am>Aj|=LKk&L!>x5 z@v{-~KK-D}i6Hi9ODK+>Bq(nu>yY%Iq^SaEd{4j!7O;hDp@-O_UoO_FYbUp2St5tnbk+1pX+aCpQmhU7u3d{16;MB+68IEUEjH4nR0uvf2nIAyPS z_=z#uMc2v3IdB*!fJakoGQ8XgawBbO&*tvHv!AtyJ=K>+#bFh$b+g*fWOIHQBmE3p1{<^;^vR$_n?7kz&yhM1qPX`_Jo^X!+L_6 z#3K6%bBCj{frB2fsR!F7l=!omkxuyRa9t6Sm*9HJ;Tmx0fgWL>;QEV&i_Q&}AaL|_ zI2#68)8azCOrp`>EL>EIDO4v>)-&c+I$KfGfN{Ite|K=10uB?h{^2MQ0&*O(o^^1+ zC+H5Y=Nw!Rb>iT9-n<{dw1>|h99;jjcol6M8t!hd;|q>DLR6K5>tEr%Cfif1!e<)} zt`{vOQm#8CTrXMccz7!g=XM8FVwN08o9AQ4D_Kq#R}?;QjLM9O>5wXw^p zNC`!nRKW);_7z?6$%6-N@G{G5Vi{RxSu2(?WtPvyGQP}mSuB%G%fMawbXj7fp^|@GR;JwFSr_%0yYzV? zvLi0pIzr+B=Cm->BU%y^aX4c4U>VuqSyfj&aBPGfpwLR`f5Jw%RZ2^!p?BQcR4@o@CT(mL8i2tE$yu>F3wjAJTF|=m9TgfZBJi8x&Q@Iztk#D}*dD+u&9taWagh zht}i?TUzn8FYK$yGR^>-xW`%^Mu=Sb`4>YZS5+uM8rjJvdXBZMHN;?J9i?TEoaTH^POu$5ywp6nh?_2gMzmhRUp# zy6$m)U9i??tMq=`VwSDyH#}oD;7&1ft5N4{)xl?u_=HyW<&{%8=GY)a8DR0ZXRnZB ze%cLj7ix#|$(5tny6bQ3`ueh0e!*hMQ7IMh4o0!?*-VYT(JL5*)=gXP<|rp3p6Q-- zr{Z=WPRKdR=e#3Ep;c6y5PKiBAN_9eL6V5mdQS^7EwPTYz zO8x~fp(>%ZqmlgF8#?mdF;W~I=5H46lhAmGYU8&pkA^6>U3+Fx=*9n~PfPb9f)b(7 zN>=Po%OQ&Wowg}9=O~}^)@;v?Qys_`7(!;*rzbK}kXMvR<~YW_S3OtpOp-mQp3{X~ z)%XRYF8_2v0(I)J|^=H~4{ubMN-OmPlH^ zL&Wi$jZABVvpEUA~y+Jg=gVv3xK^fgBm;oW`Kk zp7j(R?s_92qAy4#g|xms(2EADz5Kkx`U;vysC4sLKS79O&5-%ydnZ^>fpm=UNU|oo zN@T`jZ|V7p?$J~y<(Nz4-*I^1HL1_P)9^yJ?FFl4zWENw`*DL=+53TH=G%%3Z)GHt zUzWPK(=jD1Fjqc!duf@)7TEm592=jRg6~d7*(L!Jo_5nLaLHDEmo*8aRTKOi)R5p5 zP-@GbKy3*mZS);7VRxWw^B)eRmq;r#J@y#Yj#ivf5n*Xxme6CQ!da%fdYoB#^b%_- z3st(iC6(x;^!@gavs|d$Yh@+^wG{6SF53eO{Sq7VBv+XiD)zDAy@BgRL!qpp3fau? z=nq!WLWPbM^TmN(_-@}a6x!;S)IWSX(+^5LbH3vlb5~zNc#LBoMTwSTHWKFsxFSUd z;~(@`I{!c|DN=PFC(VGcxi6S)MT$2grv5G&k4P_Ny`e+M5($1~;38XhhkoFe8M^NA z6@|wuKKhuESZs~KcvUAII1ElaEoW&k=ozHs&>MMtkKqXl^;zy1Oi(F33&voAt?!Z; z=!YZ*8|2THo{6fk{Rc5vKR5G4Ro5+TqI809KNwK%QXCa;8=p^9d{(q*F`wufy525L z;Vo-v6)WnoT?b6Dxsc2IiD0Q&#kK~7nk8jgQ!YOvcx%v;6>7BYK~Gji()QwdvSPaC zgZeOA(N0#iu3$x(?8-_>(*06nBb-T^q8ggo_CZfkehsu{(-d>q6e8bUNt&Yi;u%cR z6ldK>DIN8fl5JTUPrd8BpZag*{Zz%;u;7`I61??8UuktZF0II^s%e_5NBh~_E+?N) z59+7o^Nw}9926Ac5mWZOM)wmD6hG$@pWzb!C@6lxB|g(8j$zT4LGia;;lF#^R0V-%-+#SN-VpY00b`(O~Cp!c=bxjBk22qA-*;|k(>Fwvj6 z5d=_S3&VxF7YKcaSX|JmS*K@#~fqnow9PXM^-LXjE3!5xm2mXMB?O?l}lZ* z-xW;kZC7HK*~BGp^n(F$Lk?MX^g7FJ;>ep4Qyg{P&|TsyY~slI8$oe7ebnLmN|*T6 zpm?lHe3eZcb^dTrJkce-+9r<391V(Ba*01-6Nm4oO>v`&B(;W1e2q;UzP}apy{1ci zty5fIHkyuQF25ZwEvtBV5#fxj{T#fqH=Dl9^CQlZV1c&GA zl|$*kJYl_a5M|gF|7huEBxFuv^?QS22x(iO$r}{kkVh{eO(;%DXmACCk6Rrpo@1-wc4zjzb4 zJNDnWJ8)CEJKq$LjSMLp5Ye0>fnUN)e=!}}iRHHF5<&s%+Lm8mvVj_6dT(@-iqwGK zl=_rTRjCElrwkfSEom9GqQlghu85}8Xll!8)Gq7?Y9Ia^>JUDHI)*<mA42le)SN`17d)K}|6{j?R-Upq+yw4Z5^ z-k1jKgD6v!#5F?d_8bc}9*hG28Tl83@LBk^3(um0Elpnc^3L?Ltkx|Js zDylDyj#^2DQD>+qI*i6ex1jOSlW0QpOEfY1Gb%1ufhLvfK~u}kqiN;#(&Od6qUkX; zXl6`rniaE%X2%?$IWgbT-14b3ul!J&Uw#uUD1V+7#)i@2*k-gOb_^|zeTJ6BeniXT zVrAo7S6US}n^wo|mhENNX>ELMS{FZ*G(*#`wR}QweGGbV31bPS{FY5-!r# zM2)s3HlSUJGii6?dD?T&9@<->6O~lFkM>mxqy3e7(t%1_=}_fPbht`qI#Oi|9jiK% zUavNbj#s-#C#u(^lhr5FnHt%2w#HgISL0hcpHz`9BxTSalOChDlIGLfN!#h2qzm+J z(%!cjw9x3NU<^uOmxyA$TeSrtw`x6hU)qw}suFaXL_iNVn=dRaWA{w&U^{~~ACzsOnjzvA2m{W-7UWggZj znuj-P$|D-R!}*O5azR=Yk4me{qaRGT|ZS#0TyLP;>-3@-aeQn;{elTxozk;{6KTPSS{;6z=3~NAX^oX>XDq-cR zKXnsRMZQMUsH>O~`2uaBE@Fz~m+1&~7E=tbmZRr8i7ASUID$HgN#~xNN*%-`x{2E# z;r85tD6Wbx!Iwy3MptQqxulso#$GXFl;W526^dW@ z7v&oxCg>oG@{KiG$Q|9q91|`Aaq?4~Z!E>dMHv}JOJXyiL=lF#E~Bx|Lf|xi*w* zW4WfuwFxz)W)x}k6#v60+UO-$D8?%%e=)^W-smmvYbeE6iws}9ucEKAC|9cLt1f?) z;ijF^-q6mLxrwP3X?l0Pr~LIY<^1+6hkdBSKFnb+aM%kS_Hhn-vBfTN(oZ?!1h=yu zZs$GRE_%3K_Heu6;r6wM+cgij8y;>ydbr*6aQnsWW`udTX&!D-9&Y75+!8$8Dtfq8 z_i#(`a7(qi867CuS5bRIYDtzpR3D}n=!N z!>ozcUe-hdE^DHFmNil2%9^zz4vG zz@LDRfJ?x~z$d_;flqI7s5Bvsb0Q8Uo<%Tdd0vZEpz=J>&;31$X&u-}dnW*6aoc2I46GA@ zr{KYpaGL|`Twp$|^I$3hih*fx>j6_bFdCQwbO$o<>o}Ok15;rw1SSDP5k@XB1lA{j znZPVy2G9|=brSG%{5;91U94SzuD}8jiMYXADdI~>QN&y%s{@4laet!bzD|PhH;C54 zt9AI{6aF*tKlmo`KgAT@5NHH62GW2BfhNF1KvSR@&>VOeNC#Q~89+;*70?=J1GEL& z0qubfKu4ex&>83gbOpKrj{x0)9>AkOPoNjj8|VY{1^NN~fdRlkU=T1E$ON*0Y#;|1 z0t^LmfjrGnQ7y;x11;9vP6fhbn1jYbkfg)fWFdmo;OaLYV#lR$B3NRIz20RW- z2W9{>fmy(8U=A=Bm;zr~b^*JAJ-}X|1lR}c2Mz!Sf!BaTz+vDBa1=NOybc@(P5>u?Q^0B9jDUut35^5_ zfX9G*U>J~xHZwv@+>%=fWKK+L#Em<0C*mdOOTOX1GGFH}nQ!p-%s;|Z!uyC%@+sn1 z(bF6QWtcv&G7poF!*d;D;=@FzyKfp2c_Vb1R-e|FQkt=mN%Rv?;@6Etme`-M6Xj-{ zNP$7(jZSJ6M3ExV^++X&O65wpShk%d#2zD6N>Nzyy1fl#%Ik~SNoz!DZ8#E8Nu0Q3 zpM7w!lSJgkNO9D5kvJVOZ=}uX-jGRUK%Vyc*X@yTM3HVrHO)r?QaN$Nr5>W#8l75= z;uw`ku~!N^Jw98&7l@K$4dHb+nItZ9e4W%X9_y-XTVXtWO3`$l$E+jABT~Y6Tt^o!1GEA880EW}J)UX2RnTaJEXhd5aH5 z)ZF|!-Lz}J$LAG z^wQWcz>2vCEXKhbFZe;yz#_YkG4#IF( zJ?Fw3QOV_H<6WvdG2!pd^?%gRM=BhR5ry`D)pH?i==Mq8U$@%psn7AK>CTSYgVkM} zN7MMlo_K6AAE)NsajLMysRH9fTr3VgjCbDeiW>Kxo~-G2!X6wR_vii2E;UV^?a28( zez9+5qssKVxY^_HThnuXM@MWe>AL=a+{*mUCaToojya;z@y7gpi_x;NqQ-puSh*!p5|9rO3Zb-T*f z(@3z|eJO0N1B^#qQHZaDCLG7m%ylrbP`&E!=j))RZ#8-{h;fqQldkrLK)~&FD&u9| z6AoFvG8qVHC6cGn=yhM{PmDGNyx|j(S_RkZ$=R-jNxQMsxu;ihD#x4MP6FNL7C5xI zmel8UBbr`a)02sbHA7FQvccWOXj02&9Z-y0;0NOz;3iNm028P*k!#xg6>TXI989N^ zK?jr)@K~B0P==clP_fT2eFS_%UULFBaz?SDcEy=0{l|M>*h0Tz%sc$EU}Jf&>Ej87pAlufnI`(@yv# zdSYHfoiy07D!%J$a>w2_v0?D}{1sj<^B&}CnX|uf!mr`CF8ssbmJ2=>2mGEcrzc$SF8l#A zR+MdC9{jEnCpT8(iOiH1PvY)UHkQVl>5P`qX*pL}I-W3=(+dx18ErLzF~B^j#xSF1 z*yfJ6R&bq8Z)D~Z_v0~ufbY~s%FtI6GkR9XP9mvP+R)h90DWQ?-&iV%1IJQ}Y1{?P zt1tv`nrwh;9kX5;O`3QaFQX}wNlchbV!C7!Gb59j7n#JY$Ry@OCNU#2iTRL8%!W*2 zE@TojA(NN~nZzu}B<4USF#|G*`HxA=eoSKSV-hnTlbH9I#H`08<~$}b<1vZ(j!DdR zOk%EM5;Gl>nCF_Xv6n18 zx`llFLhz^+Tp|S53&G=7utx~qD+Eti!KFg*K6pUj^C>IXD+D(P!BbXnnGn2R2%fQm z%Z1>e5Pa4Ot`LG7g#kNf1y>5eO~R2cSix07aI+A6$qKF(f?I^NFI&MiLU5}P9Jhjf zLU5Z9ykG_I5rPj0eO|PJYlYx;A$Zvet`mYggy0n`*e?Wk3c*P$xLybj2?Lh0g7*r+ zT|)4h6&w(P!$NSz3T_aByMX&e7Ws4_!^d;xed>5!S{Ie7X0vS`0*Wx6>1nQ)G%JC zVS+dO^fugX+k#iN;MFa7V+-EeG2q*G;MBHN>AnIsQ`EfLJc?muYPZBTM5<)AN!$gn?g=J zT!_UZZEwK4v#-K?ci{2uL3-!_f?3KB(%%VL8trz?6@4rFXoQ-3j7u54a0_)h7x2&FZ$(BfwBr^ zHA)}KJt+T%b`m(??~~p*d>wNR2O7_(ykge9c0Qp3(8O2sL^T!xtpf=x&QIL#WYh1g|kzqz4Cl sBf=uxm+-9%HG1yDcPRX$$47h#Lyg`x@QDro=sk$tT;QL`Syll42NBON-v9sr literal 9408 zcma)B=|ddJb$``8Jr_L;0|*#KAPpK$0mFb0VnEUk17=4HVkNXlNCMOY4eHe#Fo%#< zT5TNLaU93-xwhBW`gRU`V{g2&41P(VK4m1s+AZVQS|PipT~Dqh792nb)UIDQ@_K3{JXOqW zq;vb2nx80=Z+a)zO5#$3vg46$DMIWC5>TAWlF#GoAlH3F1El14C#Xr3U(72jlADy`Xmc$S>L)l&I)XONr&V#vhY05# zbh)Hbe95VpyOal)e3X=Uj{A0G9*-1{d3fAWmsd#>%FF18`Oeu)UWY5Z6v^b}s_^PE zd5y~zUNz-BIpvFtSJ4-A8M4W%rNV2S^IGT__eC6(SImLD0_FAaDl1YYU(V9{V!kFB zuThszDRN$I)0nS1zMhz`DbB0lYjgP(zAl)rdXtw|qWPk{5{k*ItHLWFv3yZpJMIdv zUNc|wawT6iX1*>}@}0DYw=ti)#V7rd1WY>y{yg-21bH%u+;7fT|7c2e2Q_j zWr|E*ReZfoXAVwa*_m$1T#DRUtVbU4$nC{@HM?Q|h_2hq^QyC+)@V@fEzNUwu6yV* zQRB(E-Tvjt!s6roj!t4v?sVO4O1F>a*Uqbv4*$u=PunM*3o9pzSh*O#5+A9V`J3F0 z56{hd62wjCNwtq84Z9j-xYbazXEhR(JDI;*Tjv{l2Kf9pvuzXk8OiPAb{oy&p4{<{#$EMFL{FTd@z8ZJ_dm_&%u?eC?<(e#+69Jh>U7`59Bds1uSN>S z@ZGWW72@Udj3u|uZ|r84kF)(u@pS#exS#2|)wV^q4Yr@DpMx!D*G9_gTlrlvyY^^u z%AN)#wCfs zaQU1wb89Av*eG0gKnou1 z_V*ER;ejo)mdYPJ95k*Z<;C-7dc^)RduGJQGiZqi*ZDMD=V{=S%JEU+$zqP?$HTa$F;}VV`VE>p zI>^K2dN~iYzmU^1d73WT*v%OQwmz)E^B`Y{%@QC90&-7pLWP&XtP3Q-wyl6)3j`YH z9{ifX|TF*nZj9B$E`itGKR6TM3+d=NhF1{-_=eTHa!NY&fJ_B!9y%;?YH zlQm$67xsKRCoc*Zg(y%MAX)Kcym6kPv$^bK?Q+&ydj{k~Q^zv6emU{>Mjfe_+w=gPy>w+fu zJB+1_DzkOKSMesH;-=iqK!5LoufadiV)3vWe~bS_;0XTUAF$p3RzhSe{EHirU&n%j zKkne3B{nixKr&h?ylLceg;bcm+Ys?h_?8>|@UH~IW@g03rvFl<_yYX98-x3gJt?6h z4*2$-xAH=pw!EPebEKqg_qp;z~tKE?49bJGcx+wVmhhkE@;UV7S;N> zEZ&MNX*q+oOPzJ|df|F@<54ZArF9Gt%c+{kWb_<6bKs2$xEHg<+`9fUJe?5mpD$(# zMp|Do@&-;4%Ve?zjU8E#FuQa~WK!rjk=e}R%ej0F13_E^8{kI95>`)ZD_#WE)5^*u z)>S64sxpZMlu0a~Ok(k55=$qOSU8!)vdJVCO(wBqGKmF~Ni3I4VzFcrOC^(7D4E1E z$s`s@Cb2{^i3O5LERRfLabyxpBa>JdnZ&ZlBo;*`u_Q8y1(8WChfHEIWD-julUN9u z#4^Yv7C|Pl1Tu*QkV!0mOk(k45=$SGSooO4HzCS?%qwnleEtAiVUz@=()UR?^HEeJ z_#r;+tkVrYLS5ws@CeLdi@-dbMJo!9qLiq0U*H8e^9j@*L^pAZ5}MAufHVmF7_Ak8 zjXG=u;8A>9`JDf_WkyxVr%edHUZUr|A!CgYnx)ppt2<{ewx2)hMA-G3K z+pvP0h2UNx_=XkSA_Vsd!D%blF9aVI#+mLU7&+J}3ka3c*Dy zxJ?KS3lp|$1-A>qLqgBDt>8mKa75_&jum`Z2p$%KpR|I5Lhy(X{FD`ZLwVvVyyW;4vZi)mCt~5PU*N`!!Z@uMj*g1i#h_?h}HeLfWsh zf{zNp6GHIot>Atkcv1*{qZK?L1fLYf{AMe7PzXLH^!&6HJR}647J}bq1xJM7hlI4B zv4V$%;F!?!JFVamA$Up%ezz5TObCt(!OvR3qeAesFy{AJ!N-N*8KLJ7SixgL@CV^T z{6M389Te2?(f2(3$$j|KPr>tjpN9L``itk`^Y`H|dG~$z>o3BWUx4$~1};<^SgJN~ zi4T0`dHBb^`|!{A;T!ki-|oYI?s52EFTfSks_t+Vn-$Z>Ud3eXH=AhOEsm zRp!_C*f^`$Y*lk$R2#TaZ6IyB`!%`CnpRbFw`1B=%U%9An-sapgSp!^u~l<-yBhdT zwSgyb;CuVG=l9w6e5%^O%c~8%f)CJLs64Q4I4N$ySD7ZlWOJ)mSM%_iY6GwRf6eB2SdGP-O{`#(@cExMZ64et+~jT5=6}Y-I;tf2ou)~(>ECUdREzN0 zY7E|IVykBG1Lha;b9e&_;D%cKn(hV<-d@&Xsr5n*KY!nj7iFKt>x~zofk@Cu0{G98 z)6hiLp_$ype}+5_e)1f&l5awQ{0a_A0cev>LA!Jj4oP?5u=ExPN*{wG(w8A5y$GGs zub@i~K(`!&UimWg$$2;`KLh>p=U_m72?pi=h9O%UL~IYiux%MeYe{*-;SJK$$1Yw$hb z#6MRaC;d5gyoB$Ce!Qyu5U@)KyxLs`yw$}AeOcpOE^71`j(A56#+HTr#xx99kv=VQE4M~!~4MF0Q* diff --git a/target/scala-2.12/classes/quasar.class b/target/scala-2.12/classes/quasar.class index 3edb5d9eb81285daabc47202c97e157c1d49e610..851347e571e33074b611d37704b3be2df07d9def 100644 GIT binary patch literal 191621 zcmcd!1$Z1svL0CN?9R3o79GUINGDAp~9b1Wvk~zs{C9Q46A`1+O!_3Ug7lum| zhnbm^3tgD`au>c=)zvdQGis0L?Z)@{le@a7>hFKLt9zh(Yo7Y^uKN^48J~Nos)W~e zB-@g$hN7yHw2|}JE+^7PJPs&`uZ@ja>rmGy|_6q()2wC&pxyA-b;R<4fJ z2gHpXS4>^GZ0;UKYGrRNuZ&G}D^>(T#%&77W^ZTFt6(j}4W} zrZrcL9o0KoHld{~Ctfgj`Ltg80DX|!eMmQba8*Ik!W_N#knW{L{l>4;3o2HP-mXA1 z3Pw#Dy}LTUD5?$_IYV98GpD}i^s*5Pb8?H8G%izfDth%d2A656ncIyjO!kWErTeWZ zDC!;7Mh+<`9o1V4RhT>VR<&`p^E9)xsPE3}M&@h`m#d|<{c@s12bGnWIk{|TvTWSO zHQ}NKxru2-dTw%3$v!b{-t+=>?g~Sz8WCMETGtw?%y?PT-qW;bY5%2p6>7KSkpAl% z;?vre9kl1FrU7ssJBJ39QnZcbx^-q^9D@P29#A!YFs+DBQAtfT_L#ln?&`Xt=-RpxUE8p0)KOlRlUfnpG%3oBQZEFaTeA1+>+TcJkh>@jKy z)Z4gZaX~?;8V#j#dKT1_m4#MBhnGh8nq0R8+-=U@<5uq4t!`4c3N=>Vt+>zJea7uO zYwTXVljWs#^+U!l<@TCcP`hk$+nxvQFtl;`n7S2(n|5#PKY8WIXf&?P)W+!}D@u!! z;T@sdJDU1W(gx>l0{FsOt=Oe~3GgYLwM&nsjeVdW4(hk0+ww81%7@hT zE}J>FCDm)w?sJxn-*?u;;`NowOZQu*nQLp(^|e(LvRNg|)Pl5q_u0A2OFPOnO;yHP zQ`yW7Ee-Xx_3h=&jV<*Jsd+8!_03If#qMl*L$a;SP;y}&^S3jUJXPr~F;uMX;tgdSeqm_$tnQif}YUca&f6e}Sqfj=y%OVwftBqi|2OKMi}lA2W|bv3K7 zB(;HCK~e&LSklnOOCTwMKPbsYLiyRmH5d3gBR*t})3EV!0(lIZM{I z*RM+@+S-%tDOKrKY4z12=nAx3*_uivpq21ktYhU3&9!Ubpec;`;ey)c)>H!MCTbh& z5_Qc@E;w`|uy8A_Ox8D`D_MrEb#=*hxDe;gD61|@%$YeSQCTr}CbFUnb9F~cLux$0 zEOiy^RGIGlc{TgNrF&XtCA;7WS0`5`mNd84sft9&P0J7%*}w)2<;7ff?ut zSCZ+8L!g%{T*%TYaG-JD0-f0O+0}`%88a3pW&?wCu5upK!;dXoShg%NW9Izo+0Zyx zGHW&{msQP9ltPzU1yvQxq46S^B{4R=db$(X$`LT;oWQxLJ-xbYR$}*gl{0|4ohP&& zn8!n76BTo3%v{O|2sK_%%K39Mk;jVC`LUkkV-xP<<2=X5@#7J!mKb!KzNn&dMxt!? zba0evI9F2?EUg$16N;Tl%q^>~SPaLZs46jkVKp}1?q!QAtHC3=ua%XT&#bEAZ8Jtv z2CdpfZ>*$joTLnxbg`WvDVr!Mn*{FW1A{G zOiZt+u7YWn3b>p{^0Mlgi6s>?aCA`#?*man05i+WEtMEIqOJiKMhkRXhOGiO!In`=?3Dx0y;mibU7AkIUO&z&)+EHQo2?$%^rQobrt0Rxs<8T5Fp zgX>l$U`VS<@7>F)s$t+(&s?~0(fsPf!kIHF7S1e(5s_O_URFMPW@0Qh5^&2Gc}JUd za~9zwdI)1)M$PN2+SvuB zP=#(wpP{n4TZ*C==t#w{i z<#T5wDxv+;3N)cvOscBOs$r(0Q@5;eCKhLIH5(SCPu%J_EX9VfIt8fAFDu`Z7r1>N zPRT03Glc4`Y#KF6g?xO#>41XOZj_@l3xBpU!k?`y_veC&x!}*9dE8ru^NzO+=N)g^I7u1KJ6=7Ucf4gd?|92_9(R_d z=kczkIFENN#d*AIDe#n(0#ivT&f{GXa31ekiu1U$6z5Ky$Gv6V_C!5zdt#ZlJ+aK& zo>=B>Pb~AcCzc_<%6Vlo64mn(i>hWO=2tGN0xm{n)uOR5%i%q4mBVkWjPM&P%l)Ps z=FmsyPDey|h;bL#vpg18!3_~zD0r^gG4mG8otGeg#}p?}U@^aS$QR7axpW# z4A|nW9o(1kJV)b)U@A^5nYVBT%o^Oz8X8=WrU$N9J+Hc~5+`oxIfStDRx5N{I1_I8 zs$s;7+oUMc7Go$TWNHdi)jdY!_BO|p%|=s409@poAi9;Gk7=@@7y|?+UpxrB~|UM9kuYfE!j|>Y-p&0 zCr(580IDPJjH zo648UH+f;@TX;>FY-wrO2v5^+(px(_F#cZop%7kn{-`RUmGw<^O!-Oq1kwJjD*Zg> z_(F1FM^iPl6g+VL3?4sc-i$?+GmGKXsJAMoF4Xd?@>^8-Mfn}t5WU;!&GzB2wXH%O>OY{wXC)_)z(&D(~we?iB5cvsV}Oj#!TfG6;4J^*43%X zEGH11sN>B4KgiwGJZznOxJ`hzT-{t(o~&J+0?!}h?UybN4uixX8&L1N<@#~X^Rzse z_DL7H`5J0(*${^5*{tbk!$r$<)_25A&yf<;4 zF(?Rokh>;rZv^p5>c@w96b$3g)vB7jVHrlZjALp#%YSj z2nnRFrc4qNshO6;MX$)1{hfyW*WTlOGI?7@#B z$<;N9)v#_9Q5Sp6@u)a?5GCf|NQ|5F#;=C~v%&)b8WseI5(w}n9r`|^?(4CH1C}L- z5=(F;S7SroG5}Fx01o6bfV^b@qQn4P#$^C`%RuT)W5Gq72ACHHD0Z!3EO>>>Anh=C zNMZnP;4(;i$XKa|jD>!88KhkT4@qi(o^~0eonWlg3C2Rdx(w1?j)x>QKzF(f(mg#^ z+S6kvMU)X9n{;Q7m3H=6PiJG^>I!LRkM(pm<}CwhXOHuAHs*x^ie1lpoTsxfZy88C zdz`1UF>e`2JA0g`voUWONIQF+r?W9{8Av;O9Q0_ottP=o>;>*V!DE)OwByHlIv(?u zfwbetLDxDx1@o4HwAaUZdL8qYfwb4hd3qi5mVva_$9sAm^TGhduDw3q)9aYG45Yn2 z-qY)tw+y7cKHk&on70h1y*?hg*1%N`-ivp-+ZYd8)>0Q34}B}{Qp7d$J`Y0L4^UUq zBpyE)pY{V3B?j24kK;^CI}VBx19S{N81a@@3w!EIyUj$Y+f4Mh4d$&= zl)BACa0VJ0t$Z+Q-8?m>{RUMfggt&UG3_@fN({goM2&nfYP~!)rX6RZ)Nv+y90&8( zIZ7R8qUAW^DMs7QQ)Ak3P_--NN#Gqi+=)lD9o&|9Kva#Q#1g!s8(){kb>`N#_C!NO z8|DE?JJBSm6HNk7$;T^-bAdaejrPE#T?-8)T)<;oFt`LB(LmSf(v#9IhN1+<<6@K2 zE{3AS0Q{z#MW2@0Bid9?t!X!#Bz3b%;7bPVSxCSxg^0GR$2#qEs3)NSj^sMYw2w`a z`q-q&5yeX}?PimtZZ>I3MA^wxPujC4Nj+;acugK`sz|JC=xAG=fOl|7=n`D1c04Ad zlJGJVyPn=;aGM@!l$K<>4OQ)dO8XibNuWILFgfj2C`t^#NxEUjI9}{%dwFV2`_yEq zPfZ5Lq26swMl{@o;XM7cgQ1>;0(gweAni<(rOq@NoJ6Y!KdSc_ru_(2BsGDvgz9T+ z8zWki$29FxlcgRt8GOdTK7zK2Xl)+rv~QuFq+;-%Fk08NM6?Yaz8MIY}0OM4HRNvL?dXG+?8P?Q*eYxIO|Pl=VuwszPIjQf`w8WPE- zjS=m1PvvQcnj&?mDc~yxV)1G19FKL{r%+GA1bl^CLpwyY3q96w(CTFnCD!09J+SVU z#*Rc|eH*-(T-B7SOMr7<=7CCk*c3F9yyycz;{6Hpd_=n%rUb_TE*%3$qvBN;$}#}( zE5;kOzBNI2BG-FSK*dG@S%!jsXraJc;^x+fc8eDVbZi)qWiaS<2m>oOt5$(uH746@ zS7XC;dci=`1_N0J23}|2m790*-Ch7VY6E~Q0{}1NO;ZoM_{hy3@S=cN)CQ|sKqyrUqZpeSw*J)u! zM$2;TwsyQDbxd8b9_l9MaP3mLYnOt<7U1PDfwy_K5s7AO+N1R{1I1VQ+l{;}MIOom%1CB+HA+SAmJuQdmu)gWWad;xWAD7{P zQ@L#%9*3{UWj5eDZX1VV;ahT<4LC_p*#*8eqIdVgIh+gMq08XFfBIN(^fw65 zz7-buYhXy~eY}Vc*Ta|WGDPsDLJM(ab8BsiJ7Gj0;Kgz{AijT>VSzu{?D&3UoKoxH zf(#4J5%>**N=rnC4s|&X9<$BmPKqz`yIVx~>$gN}ay@eK zo)v1^U~=!pm;8BFM>n=6YZEJ1M)Y00tQ;j}4P`W!ES!*6jVK?VTM=O*v)Ok7Nm*?_;f zZ5+;s>j^TOF5TvEMqE;m*o+?&QFilGg)0bFZ=)XoQe5!^A zo#v(n7=j0S0Uh3j>kkq@TxGDyiQ5MF(NaV|%!7rBR{x+Z!ve1|>l*9fzGD?`iqVhu zVmMq7S0`i`;APCh;15sw30@S3Q{s|^3g73E?mf9zz@?fd@({l z%M0W1TU^K`?30uG5-wht z{IMM#ZR(pN`XkK=a?_Q!Cs#%Ex4ke9 z_dt(o-Vb?A9GF+}OdEK<8sek3I z*WqQTEUVY+Ww@ka*DLojT)`-`&)I&36Vd58mXe6uO>ub2wVb?GBHC)GVxd;|m zHYiK#!37Jqjl-?@5=htglDKB!wsH6n9+cJN^&wodu(`>72p1-DQycJga9e9Fe}@qA zK3}7b4I_6UT(02v#{D;WH-C5X-UITxyNR@*Iu!(rsFzbi3)BH_YXk=(qOo@bG={D33 z;Y8pKz4(zfZp6kP9ha9?!eg|(dEfrk@p4bmU;DdbQ8S!NJbfs2uQhUBsk1MQ$y3x8dgZ79hN5ic7B+S4ezk4d z%78gEjp=K~Lc4{^u(s*2Y?f?mXl`0XH1~jJro5No9xSwbXcpSQvoxz|uSvi)2%Z$$ zR{N0@zf{*+YT<;PM#0E(a~7Htnu`^~vTuPCBeAl%p$_KhE@j0mw2(}yM74O+FUWR7 zbvqBLi%E5fIIUHyEzMD$w%<~dijxduW7I=`>i{9@wZPzXCv2&2d|_E=@6bMY@(DQ6 z)^(|Msip+{D5So9Bm9J+7Jm6};Pn`m7Qk(&oXg$2s=}Gp5fuDNBj0s=RSL`tyhUKJ znwkcdfg%1v4eo$R!I_2W?G;>^?LyFPByd1tt?ODLE<{Q&95}3^%dn^4&hU{l7KZjN zTT$7`ZX@pX?i`N{fWLjDpD0GS$bX?2!fuA1aPonk7@qEltuSMub)ogx`Wtu)G_;8p z&|BMJLWI*7C2;zi==AYvxpiG*vTY5-!QjhcsxsBrkK8Ad9^b;NLWl)}6T2Cj9&^}R z5Yxa}37l1V`mAh7jBVGo~Lf3|_!xOxoGfvOjiCVa@!w*WWxH6JuVA4&LYooyPJT6LU*FtT3vr;}2C#LVl>w)?hn(VG@ZH8W3o+gu z?9YK4R;z7YLq8%^psvz%b9RZC2fyrp@(8hIP@@6%9QC*MGHO3lo`rQlpcrK z&xV#~YqT7u?5@m0<)=ZzQZ8=TeLPy6~#_a7J8N7UW0*7VR&GX%Egc(@GxZ$Wlx0q2X5J+kWX%)w+ZMS z_<1LsUNQb9pvB=gw25LKcEXBXlqgQEh1;HCu6RY$hA&o?74EXX@L2-U2Xvujg*75Z z__(l`DV5Y|A2DSPNuMxfE=iv;WgbaiFl9bTUom9?N#8JKAxYmcrHZ5`M}3N|K~*OsOF$pDDE@6*8rcq#jI3k<^PRD@p3ZlvO14Wy)%j`ZJ}Tr0tlpA4vn5 zvWBEVOlcsgm?@1U4PiB+X#Tfh6tDl!Hi`&6I;l+Jh;F zkW|T(LrI#;l*34x&y>SSTF8_mNUCPaktBf+9YxYorW{Sua;6+Z(q2qCmZW`{avVwf zGUa%ZYM62YNp(y)k))MOIfcB%Q~UzmaqSQ?4QD zBBoqR(j`o}j-<<&ay>~`Fy#i4u42lKB>jykH<5HLQ*I{ddZye$(v3{Hm86@Q@^_MM zWy)u9wq5DraVT{8%%keq<=8w z36kDs%9A9$%ao@``X^JKCg}sFJVVk)OnH{1Pnhx?NuM$0d6K?h$_pfY#grFG`i3bl zk@Ou?UMA@Wro2MZznJnWN&jZbYb5>5l-Ei6l__tK^gC1DB!)vFk{02Om9*gF;%{Z$T@qA!Uz2?zVc0 zmXhx&qLTL%`JI5bEkMzZqDS0))zT+0Qg(`f=8d`M56UAlVJN;pYSt-li6TeCz$IySiKxZtXyse+u=gy5(XgR4#=)e&21R}pvX|D!D0HW;#K-C)Y1eS;~B z77nH?+Blf9XystaqMf(a(HNs^Ot9WV)qwtsssa5MRRj7jss{95R1N6As2b3JQB}07 zY~G@flvcb-YSe);KgV~{7@dq%WS3=6bjz(MrsF4);ugu-u`o$bcHMP^$Rs7%tm=)N zxfOotP=j0HXGb913O|atMoL?3VO#*%nu>jsvc*nF$M7U9+2xkPb&AlQq$aywSy4SJ zW{{5T_Q}%0sBfet?WA;kP*U1a;$~Y28%hSU(-09b$MR^Rq$cZpp=JjeB~6*nIW?_2 zhpp*Zw+^z2%ZW$*!e82Kg(MGPN+e}drv>VWYr6Gwx5Ay0rVm#>G>Q*0~x+?oT zJatv}d3froEZSE(c{zN6IQu+2bw&1hcn)GD%c^*B-9jxpUfZ8I8H9^X*OuvS(vjUsxFTeen(SSl6*$`;$d0G&&&hc?+)`!fOWl@Or-N|w{*+Bil33luOxF4C z5Zey#iQ1cYooCDZ`ZEuy`K68FnbZQ3$od zzjMTt5z0s`hwTwq4x3C$;1AaAM=7JRyi=5mZyqsaN2LVIVcP@h!_R2>myeh-Mk&Q| z_zen{!>=&;_m7w|RvCxo_v8MF;puN5F=f0m0S`Px2k>X|xS;hpN6>f7O0u+H5gi&^;X z@H?h5Bn&YQx~D@!SFdhuUXPpXjPO5AWnlPSQ`rGkx)mpzU<+PHQ!(@t25QF$K-gbK z_+x;AZ4Tj2!k;?zpwGCT=szR;g&F?Rqf)bqRH!SB@Hb}oTek}ICRY)?YJ`6_RYUD(XkO8Z9iBKo>n-PJJ zn!(nKF1p@tpMh=MFio(H!9Mrt%*YKtZz_F^ZqBYi%CMox+QI@6>&7SAn-dTu4K_CM z512WM45QFAx_3Qi*kYD;0z`x#HMk2VI;wy`%2)%`WLJ?cGK{!s^zB*&Z0Cukn-zAa zj7&SG6|=kozVB9>#P8ZwCtD$u{LBrtDgK!|!`Kc^#%l68{3Be&hA|LEkKKx*lsEXG zs8M9>z>IvO02_R8Uf37{vJMgU4g61quA-g6RjJncWJCS_d{`JGVNEnmON98ZOg7fk zCFi8tlPlpwMBf|Z3l-IXZqB8H^IKD}Jq_9vep!+y z3`7}k(J4`5vN2UvhFF~dzZ{^CueLRJK-7i$rj^YlRa~sBZ%P@)P7x&vzxH)Dia6T} z+;tRw+t}4Kb~fO*;bwg!ec2E{moUU>AUR!8#Ej`ixe1hJ1fo;{>qA*Qe^wo7PNSa>;YeEHTHxl7*DGfHrh>eOx0U3lzeY-8Z+h?b4|d4Umf(a=(!aQ zV*yNSbui}Wn-Z{@*xRKxjSQ}2U0%vfRU1)k@+XE2O?;KGC9 z6aW;bV7O~&s%_|~OJOarNi^Bilxk=L8v7ba(?}RKu%}t3VHkC=kv9q3$oo4wq@%sQ zp=1VJK=JE=b;#9NX{<7hlmWX>`&iBH)iR9zV9MvAE11!M%-0x=aIv-Y@uFZD&9G;` zxV9O7+`{ksU~{l_dh@H&3GS-Gx8wYG5KLFl7UF7c_0%D7%{C5&@s}<)jKiTdAkPE3S-(oQzVpD0BN6!s z<0z&+7JeMN@fi5QKuvvnoBO_ppEfg&GmggwI{}=*>L?!Th5snVFiyhQe|5|_1))wh zPIa^^-hCOy>85c8oU-~H)pZsNb&%>gOnr^Y&V%~#x4F!?fDT;<=Y#%|T;I~#+|G=P zN$(QSqk_vw?{cQTOU-m8TwB*O<7)DTzcKX_GP$-3ZTw|~VO-BbhoQy|#*IwaD#CtQ~yne?q;Fk!~iz$!tdE2t}Zj~ z$75@Z2bd~)9qwMWWGgcsA=O8j7A69Z!A{`{G@3-Wt_^iZlv`LX3t?-FUkV= zQ-HpG@DUh%T&U>A1g2gGTm*oNK;^I}PIpaBge7(J{mL7fhFM|G+=yLYKhwRh_=@!i;|#|1pi94A_$OF@9=C zGkygpPOH&{#xQ<|8J@1Osxn1#aoWn|*}h)=Y5dnz`$QDMEZNZpKey-&qcUBkeSbcU zMYM=+8rw%gjzNK=%7}!`h=GG5&Phk2OuvOUUL?lU?Wio5sXLIA$J9G{BS#9DI*iJ? zGj%jcJ()U|q~2Y89fE1J7?C(QEJ`fW58NWsH`1S}lgMN{$bxIBJ5jcXsbwVXz|`GI z8tipSK7b-a&B!pc+>^9MU>1hbe9Df7ELO9KvhWj9{?%IiatDiyrBfZp)a7&-d;{Wb zBonLoh^cR4kx8U786E}0_d&Ntrot10@dHy6WU;fOMdx&EC^jM(l*OL0u?R2kk+NuH zx5#v+79-w@2;67vpPtv2#*vMADf|y_KZ1nR+`(=fVqx z@FQ5!`S5g!6>X*i7cuo-k}hHDLnK|s)JI9Wf~ilDbQM#dB?&G?FOhUDQ(q@xkGyH!Gp?>-k+%rzZJ4p~ z+Z|Z+E)~58YB){sviGU%1Evikf*--f4W9Z(JEr2TK9RzcZw}nQHh^8eJyyk~3E<$t ziywv*KN7`dNL6^y<}#!z%w1fDRGlbfNL6?OXzSE9HKsX9f-kZKs~GR*4-LBr6M zlmkJ-fRmI1LBoiVlmkJ-ppTRTLBnv4lmkJ-u#A)gLBrsRlmkJ-5Q>xoLBoKEltV5U z>X7G9&@f;j<&X=8BBUI0!61W_LoOI2kaEZciq z9_5e=2D0Nh6f}%cM>*tzLFOojTrfHu<&X=8c%vM0;h%rO)iCi#J z8s(4+#z3PSa>3AMJcojY0n8|eTreCN<&X!B}FHLoOH=jB>~Y1Ab8sxnRgH z${`mFxk`70;odVe~4>As387MLFbx!K5gMTregS<&XC<|FhHsZVPqFyI3to)!mtW#F z8{9q6mx9t}d19`yUX$5C>DOcc-?-myD1>YLysj*T9NCviNSyZe|CJ<*JwgvR~SXW)H9fiI1sru^KnbkL zeLfa_Hu?h7hVsjD^d-lg`gC~5U_@UrqpwC^z-xJPqPQm6>T-DZJ^5e7>hElN912g)e(FOpS5C>&~ue(s)k5Cm3b;Qs8W z=$B~vm1Dq*gGTflXcP?m51MXsQ3$NRi+*oLzm5LjFc$}n=)aiW9p#RGHR`Q~+M}Ni>{RMuPZN1-uQ2Vv~6R7qJuIO*nQorLQ_X`WX75i*6JEfh( z69dBS#5|X-#9DUz-i*NVof(DYNxTkdW(?`Vz!}8{jtMpJ_`eu54};g$H8-W0na@wn zEMQtGsde|L;a6yw*^|_IF>NBL^9nicOUTQ?%ga^MUJW7-k&@iUadjxZYV>;q(V3?y|@s)aF zN2cvT24i3umdeI5Z7!9KXWBeEp@~eZqB3|jFosXBCcGN>5gyUBrF39trmY}pSElVt zQknO38k2@u&a@OAp2@V;B+YVM)aq*!jj2Y%grE33uY*(!XI*dZ2@|hb$uxQ(H|IiE zSXV?I433-6hd11g%cyk#0GiB&2vEheR;qoGgC-0|{I-cpR`VGK#TpzVhz)dB)vwM08GdpN7)vp(F45+vpYj?gQnn1_3kwR=aFg5 zY&SbhbC9{tu_oZuFw70$fmnjG5A;J_J;aoP;Lq?Qc}EM^;^&&dV=-VZMuvtPFLQtM z0Mp!PZi0Ek>Y*-bhIx=_9&Esyi!Y;3p+E0vnxi2L61d{&aqha2}OEARr zVCJzjfR4ldJPr;tK?GWu^O$)enVp0OP7(*W#i?X*8Xhz4Pc!WnDtne`H&fa3OzWhw z7nw#clgyW)dpKInDhZRCRp6elny(>~*O_(~;Xqs1x8}muFyAuGw~@&MbcXLT?S9gR z+X-iU5WfDk7}mpKmx=bM`2j+I$h1dD`D1Vj>)s=+X_%jy=4Xih6rq2?v?s~nE2ce9 z=kyKJo};qwnDz>l!NmJAmHmrpZ&KO6nf3;i{mis?sq9y#(VH&wccy(vb^OURdgm2W znD!Yji)l>zl-tHaO#7P3!c6;$$|6kro+J}qDYrGRZ0Ex)#z-+2d@+{Gw4W%O&$NG$ zb|KS#rLrDO`-RGSK^v#%w)M%4Ftf$_kXD>&f09-|EW`ORHUMs(+hIu+zs%CkVtjq> zh}b}^68<{^*70EP2(CfIis5bvFN8nBg-{Ps*)XOXB#mG?BWV=A7Kh7wU2QwujXSRr zR_Qbr+c8!G{T_oyT>Ii;9W`QOnH~Xlv2n5S@PZtx%Ohxb5VcnTaU?+y75hu?EH;JC zaw^m5-Ct}cruQbpU6?M~U^k}sr?Tlx9{?8S#@Gy|7g5>nOdmvLvzb1G%Jy)0EmjJx zYs4yN8{ zZP(!hh0tXC#1e2FiS6s4gM$bT8nGIt?}9B>8>?gbbb^Fu?wBxR3@&?lFcmq< zrZK%dwjXqJY>n%=3Dp0JrQygMu|_jiA8TUzEaKF{^h%Q85^B!{e8z;EmsmT~7trB# zOs^&hmXDW^v_HHaM`u`0*#nur4@n0zJxS7`Os6%7*x^j4yPw#ROkYDsk7jx^Nyjps z?oMLIGrf)c=0v8`JxAde<=hJSw}6=@*i81Jf@f z=_aOM&YzECx4@$n++FKe(}CNVel1Cz@P;4T>ITZ*$#j~_V|O#1X7Jd(OsDt%vHO{R zH|agd^an_KnCTCb^eDc`p`CJgi7{f2GyMrV^d!@tCh2LWzd+KnOsAGh z^tb5f%S`_#Nv|^fLy}%+`e!7)$@DKtdW-4bk@ODJe34@Bj#aMsXV(D^<*>7|Cxh1`M=%v`E?d{ZXT_56 z!5DrYh)c274TN2ccYrYG!oypF<)B>-;7YU%7BN{ApT7$*{H}Y>WHIi8j5!`XC0gBh ztFSzrt-C-J5JaJ)UArpvAcUUSkh9^&usMBW2p>gYjL*&q2K)1lU~!=8IF9cMI@%cP zPxTBy6}W2Uk_z6qafE?%xCjs9GhMT|L2QI*fc$*}V(=By1RIP>umtSAkK{nZ2xvI! z4DWIu$yG*?%4k%9{dVwT18>V~TGzDj5B+hvV@RhIb>Q_ef9l0MeAvOXvbL#x3}fR- zV*+Zx`!BCXDPxmKV+v|a>8df7v7Ja`XVie@V=u-y#&#o(GSt8)M(`zgY$?G<7npa! z?fSAA=tDDEh}P}dEEw<(6@yinY!A4J3T?-|npMKqB+Sw^lg(qHVmh$E@i4r8b*ib@ zU{z3~eZ}ErxPr|VMOih2y+ewj!mR~cnipov;3WWm#|n!ZZOK;H_2u1123rH!UWE!{ zd*_FqV@7{t0NU;gwn^ML3HK?CZ$c|>tX*8(*1|)_dBDJ1@Mfn3H#STz*~8v;C`@2P z)v;8elFQ)Yxlyu{%}dEXwX9zSErIqbZ-$MF8(>_+iLN%Gh3Z*!e>%%GaFz{)N;f3d z-MWH1Yz&4wy_(xsr&`z7lhIIS@3AGEX^NH^Er) zlmkJ-$nZRef`&2QDTiDznmgr?3&w1x9CE?X>y$$-7(1PE$OWUKQx3Uch;zyz7YtcW zIpl(Y$tj0iFw8j5p`c*^ampbV{OBp=kPCjqlyb-gzd}kmkAzYVx!^}X zDTiF9SX@xh@H?Dz30AP-zb9wf*E8<7VI z^1w&rL4rIm5_ymy51d3EB*+6Rk>~ty;h6F$>7}@IEb^QmE*^_K=ZDM3BG38Z0~tyX<6hsKU`cEdCm`)mqniQ!*ylKqokMO60^v2ez?di z@|+(oGmAXuhYQUj&-vjBv&eIPxW+8~ty@mb_KKU{tmdCm_PphceZ!zE~u=lpOHTI4xDT!t2T&JWk0 zDUXs~ic8TV&-vkEw8(RQxEw9=oF6Voi#+FtOVT3G`Qf6p$a8+UEG_b!A1+LbJm-f? z(<0CL;hHq%QPN9sd0ON-KU|;|dCm`)s70Rh!$oS5=lpP)TI4xDT&Na#&JUNWMV|A+ z#cGk~{BXHiv$UxcLScOS6CJjuE3Q~ch- z`rSyXj?~~*D!q|YZ2E+s8_>Osbw@<1GtyNUx$ySpbO}8CvSf90-Cy^^5y|gST#UQ? zibVM;x5>$q#v2=UXQ5pg>i zAy47=g*=6y6Y>;(ImlD^jUZ3q7lJ&69|Q6fehSD__#q%qA&9b~=5~OrDdkY_3}q(B z(=kdiPa&`|Pa!HXq=iZ)KVFD2dwG7YNau-kzDO5{bfHMAL|QGl zT`tlUBHc@*dy8}*ktRgCuSk<3tr2OhNb5ujF?czDh``HJh`-BIh`!5Hh`q~Gh`h^F zh`Y|CBgdXh*_ z7U?M>JyoQqiS%@lo*~jRMS7M<&lc%9B0X26=ZW-ukzOFu3q^X7NG}%YB_h34q?d{G za*D?l|N2K?P^gfZ^FVY7@`k+W366wPteMF=X!NiI?qHmN=QNbMP%)SOI6o$Mkt z*CsX3kJS9&q!wmE>J%5LDw|ZbAE`ybNiE5Q)cGz_OKnoi{7AuibWoq#D-%)|xJd17 zliJ6R6#S$xD5+#7q%L%ks z#-uKBky>MuYVackJ3_Z<_g(5D)nt=u_9NA@jY(bRBDK~g)#^v8Z5xxi+(oM0Ce`6b z3VtQKO}p<37pe6&sSSRlHg025SGq{;Z<9K}j}+|r*`_UZm5bDYHmQUBNWnJdZA$8D z7pX&RQiuAHf*sXCNgbZaW#$?esUvJsNBWV1tytTX)U_^BN86;1@goJl58tMwu5*z( z&L(xdAE^_zF{$faq)xO+o#aOfHra2}mb$@3>J*#QseYtjfBZHjb)$>a={Bh|{7AvR z!EH+FCKsu*Y*J_YkveA^le*bO>Rg-Dd48nM4^HaBOy;RuU8F9uNnPwm3Zgp%?Y@ji z{oO_CQk&Feexxqn#-wg@k-EYrb)_GvtF|$z+g+rtwn_cXj}(O8*rwgr=^}NlP3k&7 zQrB-|Qg^sW-C&ct(T~(k+nCg57pa?VQn&b#x^)|qy34F1{7Avx>}~2(cezM) z+NAFABL&;UgOa){lgaZQ7pc2#Qup|gx;Hqf`?DwYfKBQ_KT;0`CzVl4-Ro+phiy`i z_>p=vIH|`oX(>0UCu~wr`jL7nIH`ONOXJ#CYE#*fsq!AU)zNlUp&ySdeMD}JP24NmIyOj^oK>J6LJn|`GJ5u8*;E%kt_rQWhhz3oQ|ejgZg z@_a9omU5H&r%md8KT;nACzVl4J?Ltw4{cH(`H@O5wr_P|`_oKX%1!Dso7Criq`uh3 zE%lJArM|RDedR~$>)@om&7`H=q`tFBeeXx=hv1|#@~MYiE%l>K>R*1OehNW|>0GTQ6nBBd!7DNXeug~9%UPM#UH)T7Rp z(sY|t$d6P`U{acqiBGvnMQl=0KT>93Qffvm^_Z)rVm2w}M=CckDJ?IPmU5HIw@DTF zktz&KDzlb)+|^RuZBjk_Nc9X%O6#3TOSwt)u}Q`KNc9a&Dzlb)!qrm!Y*PLGNDT-~ zO4~k@mU5FCXp<`PBQ+>Esp3pXed=nd!8WNOex!y5CpA0+Qi^l;;xKK5O=_ecsZqg6 z?U)HE*Y-E9#3nVyj}%0m3V4~(#$`h4Xjk`*w@FR#BLy+8f|AOprCi(Jv`IFp$$q4! z1Sd5ula_Lm+Q}xhvmdElf|J@U6H>>!y06S8HQkR?xlL+YY#mmd8_kAl*6z0=&D#AY z+d7Ov%YwSptV|lpwb4wQZ8ubfUqkH?oYbC~kaBG_(<*IJbNom_jJBXHH9r$lr@35e zflX?mAE~O~q!wjD>U0;W#WtxWex#QEPf0DaNiFvywIVpFy)$X4GhHpUk4-A!M+(CB z1@)<#Oh}#OB2{aXs`De2`k#_oX_H#zM+zeM1Z}DPGHI!^T`gtre$)JRzhOMYpro2J zA$5+6REynGYyDcPH8`pEOh}#UBGqA&TIWX!!YBo8sg2o_viEdpetWtwSY%LA8MV}T zu9mX*bZLHjx-c|lP*NGSl$+EccK03X*L{ZtCzVl4xi(pAhufr%@FR6(a8gHS;!|!? z$JnHf^&@p$a8f5^Ldv!CTeG)MX@1+MFh*%mpUUWN*tPRpJH>9PQ~g@%wBV%9$fTuQ z8)CIHZBl3Xkvcm#sdF&%`|(fi{`i01p~aO6V?#YCdYonQVuTAPcKT;47 zH)u;emak2nxi*?&&9oP7QZMwcu(2u|uBnUK2Mb&qau z;L!XwaA1Jvpe>cj1`frw`%SYqaANKeHp!8bZrXKey~aX=tl~oiU%e2 z?@U_CwO2y>k4@@lKT^L0C-qw3kPkfj2_$FI{^M`kx8^swM0TLr<0^#L17k7nXh&pJpA z(@ndfVtx(90+Z4*y76?A%C$*#^COiPn3S4HR2St%S4-LZH*~-K8yMU_X!rHVr2AfS zk?Lu;R4>1l>K&X^JQGqcyGZr5N%iw1)jv3??J^3b zNEO?p2K$j35}eeqOh~=vA~oD5HNub7$p0y+Q8ua3ex%@A7eTvkOeQV$x~rv1ZBk?X zNR10lYCCZyhRk=ny1wWlAc%HX8tWR8jb2QXYeUac)q%Rhnq&J>RY))JIfrFOO_M3k?NDb4M z+6}eLuc4L)CZ(^)#HBuRk=n~9wYMLseFBrxGTQs*CY7*B?dwM>8Jtu`d*9ro?2t;j zUq~hV+)>cMm&&C3K6Z7Vy?;aZ+rNQdUJ6Jmv+i?~s<*puKfmr<6PT3VkV#8@;%ccz zn^cn@spi0>GTV9TCS`9b(fu}+=)pIY=oxJQaP4N+?M)@R-=-4$HdjEO(ldJJ@|mmq z>`f)Q-=-4$I9O0p2W8?@pSwsMZ2Qz9em-?*a8jAX z(nac6o78cBq>c|x>cmV)edQu`l1=JlKT@XzCv{pTq`r2MI^8C9h99XjgOfTt6H?!} zNS$MoI@gcXd4Wl(nZ!>~zIBm0-zIf|AE^rilhQBFq@})dk-Eetb*Uez%Yu`-A`?>I zyGUJWle)@})YXAWW%hRQ2N$Wo*`%)VBXzA!YMVSa{OI5`RKHGeD$=hPoTSeUH`tuE z&2z)g4pPH(dryh(x2FWZCmHn8m(iY*UtFZ@Jtex|o)Y}DWk6Dyxzw*NQg-+h-7kC! zeq~dT+9odbn}gF({Z8AZ?(%b~yKPQeb1D7aOeTci9i)co_t|6be!sB?pB@d^dw&I~ z2W?Uh`H^}!IH^Z7X{kS4E%lg9>Ty3(PyA0wJ!zAA%8%63!AU)vNlX3dYN_XJQqTL5 zdf|Uc%HDjV`)$6#599`Q^o%y&{MXe|_U0SiZ}Sa)tM`9M>P@@*{^8esZv`jyP6j>& zAA?GNfn%8du1)GaKT_}oc`-ue#)e!bXQCL+a~oNKT<#c zPf7h^lls+<)NeMaZE=sMh8+zxRJV3173tP4CFx_s|6`X@Cd&SWiet7ul)X(U}n+oT5gk=ibBOQ{)ss-)OO%HF0F^4q2q3cgKA z&EzGzI@CpKklj){__b7V@RrIb$kQ+vslhg>AzLP;hK7cQiFs-!e8>*Jk!OtPH)?Ze zNBsPqmj2qEvcX0Nl~74&3>-&kIDBpozJ>?V2>9Tr#=mwK)u1>Z3i1^-R2mv9YA69k zRLvQ&IW$R*&q#sr>7%8gaR4$ogxL5gzp3zTJ^Z>}ctpR=p`EV>sVmD~q+zoR6HD0&^)@>9yyK`|dx^5Gz!+WuQOwS(mKc0IKN?EY|_+5z^d9UMAD_*DATMvj70J6c{v z*Hb%GR1pashONg>?Qr7c7CH{T@r*6nEp&Y73|?)w&&}~60#DPbHu}w534NGe< z-fUG2gU}j~Q1R`dPUu*i1)NvyyX4nf*Hs&g@0PdxeR9r$TK@jf0}?)u$Pqn!lrqUJ z$Zes=0vM-nL6jMi7P&3-M6eclGW3+7Uk<&2{gFT7w$L+=!`;>$p%+j@GW5A&_@Pj& z%Z(SEQoa}?YUst#OA^3W2=H|PeC7WM_(teW3E*1<_$~mx_5TEXFZ560y6IcCk++8) zy9G`(z%3hmFWLTXedv8L#qf_PtDz4eQ+nDIQR@t47j=Sz*h4raVSYW!_5 z<7TPx$Y91TQsdFVjMqwyOM)4)%1v5TCYFr-7c$3t4W-#LerN*;@86PAyt_Ws) zu+(_ZV8(|?jpqb2K2&NvFPQORQsV`|j1QL@R|PXZLTbDynDLQP<0Zk2kCGZM3ub(@ z)ObZO<71@8dj~T#}@mW&ijlqo1mKq-r z%=jFs@qxjN&y^Y<9L)GUsqvw~jL(-EA0Ev30;%zl!Hh4I8Xq0Z_#&zCvB8WlmKq-) z%=i+i@rl8VFO?df9L)GKsqv}7j4ziOpB~Kk3aRm#!Hlnz8lN4^_$sOKxxtLDmKvWQ z%=m9o;|qfsUn4cXIGFLZQsYa58DA$gzC4)m^-|+2gBjl-HNHBS@r_dBYl0cyBsIP+ znDNb0;~Rn*-y$`>DVXuCQsY~K8UI~s{P$qSw@Hm}4`wV|^t&zRj$p=}(wgrKW_*X# z`0ilFo2AD01~a}>YJ7h%*2xk1I)cC)_jQ=4s4y(b8-;x^Z!HnOQ8s`Kven)C-1T%hDY8(w_{GQY} z7R>mcQsdlU#_vmw^MVV$@ejRocTVcaBn%}r&&Pu zkwbo-1!P)N?0a+}C%u%y|94v>_vw$2Ths?(2)AV(C5J4?0&=t*vU?VgJIWz@W&v3uhwPmNqAjirf2V?;`P7b+!7LeoRkVRQQPLM`Pr$O&0M?kb0zlm+B&a>yxJ zK$giNr)2>-T@JZ(7Les~$X&C5oFRuS%K~zy9I`wM$lc|TGqZr4C5N1q1>|fwWJMN` z6>`Wuvw++~4ml?a$UWtd^Rj@fltV7a0&`C@z5YfNYjSo}C3`iyZRYEFjm)A$FbfNYmTUYZ4DhaB?qEFjm(A+O8=a=je#>MS5P$RV%E0&=4q^13V_ z_m@N7kOkxca>$#qfZQa9yd?|B1Lcr^&jRuwIppnGKprfIydw+9L*$TmW&wGq9P;ig zAP$YbP?Pi6smtQ_*` zEFh1QLq3}YOCkZ)!Id8!=p ztt=o#G9fV@Bs`F$3U7s?@j%mVTvIpj}SKwd0|{7)8;m&hT1$pZ3H zIpl9yKwc(?{38p<%jJ;&%>wcYDP&m90`f{Zq@D%jRdUFjEFiCzLmF8?{!I=U%>wco zIboez;3PYypWF@Dlp^WjqCsbMRs zv(rg^la!kQF97ng%3oIH+gq#>0(oPVJ7AR`-X41Eucjv^>g^xYl9sXq59pTTgS5-$K^Zh~lb9-`gXnzUXUwO3;0PU~s+03E+Eogt|)!qc! z-`mrdL;FY2{+Cz#K+yilp06C*{{iivz1jzX_AmAX<CqoPJ&pg~}7$Z83Xs5wCjXbn*c$>PTV`z0VH2e~eh-GeQ`S}2t zZxje$PgierUv`Jl!&ALl0@^(TYwrQty#i~m1nu5NpRP>$0+W7TCWnG{e`5eOMC%z! zOgU9iM*e!MQGAy%QBiI+rrmAqysW#iO97BBy2B{zG-f_v%!2Y;jml1AKF==fG!{Q# zbgvxQX)NnB_8tMVL#I*OY1DTbO}6=%{9-V-tlCL;9qF#OwMz2`b=BHPS_jx#WAk_D zs&ycA-NBv4VV%a&w&J+_!Ce)PbrL-B0psLO<22i1JU>f|=9xtE?5-B)+7=UBWQ4`} zT`exMEhfq=F70Y@g>5lOW^t8magDQ~r?_-QLtp3Ag>$~4)40h-pXzFKaR#?^wYbf; zm?pEhqpQVTw#7~^3&H9h+v2`X<3U?@XW1D%Z0kPeJlkDmZuNvy7tZ#nPUC4CeK%PT zKik#fIoqPl#YeQy3tcT9KJx?KiqrMpi_OAOWz?K7L>W=mSK!8+GHSV>U~RwC#ftn=JmNfu(T zIxW(Jb-s(tnPedbtJ5MqSQp4F#9(z=qzCIlnS~gvVBs39)h^w3;v)tt>3Rq2B3Gk} zGZ2H-X^|eRi)9vKusSW$gLR3^La-8p6)aqXb*bzO#9#$o*I->Pb1N}eN!L4ASIBx; z3|6N_da&;0;v?Ee3|6N_da&*-vk-&TX^|eR`^YTBUkEiqWXv!P+FV5Q7ygu5n&#T3ouK3B_O~ zUGHFB>uPjy24b)}Ez*OvRc0XutJ5MqSle6{f|VGoVBs39?XoivgB5gLgLR$Et;Ap@ zUGHFBFY943Se+K>!Mef4N3@R^tWJycVBILQ5QEiekshr3%PhoT1q;_;-Q?1x!TOzh zupY{rd&`5h@6=E{)M@-UH7B0aY5cO;_${8J-)sEQ8BwoRVpGHMaAzdv{s)Yf2O{vW zfp^O3yWhi{)kh+PW5f-_iI{Q2ffI>GJU9_%kK)6fU1#A$<57;&Egp5?m~qpI)8!8O z2p<%k?H#TZXfUN!0Zw4;fFcU#yr+J%B(i*8Slw42gQ3jFnh&&NzNKZdAdhV zko8FKcyEqY9PjNw>l5!IM@zTiiLy3~$KxDrNIdR9>l=rb!hzswLl}+FhQm4|!|n4u zNp`;d;{7=0$ap^oX8(A9Kg>}!=E<^t84w@9F?Wm)aA0m1-_8%S#Kt^DhPi!wdyZKe z-`;^aFh0=RlH+Zh^PTg#)xSmYB91dLUgW?T6d&ZpnPTHy;2yanIwR9MBRfsqA-)4g z+9ke&1F1M(Oh~B*j1&#pTO;MJ_aXdII5N|IB&i2Ca=st9Fn{|k-o->_!-QuuyD&fQ zd@8q?4UP}y%=U;6b}$Y`)Em>o}NQ9GKa~a%RKh!#T5s@!<|;BjV7eE@on4lJl!}^0PD@ zEHB}nEx+Vp&z@oT>?QgA9qo6f)w3hx;5={%TO1$hU^yy2O3HGeoaNH4EC)LM?@~Tb z1Yvn;eqR~O(Q&xL1eVL=qa7@FjPK}ViIbV~y_rKD3DQ8v_FLf{*8z1XoCMI=x%hfsgS(*-( z|JUAmz(-NMeS9{#+~w|a$)#t~djlH+(tDGRi1aQ}l#X^pf#@GK3HQjK9|$WheR)z z?wM=^e$dH&m~J;yzGY^r(d@3^JPl& z(z2HWcxl1QGQ5oFrF;f+JIl#;VAQi5-pk8%gt@pp&ue*kj7Gj&(f9aClhbNHv$6h?M+p7+1iIrcw!WUKP3vX>)xRl&<@yqd0;IrcwC6qWr? z^wMSjd;2bH)_Iliw#%BOs|4B0>b$z_<-;@gtNaal z_H2W`XAO7**|TZ9f#6v~-q6i6>>YIb!Tp@;@K3qQclf8)6yld9zhBJD^>dcIpKEt= z)j8LQHl z^v)j+&y@2AJaa#PY|Qh>Zqy&yCcKI4+3UQC;Mr6BDL2p5vx4rLP|hC?|J0ho$ZnGF z%H(BaH`!x^l|ehRyqh%TO=T}<@TP*7&3H3iFLRtf98pxxAEK8o=a0>Ko`0M5=U;P< zZy(_O+f3eE@UjJOq3dOi^M}Jr<@_Of>2m(ql4mcs-Qd=|wS4$|-dZ@k4R7N(T)V5R+iZGXU z+0*Vg2F^9HOS~^@($+*z-cxRTJ?|+r-i!Bg^IiF9P=5@1^WL(NEZ$o%(ueoa83Xh{ zwI%dpx4p<6`{7&@yT$v$&Nb1O_my4P$omQ|^y9cRciu_V+TNhwkLUUGvXRaFdBI43 z-v3Vh*dWfOJ$dfO9{qj{-~(hAw(CjSuI;-F(N~rLSY@&z})|gluF#A0ZeS$wxYj zxSSi%1J#z$kNtT*H|*CxH;m$=WET$dQGyGj`DopK9MSK`7(PZe@-81E7#YjQ>hzL=StyR&*7+z;S}#~H zo8tW9{T}fvj_?STn_ z$tYI@ZVlXFiVJEO)IR8Gls^TVf^mHCwBY%{i%fALnIUCEDxf?X@sOobg0P6O{WhPG+1o#buf^BQs-APRg8$Mu)ijxY|C3c@zB<2muVcxj zj%&Rt%gHoV-F>Z}&wX|Gw_ySB*VX4a?1=*6v#Z}PvnLCX-|oIY zRlt0A^?wd)Rsj8X??a0M+6VW3v?{>;aP3P;)~0~>MeWa@%v31)VlbI{nS3je(v94H ztX&}(Aa#%&H>b<74uzyoYQJdm6{bF6622--!olq6LNs9NpsADbnL^e#wSP1z3uE7M zOwKNaZ~)aoR3~Y-LfS{QpEOwub02d|+UE-KfU1M)n7k!fk3!y8wZAlp?}xtTxJK=D z9}KWM$m)*V=RWDP+HacN_fwy9?AZP8qXAb3U7hUx@3X$E{ijKPKlVMxZDN@(^yYzTwLgMZ*#u9FbYrB(i58nDMmZN-u8VGxXF}yVq0~vGzQ>y4iParrrN)aEp(j?k zFG684ir+Q5!lrp9*j*=>ILSQmy89%fczKz8KgQSDC|R0xfenH_#7asJvkuZDY`j#A zy)8Y;K9-70W~qc!Rw^lVmmZVmN~NXuq%zX)QdzHuq;g*ErSe{rrHWpgrAl5`q{`kg zQWft8QdRE}Qg!duQf=?Aq&kKGsji`fRL{^-s&5!AH85mL4Gov1Mm~|!6FzmNCw&G= zO?*~JPx+jcni~D3X2vp73*$3VOXCcwmGQ9D+W4E)#`K`n&eTGB#xzapY}zJuF?}g@ z_4Spy`92~&>)TO!&i6H`yYE4%hwp8vmpMi1ZEh;{F~21BHE)&rnJ-HHEy2ruvRoQ$`BWNeHAy3^6{L~YvC=5(5oxp^m&W*Ymd5&JN#ktZ(s)}_=_T7rX_D=> zG}*tVG{t|GG}ZsQG%cX2G%H}DG&|t9G{@dudMnT*%?+F{%?qk2%@4XNEeIYbEeuJJ z7KI#?7Ke71mV^aMOT#ux%flN>E5ffzDXgCq`A`0UwE!T2EnNU$4V{(jGa-2}7w9R>Ry%=synEf(wtuppZ+*pFa=wmx7#frZ#wf&B~? zY&!tqXSh#-&u;0KU{p*7L4u-@DV1Ix``_BXW6D%sg z!hFpPEY|-AmSC2^VglNLd4a_T)B^Jciwjr+W&leJmlf>nwj|B}Eea`G=3tO_UpQot&6@-G#v8YlnKz^X=)f9YT~BFVoDuv1FH?zC20v*9k9;H z5?EcZZb?_b>Vb7l9t~C>?78F~U=6^YP2LOE5UfY?YOqFN-BT)oJptA$B@?VMSkII( zU{8YeN$CmJ1gv+eFW6IH{ZhUMYYNskwH{bAu>Pr!fi(wvKJ_SA3$THyTfka^4M+In^6(0E7+Kf(_r1e#%JsSdlqb5W(?SK zU=uP;VBNu9%A5z*18h>}1hAf96Ei;t>jgF?^IfpsV3Ug+2kQeit;lw;zF<>Xi6Z;V z{mjoZ$@|OnaC3jW@-j_L?q(itH~;*z06EmJEh5v z=jfcsHV;F-3U5l@X&xamX9~+3cX(Wl4c-fo@RHex|#+FG&EsgFs(~*eu7N$VgOvf`QH=3ts zZZf})pIP{slbN~I)VBFX^IO^G1-ndbvyAVcUh)?6QZZGNeXupB*cO}cX(QzDl>wI>dedt||yPjp-;y5nb<+vB_a@?&f<95e!TV0MDc9-LR z&NA+D9JkBmxEJMzyyhO4U$cyR9mnk#j|*hO7>k}4asq^X(C%!jm! zlkGNyUzygvzG|yVJ~vCoUGlj(6W_5Z_7FWwN-j4`5#3yFmIq{?ELsXKHdWpcb2y|V zakD(4o5W2u^QhLZY2rD}*)Jt;o27()-Zsah1eIt$rWuG zY__Fb86_K=rGkDoHma(%_KNt>X=iIn3N}k6{S<5t*C`jFmbRC@CZ^(WT2d0PS*qwJ zUb9q_hr}_(m3(TJ8oK$^VdRYu%(~mbT*H zy(xy=f~U?qRzZcO@<~ zvvM}nOwJac#Oa*2N}ei9U)?-a*a7A@7SCB^Y?&F~!iqs}eLGF(0(Sw^VS zM%WeSi4%}KP_~4Th?8@xnlElumQh-*(WvFzi57@Ekx*+a=7yZjPswa$8Lyw&ibAFJ zV4;{ukse^JI5tr}C0izG6&Hz%ktT#vajK)@G_B%dmx@k{uQ)1d&zxpUTq-&(I@14I zW@r|dic3K7(UJAnGFz*-%sn5E;^SOL)AO{7%X4XZp`)Uf37D;L$$jAL%u+|iWtzp6 z?nx$;rX87pEvvMOt8%HhMjbsRZptgmLD93dE}r3i zgc97ts%J`;D$D!&S*l#lhU?@jYGHp-j2%&pDT$>lNA(j+xfomTGUJ?c_#@Srk_*am zLO&Oji?I!I;;EdTorW+nE^D4$QH?2iiY!<4^Ax#ww#nsz-A>Q0t0y2O zwUFheerh3?0od%a(Ktu*mTFAN24wkBKO2yXu`Mn!a~k_u?WU5z$8uXgfsc!^t+^Qc zRW+vM*|GetpJ&I#*fy6f$m!Xisxc)sj#bi6jpH%^+x2%ytG8-Q$!25q(a&b%Vr+-Y z3eZN=iZ_{#%N`}^jMc24bjHQlPM2l?{=YB!Pgi*kOG;80Ymqx8 zg>g&{C3%bW0o~*+*x@Z_v#pP0TT5uc{XiU5`PvrUEU7vtT!J2T@22AlLCN%DEv297 z#nDa2DblLl3uec}iK(=TJkmJYsEX|aZ&uMtVQLx zYtC_XFH-WdSgY#iWfA>zTu0>ngunP;#SK8|mjppo+)`ytgZF)porbX z&|BMQTb*x)&xkvn)1;E!#M)UmyNR{yE^AkuCP6 zkmO@JpRV3Cr?u=D`d9cXa@Dc?6`|^@{8hE8aP!;c{`xoea(B4Dt_|`x;?58vc(%FRyVZwk%M z00bA=^LBF=g7uh<#PmM zZ}GQujJ>WIyDX+=at_2?K36t2gU=O=&ExZQjLp=HeXH-;d_G?`Hk;2Ej4j{`L}S>z ztZ!+Su84QBoNg`T3uR05_(H+bBEHCB$+33G(gMxWcR8*_lk;(ESbZgLA>FEqJjjbsyg@ zRNcXMIIC(w_)VM$@|uua+sSvzCJykOf{9&xmu$j%NN8<0-z`@?%y$b__wYT=s#;Kq3QvCz*$vm?GODiImi#nCXVuh zf{8=?ki&%IMB=zd@-BZ@uKE#wSEzcJA9hyNTKiMHP3xTB@A3C!6DRn4f{FL}`%Z^3 zZt^EWAMg+4s;Bq|Le(Suh_kBNn#6LPJ>+rwkbfwfIL$v4OdRD$ohH=Qj`3r1)ieB< zQ1v7Jk+Z7Snxwx}j`QQPiL?B;VB!Qn;V>aa@+3bgSN)8i6sn%$r<_%_*1W`7;*8|S z{A1a~dH%6r;xs?)G@%{ie*P9NQeuFBkcz zf{C;ItkZf&aF@~iHnXp=xFjBKPNZ&Ek7qT`5FIAZZgMKDEYe2 z0f(8-`RB5k@A&6}ne+U-iy7@hFv;vbaUEv9;9tmQuJJDfGhgyA#Q-RG3vO!Bw77ph z=rHyb|4KG?i+?2;`H?Le)F zZyqTXi)a-ym3$Pj@%@P1({D{H9>(d;YzSrF2(I>-?H#Zt-iw7_>8En(GgWv(2v?e%nL% z?KSZ`D}Ks4#MdCz??tO-ynEW3VaCSi{)V*aGEb<6B1L4K$g^o4YMyMKhH|xehj};3pDZQ|@^M-ox3sXpUu%N3n6(7* zlYZ`Z!|xXIkruU;w;@laZIEq(4S6nY2W%hP&L9tIuz#|D8p?M5z5V;4TmmJ`k=j{y$Z@9_DS}sC=b~`v7ber($K)v zzzmcf0{aH`N4X|&S0LgR_*;-I2zfPw9uH~}1pk6|1|1DT-ppXX;F#cel+A;?1$RgJ zYlvS6@^prD4jC9S1m!y+dqVc3JR5Q~qPiae^JvqD#eB7bP;wa`DqFkWG0 z!|H}LKshCBZrB2pUxa-h20z37!ehc=KfFPByYP-EXNRv2UyJf`_%GqVBmZg1h?)_I zXT(bpGb84pJQZ;<;#=fFjpvW>;wbCzR=h3BDSR%6U4EKh=HDSdYOToTkr+ocPio}+ z$aRrf$deisRW#}$lr^H7MqwUAZI3zi5H{?xi8{I3qFUnQX+oN}(yd7hS zu_2FYjhLn}s2}r6%%Yg3D9^=Qi@Aw>s%f#MV#}iJ9Xm1>`AuWD#=al>A@ZyG#D&FS zKEySMYZr%p#qEtd5%;l>Z*^4stMPB(--qKrjsFb!Rzng}64Ft&Pw12IJj#^`+Y)x7 zJe6=U0sT$niJ6HHpsbeIB(WLFafve$XQ5n|xHl1bY!iP>GA5akhc!OwktD<=sbf;V zqyZ?WB+X4iT#}9@eVOzP%HNW0$r$J4ipdR=8>8%&JR});V3SuT??}eHNzgLJIQhrbeeekoqvnuBn4lUqHD&bzka1l%J(uPyHTwTNBcX zrIkQl)-N+|W&DIZtVJ`+XJTGw_Rk!bIRWLa%ww4+)O@TfI~gYnoh`!wR1J-$F_7>iqjkO72R3*lZL`IR3VhOyZE%%-8K# zVk>&T^QQWgYXCboD~NDrI4Kl*J|V_|u0OFiD{XQGl8Hg9c;$J0!3q?G+@$6~xq z@_3hFk$=%`v3bW62`Vd@WdE8AIqf8}*uUwEXp2JfzuFPP6aPQDM6NkUy0Vgl_V0yC z?WViU|iO~aFV5B(+EUM5RhWj3eZW7DpoPG|V5Jb8atyL7Kg z3Oj}7pRy09UzI~tUP+UC??zP&fphkxvj_j7P^s;yA^WG>(Lz^A$-?{3gih?1V_&V! ziv7bO%-QCLO7`75B1 z!|`AHp`G2Tu}c4ONGLSwNj*RKB7~+&J_wB%p8VpE5Ta`NBt&AE@{>>4d(J9*PmO#O zDluI7%`f51RV$x`OblCo^bND^k}}(B=flv6;mfc73A3+mJ`JH5#{BG~aGI!}k3%Vj zGr#*OgtTEk52+Z|g5awV+9wJ?XvOdr6n}*fKUqLREQYxt`HWCIa)?)BPZgk0i{UP4 zehVRQR=`3ohP@#AE`+{C0Svtu{(|biHU!;Ss{%R%;xH8CK4?QxjkPJjLm>`FLGOn! zB<%|Lkch)l82X|O&6})4As8BQcnV8@yiDfn@@=h-?CC->MCvf9-=%t{5cSKoZ;7l+ zA?uskKl%4;dxC|S3pAES>?CL3c@O{{S_ZSSlPh;R7 zhhg_|99&~jn+?CuW8oT)YD)U}|K?k!UVI*dghBZUuaB(%dqjD(71$#!sA?0m6hD*o+ahJl$|l^%qDr}P>wmI#>*L}6eWeX zXD+F+aWB>FdWvU012$sBig64|SsnB^&EYTW2%s3&H3Uz`*#`q8f7d$89%Q!UR^O`UG)GM(Xx-Cv5G z8b4aDp4jDmx#}$2nVzZlm#3aO{nXD;W_x1zw_@lX$G1Fj{M&JKkL5g1EdQriy2o>Y zC!YUvJY8d2nJx0f^q$1jJ+4bUalL18b&u^bPi*gLY~AC#!V}+n9$)tuukytBABnMh zoZt4u`5%k3YpkDTYdx|4M`P_8?`mwFC*J>fyj^47jcxG6{9lQ=YuqcaY){<(wYa;+ zzB1e7iT%GCd)N3^V_Q7&|JUR1ItG>5HqRLRCu86`4vB1sXB_^saZtyCKJxR7!(ac% zkK%W)ezZ^h%dlOZC2`Nf`ge!N`Q6S$w#PFb|M_@`Ta{-#?%lTYch?6UCu~{!JWC{B zED?2?s9%CQ;2D>EGcM}b(AAb_T=K^jrfz@2R(8m zKk|%Mz8^1j%xEk0j932N3U#)`6P_hjAeNZA%+#&%lxN%u%($szM_Z(4+zQ4Psk2p{ z_AI#qwdB-gr*4^NJmXj3#!nqX+B!YsSFpBDoh|gNX9*U_C8#b#$5z^nedZa*0y~bb zV_AWn_l#wM9!vM}{L(X?1%5nT$Fv&z+B2qwVoY7fwKBWl8P`HHuC8O7$S!%twor|& zI==K))HAjP^Q|b2VQxRdw*bHOEZtnglw0@;0@wbo!)p`!&NIe^a*Syns!xUXjB)PU zT|ro{ck>206yPRp9k=?wLvZQZ#mUN+B(&DoAjCJ8& z)^1Dtd(YA?^h;Y@-k$L;{L5Qd;Z4aEy zb_8B#JA+EHT|uMRo}g81Z_sVFFSrKVAN)Ey5WJHe48Ft;hm>INg|uPshb&_sghsQY zq1D;3(CO@>&~MoBuwv{)*cf&)>@+(SUW0uc{t7!Cex7|2@c=s$F`RuG@c}!>!`Wwi z4Evma$j(QGv9BU4vah3p*f&ud*oEk)*v06D>{9d%b~&az`!;3*yApGPeHR#@JF8*w$*&A2V>`*;((72k;c96y--U;J)%JHg6+NodA?O<2HwOSH4!6Nj-s z62D`ACbf`Q(jiGoE-85>FOs}df+S-~E6J2HM)FO0Uoxi#OP17jk~MXOFXt)epZUi@R6c29+aXpno2Pl!=>1a z$3!C+&->^{GPjROlXwg4Ls z7G$gj_7Yg2aX#1tun^-!u!&&7MrwBwSeTL8oeUOg;$Tz2B23<3Q^CSbt-z*%MVe}W zy$r@pOTeasMVqF9y#f|xItKPCSgdI)*lS=hz9C?*gTD>Z>}{}8woI@!V2{}*gRKQCV;cbW4p?d18L)L= z40IEDNl>e?PEnuuA@Iz&3(a^rwDo0;}Rr{n!jvIlv!m3s^P( z{{!0!RyCj{*fy{l0oB2_gH;cpIPUNz?udA0`?(T(;ym;qhKw9XgrRAH4i!t_7PaCpzUDC z!CD5#gPj0t6KnxH3D!EeJJ>0(cEL@-J_c(W5&(7@tV8f^uus6+hYSHb1NL-CC$LY! zI)>~AI}7$q$QrP7V4Xs4fPDtmCFBg)=U|;fJAj=B>lRuU>lA=yzb>fOQXR0CoYaS6FGVi(oy&7Jyv>>k~E!>@ryIFdCz8!TN>K7+nGD z8&3WG4y=DT_4g{+^Wh!Au7M2>qj@aYuVABi zTd?22#`4F(eg_-Fsc(OPjpx+2Kf%WF@0hQRflc72Sb|Lgdnpooj?D{fQY7{qn>X0R z$O&Kuuql!Kzo7i@YI2Q!1c9ECm6W&wLO3VWi>3ie7A z_A8qo*y~Z)uWUB3*P?y{^9P#|bpb2@?2YKYV0N&X(XGJ(!QPDC1r`K0J9-6JFxadZ zbix(__Ez-IV4+}hVyN9Puz4}mZaCQ7n5AG5U<+bi2IFA!V{U>)f-Q>q6f6pCVQg8j zXs{)*DPS>Ri(|)t#eyx1?FkkKwlwxbuz0W)v75mXz?R2hpR^@{t%}1wX-fiI8Hc%H zO9p#84s*kn0=7EtW3W`PwQ;+_(!kclCxfMft&8^u%K&>P{td89unqAez>0vakN*s; zC|Gv{5?MbWxRvK(~;w-Q-VEYosfRzQ?n|J`M z9N2-xwP5AJ_9vOaDu5kIyaiSf>|he+uB{T-;UvsmTV=3!lLmlQ0ee5GJy=z+_mVJo zZPmbzBw_B_s)K!y^bJ@Iu%k&Ig4G23Fd2K8trplvN!Y_|kAodcZVXl%>_l>TusUGJ zlZS!T1v{181*{&}$z<&9w)$YFld-qk8i0MAOzWc|*qLNnAC161NufFZ1lZXWn&XYZ zK20J2o&@_Wh5Ty*b}r>I*i&HVQ;vf*1^YbpVX$UkU#3QaH3$15^#!mNU|*+p25SlS zRq8>oR$v!W-vMh4_D$;dU~RxIrJe_#T7>CRx+Gf#kZ0sB642Uu6In~W9dYIw--Fk^O$ zt()yxCfWMqT0fXc_>VDD<`!E&#@6B`V@BH$Xc>H9?$7KjkeN{}6mJU5ECMA*8O35) zEM8#)WeG5lgfbarD#|pN9*X0=nA!FMN-MYpKi0m?&o+!PsT7Rf0Jv;=6xA=A(oE^5 z3{$45D1Oovc20*~&|%k1*R^A>JB~FkHZM^bUde5kSD067Y^B21nAd7-t->~#vow~a zu+8Qz8r!0<9p;@H+o`a<=6xF5=U{#<{939EuO7v9Z(F|(_~|J3*YWS}>c4HhnLna& z&UC?a4ZT=lUSr;1-fZ4s-U~Y&{JPs-WX$r1#Jq|buNpT=#>>Vm$@sf*pJcpg+$tHr zHm;M5KN@#PCT5Z(Q?w~YGTBXmk|~rVj3nF?A(;o`7slJh-IDRF;Rs`O4cUy6$*Ux< zk-Sdw2FVPPH%Vra%p#dhGKb_XlDQ=FNam9)AX!MVh-5Lz5|X7P%Se`!tRPuQvWjFi z$=f7rNY;|PL$Z!!J;?@=ERt-JjU<~$Hj`{2*-EmFWIM?YlAR>GNOqI#A=yi^k7Pf| z0g{6xhe+NfIZW~%$@?T9kQ^cTkmM-IF_Mo+j+2}qIZ1K~Vt9lG^ke$xX_8M!&X9ac za+c&A$!8>=lbk2{g5*n*uSmWosYX)Hc$l$L#)HgI%}|{gni%RZLvuq5W~fcC8j*}Q zyu?^}_Ouu#)=xV7%OSq$JoQht=K-vRHktqGn6uvW-Q(K3CS8}_}p-w z8NM`p#f)Jj;Up0xoFtMYiX@sOh9s6GjwGHWfh3V6i6ogMg(Q_EjU=5UgCvur2uV?r z2S^?yd5Gj;l1E62kvvLLoTLOvNs`A%N|BT%DMM10q#Q|kk_sdhNh*<4CaFSFm82R; zb&?t+HA!lbJWf)Zqz*}4l6oZdNg9weBxywQ1W99(CrO%+JVnx!q!mdslIA2WNLrG# zCTT;`mZTj?dy)<$9Z8-h=|u7jNoSHSBwb0mkvvQC97%VQ9wa?UdXe-d=|j?&q#w!i zB>hPSkPIXlL^7CU2+2^A7f6PYyht*fWCY1bl2Ih1NydBeMKYIU9?5)?1tbee7LhC_ zSwgauWEshFk`*K?Nmh}pCV3meiWzq>!%o94i18F-#f`fe`-WX$624x`yq1uxBw0(6 zMY4rtC&@mNcS(+r9EV6X=+$YGb0lAq;L3}6eMfSWC5TjqUKvPCBz`0T zBtazMB+(=ZB&j4tAW}nm^&rWkB&A5olT;z8Nm7@j5y_JzO(9YfdewrY4M}^Fr%Aey zJWJA(qz}melA#buK4Jv@b1cb3l4&Hbk<28SL$ZKmDai_m)RtbYCZQmDQxLs3k!&T| zMY5OV5XpNaMTze8{r6yif-A+eDJk%W>&lEgryV)QDJB#opf$s;5s zNlKGcAgM}HgQPY@dW>GxCuvO5jHD$=JCaT$H0!*&lk_2>2`81KR}^P2inG^9k})I` zNGQ5q(@EYSnN2buVn{QjGsClVsyt@+NHUx>9FYvC4WCE`Tw_XxnTA=+u*|TW8D67v z=pvH#RJk*~8ceTVGz@2kUWVSx@U{VGNxB9xylXft89pEbTd7_Je8^xMj<*!vK8*c8 DSDCf4 literal 202229 zcmcd!2Y4JsvYsT(?rckzWUw*VfQ+1NWH|?tEX%fx93^L9SxIYISjh?wDmKHz|RRb4Z^GqdgS+%CS)pWM|wRn>o2*YxyG_f$Xg`#ldRiZU*L zfvV)L=}vSeI!r}Xl>zmunmUusV@sP_yOJHPiRRMkWMiU!!<@E;?&hSa=&I7sVOf}5 z)7{jOEbrXVTE8&and~x^991!!o9as8&s0oRVWfK3&iX`iLREIG=0s^na%FR}zN@qb zi))%1TN7Q~9m%Pxl2f;#E7_?U4Y_JgUY)8H?5swoElBiIbF?+n)+7ql3axjJ8r6+T zRn4s`F3gFE}4Sgc0PszP;S zG;fWrZdTJH_Hb<@VGImV!9`Sv;HGEI#YP8%2PHQp%h zS6rd)JFu*{m%2c;cAvf`F@WPJ@1+|XIF222BAtZepu&D@B8X$%!16T(97i;&>N%RF zqP}via8Pua>MGAqm4hzC9gS+hzde;($gjD|cXY~&qZ_DvL8NY4c_HFR?4+6Xi`m4| zep6z)YOPV{k8MpXtX{QBRkw+%{dy0{kLp#EJBo{E_vw|>Z+6YV@@--{#a8cfZKuxo z9wn=WR;VNN0sYKfS4>&CZ0_u0wYsm?tDH@2Sy8rX@8Qwn!MZj&5iMJAK>x98m-VT| z>xDU0+t&^(?`!2OIAE9JoZ&0$7grA{U0&SPIi>%Q5zD8nY?@Y>7&6b)+J;5dq2*dj zja6M-KCi!SmQ@cKr5d}}OsSqZuOOx!R9={fl$+X~IfaF-`@}RIL_hGqP`@e0+O(PQSvr%cu6y2j~OU-h=b?K{bWN3v=|ogL{`1?=Wty zURc#QYR5v&EF3v;)C_fgaa0{VV!FC;+nlCtrusXMRL0)`nv7VQhSh`Vdcox8%+YKBJ_jMBB{8mnJ<>%LR9Xj%WI zy{gpw#Nhtxn)^-dTz2T*jjaQq9lIL?%L^u3Ih6+wRQ1UR%sh05nezrr)CQDSPi$E_ zraL+2;68KrnbKXJQ(iu5pR)aDF5G6;t~1oN#nCklrMk9$�@sJSVv#_uvV6J5FgS z&q)-v^qYD>OP_-$^xChid+){3vVt6K?1sUG3q~_7XT;#nnWg1s-OPp6jit*+cQxgf zEX}J@qjP4DTmtpBELmJwSf)meWX`sQb>-#8is-Pi=suGgmVmp>*>~*9J@XqT=2xk) ziu{u8=I%Fk|CwX<>6@r1YiJrgZYh`7tit+blREc4beAD5%SSh?C^~pXOaDnLM?|Cj zv`THPKBB6uIFY+6bbEJe|B2e5yo14iMniubJYiJ-vHMr;(X|Bd6wTaYo24z=K|dV2 z!;<{vqZ=y*H}oy99MhicbMTBg%f{_Lb3)0w>g8nzEYqwtb*cI~tBTmn(q(F4O1}53 zyya!x6`H0hW1OL^a(#PqQ+-ocMO#aIQ*&}&dskCiYiEf!ThW~8>@<};7{`L;Or@8q z^p*&#N{J)co~U1)XiS!@>}YG5*4EaXOtjXvRX4$)n`kzbB30?-<203RRAn0(yQ=K$ zIL-3cE{HWzYeMwTaT^L~A1q_-or%CrjrfyH>R|%u2L2G$%Vts@vLD zcek6$_R!{FR#WK@PZHu+l|uU=P|~rszIpYkhK>?b*-2HRA`9(Hu{5k)nFNM`@bKtZ z%QGGg_ zq6c$rcYAYk9H?39DcG$#)%o-44uD7Z)XYluzy{YQ8skgaIvP|(tpaczYwaFw;d2bQ zbE;FWVP66<;Imyx#%EswzC7E79Iir_Htt)%6Pq@xHeNn``oj1uK#&lmy3{GCsag)ki(r<>*tFVdZpBWH6l2b@s=Dk%lDl2X9yY3rQwn!Ww@#4^7@ zmLMH;k5HYYW9}jX0w74o!pfOd^X58`YRacC6g0n;NfF0kgU_2jr#wDw(F|uWuqa;> zuYwzvIT`eLtb_B`#Nn1!mA*5|Yii-ft*ut+L!TuvRR?qQVn#vtjNCT?KHcP^kN&CT~a+aUb8%97T${h6fD)t=D;Fo9`>tU zGH-4*wAN`?O~u^l@oKPtih%|+2T4tBc`b}o)O1G*M`F9>j@hs%)o`cduoMm9bP7P3 zUtX~{FYx+4G|4Hz7DDw-Hl;O6h5Y`2<^Y3ZH_A~9dE?<4$=P1cxm{jPs>l{3EIgjG z+8$3d_js#n#v<@<+n=3`?axk@`*UH{T<~Y#IPNdQamQbV2Ij=RfJ<9K>0j^pX2IF6^60!~ROAeEHjIG(Nn$MN)19LL?IICkPV?l1G(6Z!o1 z#4^7SFFXMTxjbDPHIKE`w!s#$-a5?AJ;CwVZaK74kwdK_~a6`|b3XylL zkiW1JCVaJU$J^7SD8jbyp_omRDJ(ljmZ+_oQ@Jo+T{#oFVgNhu3Y1 z=88mfa}E6BG?g#lDOlIm*45e7k!V+y)7=OHeiyob1c2J6)<$=UN3eE7douW<8@?^- z0G!H{FO{z>JsY}Ivl;!pZ`vNZxPmpzE#vJD2P^Z@_{a)y#^Ym*%v zP2fQ)yf<;T7#M7Mpwi`G(2ph7H^md{I+BTo4G|SQ*DVg$ZE>K|#o_s2p|~SG%qtC- zZE2v=rQu1!rR&xvnwuIT>aJdCxNJ)Ul`aj>oG8{^*OBaOkEmz~S5L!LTNtQx;Yo0r z3uC>Iaf{+L(gakx=w!!a9k$7K_lm=HTO6p~=mT@O13E)CJhyqPJM30ZgGZ4Ico|%e zP##H%0`N+X9r`<>!Y>DpG+cC~fs{yt8*#IB;H#a8TJ4jE%Z@yd5_zyQ$&=X^_~hZT zBM+oR9{ebpSXCEa1vh+0L|yEYhs%yUkP>Oy0{FFXP%m%&TvHH-y6a0_7GZUd4M0qA#+K*}Y?N?l?s^t4AHMcarNp<#EX=ji1bvEW5LrFV(tgo{%?+8dcd#tasG4BXS zJA16JvoY@oNIQF+ud^|43m}jKIZKc zyygf?JARz6<1z0DNIQNUbgkP{Fz*ORdwra**D>!1NPB&puh%i}2uOQ*JwoO`qK53=Nik9z_Pr1zmsoPBOxeex> zCQ99A0(b*e2=7ShB3d6`g(<&5P6=Re4o?dq?^Fn+M8NSI_%(#To1(=91SLRJX^a1Q!G z#$C6qyDOs2_vuKv(nP5%O#*+RA5{ETskX=~kC$!FLNXo0BygB~zEuLZKEUtFcymO9 zH6?dLkjGIX^{+|bL$z z&WD#I)lG^hQ+zThf14!rw@H&D%5FZHlz&Z<`qyOenqIKaC%&?|yK_|>UJECnOOEhr zK_=V6NT#Em3~sYcN=tj9OQ<^5rz+)ZC?rt@uH&}UlC$;Xayy=&A?^(jgD z)MTkoO$NuI-fc-lv@?CuDF;J72?X#M59X9JO_n;-WN;F#3H<0npJ2+5kVR4xIE&F# zU*8hZF7t_|JZiGkqb7sTnAk^PtB7`$PdepW$S0{7yeAi>>)IpQbw1&glT8M48_AnN z@S1$rYl5=TP!M(A1p+OT0r&9AK!K0}S|$S?;+25{Ap^8b1{}hKn>r4yi)fqt3gD_x z0JKa2_(UI6(ADhRM$K*Ok{$7NFh9EAuMe1oKA>g#z-7FRfC3={v`hxPWn0*s7hegl z{$R^G?y_rcjwf1S!t}Ub9q92`W3)c zp#W%^0(2x)(B9G=Z)xg;_vnqS$%Z&M{%d}1z$&!K{SV(a^FD^BKty}nrvR@y3Xqn- zDFc6F+`dg6ahfu{@7LmTPh^*A0T0Y`w7{}PTSr9u#IMHXv1M|PEdxL7&5hg9)Yu4) z){^L|UxlWDRZfrRAg5@V+sxy=Yv%TqgHr zd~MC`O-P{I^_Wi!vN+w2v;+&jyDmgC*;-&{YzJ6eFYv2!c{R$&RDqWkp{nM#M1yPK z(YN*Ma=A9X{Fdo*T)VRi=c}nvOo!D&kEQU{w`il>wecNyAwDeQIQfG&Y;?=%u#o6g z<#KYAk>LWb^~$(h8sC!3WWYfg-dU>>&EU<+H4%M?UyIA1@zuFZ3-~0Tz+*?Xz!VFbQ>@q#zR9+dE$KjiHnGE=jSH|U7__AFl15UE7?1>LIP^Dj;%enAX zyi6VV&vuTwrqS`$P4MXE%U5-HOV0Ldbh#eBsF!I3Un+7mu59b5PjV-W=(tzU?F9G= zUv!S#0r921K*u-G(5z%Y?8eOi4qB3;gZG3WoGcJ9ZUxCXn@%_I{f!{Cj zwZCYF+%NI%egT>UN2<1!E8#P}ctb=__-aQsM-$SL+HnOS2eq_E^p$>bmy;r&OdR~M zw*!Q~CyaL_)*%-7^1;(NxN;z{$h{ZW2YNXj-O`b$kFQ)A(cArsTrQ0gGF0H2ybx?}t~+-kU(KXuw#o8cC`*{{&$UASx^QHYBZ0-QZHrr%h8^ME}uWugi~+SynIjh8L^Lad1sUCIh~~ zf7IZomwY8h|J|>}6j6Qxn zE-%CN5Sbpom*F~xz$^DMT+Fa|-L&{>?C7u8h$tJm*kxZok`m3tYkZxo3(i&r=i zW3az|m#?9atbV_*;X;V0U+!zT%HioJEO2CymehmG8D1HeTk!>w^!MVpqT!Ws`4C=| z)#LXeT+tBNVJyAUpB@Hshr?j14w(>A;+6v+Jv z7d5=?b@>lol(iRJgulDxmBOxIuL74d;kt)R0r-W{fNLfO>`IJ!3}u+=mwk8MtV4B->%pa;KqH;_G<+<@_*j7QUXSgFpCP zn}Y(d>wV}@=gaS@!J^FA*Vr$nM2tAp)&=ozVAao#Du7=O;8*e$)<%K}uX;?% z`w`A&#(HA|%D``FR@YS*hi4G{Qs{){ZXTo^T0v{ChX%Wa!hz-D%s9+A94m%J;X=2L z_{z5C1{kN)%1W4VG>IHzSBsN=8*DzZi#)I%Ppl`{&1zibaE|oZesdRh;kJl7kOAYSM%0)Y$2G_Xhv0YmC=t4E1;K?isf%j5U4y(ef zV=e5RZ%o<Kme{F7P(yBT`I zjR$&SSgI$sfQ%V`Hm*hM!>?+vKy#;U0llLW21IDST>{O&iJFhUmOIwM_YbQfa0_1+ zQi)L9%0OLkb7D7x=`n}B1wlC6l|ZX1QmqmyxsJ``xFvnnF{8)03){O1 zYN&5(UD?zK-zUOr)_CJORau>C2Zcounp2U-riwC2PX%4`A%VLHKE8tg;U^||zGvzX z$5%eB;NrjbK4D_(6fMMPRfpiP5%t+nDi)@hDpP zF?iq$o49PqZy`SEY^{fH7r_b*c!PrZVFSrEyt_5@_*`r|n!)UZcT)|?24N6tHuUBKNpDJ2236-X05e`OUd66@ zjo)%9^T+YE4346>y32bBN}x~Pq&|5|uoF1W9&#Muh|_KdyDp&)n)~10@iN8C_>1u# zHV}3bz?hO6x8wEjV23ZDoj^zuJ63s&h2!|%{|$ejOJKJ{lRbE#$?!R>9g-+D(1bw7 zj8BYDv6X*?8Ju5hLvm#TR@6)2my14h7{rFyezP2afTa)&t769I#uupfAN*<1wXUtR z9s-xa1h8YRlL4prKXQtHg73DhUWfr2VZ#ngSRLDXZvBYO0(F(8%$XMA5k5tih%@6m zV;6|soQLsqm zK}aE^m@-@08&xsfBt|jHyo&NkQ7`x&8Jbsue{rxleDobJ;c-%&U|aE$4Wj~^(FeOgZZcN#qs6CjHAZjnB)Dbm}DfL86XG#N6GnkSjY8F#g z5;dDCjYL&5Wff6#nbJhme5M>g)Iz4LCaRVx%|wAETZmf9lvbjaGo_8FeVEct)P77^ zL)89E=^(0(DV;^i8_)gM-g>2Q;sI;Sf(69)bUI? zmZ%e%avV`7Gv#=qPG!moM4ir*6Nx&5DJKzi7E?|p>Kvw=LezOoIhCjjm~t9X7cu2@ zqAp>|Mxrib${9pm!IU$J`V&*mBI;_UoK4i9nQ{(M*D>W>qHbWyc|_gBl=F$Yg((*h zbsJMIBPTtrk4Q!XZI6H_iB>K>+CO4NN!xs0d>m~uH$4>9Emq8?$&l|((pls^&m z1XHde>M5pNP1G|?xrV6cnDS?$USP_#M7_k6>xg=VDc2MA8dGi{>J6scNYqQkoNLDb)vawk!LXG#xIUohn^qP}FxCZhh2 zDR&d~HB;^(>RYDVOVsyFxsRwHnQ}i-KQZM2qJCk@gGBwxl!u7=ohc7>*K*N7U-l-G$G%9J;V8qSnAi5kh2 zw}{%6DQ^=snknxPHHIng5;cw~e<5lDQ{E$L5>wtMY6??6AZj?B^B_Rg!vg@mPoyCy|~K{Nc7ars{dbG#DQ>GNy$hsv`<6NoZbkT#5q)=lg}I70oTH_mW5{>6P|T!cvjm~VVX5Qyw(ZfStklPSO z0Y8axv*1MVR^pRAcU>`EiAgr9`a`{L0beRM<`(dYkeOS+MC7Cq#OF*MWCNF5AN31=X|n~8JmM~alntGZQdc0} zEw|l?&r6&ESoy8VgVz$PY^G=<;H-43gfN2to|ieCtr+imZm57xr{^uP4U;&Nt;!WC zn0RIPjm=9^38hD@^JFx{{9#7;bor6(c7`AtpxI{bN^*0eQDruZUT^MRloJ zZGZ(`5stT5HO4b``A&fMBB$4N0{R-69S;k*9qs7Jgi_9j&oS@wPTtK9pW_U2`#4#a8d-xtGIy`H@9Pr~QU30*Xr*!6k zA5ZDb0Y9GH%=mjC;K!4nHKhNd){y>-tRejuSws3SvWE0uWDV)R$QoeRw5aAZF6=0o zi$Dl+40cWovLOv)lvCVq;*kw$4o~oq=5XO7lRqG2<32Lsuup;1iBC4q^YOW6u(C%0 za@%3oNu})B#Fdo2gmfo1*}Fa`(tEHX5dc0IllyVF zxyn+Hy3L_ZMUChEDI1m~!Q}~=tnP*2R=@%6Po+ zJzc=h_*go zyh`}aG^XsX>;Y^hEMo0R6f9!x#TA?IQHNVG-?A~48Q&P+!j=a!3VY97)h>ixR~-!i zd1&rOco}vk$u~1i< z=FXN`>}7%8 z^wuxt#HcyJgjKt^@ptSu_#R;pY`sY1^&i#;vi;26ERcmyRMlzB+|z{P0=6^pds@*T zgbW*soGmO6T5nvut1S+3m0@EOKXK1hWSY}0vogKSu*J-)5!&J{fG-wA6%cb8Yk-*GA16a}hJAnH6a8CB1UZr3Ge%4o5q zM03-DbX)8TYoaMw_L&sbiI%#C#GGVTVkMl-*VeJYG~u&>dnDpQqX-RB;7PQvgW zt>``zBg_#R?n55zLq6Q+F{B-wVJ6Hv%iQ0rhekJ0uTfKHbhpB}gl(;(!9?GfD~lA> zgw6PQba8%161Jy-O`E{b_C_VUj9YYd)I7k1k1_^3od91B&}qS)ZQT%cp{aFcTWJj^ ztD9P3glUZ^FnslO8^vyI74ABM5o(QPwwbV7)@o{@qd4(=kHKyMNptNYW_Fp~7C>4X z3Q`rIGtKqzO^E}4Gsl0LCVX^IEPQG+T-+iDN6mxGLtqHTX4S(+y9utLdNYEO145@V z^Dy&p3v|I(2YnoPUPjYA3Wl`?xaa5)6xdAc?@|GI^ZkNGNNr~H*5KOYmt5Zt_e4vw z72;}@PD^wq>Ba(_$C$@ja9+1v>*&M?ok%#G$*u%}tZ zVVdW_M&1N$Bk%9(knXOg=F;i#0L9}j8xX5`o_W4yo@-tJl{sejbD8EvFy!;l70kQ@ zkzZ_H3J+U{A0G;)c{%LaFR5>Xk6ZY>4>kuo*Qdi?`jp8t?HagSt~CE-nOB%sG39r% z-!*80YnZw{Wv^rUfkS6OymtAr8Wtxv$<`d9l^+&4fDP~+ltj{p@cPe`h>c?+$ znfU@;dJ)=#{*qXS$2u_cW#W4U_^9AD;(MKGxn!m{;n}*5nQxOfyu-A768TFSZ2U69 zG~Z{&9mw&4`61K#5HCz~4U7`Z%uneO%x@`nFdQHZC_baAV0LRz!53KYf%y-n?MRot zV#W$W0GoH=do~CF%*=1_+QsI#OdCvGFniS!9nAcZSpUVeT?xR?@Fa9>jKa2w|81GS znvXJV0&)G0*=Lxx2hT=8`LCuhSO>RH#Gq?Acnyp+gI64Z-Lh&2i&(tgNQ`NF6C0e2 zY~ek-iia{{kzQE5F#?lHJDx0WNTi6g^cLJyye$@QjPzmJB4XGM%tq?qJQxm=6e%flND<6vB??TnEu$LNtUIQMJQ}Yd9Es z6$Fidibhh&C}z&0ib|oP(M5`GHZt`wQa_gIFA*C|j-n7_%c)@^)iB8^rAnp{FU*i4 zoR`+?kQRpq}yqb9RwpV4K{t{b_W%F^s8^N|;eaV82$rGp^7zGcpUb z!#s(fvP6&i)a-?hUSg5ik-e=*Riv6Jf5kJfw8&hzSyOEEKs6&U!OEq%gsM!IJcPF} z4RM~!k%f^OOWiI~Ya>f^cP4Qf;GVLG-yu_3WN~DPWiE&;b=~|pdYF;rR%8X<{QU^@ zzD)mwj2CC>j#QRl>MlgpGxa0tr6f~_QW^BzD59E}I)*6t&c`hSr0z!9Zl;zKwT`JXh=OU0_vYgRMdTnWaxhBnOT142tOl=^ZGo4E4RzI6`oWs;6x_+K>oe!yz3+VcVOl_s>7ds&Mku@xGDKT8e)J|f! z!eQX!Jd6B^5I{GsCx&YT1KNm1t|blEG4&8)xB(|RXa_h_hDB~7`J0(~BwfB0{DfcT zBV-Id@z%hWTd?0Ke+MWdb)d6B7SQ`yT*okV4?GW9$vd!4C#G&&{nCQ~n@vbUK! zjr6_C)Jv%BJ*Lhi*$pGJ8mZ>)p^*vK>CF)0}-a*t)OudV!UzmCiQNJ?vexiP7 z>O-80!q(wkbH4!fQ4L-@p!!GYLJm`(BFbdyvqVLi`T|igroK#69#dZ3zO(SYJ({hL!$ux_oU740g)M%y^5jBQs+Y&X7Y1XgX(Y=^PLuPau)5g=)=}enK)C{KWPSh->O(SYH(<+Io#^)-2 z5X+)-(IYlS=P`9L_l@WRd<@eN7OkO+wM<<>7vZHqbd?ysqD#?JHb$2*b${+N(G{qe z4_(oHNp?S`CP{XGyvB#EXdPXvXX*iT4IV(bt7yoIHqymaOvRDjJSBPnUZmkF+DtXJ zFtv+nYy(7mK0?h|L&Er*m6zHL>7wFp7=d|lstM~z;d)06fj^M=4{}Ng_90YysH5Bl zd^i=uk3*`{hI$lfhR23o%*WFxJvXB8+}MC}r$pho!RH^;0D5XfPllRtQexvjm8v)m zMoKJA!QV)goMG!A^k)(G*>)j;KbH#e0fH)Q?DPPMUTBxv&@U#fmpG+_{4&x2zoqCo zM-$5El~nvErp+ery4rcp@h1SBG{B;NCWY5BZ65Jl5322_1kCQDH`4W+m{v>I;rEaV zulYu~j(*(YE2yd9VDN*r8RQDYU~SLQK;0PoGNgEnA!mhD9cR;!sxWWl<&dfqY#LH^ zqD@1J=NNJxNY%+U4XK9Fnsa&mKxi0snQ}mA7(AJBKxh~VnQ}mA7|NJ(Kxi0}m~ud9 z7+08bKxh~em~ud97}%F`Kxi1CmvV>&1MTu05*o(Jr5s|xXt$I@EEu|$a)<>Z&QcDs zU@Te6Ar_1YOF6`XkzFZ=STKGodHltU~SSCQwC&@g%;re1|+ZCBb@&)l?W+kjT_*~ek zhoKpp#lMd+EqFBN(|69i06vOE&c>Lv(pm+S*$cjTwhn-404^wKRr5R*@u_lZ8HHxf zR*TgN(=n@!nSJ;K(^}Ij*Xk(9{j^BQfuHl{4*Z>%wH8X(736+aq~v1hPJFg#9R#HZ z7vz3Xq?lN`OD>#2tyzad=@A9FUll14EFHpsXjsQU>9Ga5Ul%D+EFF>i9rB(Cr6(2S zepdvmW>8wnCx_N)P?rF)esm8O8U&o%oAHRpzIF0w9;Sr=NDFl`xsSX!64en3rw zSAC{+g=Jl7!Q5oEnm31|||Fq!eBd;{k($1`Fsq8wqE4WEg zAGfQ@;uN5)A*A$9W!4SWjR@o>c#+_AP3pR7-C|j{npeR^e23bOFF!D{dsi}E-^eWf zQ?fnib?YkY32f+- z5FWvK%?xK=)bpdW#d~J!X`He3SkJ%F01^IWPDXZ8OZ z>kUiU*?JRp3E;S?S#Kj;xN-KQ8wXw>^Dx{PyAoqaHng=Sne{$3?E|LO6Wd2VHased zS^Q;JkM$|jRuS9Zn6{cIc#E8mw&QV88~E(m`U0oPJr=xAZYL%<-a>RWJ~KeTwEpS! z54#-PYmM~{ihm0OPDwKy3189(vum&#v%ZIghsX-+2l$b0oyW9p(*6_E=!K5;i))PH zhA}Pply?es&+kk-m?rqPR%7|dM?xZ=@pka~P2h63wg zF?nrFxMwqjK=c;V2`>7g_>Gd9lp#V+eSbn@RV>o?5y zpesI34!DSEk5S8(z+j5cWr(-KV$1kl6t2w7}j659_i>}Ox#5($!k z1^A7zI_$Z4eLJj<*vDe9Sds)+;`Nnq>(KR%?pBOc$zn}(87Dk3crjt}X#%W~#ac*j zD_&>?*J**^*<_29?lmObfjsa`E==(V{oTZ}7FpKXEPT!p7c3iy3>A6~ z9O9YSA!xuunf5f9?QoZm+iYg+NGo=f^+UQ2=x5OJV(b{yaV*p5#f)gh~!&pA-tvdhPZF>#_r*3(~DuR3hV&W{uP7O+n(6%O#6|T?*ylC zCL}3NGj^91+l1PGCGGbx?cXGDAJbK8(*q2)#Nf(M>>;M-QW;DN=xt-{F{a0;>;dx`0M39l#i3e#yJC-xfC`TBHE>0 zrqe=B>>Yfo)V8vVZnM7-==abU-(&g^%6`c7!KD9Vrt_7%p4g{MA3?fvACh8Za??KeB&;}l_y1omh=2$g3(&Oj?dY!1^;rwj9# zekM^1n0^jXHB6`34_n0ai>Yi0(`f~VEn_;(PS^^jUqzh(ORO~KU~#5jM`a17(6@r*HPi3LvW={T>GxAv8`B@a@nR!e!}Ld}tdr@F5??pd zpQN&NOn-{_HZc7;Dm#ejFA{YK(_bU%Fs8rGe>Afr;P)0xx%Ic{!qH6s3sJ|yY7E-y z1InJjbQ;UqNld2^oSnk-FX-xNOs91jwvp+yF2l}bI<3nv_+cJ{d$W|^pV&+1GW{14 zJfG>m5p^LmG@>qM1`VC;Qn-Do>~dz%LJhl;8MIKtu3`o))Ua!qu|4r!%Zvd;UC)ex zMBT`YK}6lmjNwGx3j3M)>jri^>~Mu?vO()M3>H5}L9-1S=GfiLpuvmX%M2Q_*!`|C zgzuE~j3EzFe?G(v8rRq(%)qe-`tC7i&f&NyjMBn z3+XpFl*6v)nd~LJ6<>zQWyjh$tRcW*PJAAS+XtKny(q>RAbXX)hR|L|xz|Cjgv(@a zS?q26QC^6lv3+CayX1rLTTT2Pm2lCIHueFI)@dp}A{8II?3&K>DcSX}h;}=e7`CM* zhHzjBWBduVk$sL0`5d6SuHy@Y?oP(OqV9tJZr|2&c_`iXe(2POMCZ63*4_-tY$`wdxs12r@it?O9b&d=jS zxOoa!lZQX#^HeY#_CL<>VRzxm`qr+|EYBd09OTGJ=O|-&5#opL&d49kN@BA7HU z4>|JEImWWQ0^%q{4*bOkz63v8O7W))jJx1=)p^^Xifx%eJ2mp)=VHvoV&?U;^0tRb zlrf+CcOGnZ$GM|H&&<4?n6a2H6uW*5uUnODEiv?E zZxAhMsb5^u+0Mf{`jmmU;AE#1_y0^Poh`Nm+agn0-nhK+MM_>CJUll@cA5GiiKb=x zkQ54*fW0c(U{mpWxUZq1lPs{%WM(a=R!)Uh?pCDaBe34i6Wk?Z=Isd+xwfuV$&PhR zxaFu;g5HtK6zpP_SDrV`%G)ci0(#mxp@&u~^YA4axX}!Ju@Aq<>BT+}8lILxIUqDV z`+{<~tbiw2P!0$U ms5E`B`K{+5aJWGOdKxlXZ1m%Fx@SF$A0iofk4Lpa0hUYO* z4zb`#3zS1Fc%A~~5DOlQKsm&MXB8URKwjWO3i1LUQjiz;kb=Cx zhZN)mKBV+ATwh9Uz=ss%1wN!8FYqCym*G+@ z;X?}Y0v}S47x<8ZyugPP|A7x<8ZyugPPj{188RFnry%d(<5cgG23QxRFSwHQoffP`Pjqizw!e>ZzVk{p z5F1Rd{Cl9`6~In3zj0 z#V_G-(h6U3&FyZfOLo{LMb&NfiRQ&{`~h;Cyvvt8o6p41y2}QkXpvFX1YcpWM zub1G(8ZQC(O0l9T2K?nJ5#?R0^iF0|7cJFT_TMRvN_PM6r}QafE{r_1ehg`MtW zr~BIJes&tS)BWuEU*I zgqEQL zMms&jPS3Q{v+VS2J3Yrv&$ZL@?DTv)y}(W{w9||1^kO@`#7-}@)64Aiayz}kPOr4n zKiMh7tmf^x+D;)}HP1t|YMw%@YMw%*YMw%zYM$O;r#IT^O?G;-o!(-nx7z7#c6z&= z-eISA+G&rS-esqo?DTFsy~j@PwbT3T^nN>iz)l~u(}(QzVLN@qP9L??$LthhPV@FW zVW$vpn&%b5Y{LS@Ql zY9B?(pAB@5s(hvtz=y{D1g3*+OrzwOdaFBR0_qSKsG(|q8`MB`fDLMt3>2(x*@oI8 zsGTzbb*Kkau>dtN2ox-|g#|Sz6HteFKn)h4h6I6vPqxB>8lDNL!#$uz2v8$~K*1~Z zu%Jpa0d<52)Mx>!EC>{Ql@S)yxJ*DD=>auffSM2lYGQa$lQRKzln2xl0cvUxDEMG6 ztfltI1k|w}PQoP?eFdoffi zb(ROzK?2mlL7)x^59+W?K%MOYb+`a^L=dPW!-G0H6Hw=PKpi7M9UBDdxbUD($OP2+ z9#AI=P$va}f?Y>peJUeR7kEIOB0!xQ1nRV{4C+D;sM7_gjX|Jbd-_(j)I}apX9`ef z1%WzyD}%b&1L_f9hu=WS(Bmv}&(FF;)o1PX#7Y}M|&)C1}w0qWu)P?v0FP?vc? zT`E9b76b}56K+*YUG4#Og#dMB5GdH!xK%-2;Q@7(0CjZ`sB5+|s4G37{wzRU8wBdQ z@Sv{GInh`Uk+_mP}h1uZ4#jF4gz)0Rt9yQ2h_a+)O|sqU~lwRwbb<+TO^>`-Z)J+~xPY6&?27!VoLSefvBTzScKs_x$Jre}# z*{uxf77wWB1gPhOK)tY)LEY*B^`ZdvQV=Kz^R!jF?=}ypR|Ke6gFwOO4OMa54?I2L^Y-Lb)dO*D^K>Z~M)O%YQRF4PL`vTMlL7+Yi59;Gg z2G30%P@f1;p9Xi!MDmGL1kvC zhdq`Oo4T~1OM1Wcv1Zr7$P%AP3rMUN_57qV&p!N*{wO@Ep`)2~mv!Pi_2vBuF zpz6beN@fDev!PjADL^#_fr9XcA)kF(MwaqyXx5qpr~`sPtqu>WB@;_|LA44{Z9$;g z!-ML`1k^E}yRTD#>IwqYEkJFJk3kgo*5M(Vv-_=Bb9TSUJ_fG6Ch;I;hSQOj?4tq$sU(FN`N{#2-Gp*K^>O~D9?Uo z?RWv|gdk8S{!c-jBtV@U1nQLVpiaxgQl9x!h*_Vr;_3YCALp#LEEP=BydR%Cj9^6Wgb>pzTu_csVSnyEAcgFQ|Kjqu(3k z=n(!nET{)E0p-~vuRSP0Jro4$;qag`nhl@pnYuh8Ks_1+>ap;kp2);fo=w);lLFLJ zL7<)v59--WKzTMVYGPB67PKh{V?KxVsh2VV<=MQby(}#CN|2>q4G-$|Oh9=yFKTZH zP;Ul-dMiArcQOIx*}SNUtu9*7Ru>GG9k%;E$OM#UpP=@ku+&FEmijn6s82Hib)#oU z_^SZ*w;)guY&NW=KF;Lw9Ma9|Yuu%K8bmhx;~)bpI~)ANJ6 zuUB|bg_(fzY+lrh1gPFYptcDQs!t}M?sAXldS3x*yC6{EW6kK9#F|k&J1TV%Yeo-> zHG?N9g!QRRV$CR?eS*4(HKPZ`n!!UILW0sVdcEk`lBbu5?i&=;eQ{&wA#|cp5gFr!OeH+wPSp|8*HB1fBC)${b^+`4+*(wO0OA^vh`qWHZ>PZ)af zYE}@as_>xp&IHu+9#GW+)SMttbHjt0p9!cJJfIc`Pz!@V!Px*|@4iKufO^pbYOw&d zBnZ^f@Sv7w0_r6Xs1*X#K0%=N{hxx`Pk@RCf!aSjsJcun^|HrO^#W8w5U6B$P>q>@ zdc^~3l>pTg1nPkBpqeuQ^{NL{ivZOc1gb4Os5O~@dd&l>LxAcG0@W2B)Y?oyz3u_E zPJmh;1ZqQgPzPlK>P-)*g9WHVfIebq$RJQh{ZBz1EkGR;1Paaw z+nN*4w_S!Bq912tD%Ov;F-a$$CkRYi`nXTaX#34OE>J^t5xqzcie7|griFbTpOT47 zz3%~as_4Dbf_m@t(4aEg`{o6;QGhxl2-KP3L1nb}%?s)*0qX1^Q0IgOrJtKg_kG~$ zKCyp858A(h=j(;^sm!|13+h5)sf&Uvb#Z7=`X!lI>O+sEM4%u&C{PfdIvCbc8SOmv zf)blb^q@^8cmQHZP(O<=G(*QOqe0`9S@yAW)magSsaZP@Wy~`n>|weLhpq>m5>gh~C{oMoV83F3qAW(1+ zYRJ1!%_P!{^0^1p^8(ZhL7-j?4N8AG6H9&J0riRi^=c5P*TRE(BNI^n@PK+#fO;zk z)Z3v!sTsXp{L%yJ9RcdyAW(2huI*D><%RWEE=)u8_iRkX`ujE}>F)+OsyC#cXZE|{ zTNkLIy4X{q2kj}rQ-ec-(lgpq@|_2i*i)hh?J2|sn3I4>I(sC ztGLt;E=)soCwfY;?nFWe+DS9T+QgOPr`sIHL>fZv?uR)-G3lHi)nLK2Ea$Cw!98iWD01D3@ z58Hiz04TBf#t7PcgU6tU1Z8Bj`Q~SjrNrhNBWUvtp2+?`1SO)U7(vlf@NoFBpfZV` zqWt2ql!%^U1VvB5bL#(xphWZ(BPe=`5k7i~kxBFv<=-AlZ71%&enEHN_Teq{2Y}i^ zfa)IvYCw2UJ7qFX{pzvQ&H_|%5U7FwQ&77IP$fa2289PTBoj;h=CRaJ0cuzfsNw%p zP$GJY5fnYeNJUTC8go2VaT#ie;p|c>Hk@5bvN@jdU+hxKWVu1rT%d*;VwaK;v`fkO zFLo(q^0lw3dq9a@N=DEwB_p*D{retKYO-ar1 zfD+r3jG%2wM)++?#$FkW2x_heRJj-trUi`%72!vOKLC_CJIn|=JIn}wc9@aT*Zv(=hmo6%{qaCk zEp>jW(jl}1i;*zu;5t$(-~d%P-xR2Q;0S4rpI;i)ptt}E3KZ3-HyZ33N`VnsbB1p+ zn&kQ!F_3;bhT2Gik^_v@wvs7uS}LBGnmc@lO-9=dK&7MXLmUESE}^u~Rz+-}vfWsd zrgFq4qgxJ4rgAczlugIA+A7x?>(W#L%7bpq9Oc2rA!#ZB<&j}g9txczP#($~ew1A0 zv011*POkFAEL5IkoNPBd<(MPDG0%|e#DjIcj(G~UoR^*IcFa@2F;C@oICC>KoENr+ zvqTMNyK6WLYB-zMaK79u7s)F~cQIap<6@u|y!PVFfWBO=Gu z6K_(U4vYoBQUDjRX*X=9X}8GhO>f$bqCY%MyHPalR^v9?r&3KDF%p_~x4eq+z=Dsq6tw!+`*rbURdb2mIa1n{u@C0H2h5=(BQQ=^pwN+QaeCr?|@JjOT6t*$1#78jISz$#`9^b{uhu_FBe^ zwwWyhD?l?_#!En9doAN-pbXoWUf`7%8X!^t%mu(!01W6)Z^+yBwj4yLw!LG#D|es| zW$Z1(bv@Aj`a~#Ok4rs%N#z$#4Fk<{CVqnYJ>1sa?5`$#~jM?-x%LY@cby(=)x<5HNDOA4dI@5sshFBMujaBzK^!aPz4U~}^RONE6wMYijvrfehbG=91j z8X98CrhKMM13;C?ozvSMVxSQ2?3`_KwzY4=lRn}y zRJdO_;ki=b9l{CElL`+ACp=#&yi+*g1ybSSaKa0v!n=eMu8|543MX7E6&?~!c#%|i zSUBOuQsEKdgqKK#M}-q!DitmbC%jB5Toz7vxm0*;IN=pi;ql>w_mK)u3@5y=RCsbY z;r*n-Q^N_zrNX<16W(7cyk|J!gjBdZoN%2~xFVczy;Qg|oN$9wcxE`^q*S;nobXDi z@ZRBs8>PZ?!U?aE3eO8C+$0rV5Kj02sc=m=;nh;%Md5^-rNT?X3AadvmxU8S!PPkJloD3)2B^7QAC)_O+ZVD&7Rw}$YobWoS za7#Gh^-|%@yxa8uw%H&RUK6h71Es>9;e-#83U`MSK3FQeE}ZZoQsE8Zgb$Sp9~4gb zFsbk%;e-#D3Lh3u_z0=+5#fZ7lnNgePWULP@G;?pkCqA_7f$#XsqhKmgpZX9pA=5` zIH~X{;e?Nu3ZE8E_yno&#&E(XN`=o1Cw!7r`0Q}PCrgFT4JUkxRQUXG!lz1wFAOJq znpF7WaKficg)a>!yiqEAc{t%Sq{3H*6FyTad{sE%v!ue;gcCknDtv7?;d7+I*M}26 zS1NpCIN|f8!Z(K#K3^()YdGNxq{6p{6TVO?d}lb}i=@JLg%iG5Dtvc1;Y*~#_l6U` zR4RObIN{5r!ViWMzFaE&a5&*Bq{5Ge6TVU^{CGIwKS_n33@3b*RQTy|!dFX$pA9E` zja2ygaKe9<3cnam_*$v(%i)BtlM25YPWXDM@ay4(Z;%SV8BX{{sqow3gm01xzZ*{Y zW~uOd;e>CI3V#qz_*SX#N8yBTlL~(lPWX1I@L$6T-ys$LES&J2QsK|T3HL~a{}E33 zE~)TW;e%9QKPDA6!wEkw6^@1zenKi73n%=f zR5&l3@KaLZUg3nFmI@b!6MjZ2+&i4`vr^%0!wEkp7492O_<5;tzi`4YNQHL@C;XyR zctAMem!!fwg%f^RDqI{+_!X(}F5!eNrg+p3BN5BE(<68j#PMTIN^7t!sEjU|3xZ1F`V#wQsK$rgx{A6PYoyhfmC?+ zaKax-h4&06{E<|+Je=^yQsIhl!kl~_<@hXAE|sgCn1#w^a+Q;_ zP`O;La%vVTSIAZFo`uSN*JPn`tz2bi7An`tRd#2ga=l#Tx-3*~kgME~ zg~|ivDi6v+=sldC*C3zf&qRi2xL z$`j-&&(A{TiE@<}W})&Vxyp;PP zo`uTGdsJu$9^5ra4UM*MoY8EQ5 zk*j*Olm%|hk%a+U98q4EZ~$`7(od81tAM_H)6Nv`sf zEL7esSNYd0RNf+2`B@e!Zq4Ht5%4ilUACaq!Wufv>xyrmOR6ZtG*((c`kIPjS zW})&4xys&IsC-hca@#CaJ|$P#Hw%?d%T@NvLgh1Zl{;ji@>#jc0a>VgPOfsNEL1)( zS6Q5e$`|A+cgaHKi*l8NvQYVwT;-4~RK6@%IV=m6ugF!7$U^0-a+Ra9Q2Cl%WoZ^F zUze*a%R=QFa+PDVQ2C}@<@hXAz9m;VF$jNrlJcek~FH z)-SwXDm*UtJBjcQe&G#L;R(4vN`%v*J0B<&o|OBuMEKwSnh%i*Psw$nI=h{OhjMmD zI6hP=yqiqeRQxp`CKcY@gecO!@Z5Kpx?lKksqmgs;T*s45mMp3WCk-$zwnXi!Ug5V zH)bRac8_WKh3Tvj&s|ket_(Gu2-PWT_n15^wcFYfVWr6U4+NqogC!wWK1P(^dHAyG zM<@t)ui^J9gO?4z%PhRp_Yj{_TF5T zJKG_;i*n4(Rf%D`vC5sX%5CnGVcQJ9mL?~;vN9pJNmi1fqN%0nz^`(fqS5zdo6J9B8D#) z_aNXN?B`ww+(X28<>DR&+{69c>w$ZO7@%C-qkwx?KlcXUE)^q^i+eP1m-)F51nx2B zSUZ~eB(NaHhR?svoIJe8oZ4gV(PNgQjLX~9p{`pi-yDZ0@z}A<&2a?K8XJwD#8?^EaV=imZqKlO_>Sgv3-2 z9SAW4Z&D(o8JVbW(4iD3}G(5~1=^7p)yZDBON^d_BZ`$xM!;6EsXn2SW5@=_7 z+eBQl;bE3{cpyd^9&CXA;i1awJS0KGgGVAYJk0ihd6Fb(c<@N1hKIdn5;Qz`BvQje zwM>GB2bAy(4|6@dR}&r@9&BF!@G#F~bh`yKJa{Bh!^3=;1Pu=!iPZ40z$0O!qTvB0 zJj266Sqo@*Kwi)AP%CpQ8Xjz3|M0L#*26SBxFuY}!(tB}vX4DHcqCH8!xEVU4G$iP z)bOxWCPBjkNO*^bE;sY+d&7u&dzO&)a)^co^dy z9`-NT8J@%evxm8(+{42--|&#|;vn9%;i1mccUKdaJv>YhXzRUbiAy#-G8Yrc{FHCP$D427ym|9x zv$@N5)j9Km(!*UI#2%jV@PJVdcX<$dc*;XJqaN<^fIW2Op@+`a9YS|`P;9-+Lr-1M z-7|2P2eF5zJoGZ^;Vuti4^MgMt?S|T%3U6?hps&IF`9w9JfN+vJoGh6D|dNNY`x1v zKcf|Pmj|JTP#*g0{88egmItwir#uWW>ftUAVh>Mw7--bPT^`DLm4`t(TP2oid8njq zlEFGFx7Y6SP(`yEqO)>qxywT}&1$HA_2lwUQ(qn)mQ9K-4-N87U@EZG&JTcq0!zbP zmc|g^zu)32u(Vjqg7VE^F0i!5wOV<=(pI@>^1P=QE;?yxr|3u^$vPcC5_BwJ@zSw$ z)TS{)Ocqrq5CUbL&JZZ*Si!2(@qS-2QoQg`rGg+xmg)jQf|LzxIw^aBrK?;VJ=e>l z#5$#_*#RvvP~E^Ts5!u4poSH|qc+-Tn!yk(tM!0jLCpzH12x=@p0|BtjMPFPL{{qs zA%a>cgeq!B)J3G3qS~_uEPVy z)*J*8f@UN{8q6B&iYJDT8m&kaM9FGHAWBe+hG=6oPYfp*#Sj2wwP65)S`5S#o-bV< zU<`*BSVm~`ooF=QScsK1M?tKh83%E{r#V{FoMf~v@enU-j)izZGXWBQPjj56IoU`v z5fWw1@sKEJCP9+7=0r_rs*z4IB+ELJAz9E#ffR3@shZB?Mr)A@cnyYoZ5pHsI%$xm z=x9aBGE>u;=FITinNagB9nxi;*^n;iWI%?uKl3!5=|=O)giKjy0b~j~S&-$evslxa zVWg7{*|N@3$QE>Ru)xd3*0WDnXgV{E;*$%xvd$BbE9jJf65jDyqv^~t(kTfgWu0|U zQqU;{rM&%lQq!4jq*EG7%Q{a%X+ft9l=1dwv!*jgJj2xWDhp+0ovlz-(8+^5Z=D^Q z&Rl)v$4Krhui_C zqQE$E=SBZiOTo+K#a`Lv#w%L`YRF!`4>bfYYeG#!FGm}D`9WbXM~nHlqS(7+h4C(_ z1+`=^KZ06{_VVMxUXByJTv=={R~ma+8*0m5ehRe(FY7=ZLoY8Id#T-y z_gpYu7QKAp54`l8B~R$Qq_gC!0?U>Bx=>g4@@uFocv%nX30~5tMuqmWe3#OF%F!J% z*+$64)y3Y+s|)RA*|YjkU-s-*A&{zvS$sU zq3qfB&`|KK5i}A#Gpc`zXP&#j-t}*7v17K@IA)EZvFzE8&{*)S2{aKrGpv7#XG;BZ z-@RNe=GnSp$84Q(%v^vs2Jm|PXK)FgHHD^Lo~c#M>zYdOPpN-y|5QsM=hhdy{;e-m z|Kycz2F+wIe}!g(m(8KMp_hf~pW>xb|8!pJ>feSx*t4FigblhqOIHc9mo1=$?B#FJ zLh!OBv^4axQ2kT9RO+A3OI`hYve;feY3$`aa1VJI$l)Hr%U00J(91&gPw`UwyrGEt zxA70W^whtNIxn&Q1^O2Rn(|viYuQUPv=+Q<18oE^4eOtLTUf1scni?G{ykl6&z?5+ ztSz*aJ+nYt!LxSIPV~&E{wbch>mPdNUH>-y&W%0&`;Se|SmF9li&=YUFMDQ%_JU^} zpo8d{(N(_UnR1nHLC?Ie@;4XTv(3hy-3#~1p4s4D!LyFg(aSTe9d!H3`^;7RQ?Bye z{;8HimDwV{Uo6h`^A@?DYo9%+IoAm~$zD33li+1%=q!3^bbcuQc|IoaK0me=JLk3< z=iGg8pX`|v?h`!g0$l{p49^e6GxzzS+}_rmAKQw(vfGST_I|iu_AC_c7d-0ducH#m>JS#`)JBy31ZhLU+N-9?-+k%R=Xe;-&li5WUo$9|gtsvY?Qc(FK8! z-xGSuUdBRC!OLFIOYoAaZlU*b%BKmvp|{*U9(oJi`vC5H-KP@nTlczb-Q~=})h#*? zJg3SodB>?coGPU3`-AYHJa{5JC=A{g`g-|}_mSvFoxJOiGJ}55PZmjreu7AU=&y)) zZuKc2KB!tkKJRwo&p7_hJUmw#yT!ZX66Lczj{z`1b|Do82rdkSfrj%qYCMmJ;2~Kg z9Uc-y2Em};o5xY{>T{2?L^0>FN4$sYna5xlEW3~ig9R6cz!1ZEylOm;p)gby$%dhV z$S@f8d-HfzoX6f`&ttFgJRXLJWfyYcVZnvrfS)6H?n&Z#U&Njm0VCw@C1HfneI$%j zx_fSlV@Am;LN4udX8!IPc=p6T@xCnGwN!Fx6pWGwFAbxF!AHYrFW)hb=||y=*I*2c zkwwbF7(rw#j5SyToPnw(%wxYZ_jl*v*%SN4`@)`F8VBQK7jA=bf(wtpBZl+%$ao&( zVZ1C-9>xnIkHVwBH;<3RTzaP1^LWO19ur`K>_SDDAh<9QCW`aGE3`uI{FUl72`0(i zE5Rh8`(&7`bl2sQtRk$zv&GJ(XN_~|F?dWKyfQo{3_b;>h`!_1Q4#xKDomBT-vLvF z?vKOc2ENNGg6{{4eKs60J{zXNGV-C!bMQXtuL1Zq>HJAsU z^*9eaFLh_bbH%Qy&l%U$c`#3Qp*GADT$m5@4d>x+JdXviKo+SB3j~pcu<-Zhp*tH6 z6?-0sjOVck7RfHuhed)5i(#=a54v_QVm~i|C35$Mutey-6qYL8#r>?P2)T5)*!%gg z_kNb_1%XZE_xgcNwNFQ0bULs`t5;QcH9}S`6svnQtCyU?g{|5sR_!#amz|-46`n?< zb+2O8NwYd?G-4OUs;g#o%*d*{V%1Z#I&S1wAH}M#X7!5B%I((x`LjbI5+`-uyCX43 zvGPRXHD{PGN4M2b#mWUhg_11TD8; za}_I3yv`bpxInS;#Os`q)ndiU6R-D-{92}1dE#|mXXW;5rDElY*9D!GI})pvvwImV zllS^sSSIZC<*?jSt+cpbG>ZEMMP~)9kaae~3PEQjtn}0jP3Hrn?AxU1JONM0I$Pig zL1z`LGSK-@H?K8YSQFbK+eX_a$z{7}`^NUYR zhi=67eCUI5D%kc98yEJd3jyC!^R_#Vj>ac6`pqB*u7MSLIe zljMq=61gODx#Wt#c1bMukIRUw7>E7i4#b^|!~XGI;|IrM{{&k?d;<1Q*qU%C0sAMmO6;D9 z{S&Vy`6prjq$x>DlCXbrMsmeu?4Nur`E2re$(7PIWpE1iPi3hgso~hJN!^*cM{=b# zNNb9w$ZI{n%7=dk@c!;~ROu8ct$6EbjpGWKR1%QzvqGOK1b z&TNY9xXjs^^CVZ6IV&nF2HRR$Ewfr<`&`!RS#L~F-kiKOdF!z~ zoA*WD70Jc?9km&2WMRvHvu$E#{H;hys-^zlK(f?j9A{fwvbcU@)tJTL-@R?DMcC-= z?qaszvD4euVvaws^|p5w!`{13XfgZf`_*URf1;mv-^f4NSKq%Di~bA!y)|O~qK00l zK8yPsI^J3de^bj_FX$D&KQxB-I3@nU zalFSW^$(BbJzklAVLb0K^ZunV_2X7&<^IKS^<&Rq75?S1y~n@(KN#QJhy4G@2fZIl zSe5_K4{u+p{>Q%P{h7h;ybk>F_UW$c#3#L9OIXe8$S-f-?!L}^^Y*XKb?BeBkM*uo zAN79DU=6NgKfQfzbe;R^?QfGCz+Z2lo8BNk>-}EBn%_Wvd;8w<2J_w9|5i7k|K4+G zbA!%7KaUx#-3>es@40li!RO*VpN==deDrf#!aCn1bJEXi2J3PY&C7dkU2n3v>F2kE zb-M}Y=RL2Jlk7fSviw_pOO zNuX|mVYg@u)Hu*)xRqm2Xj2Tog%d(e3T1OtU?XqwSg7%!P2!71T~_El!f0QDFf~ck z6J@L~CUQ*FxX|YD#iXtllR_uXBff;uf}czf< z{L2ZcCZ+lwcd0Lye=C-1JZY2rV)@rMxv<%V8&>`o*>Yck{_O-6lhhZ_zn`QOPyA*g ze4i+P57A0rie8fx71Pug(`%Ea?o`E^DyQlyU#ecSR29?J7uRc-u0qN>>M-UvmMv$D zXR``Chjr$;Y$7kgp5`Ulo4gbcg4Z&Q;dh(X^4g~3ypHKR zUN<0%*9&OF>jzBX4FaCwjRHR9jm>eqiMbJXnMd=c=8e3$`7Pc;vhtQv6@HJ@hqscJ z^ET2k-cGv8+gqY}2TN7n(K3*CvMlGFEl2o$md|*XzzBYSU~S$ta43Hu@JZe+@GS3P z4dgwom3c2~Z{FLwjQ6n~<$bN+^L|0uynj$zJ|Ji+9~ks39~5+%54MHyA-0NqsI5JJ z*fyIFx4p|p*wgq(`-6OxeLo-V2;yTLt@&8TQ+!-7=Z^+A<`aUK@QJ}!_#|g7KH0f| zPjz14kB4OQX(9di^pM?rMkwbqL+kQcp)>gG(6{-Vuw*_rtUF&2?#~y7FX4+KD)Pk< zXZe!IaeQf1JYN>IlP`~M&sTsyUkU5^6EThX>X=XXn%HrCZCpHG7q^qIk8jU6B>3|u z6V~&MiH-TwiJ$OIN#pqDLESH3T6H{YK2mp_{uzz^ge59E#@7aiOjxfhU&3f_g>i^#sKDF2Pw3x#P&iJGUeE3UW!#rO2H?F46f5a<3wn;`|7?lgK59)I{zz3b{9s%L;i0xi^u^45fLzgx>i#S3j2g`vtj1vE<*c$Tf^3|Ne(ulQ{D4H{=?}p?_9}T+=x8 z&&rW=#iM^#KjfOnqkmR^MG=-kb5Al zBXZHm^+>CS93a;{o&1YIu2&lQ7mHla^jgTpA=f9pG;;CC^-g~dxdi0;rf)z{rFxn$(}Wnew9rXV*k1M7h`6}bT!Cy+}+ZcxT<Eae=~%gH)E#Vc)y8bo2z^adlP(YvVVb8wZPh5`AG?`~v(!;kl}tj5|Do3=F?^MhRbD z?lv51VEB#hNr>*DhZ`7vYc%vI1H^XQ+O2 zyn&&g&d?p6)dq$pqkwNPFbptCvrPtuX5G;E{qFc?ir!JN9xMjmQGLR)`KPQYzsw%y zpRrZ^b9S76!M@{P@*Wq9De*7E0kblb$@$dL&{CmF${)1mt{-fUm{Aa)E{1<#@ z^{e0e{D1yI{5St{e$2nUANPOM&(D98pUM9%zW@{WGt-qbvni#jP({OU^L7NFCsffs zoWO$E*No+M$WfkFvD4ZyXP31L{^^c?dgkQpm1eZwY3)^D?R!9)vBP{3?ON`!KE#;k zSw7Bz^6oc&+?X`+fE2yM{E^acn6BSLf6y;}hxrqw-zZ(bL4VLMd58HkrQajEeuMv@ zU-}O7mrB1$x_(3cpkMY5^Hrta~l8pl4eOr0oUP9fH&dd9xQW znO$0!y#>~T1=i)3}FVd!4MycLyY-@Ap&ynaYgC_*d&nTQ7(Zb zjA8+cIEwPDwm=A!O+SG^!PE*?#q`JlOIvNupNS5Qm7gnWoFepW*&{n7NqvlQ5CqAC zd;vkiAU3ecgIK>32l-mPKxE^^i!bYUvY7RI#nxV6ovRs6aN05a?uQ6j+Nq=3!7h*b zBiMye9pF%-AWzL+Ag$MwCOX57l<=t`veM5GEGRj_srdh^?3493O=gl@1`9b90wE+5 z#34kG!AFRQGC}^D%w+Mhz%#Ef2$N+3AWV=6hj87z$q&`n$k4! zYRjV(3$e0ND8vd%aS$gf1%=B?qNI2{#LK3U5HFY}K!V3q8*REl&RMSHCqkku5eAzSWH5we92Ie>y#PlHP1|7fiZJ6nEEo$xF$89cUgZEE8mvBpSDV2SXOd?I^wdzdV|38i3xc%Aa-g`uRN5OS8oiI z7gnzVRFGFMXq;Fa){658dIZN(PMQg-SVgEPi%o)xg4peFyCU|OD7H=~HboPATotPX zm1ME$P)QKWhkS#)S}&eC!kW!eFN-QeWm#+vR2IalKo!Nad7@_1tPHh1;7JBcj#B8Z5Rt>7jV#}eLAa*C*X(0BLF5^5ojMt{hUaSt) zWwBLIT@bqq?lKU2+L<8iMUU7z_xqpx8c;(P+W<8Lv6@g*iP=VRnwxYndrFJhCe^cA zP)iou0<{FOyWwudGb*TB%r@&{=Gg|@Rk7MoTNW#T+JaaesH1qcOBCB8Ui<{@);!y* ziq(a>ve?AZ3#F|5MMNF3(JBz50ud8A$poJ`U8d?ZqEup1>*e=}; z@T}&WDE3tWUa{Q+_sC*z!##pnD`;gPwp%w%kC>#cW@~6Ii@gJ_1+g~J#vo>U#H1DK z**Q#KJSX4Nw#q*73>OS9sGGPgw3SD_2yKN?+d(^nDeTuRyJrd?s$%V-y)1SK+6!VG zpo4+fGrH{dh<&QY<6gK|7W)kD6~sD1M_J5$iTH&!(`Sna$rU9eS2e=};u|?3Bwx#h z!aKf$#)ej`49aHi1f66LzlBbMhn=Cb>>*xF3N`Dnt^ndYR+2D!$NIeYwV5*3eQ=*V z){k(XFjg1n;t8#{|3^gs=_*fAx*zVBm41f%1*NXgRZ&vj*2#Cc@*jW)WYb^a0l~Bz zbW@gKBqz?QIBMA=q*bILvKN{5A-Q4 zX$#T(JMK*N9Hkzy2jM|kEDRnL#QH+t!eUnWTHh9-NxmW$I*(*O=qF1?K|evVKlCqB z5;VyZ#$FD90kUK)3=kv-!a!Nl7B4TZl3EYJL$YZiJS3P7f`)%u6MkGBvT+ zoKBCJ$FqmwVOcC29u~xg!*Inj@hzV%R}*_(JVQL|Gy+D*VkKdOAT|<47M><9y{&A4 z>mXlvwFJlA~ahELjmo36i5>v@B_>bih_gn`{-$ztf_at(tmFj)5_eA@ zy2;`VvZpkqHx0HvZo+XePFAV`;{>Hg;1R{GTJjnwcVouGc-gczj2BEFg-1Q6+GuYX zr_ThKAWPJR34+8#nCR`d=f>XK-epp$M3Z2WtW+N+2}+Y;vaDn+bYt&~c+%3UUTctnlS|<5+{V=w}6F3eSj^>{cB z=E^XH4_;dx^Z7r+8}*mkf$7EE2>P!(s!m&YIZ!#$rogi7eIymIz`?VX1+b_6&4((V5~YuAYT(KaAYg&G=#D zy5ibH^Xvm-&)iQWxAiLeiRAL-h^>#N^r3hc%j1^&ndG*<#?K^opGNiqTYpXIBkyYw zCG@LdwH&R1uv&=L8d#%?7Ag(WlrD+y<~=^Gg|)KM5LhcHt%G%nlE)o9%4tfUh>x(Rvr(DdlklXhG!mW^ls3Xfui05DXiA@Y9~X+! zQ}C3mG#Z`~l%9sCy_9VDvn1*#wju1Ye1F)u3fRVJV_x_h5WSJeXLzbBWI|P{mDDd*!;<>x}wfEJHQq6Y)Ud!QC z{Nu1wP}&8%bV}X<{iaX_l-=45yJfNIuv-w@1ABC0x`2LLD7R##y|7nSnhARarG2nZ zRtlmUR%$};hyAkYY}hZDJ_FBqOtnP#PD})OPspP^3(v|DbKzM*;s6|wC2aGB(GJ2v z*>oWs6ilCk=RBs`Xy1!xt!K1Da7dO|42J}X!*E!Zkd&&Rr2F&myllD@o)=7yz!8tB zHrfxyYw`lTAWJNV7X*nH;YCG4Dc8z9l9%8m*>okmB$&PoFMCY2(S8(f(|YpzC>)g~ zR>4t0;uswBIE>e=@*SDua9lQB1IGo^SKt+osW#eAg-#E7-A=#>Sz;ZW5F}oOS3MHy zXeZ&MY`OtX3Z}2YYaUZ=w4aT)%IomDEU^(@7bH%>DMdnz2Eb|Op5M@n3wGmEu?DwE>(C-8|ZaU4DoBtC^t6^RqdIj02SHBC(N7Q_3Rwl~x_ zDz-N@!$9$Um+g#lVRu$DJg*tr#8Xec?}v&PHN%fIL%Wz-s^KNo(0wOHyKTZ9;@Yd` zco)-sU*WQ*8!TR9s)k=^hF@xiP9smRYKGd6!SE3A!a-HUz`KY3UQ-Me%Ykb6lVOa^9Tb)yIC{TehP(08id_$)eN<}eLTv@(4iRy zYmN??05Tow}eGx$tSU_1SUho%(k4D!6avB%qDFv|~kfl`WIX{$XmXOF!UV~7{ub0HP z5cZn##O$>Veh4^Fm)$RHVMF;B_+z_Fa`~V2|IGhO$z`f)YHVtX?JCm_(=KdJn9iFn zO0Ix%0ks0^V7nn;Z@@Fyeq#+e4oZeNl3S@vzXa2y7dL-5b^!+pofTxJhz_w+rtb-WS_7 z;XA|kV0$wB{qPSZS4547<`MT`J3V4W#42nrMtl?Tz2u546Ing7Cbr`uXGhM%_KnC( zk?3a>j|z=K{ivEzEuvasJ0ogk)M{+cMSU4{RdPk=Mpuc(ct($mo)$e5+oRF%M!zSy zAObQV8{0d<1joX3k7jeJE`$?|&%JB{2(LR1+ z{DSz!*uEBjG5#aTl@OOuGNBB%T@wZ;48wMF!oh^Y*#49ll!*C|STnIjBF-yuSK>>F z$0S!$KvHB9U^^sfQqmM`pG|r->2=AK9GD!F9FJ|w9fB%EuFS~H%*-6gmHlS+ z$Jv)9S59(HUJmAUPS2d-Ik*lvJ93WXyd=4pzoRx|8}4UUfAhni?5E%C$M2=!l7zqM zAE5o+U$Sm-KRJ$nj9Xu2 zvl{dk6^iqjgcq}qzF$oi z`6v46`=+qyKiOC9Pv3X+SNdX(ww2dApT+!zq1EA)C9KZk{-TCnCxs>a4INdBLh^TY zgzzN&O_x-+)KH~d13hoev}>fP*G*^m`?7K|BmP?aQHr8;&2{~xpwjMa&br1f>qC;o za{d8*bqvbfe@b8bo}@ciiGOGc>NJ#0&tj$i!Ew~FC}jWiI9llLWM%&0DXG&^LRgRG z{R`vi$2`Hx{Yzu2J|E@T?}Q@*jmj48wov17^cKcQ#c04?`h_<*yPrZxn_TB16~lTX z_$q|9=?xHCF}yd5ze0$c-yk6t!+az8jG>nAcj4RrmN!tS#c_sh4n?qgkUk|k1?N&Nw#t~b%V^m9vL-EOkEsq>?sVYnIR zru`gTch=)3Tsn36l&x2j^}0#tsGny&*5@Xkr+%(AS>Ky{uKM}bWBqS|`FhWJ;4Ly| z{k&7ypj&9(>fGt5z18Ne9mDx-$Stawdx^srlS{@yVdev8JyI}Rgn;W+4HQICzj z#bcq5M@=@?7Z3SYcIa1b)H@50_+p~{8j~k3DeO^ST(r2T`-m>Hd~wnL+M940Hqn2u{y(%m4#r>1xW{AcT+t_6MM=UazA|B)ZX?^^xQKK0LM2Yg%NnuYbRE|2&F zKhOEr<3C>yu~hliAGDfb*-r6`PS+BEO`c{?^WNHx~{jBx~;*NjS`Z@sSXQfN>TPx-dk z4Y9@4ZKjsSH+<`M!>pUSc2pvL>vm(5NP|-OmT$}5P+Lyjc52By<6FNQZvE6Xq|)hI zzZ#ASd6!x)iZEvczRo9o^iu%^}#(XPEYgp7D;imvU^=;iE z!&FrGZUkQYy$-)!>@(jQ-;`@id8mFXv~P`zE_XM=e*HZk{Um#g{G8qD>rzdZ|W^AZfoCK-`v~UYinQiZS9+WYm3|4x867Z_7=9d zqYh(!9oRg^SbrAD2CytPkac7avH5HedzB657B+<6$%gVFY#86nhWow3M)>z*BmHNv zQU0gcXj3^h#x#$O4ajBV1BS2(0V~+VfXi%>Igd>?4`ox#N7z)U9GfPMWYeY3*bGYr zHq$bi&9Yo!vje-aIf3u9xz_S*p7n9I(7KZ?vYus&gZ$Z&peAf-&``E4XeC=7bd;?K z`i8Bv#j_`Dce7Qt2ia=de744Rkgc^l*gAV#w%)#uZLojKHahNNPdTQsrycLIO~Ki0 zbMPRxCHN5A>U6Sg&h~7(a|7Gq{GJtr)MPtDX0Tl$=h*JhT(&242-_FBg6$9ef;|&f znLQi!7&{QQogEB2%MOR(MFfRP;mabo6uVO|Y@IU>JKF4zn{cLF{ZyId(2qV(-PSXXoSU zvkP(a+52%HvWxL~?1T7G?8Eq%*hdLr>{3E|_Hn{m_DRAO_Gw~eb~$kq`z-Mn_Ic9X z>`Kyu>}pa0`#PDiZ;~6bZPpSLa&uO{rm$U`!*K~=q zbQkC8!?<7iLGGVn;iilhJRoBkH)qOSU&eF2J-4xkkuYOe>LVjGSb;h+Grotfu40xsVGCsDoTnxx{G^fhu1AeU%qhFmw~QY?2M*B!ZJ%M#>zAeUyDfLu@HQY}Z3 z>xEo~1ug8okxLIG|N0=8Wg-6_L@qP18ghM+%L&Xzt{-yQf#Z?uk6eks2ay|qTy9_i zas!bo6}TL^hmb27_#1MAkSi1T337vxD{ZB98-iS(mDX)2a%F>ZkQ;_vxu9_59!Bmq z+sDWaN3MeHHRMJhSKeM8xsk}-ZcjvR6mk{qW04z;T)w>*a$}IIWIuu2SmdhMcOy3r zxyp_>6)jc;xPIbVu${G&ME z$B?TL+yuEP$lV>BkK9z`Y6VlAA4jfEFvWQqa#-cUHleg0E0Aj)`XX{G zk!u&a6}cynYa14U+$!Wcg#L!yYUJ97bw+Ltavj4OAh#B|d&5o0twXMJ*cZsHN3K(N zU*t9**Co6Sa!(?6U-%y6HX_$Gd=+v}A$NcHhsZsRT(|HO$ZbOIfrxvM+l*X~i0a5~ zL9TnmD&)2z*DK<2dE`b!&qVGBa-*Y%BliMwqoUtK z?nUIrM!$sIOUR9ZY~)@>?hyz>?kIBOpgD5Kkb4xWB6l3Q@j!EX1-Xepb31|D1h|0Q ztH@1;qsW~^Zc+@@oY#<>5<@lTb>tq48HL;_+N4 zy@cGd_{GS5jNHojN0IvkxfSsrA@?bAtKwfp?lN*uB$Pq!GvwAJ#31)Ma;p=DA@>Dx z>k_&k_a$;`6AmNy6>=LAo<{Bpa_bYRPF_WBV*=I5uaSE)k#gf31mdk=vV$dF3!6_e?V8 zl_LPT{V6HPnUOn?Vna?s?%9-v$XSqkE~O%Jfyf<9nU0(lxx*>LkPAZYP|9B9Y{(r+ zS&f_>x#v^^N!cPcFpxme_0 zPaA+-9CB}@wMQ-_IO8O8rIEXonS)#z5MC8gN_jwNPX-5U*zRJNp?Wl;{mpLyXcRO-dbG9K@ z3Arnb<#sT2GIeImX?5f~Dl_i58?W`l7{~t@lXCVrYBIJNU*g4?qdsCjeqiokP8Pxf z(JTVr6a=zpYysO?7S9s!RT9Gk3I$TJO~W<=+f0;hfc^bgprawSLC9P2PtX8nb2MU% z-;SbRA@PZHKbn6cwU*jQZKZZn2mI4U;Vg*;Tv-F|E=vuyFTRrXtOKkARSsV%+z{(f zjT`FbMp#E`+( zHGj<|M*yx*1JlQhH6&<6(3qeJfs3FiK{JBp1T6?!65K=3il8+?8-lh3?FiZvbRf8w zpd&#ig3bi@5p*HApP(zj0|ea&x)byu=tj>5pY#?}&U?ag(1WyxeBG^o@gk|oFI6W;3UCo1g{gEA~;R( z27>86TF^J?uWu2&O>lc#q&b!3Bc%2`&D4%bJ*K^k-GT3-Sv7(?(U_Gof67=1^CiYAn7?DJjQMjcpCpxI z{(zZ!n0hjnB?TdvFR*}+fKV0?9uUFIbqMMb)FY@*(14&JK_i031WgEB1WgH=5i}=g zLC})m9)eZ`tqIx?v?XXq(4L?J!My|>2|5vUCb*BF3&H&aT?rl_=tj_;pa(%uf?fo@ z3HlH`NYIy{A3=YD0R#gH9wHb-FqmKn!BB!>1P>DoCm2C6l3*0UXo4{WV+qC)JVG#@ z;8B7J1QQ7+5j;*Xncy*kDFjmqrV&ghm_aa;U>3n_f;j|p3FZ;ZCs;tRkYEwPVuB?E zO9_?{EGJk&u#(^jf>i{o3Dyv-C0IwWo?rvPlLQ+Ho+5afU=zV+f-MAF3APbzC)hzy zK(Lcw7r}0VJp_9R_7UtSc!uCvf&&Bx37#W3L~xkkd4eMZFA%&)@Djnx1V;&u5gaFY zh2R9is{|(rUL$y&;1t1Wf;R}>BzTM9ZGtld?-0C8aF*a4!FvSf5m=u2D`vW4x{4rK z7%OM~nz0YrM~vf-*D}AS3APYyC)i1_kKiD|VFJ84#_%pA!s`h9ZhG|=!C8X$2`&+Q zMsS7TJA$7P{24(20s3W5qJxF)sf(Sf*u495)335N-&aO9KoXmlMr|tdNqY$I>9W0xdaOdmJqBU zSVgd&fa1sRrB~Ysb`k6+c#hx&f@1_H2u=~aP4F%P??SKMBcLGqQxN?>CHS1+D#5n| zKN0+jVDdxY-RTv@)I{Ml*$F}kA_!s#;t5g+(g|`9cprLIl7OOXqUf3^uqFzui2`e? zK|t$kqSZ1{>^Tq&puaXFXi0w^LNJ10EWrco!F&Q*U%rT7DFMZgQ~dZ^ zf(-<65Ge^cB_XFI#Jm5>R0In*><|X9&&`oG18@fC7tm zK@ljhoC3=!u>4m7ii;mb*N+10M}hUD!1_^O{V1@06j;A_0t&1j1(xU0D~hh4EFk~2 zJpDDF;0}Vj2x<}3BWR4kE7Ggx1g!}=5Zp)5ji4t%UxJ4SDA<0(5qK4PHJV^N!DND| z1TzWd5iBHFMnECjud!UNp&v*{OZ`i%rWC%e9;e$3GXFLH6S Gv;PALaRToE diff --git a/target/scala-2.12/classes/quasar_bundle.class b/target/scala-2.12/classes/quasar_bundle.class index feab5d839ca79a747be061bebbb7300b19acbf9f..a9a26a6be3b9ec5ef694aa5a59e6323c1b980936 100644 GIT binary patch literal 54810 zcmcJ230xFM_J8$sb6TK-Mn&;J@kS94QHU|aA)+GsNYPui) z>5h9CV+)L99&G`CrE6n1H@ zvNf5LwK&JFGUpVJro|c4k}@+LNzS-xO`GM4(}%m9Q!?XC{w9+@!Q}5W`4dh4JtlvW z^m~$kf38FDuS9-s@-H#@Q%wG9lRwquZ!-CZEB|odPtgVc(a4{s{Au7{BK;#vz<-$X z9|rzT>7RrCv8MPvrucL-zY*adr~KoPU;68iXM%~pTKWb5M3cYCGi zCjTCjf0oIg5+BL`Y?FV2$v?;BpKJ1GoBT^m{<$W9waGuvnDlYhR+zsKay zRsLM4hw=oG|6zC>6-a;PLh$!We-8Q=DgR>dPfHZ>73eQE@fS!xwxj28lfT^LUt;pF zHTjP)`MoCpQj@>e5Q@mk{ zFE_=Wh}WnT7-DcT~(@Ex-oQYRE2wI@Z(ZPB!Vzr>lDvpK=hK0C>k<1$*;OwU-K zvT0m$Tw}&emt#s_Q(9|73XG!t(B!L2wWIYE&zPFVIDJ>!s9bGRL5rU58CA2Xpm)!j zq#Yy59S(=)b7pSR5*ur>cV?$A*)}IBX|WckJCfs;tSNE1;txwo@@2Y=ZB41I4Z}C& zCnv>~J98b5l+xy^{*Ls5=BA?TimoOtDTH^$Eq2yyDBc45$7rPm?c4VbOPD|2=}4&_ z)sOu8g!Gx6>vMP2Ig)p18w#73#+QwSqrkf{e)s4UcR{9}l9W)>I84`9Y9*POx?|?F zOs8|1D?V;6`scTTHq5UcoMElJhSLg}CKfeUjNTpZA78x17w^klwRwK8 zH$J1GbL`>{pCj3+Z^&!ixOaR-*T(tXoufz1%o(5GrdMVbb~YAnsmR;Z-;r^6n|DQ3 z#oTdDN9MGQhOYH_oeg`BZqFH4)Kiz1JtnifU=ZFF=PH@IA#aN>FMDT4>6ox&_rjE>;w@|9TPytQb6XqYckO`u@7TV#bWBPH^wZQ$(4I-%5?9dNSi5`S z@Xfis+iQ4c%cl9Qo^`w9=cO0+F0IKLo3gn$=!)|x{K)mIHqCFYn8!WMGH!a##6^lP zxqE3^_Kdlk7i`&hL{>xR`l8;_+U!L++Az|O?Ot)jsP&!e3%q(}x~Px3G-&to!W|WR zr#4hK7H^G|o99l=Slk-o7v&mT)Yby+X!d*81^Y$4Rr(VAQ12^~vv)%O4cE)m0%H+u zx3!PP`VG}za+fD{_w<|%MQuK)KPaE5XCfb1?!o!M`X%y_-I&**56Z`|!cG_$ra5Ij zm9N;8Fnsg;pf5gay}wBtRXKW8gMY*P7VkV`xnI>E)RVJvH1v~+g?&p)vS+N?kmvW6 zVE@f;U0U1P;2*oV%{wlmJ#}JwrtZpYfd1Co2<->`w7sGzYwQeHl6Ph5?q$O_6>ss3 z9<{YIeNk_VmaGlNk8?~7_fLI&^@IhjO|_$pX>eFayQM1tLbdHPH^)Wm*b5nlTNN3WnxtaO;@Ph1yuCax|?eVi*osD^2 zt~jT&3&+14z`^*pVS1)BcN2_%>6L|@>kHd9#-}^GU_48jruZvlTpPsgXo9#*h=b#H z7i~?BWY3iG3;LEOXD{-LabZsTJXhkj>VddS zeR1ZDPH4~VHE=v`TDWCp5#Qk$m$%i7ONHaUav|@B`7gLMwY9KoeZF5`lG!k?(Ts!R z0?Jbd{S)}wn&KN_JTKVd9esE|8>i!OuwaWnjaTF}V!mKpZpz=fbaU32l+C%BCf@18H{|w~ z#_tI8R!zun_QgX!p+4(ioT;9W5BY<6db2hHdHBZMo=VJrQ+_YxXHCka;%!Z}88hKH zh2xETri@$C3-iUIRZV$-b-{pq!*;QK9T3WPwT~|han+q=I@^FqKxxabY^iH!jaJ-fPEdU_xrQ!uDayh85jb$fRD zG&Z`**VWR|+v?4MO?S&yPgj?>qX({o6MStdB)+Fv#wN6OdZeX$wl+f*M6g?%Ls*0g zc8m~EG$a(Qq}Jwkcc3Te?$Fq%s!$EPFl)8m9&ZrwxVz8W0<{wkz$(REU7bF+uPbQY zg$)wgB~ZyN{(v`>1`qVPg8@&A*WJAxV39nBoo*y{wzjl%x}nD1{yuLY;A{12Y=m!+ zYiz5x#U1SEb&DjtEiLX=UyrA`1EN!*`nr4FTRj~?cfh*??p8=gptnnIr}`rS(AOYM zlcOgHHz0ZdBz*`HF(du%R&R4}ySvlh>UD>r5=8R8R*j`~c0(RSL?mTr#2HRq_ySnN z?yxT!EORvwEPQD)h33Ha?qE0*BSLl2?G3cGbOq-_jYYX~2fOkHyYe+=VD&@kt2(`% zIq>g>E(ERO@IfaS5$AQa?n9gX0kJ!>-RcR#y{GVY zKyIgE{8mq(6$qhSAi%pb2%Wnp&?0+GQqb4w4aokU*yC>tN;3&=VReZP0gy6Ry~|x) zUhS@`tSQICLf+r1@9pmJE`X|9KfrN#)izI`C#S>H)tgP7|9L>L6xV$?|%) ztE{Zny&Q57*{WIv>4<%`wXQ~YS^4VvZAoI>G83m@bVl1y^^@+ad`a~b(FSV?+wAx+bs#)nSsjRPqxm!AfJzUz2_2uq{$}&8< zq(`)Y@<@X6($Y}KFaeTH16@pPEi)q|hdf4Pnv$btt;`5yLUPoWS5&U531z9yRaP6e z#i1;TL_SpJQ_8Ac?vl03LW4oF+^%z1!U4-e8`$G94G~-ChC^CoW0tw<>fykxFR!g# zySm<8TV7UKTV4uBL`r3;t8{s}I}a-f@-{+ko9Zmp?7~56fCGe zjSPjAyG%n~I1s(E#zK6eUe(AqN`Zw>Ruwk2+4;wBdkf%DUJ^)4g`ei zO>W5&io(M_iBr8?M4NiKq>^Px<1htU7zT~{8g=TmAUIz zx!2Z}yH{7Ot%JNIRMoA`gHaAn1i*^)o6v^pH=#|@Z&Gm!`)ExGGUD~y07rO~M|T~Z z5Xp%`Y}K1aUT4iJx9snzaR7x}tgb9|=an{=R>4LJZj`tnw|Hs?=VfABu!&tT6uTQ% z)t14iA#kBXL&VA9LB!Rss&`f4zzr>j6yfbqEu_|#!wFwK9P#QjDG9T!j-g@7mQ|6g zwq#AzS5}wTx~s}7fWI83AtT`Jh6|2KGb;yPvCbN}2`9>M39P}jKpXTk}_si&Vq@8o1DOu5@CYfTuax+A$mMa^}V4; zxXm(iU?oTDT-_N+4hIA0j0oqDFs@C~CSz)F>m=UO)8X%Gm)Tqa)hxH8bGU+Q)3oV` znE^#<4mP`kaDlYd)3bG`OsYE@j&8WrO)-P4WmdqsmaWajgy+H0Zsu^e`8!%+wi@Ki z;##hRz#t@&#cNoV*;EV$?qgM{Dr7uX240HmK%vqNkwI|_ zVzteXv|Kw}TY`l@0ty=F^Y(eW+})mlFSx5^s~7LHB;e&XTslLyk$z#192^QIEtOPd za0Ct5-;US&&S)0^DrD8b`7hj}YYsrId7)(S{Dlh-f*Ul!7C1bLhU`ZJ3lllM zRj)FT3l2_sS0x^|u(jYmgERcWMDVM@UfV@uRzRB~Kv(OR**UPz(E-__=8?+xG` zKzDn;#c?HKJ?Y^CGG z(H5zG_d+;j#Q`+jO5lMuIZ?LBN#SsrIT3Dg2oO0QbR?*>!gT+|!A=o#?NsfTSisXn zjw3@hJnhif+#y@PazJI_5Wez1i662{V6#J!2jmBeywF+;N9T-dXKH6*DbI$Jw`kT@ zZ=0vLBbWu(CHl-+aOFELW(4GbM{+Q$l56K{7a;G2Vj>9k`+Hj8aUPue1^Pl8&?zpF zo#Il?npsN{b7+@y=4EYYT?vCz=&mw6yMYtf!8epSYiCyjbvw}MpOXO1Qf-F@cF$F?Eq9|fs$n@PELgQU9=4nBFO8m=-1}~FRceS>z39-ob8a-Bb)`K z^(W4Hr1dywL1{h7S+BI7=B!Uz&vMo;t>-!0DXkYd+a;|(b9R)pUg7L$Y5j$>-O~Ci zXM3de24{Pv^*7Frk=EOs9V@MOIXg~Tf9LFYY5jw<6QuP|&Q6rpzc@QdTL0$kWNCfE z*(uWcjI&=z>kH0KmDX3B{Zd-raCVxszT@owr1b-5r%UT6&VD5<2jlDvX*oDMQ(6XR zXGtrbv$Lg@$k{p4O6KfbX>rcZlU6Ec=Syn@XBS8-jk61-HHx!~q&1qei={P|vrD8k zj%#&^5oDa&}N!^_<-Bdsl*-7BqT&hC>|D`)phtBtbf-DXX?1h_ZY|dVh*14R$Dy{Q5 z`-`+L$jY}Bdy@#WoiL=k8^*Co=Nb5|1I5nX~Vt^$KU-OY1M3{UEKsa`vON-r(#fY5k3}pQZIS+*^{?yIj+x^>?m0 zr1cN3>C*Zq*9>X>3x1X$t$(Z83$Cy|oss!VJcE_bXXPv*rnp!^RjXvsbew9apvXg4 z88|IQVB{gMjGH<{9NsXLQIldsMIy-DWG5njiF756!h6nrA&U-+HL3Dl5e* zu+F;BdT5~xoqdRURS&5ClVDZ1)|gf8S_@Y7Yb{vSu(e=S$JT;XEn5p#^?ay?#)nz+ zt+gJ8TI|0VYO()fsKx$^p%(iuhFa{u7;3TqVyLQDYTS}*H$n?LWTj4~`Z?Yx#>aRv zgqoJ4mVq21FtX4<2FA=>c+rTAqvl=HS`ryVjjGX0Ob(I1$TRsv-$B#-F z7XlqJ-SAqeL()agYKN#n)5@wtCXMT;OnqmF-iwg~yUq}8jlrQFHpJnmR&B{#(s4MC z4V>@jW)8)LIs;ulp{Ricp~iQy&LuK~(oGC>=3X5$NOcBrgwWj?m}H(JNye;?s3|OF z?jwCKX2uRR%Y~P$$tH@KRHR>$gG6|No1`IIP{j;AE18zVNh)$&j9w*YJ#>hZPxHDk zylXJT$!B!v5GS9}p+lT}Mu!e@@);dE#K~uL=nxlA=Fmf4JPi&W;^Jv=@DLYIgM(H5 zl7pA2FUUL(aq%>md5DXr!NEgZJPi&W;^N61jMoE0Ts%dGTI|2bYO()fsKx$^p%(iu zhFa{u7;3TqV(1X{I%qYe92X`M=OVE55f@p?0BT6XwUKhYp^Tx1v{1~@Ls}>br%W+H zP~$!Z;jk|kaLPF9JTEHFbOuXJ0T`{8drC@bZW2L}RiHAE8g>UQ4wa!)?M2p%${6ZQ zV!%>T8Ajdf3#~96nkc;Rbm%;pr^8r@MW(t~xsI$>741n4OT?m9nKP>K2d;IManwv4 zUIHsas1`S^jE!9rkp;7{^E7ZBt&AHB57EgVrE-?VrooeR9iA^umlix zXTmQw%oL{IrgAom%|?cEIGZD_^Ek_v)&-o+mDWY@yI5cdEjuzT-QsK>%Rz!mVF89I zL@XZRY(C4yomULpDVBM0mdEmOCp@HDAj9AxRe@x?c3_sxKTYLqAuB}O?>Ji|8UDc8 zVrgB^S&_7E-EEaQu?WX;rc>i3?U)v#5#`(;>iK47={(I;oC*%}Oh2VJ!?6?o89CoOo;RWB`g z(6v@tZ*#UzTJLh!Ag#Z1wq9EQ;H**B$3HpSAbtPhY@_u3o3l;Q`h>G4x%V^9HcQ_Z zoVlg%E6%n^>l@BI()te8iX86i@&#e3s(Go*I$e8{{kXU= z!C=WOL;oq6O~Q~#p{^O@XYvV#fs4Ucm94ERhgCV5;jSDbzL*>FMnaMiXCy)n>w*Da z3oI#IXzJiGfW%Mgfh*YN-&nf;1wncz3Ko5#4JJON@Amp5>p+ALK2KJa~+4=0<ayQ<}{!S&(^O>25Y?uk3k6r`~V{S z%86CILD{&lTG|<|0p%4{v^mLWGTg}^%-zN`btD+g$wmwIm|>>DHo@>F8*QQ=g}Ry? zW)qC9$%YSijEL-z18jn^J=y3m=EFh(+2>)MX;S#5iLmmzRII}t4%4=`rnj@%8>pA> zL`bXh!}}H2!NOzQR?ZRC-r!b$>uOvm;DzRaU$Ugs1>rpd)t+t@!Yko56an#i4|o?N zORn?x23ow!;6)&?Lb0~D3x5~C&e!7uQdd`(AKsmSZwG47{IJqb zcp$GVlR22dU~GX^DrtBo0dJK|!}AEC;VeREIEN4#&J%=&vjm~x96@L}Ll7EH1B8Yd zUuc-zg@&nJXqecAhRIuKn7W0AiCbuxwuOdCTWFZFg@y@RXqc{rhRIrJn5u<_iCSow zriF${T4-k5T$qrH@nkc%@HJ`b4EqQX1A0igLh8LZM+Dq0q33P-s{~ zC^W1f6dKkK3VpiLzf$@PrO#CQETzv@`W&UtRr)-o&sX{ar7u+aBBd`@`VyrtRr)fe zFIV~srLR=_Dy4s|^wmoLM(JymhP8mAJg^c_Xjlg*G^_#?8rA>`4J!bJhV_3!U$68H zO5dpTO-kRa^esx?s`Ngk_bYus>D!b(sPyeh-=XxKO5dgQ-Ado1^u0>or}X_wKcMu3 zNpHupIrC(6` zMWtU-`p-(gtn@2NzpC_KlzvU=zbgH@(r+mJrqX{?`Yom3R{9;K-&OiOrC}|eC=aZ} z6B^dx2@R|8goZVELct!NZ>2w0`V*x;Rr)ifKUew-rN31AE2Y0y`WvOc zRr))nzgPMPrGHfVC#8Ru8rRif{%}>D&<>?_r46OyP-~~ctBvEe1UPlw0nz15hd;&= zW{=N4sHNNlro#w;jECurv0+9J$jLH9OVx(M76faFK!y7gv?Lg09YzrBBnP-hfMW!t zFhX;x6mlRCL*r&2)JD_%Tn0#fIUs9kKr%)ft4NAqh;{%;{Os`uwTwT4H8_`}Wkfia z@iLbpZ*dyt4JapQ69-YwIjBvcGe%M7!kmG{4O33lvIbE?E@xi<-{*3cHhT~y#<1s9}HB2rjJS4$5(srMpoLz$B1WcbXwJdaB07Yq zmX+pAL)Xw&iWF99tC=oFgw=2+Yd~n??C}|M4{Gb_BxcK)@WGa-)v6&OQL6(B57tDj z9um{l0lh{P30@0c3yIdjf4xY!F-Fmv=yV4cZ9}*{1{7^WxM-U-x9U@oqRq*MqP5XU z3@+Lhl|-WE!P*l=Ylf3ZJyfJEkeCPln?;e@wXG__AWMKh#!_cPg6T$jTzdRLEkGx` zTtHrJdDOKwPD^6HlV8x3}rN?VN$j~bP6L&BT2TL{8^lJGVl-1i?69@K7Ey)SasHD|we#m!JeD`#DIMlP$h zJ3^zxo#NoUOS@YgNfGMt`?agAQ^RTJ07}+Lw(h-_T9uc{N$@k)z(;<~NbsB1zANhJ7VYv7Yf@Tb=gYv3D6aH%!$O(eM78u(@sTwx7-3kj~Y2ELU9 zue1i(L_;wQ9U=4f+32w9ozLNxRvn&PHW(Y zNwD7<_z@Dk!y5Qe65L}A{3jCJYYqGu3GTNBew+mFvIc&F1Rre;{3Hq9V-5Ti2|mUe z_-PV+oHg(>B=`ht;ActjN!Gy6k>FFTfuASAr&Bz@N$?Zaz+aHyr>ud$B*D*E1Aj$=pR)%3ngqXK z4g3uWe#sj6TN3=THSl*N_*HA*?@91$*1$iI;Mc8ze?->E8c-9h2izn(}@d zl%LU*589yooThx(2IUtt<)bzzzoaQ2vqAY4P5Fck%CBk4r)*GuLsLFugYsLN@;Mun z-_evW*r5ELrhLf;CH$(JTC4c74ay&B%2#br{zOy0W`pu)n)3Dko)Q+ul6Co}4N8rs ze9H!CEM4Iwr8!W3hufe`rzxE_D96#1BW+NQ zrzsD!L772QjGfu>BiK{=789B+ei5=}Y52IXX$a*_?oOqw#&2IUl*a;go=sWjy@ z8 zx7(nspeZ|TP%ft_{Wd5oY04coC|A&wJvJy;(v-b6D6447ejAk4H03TElr=Qv(KaYo z(Uf~^P_CvakFi0yhNe8u24yWxd4dhfI-2q%8N z-3H})n(_=Al#MjySvDv)(3I!cpxj7Po@aw{6HR%64az2(@**3Qn`z2RY*4ys%FAp} zZlNi!utDjeDX+3Y*-TSjZG*Cfro6@mWh+g2oefGaP5C<;lx;NSA8b&z)0EfSpxjDR z-e`l;M^oNxgK`^9d8-Y|?KI_n8ZBTa6ly};o^wX4g+o0^GDetvG zxr3&>-v(uXrhL!_We-jHuno!}P5Gz|%3hlCF&mV9H02XEDEn#3r)*H}q$!`VLAi^j ze9i{tQ8eWXHYks#DPOWdxtpeZ*#_kvn(|c}lzVB)*KAN8LsPzPgYsCK@=Y6*$I+B; z*`Pe0rhLZ+1do@Ng15OFx?^^SRMr zCkdWIg3pfzr;*@n5`1Aacq9p)OM)+s29F}a^YlxIG7oy$^k@=1U%#9HUm2b97!sVP zUqyhgjs}k0AC@B|WEM1pUM22Uix#U%KaXz(Nwd^iafZ__q6)npR9gajXmPC1hVA3=f-MuVr2 z;H4z^j%e^y5_}{HzAGA>MS@*q-@YdrJdFgGkSX664W3SdOG)qp(cl>*xQqlp6b+t9 zg3C$pBhlblBzPGK{!=t~HVLjE!H-9S=aAs#B>2f_a5f39B*9NdgXfaq6(soCXz)A| zypjYz9}UhS!BzST!~pnGG?6TzN$@+-;B6#$9SMFf8oZqZH;~}>qrn{{cs&XJAR63Bf*Z*J z@WW_u7YW`#ru24elnvn@I4d(cm2U{sS8W-*78SFf{YYi2PogysVk5 zzB!Vn-4HWL`0fZMnE^=}j{Vy8|Fb0b$4nBwOoB;H!X)+m+P?o$k{W)+SXONObojIo ze5xfbYxXTh(g7poHegT`q1A3OU_V_f6x14hPe#>D;lX`#)@V)OLS<`l7c2Eb>i z_*vkQWCx77_Zj2%>t{i5PUCGx?tcB;hd=W_mNv|Z-~!H4}%XKbNHZj3Y*VT*-|!~H8CfA5IK$Yu#s#p8^tbUquI?c z9lgZHvVXI5_)_OMZ4Mi+Eo2$mDmDQ=em7A&j!n`oW|OsBS*G?Ro1(qPrfNU2EXNo& z%~8yzJL=gCM<<)$m)i(IYvoyI8EWh`QTV-4$u$#I8q5epc%upZ+T7BoI(y>ZE` zFK(*(lBt*(RrNB)(E5zBa}D@ZK5LjbaCi z0E!+IK@`0x`cU+v*ok5nila~*jbb;7Jt+2~I0nVBD2_vMJc<)goQUEi6epv=ubwdc zdI`g?kTCq32*a;}F#Ng)!>@EO{Mv^2Y6d$Kt+P;^jp7^>=b|_d#rY^MKye|8i%?vQ z;t~}2%{F!^T9=`?9K{tVu0(MaieIC+8pUr=T!Z3T6!_|QhOcmE_$qdWuT*FFYIKIL zIA{2(a)z%QXSbrj_lL8aP~42-78LtX>_>3`#ce1KqPQK!9VqTZaTkiaQQU*#UKIDC zxF5v>C>})d5Q>LUJc0sWear9_whUiI%kY)53||e)@D;BNU)9R+m8%S2oywj?@f?ch zQM`cSMHDZg_%n)^QM`iURTO_g@fwQ1qIey}8z|mH@i!E2p?Dj`J1E{o@g9o5qrg}H zF?@v|!&mV!e5D@4SK~2!#T~;})iHeK9K%<~u}@HZisCaApQHE!#g{0)Lh&^S@hM;S z4Q_sm;yV=Iqxb>Ek0^dZ@iPed9x4qj2MQg9fg%os_!J)#cdPNExf*^zR>M!eYWTrh z4L?z<;m0!>-brG3x0B(OAdClK;pIES`;ZLpd@#H($nZ7>!`l%IZ!0joJpcp9*^J@s zbcPp#46lG0UPCjyQek+B#_%GK;Z+ZeDj@L6i{YgR!~2B{@B1;l-e-8-&hYLf!v_OQ zT+-qU&_y)zdD857SJ&GSt{D|Tw6hDIy zZ%WZMv>YgO6b6bo6!9n$P$Z(jcTMQ{b_gBc=b+;o7<7DRf{t%F(DA(l`Un(G6lo|% zq8NqZFchOvj6pFLMLLRcD8{46KrsQuL==-yOh%E3VhW0>D6&vYLopr23=}g_;BOUm z{B@y@zX#Ou7koPY=1#|7$?5pJHhn&dToemYeH@ib52NP%K7KgrXS5;V71% zI0D5|6i1?Pp(sI7ilPifIf`W{Do`v(fot7$T%E4tdU73Cfa|zsTgO$_ISEE>i zq83FRih2}lQLIDJfMPw0Mid)RY(%jMMH7n6DBLKvpzxq*M$v+z6@?c?8;W)mTT$Rz zDIHfg>9`(A#}!06uKCe%m5z?XtJ5U5r^q>f$=ta?oq94Uh6uVFyh2m%wyHV^x zu@}WLD2_#O9E#&noPgp)6epoL8O13megT5vqa*Rajp3~#hWA1l-p6HlW0T=cS%x=P zVg3ezPd*sl7H4>So8fJ0CT=(5$H-x-hrQwv1%B%ozmlopWviya=Pfl2t|m1NKQXJ} zw^%j&ey#Y>tA<~5*6@SN8h%Gu!%zKc_$g!Y303(yQ}}|Xh8NxP1Ema~STTH5$M7ni W;e7xm?j+!s!HuI}9@pXPwf_&X@=SRE literal 61901 zcmcJ22YejG_5bYc>P~kW$(E~R$wjtYBp2C|o8%%+#kOoowk5epE@zdKbhesRYzvHm zBtQ}%jnI2-xS+w@3QI9R+zM%BO40*AZ#T zga1C3pfN5n3;LQHI~p}MrBWDqz2Vl5aC3iNExKzXZC#E11HIuD8cS#z><{;8<7axc z5o|b3r)Y@u<$Q7{W(_ua?@X7^{+Jj5v%_M)9+8P@RynX9O+LjOn^LWMZc$HCgh>e zE8sNA@eh@3-)KO@E>C3;uxF59_V*DQ5hjHGYg4pRP`L!85`17b?GK*Cdmt z-s+!X`lADf;F)gnq$gSGKg*0SwEA;Rf4$Ye!1NC)zu?ce@T&nu)N`pBUug9gnf`j^ z7d)#?o#Pp|I1}1%t$x~?cuQ&bm$}jkds zQQvLhx5hV_@#)cl566L4(_g6kqMmzAo_edl%k&Rg{k^6?T@8q`|6BO2{u51qy=4H^ zkC;4zmUzPxJ1^4H)p&^fhS&5LTKxgjUvC*djTGsJ^DceR8b8L2Pq&PR#so9I&@z4+ zlg#*fYy1>5e$eWlZu-+LR({`2d(~m)1Ph`4~?a!zfk!_-io9j z#*_4VYy4_6e$X0UV#cSdaaHiFG5v*>@zz*x^3+@7tIha9YkZ9vpDxE?KlVdIjL#)O zJYH&imi`76pRmNgJ+Ho~DSTw?wvCwuof~pfQ&Tr-iG$-ie4}=+D)wpVHCixuf<93% z$;!&|BrZ)&U6kt8^`xZzjp%{p;HnWUMI8@%!rowW!IXm5v8n#Z+{RozJ)tbEYkPjAw5Weu z^3EbpY83AY?9a+re4yA{mbO4k*ju&r@Py>hk}N$veNHFxdkYtBtY6r)f0i+}(NoY> zdL+rWaEIovSjrF1OJB7&m{1X{s$aY(T%CQ0?@ZEl-4N|Bo0XNixjtBukmFyHH+6Z- z%n6y>lXq)L6@irpD|ZzQ6z3yfQGet}!S>F2z-36>Ccvfc09$=lc zwyuSG26ryoTRf|OZJyWTX()lX&A~2g--5<0m^PktFlDFa-?g;z;Jl3G1HpvC#sxc< z?CG44IZ@M>chzD!>8YOa$%kj>H7x9Ft2w-8LD1V0T0bvVAI&H_SX?tMt+T#hPve5@ z?WMus!K_q&&fLb80e?by+Wzq#9$C+q&2Lz^e;eTQg1)}aBQxgY)#tYsm+V|SszMu6 zk&?L$^4z)Y$VqK^lZyIk$IP1;OeknsyY%qVC0M!3Hwu_KKu6_DV>;{xnfUv0#9o!Te4?u z$-F~+$D+>2k+Iw7Pfqn@%!K;wg8f_jAs+?3dSS)Ej`YF<#p~y_ccm4zHhTh%O*X^KuDY7*)ac0n`@I?o99Z6c&xkDSJ;`;U#DZZ+~gS?@jdEb=7 zTe~s~T8pc*(~@_u=+`&XemL%nIx~w}i)Up|)JjD@CZtSC^~_viEbmM!Xf5Bm@?fmp zyR>mTN;0GTvR&)vO~m79@z2VevRvdXSiWpO}Q5cMcc**S4oJ+?1u+2#pk=`v5Vs&*~iA32h- zE-!t>fi`b?$^1$A2R0rVJG(oha3Gq$V1iaMzaf85Bp>?0u7bX*l>W7&s-XW)fP73@ zcA&Tf`e{RcccjEKR!b;og?6u7uzTVD4eJ*#tIAxFua{?S>#ScmP!Ih9`gz;hqUP{ul7D})h^v5cTJL~3t#k>Vw_6u9 zEb}DI%v?4iQKht{7vp^d()T)!FO1cIJ2J zIl*lU>Wc>ISBvB6-CQ#6P|9x2C-fBL%S@{d6#$>m$hUUmu0`E#z?U+msA*TVF*fK~ zawt42d;9#L5$RrExi$~_b8^78YqSHQ_Co7Ege&t*63N%x51k| zadd^|-3ye$7vg*Q8G ze$d<52K}&WNbGNMxU_~(l=WLF`VAZ}5f>iA*XGr0NmzdM zWSPG#*^ce=(+f`2b6_5j7VA%b5hwDa@Dnl${jJ0?Q?`)l{kgYiJciSvptl5yE{^3s?0WB(WR z-VN8`-36YB5+}|(?5DDPna4&Q=Ru_h)p-|`JmW;ZYK!>hq1)IWMSQG3igKd;afxh) z?2pS2M7;ZDJ>WW&+_0)=pE!RcKChu@e>87lnfFoHe=F-(^viifLASn2oF~ous^xrR zLlKl;wxn$z%v-y6Eo`Y@aCmFgPHlAUq@g&NCy04m`PR%s9qG$DiYN3>Y%~g*;kses zVEmgb@{)g`?MTMjt{n?ocX%myp^I~^Trr&S`nTPP|w8hj#)ULDGICWw`VG}uM5V<@EELrQ7fE}o2O4& zHBeiWy?o=Yd^ry&D;SKxJhXdq5nlIkz7UAa>eyDbYvJBqH9X6+dr8-Z^@k@^XRgT7 zv(gV$!@L0SX>eZkRKYw+_-CdspP#;b&yLmE+vaQD{I!%C!JTVgq*aA@`?!v4_cL`LWxw|(U zEra(S2=(_iHitt!`v5jRR_T~Cgv6;W&CQ)5NL#4;K)AOz(h}C#=*TcvT1&V&)ZZ}> z5=DfYn?o&;zQ(2wh)#hV^bCaB8$0?#z2W`vkU%Q^3p{aLYPk*cuqocX#3HP=(cl9rXjM-d^hP(2Iy9zXBVEUo;m7U?vJoq1iUIs_S z6M;@JI(En+%^}zaej_5n$5{5jp_2O&+8bM1dNt;4ZyJD(1iiPtv$3zgqZ?D6(B9MA z4Zei-zQ~Di(7f%?4Z0xj-u8pNk$&OnZE5U>2Q=RH-f&~fAjU%4dVmLez9J6@TNRKj zHq1g~pe#t*vM>o!1uC8RCuAZSz-@T6{shhC5yVamh@gdNR|*f1+3166J$UK|JsisnY_ zh~`Fa$Xao+Ar4HWOJfqHYME^A>mI=4uD0>mrQjiI8t4;eco>i=I7SU|;J7r@0j;w- zps)y>$!#ITLq+6w=-G@~Ti}MRhrji1LYI-9S%AcrlzM+lM$- zR_<*)(3scJ*wvP|v1un1d$wANBbr2k^T^E9JiANo^6%CNQMBJ2SQb}Ejl{mU3iE+zHoQ%;Wb-}fvH5)6- zpz5)0$uR?G_In#Q;mMJ-^x5$b>B_u~p`Pzz&)zK=|2Fq${5_$nDxt z1)Q)vx`90&%Mh`(AvmQqHgQd`whm6*y7HQuEt~2>HRWX$HRYvnMkH61220nKhw?E= zP`A-)+mf>ss|yFIAr3r?Q>_syb5^3-(6%7dX>2sCJZKs6Vu9$D8H@6XysD9JoB|7< zOs}mdlJP&jO61EYs*jM_Q$ped*1#Wr%~sjLpwHkfGW9!23utXdvT8@kMfM-Lo&F%i*&0#(@* zEZra+L;F57DeAx$Lh;c}lhrSs;{1T-KtMEaa!a;QG#>Uzoa*Hw+S1D zxMTO>IBxZsG|mA^?`zZ=xHj z-$XY>ze&L@?4#8s$cR7Phd5%RJi2RPLL@H~Vyn(F@}^dA49WhE8V69Q#iokVP=0BB zX(enV<3>pkYKv1ln3sud!6tUWP#oH}v8D`04S|cE8X`^(4h_%Txr^mdr$5MOArCsIq)5@R!47$mk9Cz%QVwb1H`3 ztjHO<2@~Ze_zyoU6A+NCu{m?1v)UCSL%Ft4Ta?7S8gv??AC?)yFj6^W1tLs`efUG5 zG*}7a=bW4&6Mxv*U~~O%e+#IRp-JgxlWcY1TA@~iZNQm3{Lsm7g1a{1M))OV%&EwM z3kA10fhpN!g56vz)=oe)bXxyFG!kx;%^8|xGw152P#_izoU={N5n)^_*VbTZFahv3 z_H}f3waIF(hcwG=dkxofZG%>cm?~&WQ-4#aAATUUH}1&a>q{ zUP@IXy_gLA&8`E5DmO|7&0P}j*o;Vvi@=((@z~Jb1K|VVu24@S+{hVhZV%)A9v}Yv zhM&&RZKPk=V~2-AOCyqMFPuR`_P62h{ZzXP0G%>5NZxy(sTZ;qhL(A|TU*6X`asMH zvAvQUPF=Vm3Adcu!m5VT=2Q$j`z^oY^Wl71eVmY$u^fqBKXgm{TF3c_oHis1Q_LC+ zb?d@fA2<>@=8-r~&A4`wb{MmNvdBP3pUQyV+Xt5!Xuk45^G}n_{|d~mdJn+epnZ*9 zaCfG^8BUL)5&O~5#+c`~>Qx4E!O1D_vUqU|j~3i#uoeQXDm7abqZAx*wnQdv#c}N$ z+BdPiXF&q$GM;xh<_StFzXA#^i0V!^9 zju~?AD1^6L@WyaB(sr=9zqcdQ)7>G?2}r)_>>un2!{t>vI-uW!OY}K8@XL2n+z6-vH*1gse@^lso+osHJdVQ`AxRfflQFo7L@Lz%O4*tanF zNr;FBXLp=9h-D4*hqK`_1U28vwO?pY2O#d3f>hpTwv$HhK6CbM_8lbsjUZKSD=F80 zE9sttlTY5MhF=*&YAA0~bM{^KJ*0XG_N!akLy2CIM6YUWIy5gE|A%1m&=0r%v&Eg6 z=_Tb%m9vYa^>@xLmexNxyF^<5;_Oms{hPDPr1c-pE|=CP zoLwQU&p5kMT3>K>m9RXFv#X`$;p`e|8Jt}!EiY%+Nh^`F>!lUo>;`FZ&Tf=e3THP- zYcyv!OKS{gw@7OoXFrhE1kP@iRvKqNl-4B9ek83-&VDSdDV*IVt!bS7L|W51yIoq@ zoZTUnKEIeSi8?VLR?t-YMRAgvD0UX)fBXD>;shqITZ)yvr{((32zRcRgI>@{f} z;_P?QI+3&2rFEFI-%INVXKzUBRLk-tOIly!><`j9gR{4#^>xnvD6MaD_Kvj9 z=ImW*eT%dAr1c%n{v@sMarVBnzR%g8rFA}Mf05ROoc&c=7jyPEX|fHlp0f|7bt7m0me$RjeI%_PaP}W*{gAVdrS)UZK9SZ>IQvvu zcX0NZwC?2Wb7>vp>pxtZBCSujHdR`mac!EkzTjGxuyn??>C*CWZHBZAu4PNh z%e9%(O61xsX$818TUwlJbEK8RwH#@U=31__#&B(}w8p8c7yQC*>@=@m;u)-bJ}a*h z;u04xsB)tWnuV7dD#(23Dg$T62{a$_%D5RL#NiD?88tOdlo>(R9-jsuw~5i95u1oX z_9lw?fISxw7<=3->po(b*?_rJ6M@bCaC&4?@#q4dSvv}gHaT7u1sgu$cEE-Yz8!?& z^KeIDQ8x0>Ltf0xkzH-bLv>kT7L{Qc2hZAN%myvF{|u43s(7c7OXPtELi2( zS+L5ovtX6y;~i*xn6=Q^(Zf)O{TD+W_FoKj*nct9VgJQYhy52r9rj-gRe7bxExC3h zy0AkgbsE*r@kTK|#*-n`W!bh2{0!3>L(vf%AmLz#=G*z3yDoq;vNKZv5VxQF1K=Bi&_IC!>H?3boom~nT(;P zPth2BJSwBegJdqGkwFWHZWd>KjRa85P)kMRvKtvj9efoQTa6>*hF>6f1pXC8?n^N@`gEbo{nQ*9FPQ5$Y;VO|fW3hEg*{RRa+!PZbAA zu%Gi(hf~CO){8`qaM0!TR)*yeok>wyRw&6>>bz00vMJHyPIYz_DAqGcx)Bbg7#nbz z({T&NNL>9S1F7>z6^sjkj$3YQt<-Vp%vtRS8MLgdI&RUpj>^(^M(Dj5IkfAHaI7&n z+QUXT9o4EWSxY(&uVX{6cl2S7#zi{=ou6pb(1uXsyIAL9UP0+Y40P6B9XCjI262Ya z-5Ho$$r^gxA5X)B zNBHqHJa~j3Ps4*%e#ybh(idc%NBHqHoOy&FPs4*p`0+G6c!VEM)?oZSFv5=~d#Jwa&FNQkozZmMU|6-`a{)?dw`!9x$kk?_WDdo5@g_w)L(nnlmDFdh>4cA7>^@cKr z8q%UMBM)iOD7<8f3j{UpV-ODeasj7|qvm zwm4LVQrR=tjLH~lCNX3wsSKm;^+i{hj!YC=csg>Ote3-hg_)PSc(pcHtBT`E4NJtL zR#`LZ;16BvD&wdtacl{!455y=Wo2yqOqdI11GTPWEchCdOp)EWMMQU0MZ{7o@ui&#G5e$H8eWO$sj#nO6`vnA5{ z1!qg8^-Io{N$b~~Etl4BI4hLaZ#gTH*7KaLkk*Twt&}x-nX^^W_bO+rrS&_`ily~? z&Q6flo16uu^#{&Mr1eM6N~QHKXJyj*6KCbp`ZH&1r1e)=2m@_}zp{<}g)V1n**a|F zKVZR`B@gNkbvdhG>v8wLV8Qs1-RiG(IorT0G2kQ4s$@$(=B!#;pK`WQmi#$qo22hc z&Nd6nfJb&U($YDr6>&xaXLZu&<7|uc`8nGvtt8I2$-T*(ZI{+4&g$jfRL&ZtZ!Bj! zq&1$iozj}f*)AEE&e?A1%it^|t;wA2k$b0d)+ntk&YI-j8JsmsYbIwca_?-;!qS(+ zS*x_>a@HoT`JA=OxIE4x(zl4Sz0xY+Y@gh_gtHE5E#s_HT7{f-$vEhN-O^gcS&!UX z%-MeF3v$*gty0eVq*cyYzl>YU*?{y_aCSiYHgI-O`l>iPBz+q>80do`S<+T+bQ?VZHr;@=G-J&_hplVx?LLSLIekW7fMpu{ z18gdWOpOjCab79mGhp4PuWDo2mdbKi0hJXSc;dvb;KrbFqTe`VoCGzj?eC2=_v6wn zbHs`RBwjxOTqhex0>E{O#xl(1WkW+(z_J`@^JxKQ7_j)(4-=I<@j%gMd=09QjY)!< zr^vNiVvm5FVVs#{oNj!b8)q0ju#U_4CY-_4$m}!DhG*B>J+QjU_!bnUy%jLdF<_O# zXVUjQcwQ{6@59&{&F7kqNKa3=CEI754+BRmZBe(#(}jNH0^=fB-XY?HI!nkpnad`kpuYd+e2`ai^p%~QTDyUs7TslQ9uJIdJ8`nZ_ zi2}@P3ZSlsC1Np@WsiW~=r?XKZh}(vV*#*k2>=rmJ!UwQ&-fu+M`A?LcYfftDO*te z*v}>yw^~KRVbfUtVwFNZcQQCOrV>XEYtS z$7ei5B?7O*G7*pXS*r0U=JdV*SdUro800gafQwX=apOS0Jh)HcA41u@B1KR8jb9kQ z41jqUGY}GoA|=&!aab3Y3>UpYdYAcnNomHh0Ji zp3itCV7zKP3(GEKul^mJld+e6!#eg-u}pasOoGDI1D#Fb-Z~tX@DO*y`@y%uGH%>f z&e2uj{`T&cO}OkL49BPs7XH@u!wWmA8hca-uYi}b^op0=z`Mj*ptgIUw>i89UW)_k zJ!=NK@GS#dBYhDd4R&>P!%Il;T{)1$T6`UOMOOz@q@t^}8`ez<57d=qF%L5sj2^Jk zXAI8E;H~Ima8@QX%*lj?8JW;9?GhShSVF^ON@$o$2@Mk|p<%KlG)$F*hKZ8UFijE~ zCP_lW6iH~9APEiABcWk(Bs5HogocTc&@e3$8YV?T!<0y9m=FmK(;=Z@G9)xig@lHQ zkkBv<5*j8!Lc@edXqedu4HFolVfrF8OkRYBsf*AsaSYLq6iHW6ro{yA~Z}+gode!&@eF(8m1*eHz_|%NyIix zNQ8#zh|n+@5gMiHvXqbiw4U-U|VG1HNOhAN&>4(rT`4AeW9zw&!LuizhUtdTFxe0qrW!)SL_=tpW(Wp zm{th=6{TTHA+}*cAv8=Ugoeq4&@hz{8Wtuq&G=V!6A!7jm-$3nwmVWDBA zFX%D223F|rD}A2Q=PP}I(ibXykO z*DHO4(l;u7lhQXUeT&ktqE)m5*0Tx?t67DHwX8zJN>-s^9jnl=idE>_mA*siqe|bY z^j%6HQ~IY$->vjLO8-phdzHRV>HC#_KQ4{gTozEB%Vn zuPXhT(!W#sb)|o=^czaQsq|Y)|3T@umHwmB?+{zB<5rN)(_ zSRSqu722b;uC$?ag3?~4eM%=P?N>UWbdu7rB2@6gdQhQZHK@?A7F1|h2`V(K0~H!p zfeJlV>2XSrS9*fd6O~R=I$h~WN@pmYsq|!}rzkyD>1j%5DLq~38A@j>JyYpfO3zk$ zj?y_w=PErHwf1B9q{%#OK1}N0fL4_=9sV)q%gvZ~Oe^>?m>%OzkY1PuFqUMz1#+4U z(H3hj5zxy5NMaYhoW2Q!7l&< zLKAZ{GUp%Dj?hKq%9z;6mZ%+4Lqei92o|2KiQ0)!n66IfgQ7{vIs}e}kkPOcn|4Z^ zrhSzzcX-oIjUA66O*=K#w6AHWt3G8mZSFj1+Szmw!<%-7Dk4!k6SF6p_H~#<>d_{h z0fn6j|GzGpbdL5dRbW5!!9T`Qa-qOYj+Gg8RyQMd`$bP(*p6t!$As9%V>|q(=vK89*q_ZCt>u2go5wZ?tugQ z1^}&B?fdELEf*yur~{~J573!^n69&v%(Jf(vxqyiM`^|(^-&!KW)bWxqEUBfk2!19 zzaF1d-OJFqLW$I8|Key?f219;tg?fzNx*X z&LopM(S6&|(PiH!!S6T&pGShekQOoBgf2EK#@f9MQ+DGC0_8Tc|1{IN6e%E415C#PId;qkpz!&2EK^| zr#b`QOoGQc1K&b|$2$Z6fCNu;2ELU9r#l1xkOXHq1OJEwPj&|WF$tdP41602&Th1OJQ!FLMUImjo9&1K&r2S2zRTPl8uD13y55i=BZVB*8&v;D<3Eu1s{3Hpkbq0Ql1aEN$ z{sjr%<_!Ea39fer{v`?C;SBsM61>Y9_}3&j12+@M|P^&>8r5B={s};MYm;$1Ajn*uX6_e7YV+>8TdmI ze3LWqze(^d&cGj$;9H%6|3iX*1Q^Fs#TYW`K7&1Ak6} zf9eeU1qr^#8Td;Qe6J%gJdC5-e7`fWMuH!72KJEPhn<0S68xw$ut9Ai>W%11FK-=bV8#34XyDIGF^$3=*8+44h4Zea^r$NwD7;coqpxat5AFf|H$r=aAr0&cHb& zIMo?AmjsV>2A)fT$2$V+6XMkf}(Ub`;C}-1@J{Od8XiC2e${d<9$pvLDO_}V1axP6d$_3>- znljY|<$RiQtP9EoH05{~lzBAeL>H6`Y07jLl#6J}3>TF7H05L$lm#^9R2P(sY04}Y zluKyJ87?T7(v&k@P%fh>XS<+WPE+Q%pe&>*=enRQqABOQpj<&y=DDC;NmDLzLAi>i zEO0@&nx^ zHW!rJY08KT%6gh|p9{(cnzGXcST z3(5#hd6o;xy)@-HE-3fWl;3ti*+El&*9B!KO?j>h$}XDnJQtMknqT4-4W0{JQ1;N2 z7rCI^Pg7pvg0h#UyvzkE+|i?DQ|Z{d4#4s>VonVn({6el&8{^KXpNQ z8clhR3(Bw1l=r%z{3=a(zYEH*(UcFmpgf(XeAor$88qdiE-25WDIaq|`E{D|2^W;# zpedhnLHSLZ@@W^8XVH|uazS}EP5F!q%5!MSXI)T!i>7?e1?9JC$`@Qveut)f$pz(i zY06hzP=1f5e9Z;rxisbLE-1fGQ@-JX@;sXIEf-Ho*IZCuM^ox9D6gj}6I@W&rk{_~z$C2QLWSbwcgU6HLMf#&ewI8#CCy?L*vdvG}!4paFViGJ~ zB5i%QavBLyqE;nkYK|OUP6LvsWuy4J9sGxt|LoM zw1bzC;4Ngy0Xuj(3EoPAxgA_cg13>?PO*bmlHlzmc(fh7iUik_)gEI9uO`6_WXa>~ z;9?TIg9J~ogHIsAJ4tYw9ULUVyT~?AvV%)V@NTl?Ogp%g1cylQ6g#+#1n(iMJm(3EoSB7u&&`N$@_h+Dq-=8WP+=f|uLDwIsNc z1Q*%CTS;&i+2&!N4BSS7yGihBd&%2La1UAS6YSu661<-*xx@}`Ai=#PxXcdTL4x~8 z@ESXKCkgH++dS+$h`UJe09o>Sd&#>=@By;qN;^12f)A1$8ZXv;kN$_?%I81_1CczDMa4QKuLV|bN!EGe?6!JLl zwu9SA@Tp|Ud+gu{2|kT1xycUROM<^bf?Mq1eI)p+WVKuE;0_Y}HL~P(JGhespH7y% z*ADI?!Do=*4m-G;1fNNQyX@c|0z5|hh4!@iEg6PSA>s!Er{&gHJ|sWTHY)cXHoZRg zE~EFT_SD>mZ(!cJ55r0#4I(G9%-BcUl9~P)o9JVnGM~|Jy&WY#eJk$}Pg9?78>9U; zZjtZ_H!Ly}iySzrJ^Mc^@|Czn!bje)$f;Q5fuq{X|Dz%`qdQt;(zEcDM)>MoU`g&z zjKg;tr`~0JHTRhD4fuan?mfmi^|^N%-@eQE?os`==;pa%^Y-ZGd1CV@z%N$umx4!< z-DzC;fN{=I{Vv#h-A|00?=*f8-Er#!#*dEbcgr0=`H6AY=&5%aci(B;cc<~7CFbFy z`n@vd=XV;9TXsBoRDZw$_#ue-)zFfEElPd_>i?ViyNur+)gO~F)&d{~3V0&kj;G@7 zcp7#v$J_A+ z?0}qGsboIiinrtKcst&Sx8uEdJKm4C<1g`c{0(+M*L@y3!wb<42Hp1gqxwIgkGur# zmyhZng83?#uN~F@BZ)*drwz*{v=sX6CuWQ{PRM8R>hpz(_0d>^nIUoL4UZX;5QoKx zQv<^bJEHyNgkfOl&<`Iq5@n3_Ad8-E1mf-Bvbd4*W~7)g@ftQ-hFA+0y~`M5V&mm) zoEZ|2eu5biFK=n_YB0&fjvk&j(KC!ph&f(vr^py<6J>6v#oIC6QgWO=X=Ix*@ftr% zhFA-hxt(KTUjJonAqV-m)H_BBp!X488STSl4VW28mu$1MA9XAeLQd_?10OF zIN#%)4b?KndNgE*+Z1m{O}ygj;_cWPZ^!m{I~wBc*eQ32CdE4>yW@fPSiteROB2LI zb2dCijvy`Z3TQP8fLYt?aR%=8c<{aPc67ws(G^?90pEJx4KwZ}HimJQ#gf@VmcokJ zD7K5GvIF3~n2lw(vvKSNHlF>RO<| zw$Xbf+vI(OZT7y)YJ3{2^-W@1eFbcrZyVe0JCW7<&See0JJ}B3OKhj_Gqx*nJlmaE z$U=!VY)|3=)|mKh)|7Z7YfgNSwIsgG!igWSRzGKL{+X=ZU%?{&Cbrjq2HWSqnRWOd zW}W``SXaQqx&s-kC$N}Ve#QirsGl(j#vkEm6u}4QIUI*k%nwIlEM(sgnI8+kj{Gbg z^d!)k%*!Uj4}htlr-7ahdItRFdI#_x<}=*pr&GCMCH~){tZwT>q zX7QC}b{@QMm7R~`0u&dbxCq6?C@w*9DT>QbT#n)j6j!3S3dPkZu0e4vitA8ZkKzUt zH=?)+#my*gL4jWhW%#vEhF|Su`1MVOU(savHB5$IwPg5pN`_yVWJgiliQ+C4$58wf z#oZ|GLGd#b_oBED#r-HAK=B|7{8l-82(5=vJc8m;6hBAt7>dVHJb~g#6i=bRPo**Z zi32PS{@WS3Ijy~3NH#D zibNEC6af@TD8#Gs#VhZ{tLw!p=*6q##Vg^(tKG#b+QqBZ$0K3_iis%FP^6=ngdzh) zCW^@@mcjwmrl2(y#WWOID5j&Bfg&5lOcb+F%tkQ>MGlHw6mvnyPtaFr>zUS|ZDQJP z7|*ngXl+Gtj`l6aaKQ)+Ovf0*J9Z40bTNEN4+9iz;sOU4qCntk1%|5*7_J^*xC(&b z;xUHz>KNWbXLv81;XQ4J_of-%GG%zvmErwQhW9ZU-l%7I^O@mIWQO;18Qu|Qcn^x< z%{PX(?-<_CVt7Z4;XO5mH<=hdglG6Lo#8`qh7Y$HKJ8`r)Ry7XSBB5589sYv_zamX zMS)9*7%m-PxC8*kT-e0*c1+yfT&1mM8h&|RdlS|KiWe-4S0d|axS5V(5{e8InJ6Zs zn1W&|ifJgaP)tWL14TB9nJ8wVn2ll%iX0TVDCVM=hhjd81t{iA+q z9bZML_)62&SMt5FoAH~~cvMG1;h6lEyNQLI6+ z7R5Rg6)4uD*npxEMHPx_6!;1t9bej`<7;+wd@+uWud>nc_xE;MF)yb6kRCrPsnxr zqi-GmOk2l4tk&^Qp>_P@WgY+ASjRsQ*6~kz^+PBIQJje4Bov2HoQ&cKic?UWisCdB zUqSIz6kkJeI*Kz;oQdM=D87N>n<&mgaW;x`P<#so{t1$fe>9}ypZVzchdDa_DUFVQ z{G#KZtLXR#COZB}h<+i8i%?vQ;t~{>qPPsjGKD6hA<5D~cb25KCAYJ~3dp8iC=e0*0#t7(V4^_~e@56KIA{k{Ld{XZR4F z;q!2YPt@57C|04sRaFdEgfU#%1(P2Txa^YQnmksB0@uhfvDR%KOt)a31bfB$$Q~S} zeyu&D;Z09XdqI0q)8JmDrd^?3$+TOwA2RJ?9KLQs(Tc$xXq|%A*R<1_HlQ6~+U?pM zOv7ua_PF+hhPP}r?E#2mxLlUu^K6FCr5Qe7X84?#;j>SM&oCK2i)8rtm*HbvhEG%( cK9gm5*O=jbXD04kmuh9q_!CS;^aRHKAKf4>d;kCd diff --git a/target/scala-2.12/classes/quasar_wrapper$$anon$1.class b/target/scala-2.12/classes/quasar_wrapper$$anon$1.class index a8c98fd60143298421eaca2390ead754600d906d..d279b8f91eaed4022cde32c550d4ddbb9264d7e6 100644 GIT binary patch literal 7920 zcma)>d3>Bj8OMLKn{>O|Nt-5Z+Cps$O-q_m(x#;?z0(}+(v;RFr4*6vX7^39WRLXS zccB###EOWBfQX2Q2*@o*C8-v~DvF5rfhQiQc;GFbpy=sP^P9;)KdoDAaN?SXIom4KHZyf*Fo{s19AxspQ z^Z&UJA_DaWSYUdQ9F8Z3;saLW=3Fk_7($J}6ptx{DFW5XZs2xDvktjBx+t}xQpK$M z?OcXly}3Q9q%#=8bauk{G=XrkZy;vpomiS3*IleZTmE1+vCGO^&RT(xYrfD*kS;m6 zMY^VJCKXF%ol28i;i5@Vp$nY&KrEG{dpci;#Sf%7rroJ*B3(#YEqsh62IJYRmCn0Z zs(;L7LcUM?hLV}M)+V~zAjg}2DsixnJyXtVu&pisJE@Fi>jqEE=lUJ3)>sD|c0%4x#B6K7KyA`W#GG^?#@X7R z$T~}pPg-_-QtREtV(~hq8)N-O-$X2A;?nH={(!4MyvVaFxX?41UK6_}`iRGQR zQ(#3WbGU~K6~)%*gi`jCb7cpebwxrkm-^gT^)tDoRm!_Yd%9UEGLq>_u@_t)&IkL# zm}AEiR&02P6Sh2UN{KOdN{6{!WXF((rbVSbuUHZiGchZS0J;UL9Bx1YGrPy{F2zlX z8P-;0qLz)s2{_TkUq9Zc7LLShyv{ZDO3cx2XG_f0+BqzUxfz#^#5|njf^U#GS!-{U zn6I^%M5ET?5({(zT+cHqGpkrU5({yPn^(U?llC5zSfsTJB$~CBmRPK{ti-8W8$LVBiS=5$PGW=B-YcA)Y?ZRy0mtO#1^f6bbN1D&N+##h`Q~%N8(KFeV@RDb*XI1 z*}yo`w!qxtp6wIDLU@QPfBTM(-QAsy0ww6|-}>{IM?bwV{usfF_!Hfu zT_tykzi7vo1R_0~i@8YrO(*}oVsN_BDV{`=oMr#49GqgZYRJoB{0pzJjE?PX<;?!0 zGkY~cBd1DzsU_vzHzatjW!2r9ieN+pM3q3z&S-nAcSmnqcPx5VuM`thJ|a|cYTQw9 z)OrzNZl0wHGnVRBNlXfhh>#Hxaf>c3Gqt%kh6E3r zBdWYYqM@Q86&qVf%#4UxZtZKmI~d2JT?OSS3})6@g-oAi_s09u4AXVpIiAP1$UV+OD3*&Mxyut{tG?skG3!iR;R~g|e zyzojRyxIs~>4jGr;WLczRbF_t5nf}QVOM+MHAZ-?vE*yK@H!*B&In)Yh1VP5^+x!5 zFTBABZ!p3)c;Sskc%u=%(F<=f!kdinO}`GwFYaADia#8|pGRVC-2aD|`YO25Ld(uA70vwb?@YQJ2s@iScOXSm+49yjJRVEFQ;V@hp~zSI`oe zhNXceSQh9)YaoUdfde=_a2-|#?!&6UlUN;i4r_wIy5KCV54K`Ma2qxTlh_oz1Z}|^ z(H?vV9l@v38GIgH!I!b6svcXbPDQk;6WgkGqPr@^&z|l}d4t|L$6m_0hvGqTB6sw; zv{ef{SX)amj}OhkBj4u)KX>qt zuM2|L_|zEg1wW9`h3{OvK6ec~8w-9&;3H3ryaRUsc<>b9>$l){4{8j00z4iGen{XS z&pLu168OjSmf$xV{_&PT@Us9l26n+u0Q_T=Ru>n7cl>wrrq<1mQA}_a@Q<%gLNv0e F_#chidNTk3 literal 9177 zcma)?d3>Bj8ONX5>}I>$Nt&iKz0)ggle9ERPfB_wz0#&lA!)IKESudo$&x+Nci*Kg zh=_oIhzN+tAp#;IAVMH17K93Nhw9@>pLYYbBRAwB*w9 zq!pwRK_`s$Uz&|YlTo;iO%772pk;Y{%b|f}B9?GkGpT_@(&`v+5}9 zX`Gb7Gf?*2M1VI61XSls>X$M>-T$EZ= zseINwb|wX{uFPqPxYHM;$!LVJX@WxW?%s%}@MMfc9`7 zwL6!M#FG6H3uL+bU}F;8mLHpdM=DMTIf;~I>-HU&&Ga~0Ewc_eX!EQci`doyK^1W; z7IBif2wsk!SlVekKB?*Wq-Dn^Ef+LS^_Al`+=N1Bx4JEfz8Nv5&|o8K99=nHBkmx< zW9AJRbY(1KTdLnHQve z|9}(8I#DNwik4$^4djZ7Ez=2w?8`Hw4m#_ignTZOG9%SbW#U#L?=tP_W~In*syl&J zaD6av>~kU*T`?;%(2ub(xiH`hi4pe=3So9ik04dGb%i!BdIKd*rD-AZ(OyA*2lJhv zsqJGYv;3Th3@eH6wC9Trh zM2wI$H0x)h8uw(0-qi zv{7rfN!p~fPfKdi+GixS>T*9TX|qoIoTM#UyGPPit$kk7Hm!X@(sr#qAgN7j4@%mh zwINA6wRS{OyVkxaX_wX>k+fTDUy{_JwZ|px(b|^J1N&iPOmI+w`3<@_IqgjM_rcV_oq)lAfg(!{n#$VXDbL zP+NK+=f>uj@WK^Pov14L!w~&|euM_f1EViHs2{tN1!Ga@Peb$*`Wa$AmO{zHl3t;% zFj9WuK4<~jjL6koxHIcqFeo=Si&w*_&#wek9$#vZeuMrmAo-PrT5+ff{Vqh4==XTg zJezk3(jSoHaioI&7^2tdPlD#xwvEnsd2s9s1^!d$&tdq#DM*}#aZuEuh=P`#jwTy= z61MFm8`L@n#9!%eVXC6P3u+i`72bKY{E^A>75ZlwkMu9h;Q2>#EkXJZ*AQxTrk?4o z5S7#a+~zzZOyxop@vc))xGPg`Dh-MNf@pi^-bl;d&Pdm$ZGuW_>)NCUig95IiV$Xf zw39p3#Q3l%6%y`kTMO<|lxs(<7Q>w_`CO!!sFSfmEOgG+WCBa*cui28P~18BWcNWt zRY*)0Q&7g{U7JQTo2E0H9u||`p;B0@cH|s2*u^Z&e1+Z~NmcpH4vA_pCoHO6u53?R zYox2AYg2oqZFiRx^L4g(zYA}Vnln+ug~e}=PE`5ThQuOK=Qi}sVQ7nyX}+VBS5TaY zS1aGrMe|iqG^nOkE!h+njlx|6nR66cyHy472?%`F?p&(dvb&<)Nrd#u_6$BH_C@W4 zdq0v`vCDG$GVwi8JDRdE91)#m8&vtK1?ixuvF=;0H9U6pgk&WVkd;I@ zRuaKjNrYl05r~yU7*-NNSV@FnB@uv?MEF$_!BHDTpMUHCv< ziMs~e3CKYGL$vRHC_b?Y*HV=j604z0?Leo|yKpDa&HEYnbQ2D<@Ju>`fzLGI@hn`; zmVA~8OBSBZ!rdlZ#=>(b##Gxf;R+U>$HKiPJduUxvv9(MD_OXPh5Jo-5(_V2yDDYE zRV=)aZS9N+PhsIjEPTL(r?PM@TkWg~Ph;Uaw&a`%PiNtJ7CvagGgx>r3m-P&nJm17 zedhB_coqwv$d-J*30Jf5Qnus^On5d6H?SpNXu@+?xREXSA`_m=!c8oEi3!hR;bkm* zsR`Gx@NyQu+=Lgf@Cp{b!h{#H@JbfG(u5bW@G2I*%7p7!cr^=OZNl{|d=fiIt~KE$ zEWCy-`8pF`%EBkJ@bxC#z{1Tee1i!$vhZ3KzR84}Sa==X%*3i&On5m9Z(vKl)r42D z@J1HC-Go=N@Fo_%!-Q9{a0?6HX~L^nxRo7YcbV`S7T(O3e76ZVv+x!czSo4;vhY?G zzR!f$vG6t)zTbq`v+#Bn9yH+%EZoMz51H^r7T&?a!zSFq!aG^`VH0j;;dT~2YQmdY zcoz#lYQkGscsC0_X2M%pxPyg{nea9i-owIAnDBNMK82oSrlF@ycn1r2vL!!b!aG^` zS^6qIWAJrT`X~kPol1dw>j&vu!}Q%F^nGYA57N(v>6bcbn0|eXemg|_wBfZudZS|Y zF#Tni{xMAdF7o;B5S^}k1Pu${s6qIL=*)KjpY;xWy6YbirTZ5Ti|`RqHbhqbwnE+Z z=5Hsd+eH1Km^$J=11Td_5;Kp9(jn^is%xsK9&fv(0EC1{$8}wjvqb^?A z9~^ZFc;s@}s|M$dvK1RW;PbuU3(%@_2T6^C<6trG7-1Y-sC^r`QE%7(0N?X#TdyDEzrqGg-b+oi(A2pO@sIlZS zYAU&nmX{o*6(ujw%97V;l|MkM{nfO_-$Kp)(`l{Wp>_T%X}$kW+TeejHu_(p7XKU6 z8VJ+ozuI{;lC|uvO_8HL}5mXhqM76^Nbg(_{Pn zxrz#iHMprqI18Z>B(CLXfQgWkAWwj-f}8@0aEISSaWbxc3Sz^q8JZ6{tc5;B2y6f% zKnfh&Fs_CLiNG+x1=-<=%Vmz4sOmgzAGe+n2P~ zb~S}O#3d0=Q$zI>_~#+2L^Q*{JhY{&p*A|n$9T|Xs&3eZwYpGwTEU)M6KT58S0Qc54k0Ec}S8yJ}D4bmYyJ~^7#BM z=~OC^Q`Ml`rQ}GGyEsTyuWN>!uB8`9uG#t0$n>F7z%|;x1?}~^y%FrebZ$=qdxDGm zCl!D_gW3HlYP@R{w{Jwu9`A9ug+CkvZ+OzP*>kSV_-lYzIpwa zj7@R#rOfpBpewyl^10%Rw@#ifO&uLCO`5(a?-4(0WGU?TN_ryFN+7i#4-LY=%>!zvA|cLEHd%X5AjCM%JL>wOJ3KOw4gk_ zt6~{p3M2I{ibl+zYY-syr)UOZwnx-Sgaq1EK!ay#8@=;*zwj znc6{{{X>_Te$tv5)wl zhYw!RvUY0S`jN9FAM20weu2W=`o_akSGKO7TDyAkjulIWsBz1AzZAJb<;O4&V%}f81=Dso^L9;hj&N817|lk z9`1tcaa!&A@-(Gdp3C#IT=Ez9AF`DWo6$WlKXYu^n(Wqw()=yb2-d!3Qzf;r!98ay z-H_chQQZ<(Af@d)GBq(iKIoC%p6nenng_!`kRa&|4y5}wWNn&P-ZUf0rOMs_OROSS z`mzO6R!`g5kW%823j!X4*nsgF1EFKPLZunoN`~No5{;9w)dx8JInF%SP;D!m*o_q_ zg)ne=j0U8x&4&i8$*E}^w!=MHo6$9IQRV=wf0$8!QG=&-_0-T}Z|1hBUbI~w!&3Gl1^WR}?eg!EBEX4TG1$s9Xr!?cad+_ei@ zS7p_%92xNY-FhMf;#-2g9rGs*%I+=${IYdZs~1d0p48-7+&^t)DWWs(*_yd-W@z!@gBMQGW_Q;^`WV&EN=^>`~6D;2M>;qU%k*J%ZI}aWYW4^Z@jAZ z%Sx6b{c(U9v!lCgeb$y>|FpQ#0as^h|Flhr;HB&q4%XiG59B|iGEy~ny3<^9fWE;;1Mcdk%8fqFk3tF4o8k$07 zZJiCREgcz=hXqZ+jt&n=geQd9aUPN+kyJsjL`E2qZNZwxV0|c~uD!LnxTUkQwWI+a zX@X52k|L3$C@&95lSp#3t3*a`4t58pGzDAg;fbibwJ|hhNvLyEYwf~dOKnrABcr6X zwXv(sLk0ll*sdO;NyN?lCF0i~qB7dMYnmE2)wXAN$PkIdn}{44-7XpXj@bJ~% z%?=_E@R_Tl0~|&&1pN>m@R~!-Q}`2D2B;n~S|Z-C%|pgY#0AF^=^y!=mXQ%`X>G~K z@{kDctGoMJKIgI&kgPZVPSdILSPU+Dk+0{*k|SCfz?%oMN2CeLg%1m!9s8j zR4lB@k_a^n6~$|y^WyN3s|op)`Bq@#hy&x16*v*S^D6@js^*uK6asbgn4_iPF@BU? zRa{zFw2BeX-IyVZ@n>QBF;)~l&W`##yDIYYoT$%p*ynLrEob1%UtU~NSQS{94~bF< zZT0GgRmIaFW6guA(m-YL3iupM6;(^iE3xzD2bPyqLfW!i3ltO-RaCIPnJTbBulDfE z7T9tGHek{tHdkPqF0jpjbhGj+Dh=e96ahnl6*vm4z*1lZo&qZ{6yR^S`a z)+K?8#nJtVw&?yuTXcV-ExJF^7Tup{i|$XfMfWG#fS<3hpkPT=exP)5Reo`01q`9w z!1N@pudXbrT3K9(R~NUibD&!|Kv6+~;gZ0D_^E*uV@LC?5gdbGBfL(IQM#NH0TLXe zyl6pjS*by(B2ZXv>g-bHK#Ye@KCy5~peld)d}A>1^5crCVz^+baex_*buizGD!8O2 zGGKn7q7p9L%A)e};Sr0&dCrv8B&^Ruc|V5eB@9 z{ZGisUE#Ea8)%%e z6#c`9%zE*;d#|9Wu+z1TBBVR1*L^mCD8w2 z2R@(~Oe!h^l`vBArW;W>66-BDx(!X?h8rgit=JL9NdYQL0|kqjAu{)&NrnMi2-O>h zVbpkTWY-5Y2ONxk<43%Otnu&}kJGc9d0VoaL-D@g!DhxYS3Tpo&NALxJbyXlx1P_& zfu7ICA!jyusd9LKG;@HpPnisN`s zD~{tmt-w=Y1*QTkj^jNMa2)Sx#c|wf#jz8|@n~Cgf1+P>f1)kAKhYN5pJRKXaS{cOnnr8hH0I&@$^;SznVCD9mB`?zaC~uI-qlhG zJq6$YK8K87QdYRUq$mSk{HV~FsNa(xyyOe`T1Q;L+FFS$umbUh zT3Y@uAWO33g5Hr7ct(J}+|*iI5Ukl0g0vqQeNuX4H(Vhe9s}-!daoY`yr`as(1Br7 zBwvq|Ai92GY);tR314va6p(z8l;Lxo4QM?te;CGHoi&YdQfg!v*!3{bdWOMBAIEFO z*nyF;@Sz?HTF+RxBe*)7JL06Fkzruh!$9j91~(18N{odUCDs!IAL_B7^^Ap^i>tG? zAx?t#CDt&o>tUev44Y|IiLsfHvGAcD3tG?ESrE(Ki@=M5I0-VrS}%O4$AXrM=b2w> z#+VE@W)JJ$hT1p@T9jzbLHICE&o58~(NI}L02~_upb7#oN7`$vYJ;7@IB9NFG<;}8 zgDQxI1PQ+ZYKfEZaooxmJ~seB6#zh%#Mf5W^EXIw5`0CAh{s&h+Y7279?~VDJyZ|x zt@I`=i9!Ge0|8V40(7x~0OLq|oKzl#01gHMr~(AYA2)IcK?kgi3Wm>&U{D3YkU;Tz z12BGFR6M4k-T|Nr;vtEA_?B){5YA#d{&pKD!H={Ny@>g!g9vjj8`Fwk(zUH|Qe9*? z`;>>H+LJ>zWENav5ZM?N8O}cR5kx{(#luapr3zl4h2o^PsQ7UHWef8!8nFIOe?x^NfKNuApPD^y_S@kqbOLmPT@kb-0@k2c=Q58gE%3<^-m`M{S zJrxxmPRMD(gq(&6$p=gJ)QHDMeZuUU23bW}eeI!O?e+$^2fP#o5l%sL7Ep$K^5L1P z?&_$5M-Fx)dOZpxoPN`U={F6M$%iM*3i3`ANI3V1aK6UNn!_8LAeeHDp;E_!C5D!_mQqwU@Ba38D*Rkbz32>sV6h;TOM z3bQd6QqI>J9%JE0)i?>hhgsW#J_ZkAhUP-j`7IzFoiNd>BTkm0aKdSd5rXzW-X(Gz z9F&lY?2f_+XKAi5OLH;pTJ^COpBbtQHt+>0qE+EkWidUTvvVQ$qQ`AUDLD!#oURxm zXcpvO)VR%X`bFV{Gd5S4vAK|kDf}i<-QL*NX|`-o6i_&IF+@NJGBUX~R8!U2)Kvvj z1M6y9I;Y0T@cVN_2Zd8OSD3=nAt|F_vf^ZTH(`ZAFFkuu?a5|3BxW>BcAPvu3MQP% z7$AUw)QpD7iIXQs!Gv>pI;fuJMmC!fejgBf!;}UKBs+vR8P)I)p50Xp z07B!&8NVjajvY$nx$?XO;+Anxn%c#E22Y5IsUeg&c$A&Q@doO&}Ss0beTtHpL>TCxqNq0}ZwY*(1xssaz#*#EK!K{8o&ry4I#z7;Adi zGN@e3L*Ts}s}{cy>tucCZXSc{ChppxH>-Y=;h7oL_q}zg-bgogMgyF07eMIs8eq`e z+}_SjOjs(n%5B*AEzr>R?ofBAr3&7SHgs->H+ePiHPwSJJmB6AX~XSIPwnXnE$!w| zTj2_d_`E&@;r?h71RTP<=1>4{@2+l#UJF6X+^uzW@bw&W&oqMX5ghzTcCT-TsY)T8 z;fQg?J+6BG{+L}k*^tC@58yJ#>?4-GkwLOGb*1bpM<@CGV6h+4!s9l?Hw?}$2@)eYszuO?oq}Hcx3`VT z*T~mmw_gV**6b5rExVjTH8t>Es0JPrp#y61Vuzd#8zKE}=2z-1raL@0G53Yxa}+BZ z1fNCS-z0MMj|3IIngz9*%@=%zSGtVZ@5Z)cH+VWi@X9w-Yjy~4Hk`<1f)go#j8$D! z2T=KL`5rt=yV&Iy?*6Lj@Q9Bis(F^c0_S8eKPUH^?wlNRw>c&-#yzeCy)F~34_Chk zn92{z4`BlzW{ksQW)+TN@B^#y07>x@Pl}f*$tBa{i7dZL$xJc}wbx;AGNyG(q#r!d_MFj4NgkPv z&ToT<;hfQQ$abu&t22Z@Y6J5XRDM_fl^6Wrr)&V_6Fs9rxitfRg`GnVLeSqbP~B_= zrSgXy4qjil`BYK(audOj&l06%E}4f=@Ut;IgfL?y(C;}A{E9phnwNq9s^Dn?e(J5t zU{j-v`L$IUA$aKVkBgX7JA3>JiL8yZ{fN){h(5FjEo15}XM~UQD=0abpR_+w65!gO zDaq&BUnnWy+FvOt2O0H>?Ea%!_N>*@fC?zYo zHk^`GTuY~9HP=Q_vW9D;DOt<4v6QUi+IULVb8R9e8@M)!k}9rEp=2Z1vM331Er*h7 zuH{lv!?hWd)N*YWB_Xasy4G>+AWG`FHjk1`TnkXrz_kKOHgm0rl18pAprnaw#gsI2 zZ80S+Tw6j(E7!^>Y2(^5O15yVf|7QwEvKY|Ybz<~Q|$&p;!Ldj8F>!9Rlu60pz z4A-_&axB-jQ*s>F4yELHt{q0n30ymZk`uXh6eTBd?HEc<=Gt+ToWiveC^?mDCsA@5 z*G{42bgrF7$r)TbgOW43b`~XPaqS#R&gR;Al$^u03n)34YZp;+9@j3RpatGI5qU27ly+X-dTzid@om_i^lDoO~7A5y^?Hx*XaqU-> z?B?2glJJVR(X5h=Qf>`5THFTl}U>A@?F z=@xFlL{Sp~EqYx@Y*0397?+FKaxv;hGa0ZnzZ1mYablJoV5o;hqzw zTEu!5USYbZhq)gtbKyQ?WBKT-Ut)PiE{frv;{=%OxzReu+P-U+eb;RJt~vHy^{%qh ztX%u3)9t&?;I0!6(69R3@PEZw?^}DwdhgnE*8A6TM)&U&DYkat4ujI`2THH@`OSLTH;!dJbHF|Z|0r-WN!yJI0xk}~${P?N> z?$m1!;|ux&xtI?ry`F^dIx~(Xy4~_6W%}|n?k2il87t3<3%QTz@yYPPl?mKSc#^_v z*tpYVL7Mflw2cRdnxU`K%4RFxxSQzY>u%;kIPNLRIjg7fou1t9uO}4R2!oQEsGitST!zTwB$~V>_yMW)QNGf(b>qb7?-2IV3M;G z`{8{o@_r{i&4!B+#Z5OF#K66X}Ive*8I zx`p-1KAd~K5OQgWN|u$V97;GYMlVpc?;7Lb z)4C)R-x|bt_>6Xq@$eb#8sp(J+BL?*XS8dKhtFu&7+;>Ot_S?`)YCb}m#3c2F}^(Y zbk_SggQg%ahd^zYoOt@)YfAGk+1)X8xk9&HP1I zoB4~bHuD!AP1DR{SV{@|J4tuLCe5>n?b$FpTJD;LqNwA)rGZUTs$Yti- zPjn|XSD$ki(HXZaO7FcV!fVxg=M=ewo%^N0&*#RB3Vk~(N;1hL`1M?Yr6Txo)Yev% zj3<-v<9+@hv@ry7AU`|6zLno}Vv`&FoL6w)4SG;7D@+$BPF9ELH z)ZV%kCyjZO*S%z@@~W4NKo=j|->a^x1^4aB$bx8`8ZbtA2c|ijA6Yi;!nqAeQEm1p zzxFEcVMwwW!Z!CpXE*NvkMdiu@&Wox43jd}B^SefYBfRJ2Cg#L4$H-hw$+5#u5ca& z<~j^F`kX$K1YRLb zYP3urXNOezK_!r8ss#Lu?&sHsM|D947`7#BC`|Df+ewCBf$E+TfB+1c8%^V^(>$7g_U}qNy>sAH&J{8to1$ylLpr)z)ylSf2 z9~wP?4;Q?t^SfGVFx{s@7k#8^DMV5S!Sp%);nMaHOo4(v9ReM#PrT7>tVf5%t3y>- zfHB562{2QgZ_wP)+SOhYYG|ozol?Qnl7^O$M@^3-@vy0rwNv!g7UL`$m%$BNctIlCkhm}){z`ci z6E_FW;k0Ds(G<`JQRRK*3AD}x>#Stui4@`jE1AN555nOPM(8*g%h=`-{M?7rS>HNC zJy?bPq7^ltl6P=l4_PgQF*NMPd)TAShv9-Jmqca>&dLGu(mYWM)nczi)kQk9U{^;7 z^TL|L=6wSCphR8bRraf;aECF@70w^_s7oyt94|a-Ih7K53o2ox%cyCE=y!s~?95Q#=DY{srfT}Pz>{KE}Y8p5@W7TP#T(W6#V zDV={-OQkVftE19Hu5F^yRIY7?bu=|NyE^ig&1VNwwMlKplh;C}T<+gSr97^+Q|TbC zb;2V6PnvFy!f%YQFp=$|33qmN8{8sQxbhMsKJuuCf(h@zxU|2$mQ6y(uoFQYpx7ms4pYw_Qo45ZA7z(q^t*3y){~Mst1m>1|1<+1krD!t;%K6WliN z$u9hvM}>*o{@R+FX146LwL8?_-cTE&>TOu@t?KPa{dQOgSnkleNuTAv-Byi zdMsQ!@@0^;;P9+hU5}Si8)xy^U4%U^{;SEkyQ0>aKiBh*n#^lmDNdP!;d|Pn$*~sOx1s=-{Msci+RnnhJD%4;!(f% zsy|?F^VR#Csww;(2JBb23^yfQRgWfxn^Y=oWr^bUP-zF(;_)0nRvp0)DV2`qnvY7y zvoXY-Or_(vErm*_U>@#pr%~x-ZtG8_Gr8YDDxJY?gQ#>K_Zvc`bGdC8l`iJC5mdT} z+eT993Lcw5rOUZ(43)0se&eWg4Yy68(oNi!Nu?XPZ8DW^=eDU-x{cei;o`Pt%Qo08 zg6CVuY%1ODo`%$OskD>3&wxF%%*?X*dfcqYgWPs7l^)=> zd@4Q4ZG}{Ngxls*=_$@`A(fuwwnbFh#!m#S&vdnR!S@@S9&R##GYZDp)LrT>gXDHE zrP6aevK+>sC^wJ0((7K19ADz~tfbP5+#6h`u2oU#cU%in=_}s* zHB|b9+d@?Of@}3udX3{XQ0Z;1HB#w4t~FEXL$0+_>HoO4g-V}ut%FK`;#wDcoo1ty zdn=W`;WoH~npeEJ-o2{Rgxij# zvczr2Q(5J<6RGUxwv(ys<+f9)oWO0TQ#py-&ZKfOx1CMpG;TYW%Kf#5#Qh7MHT~6gu+;%0EGq~+)Dv#r~YpFb*+peebByPKr%9FY6W*BDREBPeL zZea)f3J&W&RCpX|f;b7%pXpFausVb3P)gHu9ZCt7$}>BZxZxDjp_JfSU^J+2oyOB2=F6NnAN&Zp;MN`d2)W=M9Q+8m;Eo#n2)W<}8T<&j;8qvx2o)K3 zt>8z<1$Uz0N5};?k>E$j1-FCXN5}=Ybl^wG1@~p(N5}~TBpBAFkXm+YPlPHagF|N z2v_HD{`DAk!C;$Ya@WFe6&??K**-@A53fu%MgRE%CvQXqFIplP_jo-*e(Ra!^<;V` zC%HXS;Mu#0z1^`;r=Bd&gcPE9pxffjKMDm;kOgd6Wnx7qY>u%c*j9-T*Z8soUU!ss zHCMxqmE4k20`C=@R=_e;Jl2iLyx~iY-7P!dyG=1XGq$sD<+#zMm%lxk4}YBk)~A*8 zo?X$vHkk~xw6wyWCHN;R;Mowq*zm1KIVPBrDsXen;+7`hf^Q+ST7gp zURLO3rCu)A%N2ULQZHBOB`k7c?SLgttb_$ltc2xFtc1l)tc0aatb~P4tlX%VLA|Wj z%No6`)yt4x*6C%vUT)IM2EE*@myLSaq?gTl*`k-NdfBFzTlBJBFFW+IQ!l&pvRf~= z>g6`QghfiMJ+MTHm9RjGm9RXCm9RL8m9R94m9Q|0l}GC3QF?i_ULK>D$Li&AdU?EF zo}iZ}>g7p#d9q%fqL-)YLn~P zV(oz?My!MdMy!P8MXZFyMXZFSMXZE{MXbD1FR#+etM&34y}VX0uhYxx_3{S2yiqT2 z(#xCm@)o_kRWEPT%iHzx4!yinFYnUJoqBnE$DO`KVq#rk9WF*XtY`Kn&NrkAhltwJ4E2xzMUZVdTW$ z3o`E`pAb?qal&r$*^8Vu_J$0~2DiDhl z{D@-$2gDuUDolT=kK zQt%t2T~gJ3A+<4rREU@STlzw3b3{+Io1{8ok%Avl?UL%#;Mo*Gs>>wR9g7tFU}u-q_P+E~M+B)uOj3u& zA_c!4{s&1NW|BHQ7Ag1z(=Mq#<>Zn+x;Kx+Er23RoM?{c1#w2xYEK=}m zu3b_m^d+Z`j39NQN$R9nq~PadyQEI-3#p?bNS$VqIz1LC_&wV$sk8b*>gWhkXPczX ziA4&2P`69!{JxMnE`rnrCaDW!k%C|J?UK5rFQkr-Aa$up>atj*U`l~qQdjnc)Cm!! zt};no9g7sqX|PM`y1tM)IfB&nCaD`@k%CDTc1hjb7gDE0kh;Yrb!#kAFss8ZsXO{Y z>eL8QcbcT`ibV?Mj@Tu2PhUu#89{27Nosd2QZPHkE~$I_Lh76dQumpp?vF(ZrpMSN z^-y0(ogYE!VUyIpSfpTnj$KlZ^@Y^M5u_eBNj(vZ6ig7ZOX}&qkh&~_)H5cjXJe6q zxkq+M_36p;@(5DTo1|WdMGB@k*(LRIUwZ0>2vV<@q+X3h3g$`KCG|#MNZlJj>P?f> zTd_#Nlr6iY-t7yi`yxpF$|UvcSfpU~m|aru_l4B`5u|==lKLPPDVWG+m(>2gka{43 z)JG<%k7JR7IdyhP{k|`x9*Q9KsY&XySfpTjpIuU4_J!2L5v2ZLlKNvTQZUodE~!5K z2)QqU)Ym4dzr-R1QyuM+`deRm>hTCte>X|}BNi!`IBA#EKl?)JsR&Zvo1}h-K?-MX z+9V~*eIfOdOm_wib*Op7Acs$YnN32zL0t$g46($)WBGzVEV9KQiJct3BLrhXb zW08XS%XUeP=nJWrBS@v2q(;Uf1rw<4k{aC?Qm;gi8e@_g8;cao;I>O@LSIO|8bNBJ zNh&iIDVRcTm(-NLka{hG)KrsHR_~-FTp`r z-JGR9Zwa{pg{x0!V1C6bZRPUfBZ@SgyUT?=08J>w7=~%WAtUH&|J2 zU=6PkL)JNftQSLWb^zHZH|Y%zC+0**%yuzm&%|uTmP5yT*mcy;2AvNT~ zSq(?a$G|K>98Q+Pd_D!rxCw)YOxi1-BCcWr_c1TFI2q^BV$a9PIFlAH);ReDsLZ8b z(8sbSCAz>d8C;U(6IjKk_R_R7#r5`V+G$V+KjRTiJI!p`S@PL>PKBE`F%z10k+_PU zO*==gB2GRRG~TrH-YZ`( zu67~!G<(!1UnbwcTIQ24hdJDgwmM;TBm&3m+ z;NO+-?<)9rH6wVVI74q06YH6wH(`Gm8F~|gyiLAc&!2U`1=)CcoA=7Q#jw-3m)Tyg zd?&(Uq>L3{d%f~qpkaHx@=nkcJ(uoamHQR>PG}Plkne(jI~kEZ;_sb86 z6KJ0pv}XbtEsHZ-7ROs=B#@;YaJfGsKicDBoR~Ruul$tV3h~0@7vpiD@r=dG(zqBO zGb)CQ(6}I>;-}?j1P>K2i0`)%cWnrMQQY&dh&kKod6Fyle2Tb7eoc%R!6*C_L1qdX zb&vdpy+*w$zoqv`0dy#KY4U`7dL`>=F3G=<-xmOW zzybFI;0OOA;79Vu0>Do=;Aa5%$-fBrx%`Emec`9BiM!<2?t+Hec>;*3u1`n|pyh0c}%wF(HVeklh!K;M9BkcvR76xb73tl4(9%CcCSr|OuUT~u@c%i-ECSmX*d%?}Z z;1YYmEyCbZd%>;3;HCD0+l0a8_JX$vgDdR?w+n+;*bD9u2CuRg+$juRV=uT%7`)D2 zaJMjcgT3Ib!r+beg0~5StL+7E7Y5hb3qC{`TxT!%P+{;Ud%-(|!JF*`A0`ZLvKM@~ zFu28D@Dak`HhaNG3WMA21s^30?z9(tv@p2aUhpx(;BEGTj}-7kr5@_(prdmkNV#wikSvF!)w`!Iukz zZ?_kGg)sO|d%;%xq82qNa;JbyvZ`%vLM;QFBz2IHK;9uJd-YpFN zjlJMK!r|z2N7C!Crg8F9?IFz2Fyx!9IJz zFA0N_?FGLq3{J5Z{E9F*&0g@U!r=b)f?pE`540Ejx-fWqs5TlIDi}@hWwiY$gyI`e>i{~Cx-ma z0pxfw3!~x_)F(gcn6-}|~F$EK5=|#`4Q!>SniUY_=Vo0|G$jM^JI0ukZ z#E@PGkW;N)H44L8pa+(-2%>iVt7_z?u$mwFpfes*Nh#?0# zfSf6Y9O3|SmKbuF1IRovV#sTD9G2}Q0kn_Zl6C6Mu zEQZW<02vTNPIds9FNU1z0J1;~ne70wPz*WE0c4RFa=HV^`C`bK4j>nZA@dwSE)+w~ zaR6B?hMemFa*-JFUh#}`YfGib5E_47{CWc((0CK4qvcv)8 zGBISS1IThQ%@@T96;8KArEl?xk(JU!vSQ281irjkekJj zM>>FP6hj{E0J2F8d8`A-W-;XP4j@~^kS98TY!ySE>;SS&40);p$Sq>X(;Yyziy_Z+ z0NEjiJlg?erx@~F2asK2$nzaQc8eh|bO5xES(A2ardIA#Zj7d88QfRtJzri6L)y0C}_+@=gbk z$A}?!I)FS@40(?O$m7J2yB$CtFNWOf0P+MevIvXNn=8cK~^o81h92kY|e_Uv>a_ zju`S)2axBAAzya@d7c>ZO$U(Yiy_~30C|BJ@?8gz7m6W&?Evy3G30L?Kwd0{{H+7X zOT>^LI)J=X47uL{E{6QX0pt~8$WI+WUMYtB+yUfOV#qHYKwd3|{G$WN zYs8RWIe@%Y4EePK$m_(A-#CE0UJUs+2aq?2A^+h3@oJD@(wYi*8$|6Vo2%$@-8u?&jI94F=Vm>$h*am zDGng-5ksaqfZQd9?C$__w-|Du1IRsM$UzPu_lhBhIDouY3^~jJY@~9yA@#x^C!r(0B2|;j= z{hpTzgL4Fb3*sK-ndq7y>lvIJkh7I%d(^yJc|JN=@P{Ol1JK(q2!da-5lm9#cjaH{ z!6Dem95<;RF=2JdqkMnmqzU(vQL88HQC{06zccZ%8;E=2V-Md28^J1M02uHAy-pYI6{hMg-rQrR( znWz@;55W7wXzyi2QeHM1UvUJ9Cx;P|_Uwe6%I|k8U+hu-IAO2y4gC8X{QGtSbi_pL zi0^l+@;+7Br93oYry75sI+&21>WKT*k*ibHQORY=se9BhyVVK%)J!mQD0Vn`x0=0= zjM=3;!sBK{#4Sx894k(FZrUA9lHn6O)UsdN%^Sw6{hNyt+)CG2E0vpiXYYK_*d)@#U9 zHI)IZ)l>_DTXS=S^?EgV9?ir2sx*(qFHVaK`x!M=B=;B96tBfIgrF90LGWr`j!}S-p zGI@~b91PF~FoZ5`fCXWoHZY6;iLrIJddP0|NCRt?7)#SMhIO>2S+E9agE-c)#`zqq z4Q77FYlAI*L$o1bKcl9#$wQ-9b1Ekp**a7k%CJt+hFY+OX~V+&4Xkw$tWPzYb%ud8 zTpP}?&eDckutsPjdSb1QxOT!==NVY(S~|nJKufn^jnqc=#M+QNz|zJGO@|F z;n!$mE#c#|aXg%lL2RVT8?TLLuGeYfEv^$ZU=m$ZFgeN612_`huv@)(w|WO?{CwYO zkg81{VsXU=a@V^}*Lw`tP&9wtb&u(~*Kn;%9wkJ5z;u1kaIKHv`lw0Z3DBOl^xmfA zWDDdorr&d*nU{Y+FddAMIb(!oz(+UZ!Rl@C{a*lhZ6f;q(3~1Dd4q zd&29Q^`pUjtJz|= znk~Il19wPKHQa1g({8t#_ULNh`kSIn!Hdcrr%kb3R8zI7{7injPyIBC1O#PiSuDt_ zWm$r1uNMakBV0yJHl-ZOuXhyXJ4*X?JFW@s}QP^vb=0yI;b$$>1RpPw8VaY>m&yt^Mm znx)NRNCUK47Nk5auSeVbWt_BZ|#si|>-+ppjkHL{$=k9cdG*6qykVa|qEJz1y2Mdsn7vFN+qZv{_ z3oxXyTEK#oujLC`cS0|%8_$pmv;u}SQ7f<@6>5b7PA4Z14-W)txW^|kq#~_|Ax+VW zEJ*XU`2wUFKG@T(8YsCy{rdDi0TBI#vNbbDw zwc;mdTKma8+Z^T&Vn~a%#SCelw%CGHqLm1c&glgyz>t<`OBhmtw#0%|s+9_m&W{)g z!kmg2Qkho9kQQiV7Nn)xQUTJ%y>KdKNXxWk3~8~p%z{*|l`|yvCCJS2%h>lSePZ3q-w2Nfb?)LNnXp4YP1@L)UDN6kZQGBjudgj+ZQpApE|)z#cjJ3xRJuGDx`%N z+96uVf>x*1F*NrM7^KXgBh1U@aqG~a!qYt<)ob+(=_swtwoOr)o+m$J^OQEOyKCuxlqq$aINfOLw9^o(`5(vh0AW`=Z{ z)@(s)(OLvZXP8LOM)W^#U8~m0kj~OtEl6!zn*iw?6Y2Sg;e{h@(Y7$8^Rz7%q;{=c zfOLV0^n#$DIB0$=%ZD&Z=Y1=JGhiLHr!+3}?GxG)$=~V&Jq1vGg z=_c(^3(^j4hXCmo6X~@`q`Sym@(%fge5ULt-$@CQPuVZck(NkHp{$j+3h;P zbuyHfyY6u9gz{6@x32G%{mOJ@fwBn7qm^@%^PzkZ-pc~MI!K+UPKI)|x>;?8@>ume z^+IL8`$_j(?st{_o+Qr*&nRVo+&gif#(kmekN3q7j~@x;@$nbLUkv3-@xP7#owDCM z&^z9n31zjn!`ltzt=ex%99f=Nw^%!*AqTU_(a)HhtVlC z8_G>|JKX{0PWl*q63Xuq6BCn_{fYAvS0=83^324m60e2w-Nerlzf|`7#`N$1jk7dw;J;X@qNCm3dT6p&#Ks95PZ#Q{n+ z?20WQBOFq)()uy5EYwE+2-K|fek?qoxJ>W8j30@jmFAC$X`wpiN2F?{`(xvpl&6z% zKQd*5HXmI^k_rC?e4`E=HU3@r&_(QKEX^XB|E4BboAK|g!#vvulgaI9$vQEo2G5tT- zRBLnp)AbtH3^|z0{0}$T+U);E-OzOYEEXVn|AnSooB!Xc-%R)bne$)j0&6$?H#u0c zVeWsiE3Dn|-{xV-j)VWpU1IH)p8^+4*W~{My2jc)KNUWf3##xZ(nZ#8`YCa;WYheg zP*+*I>!-%c(q#*OVqIqKwx1$5OV=&>33i>e`+lnYWRE+Ky@(2slAmZ7TD$S5%+b=7 zr9a`Ww07rDou{Qsm;S`N)Y`2-2dvC(i{~WoST^}H8euiCd?f#!Df6FOY_cJ{O*3nCCFRw+U?iX~bjMK#@g#^f^Us&6s+qd}_*uLmCHvK}|7~Rg6UvN94+uHUEZ)@;})A=swu-KiUV@e!%V8q!na2Y~2QH zh)5h6Ps&J;EF~9_W#ko7F6EF4=`vC&d&qKm3t1uWAuC!9j`Wt3qr8`rqrD%K;}WKl;}Z@cCnP*hPNqI`3SC7` zrB{

F4B}#OdVx#3RYYiO-VDd}-uzUoE-8cRRVscQ3iw_c*!5_Y%3)_b$2J_Yt|n z_eXN4?^|+LlAG*I@{@a#hLBxJW6AEMY_ccmAaZZg3FN+{R|u>dCl4ft$V16@kcX51 zPWJf=$YcIx9FS*zN~gvOFDZ4}dL6J{@cif-Obf2DXR5=9gaw+rwZ>lOF=xKCq?A z-+}EBu=STe2HT@x>*tyaw#UFW&@~QhkArQ1>twJ!0k%P|POv=*HqEsYY)^r0i0e|Y zJq@m9|0^4(78=*`C+w))>uAC3H7r-`BITCCyf-POa_PzwR z3!S*WHMyt(Wdkt*k)Rka+9c*LO3&HjV*e0k)gY8YQjd#Bb zwzt5R32jJszYVsDo>5?X2W*o)iC}vdY?I=?0Nby?HZ|@ou>BfrQ{qR0?LDw%$5XKV z25edJ7lZA6uuY3U7Hq!-TTcA%!1e*yrpLbkwhzIU>&*n)@4z!3lH0_Bq(* zC0q`+FTj?ca3a{g1Y02C6R`aOY=sH0g6)rBE1=n6`xDsa(;;B{3T#Dm2iX1$wuQ6~ zY+r+I0euo|e*xPfdMDVv0b6lmGT8nKwi5aeu>B2eixby??eAbKO)Lc4Kftym@mjEb z3$~?+r-SV~u$3i#3ATTNtvvB$yI}w(rN?=>zYX_SQ zw&h7du(`mtDrqs;6tJyKx&>@1*w!SS2R1j@Rww-hY#y+!OL`w{abR1UJP&N~VB3&9 z9&BE)txrA)Yzbi7nA`z23bv}`*T9wtw(8^u!R7;7&_5JxNnoq>d%%_qwigFq*3_|J8w$4eR6p2;fo)6b7O)KmTW9K8u#Es) zN9z4xO9xwb>UCfn3AU~@6>Ouxwk`D!V9Nm8*0eIPjRxBxX|upK25j5YE&|(Fu(51b6NvupT)NWIo(rd?cCpVZY8) z(hqJp@nj$wLpu&YNF~>lT<(aOVn+->U7gKUAN__vrXG<&s5@q$Xqqg zGZ%I@?FY@d3^y{BaPLzIH!09D^RRNu?od%6l+kdMX?UWdK4Q_RH4|2B8Z|IMGcBt z6d@FKDC$vcLeYR?Gm1tOO(>dCw4lh93khjOtqsK%6zwQFP;{c`LeY(4D~fF>wxc)% z#i1y6pg0W0;V6zkaU_bPP#llqXcWhwI2OfmC{93eB8rnxoQ&cW6sMv%4aMmw&OmV{ zinCChjp7^>=b|_d#rY^MKye|8i%?vQ;t~{>qPPsjGKD6t|+d4aMy!?m%%Tin~zkL~%EYdr<5`u^Yu66njzJi{d^M_oH|K z#e*mwLh&$)eJCD5@hFPNP&|&}2^3GFcnZbSD4s#_EC{&(Pv~=a_&kaiP`rrZB@{2C zcm>6)C|*PHI*Ka1&{Qdsxeh zQOhb{2VmgW$C}yIVg(45dY!q`)9E4&nig_pwMiD@fkD>rYA&Mdt^HD57u@FTu zibW_EqbNbK1Vt%|G89WuEJIO_q5?%FisdL)pje4w6^hj;)}UC60{<|#f`3X|!9RYj z;Ge5jHln~k39aBCaaL+j)S_rW5kgUiq8`O26q`{rqG&?VjG_faD~dK0TTry4=s?kl zq6NPDgPDiZfB1h2m@!=b$(j#d#>sM{xm)3sGEz;$jq+puj&2 zq~M?OQSguNDEQ}clq*r-pQKUnkH{$3ptu&rbttY!aRZ7QQQU;$W)!!exD~~1C~ik_ z2Z}pU+=XH%in~$VgJKto-6-~;*o)#`6!)RH9|YSQUe1P#gzcCPJHNb3q+AqvC=NoA zk75Ce5){i&tU$3A#YPl~C_*SUqi99ZiDD~?9Vm`KaWsnKP@Ie+1;rUC&P8z%ipx=4 zgW^UMx1rdHVh@T3Pz*rv2#P0BJcr^%6tAIp8^wDlK1A_h+00JR_Bzh4i=_CZ|g>JwYV;lG0d+(KE z+^}))y~QPV;*vOa>?C%I9s7H4W_NG*G&(jqC$XLH2YNI6_Pzi7XXfqf-rmgI)88L@ zkPtG~eW^qen%e`dftK=(ErF({V2hhb66sU9wzf4`mp!_+p)J_b5U3kn7_13YZl2#* z)m|5L6Ng0Hb+r|v;m=JJiKx1LNwB%Swk7Cq-P}-F5^N2&xrtjMDb^xJwN?h|0ut$4 z$TFi_g4K1w%C^y^s4lIoX$Z8nw*;q1M5)-^7HpMbu5d}pqH0NYCrEz(!n8O^k%#3p zr%@?aPF4aghcjD}Tm=EDcpMw$G&L<(a%|0!2BZy={Ek7sW-sW6IJka9t~4MpjO&v@ zKTp#aqdtS_echB;MOU_qR z|EOMB9>wPw7?38c%g^xzf^*&Sgh4*3+ASvy>PDB2?lrmEQB=6LK^FiWMw3!CB{1D*Un7~ z6el=Rm0mp-tjsE%SClb3G1oag5bG}RN&V%-g5Gl)drYmKy*RcxMv;d|gMGeQx2%j9 z+=_O2+-{(pIH|6C!_sk$wTojH#)4h^U|%!ZDbu&jPRMo6HSo|5@dixF^u$+49!GOZ zKpx+o+jm>Hgq})FubiZK-vFuD(I+rr^y)Dc&4V+N0x7YMw4(LCv{aWo$Ti7Vv@)xH zeNsmE9BD*}k{RnBvtmruLRVYOsGbwre0?%qvormQJSna@t=HHMGhBH+p!{XL{GoFE z{FIFu>a=yfJ_`*yY59Z-&2E)mAD^$Tdwq{_ZS%77n*BXg7PmwFN^pg1n`@Ms9Sjbb zB*km|{f_L0-0itTM)sZDRy$x)8rP?#ra75@$*5(M+m}u6Jpp(G^>#?+_|3uT=`j`Z zSk^!O1<*g^=|;L@^1AkJdCgKUtz5~)%1!7yxnflj@Zoy@Fiqdkck;SgwC`=TZ|Iv{ zQR@PGt_OQJ!zo&oT~Sb7SOa{Tbv~(_PiuiIy+?emvsG`0UYdTME4_Qu$|>!>K4~$m zeSL908QX0@%F_BilVTH>In(hvj&(Kr8&*wOlfSt4raE;(-HdK+?h1JtkG~Qrv9xE# zrov@Y+GZqFO=wt}-3a}l;|1iNS!-u_GA1@I&8lCreFXA5M(5Fo@yOaxv%S~sh81I~ zR}GjH@Ur%Yc6Llzx1w9hri@+_+u@>%l{CGSJGp6o$+m7qy{E+blvIiF-t1X8py#yq z(#h!)i&tf>33j6~a;{&|%SrQPOsMZMrGEW(2aFeEt5%gbop9dW`FV=xV>>^eg6HEp zKi}IqAlDzy&inldjal3c$(F)cnbxj9d9I&zl{NXr>eU!Jhi4S2~q zo^M!skNV|f+E*0i!T1@cw{z^G61oxU5iA|x_bqg>xbP42yVlpbrf#Gdr`uZ*M-9g* zn2tCJdOXI=o(}!HbX*YHwZN&ht3Q82^X%;dm&{)_W$lasbauk(F|G4vp`TYTKWRly z?~QbMcIEoM+Xj#BJ5g`vG`+lma*{aC+jJoMurhaP_edrzvGk(4oH^t&Qr;* z&R-1UojSQLP_k`&;_A%y^{kyzb)Jc(+k3fToT<&tLLS*I;6Kcz`KRTLTQfTc;?=}& zxz2CW=8bjgqzzjAD`tri8t zj$SsoA~-nBx3I)NM?t^dF2#`?H*A>XXqY$NnH+%ev2^>Cp`+DF&GY7F3`h$M_Qfi} z)aEj`!!e;0;D^d?xV}d@9P$8H{UED7^}{%`ZpP}A9`Su9RR?8{Kd@|K>pZMiw^-*g zWn?#~*OFebnZD7hGuv|K(uM52>`ALYyY0yn6IYL^cZ^gw!nn64Sd_kr_V!66OMe2& z-_%rBTUpzd+gRUJTNf;DYO8H*Xic{s=GFyTTiqlco`E9!xk;i#k_FBZ>92b>1uEAE zYJ%z2EsgaB4Q*wOg|+a|7N~QRB#9)3S-DAyM7-gq5*f5EupuzIF3?Z|&wLvi*9S+> z54NpsteO*OsHzLLrWZCgu5WL0lkPw{vZ5^-^RiTJd~#PpU8m38aaR<)$NNpFe7 z8iznJWKvaK9R!1Z@Oas>fgM;7@Ts!36$}P21nm$WVe5nSqxmytI%M5skVHHootq4i zhy#u#(#`rLnw}nLXlzK&bd%u{k!u^FX$tiQ%W21&!&9iYFa(A0po*)iuhk!zfngyW zjy9>l!dcna5|l_xAukX#9@Lb#w6>Mk!4t7jOz2S=Y~u6$W&ZN{`SZ&Q3ySigV%igO zS$k7ma4Z-swJ4?*hPtA-VjVm~PwARwIzY#i1!~HdG`3VpL@Iz@Y1yE)Z#{eHhcGM* zb(D4r+`vxjSdpD}3ah4dsBYymp|PF@o4A}gW##_7ypr-cz#w!~SPbQ`b0sDIW#xJK z3(Dp|<8sP!%)t5)2gV~aa6DS)l=)|u&nhm= z1M0>xM@zwDJe5^mP?VRylo8O(m?D$$XKvat78E+p3Ok=wZatqJc0QY(kHKO&gM^$# z1%-L#{y8}iC}mJrkEU2!Fct#VI4CdjmlZ6A^Pnm%UrPwKpUCse%JR#X6y)L6#Wk!CGz|yH&&}0M;+PZf8VE6VG|TM4G59sY z%j6hEi#QP=!7)nmXBQL~>6A+Sc_l`kUCJDY@zBV}=gs$*=Pa6~4+b87Tv}cL7cA8e zFygTcW?Nbgm$XE>&+?a+!G&9vUsAGYL0Nf8eqKRIelA=Q@ddg5+&TH>S=dOx&8r=o z+AP7W!a>TSz^mA2w$NJ63{+aa#1EX3b+dfGX~;7SQOjFQ$7AiPjeIGZGt=?rH5YB} z0*_`2-4?2#-epPJNo%KRN{)+lq?)F%sJwJ}s99Jq0#RtGM9l(KP(AEdO;cP{2({Jg zRhnCrS6&G1A2Q$rn$D!O%wGm06|cJPg(I<6bG_M66{@)2aj3P^#d)Q^+OiVzJel%=df`+T!-UMxDLmia9y@QhvQDT9gaKUIvjVxbvTZj zb)j**qZY^Uj#?bYJ8FTaKnqL-S{%naBH%dQQH$faS&L&Qj^p9F@b*Nz@b*MqczdEQ zyggAD-kzunZ%@=AzrtdFUU^w@`J&SN@&$#9N`Z^Juyj!tjB@ZG0J%`y=m%Qd=!YzB z67UFPv?vD=@tM@3Fh+S)m%;-PzfrKGGSkTGD=IGM@s24Dpul25L2h|g?y}rMIEcrC z96zwdM>}{fW5*1Qor0mbd`WRh9*i2yPro#n9UmT;U0HFNzYqs*=sAQij`dbZD9MKh zzB0Jtwa27bq^(^;aax`?g-1K$Em2l5Kfk2BFn>1S=fiC%3ExQb&p+urfi@mF)bwo4 zKEO>GX42>{vAI1w%sMuugICH>vyt|Y?j`TQ=Qr);cY8xyZGCWbXPq1woSVD{cfpFr#rnZD+#6P!ZH zugM1<@;>=6(M5g(@9W_kgu2ZVNry@wt#;u25&1X?zJ>S%J}p((HdImaJMuQ7{azxy z!rbwjfs*!yGH5CI`1c2h`1!?oiwg78;k%0PqRh5X$`|C1vE*~|C44At!%trgG2~Bh zM`#MP1nPtEK^dE%m37n#Q+M(XrsOZ=YozoI4D+GSTH43=zd`rZ1lxFzOJt_Gd$e}% z2x)H5u$ZCbALLsP`8)Xz?wG-bR`?RcUs)M!ZLO`S3rb|X89&T5BI@_#2M_riKGqRO zpsGqDv&}%fqNbYv3&@fzIiPhUCp;rSTdr-a$_-Sm4MNxt2=9~*(G6FKoBM!y&(6!o z0WYlO!L>(7W##LZ;zZXkjLmWD+Ta7O76MX&l`@>y*g&r1I)||U&wXzodmw@y$HN0h>;)?%;myK z%@=aX*w6e@)5m1EF}qpw)>g$xP@{Nr48qA6ExsTt@P@)H4sfhHKvv*@G15|1UKMBy z#7NV_yy2wo4OxLV1W4!&P(zG_kK<;(a9#(1tN;L_B(|!ehQC3Ik>Dem#UEo$t1n~) z{tzy4Ex{UiZKYLVei#B6=m?M%AV3rA2r!Pc#7HG!2wa740>qs$3EV6bdeM5zv4L@`Zqm>RcIy6NU# zd?4Q3b*=5?flY8nx;e}{6qnh;xXi}5tgY6(?+Eh_#Ulc!z1PCrofzq%F!xYEW(xyyEQDArbLXS`qgH=Btpy`y zI~G3{g3QDGE85|*j**@U0|>< zX#@_hg!zX;5G@59AfUK^YwZ>oXWtC-4~5=XVd#y8km8L1pV=DV5$xSCfKc?Isek}P z6$jYZ0v`fnqz}UYLIF5d7=U9TvNQnxr~;p_%;Pei*ZWZzgkvGNDC>rnV4!MqE!=D2 z1D6FN6p3gos00L90$zX>?XBhTXvc2&Uxk5$;&H4n9>+nHCE#^v2KmMcf;L)ZFx!#I zIEb_ad~7maN53QRN?fIz6hqeH+9BE!cibDN9{MJ8qiAQ+kWQNM-VvScO9KNOkc zgpoN8L$9^5x{bSg!rViFiH3sWA==`Do7&)Z+1gUcZZ~pb7)B^I#|dL|90VL~*#IA+ z0+qq?ruA(xa!MFPC_2$tKm$T9p)qvpgzv6nWHk&V6rtmU5jqZn&SwH?ZG#zutub=n zFq}}BqKAMC#9chc!FvtkGB6Ay6s6;YQ92&Ou2H*%;SLSS>M!V)C@Ys0u%~e zbP*7Oi1bzkE6dyJ+RI^%X?0~o+n5-6Y8Xr?gvSd*csvAUI80`Y3~xOxY(i0t4gxk1 znBg#4G4iZ1m{25-7e?}UXoYZ?>=+roZLqKj#WFew*g$0R;ktzl*YbiefKU*R7Y6Zo z4C2sm-PjIS<)Sc*P!OYaM-metHu+r-p1hi3WcZfHTnRj_MG9u!_3PQ(UYJe+FZ%TP z5|)V!F`5aypUWI-m~@yO3~x{c?o?hQ2jWPKTmf$e+h8U#G_*F4LZ5U2uYjB_!KONi z^cz}WU@U^^FD6KK2(P^W20!R2=m3O<4%Md~Oo{AD<#qDE!K#x#xPVX7Z@qJ~y7R7DL{MStU}aiDUG+=|@W;6po%`C0HDxh@!JfOZ>NFbw*a znv{SPA3}oDRNf?SM(-^U7wx(wO#KPxFuqxlwt$yaP+y z36IW!*1E=q8cuUAG&4UAXE>M2yXE82XAe}RqOGDFU+%39w62XrQVR&VsS+w|cCts7 zxl{RM`4lV|KJWR=80FQCbyYB6cF?6$`3&xIrdBLIUu$F&(A+o%({s4#xmvYq*6NlS zVQt@8lWLW8VPn)ne>(s|D^~}D>W=HIZz94{`C|DJtURn6NNU*-+z@OihZpI!ZJXh> zZza6baN`&T4=4~eT+i~!9ZjL8S8=GT;R>>xuL**?FI)u<*YT#g9>7~RRJ1^=1)*lH z#_DQ#mjkh9D8cq-4t@)JV1Xy`nxMw8|ImUCS3Uo-fn7OS5X94uVlvfeBNo2aBQ})^ zzbxk8>Bg`u`%2e|-3&d^vLVC=dSY0pCyv65%J<0ou=V$|7N~30TENlL3eN#heN6+^ zKg6ql9}HYA8{pH_dYHynA84zD%VToHII>nIbfIcdG24A3nqb?3xQhY zhH7O%GK@}+SWAW#N99N4BUs-@&Eu~&(j-QntbO zPVBadR&@{<-mn@$E4B$*@!wuID!(AVh|T^Ibga=PyjXTQ1uHAz16?IN>p}xm;l&Oy z9a2L0z0R-HHw<%l_+#dCLVXk|8U*LU?r##=^&>%ru4X~0M)d{f@Jg34`dwIeYzB90 z5WXJ>Rv8V#s|_8wP|%SA$VkP7H2{_0mw%1D^Z~p4Ld{=}56?KF8odM>=#$^_KKaNn z=j52V%`t&7?rOZsIr9*R2jaV)uzXW#vL2XsQjh;71r`k@H7{WS{1AgwAZzz!-p!z&|xr7 zsb{Aaz<`Dr3@f1WH}YQ*_iyaZ(6+I$wGw8e<2N`P^aBWrZ+TFBN69!cK9A#drCR5PZ2^P9>dfk@ISXO&m5NALD^TpKRa=1NU7sEjL ztl)4^u1$xp?5C1x2uc~KrZ$68M*@d~7Z@%+uNXenSQzpt#gt4ZGY~2nKlSh#@^m(jPM?fjo*rz5$C9Cz3D{GHEtbd%tL{g9)<^U{9cbzE zv^gVuoL@}IOx|gIDDm@LKT2|VE{&30o*PI>9?uP;B%kMoP%?|>hEXz`=SEO6hv!C8 zQowVgDVfW2nUu`qxok=bd2Spf^LcIpB}F_piIQTTgDzdbbJHkU$a6C&Dd9OkC8a!< zOGz2e=jRB1%^A+!9Jw z^V~8@%6V=DC2M$Y6(s?lE2pG_=K_>e@?0e)RXi7@B*=3$lvMLvEhRNPx1N%}_IA0=n-+yj)H$#V}; zau&}$Ov%|icZ8C2ceND-&Joi^hZsWPXQ*t}c zeM`w5JoisZ?&P^2D7lN}oDwB>^PGc{dw5QvWFODDDcR3+v6LL(xj0G=@?1P6_wrmK zC5L#qW_7p6f%&!#vlIl1F$hjgligH;|G? zd2SFTkMZ0PN*?FAVU#?S)Ln5$#Xn6fs*HW zZW1Lg@Z1ziUgWuHl)S`qGbnkP=lqns!gINlyvlR=l)T1svnhF<=L#r!gXiW^@+Qy0 z91eEhVzb#ocP?D{qOGIhcZrBbg~i-xFy3lJNTJ0s+;C7QhM~nc+-_h5JDk|bt@?Fh z6|xYr$5lIgsSt;WXcV!Eh!kE$_9PJA7GP*B3*v=FGz(Q=gs6&u7QTomGANs3j%$l- zndw#Tj3PtBl}I+waDkEyGhDZ1%S=ZTc0II9sO5yAW?B5i3rrKWFt>v>QQT%oBpYq1 zR3uC53My_nRDj8z8_g5)?VD!WH_ftdnr+`yYbra{8fPDMynWLN+;sR++ErUf@UIwa zZEFu%Yh8QBTKn2F)>_z}vDU`+jI~y_XRNjJ(K;Fz9gMNpduVDie$mus{GzGN_(fBj z@r$N5;}=bB#xI&`?J63#_!>KX0UmGE{-QX?cgDEff}4nL%VEp)j$#;E5XKEVC1)(| z<94E3s%gz1HxiAi;Y$IJ!Y{OT>L~n-B~?e^$Cr?BqfT2GU(g@T#CS;Qv=c&$5;>OW zcFWfvYHJm_ndp9{FHN(;X+Tf5n9l+ z0`{my<9b(9>_muOw6um!guX^&J;EYfj@s&4&QffL_c81JPTbA9ogNJ0_R+1Z6%mc^ zY&~M=4l3?qfHOyRr$$;Zuq#9y&Va-@g^KL7J;H8bow5(bUZ=#4c9%1j7V|FZw5U*A z3I_>eAu@*%_Mm1H`L1MIw#=b~<6`(~X8WcQ9zM?(+Cfr;ieHDKEq8T zJbZ?mMtJxPH;wS&$!vPm4^JJ9BYb%3XdL0gQ%7U1eT9RUDHb^A2p^t0B1ib})X_M? zho_Fl5k5Sbjq&q9gbz>QrZ(djQEkRAn%azCG_@JOXlgTl(bQ)AqG^P7?Xc>dj|+VT z&myoy9T&rM1JRI%YuNd^aBd?S(sY~1Lz-@dw@h|}5RLn2gu^~xXwU6L&v{{XrYBg@ zEdZ^xW%(RZbZ=rtq1F1_P&DjzSj5jwMXeWF+s|!8PZE|T|J+RUu20_yATp4#K|o|q z=G$Rsg@tZ)ov{w>D!}?vG%N`=AK=VHop0TffZK`g#Ku+y+(gvlrX37AZ;8;x2Ay-V z?svfLlHlueeMW`0^%*4@WF&lh?))9hW`fgU+n`Z0jEut5f8bxfhi`&L$!IbL&;Jpo zAb`8J6B;F%Bn#Dlq9mJ)#oS-;i}g_PY;y4wDzBEyVa|Z_ue@}fTnS7iYN>*+R5F~O z;^}|D9Du2{4Yh5sB-cCzVlj1o=lrLK40L`E{6g!+%ht9uZp2ArZiRSAALsWT(jQF{ z*j{ke?G3ocTY4sVyg-f(V1VpyHsN{mN|MVCaw1()Zct&7*+tx%5= zk0v8Rob)y91+evAWdL^!EDN;2)&lvPDuZkTLAL@^9s21_(8(TyZp9~&G@}LLu;quEz0ZUq*%yV9}qVE#%1pTEM+po`K^=^v-`Rnj2m{3pz1Q3hHj_X=i{Gp9i? zbzB*YF&RE-obwp!AtRJwFn6n<*n*b_a~e&v$JrrOMkpB&WeTjpNYI;~Umk8{G<37B zo6k1MOLr^K(>|jMG%aiL>{umB8A}zX^D_h-pXgF1c%7d)U%NZW zEkNw-7-HVmLfg~CyaPpteL|F(3T%!&L&8(jDYy=U zpIp!qgc(rKrgNa7wRtz1jlpc>P&SbFJK~P;yMU_&e%mb8Q^@R;e z1;Ea&EP>HQr*FM#+{!YTELGK5u5GFUb3wz~%!sqjD~_dvCZt(QFa>*X6D-StwP_7) zu-AJ|pf$)N7q0IW%1RFe?kcLdonK(!mO~$|@jAaqg8VG1#5uo0Z53#PUguXy!~t3| zn%maGXov%J42)%LqY>Wsp>Wo=SyAegdXF+jX`tjS+yh2dV5XWkWX4AQT9$XTc zB`}Z5EQX+ZU*Ys&x3bNo!STYa zY^PE@uK_G(h)u6-gw+h}K>}ug>b`7bF^;<0cQDrNQjYT|JCxm2O5$b0Vu*OX6gFYk zt(-`u?)>ClD)r{MQ%tmRj-p#RjY?_!+!<6F%yVZ^X#~%mL!~i1cOERGsl>_E);l(z z988r9lnb%*E~3&nZhr}tCiC27RGP+fSHKeh51Oku3coSJ;!3vRD%{wWYw#9%EmX#G z%B{fEe^}~N3#%7lAB-wC2OU@6=v8L(Eva&&a+627LAjYqIlRPMVQAHDLUY00%I#E| z%`NUU0dGWLs@%;{?x9j4x7qJePFHqA)9DOwK0j6N<#vatw2<4~55tFUg42V|4B4!6 zsywJXgbWW;X)*VC#G@R8*hcMOmyTcqRUYGpk5g#{H++&x0j_(RN^7|8St5SiKUJgCH%@5X_TlrOdym<|78~9)sI_Fkk-nOr*va+5n-EG_uY-y>j3R2}Q zEci|3ZKVD-)T_3G#k<_%J+ycacIkmR!EDVR+oAv`Bv;k8;$4j@A8^YL(eguFPyofj zC=Z>9WZ$` zxfgD=OO-#$<%sYlTL1=AJE`&~=QkLofA%PMz_lYk1wji2-*}Xh@KS2x%>GWLM&6X) zQfUri+@SoEN^M;C18x_Lll*~jZ9`>UdsT3BZDl#In?hZZO9pF~15jNKXkM#<+vW1O z+{n;b%PNgqgoR9?O*u-e%Y!I!h!TgbZ4|>z+^z(VD-m&GVY`8~Y^^qR`H=k$t|V~K zBVOMh+Ub#;q%rMkMqHqbDew1Y+XZqeY;&82$4qbIDaTSQ&G;SwOp zE_|3<%Pvdm>c_4MSAQ5`IlI;->Keew!DE~U7l-S%gSag`vc+;WtU;u%q1+fA)HGvU zj80u6xH^NC#Z{xY3LeK4Xa@Ant<2uRBktiN~dt$Tq>Q#b%j(qlk1A8bUyc8 zK&A7zu7paLaJw=pUCechsdOdREv3>GT(_J`*KyrSDqYKUtKlj$#Sd(F0n_6H4GqD% z)+toF*|i3vAwZ>@xH*JuiXKR2TemCdaaAjyQ|S)wvX)A>bC-2g+Q)TuRJw=j8mM%L z>zb%^FW0qD=^@UpjY%4@rcN=LYE3zeSYx@}Z?lI!5E`8@aCNu}qwZWona z;dXFQzRY!dsPrb+!ENmgu7lg!yIgk)mEPexxSf5-@!)p$0oTFp>=SMWx3iDA?mQ~} zf!kd`rO&wTA}W2wb#U|glI!5+^$piuL8Y&`?kXyM%XQaK=^tEo9hC{!-9V)uxb7wj zKU=~s%3G-HlGVFc&kvvi8R6cQCYh>U!ZaZ*S$pLk=*VTDra)tYgEqSx;Lmip6lMC@&vB?6_uxO-Mdtt%60Ek zc_!C=KxIGI{f5fW;OgAa>1=<_z`l!jb!){a=~3;_z`l!EnfH$a>1=z_z`l! ztylOFa=|@R_z`l!%~048W@OyegdZUn+@6FVAs5_igdZUn+&hFHAs5^QgdZUn+|Yv` zAs5`4gC8Lm++TwqAs5^!gC8Lm-0gxLVMfL+EBFy|!96JW5pu!ZBlr<=!F6o>2)W>1 z4*UqY;Fb*h2)W?S3j7GU;5G^T2)W>f2mA=R;PwUV2s6p)Rj>;jf7cS^Z&ctl)CBYA zO6^UC{zfKP#m(T8bNGi-7!CUI&*!j}2;0$>o92azaJx^G$k_sTcxSUV{HHdec_kxw z(_>-W;r$HxwR^9}eUkg+M3);r9Qx|m>m?I)>OReVLK1PhPlrb;<0snS5jK}C>x?gL zgB?cZ2b#+8=^o$K!26b>_WBCgUX^Q-3gN|O-C|e--@*rK3o;Rvr7wm zEr7eSdid*`S@26Lus*JYx9s9twj-*)p`j5re!-ttfu~*gWX1Q%<(QyKEXAE*3mWQx z3%&+{M^UB$`Xr6W#0h^c5(A4XlJG@0yn;)@H`*+PH`gqMSJf1}?yo#l; zxQeB)w2Gy$u!^N?v^1cl6$G&emey%$y_Pm;X`_}l zX=$^TwrFXqmbPhWyOwUy(v4cWNlRgo6sr#`kzy$cdW)9cs-?GS>Frv2hnC){rFUuR-CBB&mhRKi z{aSiJOAl%(EK*|ifh9^Tg#}71h2=>sg~drMg{4U>g@s8hJ*=eeHLQ9|2(xBEqy^tU)0i)gmsH=bkSevbR6m1M z|45|ZHMm_;1EVLEZjc%ji4?q%w@YehS4fpvS_*#HlU;oSq~VcB!IuMeNsWx2)F^}0 z=t!jCdkVXxvbsWQk)@@w4N_wxk%BKn?2?+$6;g{Wq$V1qCPg9z-^=_5Nlh_GO^rkf zz9OqOOoyVQHyigVcgZq~L2gyQE6HLTaUjRGC3)Q6y6Ey`NoDOS?j9m4(zYgVgd! zq~JS7yQEfih16;bsnrIl@<^oMOHR9_D!M|d+(N3-AXOEK6nx)mmsCwxNUgDuT5FK1 zjYJB*`n5}{E_zb+2C0Tfq~J?byQG@CLaNr%QY{9l)<~q_TU@)Ox-@vMw~%T#NNtEj z3cioDOR7sPwb4RqlR;{8BvSCzs9jQBYN^c@QdGm+F~KK(;#(h zBvSC@uw7ESyFzNKh1Br|sXdWM!MD?PNuAUcQrj$~_8O#4jzkK+9=A*Cw62iaVIg(8 zLF$Z1q~QB`yQI$U3aOnIQs)??&W%J0CJ5LibwO819cv+Vp+V}RNTgtff?ZOVc7@b# z3#rQtQkO>}1ydyKlDeuZq>i_cy4oOhO(aq$^f~kA>6?2B{k(k%E~Zc1hjR z6;gXGq;54x-4=-y%r&t~>dvl^I@LnzE`!wFkx0R07rUhPcZJj$7E%WcQU@cEg4s59 zN!`~KQs-Dm-EWY3AQCBgleKy3j)E8H3cbkx0ReE4!p#=nAQeETmpENWBz^6ioTDOX}6Gkh<7H>NSJZ z>yb#ooHM(m-s%deODv?`Hc0&{5-FJUW|!1^T_JU;h1B~7sb5DT1+(t#lKM?oNL^+j z^;?6~N0CUuv_HF~KJ5yr%PpjSXOQ}RBvLT%&@QRZyF%&;3#l&*Qh$s@3MM|dywLzeFMhGcWCu`fFE6U2P%tH-psQBawospLR)o*A-INSV;ZTAoYDDQZV<_ zCMj9!3aM+&q-0qqB|9RJ!pX08Nx8a0>Us+)w?Rt(4q5bdEzZ8RODe7_q;9Z~q6Vq> zNG%1^f9;a;c7@c97E(TgR8k~TF#p&tsno8Jy46Cen?b63BvLS&*)FM`T_JUcg;Xzt zRPRWnU^=y3QvJF@>P`!({syVENTgssw_Q@{T_JUsh14K})Zj>@U_!ZFQp37J>TV0E z;RdM@kx0RecDtlTb%oSE3#ritsWFjA!IXNtq_Vq0YQKflScBBKNTgs+zgRt<}=?1A8kx0R+2D_wkxjgIVlNu5`k&kIC*h2%xuE>hRX1RawX16 zlueTm-3*&@1G!2L!g)!qmTR;c<-_zuwqL{WUKt1Fda*msVT6f_nmguj5;Kn)J$ zSjleO!eHs*EVcQS$PFO3$;Whn9C1)SR!mF)3DuRXkh|pLIzR%;6K?G~%M<03IzR%; z)9kX`Yi7BZRs3`@EyR<9u{%`4|~z zq~paJBi{{$IkXG<4pyaj2N-(6#4F#;3O?9L)$SLU+p%i*8vS9Z+Py~A9*`f@Vk%U% z5gAam$HYZ+tlC3b5i#;%Y&}-BhvmniYB=sel^%k^4#VHWtV&PFPih6W5jXrJBw;ud zs5(_ebsdyn78g5*TN*8zAU`F)!df&zej3*5V6h4EGgvIkJqtPPrv&*q$SExMJmg%A zlyh8ln%N^`0a#y;{4V6Mz8?8K$T_uG`V}kO=ak=pIspOsUHE&C5&4a{ zZXb(D*s9wn@~7ee`hys>V*u$ji!o{z!)vAokf|PUxqmKy(cxkoky>G5%367%oEnf`o$qB7ZG-sQA11ervgFgY!ScE&oq3XFDxV#tEJx?vZ~G zBU<=`o+8LZL8b0-NVY2FkR9-=aco@7g$BhY^$x$sp*%s{!w)!OF^gpQIuNjo>*UeP ztA)Ab@Hk+(NC&`p4v5(C|01Bz0b5LU08HV4-2pJ=Uj*#oP_^g_J#~%PC;xCKRMf^( z7c68k78E*qYNG^O-6A=9IeKeXQV6=&K8Iu<8tyR`NHSB{yM1l-F7XSU``dHQ5jqdB z=bS5aPPgZrCv+Zc&pBV{Jk*}^ETQvod(N|k&KdTc=Lnrg*>f%sI*+mEJXh$PWzTt@ z(0Qyq=R%?Lcze$Ch0YW0ITs0?C);x_7CKM0=e$7ZJl&r2LZS0ad(I_7=Nx;^r9$UC zd(LG-=UMig7YUu`*mGVibe?O^d5O@u(4O;Bp>vTv=Ve0Y1@@em3!O{sIj;~pm)Ub( zDRf?J&v}*5d8s|;)k5dx_MFRw&MWOXuMs-0w&xrWIu;*MUbgr`JTqSg_ zw&xraI9@blz*vd85$z6noB_gwChgbKWd;KEs~#7NPT5_MEp0ozJo7yiMqQo;~Mdgw7Y( zbKWj=zQ~^Q4x#fU_MCSLoiDTJe5}y<3VY7Ggw9vlb3RV!e2qQl-9qQ<>^UDVbiTo! z^B$q|P4=8m5IWyt&-p~5^KJH=PZB!cVb6K5(D^QV&L<0<@3H56iqLt#J?B$}&Ij!| zpC)uZWY76@q4WLroX-$CKWNYSOri5(d(LMGogcC1e74Z}QG3qk2%R6d=X|cv`AK`u z=Lwykwl(D_+=&KC%spSS0Hq0sq7d(IaLonN-+e6i5^ReR2t2%TTI=X|Nq`AvJy zmkFKUwg(D@yE&Q}PX-?Qg@rO^4;_MER0I)7--`D&r_Z|yl>BXs`Qp7XUr=TGf9 zUng|_y*=mah0cGl=X`_E`3rl_HwvA^a{mbpD$? z=i7wN|FGwLyU_VNd(L+Voxiu|e5c6SN$fe_C3KeUIo~aGcG`2kN9gRb=e$qo9AnRU zztGuZ&-sARnc8zcD0EJ+=X|fw*=x`FkkC2Fp7VV|=M;O+_Y0l7*>iqC=-k7e^MgX? zp7xv{5<2&`=X_Y`+}ED-!$Rl&_M9IPIuEetd_?G+ZqNBqq4QvS&W{P5huU*~TiqM=sd=r^V34-EPKw+2%X2;bADFnJl>x3b3*5d_MD#=I#0Ie z{DRPVsy*iyh0fFMIlm-yo@vkdWubG9J?B@1&UyBnUllsfvgiDo(0PtM=hubKbL~05 zA#^UZ=lrJ7xyY8YvsgTjsc+ZkF*z5AA^S%Gxljx_APUG5F=ToakfmbC!BIe#i6MtZ z0l7#FIXnu;#bU^eC?J=JAxA|4xl{}}CJM-9V#us0AeW0F$3_9ULJT=R3dogW$ca%v zt`b8|jskME7;FNRzk1!SEVa%mKh^k@tD}Hy6GN_z0XwkROCiXk^d0l7^KxhV?BW5keKqJZ2k zhTIkf~h-$U{*; zUM7aTKMKgp#gGq10eOWO@^BQ8SBfDYi30K}G329BKwd3|d^`%sYs8RGMge)P81m^T zAg>ccJ{tw(^w;1x{C?M|6p#nRkY7Xrc~A`bWfYM2iXs0L1>_+y^%_ z$bUou`Jfo`yC@(Z5<`9;1>|8Nq?1Ge`LGyLjso%#F{CpJ$RlD%R}_$siXmg7fP730 z>4^gJaWN!~0`dtlWI_~>Pl_SEQ9wQ=hD?eA@@X+-N)(XKh#|X00r{*LvPTq<&xs*> zMgjS}7_xU1kS~ZK`$hrzq8PG&6p$~8AqPYO`LY-?JqpNI#E^rdfP7U9IW!8$*Tj&+ zqkw!}44DxH{>|$gC(J-xfoTjRNvlV#x7PK)xe}oEQbk(?IVTFpkHnC3 zqk#Na3|SZj z;QVE{bFt7l)A^Oaxx;?X3xv+ug5QF;$N6=5$+vWL_WI@3&Tl%Dyx;k^aA&~}NqGIx z+J6@~e`~{;Bsp9Tx8@v#oy>8+@BYJ=6+XiES56#$9~ro8_yOk+`y9%MBi9qxh$9c( z2|F-5Nq5rQ*mF6aIKCs@-9*lFD^kbZiTR$;{k7eflN<@17705rW08HJNJZY~i2u=w zOzpHt*rOSX?2kn{_Bm31oFcud;xxjzKWkRlivK<`c-aBPg&iZA_NXobYqt@%A!{WT ztUck@#b6z01ggn89;_3>trrl<`JG<*$}dSQIhBxZhlk&#r0!SL14{4V2bBTvmkxhJ zhC@S)z=jyUUm0~+8MDv%doUb#NSRH@T}t77O3|`prPy2KO+KKM>{k{aR+fUAL$Sl< z`<2y)$>4p?&$(Zv#jn`gE0UiQyU+P0_gic6Ti{KJ=oi1w`Db9fZoje~ez`|!Jg78} za6F*2?pHQmPh#h1>{qrvbXYm&u(D(Le&@GEBbmvuBMp<6%me>-MMO_$-HblQ2Uv%`m6mrVy*P{F!2guJ*;D;sc8)Bh?-`?8lVp7h_%WRNsk)5 zp3t!dsskC;Q|dqyR=S$r5o@)jjv=gPbgV(@AcpmvI>>}ISRLFEtK8DdfaUyl@(^_h zbALe{Vsam<4(0BA3}PeIt~$;HG+rIwv1(f_Kt|PE`3z`+I)MSrRwtN% zCaM!VGTLSV3Nb2RK$Fx-3}~J@$pkc6o!pVpj_@&9yBy~;pegDU22`w0F#%0gr*;7H zk)7f@gKHr}nx;-;NTupD6Vh~bdWX9C$g!PNZV^M8q0V4POVk-Aq?zhW0jJ&GzQXWb z#*qA~pCPSK{U)RwHAjGSyyZC|)N`vCQm&fIkjm9u6H=aAuUsvF{IPgWhSKMDt!3u&`y_j(oSbGq!sE4 zhIF>N!i2O^T`6d%%PdHtEBIW7v`SsYkj__EnUGeis|B1cw;+Z3?m~uCu9h>Ti`8-y z(i(M*fYTM0r~DA7OBqr?4KSq3)qn}9Lah)WUDe4rekDVyR4W3~{qLTXSOIFe;l zxzTb39~^EB2LzmUs5=m&DiyPKY-chm;cB#7rNcyK?A2}pII!--~A$_bK zXF}So?iL_@YP8dR0;J>B;~CQL)#FV_d(=Gwq(2x)_Y06tP)}e;U#KUTkWN%jd7XgQ`A!gNPjbs z9y5PHR*t`u%pz}*PswMBmwYG1NePNqnkvng7C>4hwM&~Iy-qqH9fI_E>3!)##VdQ| zG&vp8iE@El2w4VvhU;y` z>rQm{cMnv&v6--og< zH_x|X__N~Ah4h*DcjDhyya}lZgA;~9TAt99&Ny2JO{tYqwLnL3{C^2hAholpn}v@cWnWUl{{m!zkW-x6=9pe4FLe zbh`cr_$^?w4jgtc(@F62zT6#6b@SQmTt5;Mc1}N!aH4Z2SdYL}ch})*CpNkr78A+F zR9r#?C>>5O)_W9N-5!g#V{4+3WCL1<=X9o#6q`O)zka0Kzu>3)VwL_?KU4L3{EJ2E z#qz4=lAc}gw_@}oy}O8^<6sj+gJCpBF6kQu6*HY^ae&h4?264L{iCF0ruAcBnWzo; z5vZBz{aAQF@ffZ3(tjk1W|}`Hritp{ACan=?vIUYP##Z){>YSd+I(~wK!*Pt@bxlq z)cAMdLld!^u{4Qf{F|y^uExK!45PPal2QN0s+gLU)y>uaZ(FfI^3nfYIC5_7Zs z6u6k8CFdv5H0I{{sqis1QQl9aiOkLPQ{rT5s#!mwrZP9zPmP!Cc2%=i4t_G{C)Q-< zX8S2}Gd11ZpJ3COoA0N}&(ws4KhY*MH{(y4qp2y2e!@*@ZqA=NPt)yW!B4zN&CU9A z;0jI4-w^mo$KD>Q=5G2W)ydRV)xV&wGI!T6tzM=sTl)*^GIO{666c&f5~+;b!EdZxGT-w`Ae@SbSeK*AfGh-!n;)ORz6|e zPg?#5>Kk6?w*Qejhu3?<|4_Zd>%QrKtnT6U-||0L|L`{0_CMMN;q9>ff4CjO+hXVc zcw2CismZFI{2 zw~?@o%8rc}T zj%<#-n{0{wj%@YhlWm^U$PUjNWM^C&IW}%R*&Vl!93S@s*+UD+UV1h;mA*^Ph#x}E ziEk$7$KOXTNKnXy3B}~1gbT^V3BMtiB#tDPCT=8`B|c0p_r{Scyo<7V4z?R0lbfI-lH^dOo>7^#gLG+X(V#w|4Saw}%M(l>%iq>@@!wak>8P`UmWP|0e0} z`j(6&l9WJVT;GAtNxmh0UH=4~Ls|g3??LC1CX+O1v5`cPHsNk5po@_zNSa#$om)Bt zIvI2x=^D^EKo={02s$U|sPru86wt-V>7a9gETfuj5nDbq8G^=UmYB09}9QSkS4U z>*qWVbUi^gz_}B2y+D`d#QOFIUAhzN+Xr+5l~JJU3%bEd576}k-5{kNbp1g$R9OPL zG|&xEE&$yC&<$61fo>q^hPmDbT{`G8T#tfo5a>q0nHcwA(2aunr@4oKZe(me=!SxB zOzddT4FlciSZu%Hpv#KI_8S4Z%-Ay3wE;=cxtV z7|>1hl!7i3bQ3(-R#~8%?7_Cm2Hhmjx1bvfx~ZOzKsOF_Q{s@zc+gFcLoO3QH!bdT z&`kv0%(%^DxHWhSv6zet(bh#AUYC7m|n3KIlpl9spet=oTkj z54vK|ElR}Qgcg8qX~I{aTL`)(i3>qj0=ngiQ$SY=x@CzMgRTs8D-(|g-6GJfNc;$N zi$S+K@deN=0o^L^XwWSM-5Re7x@Dj%_ihH=a?n+HD?zscbOG-X(5(brmG@TAtpZ)8 zFCKKOL09elE9lBW7xXOw-5SuX_4z>;09}pmO3+n+Zk_LB&{cx2*7q6csz6ugdku6! z(5+7z2fAv|H6--|T@C2!la2%3TF^Bm)q}1Ubd5>Rfo>h>T9OWcZawIlle>ei4s>nF z66oqd*P0vvT?6PgB+mm~Bk09M?&}{(S_LNr8Z3NvhDX)NT6X8+cZ2SfZW#B+gYIPfg%AE~D_)O#kNX7e2VRolhg&4P?+riXK7$basSpBN zS)C6u2X2H3#7lhe10l&I6>f~NqzCCqdJ&cMAuiGv9Q#9>2I)XZ(;*#9hQiG=mW*IH zKKBKX$|Tl(A*69|-UEMet*{x@MW84m3i&N4-c|CTsCSi#$|Pm7GDVpNf0Hy_K&dcv z6`HPEsWEgl?o){aJOfI#`(pSxm1$6&Yw@>GB>edl34d{g|JVtcDSu6fA4Lv|ToidI z@=?q}F&o7k6a^^eqL_!G5XF2HMJS3s76tPVl9eV6zfo|M^T5O9z_F+adHzOjhJgf(Tt)6 zMJtLn6zwQBpxB6F6N=3!wxHOGVjGHMP;5uB1I11h$D-JSVi$_zQ0zu=Jc<)goQUEi z6njyejN%j&r=mCw#px){KyfCDvrwFk;v5v`qBsx5`6w0L4KR_o6t2;yx7jqj&(tgD4(CaTvwJC>}v^1jVB$9z*dsiYHJ!iQ*{~PlJ#f zu|uE1!)H-EhvIn@FQ9l4#Y-q&M)3-YS5dr%;&l{npm-C-L=f^W`8Xn^W_VO zd?MyfNAZOGBq8{dR|J2$ir_D2$s6R2g#CIK`%x)J4~I$|z2Nu3oW&>>pje2a1Vt%| zG8BtYEJm>e#ZnZ@P%KBW0>w%ct5B>)QI28_iU5iV6qP8dPy|s_qo_f#7DX+Jbtu-O zs6$bYq5(xCiY64zC|XdoqG&_Wj$#9fjVLyu*o_l-aid`s< zL$Mph@hJA7I040pC{9AL7sbgaPC;=hiqlY>j^Ydy=b|_h#aSrMMsW^`^H7|R;sO*G zqPPgf#V9U8aVd(+P+X4U3KUnOxC+J9D6T%<@Fb>h$JI`M~ao%qwW&KFR;h~gy_FQa$`#j7Y@L-9I_ zH&DEZ;w=l|;q1cFG3yNb<>_Tw@ic?S| zp*R!8c_=PMaRrKNQQU;$b`(fsh7c zZW-oApcsRP)p8AyZ-k-B;c>)C_+xRB!{