diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir index bccf1b0b..443995be 100644 --- a/el2_ifu_mem_ctl.fir +++ b/el2_ifu_mem_ctl.fir @@ -72,6 +72,30 @@ circuit el2_ifu_mem_ctl : clkhdr.EN <= io.en @[el2_lib.scala 455:18] clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + module el2_ifu_mem_ctl : input clock : Clock input reset : UInt<1> @@ -149,6 +173,12 @@ circuit el2_ifu_mem_ctl : ic_ignore_2nd_miss_f <= UInt<1>("h00") wire ic_debug_rd_en_ff : UInt<1> ic_debug_rd_en_ff <= UInt<1>("h00") + inst rvclkhdr of rvclkhdr @[el2_lib.scala 461:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 462:17] + rvclkhdr.io.en <= ic_debug_rd_en_ff @[el2_lib.scala 463:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 185:30] flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 185:30] node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 186:53] @@ -156,18 +186,18 @@ circuit el2_ifu_mem_ctl : node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 186:86] node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 186:107] node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 187:42] - inst rvclkhdr of rvclkhdr @[el2_lib.scala 461:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 462:17] - rvclkhdr.io.en <= debug_c1_clken @[el2_lib.scala 463:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 461:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 462:17] - rvclkhdr_1.io.en <= fetch_bf_f_c1_clken @[el2_lib.scala 463:16] + rvclkhdr_1.io.en <= debug_c1_clken @[el2_lib.scala 463:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 461:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 462:17] + rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[el2_lib.scala 463:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] node _T_3 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 190:52] node _T_4 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 190:78] node _T_5 = and(_T_3, _T_4) @[el2_ifu_mem_ctl.scala 190:55] @@ -438,18 +468,18 @@ circuit el2_ifu_mem_ctl : node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 262:28] node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 263:56] node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 263:37] - reg _T_200 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 264:67] + reg _T_200 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 264:67] _T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 264:67] uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 264:28] node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 265:43] node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 265:24] - reg _T_202 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 266:54] + reg _T_202 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 266:54] _T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 266:54] imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 266:15] - reg _T_203 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 267:64] + reg _T_203 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 267:64] _T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 267:64] way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 267:25] - reg _T_204 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 268:58] + reg _T_204 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 268:58] _T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 268:58] tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 268:19] node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15] @@ -593,14 +623,14 @@ circuit el2_ifu_mem_ctl : reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 306:15] reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 307:37] fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 307:37] - reg _T_301 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 308:63] + reg _T_301 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 308:63] _T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 308:63] ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 308:24] node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 309:37] - reg _T_302 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:62] + reg _T_302 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:62] _T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 310:62] uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 310:23] - reg _T_303 : UInt, rvclkhdr_1.io.l1clk @[el2_ifu_mem_ctl.scala 311:49] + reg _T_303 : UInt, rvclkhdr_2.io.l1clk @[el2_ifu_mem_ctl.scala 311:49] _T_303 <= imb_in @[el2_ifu_mem_ctl.scala 311:49] imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 311:10] wire miss_addr : UInt<26> @@ -613,19 +643,19 @@ circuit el2_ifu_mem_ctl : node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 313:25] node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 315:57] node _T_310 = or(_T_309, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 315:73] - inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 461:22] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 462:17] - rvclkhdr_2.io.en <= _T_310 @[el2_lib.scala 463:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] - reg _T_311 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 316:48] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 461:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 462:17] + rvclkhdr_3.io.en <= _T_310 @[el2_lib.scala 463:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 464:23] + reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 316:48] _T_311 <= miss_addr_in @[el2_ifu_mem_ctl.scala 316:48] miss_addr <= _T_311 @[el2_ifu_mem_ctl.scala 316:13] - reg _T_312 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:59] + reg _T_312 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:59] _T_312 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 317:59] way_status_mb_ff <= _T_312 @[el2_ifu_mem_ctl.scala 317:20] - reg _T_313 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:53] + reg _T_313 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:53] _T_313 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 318:53] tagv_mb_ff <= _T_313 @[el2_ifu_mem_ctl.scala 318:14] wire stream_miss_f : UInt<1> @@ -641,15 +671,15 @@ circuit el2_ifu_mem_ctl : node _T_319 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:44] node _T_320 = and(ifc_fetch_req_f_raw, _T_319) @[el2_ifu_mem_ctl.scala 322:42] ifc_fetch_req_f <= _T_320 @[el2_ifu_mem_ctl.scala 322:19] - reg _T_321 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 323:60] + reg _T_321 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 323:60] _T_321 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 323:60] ifc_iccm_access_f <= _T_321 @[el2_ifu_mem_ctl.scala 323:21] wire ifc_region_acc_fault_final_bf : UInt<1> ifc_region_acc_fault_final_bf <= UInt<1>("h00") - reg _T_322 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 325:71] + reg _T_322 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 325:71] _T_322 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 325:71] ifc_region_acc_fault_final_f <= _T_322 @[el2_ifu_mem_ctl.scala 325:32] - reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 326:68] + reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 326:68] ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 326:68] node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58] node _T_323 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 328:38] @@ -1985,10 +2015,8 @@ circuit el2_ifu_mem_ctl : node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 29:58] node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 29:58] node ifu_ic_debug_rd_data_in = mux(_T_1201, _T_1210, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 351:36] - reg _T_1211 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ic_debug_rd_en_ff : @[Reg.scala 28:19] - _T_1211 <= ifu_ic_debug_rd_data_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] + reg _T_1211 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 354:63] + _T_1211 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 354:63] io.ifu_ic_debug_rd_data <= _T_1211 @[el2_ifu_mem_ctl.scala 354:27] node _T_1212 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 355:74] node _T_1213 = xorr(_T_1212) @[el2_lib.scala 201:13] @@ -3756,7 +3784,7 @@ circuit el2_ifu_mem_ctl : node _T_2614 = mux(bus_cmd_sent, _T_2613, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 603:12] node _T_2615 = mux(scnd_miss_req_q, _T_2611, _T_2614) @[el2_ifu_mem_ctl.scala 602:10] node bus_new_rd_addr_count = mux(_T_2609, _T_2610, _T_2615) @[el2_ifu_mem_ctl.scala 601:34] - reg _T_2616 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 604:55] + reg _T_2616 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 604:55] _T_2616 <= bus_new_rd_addr_count @[el2_ifu_mem_ctl.scala 604:55] bus_rd_addr_count <= _T_2616 @[el2_ifu_mem_ctl.scala 604:21] node _T_2617 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 606:48] @@ -3786,7 +3814,7 @@ circuit el2_ifu_mem_ctl : node _T_2636 = or(_T_2635, _T_2633) @[Mux.scala 27:72] wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72] bus_new_cmd_beat_count <= _T_2636 @[Mux.scala 27:72] - reg _T_2637 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_2637 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bus_cmd_beat_en : @[Reg.scala 28:19] _T_2637 <= bus_new_cmd_beat_count @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -13563,10 +13591,10 @@ circuit el2_ifu_mem_ctl : node _T_10418 = and(_T_10417, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 830:90] ic_debug_tag_wr_en <= _T_10418 @[el2_ifu_mem_ctl.scala 830:22] node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 831:53] - reg _T_10419 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 832:53] + reg _T_10419 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 832:53] _T_10419 <= io.ic_debug_way @[el2_ifu_mem_ctl.scala 832:53] ic_debug_way_ff <= _T_10419 @[el2_ifu_mem_ctl.scala 832:19] - reg _T_10420 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 833:63] + reg _T_10420 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 833:63] _T_10420 <= ic_debug_ict_array_sel_in @[el2_ifu_mem_ctl.scala 833:63] ic_debug_ict_array_sel_ff <= _T_10420 @[el2_ifu_mem_ctl.scala 833:29] reg _T_10421 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 834:54] diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v index d2c908b7..c3b0373c 100644 --- a/el2_ifu_mem_ctl.v +++ b/el2_ifu_mem_ctl.v @@ -627,6 +627,10 @@ module el2_ifu_mem_ctl( wire rvclkhdr_2_io_clk; // @[el2_lib.scala 461:22] wire rvclkhdr_2_io_en; // @[el2_lib.scala 461:22] wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 461:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 461:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 461:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 461:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 461:22] reg flush_final_f; // @[el2_ifu_mem_ctl.scala 185:30] reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 321:36] wire _T_319 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 322:44] @@ -641,24 +645,24 @@ module el2_ifu_mem_ctl( wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 187:42] wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58] reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 308:63] - wire [4:0] _GEN_461 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 666:53] - wire [4:0] ic_fetch_val_shift_right = _GEN_461 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 666:53] - wire [1:0] _GEN_462 = {{1'd0}, _T_319}; // @[el2_ifu_mem_ctl.scala 669:91] - wire [1:0] _T_3095 = ic_fetch_val_shift_right[3:2] & _GEN_462; // @[el2_ifu_mem_ctl.scala 669:91] + wire [4:0] _GEN_460 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 666:53] + wire [4:0] ic_fetch_val_shift_right = _GEN_460 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 666:53] + wire [1:0] _GEN_461 = {{1'd0}, _T_319}; // @[el2_ifu_mem_ctl.scala 669:91] + wire [1:0] _T_3095 = ic_fetch_val_shift_right[3:2] & _GEN_461; // @[el2_ifu_mem_ctl.scala 669:91] reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 323:60] wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 275:46] - wire [1:0] _GEN_463 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 669:113] - wire [1:0] _T_3096 = _T_3095 & _GEN_463; // @[el2_ifu_mem_ctl.scala 669:113] + wire [1:0] _GEN_462 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 669:113] + wire [1:0] _T_3096 = _T_3095 & _GEN_462; // @[el2_ifu_mem_ctl.scala 669:113] reg iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 655:59] - wire [1:0] _GEN_464 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 669:130] - wire [1:0] _T_3097 = _T_3096 | _GEN_464; // @[el2_ifu_mem_ctl.scala 669:130] + wire [1:0] _GEN_463 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 669:130] + wire [1:0] _T_3097 = _T_3096 | _GEN_463; // @[el2_ifu_mem_ctl.scala 669:130] wire _T_3098 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 669:154] - wire [1:0] _GEN_465 = {{1'd0}, _T_3098}; // @[el2_ifu_mem_ctl.scala 669:152] - wire [1:0] _T_3099 = _T_3097 & _GEN_465; // @[el2_ifu_mem_ctl.scala 669:152] - wire [1:0] _T_3088 = ic_fetch_val_shift_right[1:0] & _GEN_462; // @[el2_ifu_mem_ctl.scala 669:91] - wire [1:0] _T_3089 = _T_3088 & _GEN_463; // @[el2_ifu_mem_ctl.scala 669:113] - wire [1:0] _T_3090 = _T_3089 | _GEN_464; // @[el2_ifu_mem_ctl.scala 669:130] - wire [1:0] _T_3092 = _T_3090 & _GEN_465; // @[el2_ifu_mem_ctl.scala 669:152] + wire [1:0] _GEN_464 = {{1'd0}, _T_3098}; // @[el2_ifu_mem_ctl.scala 669:152] + wire [1:0] _T_3099 = _T_3097 & _GEN_464; // @[el2_ifu_mem_ctl.scala 669:152] + wire [1:0] _T_3088 = ic_fetch_val_shift_right[1:0] & _GEN_461; // @[el2_ifu_mem_ctl.scala 669:91] + wire [1:0] _T_3089 = _T_3088 & _GEN_462; // @[el2_ifu_mem_ctl.scala 669:113] + wire [1:0] _T_3090 = _T_3089 | _GEN_463; // @[el2_ifu_mem_ctl.scala 669:130] + wire [1:0] _T_3092 = _T_3090 & _GEN_464; // @[el2_ifu_mem_ctl.scala 669:152] wire [3:0] iccm_ecc_word_enable = {_T_3099,_T_3092}; // @[Cat.scala 29:58] wire _T_3199 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 311:30] wire _T_3200 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 311:44] @@ -745,9 +749,9 @@ module el2_ifu_mem_ctl( wire _T_2539 = ~io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 534:69] wire _T_2540 = _T_2538 & _T_2539; // @[el2_ifu_mem_ctl.scala 534:67] wire _T_2541 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30] - wire _GEN_55 = _T_2524 ? _T_2540 : _T_2541; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_2497 ? _T_2523 : _GEN_55; // @[Conditional.scala 39:67] - wire err_stop_fetch = _T_2492 ? 1'h0 : _GEN_59; // @[Conditional.scala 40:58] + wire _GEN_54 = _T_2524 ? _T_2540 : _T_2541; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_2497 ? _T_2523 : _GEN_54; // @[Conditional.scala 39:67] + wire err_stop_fetch = _T_2492 ? 1'h0 : _GEN_58; // @[Conditional.scala 40:58] wire _T_11 = _T_10 | err_stop_fetch; // @[el2_ifu_mem_ctl.scala 192:112] wire _T_13 = io_ifu_axi_rvalid & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 194:44] wire _T_14 = _T_13 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 194:65] @@ -1919,8 +1923,8 @@ module el2_ifu_mem_ctl( wire _T_1505 = _T_1504 | _T_1498; // @[Mux.scala 27:72] wire _T_1507 = _T_1474 & _T_1505; // @[el2_ifu_mem_ctl.scala 418:69] wire _T_1508 = _T_1470 | _T_1507; // @[el2_ifu_mem_ctl.scala 417:94] - wire [4:0] _GEN_470 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 419:95] - wire _T_1511 = _GEN_470 == 5'h1f; // @[el2_ifu_mem_ctl.scala 419:95] + wire [4:0] _GEN_469 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 419:95] + wire _T_1511 = _GEN_469 == 5'h1f; // @[el2_ifu_mem_ctl.scala 419:95] wire _T_1512 = bypass_valid_value_check & _T_1511; // @[el2_ifu_mem_ctl.scala 419:56] wire bypass_data_ready_in = _T_1508 | _T_1512; // @[el2_ifu_mem_ctl.scala 418:181] wire _T_1513 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 423:53] @@ -2757,7 +2761,7 @@ module el2_ifu_mem_ctl( wire [1:0] _T_10393 = ic_tag_valid_unq & _T_10392; // @[el2_ifu_mem_ctl.scala 815:48] wire ic_debug_tag_val_rd_out = |_T_10393; // @[el2_ifu_mem_ctl.scala 815:115] wire [65:0] _T_1210 = {2'h0,io_ictag_debug_rd_data[25:21],32'h0,io_ictag_debug_rd_data[20:0],1'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58] - reg [70:0] _T_1211; // @[Reg.scala 27:20] + reg [70:0] _T_1211; // @[el2_ifu_mem_ctl.scala 354:63] wire ifu_wr_cumulative_err = ifu_wr_cumulative_err_data & _T_2593; // @[el2_ifu_mem_ctl.scala 365:80] wire _T_1249 = ~ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 370:98] wire sel_byp_data = _T_1253 & _T_1249; // @[el2_ifu_mem_ctl.scala 370:96] @@ -2994,10 +2998,10 @@ module el2_ifu_mem_ctl( wire [79:0] ic_byp_data_only_pre_new = _T_1628 ? _T_1870 : _T_2112; // @[el2_ifu_mem_ctl.scala 441:37] wire [79:0] _T_2117 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58] wire [79:0] ic_byp_data_only_new = _T_2115 ? ic_byp_data_only_pre_new : _T_2117; // @[el2_ifu_mem_ctl.scala 445:30] - wire [79:0] _GEN_471 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 377:114] - wire [79:0] _T_1264 = _GEN_471 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 377:114] - wire [79:0] _GEN_472 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 377:88] - wire [79:0] ic_premux_data_temp = _GEN_472 | _T_1264; // @[el2_ifu_mem_ctl.scala 377:88] + wire [79:0] _GEN_470 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 377:114] + wire [79:0] _T_1264 = _GEN_470 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 377:114] + wire [79:0] _GEN_471 = {{16'd0}, _T_1261}; // @[el2_ifu_mem_ctl.scala 377:88] + wire [79:0] ic_premux_data_temp = _GEN_471 | _T_1264; // @[el2_ifu_mem_ctl.scala 377:88] wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[el2_ifu_mem_ctl.scala 384:38] wire [1:0] _T_1273 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 388:8] wire _T_1275 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[el2_ifu_mem_ctl.scala 390:45] @@ -3037,14 +3041,14 @@ module el2_ifu_mem_ctl( wire _T_2482 = 3'h2 == perr_state; // @[Conditional.scala 37:30] wire _T_2488 = 3'h4 == perr_state; // @[Conditional.scala 37:30] wire _T_2490 = 3'h3 == perr_state; // @[Conditional.scala 37:30] - wire _GEN_39 = _T_2488 | _T_2490; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_2482 ? _T_2480 : _GEN_39; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_2479 ? _T_2480 : _GEN_41; // @[Conditional.scala 39:67] - wire perr_state_en = _T_2467 ? _T_2478 : _GEN_43; // @[Conditional.scala 40:58] + wire _GEN_38 = _T_2488 | _T_2490; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_2482 ? _T_2480 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_42 = _T_2479 ? _T_2480 : _GEN_40; // @[Conditional.scala 39:67] + wire perr_state_en = _T_2467 ? _T_2478 : _GEN_42; // @[Conditional.scala 40:58] wire perr_sb_write_status = _T_2467 & perr_state_en; // @[Conditional.scala 40:58] wire _T_2481 = io_dec_tlu_flush_lower_wb & io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 496:56] - wire _GEN_44 = _T_2479 & _T_2481; // @[Conditional.scala 39:67] - wire perr_sel_invalidate = _T_2467 ? 1'h0 : _GEN_44; // @[Conditional.scala 40:58] + wire _GEN_43 = _T_2479 & _T_2481; // @[Conditional.scala 39:67] + wire perr_sel_invalidate = _T_2467 ? 1'h0 : _GEN_43; // @[Conditional.scala 40:58] wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 481:58] wire _T_2464 = ~dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 480:49] @@ -3064,12 +3068,12 @@ module el2_ifu_mem_ctl( wire _T_2543 = io_dec_tlu_flush_lower_wb & _T_2542; // @[el2_ifu_mem_ctl.scala 538:60] wire _T_2544 = _T_2543 | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 538:88] wire _T_2545 = _T_2544 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 538:115] - wire _GEN_51 = _T_2541 & _T_2499; // @[Conditional.scala 39:67] - wire _GEN_54 = _T_2524 ? _T_2535 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_2524 | _T_2541; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_2497 ? _T_2515 : _GEN_54; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_2497 | _GEN_56; // @[Conditional.scala 39:67] - wire err_stop_state_en = _T_2492 ? _T_2496 : _GEN_58; // @[Conditional.scala 40:58] + wire _GEN_50 = _T_2541 & _T_2499; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_2524 ? _T_2535 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_2524 | _T_2541; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_2497 ? _T_2515 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_2497 | _GEN_55; // @[Conditional.scala 39:67] + wire err_stop_state_en = _T_2492 ? _T_2496 : _GEN_57; // @[Conditional.scala 40:58] reg ifu_bus_cmd_valid; // @[Reg.scala 27:20] wire _T_2557 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 555:64] wire _T_2559 = _T_2557 & _T_2589; // @[el2_ifu_mem_ctl.scala 555:85] @@ -5165,6 +5169,12 @@ module el2_ifu_mem_ctl( .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 461:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 329:26] assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[el2_ifu_mem_ctl.scala 328:22] assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 192:20] @@ -5239,16 +5249,19 @@ module el2_ifu_mem_ctl( assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 381:25] assign io_ifu_ic_debug_rd_data_valid = _T_10423; // @[el2_ifu_mem_ctl.scala 835:33] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2464; // @[el2_ifu_mem_ctl.scala 480:27] - assign io_iccm_correction_state = _T_2492 ? 1'h0 : _GEN_60; // @[el2_ifu_mem_ctl.scala 515:28 el2_ifu_mem_ctl.scala 528:32 el2_ifu_mem_ctl.scala 535:32 el2_ifu_mem_ctl.scala 542:32] + assign io_iccm_correction_state = _T_2492 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 515:28 el2_ifu_mem_ctl.scala 528:32 el2_ifu_mem_ctl.scala 535:32 el2_ifu_mem_ctl.scala 542:32] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 462:17] - assign rvclkhdr_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 463:16] + assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[el2_lib.scala 463:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 464:23] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 462:17] - assign rvclkhdr_1_io_en = _T_2 | scnd_miss_req; // @[el2_lib.scala 463:16] + assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 463:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 464:23] assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 462:17] - assign rvclkhdr_2_io_en = _T_309 | io_dec_tlu_force_halt; // @[el2_lib.scala 463:16] + assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[el2_lib.scala 463:16] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 464:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 462:17] + assign rvclkhdr_3_io_en = _T_309 | io_dec_tlu_force_halt; // @[el2_lib.scala 463:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 464:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -8347,15 +8360,6 @@ end // initial end else if (_T_9039) begin ic_tag_valid_out_0_127 <= _T_5238; end - if (reset) begin - _T_1211 <= 71'h0; - end else if (ic_debug_rd_en_ff) begin - if (ic_debug_ict_array_sel_ff) begin - _T_1211 <= {{5'd0}, _T_1210}; - end else begin - _T_1211 <= io_ic_debug_rd_data; - end - end if (reset) begin ifu_bus_cmd_valid <= 1'h0; end else if (_T_2566) begin @@ -8604,7 +8608,7 @@ end // initial _T_10423 <= ic_debug_rd_en_ff; end end - always @(posedge rvclkhdr_1_io_l1clk) begin + always @(posedge rvclkhdr_2_io_l1clk) begin if (reset) begin ifu_fetch_addr_int_f <= 31'h0; end else begin @@ -8716,7 +8720,7 @@ end // initial _T_10402 <= bus_cmd_sent; end end - always @(posedge rvclkhdr_2_io_l1clk) begin + always @(posedge rvclkhdr_3_io_l1clk) begin if (reset) begin miss_addr <= 26'h0; end else if (_T_231) begin @@ -8739,7 +8743,7 @@ end // initial bus_cmd_beat_count <= bus_new_cmd_beat_count; end end - always @(posedge rvclkhdr_io_l1clk) begin + always @(posedge rvclkhdr_1_io_l1clk) begin if (reset) begin ic_debug_ict_array_sel_ff <= 1'h0; end else begin @@ -8751,4 +8755,13 @@ end // initial ic_debug_way_ff <= io_ic_debug_way; end end + always @(posedge rvclkhdr_io_l1clk) begin + if (reset) begin + _T_1211 <= 71'h0; + end else if (ic_debug_ict_array_sel_ff) begin + _T_1211 <= {{5'd0}, _T_1210}; + end else begin + _T_1211 <= io_ic_debug_rd_data; + end + end endmodule diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala index f1db9431..1d238cf9 100644 --- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -181,7 +181,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val ic_miss_under_miss_f = WireInit(Bool(), false.B) val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B) val ic_debug_rd_en_ff = WireInit(Bool(), false.B) - + val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode) val flush_final_f = RegNext(io.exu_flush_final, 0.U) val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en @@ -351,7 +351,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , io.ic_debug_rd_data) - io.ifu_ic_debug_rd_data := RegEnable(ifu_ic_debug_rd_data_in, 0.U, ic_debug_rd_en_ff) + io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)} val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class index 44746c84..dcb6f095 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class index 588589f2..381b32e8 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem$.class and b/target/scala-2.12/classes/ifu/ifu_mem$.class differ