Update el2_lsu_addrcheck.scala
This commit is contained in:
Junaid Ahmed
GitHub
parent
2da85e1800
commit
5cc210e06d
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@ -1,194 +1,159 @@
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package lsu
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import include._
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import lib._
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import snapshot._
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import chisel3._
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import chisel3.util._
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import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
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import chisel3.experimental.ChiselEnum
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import chisel3.experimental.{withClock, withReset, withClockAndReset}
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import chisel3.experimental.BundleLiterals._
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import chisel3.tester._
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import chisel3.tester.RawTester.test
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import chisel3.util.HasBlackBoxResource
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class el2_lsu_addrcheck extends Module
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{
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val io = IO(new Bundle{
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val lsu_c2_m_clk = Input(Clock())
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//val rst_l = IO(Input(1.W)) //implicit
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val start_addr_d = Input(UInt(32.W))
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val end_addr_d = Input(UInt(32.W))
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val lsu_pkt_d = Input(new el2_lsu_pkt_t)
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val dec_tlu_mrac_ff = Input(UInt(32.W))
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val rs1_region_d = Input(UInt(4.W))
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val rs1_d = Input(UInt(32.W))
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val is_sideeffects_m = Output(UInt(1.W))
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val addr_in_dccm_d = Output(UInt(1.W))
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val addr_in_pic_d = Output(UInt(1.W))
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val addr_external_d = Output(UInt(1.W))
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val access_fault_d = Output(UInt(1.W))
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val misaligned_fault_d = Output(UInt(1.W))
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val exc_mscause_d = Output(UInt(4.W))
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val fir_dccm_access_error_d = Output(UInt(1.W))
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val fir_nondccm_access_error_d = Output(UInt(1.W))
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val scan_mode = Input(UInt(1.W))
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})
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{val io = IO(new Bundle{
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val lsu_c2_m_clk = Input(Clock())
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val start_addr_d = Input(UInt(32.W))
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val end_addr_d = Input(UInt(32.W))
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val lsu_pkt_d = Input(new el2_lsu_pkt_t)
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val dec_tlu_mrac_ff = Input(UInt(32.W))
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val rs1_region_d = Input(UInt(4.W))
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val rs1_d = Input(UInt(32.W))
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val is_sideeffects_m = Output(UInt(1.W))
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val addr_in_dccm_d = Output(UInt(1.W))
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val addr_in_pic_d = Output(UInt(1.W))
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val addr_external_d = Output(UInt(1.W))
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val access_fault_d = Output(UInt(1.W))
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val misaligned_fault_d = Output(UInt(1.W))
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val exc_mscause_d = Output(UInt(4.W))
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val fir_dccm_access_error_d = Output(UInt(1.W))
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val fir_nondccm_access_error_d = Output(UInt(1.W))
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val scan_mode = Input(UInt(1.W))})
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val start_addr_in_dccm_d = WireInit(0.U(1.W))
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val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
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val start_addr_in_dccm_d = WireInit(0.U(1.W))
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val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
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//DCCM check
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// Start address check
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if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
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val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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start_addr_dccm_rangecheck.io.addr := io.start_addr_d
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start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
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start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
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//DCCM check
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// Start address check
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if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
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val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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start_addr_dccm_rangecheck.io.addr := io.start_addr_d
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start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
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start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
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// End address check
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val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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end_addr_dccm_rangecheck.io.addr := io.end_addr_d
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end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
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end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
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}
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else{ //Gen_dccm_disable
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start_addr_in_dccm_d := 0.U
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start_addr_in_dccm_region_d := 0.U
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end_addr_in_dccm_d := 0.U
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end_addr_in_dccm_region_d := 0.U
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}
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val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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end_addr_dccm_rangecheck.io.addr := io.end_addr_d
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end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
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end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
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}
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else{ //Gen_dccm_disable
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start_addr_in_dccm_d := 0.U
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start_addr_in_dccm_region_d := 0.U
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end_addr_in_dccm_d := 0.U
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end_addr_in_dccm_region_d := 0.U
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}
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val addr_in_iccm = WireInit(0.U(1.W))
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if(pt1.ICCM_ENABLE == 1){ //check_iccm
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addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
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}
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else{
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addr_in_iccm := 1.U
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}
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val addr_in_iccm = WireInit(0.U(1.W))
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if(pt1.ICCM_ENABLE == 1){ //check_iccm
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addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
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}
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else{
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addr_in_iccm := 1.U
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}
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//PIC memory check
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//start address check
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val start_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
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val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
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val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
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val start_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
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val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
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val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
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//End address check
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val end_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
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val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
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val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
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val end_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
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val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
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val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
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val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
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val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === pt.DCCM_REGION) | (io.rs1_region_d(3,0) === pt.PIC_REGION) //base region
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io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
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io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
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val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
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val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === pt.DCCM_REGION) | (io.rs1_region_d(3,0) === pt.PIC_REGION) //base region
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io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
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io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
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io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
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val csr_idx = Cat(io.start_addr_d(31,28),"b1".U)
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val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
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val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === "b00".U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === "b0".U)) | io.lsu_pkt_d.by
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io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
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val csr_idx = Cat(io.start_addr_d(31,28),"b1".U)
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val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
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val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === "b00".U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === "b0".U)) | io.lsu_pkt_d.by
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val non_dccm_access_ok = (~(Cat(pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,
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pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7)).orR) |
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(((pt.DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | //0111
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(pt.DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | //1111
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(pt.DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | //1011
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(pt.DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | //1000
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(pt.DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))
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&
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((pt.DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) |
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(pt.DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) |
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(pt.DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) |
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(pt.DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) |
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(pt.DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))))
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val non_dccm_access_ok = (~(Cat(pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,
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pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7)).orR) |
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(((pt.DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | //0111
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(pt.DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | //1111
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(pt.DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | //1011
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(pt.DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | //1000
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(pt.DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))
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&
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((pt.DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) |
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(pt.DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) |
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(pt.DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) |
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(pt.DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) |
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(pt.DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))))
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val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
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val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) != "b00".U) | ~io.lsu_pkt_d.word))
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val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
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val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) != 0.U(2.W)) | ~io.lsu_pkt_d.word))
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val unmapped_access_fault_d = WireInit(1.U(1.W))
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val mpu_access_fault_d = WireInit(1.U(1.W))
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if(pt1.DCCM_REGION == pt1.PIC_REGION){
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unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(start_addr_in_dccm_d & end_addr_in_pic_d) |
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// 0. DCCM -> PIC cross when DCCM/PIC in same region
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(start_addr_in_pic_d & end_addr_in_dccm_d))
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// 0. DCCM -> PIC cross when DCCM/PIC in same region
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mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
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// 3. Address is not in a populated non-dccm region
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}
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val unmapped_access_fault_d = WireInit(1.U(1.W))
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val mpu_access_fault_d = WireInit(1.U(1.W))
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else{
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unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
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(start_addr_in_pic_region_d & ~start_addr_in_pic_d) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d))
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mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
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// 3. Address is not in a populated non-dccm region
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}
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if(pt1.DCCM_REGION == pt1.PIC_REGION){
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unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(start_addr_in_dccm_d & end_addr_in_pic_d) |
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// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||
(start_addr_in_pic_d & end_addr_in_dccm_d))
|
||||
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||
|
||||
|
||||
|
||||
mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
|
||||
// 3. Address is not in a populated non-dccm region
|
||||
}
|
||||
|
||||
else{
|
||||
|
||||
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |
|
||||
// 0. Addr in dccm region but not in dccm offset
|
||||
(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
|
||||
// 0. Addr in dccm region but not in dccm offset
|
||||
(start_addr_in_pic_region_d & ~start_addr_in_pic_d) |
|
||||
// 0. Addr in picm region but not in picm offset
|
||||
(end_addr_in_pic_region_d & ~end_addr_in_pic_d))
|
||||
|
||||
// 0. Addr in picm region but not in picm offset
|
||||
|
||||
|
||||
mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
|
||||
// 3. Address is not in a populated non-dccm region
|
||||
}
|
||||
|
||||
//check width of access_fault_mscause_d
|
||||
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
val access_fault_mscause_d = WireInit(0.U(4.W))
|
||||
access_fault_mscause_d := Mux(unmapped_access_fault_d.asBool, "b0010".U, Mux(mpu_access_fault_d.asBool, "b0011".U, Mux(regpred_access_fault_d.asBool, "b0101".U, Mux(picm_access_fault_d.asBool, "b0110".U, "b0000".U))))
|
||||
|
||||
|
||||
|
||||
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
|
||||
|
||||
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
|
||||
|
||||
val misaligned_fault_mscause_d = WireInit(0.U(4.W))
|
||||
misaligned_fault_mscause_d := Mux(regcross_misaligned_fault_d, "b0010".U, Mux(sideeffect_misaligned_fault_d.asBool, "b0001".U, "b0000".U))
|
||||
|
||||
|
||||
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
||||
|
||||
// Fast interrupt error logic
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |
|
||||
(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
|
||||
|
||||
|
||||
//rvdff #(.WIDTH(1)) is_sideeffects_mff (.din(is_sideeffects_d), .dout(io.is_sideeffects_m), .clk(lsu_c2_m_clk), .*);
|
||||
|
||||
|
||||
val is_sideeffects_mff = Module(new rvdff(1,0)) //TBD for clock and reset
|
||||
is_sideeffects_mff.io.din := is_sideeffects_d
|
||||
io.is_sideeffects_m := is_sideeffects_mff.io.dout
|
||||
|
||||
|
||||
|
||||
//is_sideeffects_m :=0.U
|
||||
// addr_in_dccm_d :=0.U
|
||||
// addr_in_pic_d :=0.U
|
||||
// addr_external_d :=0.U
|
||||
// access_fault_d :=0.U
|
||||
// misaligned_fault_d :=0.U
|
||||
// exc_mscause_d :=0.U
|
||||
// fir_dccm_access_error_d :=0.U
|
||||
// fir_nondccm_access_error_d :=0.U
|
||||
//check width of access_fault_mscause_d
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
|
||||
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
|
||||
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
|
||||
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d)} //TBD for clock and reset
|
||||
}
|
||||
|
||||
//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck))
|
||||
/*
|
||||
object main extends App{
|
||||
println("Generate Verilog")
|
||||
chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck)
|
||||
}
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue