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dma buf depth corrected

This commit is contained in:
​Laraib Khan 2021-02-23 10:11:22 +05:00
parent 5509edc39d
commit 5d42a80edf
4 changed files with 2520 additions and 48092 deletions
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28427
quasar_wrapper.fir
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22180
quasar_wrapper.v
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5
src/main/scala/lib/param.scala
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@ -2,7 +2,7 @@ package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
trait param { trait param {
val BHT_ADDR_HI = 0x09 val BHT_ADDR_HI = 0x09
val BHT_ADDR_LO = 0x02 val BHT_ADDR_LO = 0x02
val BHT_ARRAY_DEPTH = 0x0100 val BHT_ARRAY_DEPTH = 0x0100
val BHT_GHR_HASH_1 = 0x00 val BHT_GHR_HASH_1 = 0x00
@ -75,7 +75,7 @@ val BHT_ADDR_HI = 0x09
val DCCM_WIDTH_BITS = 0x02 val DCCM_WIDTH_BITS = 0x02
val DIV_BIT = 0x04 val DIV_BIT = 0x04
val DIV_NEW = 0x01 val DIV_NEW = 0x01
val DMA_BUF_DEPTH = 0x05a val DMA_BUF_DEPTH = 0x05
val DMA_BUS_ID = 0x001 val DMA_BUS_ID = 0x001
val DMA_BUS_PRTY = 0x02 val DMA_BUS_PRTY = 0x02
val DMA_BUS_TAG = 0x01 val DMA_BUS_TAG = 0x01
@ -176,5 +176,4 @@ val BHT_ADDR_HI = 0x09
val TIMER_LEGAL_EN = 0x01 val TIMER_LEGAL_EN = 0x01
val RV_FPGA_OPTIMIZE = 0x1 val RV_FPGA_OPTIMIZE = 0x1
} }

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target/scala-2.12/classes/lib/param.class
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