Delete RVC.scala
This commit is contained in:
Junaid Ahmed
GitHub
parent
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// See LICENSE.SiFive for license details.
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//package freechips.rocketchip.rocket
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package lib
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import chisel3._
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import chisel3.util._
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import chisel3.util.ImplicitConversions
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import chisel3.experimental._
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import Chisel.ImplicitConversions._
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//import freechips.rocketchip.config.Parameters
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//import freechips.rocketchip.tile._
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//import freechips.rocketchip.util._
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class ExpandedInstruction extends Bundle {
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val bits = UInt(32.W)
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val rd = UInt(5.W)
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val rs1 = UInt(5.W)
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val rs2 = UInt(5.W)
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val rs3 = UInt(5.W)
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}
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class RVCDecoder(x: UInt, xLen: Int) {
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def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
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val res = Wire(new ExpandedInstruction)
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res.bits := bits
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res.rd := rd
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res.rs1 := rs1
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res.rs2 := rs2
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res.rs3 := rs3
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res
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}
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def rs1p = Cat(1.U(2.W), x(9,7))
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def rs2p = Cat(1.U(2.W), x(4,2))
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def rs2 = x(6,2)
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def rd = x(11,7)
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def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
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def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
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def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
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def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
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def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
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def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
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def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
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def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
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def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
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def addiImm = Cat(Fill(7, x(12)), x(6,2))
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def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
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def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
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def shamt = Cat(x(12), x(6,2))
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def x0 = 0.U(5.W)
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def ra = 1.U(5.W)
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def sp = 2.U(5.W)
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def q0 = {
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def addi4spn = {
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val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
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inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
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}
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def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
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def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
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def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
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def flw = {
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if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
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else ld
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}
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def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
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def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
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def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
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def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
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def fsw = {
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if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
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else sd
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}
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Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
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}
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def q1 = {
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def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
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def addiw = {
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val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
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inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
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}
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def jal = {
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if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
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else addiw
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}
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def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
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def addi16sp = {
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val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
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inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
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}
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def lui = {
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val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
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val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
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Mux(rd === x0 || rd === sp, addi16sp, me)
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}
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def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
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def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
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def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
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def arith = {
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def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
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def srai = srli | (1 << 30).U
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def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
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def rtype = {
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val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
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val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
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val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
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Cat(rs2p, rs1p, funct, rs1p, opc) | sub
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}
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inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
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}
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Seq(addi, jal, li, lui, arith, j, beqz, bnez)
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}
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def q2 = {
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val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
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def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
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def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
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def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
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def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
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def flwsp = {
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if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
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else ldsp
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}
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def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
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def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
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def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
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def fswsp = {
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if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
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else sdsp
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}
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def jalr = {
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val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
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val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
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val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
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val reserved = Cat(jr >> 7, 0x1F.U(7.W))
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val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
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val jr_mv = Mux(rs2.orR, mv, jr_reserved)
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val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
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val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
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val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
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val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
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Mux(x(12), jalr_add, jr_mv)
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}
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Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
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}
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def q3 = Seq.fill(8)(passthrough)
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def passthrough = inst(x)
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def decode = {
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val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
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s(Cat(x(1,0), x(15,13)))
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}
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def changed_q0 = {
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def addi4spn = {
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val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
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inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
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}
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def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
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def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
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def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
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def flw = {
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if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
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else ld
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}
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def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
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def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
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def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
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def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
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def fsw = {
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if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
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else sd
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}
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addi4spn
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}
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def ret_q0 = VecInit(q0)
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def ret_q1 = q1
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def ret_q2 = q2
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def ret_q3 = q3
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}
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class RVCExpander( val XLen: Int, val usingCompressed: Boolean) extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(new ExpandedInstruction)
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val rvc = Output(Bool())
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val legal = Output(Bool())
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val waleed_out = Output(UInt(32.W))
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//val q1_Out = Output(new ExpandedInstruction)
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//val q2_Out = Output(new ExpandedInstruction)
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//val q3_Out = Output(new ExpandedInstruction)
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})
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if (usingCompressed) {
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io.rvc := io.in(1,0) =/= 3.U
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val inst = new RVCDecoder(io.in, XLen)
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io.out := inst.decode
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io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
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(!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
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(!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
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(!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
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(!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
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(!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
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(!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
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(!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
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(!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
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(!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
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(!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
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(!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
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io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
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(!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
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(!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
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io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
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(!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
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io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
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(!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
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(!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
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io.in(14)&(!io.in(13))&(!io.in(0))
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io.waleed_out := Mux(io.legal,io.out.bits,0.U)
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} else {
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io.rvc := false.B
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io.out := new RVCDecoder(io.in, XLen).passthrough
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}
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}
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