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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-03 10:44:15 +05:00
parent 86bb3d7c2c
commit 5e4f49b6b2
4 changed files with 65 additions and 65 deletions
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96
axi4_to_ahb.fir
View File

@ -545,14 +545,14 @@ circuit axi4_to_ahb :
node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62]
node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48]
node _T_86 = mux(_T_64, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_87 = mux(_T_67, UInt<1>("h01"), _T_86) @[Mux.scala 98:16]
node _T_88 = mux(_T_70, UInt<2>("h02"), _T_87) @[Mux.scala 98:16]
node _T_89 = mux(_T_73, UInt<2>("h03"), _T_88) @[Mux.scala 98:16]
node _T_90 = mux(_T_76, UInt<3>("h04"), _T_89) @[Mux.scala 98:16]
node _T_91 = mux(_T_79, UInt<3>("h05"), _T_90) @[Mux.scala 98:16]
node _T_92 = mux(_T_82, UInt<3>("h06"), _T_91) @[Mux.scala 98:16]
node _T_93 = mux(_T_85, UInt<3>("h07"), _T_92) @[Mux.scala 98:16]
node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16]
node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16]
node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16]
node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16]
node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16]
node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16]
node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16]
node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124]
node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30]
buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24]
@ -740,14 +740,14 @@ circuit axi4_to_ahb :
node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62]
node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48]
node _T_223 = mux(_T_201, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_224 = mux(_T_204, UInt<1>("h01"), _T_223) @[Mux.scala 98:16]
node _T_225 = mux(_T_207, UInt<2>("h02"), _T_224) @[Mux.scala 98:16]
node _T_226 = mux(_T_210, UInt<2>("h03"), _T_225) @[Mux.scala 98:16]
node _T_227 = mux(_T_213, UInt<3>("h04"), _T_226) @[Mux.scala 98:16]
node _T_228 = mux(_T_216, UInt<3>("h05"), _T_227) @[Mux.scala 98:16]
node _T_229 = mux(_T_219, UInt<3>("h06"), _T_228) @[Mux.scala 98:16]
node _T_230 = mux(_T_222, UInt<3>("h07"), _T_229) @[Mux.scala 98:16]
node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16]
node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16]
node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16]
node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16]
node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16]
node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16]
node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16]
node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30]
buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24]
node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65]
@ -781,14 +781,14 @@ circuit axi4_to_ahb :
node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62]
node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48]
node _T_263 = mux(_T_241, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_264 = mux(_T_244, UInt<1>("h01"), _T_263) @[Mux.scala 98:16]
node _T_265 = mux(_T_247, UInt<2>("h02"), _T_264) @[Mux.scala 98:16]
node _T_266 = mux(_T_250, UInt<2>("h03"), _T_265) @[Mux.scala 98:16]
node _T_267 = mux(_T_253, UInt<3>("h04"), _T_266) @[Mux.scala 98:16]
node _T_268 = mux(_T_256, UInt<3>("h05"), _T_267) @[Mux.scala 98:16]
node _T_269 = mux(_T_259, UInt<3>("h06"), _T_268) @[Mux.scala 98:16]
node _T_270 = mux(_T_262, UInt<3>("h07"), _T_269) @[Mux.scala 98:16]
node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16]
node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16]
node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16]
node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16]
node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16]
node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16]
node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16]
node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92]
node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92]
node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163]
@ -869,14 +869,14 @@ circuit axi4_to_ahb :
node _T_335 = bits(_T_310, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_336 = geq(UInt<3>("h07"), _T_313) @[axi4_to_ahb.scala 175:62]
node _T_337 = and(_T_335, _T_336) @[axi4_to_ahb.scala 175:48]
node _T_338 = mux(_T_316, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_339 = mux(_T_319, UInt<1>("h01"), _T_338) @[Mux.scala 98:16]
node _T_340 = mux(_T_322, UInt<2>("h02"), _T_339) @[Mux.scala 98:16]
node _T_341 = mux(_T_325, UInt<2>("h03"), _T_340) @[Mux.scala 98:16]
node _T_342 = mux(_T_328, UInt<3>("h04"), _T_341) @[Mux.scala 98:16]
node _T_343 = mux(_T_331, UInt<3>("h05"), _T_342) @[Mux.scala 98:16]
node _T_344 = mux(_T_334, UInt<3>("h06"), _T_343) @[Mux.scala 98:16]
node _T_345 = mux(_T_337, UInt<3>("h07"), _T_344) @[Mux.scala 98:16]
node _T_338 = mux(_T_337, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_339 = mux(_T_334, UInt<3>("h06"), _T_338) @[Mux.scala 98:16]
node _T_340 = mux(_T_331, UInt<3>("h05"), _T_339) @[Mux.scala 98:16]
node _T_341 = mux(_T_328, UInt<3>("h04"), _T_340) @[Mux.scala 98:16]
node _T_342 = mux(_T_325, UInt<2>("h03"), _T_341) @[Mux.scala 98:16]
node _T_343 = mux(_T_322, UInt<2>("h02"), _T_342) @[Mux.scala 98:16]
node _T_344 = mux(_T_319, UInt<1>("h01"), _T_343) @[Mux.scala 98:16]
node _T_345 = mux(_T_316, UInt<1>("h00"), _T_344) @[Mux.scala 98:16]
node _T_346 = dshr(buf_byteen, _T_345) @[axi4_to_ahb.scala 305:136]
node _T_347 = bits(_T_346, 0, 0) @[axi4_to_ahb.scala 305:136]
node _T_348 = eq(_T_347, UInt<1>("h00")) @[axi4_to_ahb.scala 305:205]
@ -933,14 +933,14 @@ circuit axi4_to_ahb :
node _T_393 = bits(_T_368, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_394 = geq(UInt<3>("h07"), _T_371) @[axi4_to_ahb.scala 175:62]
node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 175:48]
node _T_396 = mux(_T_374, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_397 = mux(_T_377, UInt<1>("h01"), _T_396) @[Mux.scala 98:16]
node _T_398 = mux(_T_380, UInt<2>("h02"), _T_397) @[Mux.scala 98:16]
node _T_399 = mux(_T_383, UInt<2>("h03"), _T_398) @[Mux.scala 98:16]
node _T_400 = mux(_T_386, UInt<3>("h04"), _T_399) @[Mux.scala 98:16]
node _T_401 = mux(_T_389, UInt<3>("h05"), _T_400) @[Mux.scala 98:16]
node _T_402 = mux(_T_392, UInt<3>("h06"), _T_401) @[Mux.scala 98:16]
node _T_403 = mux(_T_395, UInt<3>("h07"), _T_402) @[Mux.scala 98:16]
node _T_396 = mux(_T_395, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_397 = mux(_T_392, UInt<3>("h06"), _T_396) @[Mux.scala 98:16]
node _T_398 = mux(_T_389, UInt<3>("h05"), _T_397) @[Mux.scala 98:16]
node _T_399 = mux(_T_386, UInt<3>("h04"), _T_398) @[Mux.scala 98:16]
node _T_400 = mux(_T_383, UInt<2>("h03"), _T_399) @[Mux.scala 98:16]
node _T_401 = mux(_T_380, UInt<2>("h02"), _T_400) @[Mux.scala 98:16]
node _T_402 = mux(_T_377, UInt<1>("h01"), _T_401) @[Mux.scala 98:16]
node _T_403 = mux(_T_374, UInt<1>("h00"), _T_402) @[Mux.scala 98:16]
node _T_404 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:147]
node _T_405 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:165]
node _T_406 = add(_T_404, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52]
@ -970,14 +970,14 @@ circuit axi4_to_ahb :
node _T_430 = bits(_T_405, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_431 = geq(UInt<3>("h07"), _T_408) @[axi4_to_ahb.scala 175:62]
node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 175:48]
node _T_433 = mux(_T_411, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_434 = mux(_T_414, UInt<1>("h01"), _T_433) @[Mux.scala 98:16]
node _T_435 = mux(_T_417, UInt<2>("h02"), _T_434) @[Mux.scala 98:16]
node _T_436 = mux(_T_420, UInt<2>("h03"), _T_435) @[Mux.scala 98:16]
node _T_437 = mux(_T_423, UInt<3>("h04"), _T_436) @[Mux.scala 98:16]
node _T_438 = mux(_T_426, UInt<3>("h05"), _T_437) @[Mux.scala 98:16]
node _T_439 = mux(_T_429, UInt<3>("h06"), _T_438) @[Mux.scala 98:16]
node _T_440 = mux(_T_432, UInt<3>("h07"), _T_439) @[Mux.scala 98:16]
node _T_433 = mux(_T_432, UInt<3>("h07"), UInt<4>("h08")) @[Mux.scala 98:16]
node _T_434 = mux(_T_429, UInt<3>("h06"), _T_433) @[Mux.scala 98:16]
node _T_435 = mux(_T_426, UInt<3>("h05"), _T_434) @[Mux.scala 98:16]
node _T_436 = mux(_T_423, UInt<3>("h04"), _T_435) @[Mux.scala 98:16]
node _T_437 = mux(_T_420, UInt<2>("h03"), _T_436) @[Mux.scala 98:16]
node _T_438 = mux(_T_417, UInt<2>("h02"), _T_437) @[Mux.scala 98:16]
node _T_439 = mux(_T_414, UInt<1>("h01"), _T_438) @[Mux.scala 98:16]
node _T_440 = mux(_T_411, UInt<1>("h00"), _T_439) @[Mux.scala 98:16]
node _T_441 = mux(trxn_done, _T_440, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 311:102]
node _T_442 = mux(bypass_en, _T_403, _T_441) @[axi4_to_ahb.scala 311:30]
buf_cmd_byte_ptr <= _T_442 @[axi4_to_ahb.scala 311:24]

32
axi4_to_ahb.v
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@ -264,14 +264,14 @@ module axi4_to_ahb(
wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74]
wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38]
wire [3:0] _T_86 = wrbuf_byteen[0] ? 4'h0 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_87 = wrbuf_byteen[1] ? 4'h1 : _T_86; // @[Mux.scala 98:16]
wire [3:0] _T_88 = wrbuf_byteen[2] ? 4'h2 : _T_87; // @[Mux.scala 98:16]
wire [3:0] _T_89 = wrbuf_byteen[3] ? 4'h3 : _T_88; // @[Mux.scala 98:16]
wire [3:0] _T_90 = wrbuf_byteen[4] ? 4'h4 : _T_89; // @[Mux.scala 98:16]
wire [3:0] _T_91 = wrbuf_byteen[5] ? 4'h5 : _T_90; // @[Mux.scala 98:16]
wire [3:0] _T_92 = wrbuf_byteen[6] ? 4'h6 : _T_91; // @[Mux.scala 98:16]
wire [3:0] _T_93 = wrbuf_byteen[7] ? 4'h7 : _T_92; // @[Mux.scala 98:16]
wire [3:0] _T_86 = wrbuf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_87 = wrbuf_byteen[6] ? 4'h6 : _T_86; // @[Mux.scala 98:16]
wire [3:0] _T_88 = wrbuf_byteen[5] ? 4'h5 : _T_87; // @[Mux.scala 98:16]
wire [3:0] _T_89 = wrbuf_byteen[4] ? 4'h4 : _T_88; // @[Mux.scala 98:16]
wire [3:0] _T_90 = wrbuf_byteen[3] ? 4'h3 : _T_89; // @[Mux.scala 98:16]
wire [3:0] _T_91 = wrbuf_byteen[2] ? 4'h2 : _T_90; // @[Mux.scala 98:16]
wire [3:0] _T_92 = wrbuf_byteen[1] ? 4'h1 : _T_91; // @[Mux.scala 98:16]
wire [3:0] _T_93 = wrbuf_byteen[0] ? 4'h0 : _T_92; // @[Mux.scala 98:16]
wire [3:0] _T_95 = buf_write_in ? _T_93 : {{1'd0}, master_addr[2:0]}; // @[axi4_to_ahb.scala 233:30]
wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51]
wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33]
@ -321,14 +321,14 @@ module axi4_to_ahb(
wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48]
wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62]
wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48]
wire [3:0] _T_223 = _T_201 ? 4'h0 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_224 = _T_204 ? 4'h1 : _T_223; // @[Mux.scala 98:16]
wire [3:0] _T_225 = _T_207 ? 4'h2 : _T_224; // @[Mux.scala 98:16]
wire [3:0] _T_226 = _T_210 ? 4'h3 : _T_225; // @[Mux.scala 98:16]
wire [3:0] _T_227 = _T_213 ? 4'h4 : _T_226; // @[Mux.scala 98:16]
wire [3:0] _T_228 = _T_216 ? 4'h5 : _T_227; // @[Mux.scala 98:16]
wire [3:0] _T_229 = _T_219 ? 4'h6 : _T_228; // @[Mux.scala 98:16]
wire [3:0] _T_230 = buf_byteen[7] ? 4'h7 : _T_229; // @[Mux.scala 98:16]
wire [3:0] _T_223 = buf_byteen[7] ? 4'h7 : 4'h8; // @[Mux.scala 98:16]
wire [3:0] _T_224 = _T_219 ? 4'h6 : _T_223; // @[Mux.scala 98:16]
wire [3:0] _T_225 = _T_216 ? 4'h5 : _T_224; // @[Mux.scala 98:16]
wire [3:0] _T_226 = _T_213 ? 4'h4 : _T_225; // @[Mux.scala 98:16]
wire [3:0] _T_227 = _T_210 ? 4'h3 : _T_226; // @[Mux.scala 98:16]
wire [3:0] _T_228 = _T_207 ? 4'h2 : _T_227; // @[Mux.scala 98:16]
wire [3:0] _T_229 = _T_204 ? 4'h1 : _T_228; // @[Mux.scala 98:16]
wire [3:0] _T_230 = _T_201 ? 4'h0 : _T_229; // @[Mux.scala 98:16]
wire [3:0] _T_231 = trxn_done ? _T_230 : {{1'd0}, buf_cmd_byte_ptrQ}; // @[axi4_to_ahb.scala 291:30]
wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65]
reg buf_aligned; // @[Reg.scala 27:20]

2
src/main/scala/lib/axi4_to_ahb.scala
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@ -172,7 +172,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
}
def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U).reverse
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
MuxCase(8.U, temp)
}
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld

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target/scala-2.12/classes/lib/axi4_to_ahb.class
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