diff --git a/el2_dec_decode_ctl.fir b/el2_dec_decode_ctl.fir index 341c2abd..47fa8212 100644 --- a/el2_dec_decode_ctl.fir +++ b/el2_dec_decode_ctl.fir @@ -2573,11 +2573,11 @@ circuit el2_dec_decode_ctl : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -3005,14 +3005,14 @@ circuit el2_dec_decode_ctl : cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] + node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] @@ -3046,17 +3046,17 @@ circuit el2_dec_decode_ctl : cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_103 = eq(r_d_in.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:100] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] - when _T_107 : @[el2_dec_decode_ctl.scala 334:131] + when _T_107 : @[el2_dec_decode_ctl.scala 334:126] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3124,17 +3124,17 @@ circuit el2_dec_decode_ctl : cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_129 = eq(r_d_in.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:100] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] - when _T_133 : @[el2_dec_decode_ctl.scala 334:131] + when _T_133 : @[el2_dec_decode_ctl.scala 334:126] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3202,17 +3202,17 @@ circuit el2_dec_decode_ctl : cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_155 = eq(r_d_in.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:100] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] - when _T_159 : @[el2_dec_decode_ctl.scala 334:131] + when _T_159 : @[el2_dec_decode_ctl.scala 334:126] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3280,17 +3280,17 @@ circuit el2_dec_decode_ctl : cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_181 = eq(r_d_in.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:100] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] - when _T_185 : @[el2_dec_decode_ctl.scala 334:131] + when _T_185 : @[el2_dec_decode_ctl.scala 334:126] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3326,8 +3326,8 @@ circuit el2_dec_decode_ctl : node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] + node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] @@ -3632,18 +3632,18 @@ circuit el2_dec_decode_ctl : io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] @@ -3790,11 +3790,11 @@ circuit el2_dec_decode_ctl : reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] @@ -3914,8 +3914,8 @@ circuit el2_dec_decode_ctl : io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] @@ -3924,7 +3924,7 @@ circuit el2_dec_decode_ctl : node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] @@ -3935,8 +3935,8 @@ circuit el2_dec_decode_ctl : mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] @@ -4073,7 +4073,7 @@ circuit el2_dec_decode_ctl : r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -4082,8 +4082,8 @@ circuit el2_dec_decode_ctl : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] @@ -4120,7 +4120,7 @@ circuit el2_dec_decode_ctl : io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] @@ -4440,22 +4440,22 @@ circuit el2_dec_decode_ctl : io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock @@ -4463,55 +4463,55 @@ circuit el2_dec_decode_ctl : rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock @@ -4519,57 +4519,57 @@ circuit el2_dec_decode_ctl : rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock @@ -4577,43 +4577,43 @@ circuit el2_dec_decode_ctl : rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] @@ -4625,13 +4625,13 @@ circuit el2_dec_decode_ctl : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] @@ -4700,25 +4700,25 @@ circuit el2_dec_decode_ctl : reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] @@ -4858,18 +4858,18 @@ circuit el2_dec_decode_ctl : node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] diff --git a/el2_dec_decode_ctl.v b/el2_dec_decode_ctl.v index c6cb93b1..f5825fae 100644 --- a/el2_dec_decode_ctl.v +++ b/el2_dec_decode_ctl.v @@ -1248,8 +1248,8 @@ module el2_dec_decode_ctl( wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] - reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] @@ -1392,34 +1392,34 @@ module el2_dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_103 = r_d_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] @@ -1429,13 +1429,13 @@ module el2_dec_decode_ctl( wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_129 = r_d_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] @@ -1445,13 +1445,13 @@ module el2_dec_decode_ctl( wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_155 = r_d_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] @@ -1461,20 +1461,20 @@ module el2_dec_decode_ctl( wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_181 = r_d_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] + wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] @@ -1561,13 +1561,13 @@ module el2_dec_decode_ctl( reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] @@ -1576,12 +1576,12 @@ module el2_dec_decode_ctl( wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] @@ -1589,16 +1589,16 @@ module el2_dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] @@ -1628,14 +1628,14 @@ module el2_dec_decode_ctl( wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] @@ -1652,8 +1652,8 @@ module el2_dec_decode_ctl( wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] @@ -1709,13 +1709,13 @@ module el2_dec_decode_ctl( reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] @@ -1751,34 +1751,34 @@ module el2_dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] @@ -2077,7 +2077,7 @@ module el2_dec_decode_ctl( assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] @@ -2127,10 +2127,10 @@ module el2_dec_decode_ctl( assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] @@ -2139,7 +2139,7 @@ module el2_dec_decode_ctl( assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] @@ -2283,7 +2283,7 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_valid = _RAND_7[0:0]; + x_d_i0valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; @@ -2305,19 +2305,19 @@ initial begin _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_bits_i0load = _RAND_18[0:0]; + x_d_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_bits_i0rd = _RAND_19[4:0]; + x_d_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_bits_i0load = _RAND_22[0:0]; + r_d_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_bits_i0v = _RAND_23[0:0]; + r_d_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_bits_i0rd = _RAND_24[4:0]; + r_d_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; cam_raw_0_bits_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; @@ -2339,17 +2339,17 @@ initial begin _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_bits_i0v = _RAND_35[0:0]; + x_d_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_bits_csrwen = _RAND_38[0:0]; + r_d_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_valid = _RAND_39[0:0]; + r_d_i0valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_bits_csrwaddr = _RAND_40[11:0]; + r_d_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -2365,13 +2365,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_bits_csrwonly = _RAND_48[0:0]; + r_d_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_bits_csrwonly = _RAND_50[0:0]; + x_d_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_bits_csrwonly = _RAND_51[0:0]; + wbd_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -2411,9 +2411,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_bits_i0store = _RAND_71[0:0]; + r_d_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_bits_i0div = _RAND_72[0:0]; + r_d_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -2423,13 +2423,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_bits_i0store = _RAND_77[0:0]; + x_d_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_bits_i0div = _RAND_78[0:0]; + x_d_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_bits_csrwen = _RAND_79[0:0]; + x_d_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_bits_csrwaddr = _RAND_80[11:0]; + x_d_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -2473,7 +2473,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_valid = 1'h0; + x_d_i0valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -2506,10 +2506,10 @@ initial begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_bits_i0load = 1'h0; + x_d_i0load = 1'h0; end if (reset) begin - x_d_bits_i0rd = 5'h0; + x_d_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -2518,13 +2518,13 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_bits_i0load = 1'h0; + r_d_i0load = 1'h0; end if (reset) begin - r_d_bits_i0v = 1'h0; + r_d_i0v = 1'h0; end if (reset) begin - r_d_bits_i0rd = 5'h0; + r_d_i0rd = 5'h0; end if (reset) begin cam_raw_0_bits_rd = 5'h0; @@ -2557,16 +2557,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_bits_i0v = 1'h0; + x_d_i0v = 1'h0; end if (reset) begin - r_d_bits_csrwen = 1'h0; + r_d_csrwen = 1'h0; end if (reset) begin - r_d_valid = 1'h0; + r_d_i0valid = 1'h0; end if (reset) begin - r_d_bits_csrwaddr = 12'h0; + r_d_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -2590,16 +2590,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_bits_csrwonly = 1'h0; + r_d_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_bits_csrwonly = 1'h0; + x_d_csrwonly = 1'h0; end if (reset) begin - wbd_bits_csrwonly = 1'h0; + wbd_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -2659,22 +2659,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_bits_i0store = 1'h0; + r_d_i0store = 1'h0; end if (reset) begin - r_d_bits_i0div = 1'h0; + r_d_i0div = 1'h0; end if (reset) begin - x_d_bits_i0store = 1'h0; + x_d_i0store = 1'h0; end if (reset) begin - x_d_bits_i0div = 1'h0; + x_d_i0div = 1'h0; end if (reset) begin - x_d_bits_csrwen = 1'h0; + x_d_csrwen = 1'h0; end if (reset) begin - x_d_bits_csrwaddr = 12'h0; + x_d_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -2787,9 +2787,9 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_valid <= 1'h0; + x_d_i0valid <= 1'h0; end else begin - x_d_valid <= io_dec_i0_decode_d; + x_d_i0valid <= io_dec_i0_decode_d; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -2880,16 +2880,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0load <= 1'h0; + x_d_i0load <= 1'h0; end else begin - x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_i0load <= i0_dp_load & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0rd <= 5'h0; + x_d_i0rd <= 5'h0; end else begin - x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -2908,31 +2908,31 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0load <= 1'h0; + r_d_i0load <= 1'h0; end else begin - r_d_bits_i0load <= x_d_bits_i0load; + r_d_i0load <= x_d_i0load; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0v <= 1'h0; + r_d_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_280; + r_d_i0v <= _T_733 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0rd <= 5'h0; + r_d_i0rd <= 5'h0; end else begin - r_d_bits_i0rd <= x_d_bits_i0rd; + r_d_i0rd <= x_d_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin cam_raw_0_bits_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_bits_i0load) begin - cam_raw_0_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_0_bits_rd <= x_d_i0rd; end else begin cam_raw_0_bits_rd <= 5'h0; end @@ -2951,8 +2951,8 @@ end // initial if (reset) begin cam_raw_1_bits_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_bits_i0load) begin - cam_raw_1_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_1_bits_rd <= x_d_i0rd; end else begin cam_raw_1_bits_rd <= 5'h0; end @@ -2971,8 +2971,8 @@ end // initial if (reset) begin cam_raw_2_bits_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_bits_i0load) begin - cam_raw_2_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_2_bits_rd <= x_d_i0rd; end else begin cam_raw_2_bits_rd <= 5'h0; end @@ -2991,8 +2991,8 @@ end // initial if (reset) begin cam_raw_3_bits_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_bits_i0load) begin - cam_raw_3_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_3_bits_rd <= x_d_i0rd; end else begin cam_raw_3_bits_rd <= 5'h0; end @@ -3023,30 +3023,30 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0v <= 1'h0; + x_d_i0v <= 1'h0; end else begin - x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwen <= 1'h0; + r_d_csrwen <= 1'h0; end else begin - r_d_bits_csrwen <= x_d_bits_csrwen; + r_d_csrwen <= x_d_csrwen; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_valid <= 1'h0; + r_d_i0valid <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_280; + r_d_i0valid <= _T_737 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwaddr <= 12'h0; + r_d_csrwaddr <= 12'h0; end else begin - r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + r_d_csrwaddr <= x_d_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -3102,9 +3102,9 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwonly <= 1'h0; + r_d_csrwonly <= 1'h0; end else begin - r_d_bits_csrwonly <= x_d_bits_csrwonly; + r_d_csrwonly <= x_d_csrwonly; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin @@ -3118,16 +3118,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwonly <= 1'h0; + x_d_csrwonly <= 1'h0; end else begin - x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_bits_csrwonly <= 1'h0; + wbd_csrwonly <= 1'h0; end else begin - wbd_bits_csrwonly <= r_d_bits_csrwonly; + wbd_csrwonly <= r_d_csrwonly; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin @@ -3267,44 +3267,44 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0store <= 1'h0; + r_d_i0store <= 1'h0; end else begin - r_d_bits_i0store <= x_d_bits_i0store; + r_d_i0store <= x_d_i0store; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0div <= 1'h0; + r_d_i0div <= 1'h0; end else begin - r_d_bits_i0div <= x_d_bits_i0div; + r_d_i0div <= x_d_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0store <= 1'h0; + x_d_i0store <= 1'h0; end else begin - x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_i0store <= i0_dp_store & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0div <= 1'h0; + x_d_i0div <= 1'h0; end else begin - x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_i0div <= i0_dp_div & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwen <= 1'h0; + x_d_csrwen <= 1'h0; end else begin - x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwaddr <= 12'h0; + x_d_csrwaddr <= 12'h0; end else begin - x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v index 28da1375..462fb7f8 100644 --- a/el2_swerv_wrapper.v +++ b/el2_swerv_wrapper.v @@ -82580,228 +82580,228 @@ module el2_swerv_wrapper( input io_mbist_mode, input io_scan_mode ); - wire mem_clk; // @[SweRV_Wrapper.scala 345:19] - wire mem_rst_l; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_clk_override; // @[SweRV_Wrapper.scala 345:19] - wire mem_icm_clk_override; // @[SweRV_Wrapper.scala 345:19] - wire mem_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_wren; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_rden; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 345:19] - wire [14:0] mem_iccm_rw_addr; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_correction_state; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_wren; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_rden; // @[SweRV_Wrapper.scala 345:19] - wire [2:0] mem_iccm_wr_size; // @[SweRV_Wrapper.scala 345:19] - wire [77:0] mem_iccm_wr_data; // @[SweRV_Wrapper.scala 345:19] - wire [30:0] mem_ic_rw_addr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_tag_valid; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_wr_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_rd_en; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_ic_premux_data; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_sel_premux_data; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_wr_data_0; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_wr_data_1; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_debug_wr_data; // @[SweRV_Wrapper.scala 345:19] - wire [9:0] mem_ic_debug_addr; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_rd_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_wr_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_tag_array; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_debug_way; // @[SweRV_Wrapper.scala 345:19] - wire mem_scan_mode; // @[SweRV_Wrapper.scala 345:19] - wire [77:0] mem_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_ic_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [25:0] mem_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_eccerr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_parerr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_rd_hit; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_tag_perr; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_debug_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_iccm_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire dmi_wrapper_trst_n; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tck; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tms; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdi; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdo; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdoEnable; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_core_rst_n; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_core_clk; // @[SweRV_Wrapper.scala 346:27] - wire [30:0] dmi_wrapper_jtag_id; // @[SweRV_Wrapper.scala 346:27] - wire [31:0] dmi_wrapper_rd_data; // @[SweRV_Wrapper.scala 346:27] - wire [31:0] dmi_wrapper_reg_wr_data; // @[SweRV_Wrapper.scala 346:27] - wire [6:0] dmi_wrapper_reg_wr_addr; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_reg_en; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_reg_wr_en; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_dmi_hard_reset; // @[SweRV_Wrapper.scala 346:27] - wire swerv_clock; // @[SweRV_Wrapper.scala 347:21] - wire swerv_reset; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dbg_rst_l; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_rst_vec; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_nmi_int; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_nmi_vec; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_core_rst_l; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_insn_ip; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_address_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_valid_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_exception_ip; // @[SweRV_Wrapper.scala 347:21] - wire [4:0] swerv_io_trace_rv_i_ecause_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_interrupt_ip; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_tval_ip; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_clk_override; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_icm_clk_override; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_i_cpu_halt_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_i_cpu_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_halt_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_halt_status; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_run_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_debug_mode_status; // @[SweRV_Wrapper.scala 347:21] - wire [27:0] swerv_io_core_id; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_halt_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_reset_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_halt_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_run_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_debug_brkpt_status; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt0; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt1; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt2; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt3; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_wren; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_rden; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 347:21] - wire [14:0] swerv_io_iccm_rw_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_wren; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_rden; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_iccm_wr_size; // @[SweRV_Wrapper.scala 347:21] - wire [77:0] swerv_io_iccm_wr_data; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_correction_state; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_iccm_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [77:0] swerv_io_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_ic_rw_addr; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_tag_valid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_rd_en; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_wr_data_0; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_wr_data_1; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ic_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_debug_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [25:0] swerv_io_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_debug_wr_data; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_eccerr; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ic_premux_data; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_sel_premux_data; // @[SweRV_Wrapper.scala 347:21] - wire [9:0] swerv_io_ic_debug_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_rd_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_tag_array; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_debug_way; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_rd_hit; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_tag_perr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_awid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_lsu_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_awregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_awcache; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_lsu_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_lsu_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_lsu_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_bid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_lsu_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_arcache; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_lsu_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_ifu_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_ifu_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_ifu_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_ifu_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ifu_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ifu_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_sb_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_sb_axi_awregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_sb_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_sb_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_sb_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_sb_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_sb_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_sb_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_sb_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_sb_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_sb_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dma_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_dma_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_dma_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_dma_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bready; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_dma_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dma_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_dma_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_dma_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_dma_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dbg_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dmi_reg_en; // @[SweRV_Wrapper.scala 347:21] - wire [6:0] swerv_io_dmi_reg_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dmi_reg_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dmi_reg_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_extintsrc_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_timer_int; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_soft_int; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_scan_mode; // @[SweRV_Wrapper.scala 347:21] - el2_mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[SweRV_Wrapper.scala 345:19] + wire mem_clk; // @[el2_swerv_wrapper.scala 345:19] + wire mem_rst_l; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_clk_override; // @[el2_swerv_wrapper.scala 345:19] + wire mem_icm_clk_override; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_wren; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_rden; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [14:0] mem_iccm_rw_addr; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_correction_state; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_wren; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_rden; // @[el2_swerv_wrapper.scala 345:19] + wire [2:0] mem_iccm_wr_size; // @[el2_swerv_wrapper.scala 345:19] + wire [77:0] mem_iccm_wr_data; // @[el2_swerv_wrapper.scala 345:19] + wire [30:0] mem_ic_rw_addr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_tag_valid; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_wr_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_rd_en; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_ic_premux_data; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_wr_data_0; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_wr_data_1; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 345:19] + wire [9:0] mem_ic_debug_addr; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_debug_way; // @[el2_swerv_wrapper.scala 345:19] + wire mem_scan_mode; // @[el2_swerv_wrapper.scala 345:19] + wire [77:0] mem_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_ic_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [25:0] mem_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_eccerr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_parerr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_rd_hit; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_tag_perr; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_iccm_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire dmi_wrapper_trst_n; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tck; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tms; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdi; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdo; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdoEnable; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_core_rst_n; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_core_clk; // @[el2_swerv_wrapper.scala 346:27] + wire [30:0] dmi_wrapper_jtag_id; // @[el2_swerv_wrapper.scala 346:27] + wire [31:0] dmi_wrapper_rd_data; // @[el2_swerv_wrapper.scala 346:27] + wire [31:0] dmi_wrapper_reg_wr_data; // @[el2_swerv_wrapper.scala 346:27] + wire [6:0] dmi_wrapper_reg_wr_addr; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_reg_en; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_reg_wr_en; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_dmi_hard_reset; // @[el2_swerv_wrapper.scala 346:27] + wire swerv_clock; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_reset; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dbg_rst_l; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_rst_vec; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_nmi_int; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_nmi_vec; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_core_rst_l; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_insn_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_address_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_valid_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_exception_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [4:0] swerv_io_trace_rv_i_ecause_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_interrupt_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_tval_ip; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_clk_override; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_icm_clk_override; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_i_cpu_halt_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_i_cpu_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_halt_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_halt_status; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_run_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_debug_mode_status; // @[el2_swerv_wrapper.scala 347:21] + wire [27:0] swerv_io_core_id; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_halt_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_reset_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_halt_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_run_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_debug_brkpt_status; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt0; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt1; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt2; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt3; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_wren; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_rden; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [14:0] swerv_io_iccm_rw_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_wren; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_rden; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_iccm_wr_size; // @[el2_swerv_wrapper.scala 347:21] + wire [77:0] swerv_io_iccm_wr_data; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_correction_state; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_iccm_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [77:0] swerv_io_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_ic_rw_addr; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_tag_valid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_rd_en; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_wr_data_0; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_wr_data_1; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ic_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [25:0] swerv_io_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_eccerr; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ic_premux_data; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 347:21] + wire [9:0] swerv_io_ic_debug_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_debug_way; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_rd_hit; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_tag_perr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_awid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_lsu_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_awregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_awcache; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_lsu_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_lsu_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_lsu_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_bid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_lsu_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_arcache; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_lsu_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_ifu_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_ifu_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_ifu_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_ifu_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ifu_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ifu_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_sb_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_sb_axi_awregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_sb_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_sb_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_sb_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_sb_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_sb_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_sb_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_sb_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_sb_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_sb_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dma_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_dma_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_dma_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_dma_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bready; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_dma_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dma_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_dma_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_dma_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_dma_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dbg_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dmi_reg_en; // @[el2_swerv_wrapper.scala 347:21] + wire [6:0] swerv_io_dmi_reg_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dmi_reg_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dmi_reg_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_extintsrc_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_timer_int; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_soft_int; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_scan_mode; // @[el2_swerv_wrapper.scala 347:21] + el2_mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[el2_swerv_wrapper.scala 345:19] .clk(mem_clk), .rst_l(mem_rst_l), .dccm_clk_override(mem_dccm_clk_override), @@ -82849,7 +82849,7 @@ module el2_swerv_wrapper( .ic_debug_rd_data(mem_ic_debug_rd_data), .iccm_rd_data(mem_iccm_rd_data) ); - dmi_wrapper dmi_wrapper ( // @[SweRV_Wrapper.scala 346:27] + dmi_wrapper dmi_wrapper ( // @[el2_swerv_wrapper.scala 346:27] .trst_n(dmi_wrapper_trst_n), .tck(dmi_wrapper_tck), .tms(dmi_wrapper_tms), @@ -82866,7 +82866,7 @@ module el2_swerv_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - el2_swerv swerv ( // @[SweRV_Wrapper.scala 347:21] + el2_swerv swerv ( // @[el2_swerv_wrapper.scala 347:21] .clock(swerv_clock), .reset(swerv_reset), .io_dbg_rst_l(swerv_io_dbg_rst_l), @@ -83028,233 +83028,233 @@ module el2_swerv_wrapper( .io_soft_int(swerv_io_soft_int), .io_scan_mode(swerv_io_scan_mode) ); - assign io_trace_rv_i_insn_ip = swerv_io_trace_rv_i_insn_ip; // @[SweRV_Wrapper.scala 558:25] - assign io_trace_rv_i_address_ip = swerv_io_trace_rv_i_address_ip; // @[SweRV_Wrapper.scala 559:28] - assign io_trace_rv_i_valid_ip = swerv_io_trace_rv_i_valid_ip; // @[SweRV_Wrapper.scala 560:26] - assign io_trace_rv_i_exception_ip = swerv_io_trace_rv_i_exception_ip; // @[SweRV_Wrapper.scala 561:30] - assign io_trace_rv_i_ecause_ip = swerv_io_trace_rv_i_ecause_ip; // @[SweRV_Wrapper.scala 562:27] - assign io_trace_rv_i_interrupt_ip = swerv_io_trace_rv_i_interrupt_ip; // @[SweRV_Wrapper.scala 563:30] - assign io_trace_rv_i_tval_ip = swerv_io_trace_rv_i_tval_ip; // @[SweRV_Wrapper.scala 564:25] - assign io_lsu_axi_awvalid = swerv_io_lsu_axi_awvalid; // @[SweRV_Wrapper.scala 584:22] - assign io_lsu_axi_awid = swerv_io_lsu_axi_awid; // @[SweRV_Wrapper.scala 585:19] - assign io_lsu_axi_awaddr = swerv_io_lsu_axi_awaddr; // @[SweRV_Wrapper.scala 586:21] - assign io_lsu_axi_awregion = swerv_io_lsu_axi_awregion; // @[SweRV_Wrapper.scala 587:23] - assign io_lsu_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 588:20] - assign io_lsu_axi_awsize = swerv_io_lsu_axi_awsize; // @[SweRV_Wrapper.scala 589:21] - assign io_lsu_axi_awburst = 2'h1; // @[SweRV_Wrapper.scala 590:22] - assign io_lsu_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 591:21] - assign io_lsu_axi_awcache = swerv_io_lsu_axi_awcache; // @[SweRV_Wrapper.scala 592:22] - assign io_lsu_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 593:21] - assign io_lsu_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 594:20] - assign io_lsu_axi_wvalid = swerv_io_lsu_axi_wvalid; // @[SweRV_Wrapper.scala 596:21] - assign io_lsu_axi_wdata = swerv_io_lsu_axi_wdata; // @[SweRV_Wrapper.scala 597:20] - assign io_lsu_axi_wstrb = swerv_io_lsu_axi_wstrb; // @[SweRV_Wrapper.scala 598:20] - assign io_lsu_axi_wlast = 1'h1; // @[SweRV_Wrapper.scala 599:20] - assign io_lsu_axi_bready = 1'h1; // @[SweRV_Wrapper.scala 600:21] - assign io_lsu_axi_arvalid = swerv_io_lsu_axi_arvalid; // @[SweRV_Wrapper.scala 603:22] - assign io_lsu_axi_arid = swerv_io_lsu_axi_arid; // @[SweRV_Wrapper.scala 604:19] - assign io_lsu_axi_araddr = swerv_io_lsu_axi_araddr; // @[SweRV_Wrapper.scala 605:21] - assign io_lsu_axi_arregion = swerv_io_lsu_axi_arregion; // @[SweRV_Wrapper.scala 606:23] - assign io_lsu_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 607:20] - assign io_lsu_axi_arsize = swerv_io_lsu_axi_arsize; // @[SweRV_Wrapper.scala 608:21] - assign io_lsu_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 609:22] - assign io_lsu_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 610:21] - assign io_lsu_axi_arcache = swerv_io_lsu_axi_arcache; // @[SweRV_Wrapper.scala 611:22] - assign io_lsu_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 612:21] - assign io_lsu_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 613:20] - assign io_lsu_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 614:21] - assign io_ifu_axi_awvalid = 1'h0; // @[SweRV_Wrapper.scala 616:22] - assign io_ifu_axi_awid = 3'h0; // @[SweRV_Wrapper.scala 617:19] - assign io_ifu_axi_awaddr = 32'h0; // @[SweRV_Wrapper.scala 618:21] - assign io_ifu_axi_awregion = 4'h0; // @[SweRV_Wrapper.scala 619:23] - assign io_ifu_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 620:20] - assign io_ifu_axi_awsize = 3'h0; // @[SweRV_Wrapper.scala 621:21] - assign io_ifu_axi_awburst = 2'h0; // @[SweRV_Wrapper.scala 622:22] - assign io_ifu_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 623:21] - assign io_ifu_axi_awcache = 4'h0; // @[SweRV_Wrapper.scala 624:22] - assign io_ifu_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 625:21] - assign io_ifu_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 626:20] - assign io_ifu_axi_wvalid = 1'h0; // @[SweRV_Wrapper.scala 627:21] - assign io_ifu_axi_wdata = 64'h0; // @[SweRV_Wrapper.scala 628:20] - assign io_ifu_axi_wstrb = 8'h0; // @[SweRV_Wrapper.scala 629:20] - assign io_ifu_axi_wlast = 1'h0; // @[SweRV_Wrapper.scala 630:20] - assign io_ifu_axi_bready = 1'h0; // @[SweRV_Wrapper.scala 632:21] - assign io_ifu_axi_arvalid = swerv_io_ifu_axi_arvalid; // @[SweRV_Wrapper.scala 635:22] - assign io_ifu_axi_arid = swerv_io_ifu_axi_arid; // @[SweRV_Wrapper.scala 636:19] - assign io_ifu_axi_araddr = swerv_io_ifu_axi_araddr; // @[SweRV_Wrapper.scala 637:21] - assign io_ifu_axi_arregion = swerv_io_ifu_axi_arregion; // @[SweRV_Wrapper.scala 638:23] - assign io_ifu_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 639:20] - assign io_ifu_axi_arsize = 3'h3; // @[SweRV_Wrapper.scala 640:21] - assign io_ifu_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 641:22] - assign io_ifu_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 642:21] - assign io_ifu_axi_arcache = 4'hf; // @[SweRV_Wrapper.scala 643:22] - assign io_ifu_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 644:21] - assign io_ifu_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 645:20] - assign io_ifu_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 646:21] - assign io_sb_axi_awvalid = swerv_io_sb_axi_awvalid; // @[SweRV_Wrapper.scala 649:21] - assign io_sb_axi_awid = 1'h0; // @[SweRV_Wrapper.scala 650:18] - assign io_sb_axi_awaddr = swerv_io_sb_axi_awaddr; // @[SweRV_Wrapper.scala 651:20] - assign io_sb_axi_awregion = swerv_io_sb_axi_awregion; // @[SweRV_Wrapper.scala 652:22] - assign io_sb_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 653:19] - assign io_sb_axi_awsize = swerv_io_sb_axi_awsize; // @[SweRV_Wrapper.scala 654:20] - assign io_sb_axi_awburst = 2'h1; // @[SweRV_Wrapper.scala 655:21] - assign io_sb_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 656:20] - assign io_sb_axi_awcache = 4'hf; // @[SweRV_Wrapper.scala 657:21] - assign io_sb_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 658:20] - assign io_sb_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 659:19] - assign io_sb_axi_wvalid = swerv_io_sb_axi_wvalid; // @[SweRV_Wrapper.scala 661:19] - assign io_sb_axi_wdata = swerv_io_sb_axi_wdata; // @[SweRV_Wrapper.scala 662:19] - assign io_sb_axi_wstrb = swerv_io_sb_axi_wstrb; // @[SweRV_Wrapper.scala 663:19] - assign io_sb_axi_wlast = 1'h1; // @[SweRV_Wrapper.scala 664:19] - assign io_sb_axi_bready = 1'h1; // @[SweRV_Wrapper.scala 665:20] - assign io_sb_axi_arvalid = swerv_io_sb_axi_arvalid; // @[SweRV_Wrapper.scala 668:21] - assign io_sb_axi_arid = 1'h0; // @[SweRV_Wrapper.scala 669:18] - assign io_sb_axi_araddr = swerv_io_sb_axi_araddr; // @[SweRV_Wrapper.scala 670:20] - assign io_sb_axi_arregion = swerv_io_sb_axi_arregion; // @[SweRV_Wrapper.scala 671:22] - assign io_sb_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 672:19] - assign io_sb_axi_arsize = swerv_io_sb_axi_arsize; // @[SweRV_Wrapper.scala 673:20] - assign io_sb_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 674:21] - assign io_sb_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 675:20] - assign io_sb_axi_arcache = 4'h0; // @[SweRV_Wrapper.scala 676:21] - assign io_sb_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 677:20] - assign io_sb_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 678:19] - assign io_sb_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 679:20] - assign io_dma_axi_awready = swerv_io_dma_axi_awready; // @[SweRV_Wrapper.scala 682:22] - assign io_dma_axi_wready = swerv_io_dma_axi_wready; // @[SweRV_Wrapper.scala 683:21] - assign io_dma_axi_bvalid = swerv_io_dma_axi_bvalid; // @[SweRV_Wrapper.scala 685:21] - assign io_dma_axi_bresp = swerv_io_dma_axi_bresp; // @[SweRV_Wrapper.scala 686:20] - assign io_dma_axi_bid = swerv_io_dma_axi_bid; // @[SweRV_Wrapper.scala 687:18] - assign io_dma_axi_arready = swerv_io_dma_axi_arready; // @[SweRV_Wrapper.scala 690:22] - assign io_dma_axi_rvalid = swerv_io_dma_axi_rvalid; // @[SweRV_Wrapper.scala 691:21] - assign io_dma_axi_rid = swerv_io_dma_axi_rid; // @[SweRV_Wrapper.scala 692:18] - assign io_dma_axi_rdata = swerv_io_dma_axi_rdata; // @[SweRV_Wrapper.scala 693:20] - assign io_dma_axi_rresp = swerv_io_dma_axi_rresp; // @[SweRV_Wrapper.scala 694:20] - assign io_dma_axi_rlast = 1'h1; // @[SweRV_Wrapper.scala 695:20] - assign io_dma_hrdata = 64'h0; // @[SweRV_Wrapper.scala 698:17] - assign io_dma_hreadyout = 1'h0; // @[SweRV_Wrapper.scala 699:20] - assign io_dma_hresp = 1'h0; // @[SweRV_Wrapper.scala 700:16] - assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[SweRV_Wrapper.scala 576:23] - assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[SweRV_Wrapper.scala 577:23] - assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[SweRV_Wrapper.scala 578:23] - assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[SweRV_Wrapper.scala 579:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[SweRV_Wrapper.scala 363:15] - assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[SweRV_Wrapper.scala 572:25] - assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[SweRV_Wrapper.scala 573:24] - assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[SweRV_Wrapper.scala 574:25] - assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[SweRV_Wrapper.scala 567:21] - assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[SweRV_Wrapper.scala 568:24] - assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[SweRV_Wrapper.scala 570:26] - assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[SweRV_Wrapper.scala 569:20] - assign mem_clk = clock; // @[SweRV_Wrapper.scala 403:14] - assign mem_rst_l = reset; // @[SweRV_Wrapper.scala 402:16] - assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[SweRV_Wrapper.scala 366:28] - assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[SweRV_Wrapper.scala 367:27] - assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 368:35] - assign mem_dccm_wren = swerv_io_dccm_wren; // @[SweRV_Wrapper.scala 369:20] - assign mem_dccm_rden = swerv_io_dccm_rden; // @[SweRV_Wrapper.scala 370:20] - assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 371:26] - assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 372:26] - assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 373:26] - assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 378:26] - assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 375:26] - assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 376:26] - assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[SweRV_Wrapper.scala 379:23] - assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 380:31] - assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[SweRV_Wrapper.scala 381:32] - assign mem_iccm_wren = swerv_io_iccm_wren; // @[SweRV_Wrapper.scala 382:20] - assign mem_iccm_rden = swerv_io_iccm_rden; // @[SweRV_Wrapper.scala 383:20] - assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[SweRV_Wrapper.scala 384:23] - assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[SweRV_Wrapper.scala 385:23] - assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[SweRV_Wrapper.scala 388:21] - assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[SweRV_Wrapper.scala 389:23] - assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[SweRV_Wrapper.scala 390:19] - assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[SweRV_Wrapper.scala 391:19] - assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[SweRV_Wrapper.scala 392:25] - assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[SweRV_Wrapper.scala 393:29] - assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[SweRV_Wrapper.scala 394:21] - assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[SweRV_Wrapper.scala 394:21] - assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[SweRV_Wrapper.scala 395:27] - assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[SweRV_Wrapper.scala 397:24] - assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[SweRV_Wrapper.scala 398:25] - assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[SweRV_Wrapper.scala 399:25] - assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[SweRV_Wrapper.scala 400:29] - assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[SweRV_Wrapper.scala 401:23] - assign mem_scan_mode = io_scan_mode; // @[SweRV_Wrapper.scala 404:20] - assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[SweRV_Wrapper.scala 348:25] - assign dmi_wrapper_tck = io_jtag_tck; // @[SweRV_Wrapper.scala 349:22] - assign dmi_wrapper_tms = io_jtag_tms; // @[SweRV_Wrapper.scala 350:22] - assign dmi_wrapper_tdi = io_jtag_tdi; // @[SweRV_Wrapper.scala 351:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[SweRV_Wrapper.scala 357:29] - assign dmi_wrapper_core_clk = clock; // @[SweRV_Wrapper.scala 352:27] - assign dmi_wrapper_jtag_id = io_jtag_id; // @[SweRV_Wrapper.scala 353:26] - assign dmi_wrapper_rd_data = 32'h0; // @[SweRV_Wrapper.scala 354:26] + assign io_trace_rv_i_insn_ip = swerv_io_trace_rv_i_insn_ip; // @[el2_swerv_wrapper.scala 558:25] + assign io_trace_rv_i_address_ip = swerv_io_trace_rv_i_address_ip; // @[el2_swerv_wrapper.scala 559:28] + assign io_trace_rv_i_valid_ip = swerv_io_trace_rv_i_valid_ip; // @[el2_swerv_wrapper.scala 560:26] + assign io_trace_rv_i_exception_ip = swerv_io_trace_rv_i_exception_ip; // @[el2_swerv_wrapper.scala 561:30] + assign io_trace_rv_i_ecause_ip = swerv_io_trace_rv_i_ecause_ip; // @[el2_swerv_wrapper.scala 562:27] + assign io_trace_rv_i_interrupt_ip = swerv_io_trace_rv_i_interrupt_ip; // @[el2_swerv_wrapper.scala 563:30] + assign io_trace_rv_i_tval_ip = swerv_io_trace_rv_i_tval_ip; // @[el2_swerv_wrapper.scala 564:25] + assign io_lsu_axi_awvalid = swerv_io_lsu_axi_awvalid; // @[el2_swerv_wrapper.scala 584:22] + assign io_lsu_axi_awid = swerv_io_lsu_axi_awid; // @[el2_swerv_wrapper.scala 585:19] + assign io_lsu_axi_awaddr = swerv_io_lsu_axi_awaddr; // @[el2_swerv_wrapper.scala 586:21] + assign io_lsu_axi_awregion = swerv_io_lsu_axi_awregion; // @[el2_swerv_wrapper.scala 587:23] + assign io_lsu_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 588:20] + assign io_lsu_axi_awsize = swerv_io_lsu_axi_awsize; // @[el2_swerv_wrapper.scala 589:21] + assign io_lsu_axi_awburst = 2'h1; // @[el2_swerv_wrapper.scala 590:22] + assign io_lsu_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 591:21] + assign io_lsu_axi_awcache = swerv_io_lsu_axi_awcache; // @[el2_swerv_wrapper.scala 592:22] + assign io_lsu_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 593:21] + assign io_lsu_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 594:20] + assign io_lsu_axi_wvalid = swerv_io_lsu_axi_wvalid; // @[el2_swerv_wrapper.scala 596:21] + assign io_lsu_axi_wdata = swerv_io_lsu_axi_wdata; // @[el2_swerv_wrapper.scala 597:20] + assign io_lsu_axi_wstrb = swerv_io_lsu_axi_wstrb; // @[el2_swerv_wrapper.scala 598:20] + assign io_lsu_axi_wlast = 1'h1; // @[el2_swerv_wrapper.scala 599:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_swerv_wrapper.scala 600:21] + assign io_lsu_axi_arvalid = swerv_io_lsu_axi_arvalid; // @[el2_swerv_wrapper.scala 603:22] + assign io_lsu_axi_arid = swerv_io_lsu_axi_arid; // @[el2_swerv_wrapper.scala 604:19] + assign io_lsu_axi_araddr = swerv_io_lsu_axi_araddr; // @[el2_swerv_wrapper.scala 605:21] + assign io_lsu_axi_arregion = swerv_io_lsu_axi_arregion; // @[el2_swerv_wrapper.scala 606:23] + assign io_lsu_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 607:20] + assign io_lsu_axi_arsize = swerv_io_lsu_axi_arsize; // @[el2_swerv_wrapper.scala 608:21] + assign io_lsu_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 609:22] + assign io_lsu_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 610:21] + assign io_lsu_axi_arcache = swerv_io_lsu_axi_arcache; // @[el2_swerv_wrapper.scala 611:22] + assign io_lsu_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 612:21] + assign io_lsu_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 613:20] + assign io_lsu_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 614:21] + assign io_ifu_axi_awvalid = 1'h0; // @[el2_swerv_wrapper.scala 616:22] + assign io_ifu_axi_awid = 3'h0; // @[el2_swerv_wrapper.scala 617:19] + assign io_ifu_axi_awaddr = 32'h0; // @[el2_swerv_wrapper.scala 618:21] + assign io_ifu_axi_awregion = 4'h0; // @[el2_swerv_wrapper.scala 619:23] + assign io_ifu_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 620:20] + assign io_ifu_axi_awsize = 3'h0; // @[el2_swerv_wrapper.scala 621:21] + assign io_ifu_axi_awburst = 2'h0; // @[el2_swerv_wrapper.scala 622:22] + assign io_ifu_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 623:21] + assign io_ifu_axi_awcache = 4'h0; // @[el2_swerv_wrapper.scala 624:22] + assign io_ifu_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 625:21] + assign io_ifu_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 626:20] + assign io_ifu_axi_wvalid = 1'h0; // @[el2_swerv_wrapper.scala 627:21] + assign io_ifu_axi_wdata = 64'h0; // @[el2_swerv_wrapper.scala 628:20] + assign io_ifu_axi_wstrb = 8'h0; // @[el2_swerv_wrapper.scala 629:20] + assign io_ifu_axi_wlast = 1'h0; // @[el2_swerv_wrapper.scala 630:20] + assign io_ifu_axi_bready = 1'h0; // @[el2_swerv_wrapper.scala 632:21] + assign io_ifu_axi_arvalid = swerv_io_ifu_axi_arvalid; // @[el2_swerv_wrapper.scala 635:22] + assign io_ifu_axi_arid = swerv_io_ifu_axi_arid; // @[el2_swerv_wrapper.scala 636:19] + assign io_ifu_axi_araddr = swerv_io_ifu_axi_araddr; // @[el2_swerv_wrapper.scala 637:21] + assign io_ifu_axi_arregion = swerv_io_ifu_axi_arregion; // @[el2_swerv_wrapper.scala 638:23] + assign io_ifu_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 639:20] + assign io_ifu_axi_arsize = 3'h3; // @[el2_swerv_wrapper.scala 640:21] + assign io_ifu_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 641:22] + assign io_ifu_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 642:21] + assign io_ifu_axi_arcache = 4'hf; // @[el2_swerv_wrapper.scala 643:22] + assign io_ifu_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 644:21] + assign io_ifu_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 645:20] + assign io_ifu_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 646:21] + assign io_sb_axi_awvalid = swerv_io_sb_axi_awvalid; // @[el2_swerv_wrapper.scala 649:21] + assign io_sb_axi_awid = 1'h0; // @[el2_swerv_wrapper.scala 650:18] + assign io_sb_axi_awaddr = swerv_io_sb_axi_awaddr; // @[el2_swerv_wrapper.scala 651:20] + assign io_sb_axi_awregion = swerv_io_sb_axi_awregion; // @[el2_swerv_wrapper.scala 652:22] + assign io_sb_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 653:19] + assign io_sb_axi_awsize = swerv_io_sb_axi_awsize; // @[el2_swerv_wrapper.scala 654:20] + assign io_sb_axi_awburst = 2'h1; // @[el2_swerv_wrapper.scala 655:21] + assign io_sb_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 656:20] + assign io_sb_axi_awcache = 4'hf; // @[el2_swerv_wrapper.scala 657:21] + assign io_sb_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 658:20] + assign io_sb_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 659:19] + assign io_sb_axi_wvalid = swerv_io_sb_axi_wvalid; // @[el2_swerv_wrapper.scala 661:19] + assign io_sb_axi_wdata = swerv_io_sb_axi_wdata; // @[el2_swerv_wrapper.scala 662:19] + assign io_sb_axi_wstrb = swerv_io_sb_axi_wstrb; // @[el2_swerv_wrapper.scala 663:19] + assign io_sb_axi_wlast = 1'h1; // @[el2_swerv_wrapper.scala 664:19] + assign io_sb_axi_bready = 1'h1; // @[el2_swerv_wrapper.scala 665:20] + assign io_sb_axi_arvalid = swerv_io_sb_axi_arvalid; // @[el2_swerv_wrapper.scala 668:21] + assign io_sb_axi_arid = 1'h0; // @[el2_swerv_wrapper.scala 669:18] + assign io_sb_axi_araddr = swerv_io_sb_axi_araddr; // @[el2_swerv_wrapper.scala 670:20] + assign io_sb_axi_arregion = swerv_io_sb_axi_arregion; // @[el2_swerv_wrapper.scala 671:22] + assign io_sb_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 672:19] + assign io_sb_axi_arsize = swerv_io_sb_axi_arsize; // @[el2_swerv_wrapper.scala 673:20] + assign io_sb_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 674:21] + assign io_sb_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 675:20] + assign io_sb_axi_arcache = 4'h0; // @[el2_swerv_wrapper.scala 676:21] + assign io_sb_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 677:20] + assign io_sb_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 678:19] + assign io_sb_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 679:20] + assign io_dma_axi_awready = swerv_io_dma_axi_awready; // @[el2_swerv_wrapper.scala 682:22] + assign io_dma_axi_wready = swerv_io_dma_axi_wready; // @[el2_swerv_wrapper.scala 683:21] + assign io_dma_axi_bvalid = swerv_io_dma_axi_bvalid; // @[el2_swerv_wrapper.scala 685:21] + assign io_dma_axi_bresp = swerv_io_dma_axi_bresp; // @[el2_swerv_wrapper.scala 686:20] + assign io_dma_axi_bid = swerv_io_dma_axi_bid; // @[el2_swerv_wrapper.scala 687:18] + assign io_dma_axi_arready = swerv_io_dma_axi_arready; // @[el2_swerv_wrapper.scala 690:22] + assign io_dma_axi_rvalid = swerv_io_dma_axi_rvalid; // @[el2_swerv_wrapper.scala 691:21] + assign io_dma_axi_rid = swerv_io_dma_axi_rid; // @[el2_swerv_wrapper.scala 692:18] + assign io_dma_axi_rdata = swerv_io_dma_axi_rdata; // @[el2_swerv_wrapper.scala 693:20] + assign io_dma_axi_rresp = swerv_io_dma_axi_rresp; // @[el2_swerv_wrapper.scala 694:20] + assign io_dma_axi_rlast = 1'h1; // @[el2_swerv_wrapper.scala 695:20] + assign io_dma_hrdata = 64'h0; // @[el2_swerv_wrapper.scala 698:17] + assign io_dma_hreadyout = 1'h0; // @[el2_swerv_wrapper.scala 699:20] + assign io_dma_hresp = 1'h0; // @[el2_swerv_wrapper.scala 700:16] + assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[el2_swerv_wrapper.scala 576:23] + assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[el2_swerv_wrapper.scala 577:23] + assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[el2_swerv_wrapper.scala 578:23] + assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[el2_swerv_wrapper.scala 579:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[el2_swerv_wrapper.scala 363:15] + assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[el2_swerv_wrapper.scala 572:25] + assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[el2_swerv_wrapper.scala 573:24] + assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[el2_swerv_wrapper.scala 574:25] + assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[el2_swerv_wrapper.scala 567:21] + assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[el2_swerv_wrapper.scala 568:24] + assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[el2_swerv_wrapper.scala 570:26] + assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[el2_swerv_wrapper.scala 569:20] + assign mem_clk = clock; // @[el2_swerv_wrapper.scala 403:14] + assign mem_rst_l = reset; // @[el2_swerv_wrapper.scala 402:16] + assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[el2_swerv_wrapper.scala 366:28] + assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[el2_swerv_wrapper.scala 367:27] + assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 368:35] + assign mem_dccm_wren = swerv_io_dccm_wren; // @[el2_swerv_wrapper.scala 369:20] + assign mem_dccm_rden = swerv_io_dccm_rden; // @[el2_swerv_wrapper.scala 370:20] + assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 371:26] + assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 372:26] + assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 373:26] + assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 378:26] + assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 375:26] + assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 376:26] + assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[el2_swerv_wrapper.scala 379:23] + assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 380:31] + assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[el2_swerv_wrapper.scala 381:32] + assign mem_iccm_wren = swerv_io_iccm_wren; // @[el2_swerv_wrapper.scala 382:20] + assign mem_iccm_rden = swerv_io_iccm_rden; // @[el2_swerv_wrapper.scala 383:20] + assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[el2_swerv_wrapper.scala 384:23] + assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[el2_swerv_wrapper.scala 385:23] + assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[el2_swerv_wrapper.scala 388:21] + assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[el2_swerv_wrapper.scala 389:23] + assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[el2_swerv_wrapper.scala 390:19] + assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[el2_swerv_wrapper.scala 391:19] + assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[el2_swerv_wrapper.scala 392:25] + assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 393:29] + assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[el2_swerv_wrapper.scala 394:21] + assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[el2_swerv_wrapper.scala 394:21] + assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 395:27] + assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[el2_swerv_wrapper.scala 397:24] + assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 398:25] + assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 399:25] + assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 400:29] + assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[el2_swerv_wrapper.scala 401:23] + assign mem_scan_mode = io_scan_mode; // @[el2_swerv_wrapper.scala 404:20] + assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[el2_swerv_wrapper.scala 348:25] + assign dmi_wrapper_tck = io_jtag_tck; // @[el2_swerv_wrapper.scala 349:22] + assign dmi_wrapper_tms = io_jtag_tms; // @[el2_swerv_wrapper.scala 350:22] + assign dmi_wrapper_tdi = io_jtag_tdi; // @[el2_swerv_wrapper.scala 351:22] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[el2_swerv_wrapper.scala 357:29] + assign dmi_wrapper_core_clk = clock; // @[el2_swerv_wrapper.scala 352:27] + assign dmi_wrapper_jtag_id = io_jtag_id; // @[el2_swerv_wrapper.scala 353:26] + assign dmi_wrapper_rd_data = 32'h0; // @[el2_swerv_wrapper.scala 354:26] assign swerv_clock = clock; assign swerv_reset = reset; - assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[SweRV_Wrapper.scala 406:22 SweRV_Wrapper.scala 428:22] - assign swerv_io_rst_vec = io_rst_vec; // @[SweRV_Wrapper.scala 429:20] - assign swerv_io_nmi_int = io_nmi_int; // @[SweRV_Wrapper.scala 430:20] - assign swerv_io_nmi_vec = io_nmi_vec; // @[SweRV_Wrapper.scala 431:20] - assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[SweRV_Wrapper.scala 434:27] - assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[SweRV_Wrapper.scala 435:26] - assign swerv_io_core_id = io_core_id; // @[SweRV_Wrapper.scala 436:20] - assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[SweRV_Wrapper.scala 439:31] - assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[SweRV_Wrapper.scala 440:30] - assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[SweRV_Wrapper.scala 441:30] - assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 377:28] - assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 408:28] - assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[SweRV_Wrapper.scala 416:25] - assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 407:29] - assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[SweRV_Wrapper.scala 409:23] - assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[SweRV_Wrapper.scala 415:29] - assign swerv_io_ictag_debug_rd_data = mem_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 410:32] - assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[SweRV_Wrapper.scala 411:22] - assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[SweRV_Wrapper.scala 413:22] - assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[SweRV_Wrapper.scala 414:24] - assign swerv_io_lsu_axi_awready = io_lsu_axi_awready; // @[SweRV_Wrapper.scala 445:28] - assign swerv_io_lsu_axi_wready = io_lsu_axi_wready; // @[SweRV_Wrapper.scala 446:27] - assign swerv_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[SweRV_Wrapper.scala 448:27] - assign swerv_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[SweRV_Wrapper.scala 449:26] - assign swerv_io_lsu_axi_bid = io_lsu_axi_bid; // @[SweRV_Wrapper.scala 450:24] - assign swerv_io_lsu_axi_arready = io_lsu_axi_arready; // @[SweRV_Wrapper.scala 453:28] - assign swerv_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[SweRV_Wrapper.scala 454:27] - assign swerv_io_lsu_axi_rid = io_lsu_axi_rid; // @[SweRV_Wrapper.scala 455:24] - assign swerv_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[SweRV_Wrapper.scala 456:26] - assign swerv_io_ifu_axi_arready = io_ifu_axi_arready; // @[SweRV_Wrapper.scala 469:28] - assign swerv_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[SweRV_Wrapper.scala 470:27] - assign swerv_io_ifu_axi_rid = io_ifu_axi_rid; // @[SweRV_Wrapper.scala 471:24] - assign swerv_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[SweRV_Wrapper.scala 472:26] - assign swerv_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[SweRV_Wrapper.scala 473:26] - assign swerv_io_sb_axi_awready = io_sb_axi_awready; // @[SweRV_Wrapper.scala 478:27] - assign swerv_io_sb_axi_wready = io_sb_axi_wready; // @[SweRV_Wrapper.scala 479:26] - assign swerv_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[SweRV_Wrapper.scala 481:26] - assign swerv_io_sb_axi_bresp = io_sb_axi_bresp; // @[SweRV_Wrapper.scala 482:25] - assign swerv_io_sb_axi_arready = io_sb_axi_arready; // @[SweRV_Wrapper.scala 486:27] - assign swerv_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[SweRV_Wrapper.scala 487:26] - assign swerv_io_sb_axi_rdata = io_sb_axi_rdata; // @[SweRV_Wrapper.scala 489:25] - assign swerv_io_sb_axi_rresp = io_sb_axi_rresp; // @[SweRV_Wrapper.scala 490:25] - assign swerv_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[SweRV_Wrapper.scala 495:28] - assign swerv_io_dma_axi_awid = io_dma_axi_awid; // @[SweRV_Wrapper.scala 496:25] - assign swerv_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[SweRV_Wrapper.scala 497:27] - assign swerv_io_dma_axi_awsize = io_dma_axi_awsize; // @[SweRV_Wrapper.scala 498:27] - assign swerv_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[SweRV_Wrapper.scala 503:27] - assign swerv_io_dma_axi_wdata = io_dma_axi_wdata; // @[SweRV_Wrapper.scala 504:26] - assign swerv_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[SweRV_Wrapper.scala 505:26] - assign swerv_io_dma_axi_bready = io_dma_axi_bready; // @[SweRV_Wrapper.scala 507:27] - assign swerv_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[SweRV_Wrapper.scala 510:28] - assign swerv_io_dma_axi_arid = io_dma_axi_arid; // @[SweRV_Wrapper.scala 511:25] - assign swerv_io_dma_axi_araddr = io_dma_axi_araddr; // @[SweRV_Wrapper.scala 512:27] - assign swerv_io_dma_axi_arsize = io_dma_axi_arsize; // @[SweRV_Wrapper.scala 513:27] - assign swerv_io_dma_axi_rready = io_dma_axi_rready; // @[SweRV_Wrapper.scala 517:27] - assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[SweRV_Wrapper.scala 547:27] - assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[SweRV_Wrapper.scala 548:27] - assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[SweRV_Wrapper.scala 549:27] - assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[SweRV_Wrapper.scala 550:27] - assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[SweRV_Wrapper.scala 360:23] - assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[SweRV_Wrapper.scala 359:25] - assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[SweRV_Wrapper.scala 361:26] - assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[SweRV_Wrapper.scala 358:26] - assign swerv_io_extintsrc_req = io_extintsrc_req; // @[SweRV_Wrapper.scala 554:26] - assign swerv_io_timer_int = io_timer_int; // @[SweRV_Wrapper.scala 552:22] - assign swerv_io_soft_int = io_soft_int; // @[SweRV_Wrapper.scala 553:21] - assign swerv_io_scan_mode = io_scan_mode; // @[SweRV_Wrapper.scala 426:22] + assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[el2_swerv_wrapper.scala 406:22 el2_swerv_wrapper.scala 428:22] + assign swerv_io_rst_vec = io_rst_vec; // @[el2_swerv_wrapper.scala 429:20] + assign swerv_io_nmi_int = io_nmi_int; // @[el2_swerv_wrapper.scala 430:20] + assign swerv_io_nmi_vec = io_nmi_vec; // @[el2_swerv_wrapper.scala 431:20] + assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv_wrapper.scala 434:27] + assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv_wrapper.scala 435:26] + assign swerv_io_core_id = io_core_id; // @[el2_swerv_wrapper.scala 436:20] + assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv_wrapper.scala 439:31] + assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv_wrapper.scala 440:30] + assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv_wrapper.scala 441:30] + assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 377:28] + assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 408:28] + assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[el2_swerv_wrapper.scala 416:25] + assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 407:29] + assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[el2_swerv_wrapper.scala 409:23] + assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 415:29] + assign swerv_io_ictag_debug_rd_data = mem_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 410:32] + assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[el2_swerv_wrapper.scala 411:22] + assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[el2_swerv_wrapper.scala 413:22] + assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[el2_swerv_wrapper.scala 414:24] + assign swerv_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_swerv_wrapper.scala 445:28] + assign swerv_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_swerv_wrapper.scala 446:27] + assign swerv_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_swerv_wrapper.scala 448:27] + assign swerv_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_swerv_wrapper.scala 449:26] + assign swerv_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_swerv_wrapper.scala 450:24] + assign swerv_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_swerv_wrapper.scala 453:28] + assign swerv_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_swerv_wrapper.scala 454:27] + assign swerv_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_swerv_wrapper.scala 455:24] + assign swerv_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_swerv_wrapper.scala 456:26] + assign swerv_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_swerv_wrapper.scala 469:28] + assign swerv_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_swerv_wrapper.scala 470:27] + assign swerv_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_swerv_wrapper.scala 471:24] + assign swerv_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_swerv_wrapper.scala 472:26] + assign swerv_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_swerv_wrapper.scala 473:26] + assign swerv_io_sb_axi_awready = io_sb_axi_awready; // @[el2_swerv_wrapper.scala 478:27] + assign swerv_io_sb_axi_wready = io_sb_axi_wready; // @[el2_swerv_wrapper.scala 479:26] + assign swerv_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[el2_swerv_wrapper.scala 481:26] + assign swerv_io_sb_axi_bresp = io_sb_axi_bresp; // @[el2_swerv_wrapper.scala 482:25] + assign swerv_io_sb_axi_arready = io_sb_axi_arready; // @[el2_swerv_wrapper.scala 486:27] + assign swerv_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[el2_swerv_wrapper.scala 487:26] + assign swerv_io_sb_axi_rdata = io_sb_axi_rdata; // @[el2_swerv_wrapper.scala 489:25] + assign swerv_io_sb_axi_rresp = io_sb_axi_rresp; // @[el2_swerv_wrapper.scala 490:25] + assign swerv_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[el2_swerv_wrapper.scala 495:28] + assign swerv_io_dma_axi_awid = io_dma_axi_awid; // @[el2_swerv_wrapper.scala 496:25] + assign swerv_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[el2_swerv_wrapper.scala 497:27] + assign swerv_io_dma_axi_awsize = io_dma_axi_awsize; // @[el2_swerv_wrapper.scala 498:27] + assign swerv_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[el2_swerv_wrapper.scala 503:27] + assign swerv_io_dma_axi_wdata = io_dma_axi_wdata; // @[el2_swerv_wrapper.scala 504:26] + assign swerv_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[el2_swerv_wrapper.scala 505:26] + assign swerv_io_dma_axi_bready = io_dma_axi_bready; // @[el2_swerv_wrapper.scala 507:27] + assign swerv_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[el2_swerv_wrapper.scala 510:28] + assign swerv_io_dma_axi_arid = io_dma_axi_arid; // @[el2_swerv_wrapper.scala 511:25] + assign swerv_io_dma_axi_araddr = io_dma_axi_araddr; // @[el2_swerv_wrapper.scala 512:27] + assign swerv_io_dma_axi_arsize = io_dma_axi_arsize; // @[el2_swerv_wrapper.scala 513:27] + assign swerv_io_dma_axi_rready = io_dma_axi_rready; // @[el2_swerv_wrapper.scala 517:27] + assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_swerv_wrapper.scala 547:27] + assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_swerv_wrapper.scala 548:27] + assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[el2_swerv_wrapper.scala 549:27] + assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[el2_swerv_wrapper.scala 550:27] + assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[el2_swerv_wrapper.scala 360:23] + assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[el2_swerv_wrapper.scala 359:25] + assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[el2_swerv_wrapper.scala 361:26] + assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[el2_swerv_wrapper.scala 358:26] + assign swerv_io_extintsrc_req = io_extintsrc_req; // @[el2_swerv_wrapper.scala 554:26] + assign swerv_io_timer_int = io_timer_int; // @[el2_swerv_wrapper.scala 552:22] + assign swerv_io_soft_int = io_soft_int; // @[el2_swerv_wrapper.scala 553:21] + assign swerv_io_scan_mode = io_scan_mode; // @[el2_swerv_wrapper.scala 426:22] endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index bde2aec4..4ec29fe7 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v -/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv -/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala index 382f5d37..65912352 100644 --- a/src/main/scala/dec/el2_dec_decode_ctl.scala +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -133,11 +133,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val x_t_in = Wire(new el2_trap_pkt_t) val r_t = Wire(new el2_trap_pkt_t) val r_t_in = Wire(new el2_trap_pkt_t) - val d_d = Wire(Valid(new el2_dest_pkt_t)) - val x_d = Wire(Valid(new el2_dest_pkt_t)) - val r_d = Wire(Valid(new el2_dest_pkt_t)) - val r_d_in = Wire(Valid(new el2_dest_pkt_t)) - val wbd = Wire(Valid(new el2_dest_pkt_t)) + val d_d = Wire(new el2_dest_pkt_t) + val x_d = Wire(new el2_dest_pkt_t) + val r_d = Wire(new el2_dest_pkt_t) + val r_d_in = Wire(new el2_dest_pkt_t) + val wbd = Wire(new el2_dest_pkt_t) val i0_d_c = Wire(new el2_class_pkt_t) val i0_rs1_class_d = Wire(new el2_class_pkt_t) val i0_rs2_class_d = Wire(new el2_class_pkt_t) @@ -311,12 +311,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error val cam_data_reset_tag = io.lsu_nonblock_load_data_tag - val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data + val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data val load_data_tag = io.lsu_nonblock_load_data_tag // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one // don't writeback a nonblock load val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} - val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load + val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load for(i <- 0 until LSU_NUM_NBLOAD){ cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid @@ -331,7 +331,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ cam_in(i).bits.wb := 0.U(1.W) cam_in(i).bits.tag := cam_write_tag cam_in(i).bits.rd := nonblock_load_rd - }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ cam_in(i).valid := 0.U }.otherwise{ cam_in(i) := cam(i) @@ -350,7 +350,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_nonblock_load_waddr:=0.U(5.W) // cancel if any younger inst (including another nonblock) committing this cycle - val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) + val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) @@ -464,14 +464,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ //dec_csr_wen_unq_d assigned as csr_write above io.dec_csr_rdaddr_d := i0(31,20) - io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a el2_dest_pkt + io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb // also use valid so it's flushable - io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r; + io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r; // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. - io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb; + io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb; val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} @@ -511,9 +511,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val pause_stall = pause_state // for csr write only data is produced by the alu - io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data) + io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data) - val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly; + val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly; val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0) val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1) @@ -559,8 +559,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_pmu_postsync_stall := postsync_stall.asBool io.dec_pmu_presync_stall := presync_stall.asBool - val prior_inflight_x = x_d.valid - val prior_inflight_wb = r_d.valid + val prior_inflight_x = x_d.i0valid + val prior_inflight_wb = r_d.i0valid val prior_inflight = prior_inflight_x | prior_inflight_wb val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) @@ -575,7 +575,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ mul_decode_d := i0_exulegal_decode_d & i0_dp.mul div_decode_d := i0_exulegal_decode_d & i0_dp.div - io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb + io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb //traps for TLU (tlu stuff) d_t.legal := i0_legal_decode_d @@ -604,13 +604,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ r_t_in := r_t - r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger + r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } io.dec_tlu_packet_r := r_t_in - io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid + io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid // end tlu stuff flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} @@ -662,52 +662,52 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) - d_d.bits.i0rd := i0r.rd - d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d - d_d.valid := io.dec_i0_decode_d // has flush_final_r + d_d.i0rd := i0r.rd + d_d.i0v := i0_rd_en_d & i0_legal_decode_d + d_d.i0valid := io.dec_i0_decode_d // has flush_final_r - d_d.bits.i0load := i0_dp.load & i0_legal_decode_d - d_d.bits.i0store := i0_dp.store & i0_legal_decode_d - d_d.bits.i0div := i0_dp.div & i0_legal_decode_d + d_d.i0load := i0_dp.load & i0_legal_decode_d + d_d.i0store := i0_dp.store & i0_legal_decode_d + d_d.i0div := i0_dp.div & i0_legal_decode_d - d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d - d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d - d_d.bits.csrwaddr := i0(31,20) + d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d + d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d + d_d.csrwaddr := i0(31,20) x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) - val x_d_in = Wire(Valid(new el2_dest_pkt_t)) + val x_d_in = Wire(new el2_dest_pkt_t) x_d_in := x_d - x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r - x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) r_d_in := r_d - r_d_in.bits.i0rd := r_d.bits.i0rd + r_d_in.i0rd := r_d.i0rd - r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb) - r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb) - r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb - r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb + r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb) + r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb) + r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb + r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) - io.dec_i0_waddr_r := r_d_in.bits.i0rd - i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r - io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe + io.dec_i0_waddr_r := r_d_in.i0rd + i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r + io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe io.dec_i0_wdata_r := i0_result_corr_r val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) if ( LOAD_TO_USE_PLUS1 == 1 ) { i0_result_x := io.exu_i0_result_x - i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) + i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw) } else { - i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) + i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) i0_result_r := i0_result_r_raw } // correct lsu load data - don't use for bypass, do pass down the pipe - i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) + i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) val last_br_immed_d = WireInit(UInt(12.W),0.U) last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) @@ -716,16 +716,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ // divide stuff - val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid) + val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid) - val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) | - (x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) | - (r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) + val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) | + (x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) | + (r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) // cancel if any younger inst committing this cycle to same dest as nonblock divide val nonblock_div_cancel = (io.dec_div_active & div_flush) | - (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r) + (io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r) io.dec_div_cancel := nonblock_div_cancel.asBool val i0_div_decode_d = i0_legal_decode_d & i0_dp.div @@ -765,11 +765,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ // scheduling logic for primary alu's - val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1) - val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1) + val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1) + val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1) - val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2) - val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2) + val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2) + val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2) // order the producers as follows: , i0_x, i0_r, i0_wb i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index 21fa4b30..11ebd30f 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -103,6 +103,7 @@ class el2_dest_pkt_t extends Bundle { val i0store = UInt(1.W) val i0div = UInt(1.W) val i0v = UInt(1.W) + val i0valid = UInt(1.W) val csrwen = UInt(1.W) val csrwonly = UInt(1.W) val csrwaddr = UInt(12.W) diff --git a/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class b/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class index 06e4b5ea..e33fbca3 100644 Binary files a/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class and b/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class differ diff --git a/target/scala-2.12/classes/include/el2_alu_pkt_t.class b/target/scala-2.12/classes/include/el2_alu_pkt_t.class index 52e48070..6278d257 100644 Binary files a/target/scala-2.12/classes/include/el2_alu_pkt_t.class and b/target/scala-2.12/classes/include/el2_alu_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/el2_cache_debug_pkt_t.class b/target/scala-2.12/classes/include/el2_cache_debug_pkt_t.class index bae053e5..c0d79495 100644 Binary files a/target/scala-2.12/classes/include/el2_cache_debug_pkt_t.class and b/target/scala-2.12/classes/include/el2_cache_debug_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class index 678ca3bb..bce2084d 100644 Binary files a/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/el2_class_pkt_t.class b/target/scala-2.12/classes/include/el2_class_pkt_t.class index 076efdf6..38d93ddb 100644 Binary files a/target/scala-2.12/classes/include/el2_class_pkt_t.class and b/target/scala-2.12/classes/include/el2_class_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/el2_dccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/el2_dccm_ext_in_pkt_t.class index e5cbbcee..e3c26a2a 100644 Binary files a/target/scala-2.12/classes/include/el2_dccm_ext_in_pkt_t.class and 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