From 5ed044d54b569030fe1c51410001baba18825df3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Tue, 24 Nov 2020 14:28:34 +0500 Subject: [PATCH] dec update --- el2_dec_decode_ctl.fir | 478 +++++----- el2_dec_decode_ctl.v | 354 +++---- el2_swerv_wrapper.v | 902 +++++++++--------- firrtl_black_box_resource_files.f | 4 +- src/main/scala/dec/el2_dec_decode_ctl.scala | 102 +- src/main/scala/include/el2_bundle.scala | 1 + .../classes/dec/el2_dec_decode_ctl.class | Bin 548753 -> 548210 bytes .../classes/include/el2_alu_pkt_t.class | Bin 4186 -> 4186 bytes .../include/el2_cache_debug_pkt_t.class | Bin 2082 -> 2082 bytes .../include/el2_ccm_ext_in_pkt_t.class | Bin 2666 -> 2666 bytes .../classes/include/el2_class_pkt_t.class | Bin 1767 -> 1767 bytes .../include/el2_dccm_ext_in_pkt_t.class | Bin 2669 -> 2669 bytes .../classes/include/el2_dec_pkt_t.class | Bin 8216 -> 8216 bytes .../classes/include/el2_dec_tlu_csr_pkt.class | Bin 13337 -> 13337 bytes .../classes/include/el2_dest_pkt_t.class | Bin 2568 -> 2727 bytes .../classes/include/el2_div_pkt_t.class | Bin 1622 -> 1622 bytes .../include/el2_ic_data_ext_in_pkt_t.class | Bin 2678 -> 2678 bytes .../include/el2_ic_tag_ext_in_pkt_t.class | Bin 2675 -> 2675 bytes .../classes/include/el2_lsu_error_pkt_t.class | Bin 2164 -> 2164 bytes .../classes/include/el2_lsu_pkt_t.class | Bin 2890 -> 2890 bytes .../classes/include/el2_mul_pkt_t.class | Bin 4119 -> 4119 bytes .../classes/include/el2_reg_pkt_t.class | Bin 1755 -> 1755 bytes .../classes/include/el2_trigger_pkt_t.class | Bin 2401 -> 2401 bytes 23 files changed, 920 insertions(+), 921 deletions(-) diff --git a/el2_dec_decode_ctl.fir b/el2_dec_decode_ctl.fir index 341c2abd..47fa8212 100644 --- a/el2_dec_decode_ctl.fir +++ b/el2_dec_decode_ctl.fir @@ -2573,11 +2573,11 @@ circuit el2_dec_decode_ctl : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -3005,14 +3005,14 @@ circuit el2_dec_decode_ctl : cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] + node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] @@ -3046,17 +3046,17 @@ circuit el2_dec_decode_ctl : cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_103 = eq(r_d_in.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:100] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] - when _T_107 : @[el2_dec_decode_ctl.scala 334:131] + when _T_107 : @[el2_dec_decode_ctl.scala 334:126] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3124,17 +3124,17 @@ circuit el2_dec_decode_ctl : cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_129 = eq(r_d_in.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:100] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] - when _T_133 : @[el2_dec_decode_ctl.scala 334:131] + when _T_133 : @[el2_dec_decode_ctl.scala 334:126] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3202,17 +3202,17 @@ circuit el2_dec_decode_ctl : cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_155 = eq(r_d_in.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:100] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] - when _T_159 : @[el2_dec_decode_ctl.scala 334:131] + when _T_159 : @[el2_dec_decode_ctl.scala 334:126] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3280,17 +3280,17 @@ circuit el2_dec_decode_ctl : cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:126] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_181 = eq(r_d_in.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:80] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:100] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] - when _T_185 : @[el2_dec_decode_ctl.scala 334:131] + when _T_185 : @[el2_dec_decode_ctl.scala 334:126] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:126] else : @[el2_dec_decode_ctl.scala 336:16] cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] @@ -3326,8 +3326,8 @@ circuit el2_dec_decode_ctl : node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] + node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] @@ -3632,18 +3632,18 @@ circuit el2_dec_decode_ctl : io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] @@ -3790,11 +3790,11 @@ circuit el2_dec_decode_ctl : reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] @@ -3914,8 +3914,8 @@ circuit el2_dec_decode_ctl : io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] @@ -3924,7 +3924,7 @@ circuit el2_dec_decode_ctl : node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] @@ -3935,8 +3935,8 @@ circuit el2_dec_decode_ctl : mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] @@ -4073,7 +4073,7 @@ circuit el2_dec_decode_ctl : r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -4082,8 +4082,8 @@ circuit el2_dec_decode_ctl : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] @@ -4120,7 +4120,7 @@ circuit el2_dec_decode_ctl : io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] @@ -4440,22 +4440,22 @@ circuit el2_dec_decode_ctl : io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock @@ -4463,55 +4463,55 @@ circuit el2_dec_decode_ctl : rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock @@ -4519,57 +4519,57 @@ circuit el2_dec_decode_ctl : rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock @@ -4577,43 +4577,43 @@ circuit el2_dec_decode_ctl : rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] @@ -4625,13 +4625,13 @@ circuit el2_dec_decode_ctl : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] @@ -4700,25 +4700,25 @@ circuit el2_dec_decode_ctl : reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] @@ -4858,18 +4858,18 @@ circuit el2_dec_decode_ctl : node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] diff --git a/el2_dec_decode_ctl.v b/el2_dec_decode_ctl.v index c6cb93b1..f5825fae 100644 --- a/el2_dec_decode_ctl.v +++ b/el2_dec_decode_ctl.v @@ -1248,8 +1248,8 @@ module el2_dec_decode_ctl( wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] - reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] @@ -1392,34 +1392,34 @@ module el2_dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_103 = r_d_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] @@ -1429,13 +1429,13 @@ module el2_dec_decode_ctl( wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_129 = r_d_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] @@ -1445,13 +1445,13 @@ module el2_dec_decode_ctl( wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_155 = r_d_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] @@ -1461,20 +1461,20 @@ module el2_dec_decode_ctl( wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire _T_181 = r_d_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:100] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:126] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:126] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] + wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] @@ -1561,13 +1561,13 @@ module el2_dec_decode_ctl( reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] @@ -1576,12 +1576,12 @@ module el2_dec_decode_ctl( wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] @@ -1589,16 +1589,16 @@ module el2_dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] @@ -1628,14 +1628,14 @@ module el2_dec_decode_ctl( wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] @@ -1652,8 +1652,8 @@ module el2_dec_decode_ctl( wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] @@ -1709,13 +1709,13 @@ module el2_dec_decode_ctl( reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] @@ -1751,34 +1751,34 @@ module el2_dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] @@ -2077,7 +2077,7 @@ module el2_dec_decode_ctl( assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] @@ -2127,10 +2127,10 @@ module el2_dec_decode_ctl( assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] @@ -2139,7 +2139,7 @@ module el2_dec_decode_ctl( assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] @@ -2283,7 +2283,7 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_valid = _RAND_7[0:0]; + x_d_i0valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; @@ -2305,19 +2305,19 @@ initial begin _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_bits_i0load = _RAND_18[0:0]; + x_d_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_bits_i0rd = _RAND_19[4:0]; + x_d_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_bits_i0load = _RAND_22[0:0]; + r_d_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_bits_i0v = _RAND_23[0:0]; + r_d_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_bits_i0rd = _RAND_24[4:0]; + r_d_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; cam_raw_0_bits_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; @@ -2339,17 +2339,17 @@ initial begin _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_bits_i0v = _RAND_35[0:0]; + x_d_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_bits_csrwen = _RAND_38[0:0]; + r_d_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_valid = _RAND_39[0:0]; + r_d_i0valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_bits_csrwaddr = _RAND_40[11:0]; + r_d_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -2365,13 +2365,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_bits_csrwonly = _RAND_48[0:0]; + r_d_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_bits_csrwonly = _RAND_50[0:0]; + x_d_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_bits_csrwonly = _RAND_51[0:0]; + wbd_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -2411,9 +2411,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_bits_i0store = _RAND_71[0:0]; + r_d_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_bits_i0div = _RAND_72[0:0]; + r_d_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -2423,13 +2423,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_bits_i0store = _RAND_77[0:0]; + x_d_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_bits_i0div = _RAND_78[0:0]; + x_d_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_bits_csrwen = _RAND_79[0:0]; + x_d_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_bits_csrwaddr = _RAND_80[11:0]; + x_d_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -2473,7 +2473,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_valid = 1'h0; + x_d_i0valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -2506,10 +2506,10 @@ initial begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_bits_i0load = 1'h0; + x_d_i0load = 1'h0; end if (reset) begin - x_d_bits_i0rd = 5'h0; + x_d_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -2518,13 +2518,13 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_bits_i0load = 1'h0; + r_d_i0load = 1'h0; end if (reset) begin - r_d_bits_i0v = 1'h0; + r_d_i0v = 1'h0; end if (reset) begin - r_d_bits_i0rd = 5'h0; + r_d_i0rd = 5'h0; end if (reset) begin cam_raw_0_bits_rd = 5'h0; @@ -2557,16 +2557,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_bits_i0v = 1'h0; + x_d_i0v = 1'h0; end if (reset) begin - r_d_bits_csrwen = 1'h0; + r_d_csrwen = 1'h0; end if (reset) begin - r_d_valid = 1'h0; + r_d_i0valid = 1'h0; end if (reset) begin - r_d_bits_csrwaddr = 12'h0; + r_d_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -2590,16 +2590,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_bits_csrwonly = 1'h0; + r_d_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_bits_csrwonly = 1'h0; + x_d_csrwonly = 1'h0; end if (reset) begin - wbd_bits_csrwonly = 1'h0; + wbd_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -2659,22 +2659,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_bits_i0store = 1'h0; + r_d_i0store = 1'h0; end if (reset) begin - r_d_bits_i0div = 1'h0; + r_d_i0div = 1'h0; end if (reset) begin - x_d_bits_i0store = 1'h0; + x_d_i0store = 1'h0; end if (reset) begin - x_d_bits_i0div = 1'h0; + x_d_i0div = 1'h0; end if (reset) begin - x_d_bits_csrwen = 1'h0; + x_d_csrwen = 1'h0; end if (reset) begin - x_d_bits_csrwaddr = 12'h0; + x_d_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -2787,9 +2787,9 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_valid <= 1'h0; + x_d_i0valid <= 1'h0; end else begin - x_d_valid <= io_dec_i0_decode_d; + x_d_i0valid <= io_dec_i0_decode_d; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -2880,16 +2880,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0load <= 1'h0; + x_d_i0load <= 1'h0; end else begin - x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_i0load <= i0_dp_load & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0rd <= 5'h0; + x_d_i0rd <= 5'h0; end else begin - x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -2908,31 +2908,31 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0load <= 1'h0; + r_d_i0load <= 1'h0; end else begin - r_d_bits_i0load <= x_d_bits_i0load; + r_d_i0load <= x_d_i0load; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0v <= 1'h0; + r_d_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_280; + r_d_i0v <= _T_733 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0rd <= 5'h0; + r_d_i0rd <= 5'h0; end else begin - r_d_bits_i0rd <= x_d_bits_i0rd; + r_d_i0rd <= x_d_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin cam_raw_0_bits_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_bits_i0load) begin - cam_raw_0_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_0_bits_rd <= x_d_i0rd; end else begin cam_raw_0_bits_rd <= 5'h0; end @@ -2951,8 +2951,8 @@ end // initial if (reset) begin cam_raw_1_bits_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_bits_i0load) begin - cam_raw_1_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_1_bits_rd <= x_d_i0rd; end else begin cam_raw_1_bits_rd <= 5'h0; end @@ -2971,8 +2971,8 @@ end // initial if (reset) begin cam_raw_2_bits_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_bits_i0load) begin - cam_raw_2_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_2_bits_rd <= x_d_i0rd; end else begin cam_raw_2_bits_rd <= 5'h0; end @@ -2991,8 +2991,8 @@ end // initial if (reset) begin cam_raw_3_bits_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_bits_i0load) begin - cam_raw_3_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_3_bits_rd <= x_d_i0rd; end else begin cam_raw_3_bits_rd <= 5'h0; end @@ -3023,30 +3023,30 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0v <= 1'h0; + x_d_i0v <= 1'h0; end else begin - x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwen <= 1'h0; + r_d_csrwen <= 1'h0; end else begin - r_d_bits_csrwen <= x_d_bits_csrwen; + r_d_csrwen <= x_d_csrwen; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_valid <= 1'h0; + r_d_i0valid <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_280; + r_d_i0valid <= _T_737 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwaddr <= 12'h0; + r_d_csrwaddr <= 12'h0; end else begin - r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + r_d_csrwaddr <= x_d_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -3102,9 +3102,9 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwonly <= 1'h0; + r_d_csrwonly <= 1'h0; end else begin - r_d_bits_csrwonly <= x_d_bits_csrwonly; + r_d_csrwonly <= x_d_csrwonly; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin @@ -3118,16 +3118,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwonly <= 1'h0; + x_d_csrwonly <= 1'h0; end else begin - x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_bits_csrwonly <= 1'h0; + wbd_csrwonly <= 1'h0; end else begin - wbd_bits_csrwonly <= r_d_bits_csrwonly; + wbd_csrwonly <= r_d_csrwonly; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin @@ -3267,44 +3267,44 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0store <= 1'h0; + r_d_i0store <= 1'h0; end else begin - r_d_bits_i0store <= x_d_bits_i0store; + r_d_i0store <= x_d_i0store; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0div <= 1'h0; + r_d_i0div <= 1'h0; end else begin - r_d_bits_i0div <= x_d_bits_i0div; + r_d_i0div <= x_d_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0store <= 1'h0; + x_d_i0store <= 1'h0; end else begin - x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_i0store <= i0_dp_store & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0div <= 1'h0; + x_d_i0div <= 1'h0; end else begin - x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_i0div <= i0_dp_div & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwen <= 1'h0; + x_d_csrwen <= 1'h0; end else begin - x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwaddr <= 12'h0; + x_d_csrwaddr <= 12'h0; end else begin - x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v index 28da1375..462fb7f8 100644 --- a/el2_swerv_wrapper.v +++ b/el2_swerv_wrapper.v @@ -82580,228 +82580,228 @@ module el2_swerv_wrapper( input io_mbist_mode, input io_scan_mode ); - wire mem_clk; // @[SweRV_Wrapper.scala 345:19] - wire mem_rst_l; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_clk_override; // @[SweRV_Wrapper.scala 345:19] - wire mem_icm_clk_override; // @[SweRV_Wrapper.scala 345:19] - wire mem_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_wren; // @[SweRV_Wrapper.scala 345:19] - wire mem_dccm_rden; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 345:19] - wire [15:0] mem_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 345:19] - wire [14:0] mem_iccm_rw_addr; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_correction_state; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_wren; // @[SweRV_Wrapper.scala 345:19] - wire mem_iccm_rden; // @[SweRV_Wrapper.scala 345:19] - wire [2:0] mem_iccm_wr_size; // @[SweRV_Wrapper.scala 345:19] - wire [77:0] mem_iccm_wr_data; // @[SweRV_Wrapper.scala 345:19] - wire [30:0] mem_ic_rw_addr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_tag_valid; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_wr_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_rd_en; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_ic_premux_data; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_sel_premux_data; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_wr_data_0; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_wr_data_1; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_debug_wr_data; // @[SweRV_Wrapper.scala 345:19] - wire [9:0] mem_ic_debug_addr; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_rd_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_wr_en; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_debug_tag_array; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_debug_way; // @[SweRV_Wrapper.scala 345:19] - wire mem_scan_mode; // @[SweRV_Wrapper.scala 345:19] - wire [77:0] mem_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 345:19] - wire [38:0] mem_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_ic_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [25:0] mem_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_eccerr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_parerr; // @[SweRV_Wrapper.scala 345:19] - wire [1:0] mem_ic_rd_hit; // @[SweRV_Wrapper.scala 345:19] - wire mem_ic_tag_perr; // @[SweRV_Wrapper.scala 345:19] - wire [70:0] mem_ic_debug_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire [63:0] mem_iccm_rd_data; // @[SweRV_Wrapper.scala 345:19] - wire dmi_wrapper_trst_n; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tck; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tms; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdi; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdo; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_tdoEnable; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_core_rst_n; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_core_clk; // @[SweRV_Wrapper.scala 346:27] - wire [30:0] dmi_wrapper_jtag_id; // @[SweRV_Wrapper.scala 346:27] - wire [31:0] dmi_wrapper_rd_data; // @[SweRV_Wrapper.scala 346:27] - wire [31:0] dmi_wrapper_reg_wr_data; // @[SweRV_Wrapper.scala 346:27] - wire [6:0] dmi_wrapper_reg_wr_addr; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_reg_en; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_reg_wr_en; // @[SweRV_Wrapper.scala 346:27] - wire dmi_wrapper_dmi_hard_reset; // @[SweRV_Wrapper.scala 346:27] - wire swerv_clock; // @[SweRV_Wrapper.scala 347:21] - wire swerv_reset; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dbg_rst_l; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_rst_vec; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_nmi_int; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_nmi_vec; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_core_rst_l; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_insn_ip; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_address_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_valid_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_exception_ip; // @[SweRV_Wrapper.scala 347:21] - wire [4:0] swerv_io_trace_rv_i_ecause_ip; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_trace_rv_i_interrupt_ip; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_trace_rv_i_tval_ip; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_clk_override; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_icm_clk_override; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_i_cpu_halt_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_i_cpu_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_halt_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_halt_status; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_cpu_run_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_o_debug_mode_status; // @[SweRV_Wrapper.scala 347:21] - wire [27:0] swerv_io_core_id; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_halt_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_reset_run_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_halt_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_mpc_debug_run_ack; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_debug_brkpt_status; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt0; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt1; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt2; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dec_tlu_perfcnt3; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_wren; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dccm_rden; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 347:21] - wire [15:0] swerv_io_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 347:21] - wire [38:0] swerv_io_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 347:21] - wire [14:0] swerv_io_iccm_rw_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_wren; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_rden; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_iccm_wr_size; // @[SweRV_Wrapper.scala 347:21] - wire [77:0] swerv_io_iccm_wr_data; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_iccm_correction_state; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_iccm_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [77:0] swerv_io_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_ic_rw_addr; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_tag_valid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_rd_en; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_wr_data_0; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_wr_data_1; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ic_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_debug_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [25:0] swerv_io_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 347:21] - wire [70:0] swerv_io_ic_debug_wr_data; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_eccerr; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ic_premux_data; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_sel_premux_data; // @[SweRV_Wrapper.scala 347:21] - wire [9:0] swerv_io_ic_debug_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_rd_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_debug_tag_array; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_debug_way; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ic_rd_hit; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ic_tag_perr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_awid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_lsu_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_awregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_awcache; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_lsu_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_lsu_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_lsu_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_bid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_lsu_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_lsu_axi_arcache; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_lsu_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_lsu_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_ifu_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_ifu_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_ifu_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_ifu_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_ifu_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_ifu_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_sb_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_sb_axi_awregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_sb_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_sb_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_sb_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_sb_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_sb_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [3:0] swerv_io_sb_axi_arregion; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_sb_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_sb_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_sb_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_sb_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_awid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dma_axi_awaddr; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_dma_axi_awsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_wvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_wready; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_dma_axi_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [7:0] swerv_io_dma_axi_wstrb; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bready; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_dma_axi_bresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_bid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_arid; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dma_axi_araddr; // @[SweRV_Wrapper.scala 347:21] - wire [2:0] swerv_io_dma_axi_arsize; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rvalid; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rready; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_axi_rid; // @[SweRV_Wrapper.scala 347:21] - wire [63:0] swerv_io_dma_axi_rdata; // @[SweRV_Wrapper.scala 347:21] - wire [1:0] swerv_io_dma_axi_rresp; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_lsu_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_ifu_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dbg_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dma_bus_clk_en; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dmi_reg_en; // @[SweRV_Wrapper.scala 347:21] - wire [6:0] swerv_io_dmi_reg_addr; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_dmi_reg_wr_en; // @[SweRV_Wrapper.scala 347:21] - wire [31:0] swerv_io_dmi_reg_wdata; // @[SweRV_Wrapper.scala 347:21] - wire [30:0] swerv_io_extintsrc_req; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_timer_int; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_soft_int; // @[SweRV_Wrapper.scala 347:21] - wire swerv_io_scan_mode; // @[SweRV_Wrapper.scala 347:21] - el2_mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[SweRV_Wrapper.scala 345:19] + wire mem_clk; // @[el2_swerv_wrapper.scala 345:19] + wire mem_rst_l; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_clk_override; // @[el2_swerv_wrapper.scala 345:19] + wire mem_icm_clk_override; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_wren; // @[el2_swerv_wrapper.scala 345:19] + wire mem_dccm_rden; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [15:0] mem_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 345:19] + wire [14:0] mem_iccm_rw_addr; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_correction_state; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_wren; // @[el2_swerv_wrapper.scala 345:19] + wire mem_iccm_rden; // @[el2_swerv_wrapper.scala 345:19] + wire [2:0] mem_iccm_wr_size; // @[el2_swerv_wrapper.scala 345:19] + wire [77:0] mem_iccm_wr_data; // @[el2_swerv_wrapper.scala 345:19] + wire [30:0] mem_ic_rw_addr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_tag_valid; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_wr_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_rd_en; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_ic_premux_data; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_wr_data_0; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_wr_data_1; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 345:19] + wire [9:0] mem_ic_debug_addr; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_debug_way; // @[el2_swerv_wrapper.scala 345:19] + wire mem_scan_mode; // @[el2_swerv_wrapper.scala 345:19] + wire [77:0] mem_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 345:19] + wire [38:0] mem_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_ic_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [25:0] mem_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_eccerr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_parerr; // @[el2_swerv_wrapper.scala 345:19] + wire [1:0] mem_ic_rd_hit; // @[el2_swerv_wrapper.scala 345:19] + wire mem_ic_tag_perr; // @[el2_swerv_wrapper.scala 345:19] + wire [70:0] mem_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire [63:0] mem_iccm_rd_data; // @[el2_swerv_wrapper.scala 345:19] + wire dmi_wrapper_trst_n; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tck; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tms; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdi; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdo; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_tdoEnable; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_core_rst_n; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_core_clk; // @[el2_swerv_wrapper.scala 346:27] + wire [30:0] dmi_wrapper_jtag_id; // @[el2_swerv_wrapper.scala 346:27] + wire [31:0] dmi_wrapper_rd_data; // @[el2_swerv_wrapper.scala 346:27] + wire [31:0] dmi_wrapper_reg_wr_data; // @[el2_swerv_wrapper.scala 346:27] + wire [6:0] dmi_wrapper_reg_wr_addr; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_reg_en; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_reg_wr_en; // @[el2_swerv_wrapper.scala 346:27] + wire dmi_wrapper_dmi_hard_reset; // @[el2_swerv_wrapper.scala 346:27] + wire swerv_clock; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_reset; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dbg_rst_l; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_rst_vec; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_nmi_int; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_nmi_vec; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_core_rst_l; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_insn_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_address_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_valid_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_exception_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [4:0] swerv_io_trace_rv_i_ecause_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_trace_rv_i_interrupt_ip; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_trace_rv_i_tval_ip; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_clk_override; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_icm_clk_override; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_i_cpu_halt_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_i_cpu_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_halt_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_halt_status; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_cpu_run_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_o_debug_mode_status; // @[el2_swerv_wrapper.scala 347:21] + wire [27:0] swerv_io_core_id; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_halt_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_reset_run_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_halt_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_mpc_debug_run_ack; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_debug_brkpt_status; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt0; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt1; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt2; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dec_tlu_perfcnt3; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_wren; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dccm_rden; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [15:0] swerv_io_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 347:21] + wire [38:0] swerv_io_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 347:21] + wire [14:0] swerv_io_iccm_rw_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_wren; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_rden; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_iccm_wr_size; // @[el2_swerv_wrapper.scala 347:21] + wire [77:0] swerv_io_iccm_wr_data; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_iccm_correction_state; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_iccm_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [77:0] swerv_io_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_ic_rw_addr; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_tag_valid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_rd_en; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_wr_data_0; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_wr_data_1; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ic_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [25:0] swerv_io_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 347:21] + wire [70:0] swerv_io_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_eccerr; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ic_premux_data; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 347:21] + wire [9:0] swerv_io_ic_debug_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_debug_way; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ic_rd_hit; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ic_tag_perr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_awid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_lsu_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_awregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_awcache; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_lsu_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_lsu_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_lsu_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_bid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_lsu_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_lsu_axi_arcache; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_lsu_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_lsu_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_ifu_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_ifu_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_ifu_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_ifu_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_ifu_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_ifu_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_sb_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_sb_axi_awregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_sb_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_sb_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_sb_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_sb_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_sb_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [3:0] swerv_io_sb_axi_arregion; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_sb_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_sb_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_sb_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_sb_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_awid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dma_axi_awaddr; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_dma_axi_awsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_wvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_wready; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_dma_axi_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [7:0] swerv_io_dma_axi_wstrb; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bready; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_dma_axi_bresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_bid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_arid; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dma_axi_araddr; // @[el2_swerv_wrapper.scala 347:21] + wire [2:0] swerv_io_dma_axi_arsize; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rvalid; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rready; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_axi_rid; // @[el2_swerv_wrapper.scala 347:21] + wire [63:0] swerv_io_dma_axi_rdata; // @[el2_swerv_wrapper.scala 347:21] + wire [1:0] swerv_io_dma_axi_rresp; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_lsu_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_ifu_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dbg_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dma_bus_clk_en; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dmi_reg_en; // @[el2_swerv_wrapper.scala 347:21] + wire [6:0] swerv_io_dmi_reg_addr; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_dmi_reg_wr_en; // @[el2_swerv_wrapper.scala 347:21] + wire [31:0] swerv_io_dmi_reg_wdata; // @[el2_swerv_wrapper.scala 347:21] + wire [30:0] swerv_io_extintsrc_req; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_timer_int; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_soft_int; // @[el2_swerv_wrapper.scala 347:21] + wire swerv_io_scan_mode; // @[el2_swerv_wrapper.scala 347:21] + el2_mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[el2_swerv_wrapper.scala 345:19] .clk(mem_clk), .rst_l(mem_rst_l), .dccm_clk_override(mem_dccm_clk_override), @@ -82849,7 +82849,7 @@ module el2_swerv_wrapper( .ic_debug_rd_data(mem_ic_debug_rd_data), .iccm_rd_data(mem_iccm_rd_data) ); - dmi_wrapper dmi_wrapper ( // @[SweRV_Wrapper.scala 346:27] + dmi_wrapper dmi_wrapper ( // @[el2_swerv_wrapper.scala 346:27] .trst_n(dmi_wrapper_trst_n), .tck(dmi_wrapper_tck), .tms(dmi_wrapper_tms), @@ -82866,7 +82866,7 @@ module el2_swerv_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - el2_swerv swerv ( // @[SweRV_Wrapper.scala 347:21] + el2_swerv swerv ( // @[el2_swerv_wrapper.scala 347:21] .clock(swerv_clock), .reset(swerv_reset), .io_dbg_rst_l(swerv_io_dbg_rst_l), @@ -83028,233 +83028,233 @@ module el2_swerv_wrapper( .io_soft_int(swerv_io_soft_int), .io_scan_mode(swerv_io_scan_mode) ); - assign io_trace_rv_i_insn_ip = swerv_io_trace_rv_i_insn_ip; // @[SweRV_Wrapper.scala 558:25] - assign io_trace_rv_i_address_ip = swerv_io_trace_rv_i_address_ip; // @[SweRV_Wrapper.scala 559:28] - assign io_trace_rv_i_valid_ip = swerv_io_trace_rv_i_valid_ip; // @[SweRV_Wrapper.scala 560:26] - assign io_trace_rv_i_exception_ip = swerv_io_trace_rv_i_exception_ip; // @[SweRV_Wrapper.scala 561:30] - assign io_trace_rv_i_ecause_ip = swerv_io_trace_rv_i_ecause_ip; // @[SweRV_Wrapper.scala 562:27] - assign io_trace_rv_i_interrupt_ip = swerv_io_trace_rv_i_interrupt_ip; // @[SweRV_Wrapper.scala 563:30] - assign io_trace_rv_i_tval_ip = swerv_io_trace_rv_i_tval_ip; // @[SweRV_Wrapper.scala 564:25] - assign io_lsu_axi_awvalid = swerv_io_lsu_axi_awvalid; // @[SweRV_Wrapper.scala 584:22] - assign io_lsu_axi_awid = swerv_io_lsu_axi_awid; // @[SweRV_Wrapper.scala 585:19] - assign io_lsu_axi_awaddr = swerv_io_lsu_axi_awaddr; // @[SweRV_Wrapper.scala 586:21] - assign io_lsu_axi_awregion = swerv_io_lsu_axi_awregion; // @[SweRV_Wrapper.scala 587:23] - assign io_lsu_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 588:20] - assign io_lsu_axi_awsize = swerv_io_lsu_axi_awsize; // @[SweRV_Wrapper.scala 589:21] - assign io_lsu_axi_awburst = 2'h1; // @[SweRV_Wrapper.scala 590:22] - assign io_lsu_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 591:21] - assign io_lsu_axi_awcache = swerv_io_lsu_axi_awcache; // @[SweRV_Wrapper.scala 592:22] - assign io_lsu_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 593:21] - assign io_lsu_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 594:20] - assign io_lsu_axi_wvalid = swerv_io_lsu_axi_wvalid; // @[SweRV_Wrapper.scala 596:21] - assign io_lsu_axi_wdata = swerv_io_lsu_axi_wdata; // @[SweRV_Wrapper.scala 597:20] - assign io_lsu_axi_wstrb = swerv_io_lsu_axi_wstrb; // @[SweRV_Wrapper.scala 598:20] - assign io_lsu_axi_wlast = 1'h1; // @[SweRV_Wrapper.scala 599:20] - assign io_lsu_axi_bready = 1'h1; // @[SweRV_Wrapper.scala 600:21] - assign io_lsu_axi_arvalid = swerv_io_lsu_axi_arvalid; // @[SweRV_Wrapper.scala 603:22] - assign io_lsu_axi_arid = swerv_io_lsu_axi_arid; // @[SweRV_Wrapper.scala 604:19] - assign io_lsu_axi_araddr = swerv_io_lsu_axi_araddr; // @[SweRV_Wrapper.scala 605:21] - assign io_lsu_axi_arregion = swerv_io_lsu_axi_arregion; // @[SweRV_Wrapper.scala 606:23] - assign io_lsu_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 607:20] - assign io_lsu_axi_arsize = swerv_io_lsu_axi_arsize; // @[SweRV_Wrapper.scala 608:21] - assign io_lsu_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 609:22] - assign io_lsu_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 610:21] - assign io_lsu_axi_arcache = swerv_io_lsu_axi_arcache; // @[SweRV_Wrapper.scala 611:22] - assign io_lsu_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 612:21] - assign io_lsu_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 613:20] - assign io_lsu_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 614:21] - assign io_ifu_axi_awvalid = 1'h0; // @[SweRV_Wrapper.scala 616:22] - assign io_ifu_axi_awid = 3'h0; // @[SweRV_Wrapper.scala 617:19] - assign io_ifu_axi_awaddr = 32'h0; // @[SweRV_Wrapper.scala 618:21] - assign io_ifu_axi_awregion = 4'h0; // @[SweRV_Wrapper.scala 619:23] - assign io_ifu_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 620:20] - assign io_ifu_axi_awsize = 3'h0; // @[SweRV_Wrapper.scala 621:21] - assign io_ifu_axi_awburst = 2'h0; // @[SweRV_Wrapper.scala 622:22] - assign io_ifu_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 623:21] - assign io_ifu_axi_awcache = 4'h0; // @[SweRV_Wrapper.scala 624:22] - assign io_ifu_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 625:21] - assign io_ifu_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 626:20] - assign io_ifu_axi_wvalid = 1'h0; // @[SweRV_Wrapper.scala 627:21] - assign io_ifu_axi_wdata = 64'h0; // @[SweRV_Wrapper.scala 628:20] - assign io_ifu_axi_wstrb = 8'h0; // @[SweRV_Wrapper.scala 629:20] - assign io_ifu_axi_wlast = 1'h0; // @[SweRV_Wrapper.scala 630:20] - assign io_ifu_axi_bready = 1'h0; // @[SweRV_Wrapper.scala 632:21] - assign io_ifu_axi_arvalid = swerv_io_ifu_axi_arvalid; // @[SweRV_Wrapper.scala 635:22] - assign io_ifu_axi_arid = swerv_io_ifu_axi_arid; // @[SweRV_Wrapper.scala 636:19] - assign io_ifu_axi_araddr = swerv_io_ifu_axi_araddr; // @[SweRV_Wrapper.scala 637:21] - assign io_ifu_axi_arregion = swerv_io_ifu_axi_arregion; // @[SweRV_Wrapper.scala 638:23] - assign io_ifu_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 639:20] - assign io_ifu_axi_arsize = 3'h3; // @[SweRV_Wrapper.scala 640:21] - assign io_ifu_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 641:22] - assign io_ifu_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 642:21] - assign io_ifu_axi_arcache = 4'hf; // @[SweRV_Wrapper.scala 643:22] - assign io_ifu_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 644:21] - assign io_ifu_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 645:20] - assign io_ifu_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 646:21] - assign io_sb_axi_awvalid = swerv_io_sb_axi_awvalid; // @[SweRV_Wrapper.scala 649:21] - assign io_sb_axi_awid = 1'h0; // @[SweRV_Wrapper.scala 650:18] - assign io_sb_axi_awaddr = swerv_io_sb_axi_awaddr; // @[SweRV_Wrapper.scala 651:20] - assign io_sb_axi_awregion = swerv_io_sb_axi_awregion; // @[SweRV_Wrapper.scala 652:22] - assign io_sb_axi_awlen = 8'h0; // @[SweRV_Wrapper.scala 653:19] - assign io_sb_axi_awsize = swerv_io_sb_axi_awsize; // @[SweRV_Wrapper.scala 654:20] - assign io_sb_axi_awburst = 2'h1; // @[SweRV_Wrapper.scala 655:21] - assign io_sb_axi_awlock = 1'h0; // @[SweRV_Wrapper.scala 656:20] - assign io_sb_axi_awcache = 4'hf; // @[SweRV_Wrapper.scala 657:21] - assign io_sb_axi_awprot = 3'h0; // @[SweRV_Wrapper.scala 658:20] - assign io_sb_axi_awqos = 4'h0; // @[SweRV_Wrapper.scala 659:19] - assign io_sb_axi_wvalid = swerv_io_sb_axi_wvalid; // @[SweRV_Wrapper.scala 661:19] - assign io_sb_axi_wdata = swerv_io_sb_axi_wdata; // @[SweRV_Wrapper.scala 662:19] - assign io_sb_axi_wstrb = swerv_io_sb_axi_wstrb; // @[SweRV_Wrapper.scala 663:19] - assign io_sb_axi_wlast = 1'h1; // @[SweRV_Wrapper.scala 664:19] - assign io_sb_axi_bready = 1'h1; // @[SweRV_Wrapper.scala 665:20] - assign io_sb_axi_arvalid = swerv_io_sb_axi_arvalid; // @[SweRV_Wrapper.scala 668:21] - assign io_sb_axi_arid = 1'h0; // @[SweRV_Wrapper.scala 669:18] - assign io_sb_axi_araddr = swerv_io_sb_axi_araddr; // @[SweRV_Wrapper.scala 670:20] - assign io_sb_axi_arregion = swerv_io_sb_axi_arregion; // @[SweRV_Wrapper.scala 671:22] - assign io_sb_axi_arlen = 8'h0; // @[SweRV_Wrapper.scala 672:19] - assign io_sb_axi_arsize = swerv_io_sb_axi_arsize; // @[SweRV_Wrapper.scala 673:20] - assign io_sb_axi_arburst = 2'h1; // @[SweRV_Wrapper.scala 674:21] - assign io_sb_axi_arlock = 1'h0; // @[SweRV_Wrapper.scala 675:20] - assign io_sb_axi_arcache = 4'h0; // @[SweRV_Wrapper.scala 676:21] - assign io_sb_axi_arprot = 3'h0; // @[SweRV_Wrapper.scala 677:20] - assign io_sb_axi_arqos = 4'h0; // @[SweRV_Wrapper.scala 678:19] - assign io_sb_axi_rready = 1'h1; // @[SweRV_Wrapper.scala 679:20] - assign io_dma_axi_awready = swerv_io_dma_axi_awready; // @[SweRV_Wrapper.scala 682:22] - assign io_dma_axi_wready = swerv_io_dma_axi_wready; // @[SweRV_Wrapper.scala 683:21] - assign io_dma_axi_bvalid = swerv_io_dma_axi_bvalid; // @[SweRV_Wrapper.scala 685:21] - assign io_dma_axi_bresp = swerv_io_dma_axi_bresp; // @[SweRV_Wrapper.scala 686:20] - assign io_dma_axi_bid = swerv_io_dma_axi_bid; // @[SweRV_Wrapper.scala 687:18] - assign io_dma_axi_arready = swerv_io_dma_axi_arready; // @[SweRV_Wrapper.scala 690:22] - assign io_dma_axi_rvalid = swerv_io_dma_axi_rvalid; // @[SweRV_Wrapper.scala 691:21] - assign io_dma_axi_rid = swerv_io_dma_axi_rid; // @[SweRV_Wrapper.scala 692:18] - assign io_dma_axi_rdata = swerv_io_dma_axi_rdata; // @[SweRV_Wrapper.scala 693:20] - assign io_dma_axi_rresp = swerv_io_dma_axi_rresp; // @[SweRV_Wrapper.scala 694:20] - assign io_dma_axi_rlast = 1'h1; // @[SweRV_Wrapper.scala 695:20] - assign io_dma_hrdata = 64'h0; // @[SweRV_Wrapper.scala 698:17] - assign io_dma_hreadyout = 1'h0; // @[SweRV_Wrapper.scala 699:20] - assign io_dma_hresp = 1'h0; // @[SweRV_Wrapper.scala 700:16] - assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[SweRV_Wrapper.scala 576:23] - assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[SweRV_Wrapper.scala 577:23] - assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[SweRV_Wrapper.scala 578:23] - assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[SweRV_Wrapper.scala 579:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[SweRV_Wrapper.scala 363:15] - assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[SweRV_Wrapper.scala 572:25] - assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[SweRV_Wrapper.scala 573:24] - assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[SweRV_Wrapper.scala 574:25] - assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[SweRV_Wrapper.scala 567:21] - assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[SweRV_Wrapper.scala 568:24] - assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[SweRV_Wrapper.scala 570:26] - assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[SweRV_Wrapper.scala 569:20] - assign mem_clk = clock; // @[SweRV_Wrapper.scala 403:14] - assign mem_rst_l = reset; // @[SweRV_Wrapper.scala 402:16] - assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[SweRV_Wrapper.scala 366:28] - assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[SweRV_Wrapper.scala 367:27] - assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[SweRV_Wrapper.scala 368:35] - assign mem_dccm_wren = swerv_io_dccm_wren; // @[SweRV_Wrapper.scala 369:20] - assign mem_dccm_rden = swerv_io_dccm_rden; // @[SweRV_Wrapper.scala 370:20] - assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[SweRV_Wrapper.scala 371:26] - assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[SweRV_Wrapper.scala 372:26] - assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[SweRV_Wrapper.scala 373:26] - assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[SweRV_Wrapper.scala 378:26] - assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[SweRV_Wrapper.scala 375:26] - assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[SweRV_Wrapper.scala 376:26] - assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[SweRV_Wrapper.scala 379:23] - assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[SweRV_Wrapper.scala 380:31] - assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[SweRV_Wrapper.scala 381:32] - assign mem_iccm_wren = swerv_io_iccm_wren; // @[SweRV_Wrapper.scala 382:20] - assign mem_iccm_rden = swerv_io_iccm_rden; // @[SweRV_Wrapper.scala 383:20] - assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[SweRV_Wrapper.scala 384:23] - assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[SweRV_Wrapper.scala 385:23] - assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[SweRV_Wrapper.scala 388:21] - assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[SweRV_Wrapper.scala 389:23] - assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[SweRV_Wrapper.scala 390:19] - assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[SweRV_Wrapper.scala 391:19] - assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[SweRV_Wrapper.scala 392:25] - assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[SweRV_Wrapper.scala 393:29] - assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[SweRV_Wrapper.scala 394:21] - assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[SweRV_Wrapper.scala 394:21] - assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[SweRV_Wrapper.scala 395:27] - assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[SweRV_Wrapper.scala 397:24] - assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[SweRV_Wrapper.scala 398:25] - assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[SweRV_Wrapper.scala 399:25] - assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[SweRV_Wrapper.scala 400:29] - assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[SweRV_Wrapper.scala 401:23] - assign mem_scan_mode = io_scan_mode; // @[SweRV_Wrapper.scala 404:20] - assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[SweRV_Wrapper.scala 348:25] - assign dmi_wrapper_tck = io_jtag_tck; // @[SweRV_Wrapper.scala 349:22] - assign dmi_wrapper_tms = io_jtag_tms; // @[SweRV_Wrapper.scala 350:22] - assign dmi_wrapper_tdi = io_jtag_tdi; // @[SweRV_Wrapper.scala 351:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[SweRV_Wrapper.scala 357:29] - assign dmi_wrapper_core_clk = clock; // @[SweRV_Wrapper.scala 352:27] - assign dmi_wrapper_jtag_id = io_jtag_id; // @[SweRV_Wrapper.scala 353:26] - assign dmi_wrapper_rd_data = 32'h0; // @[SweRV_Wrapper.scala 354:26] + assign io_trace_rv_i_insn_ip = swerv_io_trace_rv_i_insn_ip; // @[el2_swerv_wrapper.scala 558:25] + assign io_trace_rv_i_address_ip = swerv_io_trace_rv_i_address_ip; // @[el2_swerv_wrapper.scala 559:28] + assign io_trace_rv_i_valid_ip = swerv_io_trace_rv_i_valid_ip; // @[el2_swerv_wrapper.scala 560:26] + assign io_trace_rv_i_exception_ip = swerv_io_trace_rv_i_exception_ip; // @[el2_swerv_wrapper.scala 561:30] + assign io_trace_rv_i_ecause_ip = swerv_io_trace_rv_i_ecause_ip; // @[el2_swerv_wrapper.scala 562:27] + assign io_trace_rv_i_interrupt_ip = swerv_io_trace_rv_i_interrupt_ip; // @[el2_swerv_wrapper.scala 563:30] + assign io_trace_rv_i_tval_ip = swerv_io_trace_rv_i_tval_ip; // @[el2_swerv_wrapper.scala 564:25] + assign io_lsu_axi_awvalid = swerv_io_lsu_axi_awvalid; // @[el2_swerv_wrapper.scala 584:22] + assign io_lsu_axi_awid = swerv_io_lsu_axi_awid; // @[el2_swerv_wrapper.scala 585:19] + assign io_lsu_axi_awaddr = swerv_io_lsu_axi_awaddr; // @[el2_swerv_wrapper.scala 586:21] + assign io_lsu_axi_awregion = swerv_io_lsu_axi_awregion; // @[el2_swerv_wrapper.scala 587:23] + assign io_lsu_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 588:20] + assign io_lsu_axi_awsize = swerv_io_lsu_axi_awsize; // @[el2_swerv_wrapper.scala 589:21] + assign io_lsu_axi_awburst = 2'h1; // @[el2_swerv_wrapper.scala 590:22] + assign io_lsu_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 591:21] + assign io_lsu_axi_awcache = swerv_io_lsu_axi_awcache; // @[el2_swerv_wrapper.scala 592:22] + assign io_lsu_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 593:21] + assign io_lsu_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 594:20] + assign io_lsu_axi_wvalid = swerv_io_lsu_axi_wvalid; // @[el2_swerv_wrapper.scala 596:21] + assign io_lsu_axi_wdata = swerv_io_lsu_axi_wdata; // @[el2_swerv_wrapper.scala 597:20] + assign io_lsu_axi_wstrb = swerv_io_lsu_axi_wstrb; // @[el2_swerv_wrapper.scala 598:20] + assign io_lsu_axi_wlast = 1'h1; // @[el2_swerv_wrapper.scala 599:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_swerv_wrapper.scala 600:21] + assign io_lsu_axi_arvalid = swerv_io_lsu_axi_arvalid; // @[el2_swerv_wrapper.scala 603:22] + assign io_lsu_axi_arid = swerv_io_lsu_axi_arid; // @[el2_swerv_wrapper.scala 604:19] + assign io_lsu_axi_araddr = swerv_io_lsu_axi_araddr; // @[el2_swerv_wrapper.scala 605:21] + assign io_lsu_axi_arregion = swerv_io_lsu_axi_arregion; // @[el2_swerv_wrapper.scala 606:23] + assign io_lsu_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 607:20] + assign io_lsu_axi_arsize = swerv_io_lsu_axi_arsize; // @[el2_swerv_wrapper.scala 608:21] + assign io_lsu_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 609:22] + assign io_lsu_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 610:21] + assign io_lsu_axi_arcache = swerv_io_lsu_axi_arcache; // @[el2_swerv_wrapper.scala 611:22] + assign io_lsu_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 612:21] + assign io_lsu_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 613:20] + assign io_lsu_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 614:21] + assign io_ifu_axi_awvalid = 1'h0; // @[el2_swerv_wrapper.scala 616:22] + assign io_ifu_axi_awid = 3'h0; // @[el2_swerv_wrapper.scala 617:19] + assign io_ifu_axi_awaddr = 32'h0; // @[el2_swerv_wrapper.scala 618:21] + assign io_ifu_axi_awregion = 4'h0; // @[el2_swerv_wrapper.scala 619:23] + assign io_ifu_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 620:20] + assign io_ifu_axi_awsize = 3'h0; // @[el2_swerv_wrapper.scala 621:21] + assign io_ifu_axi_awburst = 2'h0; // @[el2_swerv_wrapper.scala 622:22] + assign io_ifu_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 623:21] + assign io_ifu_axi_awcache = 4'h0; // @[el2_swerv_wrapper.scala 624:22] + assign io_ifu_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 625:21] + assign io_ifu_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 626:20] + assign io_ifu_axi_wvalid = 1'h0; // @[el2_swerv_wrapper.scala 627:21] + assign io_ifu_axi_wdata = 64'h0; // @[el2_swerv_wrapper.scala 628:20] + assign io_ifu_axi_wstrb = 8'h0; // @[el2_swerv_wrapper.scala 629:20] + assign io_ifu_axi_wlast = 1'h0; // @[el2_swerv_wrapper.scala 630:20] + assign io_ifu_axi_bready = 1'h0; // @[el2_swerv_wrapper.scala 632:21] + assign io_ifu_axi_arvalid = swerv_io_ifu_axi_arvalid; // @[el2_swerv_wrapper.scala 635:22] + assign io_ifu_axi_arid = swerv_io_ifu_axi_arid; // @[el2_swerv_wrapper.scala 636:19] + assign io_ifu_axi_araddr = swerv_io_ifu_axi_araddr; // @[el2_swerv_wrapper.scala 637:21] + assign io_ifu_axi_arregion = swerv_io_ifu_axi_arregion; // @[el2_swerv_wrapper.scala 638:23] + assign io_ifu_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 639:20] + assign io_ifu_axi_arsize = 3'h3; // @[el2_swerv_wrapper.scala 640:21] + assign io_ifu_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 641:22] + assign io_ifu_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 642:21] + assign io_ifu_axi_arcache = 4'hf; // @[el2_swerv_wrapper.scala 643:22] + assign io_ifu_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 644:21] + assign io_ifu_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 645:20] + assign io_ifu_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 646:21] + assign io_sb_axi_awvalid = swerv_io_sb_axi_awvalid; // @[el2_swerv_wrapper.scala 649:21] + assign io_sb_axi_awid = 1'h0; // @[el2_swerv_wrapper.scala 650:18] + assign io_sb_axi_awaddr = swerv_io_sb_axi_awaddr; // @[el2_swerv_wrapper.scala 651:20] + assign io_sb_axi_awregion = swerv_io_sb_axi_awregion; // @[el2_swerv_wrapper.scala 652:22] + assign io_sb_axi_awlen = 8'h0; // @[el2_swerv_wrapper.scala 653:19] + assign io_sb_axi_awsize = swerv_io_sb_axi_awsize; // @[el2_swerv_wrapper.scala 654:20] + assign io_sb_axi_awburst = 2'h1; // @[el2_swerv_wrapper.scala 655:21] + assign io_sb_axi_awlock = 1'h0; // @[el2_swerv_wrapper.scala 656:20] + assign io_sb_axi_awcache = 4'hf; // @[el2_swerv_wrapper.scala 657:21] + assign io_sb_axi_awprot = 3'h0; // @[el2_swerv_wrapper.scala 658:20] + assign io_sb_axi_awqos = 4'h0; // @[el2_swerv_wrapper.scala 659:19] + assign io_sb_axi_wvalid = swerv_io_sb_axi_wvalid; // @[el2_swerv_wrapper.scala 661:19] + assign io_sb_axi_wdata = swerv_io_sb_axi_wdata; // @[el2_swerv_wrapper.scala 662:19] + assign io_sb_axi_wstrb = swerv_io_sb_axi_wstrb; // @[el2_swerv_wrapper.scala 663:19] + assign io_sb_axi_wlast = 1'h1; // @[el2_swerv_wrapper.scala 664:19] + assign io_sb_axi_bready = 1'h1; // @[el2_swerv_wrapper.scala 665:20] + assign io_sb_axi_arvalid = swerv_io_sb_axi_arvalid; // @[el2_swerv_wrapper.scala 668:21] + assign io_sb_axi_arid = 1'h0; // @[el2_swerv_wrapper.scala 669:18] + assign io_sb_axi_araddr = swerv_io_sb_axi_araddr; // @[el2_swerv_wrapper.scala 670:20] + assign io_sb_axi_arregion = swerv_io_sb_axi_arregion; // @[el2_swerv_wrapper.scala 671:22] + assign io_sb_axi_arlen = 8'h0; // @[el2_swerv_wrapper.scala 672:19] + assign io_sb_axi_arsize = swerv_io_sb_axi_arsize; // @[el2_swerv_wrapper.scala 673:20] + assign io_sb_axi_arburst = 2'h1; // @[el2_swerv_wrapper.scala 674:21] + assign io_sb_axi_arlock = 1'h0; // @[el2_swerv_wrapper.scala 675:20] + assign io_sb_axi_arcache = 4'h0; // @[el2_swerv_wrapper.scala 676:21] + assign io_sb_axi_arprot = 3'h0; // @[el2_swerv_wrapper.scala 677:20] + assign io_sb_axi_arqos = 4'h0; // @[el2_swerv_wrapper.scala 678:19] + assign io_sb_axi_rready = 1'h1; // @[el2_swerv_wrapper.scala 679:20] + assign io_dma_axi_awready = swerv_io_dma_axi_awready; // @[el2_swerv_wrapper.scala 682:22] + assign io_dma_axi_wready = swerv_io_dma_axi_wready; // @[el2_swerv_wrapper.scala 683:21] + assign io_dma_axi_bvalid = swerv_io_dma_axi_bvalid; // @[el2_swerv_wrapper.scala 685:21] + assign io_dma_axi_bresp = swerv_io_dma_axi_bresp; // @[el2_swerv_wrapper.scala 686:20] + assign io_dma_axi_bid = swerv_io_dma_axi_bid; // @[el2_swerv_wrapper.scala 687:18] + assign io_dma_axi_arready = swerv_io_dma_axi_arready; // @[el2_swerv_wrapper.scala 690:22] + assign io_dma_axi_rvalid = swerv_io_dma_axi_rvalid; // @[el2_swerv_wrapper.scala 691:21] + assign io_dma_axi_rid = swerv_io_dma_axi_rid; // @[el2_swerv_wrapper.scala 692:18] + assign io_dma_axi_rdata = swerv_io_dma_axi_rdata; // @[el2_swerv_wrapper.scala 693:20] + assign io_dma_axi_rresp = swerv_io_dma_axi_rresp; // @[el2_swerv_wrapper.scala 694:20] + assign io_dma_axi_rlast = 1'h1; // @[el2_swerv_wrapper.scala 695:20] + assign io_dma_hrdata = 64'h0; // @[el2_swerv_wrapper.scala 698:17] + assign io_dma_hreadyout = 1'h0; // @[el2_swerv_wrapper.scala 699:20] + assign io_dma_hresp = 1'h0; // @[el2_swerv_wrapper.scala 700:16] + assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[el2_swerv_wrapper.scala 576:23] + assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[el2_swerv_wrapper.scala 577:23] + assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[el2_swerv_wrapper.scala 578:23] + assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[el2_swerv_wrapper.scala 579:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[el2_swerv_wrapper.scala 363:15] + assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[el2_swerv_wrapper.scala 572:25] + assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[el2_swerv_wrapper.scala 573:24] + assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[el2_swerv_wrapper.scala 574:25] + assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[el2_swerv_wrapper.scala 567:21] + assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[el2_swerv_wrapper.scala 568:24] + assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[el2_swerv_wrapper.scala 570:26] + assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[el2_swerv_wrapper.scala 569:20] + assign mem_clk = clock; // @[el2_swerv_wrapper.scala 403:14] + assign mem_rst_l = reset; // @[el2_swerv_wrapper.scala 402:16] + assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[el2_swerv_wrapper.scala 366:28] + assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[el2_swerv_wrapper.scala 367:27] + assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[el2_swerv_wrapper.scala 368:35] + assign mem_dccm_wren = swerv_io_dccm_wren; // @[el2_swerv_wrapper.scala 369:20] + assign mem_dccm_rden = swerv_io_dccm_rden; // @[el2_swerv_wrapper.scala 370:20] + assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[el2_swerv_wrapper.scala 371:26] + assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[el2_swerv_wrapper.scala 372:26] + assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[el2_swerv_wrapper.scala 373:26] + assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[el2_swerv_wrapper.scala 378:26] + assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[el2_swerv_wrapper.scala 375:26] + assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[el2_swerv_wrapper.scala 376:26] + assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[el2_swerv_wrapper.scala 379:23] + assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[el2_swerv_wrapper.scala 380:31] + assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[el2_swerv_wrapper.scala 381:32] + assign mem_iccm_wren = swerv_io_iccm_wren; // @[el2_swerv_wrapper.scala 382:20] + assign mem_iccm_rden = swerv_io_iccm_rden; // @[el2_swerv_wrapper.scala 383:20] + assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[el2_swerv_wrapper.scala 384:23] + assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[el2_swerv_wrapper.scala 385:23] + assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[el2_swerv_wrapper.scala 388:21] + assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[el2_swerv_wrapper.scala 389:23] + assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[el2_swerv_wrapper.scala 390:19] + assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[el2_swerv_wrapper.scala 391:19] + assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[el2_swerv_wrapper.scala 392:25] + assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[el2_swerv_wrapper.scala 393:29] + assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[el2_swerv_wrapper.scala 394:21] + assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[el2_swerv_wrapper.scala 394:21] + assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[el2_swerv_wrapper.scala 395:27] + assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[el2_swerv_wrapper.scala 397:24] + assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[el2_swerv_wrapper.scala 398:25] + assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[el2_swerv_wrapper.scala 399:25] + assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[el2_swerv_wrapper.scala 400:29] + assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[el2_swerv_wrapper.scala 401:23] + assign mem_scan_mode = io_scan_mode; // @[el2_swerv_wrapper.scala 404:20] + assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[el2_swerv_wrapper.scala 348:25] + assign dmi_wrapper_tck = io_jtag_tck; // @[el2_swerv_wrapper.scala 349:22] + assign dmi_wrapper_tms = io_jtag_tms; // @[el2_swerv_wrapper.scala 350:22] + assign dmi_wrapper_tdi = io_jtag_tdi; // @[el2_swerv_wrapper.scala 351:22] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[el2_swerv_wrapper.scala 357:29] + assign dmi_wrapper_core_clk = clock; // @[el2_swerv_wrapper.scala 352:27] + assign dmi_wrapper_jtag_id = io_jtag_id; // @[el2_swerv_wrapper.scala 353:26] + assign dmi_wrapper_rd_data = 32'h0; // @[el2_swerv_wrapper.scala 354:26] assign swerv_clock = clock; assign swerv_reset = reset; - assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[SweRV_Wrapper.scala 406:22 SweRV_Wrapper.scala 428:22] - assign swerv_io_rst_vec = io_rst_vec; // @[SweRV_Wrapper.scala 429:20] - assign swerv_io_nmi_int = io_nmi_int; // @[SweRV_Wrapper.scala 430:20] - assign swerv_io_nmi_vec = io_nmi_vec; // @[SweRV_Wrapper.scala 431:20] - assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[SweRV_Wrapper.scala 434:27] - assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[SweRV_Wrapper.scala 435:26] - assign swerv_io_core_id = io_core_id; // @[SweRV_Wrapper.scala 436:20] - assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[SweRV_Wrapper.scala 439:31] - assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[SweRV_Wrapper.scala 440:30] - assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[SweRV_Wrapper.scala 441:30] - assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[SweRV_Wrapper.scala 377:28] - assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[SweRV_Wrapper.scala 408:28] - assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[SweRV_Wrapper.scala 416:25] - assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[SweRV_Wrapper.scala 407:29] - assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[SweRV_Wrapper.scala 409:23] - assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[SweRV_Wrapper.scala 415:29] - assign swerv_io_ictag_debug_rd_data = mem_ictag_debug_rd_data; // @[SweRV_Wrapper.scala 410:32] - assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[SweRV_Wrapper.scala 411:22] - assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[SweRV_Wrapper.scala 413:22] - assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[SweRV_Wrapper.scala 414:24] - assign swerv_io_lsu_axi_awready = io_lsu_axi_awready; // @[SweRV_Wrapper.scala 445:28] - assign swerv_io_lsu_axi_wready = io_lsu_axi_wready; // @[SweRV_Wrapper.scala 446:27] - assign swerv_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[SweRV_Wrapper.scala 448:27] - assign swerv_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[SweRV_Wrapper.scala 449:26] - assign swerv_io_lsu_axi_bid = io_lsu_axi_bid; // @[SweRV_Wrapper.scala 450:24] - assign swerv_io_lsu_axi_arready = io_lsu_axi_arready; // @[SweRV_Wrapper.scala 453:28] - assign swerv_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[SweRV_Wrapper.scala 454:27] - assign swerv_io_lsu_axi_rid = io_lsu_axi_rid; // @[SweRV_Wrapper.scala 455:24] - assign swerv_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[SweRV_Wrapper.scala 456:26] - assign swerv_io_ifu_axi_arready = io_ifu_axi_arready; // @[SweRV_Wrapper.scala 469:28] - assign swerv_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[SweRV_Wrapper.scala 470:27] - assign swerv_io_ifu_axi_rid = io_ifu_axi_rid; // @[SweRV_Wrapper.scala 471:24] - assign swerv_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[SweRV_Wrapper.scala 472:26] - assign swerv_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[SweRV_Wrapper.scala 473:26] - assign swerv_io_sb_axi_awready = io_sb_axi_awready; // @[SweRV_Wrapper.scala 478:27] - assign swerv_io_sb_axi_wready = io_sb_axi_wready; // @[SweRV_Wrapper.scala 479:26] - assign swerv_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[SweRV_Wrapper.scala 481:26] - assign swerv_io_sb_axi_bresp = io_sb_axi_bresp; // @[SweRV_Wrapper.scala 482:25] - assign swerv_io_sb_axi_arready = io_sb_axi_arready; // @[SweRV_Wrapper.scala 486:27] - assign swerv_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[SweRV_Wrapper.scala 487:26] - assign swerv_io_sb_axi_rdata = io_sb_axi_rdata; // @[SweRV_Wrapper.scala 489:25] - assign swerv_io_sb_axi_rresp = io_sb_axi_rresp; // @[SweRV_Wrapper.scala 490:25] - assign swerv_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[SweRV_Wrapper.scala 495:28] - assign swerv_io_dma_axi_awid = io_dma_axi_awid; // @[SweRV_Wrapper.scala 496:25] - assign swerv_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[SweRV_Wrapper.scala 497:27] - assign swerv_io_dma_axi_awsize = io_dma_axi_awsize; // @[SweRV_Wrapper.scala 498:27] - assign swerv_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[SweRV_Wrapper.scala 503:27] - assign swerv_io_dma_axi_wdata = io_dma_axi_wdata; // @[SweRV_Wrapper.scala 504:26] - assign swerv_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[SweRV_Wrapper.scala 505:26] - assign swerv_io_dma_axi_bready = io_dma_axi_bready; // @[SweRV_Wrapper.scala 507:27] - assign swerv_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[SweRV_Wrapper.scala 510:28] - assign swerv_io_dma_axi_arid = io_dma_axi_arid; // @[SweRV_Wrapper.scala 511:25] - assign swerv_io_dma_axi_araddr = io_dma_axi_araddr; // @[SweRV_Wrapper.scala 512:27] - assign swerv_io_dma_axi_arsize = io_dma_axi_arsize; // @[SweRV_Wrapper.scala 513:27] - assign swerv_io_dma_axi_rready = io_dma_axi_rready; // @[SweRV_Wrapper.scala 517:27] - assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[SweRV_Wrapper.scala 547:27] - assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[SweRV_Wrapper.scala 548:27] - assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[SweRV_Wrapper.scala 549:27] - assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[SweRV_Wrapper.scala 550:27] - assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[SweRV_Wrapper.scala 360:23] - assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[SweRV_Wrapper.scala 359:25] - assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[SweRV_Wrapper.scala 361:26] - assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[SweRV_Wrapper.scala 358:26] - assign swerv_io_extintsrc_req = io_extintsrc_req; // @[SweRV_Wrapper.scala 554:26] - assign swerv_io_timer_int = io_timer_int; // @[SweRV_Wrapper.scala 552:22] - assign swerv_io_soft_int = io_soft_int; // @[SweRV_Wrapper.scala 553:21] - assign swerv_io_scan_mode = io_scan_mode; // @[SweRV_Wrapper.scala 426:22] + assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[el2_swerv_wrapper.scala 406:22 el2_swerv_wrapper.scala 428:22] + assign swerv_io_rst_vec = io_rst_vec; // @[el2_swerv_wrapper.scala 429:20] + assign swerv_io_nmi_int = io_nmi_int; // @[el2_swerv_wrapper.scala 430:20] + assign swerv_io_nmi_vec = io_nmi_vec; // @[el2_swerv_wrapper.scala 431:20] + assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv_wrapper.scala 434:27] + assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv_wrapper.scala 435:26] + assign swerv_io_core_id = io_core_id; // @[el2_swerv_wrapper.scala 436:20] + assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv_wrapper.scala 439:31] + assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv_wrapper.scala 440:30] + assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv_wrapper.scala 441:30] + assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[el2_swerv_wrapper.scala 377:28] + assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[el2_swerv_wrapper.scala 408:28] + assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[el2_swerv_wrapper.scala 416:25] + assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[el2_swerv_wrapper.scala 407:29] + assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[el2_swerv_wrapper.scala 409:23] + assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[el2_swerv_wrapper.scala 415:29] + assign swerv_io_ictag_debug_rd_data = mem_ictag_debug_rd_data; // @[el2_swerv_wrapper.scala 410:32] + assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[el2_swerv_wrapper.scala 411:22] + assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[el2_swerv_wrapper.scala 413:22] + assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[el2_swerv_wrapper.scala 414:24] + assign swerv_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_swerv_wrapper.scala 445:28] + assign swerv_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_swerv_wrapper.scala 446:27] + assign swerv_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_swerv_wrapper.scala 448:27] + assign swerv_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_swerv_wrapper.scala 449:26] + assign swerv_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_swerv_wrapper.scala 450:24] + assign swerv_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_swerv_wrapper.scala 453:28] + assign swerv_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_swerv_wrapper.scala 454:27] + assign swerv_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_swerv_wrapper.scala 455:24] + assign swerv_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_swerv_wrapper.scala 456:26] + assign swerv_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_swerv_wrapper.scala 469:28] + assign swerv_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_swerv_wrapper.scala 470:27] + assign swerv_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_swerv_wrapper.scala 471:24] + assign swerv_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_swerv_wrapper.scala 472:26] + assign swerv_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_swerv_wrapper.scala 473:26] + assign swerv_io_sb_axi_awready = io_sb_axi_awready; // @[el2_swerv_wrapper.scala 478:27] + assign swerv_io_sb_axi_wready = io_sb_axi_wready; // @[el2_swerv_wrapper.scala 479:26] + assign swerv_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[el2_swerv_wrapper.scala 481:26] + assign swerv_io_sb_axi_bresp = io_sb_axi_bresp; // @[el2_swerv_wrapper.scala 482:25] + assign swerv_io_sb_axi_arready = io_sb_axi_arready; // @[el2_swerv_wrapper.scala 486:27] + assign swerv_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[el2_swerv_wrapper.scala 487:26] + assign swerv_io_sb_axi_rdata = io_sb_axi_rdata; // @[el2_swerv_wrapper.scala 489:25] + assign swerv_io_sb_axi_rresp = io_sb_axi_rresp; // @[el2_swerv_wrapper.scala 490:25] + assign swerv_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[el2_swerv_wrapper.scala 495:28] + assign swerv_io_dma_axi_awid = io_dma_axi_awid; // @[el2_swerv_wrapper.scala 496:25] + assign swerv_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[el2_swerv_wrapper.scala 497:27] + assign swerv_io_dma_axi_awsize = io_dma_axi_awsize; // @[el2_swerv_wrapper.scala 498:27] + assign swerv_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[el2_swerv_wrapper.scala 503:27] + assign swerv_io_dma_axi_wdata = io_dma_axi_wdata; // @[el2_swerv_wrapper.scala 504:26] + assign swerv_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[el2_swerv_wrapper.scala 505:26] + assign swerv_io_dma_axi_bready = io_dma_axi_bready; // @[el2_swerv_wrapper.scala 507:27] + assign swerv_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[el2_swerv_wrapper.scala 510:28] + assign swerv_io_dma_axi_arid = io_dma_axi_arid; // @[el2_swerv_wrapper.scala 511:25] + assign swerv_io_dma_axi_araddr = io_dma_axi_araddr; // @[el2_swerv_wrapper.scala 512:27] + assign swerv_io_dma_axi_arsize = io_dma_axi_arsize; // @[el2_swerv_wrapper.scala 513:27] + assign swerv_io_dma_axi_rready = io_dma_axi_rready; // @[el2_swerv_wrapper.scala 517:27] + assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_swerv_wrapper.scala 547:27] + assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_swerv_wrapper.scala 548:27] + assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[el2_swerv_wrapper.scala 549:27] + assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[el2_swerv_wrapper.scala 550:27] + assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[el2_swerv_wrapper.scala 360:23] + assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[el2_swerv_wrapper.scala 359:25] + assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[el2_swerv_wrapper.scala 361:26] + assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[el2_swerv_wrapper.scala 358:26] + assign swerv_io_extintsrc_req = io_extintsrc_req; // @[el2_swerv_wrapper.scala 554:26] + assign swerv_io_timer_int = io_timer_int; // @[el2_swerv_wrapper.scala 552:22] + assign swerv_io_soft_int = io_soft_int; // @[el2_swerv_wrapper.scala 553:21] + assign swerv_io_scan_mode = io_scan_mode; // @[el2_swerv_wrapper.scala 426:22] endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index bde2aec4..4ec29fe7 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v -/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv -/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala index 382f5d37..65912352 100644 --- a/src/main/scala/dec/el2_dec_decode_ctl.scala +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -133,11 +133,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val x_t_in = Wire(new el2_trap_pkt_t) val r_t = Wire(new el2_trap_pkt_t) val r_t_in = Wire(new el2_trap_pkt_t) - val d_d = Wire(Valid(new el2_dest_pkt_t)) - val x_d = Wire(Valid(new el2_dest_pkt_t)) - val r_d = Wire(Valid(new el2_dest_pkt_t)) - val r_d_in = Wire(Valid(new el2_dest_pkt_t)) - val wbd = Wire(Valid(new el2_dest_pkt_t)) + val d_d = Wire(new el2_dest_pkt_t) + val x_d = Wire(new el2_dest_pkt_t) + val r_d = Wire(new el2_dest_pkt_t) + val r_d_in = Wire(new el2_dest_pkt_t) + val wbd = Wire(new el2_dest_pkt_t) val i0_d_c = Wire(new el2_class_pkt_t) val i0_rs1_class_d = Wire(new el2_class_pkt_t) val i0_rs2_class_d = Wire(new el2_class_pkt_t) @@ -311,12 +311,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error val cam_data_reset_tag = io.lsu_nonblock_load_data_tag - val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data + val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data val load_data_tag = io.lsu_nonblock_load_data_tag // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one // don't writeback a nonblock load val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} - val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load + val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load for(i <- 0 until LSU_NUM_NBLOAD){ cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid @@ -331,7 +331,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ cam_in(i).bits.wb := 0.U(1.W) cam_in(i).bits.tag := cam_write_tag cam_in(i).bits.rd := nonblock_load_rd - }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ cam_in(i).valid := 0.U }.otherwise{ cam_in(i) := cam(i) @@ -350,7 +350,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_nonblock_load_waddr:=0.U(5.W) // cancel if any younger inst (including another nonblock) committing this cycle - val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) + val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) @@ -464,14 +464,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ //dec_csr_wen_unq_d assigned as csr_write above io.dec_csr_rdaddr_d := i0(31,20) - io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a el2_dest_pkt + io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb // also use valid so it's flushable - io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r; + io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r; // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. - io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb; + io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb; val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} @@ -511,9 +511,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val pause_stall = pause_state // for csr write only data is produced by the alu - io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data) + io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data) - val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly; + val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly; val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0) val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1) @@ -559,8 +559,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_pmu_postsync_stall := postsync_stall.asBool io.dec_pmu_presync_stall := presync_stall.asBool - val prior_inflight_x = x_d.valid - val prior_inflight_wb = r_d.valid + val prior_inflight_x = x_d.i0valid + val prior_inflight_wb = r_d.i0valid val prior_inflight = prior_inflight_x | prior_inflight_wb val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) @@ -575,7 +575,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ mul_decode_d := i0_exulegal_decode_d & i0_dp.mul div_decode_d := i0_exulegal_decode_d & i0_dp.div - io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb + io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb //traps for TLU (tlu stuff) d_t.legal := i0_legal_decode_d @@ -604,13 +604,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ r_t_in := r_t - r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger + r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } io.dec_tlu_packet_r := r_t_in - io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid + io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid // end tlu stuff flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} @@ -662,52 +662,52 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) - d_d.bits.i0rd := i0r.rd - d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d - d_d.valid := io.dec_i0_decode_d // has flush_final_r + d_d.i0rd := i0r.rd + d_d.i0v := i0_rd_en_d & i0_legal_decode_d + d_d.i0valid := io.dec_i0_decode_d // has flush_final_r - d_d.bits.i0load := i0_dp.load & i0_legal_decode_d - d_d.bits.i0store := i0_dp.store & i0_legal_decode_d - d_d.bits.i0div := i0_dp.div & i0_legal_decode_d + d_d.i0load := i0_dp.load & i0_legal_decode_d + d_d.i0store := i0_dp.store & i0_legal_decode_d + d_d.i0div := i0_dp.div & i0_legal_decode_d - d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d - d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d - d_d.bits.csrwaddr := i0(31,20) + d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d + d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d + d_d.csrwaddr := i0(31,20) x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) - val x_d_in = Wire(Valid(new el2_dest_pkt_t)) + val x_d_in = Wire(new el2_dest_pkt_t) x_d_in := x_d - x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r - x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) r_d_in := r_d - r_d_in.bits.i0rd := r_d.bits.i0rd + r_d_in.i0rd := r_d.i0rd - r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb) - r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb) - r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb - r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb + r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb) + r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb) + r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb + r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) - io.dec_i0_waddr_r := r_d_in.bits.i0rd - i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r - io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe + io.dec_i0_waddr_r := r_d_in.i0rd + i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r + io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe io.dec_i0_wdata_r := i0_result_corr_r val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) if ( LOAD_TO_USE_PLUS1 == 1 ) { i0_result_x := io.exu_i0_result_x - i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) + i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw) } else { - i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) + i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) i0_result_r := i0_result_r_raw } // correct lsu load data - don't use for bypass, do pass down the pipe - i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) + i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) val last_br_immed_d = WireInit(UInt(12.W),0.U) last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) @@ -716,16 +716,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ // divide stuff - val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid) + val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid) - val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) | - (x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) | - (r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) + val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) | + (x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) | + (r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) // cancel if any younger inst committing this cycle to same dest as nonblock divide val nonblock_div_cancel = (io.dec_div_active & div_flush) | - (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r) + (io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r) io.dec_div_cancel := nonblock_div_cancel.asBool val i0_div_decode_d = i0_legal_decode_d & i0_dp.div @@ -765,11 +765,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ // scheduling logic for primary alu's - val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1) - val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1) + val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1) + val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1) - val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2) - val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2) + val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2) + val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2) // order the producers as follows: , i0_x, i0_r, i0_wb i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index 21fa4b30..11ebd30f 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -103,6 +103,7 @@ class el2_dest_pkt_t extends Bundle { val i0store = UInt(1.W) val i0div = UInt(1.W) val i0v = UInt(1.W) + val i0valid = UInt(1.W) val csrwen = UInt(1.W) val csrwonly = UInt(1.W) val csrwaddr = UInt(12.W) diff --git a/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class b/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class index 06e4b5ea66b5fb2257a7508e2bf4df8b44197f09..e33fbca354dea4d4e262856aa9245643c71f43b6 100644 GIT binary patch literal 548210 zcmcG133yz|Rqnmr>b)de@*>HWJtJH8SQ*(;ciYzHv8E;4vTRu%OY$Pya=Rt9$cFXXWkAn+0(0Rn{N{in`d>Ry#K zhVZ^`#ya=hI;W~m{dMZpsoVE{{2RacLBlW(Z~J}I*glh=ZqFA}S^TB{%QN}xbfp+E zOw-skeXFpXFQ(fIrAmIOlqZ^*2_d-eKlXquzqbf5zpNp*;*yXpX{4SS2r1Fos{DR7V+U3WrnMVU0IpOl{87cXvUH*_-e%R#~ zRK7KX$quow(*AL`e5=a8;_`Pc(SDG$s(>NOIn^x&WuRZnHk9;#q&jk z%P**W_IwhEmgi$V?D-g=?8%tVo=@^E&&PcBe3EZ@KIXIMWBu&mn9rV%^{e~?Zaarm zew)iLsC@R6te-s`>t|2N`c*!AO3Al8C6{MUDfyPCY?OdtPuWkvvOFc1KjF5gl|3c% zPrLjfmCv4)^{agLtdeheR@TFwRq|EO8gV^qQuVA6*Rv*V&nnw*c~;qe_N=Ub#%*V- z%D?6Ehg5#i-k)6(H)a0Nv^e5Or68ZgmBSx+_4p zx&lPq6`mj?X z*pPu~c}UqFtGv{2c}UqFm2Y`S*&fRi%JPvT>Uzj-+e69;ZFxun ziWPgZ!*D%hx9TCIu7~WlJ)~@p<-au}4(4dU%Atm4Pki=I#WX$!D8P!9g(T*M~=9L|YxgIj3 zddQgTAv3mzl=WI3lIkreo;GHANaEWbQkJ(oq-?(u^TsR>2}5L54;gbkWXAT8Qjg^! zrGCY;#Vij=dRkS!>mf6$hm5%%GE=b1OZ}FIl=_v}Hs*TBjOrm{u7}L19x~>7$c*YC zW3GqHs2(!rddQ6JAqglk%R@^0C^2&Ex;u^qm4DOa+cC22*Nn@zV&qoZB*tz@{s1)(yT4M{$$7VJYQ)1p&h4oAOtNb;WKcw>SyL{E7#}tpAu|2vpgyqp? z1xm~tvpl*qkjl3_I`P#QIc9lu;@ciw>bE?))UU+Iu?8n5%BV4NtjXo8F>;Jo016#4 z>Ix8ZSAdMY0?2x;6@bbQDJw?IS^AlY#gWxR@GIn`Wj<oK$vxRUnb6{uJ?ZUHr_T-vt zYa`Xw!RD$!RX9{zTe_YIMz++UzAaUwjmhMNGXWFVnZV|r*>n3Vmk(Y~mkZCvlg-z< znwx7IyJvFS;<4(B>Dmwip-Yv)>g(y)w(5L38JFp^iT!3m+HuqM-kaxAZC#tLb<8e~ z4$sxxKs~(y)KgP+b6<0^_FR80s$VHJbwYmIVOKux${*j_b?|COVIb8K?H}kr5~;7N zuH9o+T@RW47^jg^c2WKO5S5mhp zM_R57Wcs_g{ky3BhtdAfllzwkHwD90&sHDY+t@r{MzZn6z}56j-~Osf+s>{^;X&_# zgVoUcLRW8d74SfM8@gxuZfvcOKt51o$#=$UtFHIl?d!QeH`3U-FnH+xsnYdizVE6S zJhU@?^V*&Z$qN_y_lK(X#d5i(Kzp+3O1YtHVKP3mTADa|bKg!!Immf^89%@YA9P2r}HoOb%+qu)}cP`Rdx$|Iob)+dZpRKvR zDz0};4LvwJH*%w6WnlOH{nXz&x4ju{d+Wqt`$Wg;Kx%lf8s)b?TKU=hnfp(W{vCGt zY`l2`{b3XWzm%3kHeYGP$Fe=C%7i@bh zgpzXn$NHZ=b$;^5t@GQruC-lHt_<$Ee~Q|>->$zi-W;Uy9G$sbzH)52uU}j)Po{6? zF%Gqt>~W|M9I0*Vgx%-wJP0<_Os40@dWPppsCR5cz}|%KBS$TK-g_bwpP##Q-(T;g z8q}L|>&*lS2mM9V+j)B~JX2rV(KS27<9f~R$MsO7>_;KhwkEEor|;~(e{|E0Lq|?6i;Gr8mg}zi<{rt6#g~{zap2yvKYh{1y+MYOg=7HbS2OE2*aKF{QpBy%8hPF4Yw(V@ZIaVX)<{PO0`#RnE z8Ke2Rz2;oU?ZNQj)#0m+H-`wxxZ~y>;O*pHd#2G z-;#0WQF{7pO%vaL(!M`gp9$LYEVZ1wRGX}AibW!wO|f!wPfe(Lh5Y0~WFVGl-rak9 zVt;coIoV$hZA)&izJ4T6^Ss=A4CVG6=+E@u4elD6D>ZiB9ojye$>ok!-HzujR5$Io zdGgHtaCv9%%>vq=%)0G=%x-_YY7KrMe|8Eu%^i1f+TDD4exl=c?zt_Ia>L`e!KnkfhWkXTc}api0r ze;Y%ISZAX<-eDTgy{8Y|=$MbS{)JZ;QKAXxDQ}yQ&@kkNJJ{(9X_z;IyIU zMtZsrb`DI%Y&#wbUX*rRnYeU+w)%Q+6qqi2@OCERi+9ev^R zlWAH%B`#xGr5_=uAB)+Mmag{4x@P+7s9n{ro}@dz)gv_jnz3#=^RJfXS8<{T?Q9vO z`N#5`T=}P@{LI{$`=<_FJv=q>U~dHD^0+-N3!#D>m%)*(Yr~U0sXpK{FjZ^IcLkHu zk1n4bX**qWqoYLi=iU12CPvyIm#*ANwX787IiY&^MV$5VG{ofMO)n~Q|MvogLzdm5iuj$-#=?0pw z-2ZyF{ZF+vjag%$$S>lo6k<@bE{^I3BJJPa!$x&{fxu+$N z*oSzgv3q-{_Nh>?zrPaOdp2WE?Smf#j^GCeX#JTyy3#jFcG+*Y`%sW^2tT(M{tkYS zaX8}Qgx4?3Q}|u@3E;ZsD%Za_Zri6RAlENi56(0-pqEn1r&Z9dnjyKtMD~DSK&rNnL!>$wdeT2k67z-^Sy(aVChckez+a;VzfV*OkVF_j6G3>xVtBGX@7HO z@ml{%=!o3!$a2>Dmq9rhmzsOJ0*Tt;IrJBJc`h>0-(QLhw8S=rf>pQbsv81e)Xuq;JnZ*jaz>dTJK& zPNvpbf3beab%o+s%RihEtH2BTd9llh!%P{6oT9imyW?(YbHh_JAv(Jdh_>BB)TVvO=eU~crvK`yD+3VH4 zC%7F)=Xdqo%mb&@JEXt6fX4@{IKMvNwxgHY0i3oLu-~%dF?T({I#<1e*RMT$LN3lS z&U$e7{4P0fD2@+rxBYQvJR{@2nx+G^?hmA95WjV;^zArI{i$~QQ|rW=6yMDwF0HxB z?U~~CTv$9|%JzueorqsW=lr$wO5d5bJRcH#`h-^s=&Yr?tDql>0@BM;G(kTk1=Vy*G0Y_Ff*y4D4!dY@8@HcZZMB`Y<{0 z*p}MXdo#_w!M$?-+`W9ZZn(4hM#tji(fg;!o+oU3X5+PcVV~TYw!wqfQ16aok&#Kl zPpi6)Zh_yUI3Yh)(_+Pmaz2NLAEqbX(l9UM@z#6FdMpTs;%ahb;K7q~SZBlIu6(oH zkJhxDE@54v`e$AIZkKYC7$~#*`Es2!JWsq)~1ou}IyJLjo=bH4TsU+*fPOx*{LI_9(Cmet}7 z*^ddk9M-=EYTx>D$@~!Fy*=tW&Fj(Pz@?@u^Mv!!Ho|w0AK$rfTNl=O#K$ctm%2sm zve#Rz3v%5MSC6drg_{Q3cOJuf-#Ve(kI!M>Q@YZLJdmgjUQbV5KK1POL+3~z#oI^9 z!J*vcgA+$nefvelj;}|WY6E+dv@gTH33033$6?=n$c)dQ4PURHqxH{w&XHL zlKD%u7i#N}PdeW=(HabfYijl#Xg-mi&p)^23UDHE*=`1J=Y~+;Oy4Yon={y_HV3OS zYvP6(T7=)-XI9LsYxK7U_sj8? zdb9u7G~I8;JQ{kiljfsb$J%Kf+a}ks&9sgc8#|}wMy!2UxVskfINw)OwIy@HiWjb= z<_AWaus=38!>;?wlZ`hAQ*xa}yB4YZ^4ytck5*q#R_4&I9LpgNv*dQv26iF-k#TZe zTV&JjBR7Y__gL=Kv!@R3=w7)1zrW9n(tfV%JmmrVTd+S#2OeWNtaFxJAikKJNS6Ar zUK}z*GXqEO-)-MP_HL{{h&)>2Y}FLkn)u^tZ8CNr1PGqxWpQNC_+U=4mK zwg5l0kMnp719kV09-QdBnL7l#V_XNr#mK%4>zDhf@P#DZFP|A6Y)60gR*TDo!+ET0 z^ONw;lwS%5!Vj?CFAfe=BGd8aX=>;G3fA$S*}3g4Ys1JZWJ0wm(lZo>A5!?ibJTvB zXIZ6v!P(LKvzX7#!E=kgJW?;>Xz-yhmSRw1F5NN54JSS@2(A0TkQ?* zlJ(r448$);T=ci?$?OSZU8$a490-M~(~Yf}Ohm3Ll;5-L5y7~hLMk?}1>+%hbl)WX znE~LVt_u5@g(`R$eSJ7-5Y4$H#5llFS(ysxHAe|R&_7TjW#trb3Mg*$Lr?ioX-ztLK7z9K-XU+ z%`RnKZVt8%QU36DZu|X9=dPQA){*v|-Lrk$D;RgeA?NojznKr>JOue(!pVNl{}Eo} z(w~Z^H1d>NxZi~TkSuqq=4#K18$Y9eCpjO$>x^68Jf-EM9q~%x_|_}PPf(n`pY3-4 z(jhaU_s<~W~_t{=IcobNk>dQPsx2lB5Xxz~I{>mb(K z;690?8N_?wR}uffp$RiecshSA*^Imw;cWTrs4xld6whoLGV5qQS$PF}UssR*C6QNL zgB zon@DD+_^9PiF;kO#nN|5=69gKnf2S(XjcUFZ^638ao?eg_Zsu52IF-1`~>@Dp&t0LB%Mpl@w~ls4spprva3H1lX*e0NO7+JT!GJ1ux?gk zKY?{(@ZzwTIR-)Kd$4?Qg%@ zb9Z7C{3gn;2^q)dw>MqcgmWU=N1#8L@7Pyd?Rj>x#>%&c7fn0g$MIa%mgZBiqjHWz z`&rAs)T5r+Qd8IT#POz1#0j*ImGLk9Oy=N@)ZOzB(wAvpOL?Dj6TP?kc3^)w0Y5{2 z-_GM;UPI6JL)SZTE&zWn@kr~r%y%_N{7@XeyK|*)%EqI0ea6D0)vrA87?3#Xt%pAY ze#HgvHTqK}{rFwrg!5)*ROUU3kUI-pmv&+tc>XO~=T-K6w68G^G@rW`3UTa*cl0c0 z&xl3xE0f1t4j})+=RZT{RvHIfuh{$YvuC!hjZB)`w0x}VvR;Z~kbf&T^>DrJwdF^U z-?Hx8enaYoyo}S}N4TC2E5+@Zkc=;!{pQItB4_(oxnGQLg@2*>9Hjm0?Lov- zH8;#n=)bdH9Bx7!pCo%a`_Pr(5$|;-G(`SvD)%7Rb?%&*AiPvhb}SB_32bR5{}ir5 zoSr(uxT1Y{(;(K(8pMyQSchqToNAvqjCoA);<4qiQOv&^$y;c@jML=#p^W!LZps@k zqWv+7Z?}&$9lJ^M2m554V~BNeCF@(1`jog5_M`Z3FYuUTdBlPHs2x^3f%%7ZU@!K= z=2mL26_;>4i+mi-XTM)Uex-K6=f{S3(fXZ}=b>Cb&QHUO8F}u?c|)`t^C#jzXFWDG zvA<=t4RP<;l&J48H~G&U<@x9Q6JL7K_G5ksd7gT$z6R$dGOsu(@y_SGhlXjL zTti-OKi1i8{`L=saUQp$Gw@`$?|hi{n-gio=NIZQ-flbM_b;DsN>AlyZ9g@!@qNS{ z7{~d((YDJqlZoJ_-oR9Dsv%n1b#lBvb0WE|w!3j|&kn@V$P@4GojNI>H#l*4(^$ND zYN8AAFZRRNy2{&P-4jn_f|Wt!hYkjV(S=>1mdwDu^3e7ZSE{e#`GWoni^=mRdLz?2 z3bV}(HKASmwg&o79NRQjmoqQ*E<(@NX2kzkAFdp1>TV9!W=`*`-Wf%>>H(D?K=}s2Aa~A|LsU;LK$lv5`zb^Pr^9~{C*Pi zcu4Z)KIy8Npu8Q=18Y4dzqPwd&Re-2yVq9yM0sx5ElvC4+Gx}M=EV!+{lU;vp65eu z4vx;$=lU`KkWZoYjplV3cAt1~_VS_Ya@}^X;dh=O+)TnAIENdoPC4;TtDX-$OFuwy z9rBaO%Gt2o=PqJAkbg)`&26{V1B$!kHLnM`7YHtI$8CuB%6wnOClvqjwPg>PFO+_P z;}iED8*+x$v?pUFap+Nwm;&uWMk*~ z$&R)Be&k^qX#JDd%V&`X5?NF5`BfUvCk(*f$Z?eQEvofl-nsP+VBhD|ch6VfJ#T$a zH3#>}`fgu4dOzG@h6yLM-rii4^Q32a>?r(B){LVa4HiE$rJl=8i3{Fqig&60JN5IE zM{h2Mxxd$No>6K*eHnk8f_gJC?!Sy<*&m|*7^%;Kd!HQq1-Tc_hAnn_7 zXNFgi-z59+`EA$?pnj~IvVPfq;2h5dY`t8*+A(*wr|B}z_bHFBK4)+{6T0V#e-MAI zwo`sQ-nKU1aCmmIrVaT8+OJ=b`vj~jw2uzd(>%bwU~aZT^GWW9%h!8W==z|HlY?ue zUA=T3OSqhxgg@lC??Nrkwb>rPWv%qj>05~ZYiT`}`+0lam(TOq>pspUC0+~3P1lah z6&{?0-|NSQrr#f+AaFXUTT_Ya2*0n6pO*l^vIhl9j=Uw=m!-{9*esVwdQIuzs@yy)l zeLUA?%i<_OkO0R(vzN zc*%MWr;g*Bvr}yc-24O8^JJuBw-cw!cDLbNnDV*u91wnp;xNda_U|`ke2w*FleD|@ z+#Tf?Yb`w9p4>st%^X4ei#+VEp4(Z>-;t)n^JBYD43=rWokSc@_C%fw=g7A%i~_$C z=9YExH@1?Ud0db;JC_<>t=`!icr3HEp#=YiIB4+DwZnx%0MA$W>$#GiI~Q)W<^!Ii z+R=IY{2t`{cO0HWUQ|ApRlxkg^L)#FN5x>d@d)w<&3ZoUp?@xDOG9&*&bxwF@O(rG z&mB>F%4d=9K^#GG-~LTk<+)-#?@JN4&^a{x2#p)|x%Kd0=^W?5u>T#te5h#$;#4`$ z?vCMHc%-^f&a<`~N8k^)Rv}KLyjpnSN-D64=1sO^#@atG_to(J8S@`@Lw>o=$uDz$ z;wi#2=If;yj04WSDBnl<1AD(h>oM*BpUTzG@9L#E+}`KZn<3d1F33`4A^NpXE!Z=O& z_G^6Z7;e_{k>@45(sM7$zLoZur)VFj;2Zla_Z)%p;5b)Cy$PHv9a*LP4*Y8jaJh-Rv<9GA}*GzXhyKWRVG&@B6Lb`Jgz>ly4W&&lL^hWRJ? zw4O?jn#}VLZLh-mh36cB(~eA>{FQuu;%tB09L_Cqjkv+o z@wYVOBp&H`gY;}}dj)YO;Zx@E=sAP~9{v>N@nn9ug7IEF+k^RqYuL3}$IpiwDGsM| z2Rc8Poy7d0>rBYpBKfD(`~c@|?ffa7LkB}=X#P~DpYuPbY3F61oWnk;IcRdZ{Kn-1 z0~l}lyo8dkkozC|`3dA}5Vx5|%Knl4$+d-IVY*NmD9ZN#70BsehkBOG~a)F0~{h#(vY-cRP1C z*Ivw(=I~~PyX8Ci_H+5lt@6z2Txq75Uv3#Lm+!1BM2rJaw{g*k@dDEbb9oqBc^N~? z(%tFeom(?YFy%qhh&h*NxVPBM>}(!|I!q(7bXQ)i(?suZSYAe;%yH6#)fB> z@-z9_mdw&pc{Q`VT&CeWY8pbl8!@`@wg{z&X}o~%PnV1Iz6Suey)Zw&Qprsf^X;QB zPQGQRG+kU-F5JbtCh-1;$Dgl!#CQtrbA(JIP$&Z!!}f^wuaJGAskWHU-AQH($?S3^ zS1e`=B>=%GMz~Z8btr{`g^nfDs2?s+!)EgG%@<4gx$MH7N|t1TGuaBv;<;a0$}PAB z)~G-j|H?{(OY#!`^5sl+#xFjTU#_U)C;%z^8^*sZwK_$Yg$`U#;|(01+NWvqJMuLs zw6vVeG8a-i}k2x1Bl|r%o zQm$B-Ip%3#v7AG*p^|NQy!SYC#AF>ynBEvHqA^dhOY|0z?A=@uZzgfnqE5FCIdUXl zM=~?HN=_Bpf*CkfEKlFb$~sqBz3k3XZWR{fir|^ZlnaFxm*$TP2VZ6VBl*O%F7j+K8z{Mh=pYZUUA4T6c+MXvhF5a$cA#8 zF%)(3vN!`ka1}H@Tb3*3r95|bLoSADQ>D0)U0up9!z) z6vxz|;c@2;xqR5ZdKPo`R(7_47sg~UTk3pPkeH1Ymshd{%to?_t4`jFa|`D2DjL&> zl1cC;7z{cgeBn0U6cZt0DGz(rl8vN^tykB;AT$V4f`>@j^frJ%L!7WA-O-y`%9dwm z0W4S&H>a1EU?AWwTP_vv$!P}eZNeP21hA(rk(xDnO^zHWx>|CssQT3@&*d7A4h^bA zh~whvnlX+ru?p2~YEwv^)sn}W4y@RaN~LD z$)sgi>l$0lssrkU?Bg6TBs*H|USiz>Fr67bK(hz9BGXMREsz5!phsk?Qn`Zh%VXVv zLK;3?Rd_gUt~5B@hE<4KG!7)45sO^A$?V6{m(k0gEIJ87wnXn8qw5 zGbz_4pol88@8gmblK-DhDfD58IUX)s$<0~Uj+a~K^<7I>@DCTXp zlAnhweZqRVlXkHmD$V5A@-t)kMGW)wqm?{n6&qh!DCX0?CBVUsbV=STUSO)$T9O!r z8jlv#9$L-K%wSaG#Tm;l!%4aq7{n+~yd2CLbG(I(&g@Ew#@~%M+6JFk0iGX%r z0Sd^ZLa9y$8}6z@Yr&?4r9v4_*LK&yxZ;Mg1(Z;)rSq370sAz|l-6R5p65#Uq%xR< z{JdOKc*2qgAWKy*-zv-^OyeaT`t4;+7O;Ia`9*G;;vvaZ@gk0PkS_AJyliv)36`_k zI~;1Rv-A@Z@@p&3HL1k4>)^LC!@n4A=Ef9Cv&F*PEjgOCKGy0K=7E<7AK+zV^Ru%6 zDJ?PB3C+#rm$LJ@%JeN-C$6p;LB~!YR zDib9iw{$wjk&A^DO7ie=k(BG{*B7Zikr~fq&z(G%9UdAv>GQ0I;qb1guJ-V;VRvJD ze(E;5*!y4OP_!Q%&&_2omuaQLi(QOOOLwguDndxSsE{^n-Yu_n8=@#{ZId5X*1Ckv(zpneo#w6mbSmqi|;I zbQY_Pc@@6TW{wSAg)yUa$z-B`ykAvrU$Jt!Qk7Rz>HhJ|VD{Ac;S=bBbIsbe(ly;m zWrs#ioV+3%VHJ~%r0jzfv#zNk_d4afpUQggr+xR+@_v-6&l@e>v%^rJS08VmFtAxQQLQNB-1~95-rql(MAmyt<-SQP7N0=)o{^P4HvD| zaM4~*AI@dQ&id_1Jik4O=eH;E{PrZC-=4(t+mm>HdlC=rt2r?+a4y@Q89AHn9~vKn z%Vmb7H!(dielmM`=mgC$=EyOyIIQ60z<^yOA%%Eo05N%WN|j(8JV&@r)-iIC8-hl# zj?t5YL+3~ACXHoIj5@TO%B)DX!)ko>iF283|HV_bLx}VBSat{#R@fJWc&bB|9m`@$ z!>ygljE!UBj-MPIz4**{cJ$@w1=$D zy6GJ>i^+PakHX>%k7UQ-X6;7GQA9&wsZCZ1VxfC9t`_I~$S`_qi;NA7oX8Ht{%!$w zXm(4+#xvvaRNQr2iafE^bK7jhayxDh9C67I_Mo6C&twM9N`@Ev=#tH#9-?~t($yMc zrko$>4hq^$zVoP}~(T0uFhVq37VgLqlgLOjzF@$sQk7lCgJ&-R6dXZup( zxprs-c=q{mKac#5pGSVj&r54~rS`Rz$OzdeaZ?HfLyIguSd zpS?JCGW*Q%#WA!cGCX!M1uus{0F;Xx`@+JFeJOEMLsx{+k$%#MEs2-mczI%vAt2&~ zLSBt4p0{@7e3tP}f60NO70(O}WK#nZ1H-teri=azT1(*_;xc(HwaHs>#o5c}M^C_O zNI83I$a3r+WV!M4W~1jp|!IxI>Ru31!tDXd(Q~-qvrca+pn3%PM-;Ead%+};hFmBfphpTr`ukXy>l=W#enR#}!~cTE{#9&=&-j`_RP z%HML$O|^YGNOZg!vis58~#h&Cg;H&6k$(PWR08 zbbficfb%}nII8ORiEgO%bLJn$VU*7UrbykH#-OT*JF4{jKco4N%s(dU{0YJa*z#6+ zW*|3xE03A5$3IT%0FOx%VHp(P@$mY|2l^}z(FT|0ZEwWV(AabL|rschlNZ9G;T#Lu!7Xc0>d5wT-yR5H3EQ@ zM*!Eh07#7h5abcSwJiWrBLLWV1aNH&fYb;8Bpv}=+X5gp0)T`^0N1tvNR0q6;1R&J zEdWv@fWh_%;Mx`dsS&`)dIWH73up(Oa;>TWU0VV~uCF2G8)>?>1+*ib@{KfI+XC8= zPWeWfu5AJBNTH9wIdYfJh86QYlLh2SfunxK<6G zcELoXMjptB69$m-#!+%KfI|(B0vAMSEr`-UgG3_~*oV9eSeyblvGyo(0YoC2mH-eQ z0T(N2EmqP%fk(gv2;I`u-~&k71qhKE0UtopE<_zRPoze`H};3!u_to9z!Bfr)3r7BL}~9!)2RiV2trRZ@D86A7Zy}r(;SRFJpg4lXNsbIwC24&JuX^~Xwh;6kf^b};zE|x zL<88cdu-z(h>B|(<3rF97ePd>7dYxe5M5gcB2ps&n5f;Iox6pH8=`@adRuzb1s0JS zJwT7rT~ZSbeB7tR1=~?A*pB+ZM%Q-hwO~8y0~=l20$Q*g1#<9AgIufliKJ-Y)4o=s zh^+&prmMh>-PM_?{4~Ds77cvPr^JQXQ7z1l0yMS~I=hxe|6`vL7h_ah(-MHjUO4ed zIXcqDi8fmE7d}NU&W>tvcGQP6y0&eg#aX8hXLM}|5V^jooj{EWeY&;hT7Yz7 z#61Eo80eO!28^snz#a5X?Vxx12A!_$PHP9f%QxtBZ3z&$zDZraL8oh5Ks)GNzCovJ zTR=PLT^LTa({ybMXh*usH_~)%3us5W%Qw<=Z3}2ey304xbZrZ0N4m>5(sXSLXh*us zH_~)%3us5W%Qw<=Z3}2ey4yF>bZrR`xqhU(eIrfRwt#k|yL}@~*S3Imq`NVk_3QI- zv^vj6gFYBgVOyIP2HhBIjW){eEk%Pq`%+8yDi2dBAJdKE2ce$1LK3!0EzY`OhaC@TC51D=Gd_hb4oOsl5+4q` zT^tg*Rg+)?+TzwjW0dj?j$+wVatg@~6o}b*Hqbg90AM|>`QFsNd?qy-yzEzq(vCvV zI)wnJw-I1CGN5%bfZ;YxBl4waFzZ)`vW_~?I(5LIw+Uc4GN5%bfTC9h3`YjEP6k-> z%7Ed>fY!+XOkNo<92w9$8Q{e$1BN35S|ammrCOjP{hSOR- zVCcE*2I{yxf8azNey)WdWZ)+&(IB?xUX2QzNL1GaAVwlu(I``YQ1?B4bqdmwdZZ-* zCVTgWb|Mo+MC)XLun;|Xx)2S%(O;#4#H1dHNk0;a;S7i# ziIgk$n4B244AGiqQs&qzqaclL>STZ+uZ#jP$}H<-`~ahbvePy_z$icLtw(_n-PF|s zD0pQQoKTKfCxcP<$|#VajId6|4++ZtI{nc@g7Up`r%0ZHei8&UV*Bo`T7d?Y*Hw+t zmkvjLa2~2~8tzr4Aciu>8da1Z_Q(*!?gi008Gu3_bID%J(9bZaBfsv~q~M6M$~sMe zilb?DNovAO$FaG$O$xdw-K^6D06CVGzx|2^f7h=@0UTwWb!vbq$D?82$G@wgUztsj zNBfLlqXI`tL+dmW;_StNe=&fA#q8{CH28;pZ3<8+7p>CI6*VjIrjs$T6?zNnP zW6D(YYP#=C(W*`U$`yc-gr;)JfXif;q9{8(7p>ar(?tdCMiH&kgmmo#nw>1@Iz@h1Qc~Wri5`}eL>Glw{JI@K$E19Dv})X6vjS8quB(}Vs%8%; zt?tyU2PGxU<+N9SnHa6Q?$@M1l|*#4`=Lr%cBghdR4JJ*j|to#&qb^7Jf5c)RLIst zw5D!Kw|iw29MVml3?Q||#x{qqGAN2x;isZrWeN}}Ij>U&P|069s=v^r$G@r;{mK+5 zQnp^F48W?Jna^csrl;qvUldDScm28)G*V7qrwf3qqa>I7^&LljQkQ>MPkDXE%6gPi zCf{oq1(S4BSHB;Vl-+mg(PNVG`Mg)2>fm4QBdD)>nZI%ck|d$4+z&}Q18^$WLy}Vc zo=y_OmLXbG4<-J+G79|YrcMSxlCcZ@3f4LzlX(Gj^>u!A3IOTMK&K8+@-{)i866ww zWC$`e1E>l3OGyc93jDBNn}RetQ_yJxXuK^@5JkrdIvGEr=rqAGwjNP*ejuO8qEU37tAW=IAuS>5?9E^3Z_>g3kA_Xj@|e zB)rGh04ixKBU;k{I-79TS19CXyb;R%Proh&q$H%%1+aO>l+H1n`t?Yp!wFtdthZv! z;-|;ast@}$DflE2UF`sxef}#?vnzNoopj*|d2g!}bkb>tP8R?uQ3H#3e~k`(zvJB`sx=Uf+OJ2cd};9p5kfq3uuo+FTH_*t$cKR0nV-0VU&Eyh;u)m;ju= z;Me3rQ;O)?1)O>N;({>Mp#@>81925;$#7(}fJ$`$Gxh^-@=XHKs{io!(1n;RuCWRoG`L#uLV;)~;M1a< zOQiJY5-B=yaGorgm+uUUhJ2fSS;+2_{)i$)hYy}HB8DRaTGsv(pBcn$Kof^pZe#ra`PFF*Is89(woUXW2`M@j@YF*L zM+UT}KXd@#l~I7AKOIO>w%;qG07ZWkkfMCPS4IJfKG~n5ti4x8!G%7hpQ5z9S4P2s zK4+hz6unnQ!2#XW+0Bmw%F{cx2Cb9vGS$2%F}y$pdd(}#7|M4UjD=dQMUCGrnPA3fnSjVD}81^MHzbeJ333td^GeDzZL~( z`h%*!0CZTY4}=-cdgd)+YqCnSNW<}Quir+>OMu8dYRFL z1>ILxMMJOkt5P6HGMb)HdfwA}V%R;==k8OKs`tt$fTNqbdi?H*^7T$Vpmj2Sa8bVA zkpZof0c^Z&Q*cCie4PwH;+0WQqtDZ)?z8rdu0^-&`n(r{rI6Yy3<2Fe&loPDi)NK zdWvXWJ$|o433I0&z1N{!xwk(Ge(0vA9+^B>+omMSQ~E@C%AY8g47+XmM0tu*-k!D* z!;t~4Ya52$E2H2*pY~2s2HPv6;6R_=PEpp{E2H3mZtB|R#{s3To&M-?Kv`=}NjvZ2 zOGZO~)T|1TQ!9iJTSve&@urAOG|DvIP@K>%Nh9oqV`*YhVCATeU zoebQC{gV<@jQ1EuL;vclno`_$AN1+&6s4^_14Rr+Mh_xNTPMi9aG%$rVbiZfL6ttq zouX{Dw_*iV`c!s`vejN01y%Y~c8W6BUKs^dbW>+rU<5DC#JevkVsKvB7!CWLA4pN^ z+A)?MSd@<%I1-H|6S-cXCF<>ujoEM4wDfQSR8)m-6ac*FFV5`bXZ=lxUXEwb2&AZJ*qz z%tXV-ygio1tr3*;dMl+V+pJniG8`G))XBgS+x5@>N5d!l`ds9tDH*NP2cWsVa;#+c z3h!9+w$R08TAz1L`}59{;q(d^)wRNh%QWSh9U0I%89+}SgOfF^vm$!oa5OybZ?p^8 zG-a!G%6x!GQ-<1U0BD_z&vB(GL+!|b*2w^8UW2;8OH;O5BSZOQd5l0EwchuRUeb$< zl^`muq@X3O)8q#nrI_s&>(k9?f4W&R92tNrGJj{3zEuHS;`LGX*GDq+@Q&o;6+cm{ zNQ-GC4>(0e^NTA5ycfwWsTCLDQn;KjqTvO+Z>n;uunfQsBhev0M?wh?>(G(kG+woo zU%+D!j~y6t>XF~ca8+9$JTYNE6R%VVkpLRjc0hf>ZSTh7BD@y9moUQNXVHIp4e&q) z58P~aUY{l3(@yUJzUpKB_r3|(su``{Vl?!rvW!CCTA8 z2b=Rnc$UhPd_&W%-104a>c_=_etZH8(`b%g5LG?tZQ_Q*EW)n|zm^*DIvkbzb>VeS z#TlSh%Wo0kA7IfpD9w;hS91sIY%zxikso3aJcQtMnSQs;5W zzR`Qj`l9Id&#g=jgrRwSE=^exA+rb|_!EJ4Mf|=h4Hk{b`c8!$jG4vGR9g z!@hKPi9VEMweax+L+d6fzfn%2K84wL{CSGFA5zeMIsub~-X6*?`D9YQX#Px>OS6T!l_h#6Gds6x8h70O@Rv{=eabT7@HC^g(YIw-%L)a(>8F*Jjdl9rDMT#3%w2TQ$9c0oNX4!2j=k z6yZ;YKSLJ(1GLStjbckVt>|3|_@E6Qqk=VNXwn1QE)x*^JkQww;}qvb*ECMM1GW(w zH1~XKlxe*9ze$xlt2MPcHqhLox9bOJ285~aWQNExecFdUabg*SyNwaO_>d9RsNJYa zpAkg(FT-D;;rc5%4c#HgQaX{mt20vIU|hb)G`py5ZiJ?%laVa7*we*V^p z@IQzDg?jom{N%{586OeM;R{qP*ii)!P#m`7p(W6Y&E8f}T=w{TNP*vsuWKoPi$a)<<_=QVh}FgVdWBcnPFB`r8vD`J7V_2fH;dg1-X5E6 zkuPAkzv_`~$uA;&IpFz{M{nyT)41m4{Wr$+q`g_&v~laBAKWU6zb^@MClBOaVKy``IvXI_^u zpI}~(Fb^>Am@r$JIxfr?F!i)BpJb|Em~Bj*5avOqP6_i6Q>TU5&ic*>vxBK&VJ4Xx z5oU_ZJtNFCQ=`H>%+$Crk1z#G9A)Z?Fguw-&%2nqF3fJGZV0o7shh&=d5kH% z$M`9xW`%j2sawMAW9qgrpJu8k%nVZ{VfHh%Aj|>Qyd=yMOjU$=lBv7GJjK+SFbA1> zR+y)mx-ak<7dasx2=fe6FB0Zird}+}VWz%AnCF;!nJ`C~dWA60Gxc4x6lcsqYu&C8pjW%*#x@QJ7bl`e9*Cu;w=je62;c^v8sG zjj1;a^Ey*+5#}UQZx!YZrhZzOS*Ctgm^Ybvo4~ePYI(cBCR|eQ5au*f?-J$=Q|}RG zo~icTUb3rw96<~x`g7Unyd8WHBZn0iK-?`CRLnD1d~ z9Ixi4r9!^_++D-uCztqhOuSZXSZMe>7n19tPSdFK@g^>~?;%yX-*mE9sH?P??cJa_ zeIkGhKlYGPZV7EC==)F4+f%#HhCQW1{+_nz8ij(+2d22~8y0gr@Z>|Z`9DXsu~PZ5 z68cKjBNel|{IDiUZS+m6N6-jeETHR#^>MhA{Lmg3(+$2=%=!Kvm(*cSEony%&sWY49dwRM)yLx^ zvpCPwNcn9)Zlun2+DesA{yl%+?Jogx$qm{nr>6W&9v9U`idG9`QJyM~U|2Rc7N=N%;UKtJ3;K|93GT zz32wPr}`yG${K7CeEN%S5PbTJZV-I>i*68n`ipK5eEN%Suz6C8KJVsfec=r@PwNYB zuz6Zv*s`zIc_~=nHgB+bTCaJ7&C~kA8*HA|7v5m=q!y*#W|!I6 zrP-xu$&?F(&hJwpa{K(rRxYQD^L*u$2v)ZQP-*J}udGtHHpxQncVD@n&h4)I94r^r zS-TJp=6y80vC0%h4mL8!WX?7&n=ELKr!wT7@yi)RV%PW(u#4+yx%cC^L0J7z<3D62>A^r-iY^)EQwcGc_!X3R5Fq@XDtKg|TAXr6ykx#wr&Z6UG`- z7lm<;?_L(hvrJ70d2K!gvu=d0~7zQ**+2F;fL$ zyo9Mc!uSrR=7sT6rpm&28B>eGcsWzc!gvK!E5i6rrdEaVT}<5*#&A=6~^~7 z^?kzl0oM0gVZ4EPuNTG-GW7$(cq3CkD2yLs>WAp58W)=U45ToA*!U3|k2eY9O|0+7 zgz=+Hy;&GP#?)Jc@#C!Jt-^RSQ$Hy-yfF%M$Mw#?LYJi^6yt-~E6vex7+B6vo?`_aR~Y0`op1jCU~aSB3FT zrhZKr?_%m>!gx1R9~Z`ZnEHe;-pkY{h4DVt@;j!{3cK(#%+uu}eK)F5F0~it=T|E9 zglzjz37<~O&y3|4;W+Y-TK1Uw1XJ4Q1{{~Jd6t%4%l|OmPvi0_VSIpF{25{V61VuX z!uTLlpA*I}Gxd34e2A$(62^y_!Yj4up)J*MfX>n{HiYpJ<5x)kp9|wxS^r-ObiZ2VwjsQ(qCrCz$#tVf+?T|00Y}GWD;* z_-&^CT^PT^)PD%$cew@M6vppKDsBqn_n8U`<5Nt9gz;&nBEtBLl#R!P@dwOH2;;NN z!;Jm zV_vf`{+y}3!uSiO_6g%Jx!e=N_yY4U8=DP=l@i$Dh3*(D?Hz|z2WhyO< zzvH_{gzJ-M8nCceBmzlx{{ykGq3F9A_>J!F4vX+c6zQWXiFuuyvNn!kxTrT5- z!uV&VhJ^7ia`}y)6~@<0!i+F=N0?Ej=7kw!sw~Vn zQ;Wh(Ftsdz9a-CoFsqqb6=n_F;GQryG4(>PH{_p8iEuGIk4Guvcms(VmW|?FmrFA+ z`P0$Ar`z~FPxu(#Y+O0M{t3}bBL0&2cf^gu@t5LxNcSV_7xqVEM2#3)4ABY+;@+-tv2n)IWO)TAM_E)xH71YLIXPp)yD19(WbP|TlSAYZ zp0{8mju(as`yR!Ik@(x`M?mFl%Tx{z@!ojYQ`Qe3B{E5`(@}4Iu((0U;I7s_fkdg^8-FbVgEw`e@PfKv35c z>6n|#V^BYUdFph@X3J6hU@ZPiaeP%|A0F9VS7LUlJP%`!mxu9rjHMhchmXZS9ESvc z>|bdM%)X->qy zMwtI>9Q$sslgAIMl^-R_rg|H`z8`BXDN=>$Bb`HzesQ2U2d|EA8H`e$h<`I-pwa}E zZ*TkY(}~uHkAfXaJ3j}+bHc_B@6wZ5!eW?NUM^45&k;VJ2*-@hLH9^ED=v24%RkLzGupF5E?8CQ+Bz5=T{AH^<+E=6crd!!5a) z+(LzZw$%G@^Q>RxHPN^!oY;YhhjY>IGn-fhz!!RQB4@RqwtvHrn zDj<*XtPDC5k3*9ijo{0U1Zz5I+|4C{k`E_Z>kKpT0z?*%wAlmf+7OOeu+!qh-5D~D z55*D(6Yb<3bEW>3LUHC4R+@+GFYz;74A6A@fKn7)OeRusD50Mx&F3)7hwTQqU0L5E ztu9@7l{k_(8aIw5@M?v}*BN1aDTjBo$}e@CFHPqoiEh*AQit9eqm4(+DzrI)@Z#U& zUne9#h4DJRIsSD7#Ln*7?oLXMOr{RS`svq3`I(jJJgwVSFWqw5{+vjhOeA^|r_>dx zP+5*7PRA2NQ!!<^*z7)f8<3!^`p?)3~6#!{A%?q@1x$Jd?P9 zWj!$pFV-?&D6K5F%q`_}h&^0)WEzJb(bPO{mU|V6@x;YAyyqpr+I2_e(p0fLeTTo| zz;Ef8$1f_2xqFYg#gHw>&;DJXL2ued*p76_-STvf;_C6-(p1>1?~ z#7sOfmB23Yz2^G}baRLp-C~T&NCIn7nEi_U9lyW8^SLAo+#+!&QH+~^oxtRlEz7Me z1GJQFaWy(SKFsQJVj-TmmRM9^N|8n+f!*6H7>X;NpN@J1I`5VA`R=M=hb)QJIPABE zcn2}hL8T$jJ8(#Ag%($GMaX$qdbo)VS9)il5ClRA!Yw4AZ^}?B@gl!6yqcwH1CI>= z?^Po)JDhid^~;5s$}NQIdlKJ)P(6XYGk!H?G%LF^XS&W7mX<2Tc1t4h^296RMswmj zO{3inne~NTv+~r9|7zm95%MNp>F*6vF%vv+-wO=TE@5GTHoE_3y>)||`SVDy zbE#jz8Bi=t6ZM@4q||1)r$~{+yV0#e2UYW4s^&cjcyvJyJHN>PdBR{hWR8n*26$a2 z;}Q4Bmi6DC_@89`U*yeT3u15jUnKAv2?~$#A_>|g(uSS>7l~hH{)g6?0efAaVbbwL zg-q;Ywu!VV?Uq zn5>v94-c>GneXn3F#nw$I^6yU0&O_`&!{_en=QTlXJd&!Nc?ZpD7sV9>*l;y-|}cW zZt@S~sQB~#`HWMtpT|}Xc>H4=HL&&n6h{rr`*R#MFb`?+DaP_&A$G9MuzD+BLT~>D zc69J3d9tg28%umK@pmHeT;c&$@Fj#pU)~&h=06p|cE~vCAM1=@;wzgY)gtlY#7juo zKSSBSP~acL%#c2)Wq$fn%Q8a8{*4BZqX>I5MXOd<`x!gf>acWR<@&e8zt!l?` z2&{0O5l(zvB;LlQVqnGVj0lzb2$!k`tESF~QjfOStyLRg$XcDTtLTxAIG?1zP;aHRiGP|5vSXNr)X{C)M915+CJ0?MD5N)fsW> z({FK;_JFmw&PY(tKN)`|U?H$Y64)Z)txXS^!}h+{8FI3+zz#`>7l_2~v*I>rIap^@ zQ(v7#$ZDZ-OP(IKL^`r>E|&b4!L?h2f1ze~<%aRQDJ zX(bu|;IGdOVh0pllkbXHYr)+u&hk5*D`qQsECq;}HVl!JXgv)VDb(wTIH%ZEcKB4G zScF~At9Es7NV{H$iDv|Ukow{9N*vTU5;Zc5D=rE1Yi#Q)c<3YgH8Si~JUpN-uFi8I z5pf;qI@mx=iW|cG4;H+MlpXV?^zpG0R$A6w&ymLfVkRy|1m*=^7r@rVU%W7YY5a99 zz1EUEOm@V}$yDq3v(<7apd^q@3Q;oOPx{O2^k7-Uh(SO8^(vSNbKf(82zwTaI1R|{e4bTs>N&Wci+Dqy`EbxnV+LnnQK{?n>mcw6P zxg#P_%jMqe11`OVk<;MfEie+ru0p&OtF!n?@lztOouz&Tw^nghC&bV3t+$ClBj3Wo zN^~}d2bAE9g?Iz4VYv|k5uiciD;hl-8omM%pb_FL5WYSf6@kZC zCmvdOHCygOBCv;fA3-{u8oZA$KMGUGZ$Jw1>)a#+dY=#<6M+L<06G7_)IA}7i|){pTRp+o|eu;~Hnd<&B84I(8 zjRhh=-zMTKn#=SVBEA9@v zD;g^L)DB;P*yhYC`St01ZYGQAhG%ooWFt@=f!pk@&dV zIQs8o?}NUrpZh#wq`Ey`-LZael>UFbT?c>@Mfcxqvbnota@osqU?>WTC9roF81C9#a{ToDVf{ZybR;!yZ`5R%$v#l-u$NQ zw0%1RJxNcV3{qTd0_}x1XHic|}&O1Z>vH#ZcwM8`6iFN}0rZeqk&wDoR|KxES_|=***j&Qh<0 z0cuO)vKXLXFYb8HM*IJGtxs)yX;M(=wG#8`I0OW<>xn+Oyb!J_vPu&R07CoL(!{mI z9?aXrVraH>cW3TQl32o~*@^4H>XknVHxhd&k9IS$M{wy@h{q;_iQB;@mdCpjY+|_t z+h=om_kAze;_@(<42+WrlGW+!xOiMzZ0o>4De)Mw$8(h%zy_BmvypBI{z2?1 z{0G?LN_#sudNl!<%!qkf;z^jCOq)C#N{-r7B(^4=CiV=D+y=!8``>WzDM@VSKR!q7 zS^UQxFcOaCr_z$di~QG@h&`A8`U(`oOjv$RC5hMgZ(t*NHb_t)ZxZ`-9_wwGpwFB# zh9utQadv{uFpu*-vCrahJ_LS1c@9Z@%p<|H=Ug5MrakBKNMM8D&`1#LD<11>Vqd_2 zgYzG&dGik!F!3pB;`>{>v}Kp3kM<=u~d9Dh6A(^BCdcFl-OP0??Yk%w>wBP`+@=>q%p0k>Wy# z8{1I~wvy-bxN(RZgSK-4_ZEY3G?!drU&oRtP7(VCE>(ldm?J8qxH`m3{7_s2jHo#x zE#9BOb}ZcK16#7BxE9+kEv`-Mo4JPlA@j79i|cZ9J!0R+e>n&`TPQQQ7ZPkkiVx;L zHvs!%p1VWA{+LVUV1LXLY)tGsIruPWQN<9MZcJNtadTqd!+(HzK{05BE174_$>?rP zb#E<(srmgpQahRt@IJ)79f`e+OGglUHJ6Sg_G4V?OzbDP)RovIJ?#EN_PwZFtFUQihiCxLIa*9VJ zqs1drRucAQV(aKgXBQt2LGYrivu1K*yuVjGCS|$BFamzSDV#*?Pq{RKL>Kb5Gl|$= z@h~u@p&S0dVJfk|U{O{~ z=bgo;6`uii;yjJBi2VoG0%KTFCMv|FtsY{Y4|e1{<~(Bm&0}6fLLcy7F9C`3zl_*> z`L8ezglEqkON!_7I9Gwh<6J|+e5qW#5T3-TVAw#47x74oLE@2?kg&rQ-2lc+{MVaE zxR8h4LV>5#woG540KeNo;=nseIL;&8O&LJ%ReUdxb00`N&I2S|%;P*n?ik#Gr*vx3DLLyGCE0!V8$NIXsj30LEB*0Hppyw>wL8$jZ5Hj;1+9%mCQ*!Zto zNVp~s+X}d`^kIIQ|MCn-9QP~<*Wq!Vqj9E>C&fE>oEJdiab6b#ykvm;=@zMKnZ@!fB6o+@!&YH_)@1jednIu{OI}x#n4InraJr=I@Kxu zsi=5&@z3yzgPJByt$b|{tIq~TRzw|1@h`={g6&W-bo8p>P|HfgAvpEcx5tw)X+gHx zyt`#!Mp67n@t?F{{({Z{_G@vwA6m>JO|t&~-g1jFl2)QBX_^?8hA zdQpo?YUZ4bFx@#Lc((U4uV#|bSn=*;0SPx{m6$9d;TBv1+pc@qWHy-qyN*OJ66U)S zNtc8V=TTB5d?c5uk#ILIRVU$IT-wj`<{hfFenAq}$i;FhM1yEOCuZoz>h{sG(DPqu_8tzh_;?~How*^KvqZ+zI3 zp6o-y6L|D~Bs`f*14wu(mj;qBpNu94!&h1y0mE+v^gW<<7_4$DcY@?*|Nr1gZ3*Qw zA~}*KG77klHh5B7c65^`q^z1H!_VE2^vpnE5BCq^#=6ljF&8@wSAV!b^BMpk}138u2cK%pr5BqFE3$+a+^T z)_%#82|1IQc_mMS(9=^^nnpa2M?4FH&Q4i1X{?KQtn(n~{FGITntQpNL*FrT#!c!@ zXMqLD3!xWA458S@Lh|BR@}lG=#9D7{fDcNNmys}EG9<5n&!l)2&WF#Wcoo9u5KnMv z0SWWPL-JY}5ZK_7TuiKFD@6Jo z*QXCj(#Zk@+^4=lYEh7U00z2aIzxiwDqtSV$n$Q zaUN+Sgs?~?xrxVtHK8+}Ezgoq@;ES=aJs`yJ;0GpCm^|JK=t^s&@Y@!lF#x;+aaiX zmx0|o_a@2bc`W!?Zxj3o^$Z{DQNwbOUItxV2MruJlq6r}v0j5U1cVG7*lTcil6->) zz6trE(Ykl;Mv`yyuy-JZnbS_7R_)21JW<$h33u*u97)m%Bk+O+p)+W3|AC;0t_UII z6DTQq00K#V#sfYF$h5grN%Bjs;w$j?Jr1(=4gVdMgr$gCYeDjRsJYX?GI`+m31E>p z<_x+_M^GOU1eaMf=U0~Ln+^xJ6fhZj6M_<6#88LuSp*Ehb^Uf_Gg)=Ch&IO(mmlY09bt<7${M;$4_# z@I}14AAC^D_Ga9gge>HM+5o7Nvi7Hdg*=72B)o)62NJTFN2?Ff4o+DIka8&dOogzn zrRx~5q;X+ay;N3-45yXimKV7V-9}17=mNH28S@NJTT&YW-}DV_aht?I!C~+zC@%_l z1wg0!P$=*M#ewk!-XprLSc7+4!=_^#jJ=-W5!%5QqFn00qc(3r+{1ZP_%e|`-Js@3 z626h=w=;a{%oFKK!h9RR?e1G4(%XUg3eoKubB`{DbqQbdyT`!OHf#Je;`RX@?$K^v zka$}CNtiGH-DBaaYM#O%66ULY_c&h)@C0X47z+Idy;qREx^jn8y~ErQ#2wD{jv`^c zMc^LKBDN3_PvjBD5cfnLaU2OR&`biWdQgq3o^ zs?dFygg@j7EhXX4xU`HUqP)ykKxwW_S@mhve93=YLlQ;&$F=a| zx|DS={qYX0sZlN{^J&sNb(=I!jDg-tV8IJyZDdWNFv3X!*=-b zxs-J%{8&(vbm!`YR-3|NX?oY5~1<8$>O@oQMhll67V!n_#% zB9SPU{(*xaIPJY8!nck}V7vEChA0V>M0M6+O2F!^1gzc~LW7C$-J_Bsl1TF(^C!Vt*c#gdjI%HKOrLSyCmXoGAY?fs~Z7*Bm9)Nn}6%`+g)+i%T`(8+=Bpq&9rr z&#CNBB7C=}q%M4o&wo7-zQ*Uj)+Z6Z&r{NXMEGt_35;Z{yO=S3>KUY@93b)4CGdg# zVh)B6G^?!U3i8SYo+K@;qF2P82Jx{X(eB;lh!{NJs zE_H$q2lfx?5glD~a%3gp%$g(wXb)NqdR5<60D!^dgZSJPf{) zr(ZByc1d3n>CMCXlgI!r9ZMpExHO1FhH(kLlK+S!hQjFqTpCUyd}&)Ul2~-23HnCE zi30rB6G()=$|-@j7xj3hje|-%DP=XLa|5_3>{L?1N0gFDB*It3C9p9|H_$-UR1%rQ z6Q2%8A#kNLN#tZ6HVY0D;qm6cc`sZ#l~}aX2JGo@oB>CiNg^{j;%pM(tEZB4NrX?E zO3o({K3OW62ge?8>_u?w0ms4$jZTk2-(@5+k88PtL@wqMj4Jd^3jBICiCn?M7LdqQ zT)GyHN8rCMCXod^YzeWx;rebMkwrZ0CKBOqC`xW2k(+tgZ6tCBm+l~uySa21iQLDf zdr0JAF5L%*Ebug7BJ(|$9)d#_xbz4d48c=-6pmZqVarLPKCgw4W?FD@JbIpE1Wo; z;%UBtH7uNpCO3oc`!Afj!6Y!4O&r1o_LQBBrot)fFxuNTW)reh6oLv; zR#TXeMLuVGQ!x_Z^98t*1t!HZwkhNR^SuF0P^m ziTuo^G>PyLJ5`HB_^Xms9rz}LHMP_MB*I^cr0NkT#1RJ(hmSC+gNeh(l@uIULbp6D zJJk@TYH{D*Ui)0a!<6K4RI<`IXFL8*&~GlYj-LY(1Tx{NrZxO4?^PT|Jm&6_0lharn@Xg6{Zt9`*on_>wyH5OMg>ka~nTd}v5LN*w+MJhhxS*K>XF z8v9{hoU7p^DK0^O{0G;!jyN~*c+emJ$-^Ee&aFJ`3F7eKBDI+~e7HzGNgO_0q@E(q zgFN0daOMriK1-ZOc-V7rA`TDRK^*?-IQ1fNR`Xw9hO=?_udfp8UoO2)9KIw=y-A$M zdAzrYvxQ6V66Yx{y+;zgc@zHtn)rt)s}+3`w(%c7Ar9|SQ=bv%1s?VVabD)qSHyXZ zOWzRZO)h;$oOihN199Ht(k|lgWl!oSIEaVS+e4gB_^-dhkvu#M?yYjT1ou{1T>6_h zq9gm4IA1YDsRal2uwP5T$~VNN2ywpWzeb6}`>oPK;{3wHV#N8KO9YPi;fP}5{KLas z61BLLB2kA+)kw6EOV!~hAdc9NM0pQZT9ZVVv)$^_+9b-mrc$`Ks))y{OQNM5dmxEc z=MvoFndVXh60OapL*Z;eW_wp!PC_w`Z45^XaS6J=U-_@ipueL}_9IDLpqU_>~KOC3q{0G`khB+9#`(j!TfcSfb1NtAa+rCmvscR{7yNtAayrEq2w z-A=IVQaH0|5|?_DDDQ$w`@#uFtnHWfC($-Mjbq^(86Gx>L_6}Z<4E)U zqDOOSB#HLr(r6Op{YmKwB+C1f(lI1DjQ={0MEU%+bUcY3&%-8?=ol_dCeaC8I+;ZI zTbEL>d$U`>>q2g-34+}M-VJdd2zHD186OCCOL(cuexrijvU$b_g545!r1){b~r zRIpoRxKP1vmEl4KyH$n@73@|SE>y5vWw=nmZk6Fe1-n&-3l;3v87@??TW7dX!ET-5 zLIt~Zh6@$!))_8Tuv=%iP{D4U;X(zwb%qNS?A94BRIpoTxKP1vli@-IyG@1*73?+{ zE>y7FWVlelrZ?oW8l!^UCc}jacAE?rD%fo@T&Q5T$#9{9-6q3@3U=EJ7b@6oGhC=( zx6N>&g55U5g$j1t3>PZcZ8Kb`V7JY1p@Q8u!-WcV+YA>f*ljahs9?9taG`?TF2jWi zcDoE0D%kBZT&Q5T%W$EB-7dq03U<2;7b@88GF+%&x65#$g555|g$j223>PZc?K51c zV7Je3p@Q8$!-WcV`wSN<*zGf1s9?9xaG`?TKEs6ycKZw$D%kBaT&NIk-V8Vt@NX+X z0za@2evrTqJcJ)4@BcH6?w_|cAA_!&Ribqhb^M>}ufXZ&cd zE&Plh?ZAbf@uNMr@H2k2?-qW>kM`ce&-l^)oBOF0Zcck};b;74A1?fiAMM43pYfyp zxbQQ6v?mvS#*g;p!q528-dy+@KiZ!QKjTMxbm3?GXrIpgR0=nzy}Ix-ezac~e#VdX z?849Z(Y{^y89&;)3qRvW`*-1I{Adp^{EQ#%*N@uQ=K@H2jNybylIkB%6^&-l?X zL--j#I%)_%<<~-vA4~#&h98r_pW(+O@Mrij3H%v;Oagy~ACthJ;m0KKXZSG*{26{s z0)K`dlfo_J_`xLbOMX-WzvM?H@JoJF0>9)(CGbmrR06-`M9)(CGbmrR06-`M9)(CGbmr zR06-`M9)(CGbmrR06-`M9)(rEm*5elQ9Ak{^}8FZodk{E{D)z%Thx3H*{DmB26gQ3?E# zAC9)( zCGbmrZ2bW?1Y$g4Qn;lYKbQpm3_m7;Kf{kn;Lq@568JOxm<0X|KPG`c!;eYe&+uas z_%r;N6mBWU4<>;>Q+`YWzvM@yyz zpFMEy^ub^)RZs?>l*Q&wA3Njp!870;HN5G^EH8VJvK3`3V`a0+Yeg`f#F?IE!*TKXDSi0d4C|N}TkVIk9s5Njw_7 z`p-%O&U#jJ#G`hrOroIdiIBAjQUAX_vQn`2s#O?^-@D55D?^W$ZH|>~D%+BbmOTkp zUQ^len;z<e>RvR_L>f-Pj;mrJ&y-( zjGyoghmU~PG&B!-{OXX&vnPX+&eNyQn8S|ygNQB|m&}0O3@o^m<#vUFc)s9VJ=)j!(6z4hPiP4 z40GY~8Ro*(Gt7m%Wta;$%P<%2m0>R2D#Kj3Q--;4XAE=U#u(=QTcdy{-0H%@;l>sjegcHUy)B9#Zf{ZiaEFWZQ$28#i{giSTbN$B zwS~EGXA5&D33sw^;kFhQ4tKRMcdBsVo)+eZTUwY4ceF4UZfIfdDZ+)@S(tyeaN%Ya z=7&pImT)13?g~Qb<%$+Y>xK@Sv;Zham!j&q_ zg$q@fyHL1rnF{kS5-wb%!u)WJ3UlES73RVfD$IooRG16br!W^TPhl=xox)tWB!#(f zMGAA_f)wW7AzZi|h56xX6z0OkD9nXxQJ4#tqA(Y(L}4ymh{D_lg!`ay;VKjs4i}*? z_Yn~em!L2|T!F$|xB!K@aQz8$R|prbK4Jb(`ZVJ=*G!d$pqM7GDrz#0hb z=~*~jHNsrDXoR_N%?NYhk`d-^7A{;c!u)WF2y@{I5$3`LBFu&BLzoMfhcFke4q+}_ z9Ku|q3|dmxVAFt_or9D0AVg%|G`|i{DZk)iSVz53)gRrT<*bKxY~ocaIpt-;aU&o!lfR}g)2Rn3m1AY z7q0VQE?nk8U3!%VbKxQn=E5}|%!Nxlm`Lx?Z@17s3wbFi~XJo z)fR3Y;qD(gfc;)q`0EMxK;a%F-1@>jSj2B2{D%ntp~Bx#xaGoaB;3ZrZ6e&mgxgf$ zn+dnMa9fDqTMD<8a9azvjd0rvx1Dg?3%7%CI|_Y=3-<`&b`tK9!aYj3orT*)xLt*w zZo=&@+#bU1Dcqxl+e^5|2)DOz`v|wMaQg|jziB5~M;?ETRQ-nK9xU+>jN4Rr^d#b>lCj6%h_YC2lDcrL}yt9RSjtDM?3?v28|Nw_x)_ZH#aD%{(Id%JM&5bmAAy-T=v3-=!3-YeYugnPdz zzXyc>LE%0m+=qqxh;Ww*_fg?46Yg^1t`P1@;jR+yYU+kBhMRWQgeqVa^(^#SXTwZ7 z3~rP4p{FdXPowgR(6+vfpRt_A%U6b8C@&4Y)Tko#T1DuciqQLg8dzpgCMu-MIRGYPCYD znj}@GBL((nRZ41&LaK%&wV#d@n8H;lsS1TuO-ZVjjucqsRVk^p3aL7h)c!hBV8K_V zq#jd9)s>{`=}3VwVU?0vuaG)OlB%yG1$K>9N@{~bs(~bRh>jGPSXL>i#}!fyC8=^9 zDX{jeQc@cgQjI04COT4Jcv_{To=`|Nm86>KNP)d;m6F<|kZK`GwbYRU>;EbxwOJw6 zT9Rs`BL!c!RVk@03aNIIRC^t%4pmI*NrhBLN$PMNsUyru9T{Yn@UuedC`qcbj#L+O zQr!ZOvd1chuMhUiEQH76BhHDkS@kQydQ4cCzxVNNQ@YQ{%uq$D*; zM{2Y=sUT0E^{!G<$4gQt=t!MtPHJqBr|$!W)Hq4%Bps>o=Ahvlm^`%1U3`y!t9jUXbnABGask0@ib9AK6tzuGNE2Peoq|Vooy1<-N zpnggvHBXYdP)F(_b5eo2gm09Rx>%CBL`Mp~3O0TEE)UXqs-&)vq^{JFnr}`jP)U8O zl+;y{)YUpt*O-$E)TUHY3nZz9I#Tf2wrTYRDyi?3l3FB5E!L5`&YV=BlG>$^S|UkZ zuOoHC|0}5*C8?Wqq;9TaQoEIsxJA;LJIzT2YUt`-!d;To z-8xeDR57VNN=e--N!_O-b-y{OKu@1a>H$gWK^>`w%t<{GWSIFyDXFEB)T265aJqzP z=eZ((QY$5?RXS2|(1j_fiXfzZRZ42DB(+XQ3eMLsCAA@cQjbeg8+D|fFeeqLq5r0o z)Fw%4vyK#;I$~NW66;e-1Qd@PT-~bd;QqKgbzCRRF+a#%Hb)>eNlX^aXQadE6 z7j&dvG$$3P`uLp3)WgV$k%t-}m=qjmKC8^hRq+T~C^=5$TgHL8W_EYv-lGNKe zQg9%TX+z(cKdJX5srPlHJ}@WsQ4mtaN=bbzNqwRt^{F|j&x4RkDx|)Uq`uUV`pTSC zkcJ+rrjYttlKMtR>f0(NRi==VHhH$rCXZeVWZKY!EZalX6;eOSlG>#!sohmfs)j=9 zCrRpO9jQI$q<#(3(DzeF{U%BMt|RqF6_ZLUr2dqo{?d{9yNXHGQb_$HN&TxMwYQ2% z)%KDKOY6n3&U%qvXJz{I1!_}u6jI?#NrfYtlA_mVRVk_c6;e@2sz67ou!>0?ppYt( zq+&W!aI{^OmQ-DZ6p^G7I#R_|OsbwjDk(|1I#MN7OzJ>|R7#R6)sd=J#iR~WNR>%a z)pexcK-DU3Q}q>6`$QIGLeM#zI9jOLYOsb(m>JUllP#vj;RZOZ}AyqC(HPVr4T*agsDWsZ6 zQithCH8my`?6arl3aMt2RC67v7RIE)t%A(aTPUQYoo85Q=SlBDH0;sC?SqhNrI6|% zORA%;qz*SG6$C-nTNJ({4NDY=Hb)2rGhM1EY z7KGFZ3aR0e)Ce6ZI5FC^qymu|qmUXUNsZQ#I^LYri9t$Av9b=2k)+1zNR2Zm6{w$5 zNu4A~jn|QaBfSl)FW7)QPN}|$lGG#}smbP~0)5D;lA0n(ovb4@)tpqIFSb=u(#|ui zv-6}k-I`Wkps#CHQqs;dth4i^cefgn3J2;ECM#`9+Ifa`cAoU2SW{A`1?duIDWp!9 zZR!kNn>y2+)Y(BuU9ONiN0K^MN9sItQWpdvb%jDoS}%rm){FGIPSffOG$1QqY=@=w zVpwOrNUsSsB^Bs3$TdnyN$bV1&U%sFSZYe@>LAsplDbB=sRg<=wa}c@q9CNMRZ42H zBz2vR)Dm-2fl5jxb-g5YgO1dV=A>>8Qd0LTB_(b0!aAEgdZDXnn+ing0fm&b$qVaj z^61^MRZ8kXg_N|(3+rt1=w-Err0gJHt%V*|NJ*Q#u+Aor-j-XXq#jX7Nt?W|&L)pu zzgwlGmMWwkmQUX!x~Fex6_a{YA@!&vwM<89xjCsIU#*3dgF(V8B&n4;Qmf2K1v-Oc zrBYI>C8;$!QWgKNq@?v?SZBRRFKjk!=;0vNi=k(fl9JYoVV(6Ny)oL9)aD?=%yxy; z7Fm5y>Z)(6IjKN%^p_M;Pf1cw>qtFgPU_hpCH1O8YP%%$oQ~A<=A>Q-LQ47MH~gX` z^^%Sh+*W7Wrd|y~>MfO*ry{ELP&n2lZbfmtlVp8ubq`s1*zSfcYriw`^Uu=iJ zm88DYk%FrtO}m6Z)%T%NQa?yiKk7)qt(8?u>LZ1eJW(*LJ5exfexjfqJp6|w^{0;1U&f?@m6S^AZ%OJO9jSkfNkyz6C8c~E9SLPf zMQjbJNZ6QEIM4>ikKQ&FiAYk8j#Si`RHQISNvWiyOL;c8N@Vq=bk$dCUVUXjNGTtPMXF0uHFTu*GbUvRsy^itl}K8W zs;MJY%a~N8PLPsPNl8nyh|bb1@*gbC0+rNXN}H0FW)YpGS>!)hngtsB{#HmyOS6d1 z(kx@f_aiyfBrCCI0X%;cJ zG>dc!(xy~WN6P9uN>_cI&8x3#5K_vgbdhe7RCgVz9_FNu4nnF#slHy4)G<0zz0FDW z4MHlVkm@H%_1BRaU`)ym^19Y8RY)BxNe$GI8e~i=a$Jy-Qb`Swq=xE94KpSc4)VIz zR=)3xNK3Pb&eAMmZfO=79i*g`Pw67^oV1#N2)= zSV^g*&X;ZK0$rP$XWXWO_2|mSJdq0}sf%=^E;c3=xim;aS4mwaNnNfZb%imhK$~W^ zO6p2UYQB!tRmP-(l~hBepO-Dso+rHq}HaDS7%^ zM0fgI#QgNPU{9Y)>PA^oH|a|1X7iG|HAqPvrj*oelGN=wQg@h>3e+X2r0$fY?$VLE z+n7|a>QhPGBT3z>BXyrKsmKFCs;{Y1eGf`f59vrfY))!v5K_$)Qjbbf%XFlc8QhPTGaaeV%}IS3 zgw#n2DQQ0y(b-Q$%L(qkpN&ZcTa2otr2SMxXFnA&x1S0H`H36` z3MqN|TSRyITg3eIx5&Rix`f#ZslAytkwDQRiu=q$|~b4xR)O^_~Oi9)KatiE=->T7RaeI0|4x?Ul5xFmIi zj#MXOQo)9qn-x;h(#+9WnmOi{X5m0@+wW9J$urFy-I-?2e>l@D&|>s1g;aN0eLZy5 z*VDNAf^C}JtB^WclIo=+b&NTwKwH)iD5QEzQhju!`Wll8wnA1(^^>If>qreSCKYUZ zQ8~oHkv4gb&L+<>x5*1uQYxvzvZRjFmDCXPk_uuZZ!0HDI720=VLDR7%}E7n=*yIb zK0=ZjsUtP2ib*Y3NR5`Hj@OYop^8bZP)MC9NsZBw8e7GrRw|^%Nm3{2NR2lq6{w-F zR!B+fMMr17=$KnCI#Ys7T`Ck(C(DwWsw=5!#w8UF@@>1lRv|TAlA56-HPe`s6UcgT zokB`lFFHEwMaSHF(Fru4dQ2fDtrs1g^`c{Ly%=ojvOytrmaM+Bb=7x{dG(zaq@izA zNJ;BOM`yk0m|HJ87X=~pghEQ5{^saTe{;-Fe+x!xi$Y3TFFHEwMaSHF(Fs(2Dk*8b z=;*8$9dqkN=b9kZr<{P}$h&JD-QBg0`Q5e7;vl59Db;tKeEOE?p1$jipFTUt)h@P5 z>IO;bMjfe}s+iPvrKE0_q;AoXy49RipjpE63Mpy5=;*8$9dql&U<-#=6;jfA(a~8i zI{(3XF~}(Z_G=0$X}##^tQQ?~>&0MG7nRigvQ0gpYf}#zx2a&?%_s*LIS)xv59>%h zQpKd+R;o|lUF+!Xu64}su62UkU2ChPR?3oEr7Nk`#wF!c1nJS=RZ2>p{^saTe{;-F ze+$;8l(T}I^|GWk=t}Bw^OAZZNJ*)rHc3*Ob)>c!lL}T+%2`3qlaka{9jT{`Nriq1 zQc^0ZrzNRpbfmVKlL};3@`=*WrJbjvv-5QRgPmufj}BE*&&!h9p)08uj7ut5Kc$j- zQIdK|N9tu`Qo#&xl%t-US0t%db);T1CKc@IQ%SupNxh*X^`CH1kcq&}(QlKMd* zB`sndokgr;ZV?--q;@H!zK|vLrLLsDGA=3Sn;>J~ZiUphlGJxPQr{bs3RY4oDQOYw z=qzF#bBkE#rywQulTuPY%aYooE2&?qxTI84ze-ZS=}7%Y0@q@tEFsi+;KP5t66sc1MuDjLy|a*Rm@D=C#!RFW#tkt#GM73}Hz zO(`j95gXN6#7506VuMxRUkWK{5gXN6#7506VxvJ$6ttCt)}ke{`ck^;D>bgZKt}Rm zODU;pl2nol(dMA>MUZT<`%KxAh*)_NJ)#>sLmobYHkr5=&~*!DQOWK)mg+w%`IXB zt&qdDmFklgu~D5xY}DK$Hdytkq@+b`RA&(zHMfWjR(&cdX%QRMS;R)oEn=fBgY;7e zDb?3Xb_uO@T|yh^!69cAn87XD^1EE7dndR^L!v^$jzwzCcGk`AEsL z7o)nf7o-2-?8PAVQ$A9oWJ!(ImDKUZB^BsIK_96TB&id1q{bMNijE7?CA3i5)Jc-m zcpa$;#-xIkR7-`FyyZ8lyX7}(e#>t#QmqtH@|NGI=9b@3bZT^(6)JnyvaF_72>!Dy zr+i)Xl;t4UWzWICurCAu7Bbz0M~Kdf&W5m1bWU`xxLBmS6^8#TtDwAA<8{%qaCluF zMZh6)^wdx_rm`S!R1;dCg|I5K2(0T*z21!ByUvhsv99mAB@h^0w&hBIA{_M# zb13+N=$+nHbO*GeJ6Sp0mm`ITO;fmErtp9_h5I3e2UrS^;Ki~GPawPUSOS^$0BWI$ zEzd!EHLf$eSXhH##j?Un8k$CQ1xsN~w89FrXMcbdf&bt!FRxX*$-3whcoOA2j(jo- zqwB=;TNr%|B>H3(M%P1PVe#~>Wm!suqw65i$KY>0OL$X`tZl{9&Cc3pSszN)Hp{F% z6@6N?smiQ1Y7AN1fhUojwP!>Uh0$%a^jOxOwN8bs(T)JJ^b91n4gQ{GS$ZM*qDXL# zRRI54R&hBbn2w~KbaY+xZ9Lhdc}!WN#nG3nTUlE!j=mgyhb3DaeT61VHAY_riPlqb z^fiziCcO?)l#xnD0q#a$hQC+f?^XDF4gOwd1mDG5=m$8l>=wF{mPe+A?qn)IjD95A z&nVzR*~ECB*G0d=)wbfXWPW4OPed`tqBH?o%(3XFAkqBBqMv~j5pC&XmUu}7ATC69 zA({&j=%eyAp11FC5=MFZKKcXRfPTW2W;dWr&I)DD3VF^l4ak!Z$ivUkJy{Q9qsDdC zMgK5OkUn^9tcIs8(_-mknRyt0$s`O9VdjB^g#V2G1r_U`0qn&GM`eh$LIoCD@&#d> zvq{N^Tx7^!UEtsv6+V?iey9}5)arr)vrH8h6p0d{1xkz5Eni&_-v+arwFOBkQZnJP z?et$O6wjJMa8|Bp=Ai<&pafA^$`w`zg{A*dVU2?Q5QR0l!aAU^=6_VUf58Ew^;J%h z8m%dCRzMaFrbwZ+A(}%rzU*NtLQ=ttlulS6w+(;wnS6(AuqU zRJ)Ga20j=q?Y3s%258Fd&A^ACDR(pjABv`Ygc-OY3O>>dT#kY}n}Hjl;I3xi#wfVE z8Mp}w?r8=-3AL{LczzGfm@^C zp=RJVD0sLTxGf4EX$EeGf=8Qy+oRwU%)lK`@E9|2N3?~FGXo!vg2$VIk3hi_&A^>d z@MJUaktq0NGw@L;c$yiwGYXzz2JV7_PcZ{`MH|U%GjKN)Jl71|9R;6e2JV4^&oBe` zM8Rj7fsaPP=a_+eq2Tk(z{jBA3(Ua1QSgOk;65n$Vl!}G6nv=}xE~6>+zi|w1z%|f z9)LboSDAs2MN_`U3_K78FEj%WLcxp7z=Kinb!On>Q1JC;;2|jZMlMrDotU zD0rC}cq|HDVFn(Df>)V=PeQ?K%)sMO@LDtQ1Qh(38F(TJ-e3lvgg%lR&A^jU@Fp|x z6qNQBGw{hMc&izBDhhtu3_J}5Z!-f=N5R|8z%$U&e%=f`6HWOAGw>-W_$4#&EEN2T z8F)4de$5O#2L-=j2A+$8-!cQAidNM-X5iD%ly{nePe;M;n}N?j!5^A|&qTo=n}N?l z3+z)f@YyK%b2IQcDD5xJz~`diug$>cp|rm>1D}tk{Jk0Y0u=nC8F(HF-fafH5C#8i z2EGUd|6&Hd7zO`k2EGIZ|6vBc6b1if2EGgh|6>Ne90l(+17CrG3qxk$D^YOR3_KqN zJ7(akP;h}6_-YhfWCp$l1;@?63s7*v47?BpC(XduqTmuU@FEmkY6f16g3HXn*P-AV zX5b|#IBf>L9tGDj1K)sx>zILWM8OA`fp0>=^~}IGqu_(gz_*~_gU!IVqToZ!z_+2` zhGyW~QE($O@Es_)i5d7#6x`Gdd>0CCZU(*^1-CQ<--Ci%n}P2|!EMdJ_o3kSX5jm= zd01gbGw=gw%14-iA4I`Nnt>le!JW;(52N6&X5dFqaCbBCQWV_N4E!hx?qvpEhJt&W zftRD;zGmPRD7e2FcqIxx)(pG~1rIUQEY7l{xyme-<8YQon5)cUc@nPj$UIbz$5nRDL*)cq zW!F4ZPQ+Dq&qL)TTxHKZR8GcK_R2%$6ue#bHdmR|E>Ff)_RT}(R9t2MJXB7@%ko%r zm03^EbX?`2JXFrWRUVgz%9*&zp?Ro01y?yd50$fUl_T>|IU83wIuDg|aFr+Ip>i&+ za!ej7PsN{}apo$sp7GOgmE-eJc{;9gVje2bz*SDpL*<#c%9Ha@c^0m6S{^FT##PS9 zL*+TR%2V=Cc`n}6XPc|c>VnV1RnE;r<@vbE)ACSx0j~0lJXFrZRi2fH$_sIo=j5UC zB3$Kpd8oV?S9w7mDlfrRUYLi}KU{ybFPh^u@s z50y9JDj&{6<;}RtrFp2l1y{K&50$s#Dp%y8@-|%MsytNQj;maghsrx}m22}*c_*&& zu{>1Xg{$0+y_#Ypyb@EH~gRzc*KzmGQ@Ml|Sa8 zawD#CcOELAz*YX7hssU3%3tzOxfxgaTOKO6;41&fL*(`%EC|{DxbkshVxLl4Oi*pq4HT=WkDV)x8o{{@=*C4t}>p7%I9&Fi9A&9z*Q#m zQ27F`vLp|cFXAdo^HBK`uCgo-l`rEeYviHw6&j;lN% z50!7=D(mH;@=aXjL3yZr3s-q?9xC6)RUVRu%6D*;4f9a>F0Qgs9x8X@Dx2h?@;zK- z(>zqZkE?8+hsqCdl`Zp7`5~^dbsj1|!d14-L*>V~%JzAv`~+S16m~RMnYHfu6lZya zxyr0{&u6&GBlA%CIj*vE9xA`URd&ro<(Ih1?s=&E3Rl@P50zizDtqOj@*7-b?>tm~ zi>vILhsy78mHqQj`8}@k*gRDJfU6vohsqyumB$5FX&qI#EBj#8!mN{;i?B-!tS*H= zBj8{B=MA5ag1e#M-~8YUP;mFc-;tF6^n>T2;GTuq$2PAn{KpTz5C!)_!F&DSi%{?} z7`Q0p2VabWd!yj2^P(?7!F^D0*3r?l_+>13U>YA`6zf$QRdWY&vC^??5Jw*kUo;`mE4@I1Q<*}!7csZTTt*sv^});gKtH_lTdJ5 zKlnBjJQ)SI_k(Xo!BbFhM?d%u6nruYKEe;a69rF2!AJVRccI{ED7dp9d^ZZ7j)J@T z!S|rx87R2BAABzgo{55c`oZ_1;8Rd=FF*Kx6g&$B_x6JyK*6(7a9=<8K@>a(1^4%Z zA40)%iv}Ri^FTlNVHA8Cn(|;j_z@I*Itm`*2QNjzXP~r)`N5B(;4@M12tRlk3O);^ zJ<1PWj)Kod!N>c-D^Tz`DELG_cqIxx7X^>?gIA&8^HA_fe(-7(d_D@E;0Lck!55(5 zNq%qz3Z938r})8ZQSgN*c&Z<~4h3I?f~WhzkD=g;QSeMZcs&Zf1O?CXgEyeyOHuF~ zKlpJJd>INp)eqi?f-gtGr~AQApx`S|@R@$_CKP-n3O?Hp-i(6hqu_J>;4LWlDinOa zAN(W=z8VE*T_(5{1z&@9fEW2wehLLIKvTZN4}Ka2FGRtY`N7Yi;A>Iv6@KtG6ubxp z&-a6$MZt?v@YR0sb`*Ra3SQs`KZk;spx|r$;O9~B^=LgW_Jenz;2Y4Cm-xXipx_%( z@C|#|lixBI~#py1ok(!SFV{saZzj)L#@ zgTF_?cc9>V{oq|F_)fII?)QUtqu{$x@PmHvPbm0q6r6RDnX9yHHOeJO`56nrlV z_TO+BvQhATDD4&gl#5aD{U~^qADlwL51`;ResDDu{2&Tm>j#&i;D^uxd(026j)EUX z!5jSG8YuV?l=enHxCIJcil)5D59YTGEBEigZpEW$%3J*4)@aJh(3H3O!EI6Sax~?q z{or;ecm)dH<_C8`!7EYlc0afy3SNbRpZ9}1q2Sdh_ys@sNEEyV1;6A6k3qo|XjQ%9 z2aiL+Yl~h*wmRSNgC}N##YW?6(9#}9>A&SyGAUaLfH$J_-!TI}fr59Mfj6Px_x<2g zP}-YO@P~fzEEK#21%K=Z&ql#d7JY&Y@}K#^_{)>0(5m{v5568v`Dv8)SAH4x3fAxd$sq+gc_;)|}J+!o6M8WS=?M1=wqO?=Kl_?{oi&f(QD+ z_6g=1u#j!^_rW{7WC;7qXR&^+Xf+zUFKcFc)D0q?|j82(DQ4~DI z4@Ni1Lj@>!svrClO1lsRPxpg=LBT~Rc%~ox7YdG{;8{L!7~Lcf#ZmAaKRAS@Oi=Kt zesCBCCs6R|elWUB2o<9v#+iO_O*G{s3O?HpuAL2bJ4dI+&dJ(Xs)(KE16zd{*g7h9 zJ_4R+0Jc&Eq#z-{3@3 zyfk)WNhso`*T!zCh~2R{b{B-NjNM-mdzg8bR>W4RF&pKMne{Tp+rmf3uA)U>wgX5w zq1aWf3;fo_9^?E%3#=l_FVqjXZCDxG9Il9Mt%yCteU(fd_n_SAKesuyL*~hGt3k|6 zR$iuxDq^pJ<_OdLri>U>BEG{T?nELMU=cq+A{Js1KSm-JVG%z=BF38|hhKj7eLa|W&kZ0*1>W5X-SFx`}L%IbNg`p1n*Q$Mo z)d@=L``Q(;pEk$#RK$Mswv?uBzuYzT=lxcR3Z)$de~^nT`!DOLz6G(j%btTk_)-9f zH)WkpU7j*0NIAs53BgxpO!^iio3*Y)n6|FiH3)-b>+IVqKn_@G%wfzU3A1{@ZH~RYIX(v- z4cUXlPxW%{j#+QQlSSwTzAGz0Z zq#puD7sRJ{8Z3WHNE>WTD;hsDeil?xfmJ(xw$+(6*zw3y7C$F`uE_2bh)f%58z}P& zYS9Nwt*jny-JH3I`xkkk9_;DijjN3;^)~VI{H1;#EA@Ht3k8iCf<{OBureCrIcKHI z`k(kE74a)7;#bN3v}dj^h(F0aJzP3UE**1mxmp&<)#BM50Y$PvX@dhkW@$HqIzAX*g~~LvF!w^*DJ+F2OqrHj&W-Nwaj=0!%!tMe)Hz| ztrhV*M5D&>y;+M8`1qX&{vHUsPgYZ(ea3$f;y*0o_f_Lpjw~sdh*_aytPY{x)|sI` z)(w03K}Xzk6RNY&OZx?tIc`nxrNkZj|XZHRXb{VN$*&1Ji3 zo{Pa&$zZf#&@jUwQ`$1+W8LbNDaW7kr+lm@<%TllhPhIHTDI7wFm0vHzZs;wjXjub z+Ul)^LApk}0hrFC0~d^C+Z$JoW&N7)v1}QPMw!geIhJUm_oxZ<&t1(*6CLDg8idkB z>0D0Cl%G-4nw>kX=hT?GW=cocBdk7Fe>uV)LPyyCRv5-T7+oueSQ%i$j8Gk82eDc! zhYIKqW9;)V#)hrKVT|1YV=N4wp=Ozy3^mJDlP}0Nbh2neZ8L4iQ{1%Y<;#X=WQ!Wi z)=aX$^|z?Oo)*_#mf=+bm)0QD-IWMELoY>p66dkLYRYR5{jPZM6 z;^LjBbXN;)C?iHECN-eYUSSiH2o&0@Vq#LClU3Gf@z-QAnLq5q^bh+mPXQS`?61e) z5Ob27#DsUk%J{pPx`O(V)4kaDApYcSiX+_~IU8*Z7L9vkrH*u)db)}C;U{$hYlZj= z20oRVAnSEPu6q3-Q*e>ZKpT3B@GjuY#x`(2g1=Ap^>}x7yX0iAjzFE=Cb?tU-gMNZ zT4#5t1}6)rvs=?sI8On0HZukHGx+<$s~_v8y0~3)r=oOIUG|ZW_*dRJRpl7k#T}MA z1zYB$i+83Kr}!fh*(XDEBac;=5gO7?5){uTgH#+_=i-HOgBF zbgB^wr^5BZ^<^Jj4t;dEzGkEg7sTfjkmi|wdx%vAgIQ77ckD+dMjZhD} zUZ|&iD7c+Nz3eHWe)cJ${`TqME(jfKUmqG^FAEK_9}5k(H-r05XsG>3Xqf$VXlU3D zjSL?b8kHG5fl8G0po3?)#Hvkt^1(B_E7Q4!cjZ`}lcS@zi#~abSerE|S9VLrx+ml; zu~?ST_*l<~(1i4|V4nj1*MuAcQf6-ef?WuJEfCV1^x>)7&%@?#6pHBA4W!@jm1Iz1 zrZvFise&AbbWF+=f1;+_AkbK43mu-_LSeHZ_O>?xwP&5E-2?LCGHVZ@KC*(G;2pju zmRPsvEJk$%fT&mHj!K7sc^x9@2%T<{G3kh$Z^k<~X(zLLqRmi=wOOBl+$K6b~2eNp0XA&-J_eGw0+NH+f)|(Qn^Vwi9JC4JAgtm&DtQh+rdL0 znN#-lz)o_z=Pc~(2bQPD=R!@$Ecw9B_CBz);DMdZQlCTSA{l}GHkiliGIFXnBd0P| zXUZMj96iq@cS6pLkaO|$G8s8bY`!)jXL~kZ$ytz*vsvorp&7YwpBXvdo00RGs*7Ys z#)>ZVFtrPvRAOBcFeitRi$zWjBbRt{axvuO5|;d>(w4j~+irxmwSindd@Z?>7E#F4 zwl0I_Ghgn;ZUnM)kH1b?jN}^#^VtI+ zHeJazY;6OZu4I8&+w?)!He{j9)lkS4eZHEoT#-eUGeSvwf!hvhL#3^@-36Y9unCsl z;#}#$d$-IgMy9uDpXn{yS9;gW^m5eNjpnts-0hH+{r|pI?yI%sO0C@_Ywc!Tt=*zq zFq7NRECpLIuafj&!Ax#v^kBhE?hy2_1v9xb^J3FJ2lf?;;8~hT2VcIPCwC+C_K4{! zxwnEm04*W+PVs8DPGu#;=nKnvbh`+K^oN>wMszmL)Au1>%}ceK*JNwv69dq_EbVxd zN7GS0UGOSjsa0NqC@)ACFygDz1s>&v=|YckxfR8+a_*jTJDgX0}8|TT`tW zFdJBBZMSy7?4S(h2My)yV2V|UZI$e`jVB_85dk ztqPb#tcNfs)DXfpKv-d@6v7^dF#4u`14p4oSk+s^epC-rSW^krJv4oxeA z*(!bVUgG**miit?^cAIxSgUs!k8y(9TOf#^%56HMREbi$*rI9;5r?|rD*52dnAh_Yll$&`JZPI{ENX*XNh zr=aX}scbW%tR!8+lzo{l@hD5BQ`ySC24&w$Wm^zsrRh?p?E7@7M_ILWwQOau=|-E~ zZmI7{Ro@EOoXhkYJ*^?uaOfqjv+lDV1ow06SL+YxJz9r)gnEH{acD{CMsVKZjcxv2kmb;I*{`e___yclFu95c0Kgk~XXVxPRhn{v1>ydjvkNgYkkspMx zUs;d52zuY&Xpe0D0b#$>9@+X7!v3H=a;O)C{Rv^QP)i8=3&M)vb!Q>@8^TEFLJ0c@ z!s4N?A?#lWD-OK|VS6DgVYjgg6BdNIc3rDpA_QSc`$7n_AuMH2gRn4!mDn#sSOmhV z+3O+9fv{5A#Ump@A}Xg(>ZCUTHY8#aTG?m4=eDZsqvJ4F&swl~KLx}ly@{e+>BW)s z-gjH>BR#J{GMXOAm0mHD-Us_k&-=k4nqD$jdL>ADAG)pgkw5P@ifDQ%IjJ8Z7A?*A zQfxy-qD&@P`L^mKe-^V2i|~HgC|;Z??|>53Ws<%ovmcV)ZnuS+#jNza2XdfUOw07} zbxWcaGG9?`e`I(6v)eX{PTuR5pXI^;Onefx;lX1jK8ZT;;L&9yw%SbWFLUK9#kxo- z?m=j)tIa)(1K;vNOR-+A^bX2S&#vjV$tor#J=<$`jHXvVS9%SQ^xF9!1b-{By=O$A z=^Y{;yyY;ZrF#<8f>bQD5)JVt;u&0M)xGPO|%o+krPCLAI@wG z6CI$W5BF?W+gE5_{D8?|;>gX3&b}>0+xt=0;aH(|$(4LJcmw6NShTMUki7S^E;RY> zvQ96A*%57S!`T3m=oyW8^FH4l1YH9DvMg~-W$Tm`Jl{QfAAJblrQ_{wI94>hB{yFm z*%wLg!+rKy`oYu+#V!BA9&`6x_Oco;fA4!|h)6u; z{uE?jb46nE%EVL<;Dryf(o9UxE<5O1YS#l!%%Rpj=;4_J75n_Q5~Amm5B=|c4gv{4e?u{5HGDrTp`PG5i>*1 zJPOiu+FInRh}e&7is~tRv`_M4uSuFHje`_2YG)w%T<6xS>^l;be6I6u*+Ml^J`GG1 zE^!Y;6)ti2_k?qWhngt7Ug>2j8D8%mkfpF(QHYiQ4c?K#RCq7XQs|O3lQMHAT&_h_`sHSZRGg#Fk3?fL;0APs^=J>GQ_g+8llx z0&lCpwXO4ZrIGQ}+ndAhK%Ui(=I}d}rp!}6LV?4Zh}=bYm(ovh_>l@+oAsdTl%D&;gW(?F+Qb zUo`+4Awm1h=W^tk8f6Y&;WgtFquuf5@Ri75d7?Rd6#^e?4qvT|XZ(>o$sE2$8TL4Q zf;n7y6)TEvk~w^>zkM%TQ#3_^yYT8NcW1f|8A#}g%W%Q+7}6h2H;1oRhHGASGtJ=} z{7(vGewI1>apd8iV-DYlz)v-YKY_qcH-~RR;Afh{HzV+~&EZ=R__^lrClUDh=J2g< z!>lowen!k2ZH{jBDSw*KLtZ37`|Kf~Mjn()%;C=<@XO5M+YtB_3f!%$d(5BpXC9uE z`TqgGU0Fo%2lZ+Nubp!}hxCyP%;C>_t?or1d98%!sP7&Ao)PMMu>{fj))(0e$dI_? zKj2^Vrw>Jb!+*fPgy3%~r+Zu-n8nY8b&2cJQP10UW?I2Nx~3nhCEzVaX6vfNdX4Qn z<9k<$8)$6!yUB}qoi&+U2ye{S++OfF;xS{Z7-MEe1dMM<7kU^o;|;->T5iwlzzjDa z-fiiaCmu7($i(xe{DzLB_nS`Zb!NPmnRwZH3p}NXKe5J}#s@m&TJ{7m z(;z67wdrC{sW8i*%o9+NSih#|cHR{*;~$9rc-r+uXSO{wIx`8RHe(6z*T~io#X*fN^UyAR6vJa%PFA-(6 z)3uqhkJ7b0%Ic)+WGe$(v4pf0v%W%xKreZy+6ZW^W|P}JY0 z>v{n7()E0RA1V?*%4~d%qZgx#F?>5z?0qq4eaCDQ@WHLvk%@liHmH2ez*tnMDyS%q zfk?cM{r7I~oR58R0%9lC*dubrrW1f-u)L`pM80B@J6@eWPW;w%4*5p{yrmr}~R*xS?`X?Tw|v39XfmvhAAUw$2y zK8#g%S^6+fWj9SX^;9cWpWWkga#9Qb zXLnT2m}IEzsD5VCBy~Q}Cf$Z*sa3j-CrfS9ZL_n~mX$%fbUOxUpKj*?v`@G90pJM( zD-$*Udo($spP{O=sXdxwtknGPac7z2e-D!X4(SdoJBOz`c(T(m-H~T!8H{Tz+lQwQ zXYo3v5BJ17B7H<6Y%|QPMTtl`HY|#l;=GPr+}R&VfENYW@7?4#`>S zYW@7?4$c{qb`B4-tanRyW2}3myLni5Pj~mRhNr71WVNO&hu_`ipgvRHe4g7Q-GeFX zmG0qD)-&C+vK(2WN2iZw@p`9^_QdOz?o}C2rt^odylK52lRk#w`=*ca;CrWgXOkYl z66}-i!vF)*eLR4^>ApSyJU@eE%76M=F4NR6-H&NHF5SE|sDsmkS=5Q? z!JeqcrH{*Gh&{6#DvBpdYDw?A3^+@Ha%c0i#9Q9Hr`S{u&pVx;CEzSfIpYeYSi8ex zv&ZFgH8%aQFjwp~MXPu@3`q}RnL9Z>#FM$9>7hJxo@ZB`M}?|swxZ&Tp`vUrn`)Z5 zZQK{LW^Uepg5GJW-rOfh6gz8**6>^oOAlkYoRJ>p$>s3$@O|a7>_6qQOq)wT_cDzY zBIUl8b03i&!MLB29^v6WGCeZW{9?@2Mg$EW{~z3YIFqUhqgdqChWA(ui~S_lDCfP`KGQd9&&Hz>kMFVdwWy-Ste zd+!|*5Cj1cq$pKE6dNdtBA{6Dlkd&!?cU7hZgWSLkih$X^6lo`&YL%{{NJ>lZABmL zFSlYIZ7sK^kLDbBDCfZBoP(it+O{S!FT14UoC;_ox1nr?%WW7oZRNHs8`$ELbBq>7 zvKuz-Lzz%IW1RYTB&ggbHk~-+?{e-Eq7-)^^kk8oYpCvHfWp*yW!MR?nyaq zl6x|o-jLs5Ic-%qZPz%3yW!MJ?nOE6lzTCpddt08PDu)u#{pgfS} zbX<|?geFrlH=N#--=v&Q$!{{82FZh1P9H0rT(4+8VJjgFkiM3OGn_`qBUnz~ z0;F8mloZWw_;LclNO>e>^SwNhVKYh|#j^Q<3KWn_;}qkD(`b1#<#baX&2Snck6}68 z0)e#YGO@UxjcxkQocCOZ4nr?scyi9aV)g~X0esG5hXXB#0<$IuX4hni<4(SUE~%{% zh&wudtUQ*;6KIvkGV+X*$5DCcxxN~Y(p;Zqg_0)Tl3~*UFz}b(Vi=5<$14nAyizwN zIWT9I4i+{Cl`)vd2@FiiaX?`{L7qUF2gwr{<`d?YDbJ*`M#(c7S!cEK57+>e;oUIsz1WQ2Y_P zZS9`t@<^wTye>aFexbaOitxO=kP%^#yhss&On=ko7R!t2bG78f%yUcRCF*nJ z_XQ>p)z#A-dEL(5-lLz`5?GIFm&!@JferYldwAr_jnu_<26Lb`SGH}(F5)ZJf-!uG zW4+oNzz#Wv4ivjoUP=|#NM6b)Y?-{wr7*T7?G4@tBQvkSak;#la%>_mXE?5qS9s#s z)}w9+N1L-@-05EJ4G)r6TDDSNN##hCS2A*}l2>_fJkvnn} zSNwW%N6xZ}-$2BX*U9VU4N#)~I>Ek9uU+gx6|Cvg0G#ghUj#>DInoT#u!%5lm0 z7h#i>1D1N|Z-iA+j?bz0ZIm}s6HS&kGA7z2Z&FO8%qIqFyZgm1I^0v#JPkC!eZHit z!Ni3BaAFwNnq3VB$^OGN6Lw9}!3fBnl;f(Bi8jldX+vhoo0*1ek+-;fEh)!W3eo#vmIPGv};If^8tCIuQL7VM4 z4+L&#Zc)Ar;S>hG<3N9h1~f}-o`v}>r&axJ8~rUS^IPCf^|vJYTQ>H$z3OlK>2H4Q zZwJ-i4%6SVv%eixe>+ZpvvW*Osy}|D{HSpagrpOAjwDuVowQm28(3*>b3QOsS1g^lcIkZTyFA$tbU7 z8|9U3R}|T-s%*shuc}J@TKUn&{OGUQ_?q&gKl`KR9p5WI1~5Mc{;0D3nf!Pt@E7-X1A#Y^>Vw((+rA*k8E|J})q0L10&|T;=z|67AYP-ChvI>y5Gpu&V zI}}!@nau^_B=#jx>seqCsP=|;$`HaJQINcoVY5r#McFue!*)0mN_Wui6n3yiPJ8l) zU2BkTcgwpezdZ78hF_8l_&{0+6YSeyFu0OFn=B{OXJLy9^XwjZkLy`h(bEj}_VM^Q z&0tc}zZuVyoVnrNc-CE-9j590fb7pBrxe@s$LzC*rBKfF6pzCx`T?#9su|o_&@j^V zhi!SFyuC7DCKw}J-peTD9r+!XLI@wW0W%E_#iq-Ht10Jw@;=HrLf*%4-Y)|*t7hT3 z8ob`kZpsp8+M9S(Ag}6~1|v^K)iYD*ZnaC*kttNoy)#K7)Lw!_kUflT&OF*-aBpQB z*)EaofOT7Q3oRI8XLp~7^9)vY0umro(n6tpZ3YKP&rWO(I|e|&LUuTi#WiN0N6)-) zFCx_A#4&qZQjYJHQMbLc9S+HHF_>?3d^NizM4WHX)3N>s!j-n`lrY~Qo&sQubtp)9 zpnRB(m&o&O0y2_uS5Ie;&P3}Wr};y5cK1^T^Xe(3`WpIH!73tN`pNyY3F5o7ucJ7eA0h7 z-@2L}pCnz&o1WCN&;jfbU!} z&M{o&9m7?6hB|*|~p`c#oY^z-q6v z$7&=0b!C9ndR4*T;a&M%+QolPewXRuACM0yU3~5J3;PS23D>cGZ8C@hHV0*xn}IRN zi}FE+&3p2D3>(-DY_F4ShgCDkI?OWgdfogc;de+rMETW|4>9}>%P{dnMjq6-WcZzuPbvK90g2j(7Uq<7!~N~-fi`3!0xWx4 zK22Hnl}|G)Kayc)PHD2Xe5HJ`d35~8^2fA9fB9pk#2NVvTf&u@c6xcpRgk!oo#3z? zrMu|tgUBvA`!Hq~-7a?G7(Rrw&pwLzbuSxK{sn0p&&p@1#AD>MjKt^Ub1tIwq(3~ zo@vPi`GVRKeuC_T9X>kl0pR$_mJ{^MWKU3-l;e(5j7j?DpR_;gu?oKVCk^^^B%A%} ztm18b6{qY~ysScbuh(-c?m-pyX?p&rz2<+KzBlZd{~y5mx>5!86*eJ%Y|wmu@bR%> zEt-pd%tbS#ZiwcKGR$uSK+KRYGXC+2{E6xx&JCh=up^O>TdY50;4NgS#XgN~&l&o; z2=}^RmRioRCo(uO=TrGpD&;KsQ%1^5GR%Jy%u$w#$n=k$o02(iFi{U@>i-%#HFa}pr0LLUz=>-kZj+`ih0Fgc9Zn4U4=KhEA08jF}`1Y#UPC7 zN+GceFPGWz!d#ahQ%R9 z;A5_$|7k^U$~S4z59OOo(Vyg>xT2?>MYknc1(FtE>mfi+2rQ~F!|H1WotJ(l5bJ@=vU{G?VluBC8tdxA1KLnpMFK z+Wm5$72r5sSf7Ro7JGhx3Nix#UCLzpw@^NdI(2{DkDIKy;pK!nT}9N^yLpj*FjxuY zdni9-_ZVWyDslvXOe`OT*oBW&86wWovWLU7Y|EO$^1lUfpW^*Yp8?Qj{ zOJHq>&6xJvtS)~tm{qg?#y?38fp)KT`yc$15gwoPZ>Ce@UmgVe*=XbrYmTt@K-*tn zR}^OlPo-C0zvaI*?Z7TP?syOJj=`ouk~V|5(as&C?mjnZbH^YZGozh5 zy3r1iP94Gq!S@(-L)g3Q@Xk5e@sA8X2937L|1gcdFW*-iO?oH+Yqg%;uiQRo=;gr4 zHd>WAQ&jnzJp}CJn*1ck+Gvjlr+ECH{&6tNzw*CS!ch5NM#BHe|Kla3k}&z?4+GN# zya!J&WJCK8gPoDQtN&qOMB720Cpj3)J+LrF{Da$11-%Y3tFHx&a}7;99f{u}{I`Lh z1m&TeK!g9uu!9F|EX)5f8hju>P&G(DY&!aAyeJ%%MS(t>pWJCr2f}Y6P(-DKGRO#G z-)B$Q`Gk96-t8(z>&R6{uEPq8z#7O4xv6 z(^OiQ?bS)y3}(`U%Cj2GX3(RCIU{SRD!e~b=TAkcNbWdM0)P^bLin6O%}GmCCU;zk zK%fM=gl99L#&;~ng z-wWi9YhMshf?OJ5>$atWPQ0Wxdu5LvPSNREp10?7-N@6_4TC|pU@G^EkVf$p};DXR#S)Ean<4e%XTC?FCO7ydn~iWX-22l}w6rlY^4o(2J6+1)NsM z4VunPtx%ubaaPC!lsu{xNEa@sp$hd@rN2al$p;nYqr$vI?l@sceXXE1fD8FIkY2p9ES*?M7Y$&babS=`l)Gh z_+ZKw%Ld+0&vamqLX>2Kt|PA>*`UYnnu-L5xpm{Ft*&uXC;hkyzE8#vvp~uFlY_{z zDCx5n1#J|in(9XGI87A;N->wFSf|RLiYcFQ0a#EEwqQXc-ND>273vwN_!%nH8|01? ziu7C~HKEu!38|og{%9AjH!q3jy}9IR?jTU$-P&V9CQnnjqd>MODtBLU$H`4P$IX)F7)tt@0TTS?@Gjd2IT$=RJAQW$j^_X3gh%FX4%)8s=7 z?w{rXCd?pvaWgZ}NYA@tNh1T7aqEO2Q1z%%Tb$#6De^b_PAPj_@AB zKV8y5k|b-C5*Pj_ogNbdUJ*k*W*E8SJf=8MifbMNxK4en1W-%R5+leRSE3|PO1et0 zf)z2?I>TqxB8ID^N!A!=6JUOa3KR>K#!`VskvmSHIH1J21ag)r1=Lcs#29kNl_(9A z(ykJ06Cw<@$n#BzFc`~`L{kEq5CjYVLE~BeMGZ<(znI8B?YW0ehJUfNjwCA_+eXzy z#(rgJqbHL)uF++IQdVs=NouqN8T*x^CEg}?T#52PDX*3wQ#3)-SmB}!CO7z;6J?OS z$yO~YNd>5_0+nP2x#J`u!@`Q1Bpe<`85m42h3Cxo53a!$Xj3Qey{)v}1(acX%M zD9@^D(PF9^P^-}rOUNBpqB>BjyGm$dqLR8-)0LR00Z-SUoR*P0j#Evb)O2xjO8Xp8 zpQ9yKkUOr#^FVoCEul@hk_m?eqs<)J`UOH=NU!G*G0Pae6FC= zdhCAD_x;v`6dPEj#oJ#sD8WBj%j1)-H}pV+K*ne3?lDLuWEQ4A)zyA-$LXp8P#UPZ zBC!&505lBKE*IG9tI{(L-FpTTs#Uq&vJf)h4$E+ zY7z$i$TF;Mz>tx!dJ2XwXbgk8uncQ>$FPQ;A@$CNpw)&{<44FHr}0KWX~b%r#MFUkb*zlq|hNqp1ArogWQN?^r?l{FH0wvL<7=87%4V;&0a&33j!$Bd` zpk$VcKimy=J zen;*&-8KUXY+xbNi*!2_ykk$xybAPJX_*`3jw{m~D9v5&pzKA`8r;MH`5A9$qL(=6 zM`gM%a2_PBs;qlAHF#sys_n@F9Bu)EwV*=(MD94D9YAqtLSIe}`bCqtsol>7>H(#} ze0SjAkJ|6A*sc2ClY>CHK|hjt;q-F-4 z07kdXxDBa*96|S-Q>oA}UboGSrgvD~wt^U)|DE%km85bJaZ$T)#8xeS+}|FNFj+8{QpyTC1g{{y~29gp1- z(&Y)d2Q~5qjAk-5(Oa|MsU)w-5YfMmNe&jZN80d@(DzD$vy%5pf^)du9Ff|wpU@zu zGb{Mf0d(Af=s(y-?l}E-1WHG$|A12TAhdv3t=0}S7F5lvgMv;_q7&stR;4>}++GLD z>ngVZSjWFg6(0;c7--^WwbRjHRiBBUj+_ugJDasmbZ}^jPIPDX8`a7?M*v2hL9WhJ z=G^3tler5}y0|>hsk5#??Mh3K#kH+K16%;riF#03b$_LN~>?sW{Qhj$EnxM66oNEzDf?Ay{(PwyD^)H9?Y z+!Ku1lNy>Vc=qHBO;%^#Pz_DzSYXuhxl>oJ-Uw`dadu$XNb6-V_rQG|Me1cRG0T{& zmu~G^ftg+)V=pQ{Swro`$=@3&z4h{c=`>Ah^7r;y{@&in-&-d?#Qgr`;KEcKdS-^v zyWLVBgH18KI{O%O5yTm!wYXEIBS<@WAHF+RV2D+N;;WYr#z_HFf@{lv$ghFpphGenvO^)Fp zpbT;{eU{rnlf zIcv0mmA!e@CPfcnw84V2-fh&QtekJSXaP4&e<&KA(<7@?gCXh%Q$#3B?l?pk0+b;N zA}Akk;iq878n_RWSjTdSiF9`3lY`4EFbYF*ex~UygWe-EFY*>QyXE8wy%(^XKfnpk zbG&yv$GhWMnewz=(DR(&9nT3mp0t-wJ4Qo6w?nDktB^ZR?_@E57}dM;4Zz?U%9tRa zW|Fmz`a&HTZ#X`87nlc)m7)?u)IsMUGX|hB=hLfV9A_cpxO>@&JdN&P#<%)pX*|M^sIMpD) zXt-RGkAP+Xj#p zW#uLVr+M9?Y2LKxEsz>|%+Mk-vH2F)qVYf(@4iLTylc@keT#x&NFGo-3%8Ygy4Nk5 z?oEp(fYcLci^$aA1g=FBfils3i>7LA;ZX8Btf71fsx1D=3~! z22SF{oD7u7?!}y8G`;O|r5SoLgIiKpV#S>4jhItFlqpn9GOsp;6O-%}dE331GrbdY zW(qOeQvYDZoaK#}Q$dueR7^6THkA`|8c?RW7ju?(V$Mn-W=A3>=f$(V5pz0-GM$P^ zCW@wWVv_wXGu(?g+dDC5>&2vwHWT>Hq;-;so|#;ovw$*7sgq7^(v#E3`_SskyumG9 zJs%A!=ek{^pAEcb(|XAC&}^=rIY61CtA|egs`c0gxT$BJzMf#1>e=HQq-xSE(6<_% z3ho8Ngg*K_ywG4ZjOi~dbi>fT+!?lWp(S%^E6EUZF4s!3VP>9cL1t-aksF3&M%HZy zWQlh|E^)&%=zj{&llq1)^^WIKH$2JACCEuO@$wy|W!~{z=7uLZT7$agd{EeYs!TF? zozE$A0Z)4eGUQYX|Wk6Y`$;izCuQyoC;^%7D z8_ZNG=YoKFgc`etrbwF9CwT+9LO}e;Aw(TT~Ls~d& z)`x@hTSBmYWOMBs+oE6Qfu~5cz*Ab#tOp_1Qvpf8cReTI2B2)v1muEdo5991-d(pD zI18ivZF=Q{tkhk}@k-7B-w5(-q_UFE??z76O+eY?Ue@hi%evh=S+~29)wy~~Q#Q#N zn?atkc=vl0E=k>2>OLE6B5z%1XMyTRB;`0cD$e zS$BFZ>rU@v-Km!~sFV_b#QTG}S1fiL01KD6wuAiJY1>HOc{|s(9YEQkwT%nF-TDBe z8D=LG*h!g@PVr8T*)E{$QkW@A5HuvUh)ve_Q*GM;RFrt6ymv$S-IO=!2=C^2Cjli% z6O;?YJqB++@qxI5@T$WGWr$z$SCj?E%UjRXVclrZx>;Skw+p zlJ**m%XvZf8f;x7X*PHP&)4%2-g>^CXN?&J?4_sB>KF9)LL>K51&|)!UQPk;0OcLl z^g*ue0q=0ThR9xino*#48{Cp@#(sl0tT~6?2bJxkf{;GVK2DJRK-sTa!g`sWF4Yif zT9IYBSP8CBE4Ajk@Z7tU2g&m9ay$+I<$$X(ngbuu`$g~?_51{9PT{^QC>=CF2Y!P4 zpuyqJr0G=TgCN#HDl$o%2RV`71Il|Yk)fd*Sk)d(Z4W ze?Cz;|OB&{6bO1ux0_gy7e zr5rXmYneZ@;xOmIq$9b8XjoI)5&iE$v4)Ou%mBK1jU6+1aX{19QE1~)+J2I%j&kk) z04N{0+OKzvV+PBtybkzdVpUK)2JDZ~s!1j}##MbBD92q@Q;kr2eF#5%NDGmS@gY~} z1W-=ULauLI!@!zf96oNe{hZsVe%#=MY+lpH4SL8#({O-4InT|?t#^StWpyqE1}D)& z?t}NZW@uPvJD%DZI+`;b=hk-MgdyvpYF-QT%!BcP{C4z1*e?C!6C-gJLm zW3c!;F4dm|^`4}vCqQ|UQ~fERoZ?i^HsFN8ZU#78&R5+~g)+JE1jQZqi-Ei&p5Qhf zz!!A9*3U^g)OV&er+!`n{Ty&+BzPf$J6KRUWpMB-@d<5i;54Z2G*v4B;?ta3KLW}} zN*It8KlbhRQ@WQ8lw2p&=)_)L(dX=*x4T)%i_|bQb!W;8-bjBIBs@!{CyDPYC;d5~oO3Vz z1p{=_G;5Ta3553vHjpkEBvh@Xp8}6hDSv{ApK|;!0p*g$AKn`X{)pv&*%TVcMDiCqO%bY-;0p&AAAo4Zm0Ej$^h=_um>NT~(NyP~lA~45|7iC(KVk`N`E#r}#eu^=Ddw z{Qfgn;ucVDxk|8dUo+?gYO47K%Kt)n6HdQyyl(^Lwq7;u`6_C7Tsq)YbIoAoj`#R) z?VUXGWDc?WRzFIlmc9cb-=WPR!r$SVa~CLg)#gAL*xK-0kLh8&H08xeT4uX{QOO@3r4D2r#b7d%*S{t&&u5kE`-`p!}|@vV*hA;NPK@ z+|<=C-d6bsu>FHp`6s#Ksw9*@byaqPDue${vUXOhz7KzMuP5Cx*z~})_Ag-n7p?jM zx#Oz-8z_J4s_yEH<$vI}e@M9yk=$|R?gQn%QcjuiB`y6K0 zU4G<_tLuM2`5z~v=E`@uS#x!Uk%rfQQ0hO*F$cNhI1)WPP^Bkp=e%Zr^-^j{I4Vm5 zt;0s{*g7Q8nIv*jCt15Inw2E@O`_!j$Q@VC0u+lX8|m~=%?9cvz`6)0Ib88yw`W0$7sX{|&KqFE^$l*&dqhLAgsBUn%JQ>CYx<-+CnROSKIakZ2k z_`qlpd@mQdGldL_RvRUCbD=n9Y+;QcIjclrHM6)5X*4#gJOBBlId1-U~ zp%~1*fGGLN9mkTGFF<3-?B~?>Ml+K_Wb;t)0l;i!Q;%yN$MsBdNWmm)FK1hF0`r`- z;xKZ@RU8PEK&@iZmT-F*w-54PgYgctVd7tI+LuHSZL}Tu+iBeqq4BMSCN!I4s3^q7gNr&eJrBEDS$l&BdC=^oK1rxMh#>ui7e1^e#@=!ocz9P@Z zdcicS{$X-dxBD3i`ml6vMhYj%ZZM6-J4tp{HPlI}x=~FIL)Cb85>8b)OmdPOzBow^ zV@)tll7rO*aT2mTZGrS1G>}Aha&Sc&K}?Vb7`zumQfWv9rBGFNv$Z9_;45DAYtEY6 z2H2Z z*qXdRL7jpXA!(^Ugm9CDq*VqE7HYKiMIDS&L#W-e7w{n&YS003>tLbwhTb?>C^yE@I~XTy zE`!M=Uf5g)TA;!bd}3WOmjSXe4wj3z8F4T-2FtB`3Ve`^Q1e1JGB537RwH*@7gGj` ztaUMA8Hbk02h@DDL=AGsl_0~u{H_vgWAYhH&#Uv6QUNGmfbxEh+;O}M0;QnB+x?WT zC7;3P6ZtVwzElqQ9IW=h3qhrYs6a1}J5C@n)C_Yq)~TMtK!p(kjDcSycU*~ZpoF_h zu<9w`je3ee`685e9dgIP(DZGDii&0|5b+)ebw3l}6DH7LO;EJ#@3@zI=FT@xxAw1???ULo}rTl2{(JT+Sb zoRQYTg|l_I!54F^oUOwRRu_0%>m}>rvBhq4ez-wL4OB!9B+zv$!c(=ir`D%xYkd}g zs=T!|JnEyZ!}YeN5MLCqq$tIihUAXJ88SCiOvM>kZy{54AqnhMwk5)-+ebQxFspaD zIhg@Z;QDG2_S(jFOW?pJ!U(0ferSZ<_*-Qu5o35Z4(mrTv`g+@1nv_gmKgep zANNnvp#z6AF$SB>d7Ozc7!Fw(>y`iumY~*cLGC!~mIO*k#=0KPg0V!>{q^dgU4^Jv zC>={Vzeesj&T&AAOWn13@G0rF50y;ahbW4c0x?Qa5nGWvPQ=ncfoXJl%&g9}d60|s zTCCXA#Y*AYyb9vHcI~*-T$^u1oY$@$=e29crRLfk^u~GZ+HqdGb{Vi>8EV}&@nUf+&7~@e4*LEgo zTRwP9k9k#raaCGrS8~Ty`YceMRVt;&XsGEtD}Ov4nYtkpHq|Jb?&OYRQynPPHQ71K zlr@NX@)>EEn&gh$x0E$_|Ao2*&$qRo-(vs^cG-Lg4y-_9fCvDh4W3gwB*QwFZ9^Cacj3)esMX3uN0Ir1jt zb>wXY*Clzk=G_6;n|bf&{mp&ynZDHAy}upMdLs`2zC=+Z_4g^3}-q zJY3(%H!|NCxGvAPBj0Yg{+REdeE+jK3N$Xzwm=8Cep=v0ftxl*!S@QDEqKA^C^VqZ z_(GFxj<9lJwZiJy9EJS~=PjHcu9XVcEnMH`2=@!m8xDVm$A#Aj2max2gpUjd{^9e& z*N1O{>lfj-!tdA|MP?RRRb(w(zbbO4$Zs}BgkMD72q+g(JL1&{2VCEbm>4kyu16v+ zM0^U@n-TXTpj}0$7hO?wHC*=>JzeyS%~5QAu?@vG+Z@jfe`eYaNWZ9T{CIx(Zx-M~{vk z2iN`4r=y`^;*omm_Kcf;w6h$D_#?>1B*{6J{hiu zi=Qw4iOo^MR-!Nei;aS7jo2o!P2t)-c3A94xXzAU6T2R+H)HR|Li^+9#;uFn2-gqdK8*u^Db=V{ zn^GWGsZFKcE%lzwQ98DC_0rG5^_9}Em+oqFlo?-UewjsZ{jAK*GT={T+m`K9wm)2V zm;IpZhc-v~X5~AV?`CsUC|sd*g>p7We9icm;$MdAl=vm_%i($<{(Afko1;oZm2y=o z!nIMAHdUa$s%@(FuG$Z-`>LL*`mxPXXGxu{b-@4XT(9$coxg03y5;KDstf*6cWm7` zb;1AYo~rvr-LGtpg!~C565`<6En#TF2)OP~IGq4`u9vf3SiK@}tx>N@J!pTuU+Y`y zXR|r#zgz#K`e$v9hF>(i)e!uq(db6A8qJ04y~bG^XSX>TS7}_oaU-}cYP`AeHk+eK zT$372p0_z(YWY&nmwLnX_rz?8Ic$!^Qi(MaUw~`3#G#2$Z{pg-J&F6^`c2}miND(% zO-D7I*>nzEcQ^f@Dd^?poG*vH4D!5E{guYAB-$L!<~Cc`4D{aYV6!vL&f6TXe(~z9 zS3#cU=bC@p{5zYYMc)=a%iJx&e_F0=xu+%6*YeL+ z{;dLSj@Efwmuy`Mt_iJMw{8d5Pg>t>4fbi{*QP+5Fu2}m^KY96Hb>iKZFjfbV{^32 z)-Hd$LN-VHDeYIZ2fyxM?@+8m6kL~d*x4ZouD3g8>F8&3bbPI2?~Y)XPIWuA>eLpl zlRGW%w94jqJ?Zt6uYY87bWZ5px--<*Me35LOFo;UTe)s^yFuJ`>(p&Xx8ZR8v%7zH zkgt1m_iEk2uX_~gQMN|~xHj(5u}5dPUg>eW$FDX=&vQM$@A;$6@rL7#UT^fZIePW! zHNF@4bFbCC-s$x&Tz~0p=?(VlUATAo-j(3`Qt#J$gFp7Z(CM(}_Iq=n%`s^IptFMj zhX&mqoMkYyckt@L?+k|ehJ+8PFr>20F;p0uYiM4$HW}J!D8${+Z9|U^J#KRhj~o8N z@Y--4HhkuAu=9x0BVHU)7q0C`yg6bBTyKq(MrO4+MtwT!r%}Jy9HZxs-ZXlv%`xWe znD55?U~`NOA6sE8@E;dCE_z%ExON;jc-%0XW8%PxQzlNcIVRnnoMke|Gr8R4x|2bl zlZQ^8F?lvz_f0-C8T@6+n^WGNGTr8QJK^otZ-f4)7MNOkDzta%`%^DZ{oLl5)^*y5 zX`^k9=|R(!JUw_)DFd53L|`Qzp5+B7Xv;l-nRJY zV$kD~220v4fqIrUT-ttVC%9f(`t#D;HpjC3%StUP3)hdAU0e3O&9OXb`N`$rZ_95i z|93g~@roNO{#^mrmF-pzTsau7^Hy$Nxy|NS9lSbnb&Soirpub)Yev}|>&mUGyAJfX z?$`Bx>#a7&`iAS|jW);TC7X9{hPc>#e)EmZ(7r7tw$$7Ldfd`#OW!R6;JR$`^T8Ufd3yLRt__}y*WU3hl{TwCt$ zv%5cB5AXhTH{kc~zmsw%1=$=)^^@8rb%5&!Nmr7t+8oI>lV3@0ZiBD5?+M#e1g;nM z{IKUIn`7_dy*u{qwmFVGct7<0JT}MsrQd(?eemP=-+q7P`)h2DqlJ!^Jqq!9wDHl7 zMz^hERt@Y|DLoV&jthk^l)q33uK!&OxtQDL zxY+mNgo~5my6@tdi=fv}u6^>?C-8T0o)Lml z5p@ z81c-agz&U7QyG%TH-(uNxiy3cGlWwGRD3W>C}tK@l`(0#sZ2EuR1_l36jl{j)kL(} z%+(5rMji=sO*1uw;*UajwECry6jpGp>{?Rj2A9UsGHG*Qw1cU zm?4GJLbIY!FC!{XRiNU2Q9^@^Dx@kXv2=zOQtQan6dGk@WwHv*@PcXsf-s>;Mpr7U z*i0cTJE~kFBxVNvvO3N*0&7lOM0h!~C|Omsk{>P#%`%hVs_-OdWIDk$Z@DTo&umI( z6`v`E*Ob3YaAZd1vj)ht4bY6xKxmm+jldcrQ#V30MiHTPW;TXu5GA2i6WV6>#^@W= z{z+&M->8~G$0wyx`i8y!BsEOmxGqmxl;4sX==E>@q?bW#_JU@Cz$Pxl71zz+a3L*crW$sGCcytz*URZ}g#V`(| zIF0lDt){|6bQ<1iSjR!-=p2W0o(N$wI!{XHVI2q+$?PV_c9k$Wd%9SN1>!I3y; z3KOQGGkJC<)}c^Q1`b6O#qP#yAk09&GWILhw@_KB_!b9RtAttTT&X)3>tLubFC2_> zvS)-j=w#kG8S7}MG%p>ED2--J|I+kb#ZkgM^f&MQP4zit-ZxQLfXeetd8z`*{4grd zhoB{j(}Gty3Q8C(EJFYD-Tzb{RDw86Sb|D?I3=ozB*BbIe28FHgIay-Rg4mrp))?b zGqMheicEt;5=F8TD|Lkx=$C2pOV&40nQ8P*y?>4nR-u2U-9K3$MTMH+qeP*~`KOoF z6Gan*HR!75xGL+es8o~OHKognwS;x(vgWz0pMOI*|5=cpgMSZ%9KuGp0*xph|Cyiz zP$f)|zyZ$I%T&(~gxbO;)Um0)#psyuCC8a7()e)wvZcc~01YDo+oUt7<2hf+~OHn4+2#-U&EOS7ECOyU@{9t(bCk zgXAn<(qAFYj%rUgXD8~nkY2fS=Rs{D34NaR$u!@m;`4;R>i4MnboG0pdhG?U2w@L8 zewv*fG^+9N!tq(>NAlTwFEbJv7JTHV1E# z+QMNpNk%Y<-YoBn;UhFvMm801u4v&5nk%E5OEno;;ze^k)>$2IUByDap6h(Cb%SsYW6WE{dG(wR zO9NiXZPQG}FVb z>Vho%P7|(Stg4DJ<@y+7m5o<4>k|{N#H@6R&-tQU8R0vOSyN&)o#%**WLEPmn)Zo` z+mx|;17p`H4t)OYG3Q%VUNwHvyiZ*Gri|eqF@{yYH|3f^Vwki=jbk+N6B)-TWBDhH zWm94}1NEiZ_NeiUW`1JhSs&B$gj*QXYz(CNJ_F@vwJmB~qp6?hxF+V#Mxt3L?L5QP zzY;wmEk?MFL9PaaDc1}b1 zjwXL9;+&Y?U1EnXUj2qa&jv=C?=xs(SKFlqKAQch34CIDD~a-)cm3?2`&noC<=PDY z!8b4}LgFX6Uu-D+jxeBxh$+_$4g;i(DiomUpDHLIrdL0!AcP5jV&Iz+@Ss)7Cldrd z8~kYgr!M%3`RTwPPJ<`OKbP<~V!+dg0W1!n3p|xLKwJQhLZ(0<{4Cr@Ab47VKm`Nk z&G-ev|IihlW>?_cL98r1KzDfB-9dE;@?J2y!&BQ`V8ei}DFo)HUwhr=2RCFPv6u)` zi}*=h<_kIM+`z+LGs&C+>ly03GRbH|moU*Ch#O^Mm+&L#z=DQ44OT zm}o;FK_KxQDQf2x-2^+Yo`4bP>>zl!7=W09nBo~z*iH(%3gU_Zt`JvYIxB$)EC?*d zz`}wHx(k9!D&Rugh3&jt5Q7k75Mxru7#3&HWe{h)z!^Q(Y!X8dYY=O^!x|QE&}|TJ zyu=$l=ClxVA?6_Fc#k^$FT!@f32`Y6xI|ou?i|$Kue3+gquk-p$F1-mxEZ{m z-9`*U#PS-AyfMd9h*&IYp*taJc@rk7Jfm$q`&tY~fI@(JxLGH?-bmLbpVGXi>P+pmqg!GAOC`6dF5}HLo1d+p{w-y(pjZsS%Ny-^{mfGiUPMnSfT3$4 zfSCwj#I@K>-V?+~#4fLK$s0o;cF}-U@eADx@ynaA@$nf2!?w{$(@kPDVi;nWIdc+v zJ*qf{E`~VfBSz_6$kN8|PqpeX6*Iu4bqvz1mX!8*wd#K6N{v$BJjnb3ty?-qtB)AIig<` z;?UjPs^_6y5Z%qKKKU+OX~ejPb})B%hfe3#=~$dYm-DEihjK-9Igk3(b?JT(%Oc!8 zl#jWCIzmI=^XPjj}(y{aP%bUni;^`t(JbVR*W^(m1ZmE_f@ zVPZuDK98Q{DX$vQ(fd;MKB8|G{LuZpQkT~*itgu?J}m?Qorh@L6e}YJdhK9F*r)!6 zPUw{rvN(t?=(Wnca#eIeul1?DW;#r)fUwYiK#kRYB`c~&}&>ek_W_Rk;Xo!vv zrB7`_`&qFj0;J|mY~Fp?d-TYM@0+MRpejeQt-SYA0ZPf;9{zkWa=;&5e$z2gG z)1*%=j~5ebAz*Tz^|1L{Er*_&CeI|cP(c%2GtH{xTpL|8&H7{)v}cI55j!~tQ!(&i zujrs@c2E^RmGMwFu`aqOx@g8353#n;hV9}Iu^zf9tC}?5Ba)heq^cd%9x1x1scOYH zXUs)r_+}YBHBJl@8z7*n!E4GD0oB~dcMkJuH&yH?HbQqb#ZA?b7rLwI?n>;VbyH{30XK7WZdE&}bF}EX=7I!*uDSZufi4TYVk5B` z0neCGtvu>Qt zFQ63pHaz@49Ovg>iGp)4u_b~ttEDvGqgSV^R}*`w0FAC}uIka1&DCcr08Lz3-+4YS zwnltTGbXc&N2gAAr)Du4-Pv6AqdS|cPZlZ+?%j5#Ul7|OSR+_x-kA>8c50^@UD{lL zLBKXwp9Ub!x-+?_r`6gn(TR^HVtd4Dy@Jy8H#+uXb8KQa6|d2)%{2qMwYmEA0k3tK zE%p^VB4(!vqxH&1=YFitt>U(F(oaqCb#!lZ?XH}EtdqnWZ zj^L^dU2a}X?1pZxs>PHmx_O3ib7D_*u!(MNu36B{&DE!VyyN5F+8Nu!#2yIfrU1EW z0rd0?<>@S_qpO>18gzAY^{GNg8m`P4;NlnJ8;I?Q?N8pci{7TL@#!wHH@duDJ!$$I zF+Rg#ylPL)?ZuK}Uvzs_Ev8)2?K7;~6Z>keFT5c3N7pyS<<(v%x_*Xsect`Q7YCyI zqx(PkeSE!**$glULqM;dH2sYkAj4+>)xIPQ$Z4(^0_K_wL%>{ps-4S6aJBl``uXL& z>u3Mm&pOL5*Jk)n^b;z=W_Yq6K1)_{2&M-WE=;*%Y-F0)Aof;M1crgRX2UQrSD%j{ zHL!4}9w07u6Nh0!U^SEGdyIrk6$xxoz)&#PbQlWe>hlpN1riGM0#y+}T{6T*8nr7uPUP zn5)l6m>cwAVIgP4+oS1tqO>>$bA?_(Y5E%jBhv;3vAdctFf7b9BZh^!`b@`sLBb-3 znltLsHSDc^xweXa&N-R@5>2!@8aro_-NSD$+5Nr%7b_yazK zLOxOTfjAy>2j&i(tJ3>`Iu60`Fc(;FIbiD z{%Rh<5HZ)J7$WBC^D*TSeJ)ujPR3mF(0Rk15iwAnm_T9k35JQeX2mcuSD)^nC>?3+ z_++8@Hs%z}DLBVvV zFkH+vFNTY``pf|Ng@g;AV`gBEd8l0C$(R^4Ph`-rc?LtqToYr+n5$1u(DWGSY_54- zoQ1gta}CawdFumYT%&y9(IL*k(D7DnUOk67=ZVcZs{LKz^O-mg!$(z%DOU`iCq8_L zpQtly7(V8j8^gz3eLjYfjW;l=9s5{AT!0D48;yDW3`WpX5kYJc!VogoNA5T zAreArA`%9Oi!c#+on*YRC`Qp!6Gdz?!Z0$|>=;Jo>eCzOdW_E~>q6V;IRSr&OE4#4 zPQrDewD^EJQ-`5sE{lYh4#oMhu)i6*Ie;xbH9-fGaR z=Pw# zq|DW)w@{V=o?~;>GI15=D$G?l>1UP?sN*UOD|7J`^Od>!%m8`Fmyly~)*x{W<}6>7 zm+G?^Tu*gy5&uy07KWC&u7IIsu0Ata-XfvJ=B_j1I?P?E<|AK>i~;u42N;{bFucrl z2MjNB_2~<=WuRx>ZpN4`Zop)Q$qXkCP4xk1)T;wB3^8*77!#Vg`piH{%GWSt2WHE} zO_OP%~GbI=3|y7SoA0pWC)!ZZp-07;qSHZUR}&Zy0Xox(9}vx%zbDx~9ToI`L<7 z+!=8P<~UQ0h(U)z=OK{QJcl7?u8UyEnX69^?rSPcrc)hmH7cVW^q)tVTA7=Z>6 zO%k8-d6PzB5{4dz9`5Hd)dvhhkJO{~J2CXkMQO}>=IS#QH%`xxF{>_iu4RU}2XmiU ziluxo05Jf)01a37^Pcz)h9HI@c0Wz^0WU(3)aMGrq2hiFLsLzFnGiFfmtm-e;se2k zVQ6wDz%axx^dSthkt_)3k6X7f=Z{wu4`6b{OPa!t4^6>D4GlCm>|v7 zXC@6VUm!;NqTyQcJxq+gXfD-fF&Z%%9|A$tLdK7Q z`NQ_jF-@9kPmD{9OCMrdjZ5N#YO2JLG}nbNB+b>Q5AJO$ zw5C(NY)EEhW_J3~$(^n^xr38CnbEDE6q)Jd&Ij0QHPxP&A~8k!kX}iOB>y8msP4STl3a#l>uM&`MCwY2`$1z=+YEz6&j7=ZnnvG30Wh$p}M2RObG%++y z9#Q+?nx^VL6V|H_O*K5pyIB~T=At}iO>^~`3B%17xN#Sn7C&1*veOQ>*@->HQ{Z#>F7T zAoT$ZJOwG6M=?arbtw!{bM@(iyPFEN=~S;#h-M@EgLLPIhzG?pm{d)*G)62&tPjy{ z6tQe##V|G3tuRc@)u#_GZz|lTQ@yE$X%>=2$;n*X=+4_6;yFyKrrH_f730;1SWhip z+0=@mYOZTxsG6%!AKczl$W5nuy$MxadTk_L!1QXWtubaXW_^fvZ(^2Bu^6uAx)+A4 zx%%|M^-YD{bgI|eaMh*RVd5v4W=*v>#x2IJ4>9j;+_I?_L)Kgu!;m#spFX(1snDBF z_4*RB@Hq#GP8TPNmoU+qYHf^Kj9MQe-j}FllP!j=xo(DGYpy!H=XMBHEb;; z%Q}~6$BLg}&NbEO7`zy~J_Nq6!OP}d3|(_w4MW#lefkgvrb2K!)%!4^o7I_n;lmTo z417`i95b+~=EpF`F!lig9wv;{EUcUfvq8LyA&eo6XTq531L+XLY8aEVV=#ox%^H}6 z&DEz5;qbV^FfH{yY!)VUvJ+ax#IGg6Ao~D5X$fTFd+O=L7{=zh9fq;F z`t%_rQb1}ZD4W(W);3WpUs(N5{07sqseXX*jPdLPj-)l7)zqw>f_x3b8N(T8yiE0h zbPi`Vq{-|ThO@cZ1hccb`t%_*9#=@FrCu|#GpV1Rw(MV;Zl`V_eup_aEk;RE7K0jt z+6N#qE2xPdsJ1px7}Y+YiJ4K& zCTk39bKMZb+FX755F)0+b2`;)c39KTFu=xb_>_^*Nc<6Vwy92m!HvP~12C8!+-%;) z&^FfU662 zQHFRH`k5#=1Vx=rzm4hKR3E`u$5{6PCmv<2vnd_J++4TBFgI79K7@>^aGg%|KI$;n zrS&7?T}5<)ueA!4=7fL&)?EEXy9k89m-!a*z#d;~qV)SG5`+!*K75&6d z)z?oksJ;lE<`J3uJhysWLJ|IYXqX63hz|c3>RWbC<)u#_(WGaNG zQ@xKP^xbv>ii`KL6JV+bArc@G_<$mh0}0fQfU?b}wfH}T0E7VC=3}Z4WC93KVSsG? zK?pE6Yhf?ITz&cwPLC^$(^Bu_>ID#)v-#QjrPvNsOMHNxg0xsPMOj1yL~SIj z@m+O`5W;}DZi_Hru0DMTsT7c$3Ccch7@*%`hP}e%klbdHh><1`z@g z!UsRfNC-iE+PNT!uz(#0j}YgBdn1pB^P`Lg3;Y6Q4(v0S>e$$4z&?WypqkOZf$cXS zG??qk2o2`y(}yrK72?yW-i!zh9u_cd*oiRJ!w@MDDSSYgjEEF!M?zW9d{GKOh(L&V zxB;}Odh;Qyo}_v+DnzI-K^8a>BFxQt*o!b%pHDb+WMqiQLV6GIpFNtsSJ7Px#O{Qt z=?Sp{vBC#@%g9)vb}5vR#~V@*LIpwvjyz2DfhPzmRJb4`5QGYIvmo{=%+;q4VfVPg zJuUTS^j-yN8y$v_ce~$}La<|z7Hg*{i)evp;RC{D2DBhPu5QCbxG>kf5iZQtrw^f* z0=hFn*~|hLOa~(ub}&r!G(-$U3?GmxvmgfB$w0_3*ToSs%+;q4;b$uJr&GO|2{M?D zMjq^FnCfka8i*P`AWmjN4Ysp^uwky7BW#$fPai_iRQOM)dNUhrI6EBov$wi0e)>Qt zEXmmIFxBr6KM+5Bz@E&8A8gkHp~GBPN9ZtDpFV`4sVN|x>dlPMq0M&`lk#K7!&I+B z^g#6R0eLbbda#`jgb#Dw9pS@VefkiJrlx^(syDO32R(SpdYQh#)<`OdeGpTf4?zS$ z#0LP%tRTYnLl8pDb$NskbM@&%IGUOY(y89e3?Xb^WULg1eGyX~5P<}N#0L<{%s|5S zM-WELb$f&nbM@&%NSc}s(y89e4kOG0O*nQ)O!YuS5=0UoP$;t_3EL?_C^6Ud5lYO} zrw?IiYD!3_dY=R+VJAx(NfFpLG1UL{LFc@d1#Y6i`w7DfB31alaIau!69HM=6`?15YWe=%FPV zp~Y0U!X69uSe{~N;owD>D-}n0L3qKQi>W^Fl*5Y(G33J$2ruSlTkO4IN& zTIzk0=37`jSp97M{Bqv)vw!Yqo#mHnGyEs|2^HZDLh=%!cup#b-5OS3X}(9?LEP~H zE1y){A#tRBwgMr>+>k(sF;|~Hgln49!(*uHNro8X?v2nuio@=WsXmL?gV^H(hCRvH zqjqtWuLRGPN+Z-D)ZhfMsXl;E!=)Q_M1@epsU^)WhrJqe_31;{rrCCnp{^&rS3_)K zJhFm`m~FMT8xM9h_V?)dvuEJfbwX-2tqyp*wYF^YClL>caN8ioGFo_31-Mdu5*t#_wtF4H0{J+7%5)ijh;q3P?4vn`EkABR(NM z`GA2>J3f)vQ@ctCMdpSMLXo-p^dYQGO)2SAFG5i&-KAV71;KBn_yZ^^yO3MRAw&zq zg~P%~Q4mIn)rHYwXJL#uLl`UW6UK?xgtsJr*bP};m>{(hCQ9RlNz!&WX&(k&DvdGVRI1#i!I2m+VI2D{nI2~MH_$YXa@Nw{I z;Y^6Xa3v%_xDe7_xEL}AuI~w-gjN%tAWwD5yG zT=-G`OSqY@i||vvYr@a@Ulnc@s3qJfxLdee=ndi5uvp=@!lH05Toir}?;`vWeopwa z$Q0qPBA*F=N7NMliP$d+MJtO^(VC*AXj?H$(TQTtqDf+4(SOC@Vl%|hX9kM7BFl=o zBPWV^B9p|tk^hQv)bnEgsJF!eQJ2Jm(cxmD=x$4XL?bb}#9T3^#Mff+l96Iu$?jt5lH0{Hu>oSa*vex0*p6bw z*lS{?xIi&JZkkvnZogP9?hmngsW`Dlsk&n8QcJ|PrK7}lW$KCT%f*Tv%QX~VFV|n} zT)v6erTiSRYlR@OcLiDOQ=yjFx59dHV1={dn-zW*2UW~24z5^K98$4{IJDwx;;@Q? z#Nid^iX$pz7e`iFEsm;OLmXYXr8uVYU~z2adE&Ur2gHGuABYp;D~S{1M~IW+kBL*N z$l|oBe&Y116~q};UlC_M+ee)B>OYGMYFfmF&%GcndTx%m__^=JCC^tB zmp(s1Tvn^5xZ=f=;>z0j#Z|Sti>vF*6W7)GQe0m*R@_i`xVWkA2jb?0T;i65j^fsY zByoGa?BdRP>%?94J{I@Z`&m3zzpQw?{#NlsgYx3Z2J^*J4epDl8#=^~8-6ODX*5(k z-{=?dLgVt{r6$qhm6v`Jzes#Wyqefn{4#N|_*LR1@$06+;Ox4e>$C+mh63rIe+0pp>okY00n6L@9fl zOOmbaA5zZt^(1@yu~Ja`^HOk!8B$2cL@9U2Z=^h(YD#%Kot5O*2T1u|UnAx3>@OAW z93U0!d|E2h`7B)jkqUL$DTQ^dE*0w91+Md?!d(}^^#iGJx1v&!Za1We?i;0|J#tFL zdgPX(dVVNH_bMmF^y(^=?Df4A+xrJ8u1_1ORG-UInLgK~vVDG$%JnTOmGAqyRIzW8 zRH^TEDZYQGRJH#ssapT*QuP7lr5Xd?lAasbQmQp@r1avzb5iX$8%uTGTp=Y4ijW!% zdQoaPXpq!s&}OO0;8s%8!9Pl`49Oui8?sMoKD3t9V(2Q#F-(+N4hxrB5BoxDGwgxX zZg`~BVR(P3N)CTsn_VKQtvShr9NXml=_a9rG8_( zN(08Ol?IOUmj;b%EDatvM;bEjTe$y68upf58vfR5X~g(oY2<{w(x?ezq|p--rC}4h zNn)f_)* z&77Ii+By5Bb#p$K*3S!&Hq5UsZJK{l+C2ZJv}J)^+P2_bY5T&?(vC%;(#}PPq}_|_ zNy&>BOM8~olJ+irQF>?TY-#^8Kk40Nfzp9xEv19YUyu&3cttw0Vt{mPWee%}s`sT2 zS6ieLtFK8X*F;FC)@+r|tgSDdU)w-BxAvZNe%%D=+`668h4m|?^Xtz@mo}7=E^q8F zUD~)(y0R&s^!cVl>FVY=(pOswOW$s-E?wK!Li%>wV(Gi>#ibv&mz8dAuOj`t{R`>V zjz-ciJB~=Vcbt^&?0i){h3rAcgl5O8Wi{JiHmhA5?w&Xal*5ZF)t0myzbxY3oj#vT@y+618Glj{L(BG3xT<$*Q{ zXa(f?K${G-FnKi4rU0#wd;(~111((M1+=L^E1WMFXw!feA^!`s=|C%z?|Goj09vtp zC4n{*Xhrjl0op8}Mds@PwAny=Cf{zL%>i0;zNJ8$3$&gTL!eUh57+) zInc_4)dAWHpp_3R1GJSuD_1x_&{hGhV&SYnTMe`dh3f-t4bUnVt^l;PK&uo^o?8dB zD&ge0^+1acC+*z;v}eOfdp82DYB*`{CZJUhC+*z~v})m-fVKr_HN)osZ7a}fgx>+$ zHlRHpeg$aTf%aUHwLseev|2@`18pbJUMTV#&~^c>c9E+<+YPiABZw?XK&u-;WJv~E zod^fe_5iJ3L@l801zJMH6rjBWv<49afVK~4^&>t7+J2xliZ}$ccY)S0g80S(pf!mg zzHty}jf<`Z+Iv7tEIJivhk*7{(KA3h478Vvz5}!)KxXM541One*&}{KpRs0J)r#nw8169fc7KM zhLy+xw3|R1TA~ZkegfKv5{W?j8EC^xYzNvcpp7cA5NN*uZDfgmfOZ>bV@g~H+8v;c zE=gkMF3`r6Br)?V(8iWL1+?FQHojyM(Cz{4t=K4_{SLH=vB5z5185Usn*!}mpiPdg z2DHC`HYs)_(EbM6+p%4N_7Bje#I6V0eV|Q?oe8vmfi^Xk_}~A4HY1k!-+w@x9=8!_ z4}dl+Znh8}DgbR}9N=!K2(&qIfV-g*&}Nqc-G^F$Hm?-uJ~Ru^=9YR7Xjy@_pwtGS zWdqv$($4|S4`_=@mjGIJpe-!j6=*qtwxo1Zpjm;oxXdD;*?_jJ%s8O=18r#;!12%k zpsgqaI3Ai4Xv@p?2U;M|R+ViHG&|5%mi-WDK|otmb|=t+fwsEbZ6Q*4S9o4nSMG12 zpm0DKAgnKM5kiE6aJQj+Hz*MTB{r3R8A^mgiH#M?0WBBMwp1ttwA?`39RD)V@&IjH ze08AZ1=`m5q_DOy{#l?^ z0osN7`+!yzXy+ROQinbZv`-oWQioOp+Qmk5fmR)8ml}-(S`DCm+BiGVY69)EM!y2> zIiOu`+z4pT1MTz1m4WsG(5^Jz2DDm0yV`gG&|U=E7fqfAT5X_x)ubfQ>HzJ_mwE%O zF3`St$pN$kpnaW~18DVtcI~C#fL0%9-zL5Qv<5)?E-@Bp4S{w&k?5)s&~79WT{Q;U z_lf&})&yujCawnBOF;V}@pqsl0_~^7uYlGRXg8bA0ouzzyVZ0A&|U%B&rOMEHv`)3 zro^*f1==q!6FoNv+TE9lo?8Iz&MS#Pa{%qPSDpphYe4(88ANhuOQ8MUj6`xPpxtYB z{{M~I2Y3|aqKEOBO?EcPZn8r1}@~$ja=IoLo>nHQ=>Xr4Exw_nz#mTJj z=Vb9R|L`!`0GVHSciBLhJNzZtAXz~84OxOLF#NP^u*?%tOg2R3jqs5Tl?6pSmJO4I zM0_h7E(`9qLzXDZ(`|t)Nfz3@sBDDH?(UF{l!f(JAxoC!>oHz7N|raWoGe9FAkrfn zEz2LdO*TeWC~}@GRaP*{B^xU%5_w(rj;wIhAlW!sv8eX4@v@@P-DDGFC8C?jCd!IO zFPEjsN=1*8O_G)Dd0aMGR;K3`*%VpnUd+o>*)zSEmvmX#-UVgTWaWE3l1-PDi)kgB zA*&ekoNT77Ld;0nEZMU$-DR_7mHM(Cb7WOwSdY1~%6;{1I&7Zo`Mzaj^JUM)){rfb zy%1Yawoq0zwwG*?ta@xKS%$1y?60!LvYN4<$d<@z^t&osDy!Y^xNMoMR{w#r<+8f{ z+sRhQ>cmZyt(4V|>nB?!s~5Lhwp!LOZi#G-tUzt7JQ5uMM6k+bMf>@I~1!+3SN3$ljH;8FEMVp6tybU&?mN-WWPW zwnz5%&`z@VWp52TE88n;H*AOO16kYQys!4jIt=4|wO`hLIP-Eq)@eBNa!}SWv9|1x ztV?1M*@v>uN%>_T$-)yK$Uc^JP3kQ>EbErkT6RPhk@S)5sH{iQdf72q_mMBlj?1D( zR+OEPMUI>$J1Ofqa+vItEIPS`?6jSU< zvc4%dWuMCWr<{>}ChIqPqwI58{OIYjFJy6JuE;LP297x<`%*R_mDl@~EFqQG`?YM) z*h;dCvLR!GWtU`w$BvMFBO5lho9wb|=!B`VZ)J%S2FkvZ4Nqg9zn6`e$UOfbOG@K9 z`camg#&vW>HZpCd?5Zp!ZK&*;Y*gAA*>%~NwC%E=WTPjg%WlZVP8uY;DNCKq_4~7I z++?obTe5ei@V@#*Hem|yt6yc~r(BTTmZeSEEBj40aq4K<@3P5Lqh)`{CZ(5`{VAK8 z9w@sbo05J?c2_nnJzI89mOibi?7nQqv~scsvgy+@We;Vurlrds$!1QUE_*DSGkvg8 z(KckWXXyQGo3eQ`^nSJ-vbi($I&2@=f|+_9wy$jdtSFgNwrExhnI&5|+h69AEuM8l z<|oUTt+}`TWlLvk?(G2Ck~wu{ZrSoV#bh4YvN`)?fwGlzR?328E9Need1b5TrpSV2 ztL8P3g~-;}Q!vV5{l3(Cs!%Qi05 z=Ym~8wq>C{7wm$v%?o2>g=AR^Uy~J7Xem}%c5vBnSryqw%eu;*lYO{s zlk9of;bk*qRb?Nqs33bmc63FMteWh|$`o03+3}T8vKq2ut95-w;3$xf^Z zkkyu*UVT$mM|Nrrb5K`yb`5h-Pj+U_Em?ip`8DTc4P@umwvjcIeY&=qtdZ=Kwcp4Z z%RXOwNY+I5*}DC*7iAaLt&%mBeX)M1teNbq^_^ue$-Z2_PWH0w;`%AF=CZFd_1SH= zkbRS>&u;q_*`-Y0FD+%?X7YY%CA+*q*Noj-_WcH3Gxn>p?=}pUy(ar{Lq}N~*$*3Z z?c1-*u5Qq^Z@(eCvN2rtrtJF07iDkBu5Fwqds}v6V}h)$?5Ba!Ws`ok+Z|=MHXoFAlHK0CM%G#O>z10bF0$XZ6q0q7{kDbI8!r2E3$Hgq z_Q%#TvTm}wTm5C-Wp}oAk@b+>-`ZFfDZ97zuq;aUaO(zHwCq7vAz4q^^UvNR8zA%B79txcb7%i98zc+Z7AZ@R1#W9D8!Yo|`${%M=H0eWHdGe0y@PC+ zEM$9q*>G9#j*_xOS)Lu1EJ+r+l{nLSxn=CD4?>?yL+M}Ct{l|6IhGg-Q<>@nUi z(`4n3@qU>uD|ejt-wavBI_J`4D`oZ1^_Q)Z)jP+vwOZEj9M{$wS%dTUWou=P z&tH_SlQlAoPy1Q}tbv9RT)>^ro!@ZSAL}>9&GoO)KDrI4P^i*QJA0?SeY3V4{7%`h z4E+k(tir!r8^!;7RKR4;p#KE~TrHs51{{(d{!i=Lym8=_?wQbdSoK=_-1l=XG0Ex7Bo8UAHxj z+D086U(aY@G&Bm>Cv-oD;cuVRty}v8^vA8gCfKJ8!?(Rr!~DQ7&0X$thMzmHyO6tx zyQsUEyM+D}$+3FwhVDjBtP!T8Z@GVYV!y~N_wVjI`g1quzB$KueExlm$Mw`P?p%)X z{^J;(*OUJr+j?wI@m%gx`l(~e<#J5rr;e%XssHzD&?x6Q2X+4U{emL?c|UjFpoc+^ z|Gu9_IrsBE>#h8^X{7n^R`pi*R{fv(aM$xT_qKR)ObhPk&g<>!jd)@ae_1bY?GG*4&)J-61Om+aGq5i-{_d{R9vJ*`ZB z@S1`C0h7$YP5vUd1!c|FRj_B(RnlSW^i|leuTP$C&O+_ej&dpV0wwh|S}S zPH@OsM(5n;O;2-cu^F&4V3+Bcq|7T1sY}{>%L(YCPhe5{lB2h;*3g=lB5(VP0FyhETd-_m19(% zR3H^eCGsq(Osa6)bL4qa6?=hHBh^U_Qj^powMiXPmwVJB^+^NLkTfEVNfYuS2R9|n z$V=p9(wwv)uaIDCgkiR1)QYqwuaehD8&35)qc_N#mWnY<4Fd z*z7_w$tN6ggq$Fsk<;urN6wPH*l{wI93>~o2jmzzMb2<=Yk$iyUiQ;7UFg5aFcx5Q z*n5F|shED)V=|rGCl3_Up;+^+bi>N978}-7MzhIrOW)0gaNH`gj#I5CSJ?cXEF;Uw z7_x-D`$z^kOj6nLrhkZG?DxNH7?0TejvbNyRSYAVT*a!Ulw;5d`$!x}wZ1N+voy=x)3R$d8)5R!>9AfW>IvReR70xNUZgka!*MaBFNwwak^Ur(#FGJJAQ?mw$YAaP0g59pqXaUXB$HG! zj!Yuc$ZRr?WGIdTjFyrWWHnhwHjvFEi)<&m$oq<;Frx$HLvoayBIn5$aafI3RWp;g;UEk4UESab{Dl(c((#Z@mmnPM(G{=cKh6H6Tp3 zv#H{!!{}x53TaK+5a!<5mUJMUNjT}QIO;QsBCLWlmc$WO!O1E(M-W!Q$$Q+HvkFZZ zu?o)VWDc2677e7 zMX^{Ei$$?m6pKZ%YAEJS#nFzj(?wV4)l=l;eHHWD*^$mV?!D9405oX>yLRJdUr)w}eG;ILLL9GflrR`i*=5=OXid$|?>Iqw=H@sY0p}t}UN>q#GWRPj`oA=t%S@FE5yLc% z9aFdROSwXOYra^{Ef%wd*5TZ2c53ZxX?nSkix@%ENEGsuQXPLIM#wZ8Y@N~E!g78w zmtI;cPL1Z4a^;8-F^z5Oi#oJ4l`UjVW9P6WS{HLOh1^uRb&S|!`PpK&yu6s}HI2~Z zS~<659uJ4j=CiZezP>;tVJ4G-P&D#E%8xUDe|~c?6bZ<2?|=Ubt9K_GOg1EMgq0iJ>W#Q^W8Av2 zA4Ny1_y&qjuBrSQm){VOB_#I)Dv_PU51bGrukv@f{Dz?0gvcIghq@@)t@59A`Qs}8 zkjr0F`6-v*P@&jA;_|yyeviu^SNX?W{+i0~bNLO{+@m3moOJo!D*v?0A6NM!E`Lqs zkGlMZuu}g^F27slUv>H87Jod9`rKfCEA_uBKk3RhL=^ioF2CF2OFOq+JL4+9=(XyHYlzv5_b9BDnIV>$5non%U@IZH7>t_ zU6!0;kvf;(t@0aP{GIc9{w|l_z%GvM?{WFvD*s8BKd$l*x%@Si&#qF=Bg<8? zeRh>Rzu5ILpIxQoTdtD%>?$SSa+M7d4}DxN;mUHAEPv9iPdB?t=AU-?<0_wBE8AE3 z>{=z?a;V8LoA7z)`2Y$EZ(PjOk?9r)z zx-Ey!e0J!PZ~1fPvp<)7%b&|~qwLSwKKpIv*YSL$a=R@)`MqePGf%t6RlfB9eQaOl zOaIS&)&ECb|KDxFO_fkQ{vnHRNArpskG1jv3n?vdb58#F+%c+UyHi_vD@~K(vIaHWqmAp$+!HY ztdGjK{G+UoT>TmF&wwttj%EdMC&E1_i6^^e`Ee~h~RvD@~Kaz0!Bk^G1ida}Q8{bRT4AET~+ z?6&=*tdHd%W&IWZ7U)t zs!z=FkEl=D_K%Wp`A6cb{xRnI$F%AnW3GQpTk)=}f6VodY1Kc*T>qH1{i7_`@{d&R zn&M|;mVYF^?H{GQmSo=mb|oY`A2Erifbj`@{h9qD&O*t#JByUl(+mN@ooPo`Idi__LaCc=K9C9 z?H>szG0Q*7{!!xN*bQerOWX0Wv_I+c?f6*oXI#D&AMd9vV(hl$_hXBgw&G*v7hS#; zAMd9vYiyDE*vh6G6h9oh%l2jetNdqOz8W9L?z?=|pT}H(p0@qD><7!AOZ%38mVC>f z%l=XMmOm%H8Xw0je@=YcpG!NIKbQ8EcsJJQ#6xK{K922l`D%O|WB*TaLt6F!G1vd6 zZT~OJwfsNHk1Oj%%<})lUsL&(|CjbHzb)-p{-5~WD&O+|(!R>K{J*rX@-6=_?JIF@ z%<})zzRI`!zqGIT`Izhf(`zc<_Wz-w{evTC+j3{B?wve%H8np}ckf8$&dx-raz}O6 zY@ZpdGLusQv!beUcj|m37K%L9(9mBItf;A6&IbDW;*s`zbGA90h*eG`tNYBz+R(j~ zs-2I=LzQ#Y*}hbMY~;XT@oXp*Io=R^B3-f2Uv<5H?rJ;i&s9UeHgc{y+kBxbcPDjV zFRnL7`pv#PTf}u(={o z5e`*X7q2IRk=h!RS6eaKkW8LOC*nFC*xWO7c2D{8!Rzg%{Il_7^R=$#=IVy->Fm~c ztny-ebqG<=rSf3q_4e4-%3OOgE^}w&d(4FF$4%FJZ=OvZ=-PCxZDwI~c(&>W%IOWD zoT`eOyPK2MXZxyA{Bp6W6Z%^ZyZUig|JatUgIC+~{i&8{Uw>amq`s!IdY4&oJ!JM_ zoNk_(Y}q!_)O&MwR18)%g%Xi#jpGB!bSO~y^cM3($LyW^XCkv#Qnx2YTCVh``?|UQ zJE;DLQUB0WdzJ<_1;Z83Rvvt!p}F6TWa0~ftL@Xr_f(V*Z0{=P@AvLISP8q&ckMP; z01sq$Tle(w8(Zol&<|8u`knFWit9ahkN4c09ck#CA3SvLWbt}3cl@dtJhZ+2=Cxht zljqO(?Fm)vj%Bk=f!1WxmD0AZ`HA@SN^$(i&GBPmaBf@ga8bFAm^>hKQKZ~Jzq-PuTI`Of{Nm64{@T&C*!in!i2IduQb z?8uF_<^G-b_E39k-1?@q^{o+ut>bMg{i)%>O32qen*2=e^u4`gztNV@#G5y;kNTWw zo^0M%F&v8wAqU$P9M5*P-e@ajdbSJ}ucr#fQ}^mCueRm-M+NoAdAmR6LrFRQV|~w_ zJU7vC>s;NI)dSa)%Y(b_ouvBivCHp_HwS4vN2f2Bt{h!D-X|`XCfaZ2Fb>t1>~W|M zbW|VcM8D77xgXqCHPJpd)-ya?M7d)l0{u<+?l@xMb8T-rJ~w;mp1<5nRVX**mYWU| z4*CixxAXRFc)GsW*flf6<9f|*$MsNyY)3wIU{zdgpSrX2-jPi=l5^u!zbkJ2l1}~F z2M^uo$sbQ0sGqymHa}6v<9W<2w_3Kh=D^;AHxA!CTUYMH{K-}CZ-~uhYx@JWq2$7d zxoIeVbfqxfnFD@L9c<{G#QpvD{p7G&HB{HMa$tMI&9N#mJGYJ6zq`|&pD~)Bbya8E zZV!eJuMA&pxH&|)zG~OEDX^RBd!-|Jd{0yT*{f~KOMM4cL?dweM3aTnx!SZdkJ_is zR5kJar|kO^_35BJ&r(a-OV!EhrdTA>*%T`^_f&-{m&s4gNBU#w=AFH_$M-ZRlM{WV z(AH#K<@Jsn&GS<8QONDy*O%_Q8{9E8TWsjOJ5)EE&SsBR+>U3@S2i`?95{V1T-x4y zGmrWwGj9DKv+EzPScM!uL+jji-voM_RU3Hg(?Y z?-`Ev1^eSJKG9E^-kU>v4zCt=_RLJ6oP~b3oOTD7@wXwAh;=r& z;~l2)eB#uh8*Q`Wmztu*ZJqNa%-h1w6zcVyQm;zK|6_h1IkdfV4mjObb)$XiIQls- z8MFKGQ1GJc$K~-$_hu@u_mMN?phJ%9F;J2&m@A^(tGaPHR!tob#SeXe~Q%~x)Jy<7jM z_ea`p$oX|;ZlZTCf4`sV*Jjl(G#N@~&rY<@9Iu-0JQNOurqhUnBK_^P)y>_r&9Pvj z5;zz?0$d%m;)>?jUNby7h&ZJ6YTNYqA?mLtySzieWW!(){&cQx%f8m_?K9}FhFeyD z!5?n6{b6oIln*p^aeL0$?RDCdJbt=q-|Ut461V3u+djs_#zSpaE8)Qn{2*`yKiE&}&%}}CY`===&*DqQRPB(2sJ)g~no4QKd+9&hyKUl9rE%y4AiJKKx z`~_UMACC`5TgQ9K$2lI6^XQI?<4tzImBKB9XD8a0(68h6eTc-JR7t z165~Iz=@Q*j(YV1=N;Di+`M)$9W35S-3zy3UX1o7lgaCS3$eWwh`W12m-aNL7q0a! zhdShbN6K02Um9{UE;V;`1rpW6vuH2y@?509udf*CZ;5RR1uJgVRBj6d`j;YOTh8xl z>})??BjpPD`%lpPTz1==O&{ET^rkf~s{@$-=Wp0}sAvDMt^M}g{q6N!oHofo^DILwrB$VrNeGmVEkTN{BtvUAfdXS?)6sWSZAm9y97 zyvxtK^SXxcBmMA=1GB{|y`?D{w|?vcoP9=2#%JVb4>WW=d;C(lUe;slR(ri#+spMh zGPk4WW)3*5Y?S`)Jf0n};{5u6TaR9<2XMMSkNuV%kGbms*15_?UcYwj3b{B-JL|#S zb35d`p*TKVXZz#Mcv{ANRZaV7-S1CLBYx{zKHhkk+EeMar`m}(DZZOSTv~ON>odvq zIlpkil=TriI}yK%&be#t%g0Y2*wwr%RvoL{aV0qr3MI}o44pHhGvlWz{!T6&@3U~Y zb$7}cpLA4R$HS#@E@#Tu?gLog&+HV4V>(K+@ISkDIqPUwaLC-(3V$|u41W1)YWa9i z1>z;dFdzB)e`eyn!_Us^_>Ox7CrWL0sO1b(7;g^y72xzCA7X?crAVakRTr z#x;&yrLsR4G_EXntm#x~;_1@h{q3h(8#?ExezU&%4PWmn4W#Y?M{RSNaLY>JhHS^U zEr<1Q8`W>UTrxL=cyE`wPV;)S(0{4v${gW*^Z?g&<-&4HOi9C>~4qk7cynOQ6xv=orQlHZ z^1<;VspES@*^aMAnyLd&BxzrUeG}qVxsSuX`;Zx*I}^TMKTGSM6=#q2RMckE9m(9K z>hsk#$S0jUFup$+3|Cd{-q(DheJ=N0?G@le;zZ=Pi+oXrdP!c zGqeD|yW6Z-J3e}^ZsfWd#Wmp&_p9ao9N%BE@8jCK-weDZf{C%mH38Nj+8h$qcVTP|3Q@*ArIks;*E%;3`Tnu^+V0Dh0! zo36k$>Vy7>Ol%p%{nY`w--q_s+&gkG90;GHywya14)bw*4)gIbnvYjfbNwStRvaQ0 znlb-|?r)FmHlwu9qPS^#oa2VTV~A&D+*>tWPwOb^mE8sT+{l)4p`mkfb_DfGv)(yZ zuQ}K~ggB|EJcW3saz}3-am51bi8A)z3wg>P44IoSesY~2s;fAK{8cXaH0$LYJ&Z?R zYVz8B^5LR)u4v2Hdc#t!6LF|LKG(5|d`U}n%-j}sZW9)}nA zG@r-5bJ@y2^86T27A=1oh*gTqRYPW6+TYo8J6|W7C+R-#hnj-}4fO}Fx80t&dT&oF z<@w}#iE({F1;({1e7kC3OL~CnDf2(HA3(ftbaFfpZ=NDM99Oyga6=09zd00!pW4Y5rq*3?P+w*DGxpBHY{^8@jPEZN7p-D-xW`;VZ0<42o=4OV@_ z-PBLWUscpLOI%c3={HXZ#5oNEyCU&e!(8&bX~j7d5AymFsKmI7#_s0eZW@pF1-2ii z_%u@5)-zcO#M9Pzwj6w{8#oZ>z1J1B$P3CieQ^Bg1>kL4v-di>8@L%y9auTo(20B; z+IzisIhYc>hAw|UI!ja-|O6TqvzR)Dl3nJ`4Rv=Wqy*z zDV#MCA3A;{9Xel4>(&_ZBiL62>ZyGb9Sdh@9T+k<1BaYHwDN;PVY3GE5+}n}ei3-B z<-B2MZg%wE9&R_`KQ84&Q#Gg8wAh*Nzt0yhL z8eU5ux|%FZJ$D9vRmMByC;Wak@R+S<`(rsCvV8K-%V#hit>eArGjjdvok@rCSWiE@NC` z6n~V)kuMAnNgNGgeFAPG#6Nc}8Q4U4+Hqtu9qN|%5g%$j(*5VpR$YG@ zeyUl|$9h2P$3?`qS@JJWB7edCb+;A!_Z;`vD)wJ{HVv7A`fL75YIz*&lof)UI0lx}N=qJRidT&FYsMTUIRjdg)KxYv7XY+40?>wD%hIszmvFto`sM ztS42TYs{zZ7$@Y(*e@dvlN{`X`BR@giGK2*Td-fly4lcq4*P5LS6wUC16nsHW&VoxP2G3NF9MI1lvlz!I-RLO zzW1tG<+(<@(9m(fXTUG~Phh+Ex*2(rdYn^Gd^t#Y>tKiXIvrYAkom>?+o?X( zuKMhWqf29>m`79}TF)A)1I_3!Uw&&_^8opM#I-v+mycK7+e_`id^hbpAIEVb8`yz$ zZ>Eg=wdGgR35>sTo46 zBgL;Yzt40YY&h)1kz+kgr+^Q6p4BSn(V5xej$Yetb1*g(*_#gB&YE!Id?#S39P$?(T(uq516W6Nj6613S=u0h|r(p}bPpaypc?{iEE!=EHgKbs%0%{hVGl$sx1|}(;?J9f%vC;I?wUMWcGfrtFj7y1My=K=Uy~F#Es-F%wvid zS95!?FQRkCK>WOnC-;8ItvoIHY-sb>L*{_~F1_s;?E7a6J3OwmJBX=5F74>gksH=8(^i zZR^QlKBwh*E0>RR7tCjQ{`o|G<&7lO8~CsCpD)UD&bcdyd+Vm_4`$3A{&Q9^13qZaW*SFZo`@T%pfk{jQLALvifxxtl#O~~WzcrMuAcOtnd)6=l8A`qS4-@I`C z?1{sOqc0yqeA^$NzI-+qjNaaHa7(&BHIMigd6AC!i6^TU&X1U3?1$0rP-xRsPs5-Y zK0Q%$Akx;@e&Ni?id~btc1Bk#2M(Vf?rYs1>mJ_=JJ0So*pd!BbvFw;d((*ju|Bk3 z?OaHQn$69p8#;npyJemWKeds6Db7J2%8H8{5a+Zw=T?y+Gck^RBk!kcw`7Ajx3u=r zITKIE@H&KZV(gRTc}V*t_Jh@u&-yTP>;L^Uru7y3Ppq?5(|ZxG zz>mtfK+a$IQHsxw$UH3KY^DDZw`7x)A1$389;AH)##>(J>gaigrvnHo_mTg>zB0U7 zEpJjS5A)6~59^{^-h!{Z1#fw4>CliYZ|q26MP$r`%;#dgJw7StNjZmelOpO-i+Z%$ z{1Y;7e5z8$Q~ii{J=YZPQhP5Q8t*9_pA_8QBgp?>YeRYFqAyONa%-&i%X2;H4^e)$ zKZSjZy)P2!$%f9Eew<6oeF<&yM%rI^GCBIF9F1u>VKilAdSa_~(A@wz(UWSKe~DbhT~vOivTyKe=CT zmiq)N-xxe7=K=B&!?%i3YvH#b<;|oLA%gQpSDFyC^@;{m~q3 zmi~F>9OD0G+VAjw-d^{SXLiyn#`AS|72`mizX4=|6D(kv%=ULV05+E(~|meub_P4|L2UA4l=7^n0)` z^G^JH5A~OwcS_0qB<-6h&nDxUk(SjFJjY_?6>`A=v={NJa^6qzxSKz){H2;du=189 zm!No)%YC9gOZ{c%8_+K_K4&Hm?6dF7_@?f}m2+FPIU2$F zHs)I_!2O9lS7YbxbGvY^y)zZqy-vS(AKJUg8kgG>jr3ej$8zv#oHJbO!ue@=7U$8o z&W~b$zP_B9vyCEY%?Hf4!*gRhPYfddojnWxBcIC{#r(N?cqVuM4&see9{B@)4rm=8 z;~1vAK=8^ToX_JqBWhm>@&BIIbb_A$koom%dz$Ec{MH1{eTNZGQ`|Saqg|dG9^`%L zsX2MxOnwCYi+%1P_^(`=^I)|9#X8iEI91NGJ9~yNA8Kk$%6WFB_cr|D-U#w5GOw0t zo5pi8Sf8H0IcV*lb2y)q`)AC5^jie^Wx{!2Qx?ySAP=4ntUbTl<`YW(@gW^4XImoTpj) z#u?;wR}qI{p38lse9q*M8K(Kh&xc@~`hEMggALf9r9@iKN54`$FV8vMeJkxR<@tev zZ|t*ho|&MyY2}Q}`$wtVy19nl+jErP!9KnkdbE!}(<5X&Uy9$mbQb(t=BH@CmZovU zbA|LAK{}L{?WFxkYdR$Djlln5J)?f7=NeaOJ;VG%{vZ8|^+ftR_D@T}{WK5hTutUV zXdl9I$WPEX(msU!R_{I@PnnODc4_{|eW~>vB*x#$H?^$}*!dnIjdea=&wb`^pIRJ%gk7W~%79k#M??;zHgpwM}PEBQJ^byNN!W zhdovu*p2$hJU`-1tY10#yh+B~LjI~Wf%Ad7iYsTEu-;&Qg}8yva~Eg& z4$LCXq-&YSBR@Q@OmLf(aerdn4 zUc}gB8nqf_)7WZj&S$6YWM^|NeWg;NC1TW=#wOpbh_MAf*_ZbWA}GvFV(A0mfo(HZy;xoFSdybf%1M@!T&jX6IdjRT2o}Us-5y zQC{L-zMRfXV?sDJSuW=bt(UTe{4{JI(y)(uN}A3sm93JFQDs)i8j8TbVf@QQtW45n zz75w?cx#8pz!Z53r><2HT3kwImddzR5tDZ_ zQblloPOi#qR*kP0Bxa+9rR7W>Q%PoBSOSt4*gk8eI&csdfg2=ga$!s@DRy9y$vAH5GO26 zcl0I~Go_gs01G{dn^Q}R=pf)OQz{nLom4Ii$`Je)RHb~xOIB}6rHRcMOYR~d;hn%w!R?2PUC^2MdHQ$iq*6_thz zJu{u3!Yrh2Qm%_Y5fy0P$0Zr0#bPR@(1)Ssc(_bCJ8NA#UT&S&lQLCaueRRJNvX|V zyey)xDy8F)JuF4GdqrfAX5cV$h3pzlSj+L;!OXQGzs0LEmBnadQZz!=xieY9YMfnM zvylwzb8w}5trtRRBZHyhbZ#{_J(gR*Fi$<2@R z9WJnl0xBuEP`b68w=QT^$6Cr$1|tdr>!l0?s88$#gIDZLh-S&{x=W0Y1F$8i=W|Ic z1XPU}UCD?9^>;iKF>Mz{rO>t8mz8vx#s1}Pj)N6QU`eMjCU;H?G|^EKqtRD@g7W1O zLZCtEG;9(dP$x`N%dKk$+WZvEQJvu!a1WQzswbZ*7ZJG_V<(j<;tp(+Yo_=e!FaBS zPD0n|n6SZ;DV?OsgyiFvO{a6@Vqt}nJbWyYay|Wek;)V43+c?+fwP(6p^*WfXFUvu zcSUuzhmQ`syWn$^x6#Dj{~m{;{pf}4Z02%_Ryw>4#@MuY*V@h^gv84YX?N${A6vJf z3R!DU{UBNEHe@TUy|gX4)n`?1v>})1J9QzGK5=3+a|*R_uZGW|Jb7<)G(DaQngH*GwsUY_{<-4ECc<;CS?zhYPQ7V>eP}O&F zX!t}XeX0+@xq!CDEyk50tk0XBi_A#+!q6q$2Wu?z%;*K`z?12V!xyl6NbIHi`v=Cx zWZ%HYtmC0)*YQ#s9`YgUO_D4 z*-T%0b-=)xFWE;A&(iRtkR1DVT1CuoK-M~;ETVFLsG{kBL#D)G<&V)E*ws=+pR zj&PZ5W8@-N1eIVLqXUCO=SJ)*jipbFI<%b1Y)IC_s(j^%v*}FV#gn!}i1YPWW(X5j z*cXI&DnrVSWiX}T)=s9!E@0wb7#JPB_{@dO=)j4g(Sd%&iZ44TE&s)W^Zs-dyWWxQ6%sI|og(u&)21c}Q%X4{kfYI(mcma^n=_o_v! zLlCz_F>G!F?IEkNZh8mJVzOOoqp&!`BbhO{S-X;Q6j4$1)Fw-USZE%NtHn7tGK|*R zDr5a4Co;q6e^-DVnq8Bz3+W5+RNQo1i#)N_a=Y7zjjy&@a*&BejfQ9Kac#5pVzM8k>Bylk>Bz2$nW@h>&Mq~ z$&at+k{@5sMLjiK)KtSIKfc}q`SJB!^5ZI(d?)#FKhNKvB;`#fNc>ew*p1(hd z=kHJAQT>L`rB7rooXcDs8^}B}d~pnQi42cjOu@?`5CG-k#=fv{V_!<#RM8b-bfk|g zQo7y4aJ)RR#}E+lLLsj%D4w@^GT~g?y-+nefPn7;X1o<9;i%W? z3mh*?n!6%yU2#ub7&<#Jni(D#g#7_5LpAgUZa#`?;Xml(gZq?NTOK9$?pHYWOS@Sf z0c{Y;5_IZ5Rmck3H=DnT9R#1^EG`$z`MF#x4$zjT@Sg8%p&zM>F(gwX=C5NFoGg{f z$fjlIP2&gD8ffJBm?Cv&8iT4KZm81o|BB^5 zH~)fq=Pwa9pf7Kgru(x~w{n;XyZqy{4)B;X5!Qitf)xQ3u?VC))1ucWJZLt9h8KKn*Z)K0U65#sP!hW zbrSV3xZ zfnkpVu5AU78U?`0qkwB$0i;F&2=XZ4+ExImQ2=Z_3WPSR4IniN0EtHd*R}#kjRGLy zQNXpW08*m>40sf9Z7YD(C}6NX3b?ivKxz~)vK|Fo+X~u2r(CP5K-ZQ6k?TuH`9_+q zZ3XQ}r+gz#*S3Ooq*K0;rfXY4JJKm~5cVu`kFKME) z7N-D?q&$XP0FjEOuK);-f{T@QEmqor0*`_V5W1x)!3U6b7a&Ax6np?_cL74=dWFM2 zfY7zodqip!d;mG@0)$A7f)5~vU4Rg&QNXaPy>!?`1d$pA470EhF+X*fhVtb;6D}qW zYcX*c1MDf&9ecW^DbqLhhuyI!QlsD-`@`8z1JEFzd5rD>CIPn=eI?~38Hfr-lpCK1#q@t;f4`)YQoDsQRq0@&my0+R&q(%X# zQK8@I0*XkD0ubU+aKY251y3gsLeH3H5rO=xPuIl}Nofl6;i%Ka5s?}N!jTf=bh@A+ zQlkJAcobZKbZP<8i4pfGxL}}Lni4Rw9tC&MJGFz}=^J#qw#QIA=v}@+r)x`r$n{m~ z@(ns&+X~u2@A3^gUE2!ULGQwFs*R>=TR}V0UA~c~Yg<7((p|ohrfXY4JJMagk)~@~ zK|9i2zLBPDTR}V0UA~c~Yg<7((p|ohrfXY4JJQ|0k)~@)fynhE-R&D`y0#UxBi-#A zX}Y!*v?JY(;jCYukE7LjE*kWWDhb=xv@qy~g2ozU_ZFi;Uw4tPZB2`jZXZVI+E&nF zq#HnJTHhG?T%JrhM}s)4QGrbwwn;6Dx&f63nUs&|MuR7PCS9D7vSv^Lrp5=uJsR zruOACsnOsSzd=Yl20`l#0-)YXfZ^zX*69F-TQ!x)6{EqMeshp@%z@UK0}j1a0K?G% ztVV5v^F1 zsXv(eKEF8yX-PfOk^qyvdqX{uiK20NrQeVOKhn_E%MZV#0zaa4IzU*69z30o24Ckd zQbA%;kHn-OiNtUQM2|$u6??jz7`6`4nrc$!*sG%;jc)36fFZAr0x-%f>va48qlB_k zH$A{8KkO|>fe_u)l>;bvbrhUXj##IIQTOU7kf4mPPR9=k%Kkd-(L+L}f^APhKM4XF zv3>Uztw4k1bwy+JrNdDloQEl#hI>sZh@m91#uVj;Jvzj&TS2r=2cVG0T;%T-r|D-H z)R5ovTT*aD31*!oK*h1NvM4QKrsLS$TPFowlzG-!0)XTm-1fmR^M`&j3g9RKtuq5m zIUWuBKK@+|{mN{TJlbdc78N*BMp|c)5N8iL|6%|Ki|SZuI8 zuCIPL9SPzD+}m>sjwxHMGwH`MC8-?*=y6PGX>U0SXz8Y|901U(qo9-0)*2m3PJ48S zVb_gloerSp)lqOr$!nbsK;_j@5J&lIoemJ>V0V#!O@mqRZ+=S(=qRzRvjpULOIKh; znQWa7@KH&}T5=BJ}W{DWY|@ z{J^7Zxuc^89_7a!5Us$M((j<76?mh9XH-bcv80D1CCAo0*!M#_xQoXQCB{{ADZfA_ZO9et1z*+$mcR zFG_=Z+o&LkZfeS*Ot@T=DRM=gU;Z9>1@IzxU~QkvaqhaQ$kfIN|(!LQr#b4<#YM=LJ+ zOICnN;<}OvsA~3r(&|phdQeirTuyuSmxSr-Hnur@l|fOo0za+w8dHEs$$6bIfJ*+- zQT>G`J^od(=r^W7k+StVV*pmo^jtPGJvB9F{i0afTJhUb&`61Voh<;ahLT+J*LNKC zNn8G1J>~VCUe=?OGWp()Q7}n2b>;gpN!fj;96cr}pU->c$u|DwK7#s+m-!1GXSS>JtQgB?`b44Y#pLCSyXFh{jlo&W`7+Nw2`8&4#18x5cYCunfnF5IR$fcETJ>!#~htTI8D-H zP98eYK+yRf7Hw-RfP`Q6Re&UIV?=8zKxY%q`U->mj5k8LU-R2iKuStFTL7D9Oz9lM zDPNC7I-KAY#d<5o41RhXt@xndl7dfC(UlIM+2_CVG`oxk)5#W|koVR~K_{JN=xhOi z5;f=%@2}Be?_+*@3UcYNLub#ATspyUdPa|2I)?DpTR|t?)RhC2d36*B(lLZi#}7d| zeQ@fggGc&zwGoNLCn|zZ%wBlR-7P=6V;+kHe zg9g_MUMLU^1$|bObBUDxTp~p$4$hM$bMl=*(U5PmFNN$j>5nKva71p+f~nM~@#mF7UPo3`a+gpQIl@#Bg-<_@OfbfwRg? z=`PM)^LU~*^q9Y7h&WdCi1HsPq?98CNo#t=f25F7jua%V(;>7dTcQ*lBiMD*A1S2h z)WEBwAVYtokfIX=uMQYaIeKLHj}%hGaCG#@pi=|+-Vd3d!RczqKkOvo7|}z8juGS& z&3LO2e&iAj_4+HXKu3S(kfI|7Z-W)+&`sT701I9n1t|Ihh7=tZcy$yt!_fh)X%8I$cy$z@=uZbyl8B_y@6}OopwHQ-C`IqpQE)&vb^YeY0p;nPz6Pz+@#BE<^o|Z_jgCKOpHg!6 zlGf=E4y;gIK0<*|BXrx>M#|mWW$W|!DN5CQ`h^&d4rpE3fP%e1%9jR4LyLYZ3R?6z z{1m0>ofcSW+|Y{Oj)EY4UOz>7dT$F91nHCbDazB!pSU2(wqC-t8V$X`Z%BcaKC_>q z488mvon>V%8v0JZ6$NPegno+h_ueKbK%<+wLGS~O^7YQZ>48RR_-cxGt=jV25Tl{* z_Z6?C?o;~IeTp*mGNXwebYEE&4ZX^5N`WBhXj($4dQa<>+!zSapQlgBN88nyLCMq0o4RuR zsG;1v(;hu)DCaI;vB`c0ho+&o`)aGC=u`R>eTp*fP70M@PZkZm+iyof3n^$?K-qRr zPbum56wx{za#(cqN9o%YJVg)rlenDM#;hC_nBkN5PLid7hHVa}}pbqFmn8)QxiC zo^ps`*G-=&Pf^O-s{@9kqelj1w!JzE4)kg76lJizItmW->FpF{t-U%54(O(?5BxZw z)V0$d&^jFqHK(MVckv~op}+MPu7HE`+&V*ka8T;nDO?W@%3909DFK3YfnN9*4gHh9 za0M}>p()&-+fFIDZAt5N01*2pB`6s0F^q=rt9nnTQ;OSegFfAzqO`SFM*)#Or=6m- zb%NXrw|O-h4)~2IsM067Qrzkb;)lo1+H#K#ptg}Z)NlB;lDd`kt zm%Ta)VDzcy6lI#dItpOurmk*&uS1Dt8<_eebBglC-f|Rt=#$AQ$_aaQ6ny9t#wp4V zdvz3i&`n)?Fzj9(1qb?saf))ncA}edb;>(Aqv3V^qhLgzOioem*tM7P+Vf*hNi<8v z^=)dWM6-OZjkXAG{p3bvIvRf3+hQqhji97;7JcYyr}VR<16rp80M+TA{f~z6(k8Xn z+bIF<*wZ4fos!3HtDIi4TXouR(Z!`y)z#34%XUgcJGB6<)A8Z5opQ~N4rrYYpeK*P zsW+^%B6{I)GnSxdVuXbYCrR&qp?f!JLWH>qiRb=kYD1EB} zxWwzD>`#@X>ERv8M~*IPiL{tTa-SnInp;@TN$~?Gj3OSci`Mrtyl!+&o@S@Yuc~ryTj64A->vbrch?Q!ul5yqpwJu>?`fy^0AKa7{%79=Y?X}K@9@^%evOw^4-tN0 z_(fFR@4#5##bkvPo}Wc;?z_4lZ}Fg4l}QflRD12*Bc@?)%mhY*}5 z)9KchitO|2iqXJqI;vR*wDNPzajiH)G=>FAh&oocNY)R z<27pe@)}va^xp7lKMM+P<8Jyz7+<_Q zNzbh3(893&X_C0ZgzP)n_`9%SU%b0WUsbYd`1rn|b(56eC?`>$!t6Wt5E1u73ffO6 zV6xELL-{42Ov-nBR?v`RbD`D;qk$I! z91gnRgWLtb1&6%TB#Bm_z*CM^tzJ^~owzP;nYHlGzixQY~x%}+PRCy6^Eh-h{{E(}z&7|i# z9~AGE<^ROpRqn)JZ7 z%LD|!z%%yG9C2QBP2-e1U>l)9bI-R%nZ|eg51DdjwWd_34>b4a?fL58G<1g`L+M2FuFgn-gK_yXkIUaV z;#M$3;*aPXWR2HN4XZ52+<(&x=!}c-SHfSVM*fqmwd>O}QwR*;MK@R_hddodKK{&q zMSeqQ(D0+#p8BBK=*CBNe*W5t@YlotMlJmYesbiuj4uvm@dc_D?5KkKC=P3Upag2M z*;@;W%f1=@7TLyY98^b5D5u$i@BAk2t1el z@d(rpk*d;8e14H!AU>LiSFzTa^`wwM5aqB7&#qB<%jF!sE*CAhBqEiOsyO5}NyG51 z_tS;8qE4;>< z*w_x!*n_6Fkguk{8SGy0_Sj5|d;z=tRgX+d4m%D6#7aXA+9${4sxTijAE!QfN|?=j=b$imG1V%}CzwhK zvxTX4VeV$CLzsJ5w^NvVnb$4Meayq)?PuQ8!hDjczw^AJ;m z!fa(~NSJMG?~E{$Oq~^Gim7wLY-hRi!aU5>m@qq-x+u&eOkEacCsX6X>|*MgFuR$W z5M~ck8DaJ^l@;buE@MiVPcxMh<}s#bg?XH*yfB}~)E!}_nVJ)3A5$e^_A|90%oA*R zNtgpnEerD`Q!Bz8WNJ;Ar+%Z2$2Q{N-Z^IVr#2y>Kq-!IHDrhZVE7npjbFfTIoYGGbt>NUc=%+zazd4;Lh z33HsO9~byWi^R}R3iBHCeoC0vnRN7v>^UpAhB}Q=b%OnW;Y#<}y>C66Rf| zJ|oN(w(=*!TxH(pg}KJm7lipNQ-3bZ=QH(}!o0^Ce7e#n6G52 zT9~h5s#chw8>JaA7GSw-}H!;;M z%s0#Ni1rHe=a~1jFyF$|abf;EQ)ywom8pJV{sL12!h9Q3gTnkpriO(1OH7>+=G&P% zE6jH=bxxS?Wa_*y-^J9JFn^gTWI1=yQX$`d?yh0-lS}+LCSEHx6dFFqLUKLSSsHad z-o%2tA5f(GO(%PWx=M@L6B~%rCjwabu?I-G652-4_n#ixQd?-lmXeUar7gNjLD2cY z6xV%2F}DFvJ;0j(b5t7}l^-jiuT(vfnBC+DRZ&`_Z(2QqHTu-mBZ$!#upUXwwx%6= z^s?J?TEuxiqs0ZvxXBM;mc!SzSZ1$o6l|Fce{^djN$5=&_Z$^CR53mwwH>;YfYV+CC^tdGN`-^1H(e+iH!H>j(en({MwEUJqX ztr|#Co+^*f3H~{+1Ds`;X1(mF4F;XpTNc}|0h47)`6eOD>gJ6l%T2MzT?ckcP=3LX z&22E0(l^kD4If%CNz(TYSx`5Btb*y&e-AC!`8wi5&ACzS20f^JOYxya)0Yz!>}-Hu zlJr7ngRv%I8(|wvN9#L{TuZ$itz+KxPCv}HoDBwj|JYLAhUome{IZ?9g6fAD=2TQa zP{;yK~mOWgW%IIxL!RBebu+_g>=cQnQ>%76{X}#qQHc#t?H`qL_7v5m=qzco1V1vz* zU-S|2OI9Bdza;vI_$ARt#4m|HB7RBq5%Ei+8}#eC@29d~*r|y{@Uc_+tSSrWTpE21 zmA}%6{Y37A>*W1%F3Z*6T-|>3qHno~ z??Cnn<9S9J$H!4TszFb;+PCFn9m41{`swD^gmHqYuk&$#zBpA_p3cc9bQg28nfW{A zOc}-ojFTjfU*R;um?~AqhjJaULE{vOeNz}iO#P=YPD?6g3gZk@L17Ft74klLyj;!~ zS}$b_`Dr}Q(WX?|y>Zl2_H=Fu-)E6kJcdf1HAYZ+EGCR+m`VuaJX4jz7-edcFvggw z#^*?VjhQNBmzJE?Tre(@y)DAH#8jOyE;F@F7*}M+#Ttb%&Qy~yt}?X~kH;w0zm%Io zgZjN3_korNwXRUg;#WG^Ij4ox#%soPs?#oE+~BhCgvnzMvMdLiv@)!hQUd+@TVSFc3bHaEDQzc=%l&J+_yo{+OVSE=;%ffg$Q!B#wZl>0R z@jXmEUl`xZ)N{gk1ye5&#`iJxB4K<#Q!f_A4{(cKB8(qo-phpXLrlF~7_VgNdxY^S zrd}b8S2Okf!uVmPeoz>%Vd|B__z|}EYGJ&Vd9M-1k23XIVZ4s1*9qgtn8L%<)e1EE zkx60vxbYJ-9J|>J`X6oa@csEmjAdL60l|M9%{pc5d zI%%p@pwCR@OU2gw+}v`R9;j^{D&k9Px#_Xo0vt!~QDu*+4?MNI4o12GX9dtadV8#w zoW!pfze?lsX<_^(*Z8x-crVxZbHaEZQ-3Oq_cQfp!uSAFe<6$yGKE)d(KBAE;{ctZ zA9x7kw~XH=`(G5s@38$Z3FAYo_cy}$U8cS)jNfDG?}hPUrv6bFA7SdN!uTjt|16A; zF@-hk_nG>-Fh0)IH-zyCrv5`1f4~$LrB5=2Md=S^4dPgo{)j0oN`K5$NEn}DDk6+e zGZhoYXQXaCA&k#5uTmI)!aOV~pJS?87@z06wZiyQ=4}2zS}O0zhkOH7=O=Hr!fA3scvEXBU2c+uQ2trFuuxGjtk?Tm`V%dpZRXT zF#d(90bzWNsX<}2tFuujqxG?^cscXVCn3@nK7Fi%Ho)Kn%sjM)AOic;1f~lM^Lrl#IGt5+8m=UJ# z2s6smoG@cdm4q2*YC)I@rj`V-BTHKrW+hWA!mMIyO_-aw51uc~%}hP#^@jWlD-oUx z7xCm}{DpXAUGbHpcs1tYG&=uz(XZ0&7vm|)qj(W=`PljgN-v4{OX4q$8;9dB!{d|g zH`y=TS}d)QJBh?!9ybofUluo#BvRFq#dmvVmWwUL+zLGcx^JI<#^QN$IceRvQF;yh z=BkB$#|1we{THg%55W7zMv3|%JZQ}h?HT;II5*Q0iN6X_kmZpq9v;2(Umr)6e(I5`G=$nk;%`9E zWmkV-mCNkMGqw3b?%X{2@+GwYjd&u|@wyL?l0EXKSo~+>Z^j5yv!?Kih9e3R9-!zg zt)Jr7UJ-vw{O9Aa^;X2ycJ;i1k@(y2Lje08Eew(PFVSy?N|~0)ES~wj@t}vYA3RFb zCB05Vz2%|D)xuE4cf{WrkH0Bk`}$I-n@>IG7)d|5H5v)%ZUHU$(frF^t5&hWg8&N{jf{ zsjB}P|2I?>P+2Z!7uRU=7H38L-wE@di~one6&>MW!%)q;ts9 z4-^#V;I;8>gHf6j2{REup^2cs{`jTE{s)hO9ZEaD9>fF2Mx%G>NiSkCOfM~!rs&rT zA5BDKMrQ)cN*ym+i_67welFKKnxDFbdD;?5;3pH?EEE2l(m-V_Are)z<`m19kpr2h zA41a8{X-(LIZ=%jB~gPlv0Q4w&(m_nB`gYUl+_^2Y!La6((fc&hA0iQl)sBSPGU=9 zE27Rs-RAh~QC-j4eYhn%ot-b!ubg@x+&$~pJl|-GL_?wxSWRr-6izhZ;Z*I)=|Rut z#Ll2$7!mphVOI^eXe_swNBZVj8FVCe!IB$|;6sq5JGs{3?A+vZ_H3@4oxw*4ON(of z1Tq*^*+N<2nZ`@iDp;xzxK)}yg`ZFsa!W14rP7_{`Cg@QR#2dDJc{H|d#@>XH8Fvu z(4Q?7#^9*Y`+E|5B~ruaVZ4F1$)~Cc5Ir(FER*@c6n;xUiVTD_!M>JyAw0@FR9L_n+lnMdDK8ava|C z3SjNJqf&9QP@1~KAAR7Ldd%Smn1$@xqi!)|&GD81*Jsd+xe>M_9dfrcm8H1)LUwUB zR~}fM%E>T0lDLkYf$f>(dO4b#9Vn6m!eqLEq_(rp`R>Zub2FC6B(m^7wh7LjM-o#A z4p5Mcs~JOXt*l@>kxR_P6VnOoBHwMkhd_r_XR|BDsEj1=JLNF@75TG&zre#>k_B#& zm`fDn=HDbrR?V`@O8_lpTU?9Ijt{eXA+Z=wOeB^Rm{Oz>Nh~9~$WX+uwv}I+dILJ| zm0X_PRl^Qh5^Hhv-?NB!;DHV*6?y2uVV;K;ma_%udE>3lhphC@Kp_Z(5rkVvMQ3HG zmB2ePyvDll0pAC&i}F_vY9wZd^G>jSIX_*#g;0H0;-v`H6WBZB=T=6uvO9C8>r8%e zv0P}iG!idQe0SVvPJEAPw7Ma)UfAtcp1Sc5C0>D$H}QS`)*vZ!l?UzzfdSej%+J$C z_kYxVSb^9p6R#ro@oH@0-6>Alf;JoyaBu$z!ktMtK5x#Qp^^B}#Ovbme@*-t;xP5F z$a|y_N&EzUw!Jbb60b+Q5mqYHA_ zxdr~u69&s6b6kuw!0R#@kGMy+djHoFzfQgX8@w58LF`Tci^O|5Jbs_W$A+CY?IQ63 z=6`TqH(;;p>zMX<;x2WukBw8DcX2QMo-qHG-5K_UpQAe9N1Z%b*IPr(;4^eYnE%M? zC}}Y}0gr!)qXzE%zrs-i^S+3q2IhSUCv=SE zzd`I^cf-o9ToJAPGWyZMpXAA={(UU*cZq)xi5DbZNCkWa;m}t%$43845p0``lm4Z~ z2qwO^IZ`DO-giH)EF@`5G$2$Wd5asA@_AC?hQh{I2;r00>A$J7wLfne2g<) zq*X2*mn$KD=_B4MgrI_}&k%yVouPQMUhD*hja?d4#{ddK?ykN|yTx z$f4h)9RB*`Iz*s`<=)@}F1?$Pv)$s2=p+hJg?JMdVezx#%_30GT5rLv6&%S4@m9X| z3nI|Sx9~Ew=u8$*BEjbh@piub4iVVFx8H>kqBlH-<$ec5fCi1PX!K}k_zFaTMu@LK z_}Xwp1RiIb@52)v+;blgfhU-U(}a&xh4=8~htL)B%aB6+9#`qZB=BJo*v|qVLur$1 zLVTR>euD0PLIe)*-9JQoZ)FQJLi{n`{}kQ-lnAu){m;@R`XI%ZpU3k%EcXRaT(v(J zfeyZl_-3B(BEFgDyI&N6F20NSW`XbGF@OcW`(+X6<-326{#Zu(bQUY)KeE_YsO+y$ zXJNK*XMqUN7mN6c<}!Vph_65d=qp2f1tLHn6yhtIkMtcNz5)@TFZ{?WA_DZi9=@WX zqA&6A6%7@AfQPR@Y;|Up{3dk{k8WYQ;Sn5E*$7ld;dVU|c;^@ke3S(eegVAMh6O&x z0#$1Am&#b753{q#@3Tm?-v%BiApxZDNdZ@)atlP`AFtfH4qQ0=e?FVpw(ee+2pp56 zQMsMkZTC76K8RwEx+q7m@^SyY_W#G*b-+ncv;CRbnZ3K+?CsnhC$1nO0^(7mcTswg zB1M{rg7hv$QBhG56;Tltu`Bit$Q=lxhz0DuVSR0{Vpqhj-;=Vr$?UU3oPF>6@jLP) zoBxx4dM5Ks0*{WT@!t-~`VC5I2LG*L)^9C|)t#pf%L|KMHpELE1U21B*(5xq6_T0B#wm5pB(8FB)a-I&!wEf8iS_}yPm#+0~?T;oKJ7l z7~(y9G3+{0F3ZJ!QmDQ`W}IwwZ(p+ki@XWvGK&v1eIb-;mobXNaX-iJ8^n%ftc z!ltZe4~d5M5J!r2B8ka~DX`g;fX&33vJf*nQ?xMI`>VwCB4hu=4El-zHjDO8%!00; zDLJpcg2bFy;$-^lDObYu=lTVSc~BElKMSL4z{G;0#QX#-|HhJwK{>n|2JdOmVdxS- zKD<;tf`g((F!)JDo?n={vx*XDCeDU!6pF9!d+x3(zA6}?wkOVw0qVS1q8lY~Ta@+a zrO=~gGMVy#7plBCE-W%?B`$*PBAU)v&wjevqw;Re)RdPpTpok;E}`=fq?cV!wC8eS zD~gQL#N_~?V{2*R3Su40+rw4RZ0WYrf;l8{HCtvUR)cXX?+VuvYb1|$J+Y4C(v1+0 zEd~={IXR!l1Ix(;Tms9E#zTfIXR6>50HYAf)s78YhkHy z65YHfiS)Zo&tE{$;8vdn!}Mh zp;%#?8;(OIiD&tb&k<`L{}HSi3dZxZYDwZH{_D%cI)(oVOCDzqJbuj}iP!mWZ-4m692&zUxkB;Mt5z##H09_IsME#h%L0)9YwK1qDcBf+xgY#s@gJ!kVs z|E0-6B#8ATkF}dv=knjahVJamKU~Yim#B$vV~Ot)5b=B-@dwK0q}C+y6IZc^SQqkN z_7dw7F8xZEa#QC)I=}NsP|hp(Pk&Ku;Jt!*iw!WzWsRuV0^?>zxY&kWKzIN&CNry; z;sPjNIQwsb|VpVYIC}M5qQa55f#-$#_ z+Rmk3RNwx@dWw7d66;wm9Zjs4xCAq0Wu-^<#+jD*t5&O&z>%aPP6i+QlWP z!P|M3N0HbiY{#bfxMZ|=Ov*^Y_DgIto$0LN6CmhB)94zoxY6FmD;}RR++vskKjai9 z66;egO(xNmyzNXS)|WhNIv8#90-s5&uX)&PV)4!7;**K>BM+NLte?5G!1o|Wud(L6 zr1(^L3!51;;GwLTt~-kt7M~90;5>~*#QL3UfhX&tOjL+TTRp@)2h7EJ%=3u#7ms;9 zF+b$LUH}s3e-Vio{8yLSMo?#fy5(S zO(IdQ=o+wD;=f);B1Jq5Y#Z$v3u#-viT`vnNF2C^Lc;*2B3^o;<-sQ`(`*+?Q~JkG-`Ehw)oJkBE^ z@i>o?$o@ReHh5s;ziuayT0HDYz>TM!ncBO7?j0a;+%qInhsSx2#+fyd6u-dZya*DH z^D>DX%;UgV9T`6Z(x)Re=y?Mq9_K9*sn6rkk$U`O&_hRRi1QvuJkAFsawv}jrt6RM zUq6PAGeCkq@F|Iu^It!Q=OzB@7bMb@hwTQf)5bvwe$9UYGxen$_nm)*G+@EP7Jcd$ z6vH6xTOsjZ=nAR$r=sE?i}%2r3~GTiqw4KEJbgCQG8XDYiuV@(0wzMmFwm>^L9MFn zgWyH4Z;vNqxstu{mf5Jyyznpnz4#AWFn_|}@K-MLAkPL{%T8|bKmTSYnAyrC&6H7+ zv|>gVYAcfF`aEAp^reQA)S5ZzFx@#Lc((WWvfSLBEQl5Vm@Fib=ByHvF%oITB?6}g zvISBptC=LI`dYyE;GJR=v&r4S9G z^_)DgC|NsM2R=<>uOO4~cpRPDoNYEG>p}a8S0>@9`1Gm;mb#)+m$9lZ??o*yrT7)e z1~K5+kVFRYtTiGL{_v74C-KqoE&OC_ zhyu^%3HfTM?>^oQW!hVgS3@o6t0AhR6G^s9woe(QNoXL&lV*cK%Slt}&m4Xd(_bUA z$(wnl)Pg<%COaiNLz7A#K_Vk~u8t&;FRS~q&LMSGhqbGGPmNLdwR;)FF7NgoDlCo$Xs5+vjH_HWz>xKAY=hKg({i{ zLGxX5O3K(jIfIZhm^D{&A%vcmGSW2SVjgi31f7{O4xq8l=dl(;&^ali7Pabfd1eNT zn}5=jo^%yhkX!D!c@~hT>It z8GH@JrOQc#KRhI_fC+(3F3GEi(VJ~TC9j5|Va`l;mmFNrF=rx4UIVHUEt1y)mCTb9 zd-R1-qWidc@K~O_-upPI{KiI+8;g=RByaL<{Y;&e`3x2m+(K=hyw47vUzv(qi;`=S zuvV}K9^1b^Nz%mv1b}UY_YG3Zg5=#W(e>*JG4ACt?t>Al`=Eh6x(y-82Y3+deA_eW z3Oq@7y<;yXVd-EGfUl-WlCB*dnd-f&C%{P|t2ddUidUB%kN8UVv}d;76$Emtgwm(kq~=`_LgnMv&xdJl5;*3;`h{hV&iQ zlO*5dfp0;6XtbVPdywQiJZu-FFlXio)ObDl9#8arD7&uxk0nXEU<6+9KdXHS@J0H(#E>&@hI4pZo!=my|17=THKuz+JzrfC9)#S)SS+o4DDEVvhcS0^K`jplTtTmE>4SfwriTkeE+!rzqARMxDf2R!7zN*eE2@88+1{g5wKFY!i~g|zq&Sj*T@*V zQFu`nJC8)pV6%W*1fQcq%^8*(Cy~WGECHVzv*zX|NrXSayCsBN!lqWYG#Pbkq>KY$ zUXAdFco&u#{2|^=!*{c6Z^o@f$Vv`45CC;jMjZ-R$x}F(M6Tx2A%tATqcwnN4O7NJ zqzROLrb5`z(tR8l%($?tUMj0ZhSN%M8yC6dF2KN0Gz07gCSMsV3{P898v@_-HMhIX zVxZt~_~Mfn1?)l7A9j9XtZONuckoAZjNbwM9$f z9>Jr+7v!{e!*55C$hADb-Qa^}o=6W8;oAUiFW(a)y)&3UA-a8HZr@^fF5%Do?$OZO z=1!bR+yS7&?duK%iKlf8iSWmNcL;nu%~KdgBK&FJ9qvm3dT=HM*l8}Lw+*saS1z^O zb4R(y5qC7#dpwEoEduuh7O|y>IF3ggPuy`l;sg?TfM;N`o6t?LxdTR@x9Nfh{f&)4yNcX*TzI?uDkuLwi7o)^6v)Ph@aZ-W z`wxly!;^tY6--MoWiUx)1^1pf%k%vKq_*AtEC#844j+&6#`y(&6wcGw4IhPb3FhG> z?AwdauHccKUcL0c{Cts@ru(h?9qfs_-^2D4HT9iGgNgei5B&+gYUdPxhOgSW^b4_V zUJSnxyMRl7z}XI*_Fu&2+eGd^@GUz-l$az@lQozUux%>=+qT1?!PtDKsHA`-4&Xl) z!H=<&Q4T*Q4&p%x2r5n)jcNQEEUA(bPLzLaKuSv4D~*yG#7^_y_ak;~F2N=*T}>HQ z$pP@eKBrQf*nDTF1Rjy!=D*g35A6A`^@z>)bV}+IoA2C|G!#R_>{&BTBPERh60a`U-o)j1bb>=aTm5h6ntCJ~!I{gzCD^9#7DX~dq& z6Q2R68*rtwh&_Xc&4Kelc)YoAgbSDE6N3)WK;sl*e8v$AiG4ChoK9^1q*Stq*nEjp zau%`q!l-01oMgbU=fX(_9J>TgGT_ouVxPygTuAJtTv`UF8*s#OVqeU|E+zJ*Tv`Dq z9`IjR68mxs;`&w*`$`_Rn%MkpM9HH7AOwi5ec9_KM)Kgy-Y;nP;okZ4iz1hl%TCykp# zO4$3c79~$Z!=(WyOlm<&cJfHi5c_csgbmjs_A7fxEuq`4pyWkjKh1xC86Mqu7;L+` z;)xbsge;gvH_k~39U}qo1~J%MPOAi-l43L(G_t7^CXy2Rpac=%K`BLpsl^q%zJo6X zC(okz_xR87&{Q?dGf@$q=c3RfIcGjbDYM<#D1AepThZ4>=C=6>V|KSom?i5UI&h4;DeuEsrAoV*OqyZAt^q+8$2ABROiAHQM*XP9F7NJEjb07hCg$u8FBbrlWGo6y#P&gOMz)5eQE-! zHGB!qrMAT3ZzfXhNuqtC15KhMN%Z0c)EA=lOBt=`kVxOg&z?Jkqz15q15yKt!(T|Gjv)@Wu}i@tz%ri4 zVZ>?3^F5q6+@dZu5>95~zm6tO6aMQMIHQS&jU~?EJnTd`t%-+?Ck~&2QWJ>7r=Zj% z;&kNkU^E`U=CIT>=>AiiLlw^eT)Z+h6V6@Xg*clyNAlPw6NgVasd>cV+tjHA#OcF- zJrzF3fzRcQU%A55iE}jnVG(f#a_KDM4Cc~e;_x{rbuMv6@USJs8O^1o#5tZz7ZT@0 zE-fR@NnBb^oJm}|lsJ3}Nv$BxEFQL!I45%nhT{re2&;(0r-syOI8KU(T}vE3Nu;ia zD}mSsed!(mfA-WuZYsUZc!G3{T_Htrw}e|%2eMI1ggr0yXOpBhs45r@C+ zPCY=J)m-0NV%*1zb3Ggm#U&Vzf9LutiE|x~2jlS{JZv*@ZscK)5Qk3}sYi*!r;F4! z;_&GrwVgQk@OV$cF*Y3gG;!|dVLRcF8y@y7arkTE)bqrt;J?DrQGfGaUna&sTzZu_ z{P8RGI&rr0cyAJCJD1)j&Qo04MH2ma6Mqky`1>iNHSGyI`HvqFhYzW#kBRdl5Broj zuW;#e;=InKFNpINmv$3p7ni;!&ih>YmN@*eC-ps?t;6a4NSsgjuY2H>9Uit9PTAqo zuW&*SmwqRX7|8x4&X*kVH=M!4el0cN{2ne@#QB!}T51!Ak6Wct;_T&Ng~a)dOEEaL zha(7a{^nuDBx-WWCDACCQY2c$r5bR$4@c}rqI?7^-Je9)v7PDC14xt)O{KMo8RPNl zkZ28#txKXcxm1rt58x8q=y@QQ8p3gb%+9W~5u6spvE}d`3725_`-T773`RNHBS-Qd zU~6Oq{{b$tO7JlFl%beQV4XRNOC3nGE>EZviSl8o^av8=gHh>`B+3V)(yk=RhoI8# zB+3V#QaGAv3fIyb&g$b5Tt~@=pi;QVD#_Y@=>QUK$I}=D#~1Oi!6e$5hYcmsu3S2n zM0;>)1c~~k@T4sD8 zSgkU4yi~ASft3fxfnc?Q7g^i~g4HTx6iNlFRfY={tX3H=RIplQxKP1ro#8?St96D8 z6|B}7E>y5uXSh(oYMtRi1*>(23l*%^87@??T4%UW!D^l1LItaJh6@#}HW@Bdu-as} zP{C@G;X(zgO@<2y7EWVlelYMbFg1*>g_ z3l*%k87@??+Ge;=!J>EMvRa{n)i%S03Rc?;7b;k7GhC=(wasv$g4H&|g$h=?3>PX` z?J``bV71F|p@P*e!-Wb~y9^g9SnV=gs9?3raG`?LF2jWiR=W%rDp>6@T&Q5R&v2oF z)jq?83Re3J7b;loGhC=(wa;*&g4I65g$h>t3>PX`?K51cV71S1p@P*u!-Wb~hYS}g zSRFE4s9<%-aG`?LA;X0VR)-81Dp(ydT&Q4m$Z(;8)gi-$3RZ^<7b;jCGF+$-Y0(@w z6wvO^B=7?Z;Rgx)z(e>!0zWVjevrTqT!bGa@B;b;8lh%Nk#A051f zpYfx^x9~H5bletx#*dEN!q528v0L~VKRS8~KjTNoZ|9)(CGbmrR06-`N2N$h zIe#z-{E{D)z%Thx3H*{DmB26gQ3?E#AC9)(CGbmrR06-`M9)(CGbmrR06-`M9)(CGbmrR06-` zM@TMQLvg}LB9xPiMD|?`99f|FZ zeFYn}We?Glda@3JAaN%ir9W2^(w_{V(k8G_st<=WiQ^?F@r*HNYp+^`vG~2aJd)DfTJ~tHY-`zL z$!OU&u;`k>PSo^JCuQ5qwxoATWTrhL|#JM6Q)gMmVn=yPG9OelzM4-zV9y4z4xS12d6n`F=9rm3C2THQz z@Fs#c#t-d=gGNAW8kz?^QFZv#c~e12*IBb>&u1t2K|~kc#?7BMA8Z!6P6$d4g%rp2 zoiziv(6h4O7g;rbTor+VNL z7sU@(wlKYLVGDENx)$b6749_Q!bL4Ce1>r0k{0HND_WQf7ql=Ju4iE`T+YJWxx$?% zT)38ng~O#R%!T_`m+IgVJ_UU!d$pvg}HFQ3UlFh73N+f+-1UrdsSHYa^b?AD$EZzsxTMs zQ(^83!4vLMVg8lEy+XKfiwX;eJ5-npH>fZd?oVMZ+@8W*xI2ZpaB~WC;ocPH!mTOH zh5J#M3%8>%_h#Y3%_z*jM#O_#QJ5d@L}4!6h{9aB4~4mK8wzvbE)?e8E!=yA3%8)K z@cV=dH=r;-+<(Gcxc!8=YlR4Ul73m0zrVE!M4 z3pac)Kiu!ZT)5qXxp21!bKzzW=EA)mvYzR93b%W(aJbupxp1=wbKzbO=EAKW%!NBW zmg&RAV>k797%rM0KV3q=}8fF>%-p$<4tjXN{%`|flFl#YfZT5T0JW#lG zgnN)#m;HXQ@YfUWA;PUM+y=sJDB>R~{EdYFFySv3Ze!s#5pGlAHWTjQ!fh__Eri=r zxUIzRt%ci0xNU{oPPpxb+d;S;h1*HEorS(5gxf{9M+)~S;dT{nH{o^{ZV#cSr*L}- zx3_Tn2)D0r`w91G;r18q0O1Z4?jYeFBiz9vy&=LsRJg;0d#rGW3wMNYM+$e8a7PP0 z#|i%!;T|vCvBEt;xF-sCoN&hr_axy?5bi|bP7>~9;Z70mRFUp9;Z7IfGlV-+xU+;i zTex#X{F8-$u5jlGcfN2J2=^4>o+@w)h5t0+o-W)ogu6(@J5#u4iSV<9yI6#uBmCzI z_dMY)5$^fIT`JrQgnOZIFB0xD;a)7<<-)y0xR(m|GU2We?&ZQ=DcmcBd!=x%67DMD zUM<|!!o5bg*9!MK;a)G?8-#nKaBmXs&BDD!xNC%at8i}cMJbL z!o63x_X+oY;XWYT2Zg&z;n_w6+@_mN zSSa^zTwZDJ9MI%x!)da1z4>B!srho_O7rzfb62JL!GOl)O)AZgM>JUrfJoU6_&;u# ze;KI)^N|Ac%d(vi5H(==#APs~ptG;Y*0KQljvwK$|^ZZiLC7-i3b z?3m^z!v#{i^+|mlhSX4n)HjmUw?U-7(W?s_CM%@=l%)O&A_b;GnxrfvZ&H?-A!S(sr0BVdx}=;iq?UV2%8E)- z1wo_=^-0CTkXoydic3-?h*UzKR5A>yhZIt-Bvleb3T#z%tFJ~FQX3RfWs=l>L8QQ5 zty)P{D5Un6q|!m8z;v!!NmVMOYDrSHgGhlDU$v6jsF127NgWhK3M~GrmDIxuse>h{ zdO@VX_^?_@ZB|Itm!uj5kper&Y9+NrA$6!E)hLJ*m}FKfsYeu2<&sq6AW~o*TCJqE zDx{i9Qq6)$fuU-(l6q7j)m)Nl5kv~?W2=?aV+yHOl2q#;Qt-7vwUXMVkZLPQwF@Ez zU&2)@smB#k9VDraL8LlWGpX$gsm_wr5kaK7=#x4s%qrn0g;ZBbs#_4L?)s#9h9G5) zS4j1eqk{J)YKDoG6s zB6X}jsW1)Qcugs(;gZydAW|dsNricuG2T!}jgq8B2a!5XpH!Hq86T-JlGO1*q{ix# z3e)?HT}nxvAW5AVL~5KqsguI=z7G^q6C|mLL8K<>lbRBS)W-^`sgl&RAX3xyNzDvH z>Jx?3EJe&S}I9h5JU>TBG&DF%fbwvDyfSlspUbWF3~3ys-(VBO6pQc z>arkGEA&Z)YEvqy%O$CmL8Ra_Z{6w(RZ?FoC3U4FbyX0lRr;htmDKkNsjDTa)j_1L z`F|yKtt53_5UJ~{nbZ$TN!=hx-55mbrfMejqeALtN$Qp$Qfu@{g=*;PUc#-C)NMhe zZm(uidz6y8Lz22Ph}2#Bq(b#RmDJsm)IC9@?$sxCf0$|JXQiYbkfa_AA_b>W=nkIi z^C$I?B())k6da79OKM{nQhSw>+9XLm97GDvYyok$Oy@RH%mji&9eC zB&o-PNWm#3x+N8AocdKE^@Jq#WDqGhFh!Ttjxg2tn?h=*B=t-Xsb}>`J)b|R7bK|{ zgGjxkPbyUP{jQYM%aYV9L8M;QCl#uptE66&q+Smq^@cvFw?b4Od}8CVpR(STq}~Z4 z1qb-(HuU%MC-uH0^+6D+5A{j?Ck&}#rKCQVq&^8E^{GCo&%=;PDy04^NqrGS>Pvl6 zVH&zwLm{>1DkZwZ{^Vn|gr;z$ymedbHCG}%9ld7qZ z`bm=76GZA~eNw-KY3Tbaq<)p8ehVV?do`0vE2RFAr2Y&d^;b2Ms-=+nTax-GfE2xX zO1Ghhs=nG@QW0sr7zwgoq*q;4E2#q&Qg)`KB2G|A!SQd^N~(@Rsz8z|3?fxj&7=-e zNW~6X-VpUAX2renN$OXRBcJ>z#vj}s+m+nh15ZkRNWv_2Ujzx zLlsi>B&kD!NY$@qQjHW+4J4_CL8K0?W>SYKq#8+5hXs);uVzx^3aQ4DRFfc5O{RN$T(*Qq8qVh5PKOg+i)@B-JvAR4Z*#kv3u0=q(je(#|syWamlmNYotBBOSw# zYORp!BulDuP)Qx3P09@Qfmj=bR2NC=$RJWjX_Ja{3sX|<6jI$KsUAV3dg_zvoj<8Q zl2qRyQvLKv^$$a;y;4#GB&mTxqy|+psZI(hY3CUUvh$>ua_aWJVPQ(Di$dyHSyID; zN@|2YsZn7_ouH5!ElC|0L<&xr)-9<}q{bpx>hA6?K~qvcAoTJS4~opP(#90rAA zL&98z)M>I!ogUPt&d?`yW*AZzDWuMlq|Oc^wOF6jxnW2xQ%Fhc#Ym9#BE8B}xB5a& z$jTSn5ox^`39??KSBUD83iTS~GNq)X^4sRZ=Rc)soaTL8PwLCv|<8lDbnVDQS}z39`wfm%Zw?sZgZu zQbvk zNNvz373vI*^-4)qNK%zSq&EJ)l9JYoks#|udYQ9kLyv^9UNoOpN=jNUMuMyt>21=w zq#h45%{-%!+Agc_iJ1Pc$#3K(N$TYwQgFMSZku{745_!2l6qZ|dLxL`oBE{Q&Y#pflGLssQt#@MdOr*) z<&)pY2a?o>L8Ly?C-rguq&|_PJ`E!EnLepd&wcMHZR&GL>c2sxzNltW?<=Ifl%#eC zk@~8dNhx1!N4}P%z6l})S4-*+38AX*L#3p?lcc^6A_ccxRx7EG6jJg;!AQ`Ff)V`_ z1+6e2+?$^$q<)qqwKu4we$g+f-@*(D%4g(}-zBL(f=K))MHN!g(##IBG_&Nhr+*EOj6y6IP6k1(W^PwDKQl2orCQoZ#_^$kO+M5(@h zlGM>br26ZV8W@IDN+C5!k~$`c)L?B=R+!hdR;fa2h$J;Mh}1A`QugpLC8d%YAxVu4 zA~i~zR3yynT1)x9&z6>Ec95l+t#4^&j}22&%BOU;JSWc%Iw#Mr=5z8am6WtJvx6+n zY<){Jds3K^Qa+`#C(AZ9C8$kJ)oxQ(n73G#^3|F>O_G`(L~4dMDSK9!l2X1}vu8_E zbAm{ntWRoQ7*fh-Pqwt5vV-iWY<>GFJIuQoOC=@kr|cm6DO=xu$_`^cWgVi7=+b`5 z4zi!J_3fv^m6S^A9NDJM4Qf;8X}76xBf9c2kG({aIzNciQf*T9g<%@HO6np>YFQAe zi?vCG+BCCNQp+W&OM*yUs!b|fNgbv%^vfiv6+xsf*CrLNq*PKXC8;ZdNL{H-%3c+w zO*K_YN}m2^2c7!1D>uJ@^=u9YQqT~J9~uU}F(hAF9LN=e-$N!=Vo>K1)cp@syN z)EY_Z)*w>1X_E?9eJZKjC8;}tNZqMT%Dy{H^&PHM-#wDly+Nez(N$N< zFN7gASRwVIB=u4dsh71$g&Pu7Qm;r-uLhBNO`BAx7u(h_rKF_&lpSP0W$W8dh3kDI z6jE==l6pI+q~59Kk{YFu+9gT78${|oZBq6JVH)~qh17?V)JH+2{-aOolQ5)?Q%HR( zNqrVX>T`WkUxXnwK_MmWr|cm6DO=xu$__N-aHK9)N=lw-<^-K-=IEbk7Owh~PktSF zrkN9TrkSIErdha>Qc1}(&77b!%^dwR&78Vn#;Hq{>XUcZIze~WI{J6lh9h;ELaM$T z(HjJf=neHp^iUoWl1#-Dyb&bTv96)QcWePWFPB`wXIAWJhx-_k4+>TUZi3MqM}nG$?3A&At8)l6!gLTa2OH9m;cN!3hhy+Ue& zBsDRJ)FgdUp&I%Ig_N{jbb_oG9ewLXXL^{WOQk|;hAgR>K_xXyyQCsvzHPTQDx_vh zQgebxovcmD31z*wNg*Yz7o8yMMMvLy(FwJldRQSPtrwjj>qST3dNJJ6Ws5>;k*vNm zgR1W={pwpBrlD_DNJ;BOC&+ry(YIc7&JRQCQH7K|{mltF{ms!o{Vg1+#}!i2deI58 zUUc-W7oAYmr;?J^i%yXBqN8uU=&T4+eaZ636oI*-kFFHZii;lka zVz>u~R~1sydeI58UUdG2^v^sN`eEnQSncgZ$&cTk(UN4rgh z`))=#z{t5*lDaR5)cw^=>TRX^kHdMr#ysid|^QjZ6b+OAD1TuCWs z1vyVhQcnhvdP?6+Nn<}lv&BgN<)`+o=%XRr}HoDJVSkSsFHeK zmedPDCH10qNrfAyR8lWVQZEOQdPSR5s6*Q=<)|m;RY~f#AX2YulM2`SR8nt9Qf~&4 zdP|#Bxaw0$y)8+-6GUoPHIw>G>3#1?Qtt(kdS9DVxV?n06;kp^HrF+?+1m{ z*OJsXL8QLbCKaxvR8rC+)(NtRb@VM_ou9&#)Q?I@?U5z*b5Kd`t>%(aN&O;8{Tf8- zH*Hc*sHMvurKJ9pr2Yyb^|v;uaBWH@^-qRW)CeFIHML1aBVpRq&)$-X+LDwLL@KIH zDqKmaqzWXd!XQ#b+N8quzF(A*k`}SiAdA?jzC~=f>ia_>B`sp3K^C!5eT&#=m=gsp z<)F1_N>*QKQ1#W&uD(!4@)1KRsWM4wzaUaItC^IkklJ68N(YfTK$}#k2Zu;RAyrF~ zsvSh?z-lICE2Qd3QU?W*s;f;ZT$?&TAtfzhqd^w2QGJWpNSIscA}T3q5gQG%h>hx7 z#D==8%STFD#72WGVx#&NvEdqeZKe98MQk+4A~vdT5gV@hR8rC+HX39R8`Zan4Oe|C zDQOWK4YG)h>RZG{TZdS>L=I7^uZMNu=N>ZJINOjgH)g=t6 zLlsg-N>WD!k?N{VD%6YZh;jl>w3{T=J&05fZBo%*VM?l8DXHF)RG%PHef3El9fnjB zg;ak@YCsUFf!d_PRiAR$OjO!=MuY4;qxyE9;i^wLtt2Y#JflH&o>6@}&uEyl7b7i{ z>Kh@eZ)8yQjnb~ZP)9xaNXfGoqd{jcM*qdxi(%}ie58(-B{epvq)yN-sZb{h`beE9 zNsS94HC~%kbV8URp{3HMCQ4G1f=Er)CKaxvS}CODEx*yATYjVZxBP}9)mkAXZ~2V| z-12KiXGUikX4%t*VH|Fl@Xs)u@=ejXYeBHecEbO#X#@WkGTnqnh|Y`7hcGj`AbN_p zSfr;Bfq#ZkP+qIarsyIZUYAD^aEKf|)huHw3!)2+?x5;fP*G$>Pc>W!a3O^=qi2Z} zy!6h)^(*wso&sG~^lVVFBznG3($TQsA7rY$)~4u1_t6+xncR=ZkSwFXvM!Vn<>r`_ z8>n0sy%*pb717JHR5soeU4`d0o8?LjV|g{M^4dI9UWco^F%OkD zMQ;`vuWCh&p%vYM>&$LNx6qtJ!52i=cw5me(2CZua=0@`3is)zaFAK?--X z6z<21Wi6gScIB}IGVKA>LK9n;gLDP1GrL$=gJ8w7-b)&qMsz((p)$JBh_JqYjA6q+ z=;r0MYB${!eGE^coX3$pqcHlg=)Z;0%^=a9RT$j@iA6;3+r+Yzh(sTTL^s3V7MAd~ z99er3Pd7VjkIVW{vi7*l+EdY|MVqS1TH_{=wHNRtva_~BBvBaMNlTAq?HS`#$Qm68 zAWJ(Sv7PYu49n7s(U(Mm^Nj-dXBfrhkYL(QJL%}A=sS3_eRxb+qQ%jdjT>28E{?tu z-NlkEj=oBhr5dBJfkf-6IQlwB4wK#hDauHtqX2iKufX4{@b?=0y$*kGFoN&mE%Za2 zSau72kCsQKg}%pBeiZ$WXg_0s3uP1IdEONL5?9-r$CCMtML!Y69E;KfXfem4pMpg5 z8;gDhk}cZO$1L#@8z3%3b|IPz5olN0jpywfoP<{1zKwo|H=v(zrP&QAle0pZvqGM; zOat=d1M;vZ`g2xiY~19)P0`n7n@JctVWvYu!hb~ngo^d8 z016Cza#W^R!z?h-k}t4v&N?M;mLOC9hJq-rQQ=cH<(oB-Ol>GA)XP*+K}?hgEl^sd zZuy1+vIAB(8w;37$wbO_(EklHp0$MFtX$E|&4QAG6r!*OS6CBt*Z7wT_b*5z3TttN zbwFXQf2r`G0vKdjBdA&;HLfU#u7fOUERoDjCe0yRaupmbMhSBh?VJVm3JwuHsY-RN zih@FY)m2L+uF|ZH)@}o>+BFYE!H4RB>!9Gn^uPxdl#5!cTFh=JXrc!`7)`mE9=IL~ zZmtJD1O>O$1J_5vt@XeSP;gs4a6`1T+v|Z3MN{sm2X2I>+*uEN7@BeyJ#aY+K1vVV z7zKCJ12;jzJ@mj$QE)Fka5EI#M-O~B3ht)|ZjRP-e?4#u6g*H5+!6&JqX%w<=6Q%7 zxHSqMrU!0=f`{vY+oIr+df;{_c(fk4JqjM92kwA^$LfJQqTmztz@1R=cs+1uw1rL3 z10R8cC+UH^px`Nb;3HA+G(GT9D0qe*xGM^tr3dbYg6HUgyQAQ_df*;tBbl!U?umj= z(F6BF!3*`ky;1P#df+}Nc#$5sFA6?O58Mw0FV+Jeje^hB1NTS4OZ314Q1DVc@IVxN zp&ob;3SOoMJ_ZFZ*8>kmd)1|S;2~(rEA+raQSeGV@Gum7r5^ZL6ue3gJRAkD)&q|~ z!Pn}6N21{C^}wT0@Qr%l(P$&NSr2?1n(`Vw@E8<)n;!Uh6nuvscq|IOOAmYk3cg1V zd?E_IPY*l}1wWt%9*=_8>VZ!}!Rz(F6HxF5J@7;nT&V}1gn~EefhVKj&3fP|DEJXQ z@Km%*KB@VeNh!Jq4a&q8T`p$9%21@G1aFGgv9tp`2_P5E0r@VO}X zdp+=ZDELP`@DdcfM-O~H3f`*+UW$T$)dOFEf`8WoUx`7d@BlWsRzCd1-I4%-;RRY>VfY- z!R__HccS2qdf>aTby#6%J@DOV%3bup_n_dT^uYI`;BI>0`%rKXJ@EY~xR)OI0TkRv z5Bwks?xzP{i-P;>f!CqnfqLNeDEJsX@Ixqgh#q(Y3Ld5hu0X-VwZMfVa66_3;q90T zN8&0E%|qoVT;*YTs2p8*9A?1PL|pWDRh^uUyhstqyjkniVnN{QCah4tRRc6)rNjS^S`YN+nPQY1q(N~$paw4ws zs613o!c}(5L*-;#Wsf{mPQg|7%0uN;TxFj;R8GTH_RB-%bi7^m*H@X2j-!2 zCa&_BJXFrY%W{am%BiIsa!ej7=i@5J z=Am){uJXh@RGxyX9G{2EQ}Nz2L0@H7A76;8oRo*k({Pnj@=$p?u5wx)D$l@G&d5XM zB3$LHJXD^EtDKXE%Cm5lbMsJnHr~|d>#NKff*0c|Psu~&Ik?J&d8j-WS9y9KD$m1J zF3LmY5?tk3d8j-eSGhP3l}mAz=jNgE0$k;iJXBtYt6Z9g%8PK77v`aI8Lo0!9x5-! zRW8p%<#K!^x>R3f)^v6W&T@sm%B+#-Qe5TAJXBtWtGqG~l`C+StMX8JIj(Yb9x7Mj zDzD8$+?`~C9d+uJXBtVH}#wKRc1ByRXEEv`YN-U`qj9~+wxGk8drHo9xAWF zRo<0{%4>0z_vE4SI$Y&_d8oV|SNT95DsRA5uFXT`jkwD7d8oVzSGge%l{e!mEAvo! z3$Aig9xB)1DmUk$@>X2sBYCL24IkVd)mND{xZRGc+?I#RJMfHe*H@V}UfzkTd@>J} zci}3Z&O_zhxXPV*sJsVP`D`94@5O8Ud3}{xjp#m{<%{|%vugZ)T;kX^HBLHuJXq`R6d5Q+>?jOZMe$4d8m9GSNUrmD!1b*f6qhZ6S&Gh^HBLD zuJZ3ZR6d2OEHv^^`82N5%0uN2T&10d%AL5%XdWt`!BrOKq4HT=Wh@Vs&*3Ub9x9*5 zRTk%=@&#O_n}^C5ah0h&RKA3(tdWPxmvNQ*<)QKwT;=|GsC*Syc|aa2U&B?_&O_zv zxXL$&GMT;)-DsQesP*)0#1|HW1I$V259xXNC6sQeOF*(VQ`yK$BM z@=*B|uCjj~D!;~64$MR4H@M1U@=*CLu5w5oD!;>34$DL3_qfX8;Z+((75<$+3u6_sW;hFGIm2v94Rh4$k(Tc)bDzk3zu*`cu9f1&>C-2l>G( zQSfm^b&+O#h#!1KHdr*{gQ3*Nq6`}Nm0X#v1i&Yt3>x{tS7n0*gNC4F9IB+;uVhuA zlJTgLCVnMX2P!!URnp9_WOYs@v_L1IN}BtXTob5dVo?jEBen7?xh`7?Fqn*j+xWrP zqu?oMduZne-++RrqTmjG@Qo;V8Vc^@2j7H(r=#E_{NS5W@C+1uq#t|>3Z99AyZXUv zQ1C1i+}#hp6$Q^m!9D%p+feWv6x`bnz8wXhjDq|6!FQnGxhVK(Kln}*JP!pA@PqF{ z!Shk@AV2tS6ubZh5B7uaLBXdK4MFqqIl+ z!4II|Gf?mtKlniuya=T|)(>8bg3m<3C;GwbQ1DqOc)TCH9tEF`f+zUF524`2D0q?| zya5HDgMz2{!4)X@TogRb53WSP=b_*ke(**VyaWZ$@`E>_;PX-N96$JB6ucA#XI*!< z83kW}g6I2F-hzTJM8T){!H=Nei%{@FKX@w&UWS5C_k$lr!55?8tPB1gL&3{Y@LB$p zx1r!mQ1D_u_;D0`DGEN<58jS~FGImg{NN{0@CtMQTf!me}jT=LBV(W!QZ3cHE4m|?FavWf^S8^_xiy9#&KvRC)pEAFdSh=SUb}Jr4Q+~n^ zZiA-07ESpnKe!zVUWcZq;EiZiz2*m>gn~B}y^d^kzU2o`&IXH(#y6m)ZAIz(?_)KmWGeyi zqbU7%{S0vMV<`B2J@7UZ?7ywmJQ=0^I12ucKjpb7csmOI#1Ec_f}be*6q)2d_k%A) z!B3%8^@SgNH41(jrM=q^Mz(RGo_C<&ul-elWfZ`78?l z(GSL#&d;IXJ$^90bbcNM`(K)x_|o|W6zqR#YT`@h7g4bPl3epWw6tGB!GHSm{5}eP z83p^_xSIF^_7w~q^S^O5KSWc073&x={~K5HBNY4^3iiKoH9tYYucKi98&~sF6#NDX zF7%i7=P3A16ddz|ccb99(9$M;@OLQqZ8YU#KlnEk{0^G3>j(dVf_I@{|La)u9~As9 zO1p+HWy?mv@1ZI0=Lbho@cSrue?PbY1%H5o5AcKIDELD(&$azv{BhwUH03&eu#2Yr z9~4~I55}K0K1ONR^Mgy#ls`dJuI~rqj|-oo;D&xM{yKce7ne(-T9 z_$QQh4?h@RtnWd=z5L))(3F2h!F~MTQ&I3<%=RYM&ktUPf`385{r%vJQSh&r(Nb)n zAB?<*_84;ghE~}zekEH_2EU`=A$~Bv-~9&)9_9z*>+U~M@NhpE-@g3|1&{QDUq$o$ zHwqr@2fu}a|3SfH{NQ&nuxX&+v3@YRXg5t1e4-!xC7QB@g2(&8=o-|Fpx_C9@YiU{ zHVU5P2cuiorh|f~_`%uM$5HTnA2@<;mYW0xpW+9bXvzr`ywDGhpx|N@e7YZuJ}#I^bmmy(2Oof@ z?4sba{NUQzV7F^@X6)>&4W`Q2IX@r&PWzPZ$$BbR(y1;L9YzyaSt}u!yKXV{(+qyos zJyIEasxr2d`>L2a?jgC;e|}r+MVTkZtpPDJS$UNzs*Jq>nr)`}Z5c7DM0}S=d>@He zfJOWWiCBn5`~-}wOgN@LPDAX%(+B_gzS z#lAM&*f$1kWq-x~7UV0T7trD5+;Wxb!kkp&Mq?#viE&OqTqUY|R_>U#Z(uZe2KVFa z;3|((fhF*a{R5K8vQ=c!8$KWavJ`jXQIVx*jTi&1S|5)=^6TSC_&-t^FRfJ>uUTGe zbG)fxtdF;>jJK_fcia~5ygA;}FdmNgwTx}?qZPg-#znaa_pgi(DzA(WuH}Q=m>Y6z zWqg#H&4`lCRk9ve#S3UXifq!_ix;qLj*e&UM|l&nNt@lo_3`o0a+dUOTp6FTDL$=n zWNUmzWqi(^M$v#KmGSwHZHw*N7C!~Lh8#iS3%#7Xxbt&Tjy+r%KVw@AUZ}&$7-p9P z;>U|d*}$;=F%B>+m|qIw6AZH;e*8a%BmEF~LP30nr@`{Kg|xvQU_|4K;%7o76&SVS zXBk~tgPn-TToa z_)Gm9R_aUQ=L;IM1&vO$voac@pR>|s<4^p;%J}li_+@fD?VW1~;yt;yhf62PrBg00 zD`b&eD*EndD3X;*Gwkb@*v-2YMJ>;LB?;`7Qd-7zD6`^9Dg)x5dt5-)tj=w-vMEF$!hAq&-nL3 z{QG760c!lJnI#1aF~jUO&UW>H) zfo_A`)z=?D>%Emd(Cv^jcI;t@y`hqpOl4&pJXOtGl-9kfs$+AiioZbhGs`SwU{&3j(=&BvPR~_$PiES@F;TSn7ErKi zn->GIY)OOMnm|al^s1J`2Z%vc42%{T21biq44#q0HywXn498!LUbx*c<_141Bpr*SOm@c8y7tCnSHL04>1~%n0 z+B%q%GMS+(txShj6Bv}cnw2Ix)D375N)x3kI4XxsA@VM;QH$ zL2{lwl+Lq*j0ntrFvnI+v@*bgb)h=b4rR4g4izv6X4)5Eri~b#VWxc%W?Gm+&E}b! zG@IwD$(Ljsnl9Q{muAWVr6ozSoTg@AAc`XS5QB4(HHv;#68}o zc%0iSXH$&9qvKv#smHm8L(EL2eh5GLR|fob17A>0lJz<%SG|6eDLDIapbaBMaR&*AS2 zuYPQp>gIOOor*F{b=yZi;=8>otExG)n>#Xh3bxEgH}85YPV>QLt>8A)-L0Kdx7vof zyTxiT@dXAX!)QwyJ>0lA-un1=^qFn1VNmBE!;lesxrbIoB-RKXlSEle67$6D%Sejm zODs@Cig~P*C)U6c<2;W-`lv{1d44~}bv-{HB$7LXD>~E@aj1K`Cn6`dnZQ#g)!4!l zafEjT2|37=#d-oyIhpy7w9lUZNXKoYBh_}KVN{ZC@OURnFc zdq(g(yyL+bw;4e3O|Ll2$hq3r7`JzBTvhuT~4N%_ONQ2y{v=H-c}=UyPAEiY34xdWOIyB^JxFAs_FV5}J~JMt7J74WlVJ8l=n? z0R+1c06QV1KN-MNx1NJNVCW9!-YsO%sP$x6VWu^}>Zy_pM@A-PjXybH+#n-8Ep&8t z3xz$0*e-7Z>d-nla4X1*%RGDl^)Z#?L~nbYTw>gmvl!JW0HR)!J1U(6mUOh!HeGL$ z@o8HwIO83iw3FFH3CvK5u`M_Oxm%#-Xo4?C|H-XInG7IDFXfJEZzPk~!eVcfF~yi3 zKi+I;wlh1*j&_n^|6@!K=xBDK0S(tEh^>RZ_K&gCa5Br!swHTF8t7C({OeI}Gu;K6 z;&kXyQ`mZRB=o4Mv`3j8jY2XF!W^@{aWI(E=-dvo=&8DysDWi4U7NB2Bw z`#zcNRvGY1)n4fo)`9qE0fl6i@rc}Y2M_HsbNAI@r?@?H7It=r<>~RoP*XBbcG&se z4m%Gz?0lB`0&)tHk<+0A`BzzLMo#r+g8W@O1eGjfhMBW%ZwoG&vnUJRkl)FE_AiLo?fPMVRWA}7tr1>T%2 zg`8Z#a&nJ=BIuTkV7^Je{y9mflsl(z_Z-?}~k*48SucAc!X>w{|ThM*^Aaub@Ra8Jw+NqX?aOm1fM;E9>sBIsdH%w$bW zyx+9WgpGwF=u4C71z?M<_7{bS7dAE3j@%-Htl$nN7GThT<|J?C{TGNqP!qoz=&6*3p~mT(}f=8 zaxaQ$&wA^y(cRx$8tY(M&FqOBZ_F@e!)joY@r?02tPaXxeQ=mu9ZWL{vAvRijKPKt z%K*9p$gBc-v*p1sBkBqF|5oVx&HFnWNBMU724kdIVXQYR&7`@JwX8AFJZQ_Rlr3u` zYgw~l!LSL!Y-5a3hdc~n5#xCX+YDh*qY@SoTOiCa4}-8rAgs_Vg|Mv`14cI>;!J)R#uJ&Nc{q!Ucvd+CHnUvauPTi*vz zvmZ%ik0HvE=_FJ3aXRTy=BC|jWw4h;K9|b2A<9b9B}~~D=@O5!R63QdY&R(TS}J=S zQC6BRWy-!ymwJ@dNY}_#2D@&w+5IT>ZCCZJgWb8zsL|UPZj6Fa;ws|~<8E+2Gxi$4 z!RXP(>}B=^_k44ec@4O4n4g8<&||j1SF6%)`yC=Go?>=1b;dR&8^eHPw9Fsx-H=5&3l(8tI7qlN^!v zun~C_jI=+q5xEzP$a~p{d^d#s!bapPVD$Z!j>yJu5cV4#k&RCv>~}gMn|&ed4+x8y ztsv}A2rDwLfv~?IjF{&^*xwKqH@}3ie;};be9bsGVL({IYHJiGObBzWx)5eTSkgKV z!XglsvSvb<4PhnL%Mj*3SPg44ghe5&ln(L8Opqv$%O`cwn<#==mhYuk8A`q9wyqkZ zE4>tw z-iL0RedN#k$s(Fwsa({L77s1W`J>p@%EW#$$*R{?ANjMGb#{dJLr3xEOnC{Es40{5 zHJLP$-Vbg|HH%s4dC%uSvv`0^4}We+)JE1TstJ%B?tgOIWzos|x#cJMU;vgri36eI zF-xCB9q4$uo;DK)$z1tL@nEDB_aL;@r_DW#1K;vNOR-+A^y+7)XC2_S%_=4(J9zNF1b-{Byhlc$={1raZ!Iio>7E2NBoz-@iE_M&c+KCe@d1{l)S~KN zzhkxdMmF7sfLSEbm^BP|VoWp<4FfZ@Of=1`&5d*6fq=Fj*m_PJUR7$`Ctr5~@7ym2 z;gwXPMW*#bOwV|l@L%;H=<+r+5}Pbq$vVx^6Wid$>@miZT&DQvlK;WJkHz;3#lBCX zt?Y^If_h^6L7y06Q-u{ z8xw=eHzh{E-zfMSQ(nHsI23I46JskA#b0_r7?Bh{RLwPeTT_S0<*dPs{`XUidI$&BW~N0yGwTALkQu;k`md z;a+|CISBmM^7V;Rw~(=;HYOHk8isK$Gu9N_28q+Rk+Btpf3S#&77+0a8Sy+{#6*jV z!oRVIOR^&t8Cb;gy_TtvG-xccu!u_$jW!nX0svm9VZ= zbPzA;WfaRA%S}*-7keAa70gyS(@`#!<$Hy{B7UeSIz-_U*w3%@TC9oEXrPc$hYFeQ zRqnx6BTJ%+&sE+HU8u$w@M)x@aFtsRRk+Hn;|b>q%XJi9t&Blc46k+%%2L=wQ3#zi ztNd4cca%N(UF~b%G{4REsqLB^+O9#gHK*FP#9o9JA)e!@i5Dx1T452d_Zqp< z`hbXSl=cC8_PKk@4NB?r#@bFFej@_!puhuL=S@l@yy??T`M^x=0S&1R53{2l~8Si)CUCaPW`%iT2NUVmHLRZ%odg48h>S+3oOq&Zw4 zem~M!MoM@N$`5!=Kk3u~lt=Fi^q{|L05nE|_LCZg$luQ2w{u$*Vf_Kyv3O;a{corEWSL(x`^BU!gG4e_Y z&r#pc`$tBo?^O~+>pQr}UO=YA)&BzjqCb5o@@xME{v`x|eL39$>&WbZrff>AN=H5K z;+f$E|1z6?$CiM19GQ)+65}B!7FAl^;sm?s`H*~rB6ru;?_$6LHHUuUL$xjB+6A^*2} z5pM?RzQ!B#jeY698g$?8MZBf0`^|mmPNYHionGB<2kBPI0l=_l$#-X8Soepg%fu0Y)tMK?k( zP0${=0sbnzX?zfbq@PDG>BtO+pj0-ci#?^n?1C~qpfa(gqUaVr6fn~uh`u%LdZIJS z9~zw*3{s1-#A99_AG=+0_Sl5?vu5LCw{y;zal4`jzJLeP%%%ufY)_{=ESSlVWC1o> zi6<))JCLWWPh5K3jd&=gAJv0OW?2L(pGnv7s4PpDsrE)xC436&e=%Zwim2Q#y&pAU zO1zlf&!e(tx@NY@R}ht-Au9Jz@6S}emfqi^GM!Fms|4e;MAdWY=ZLZc(g!eQyV3`E zl+{YZ5hMOmd>@p3DEAEiizus|uFaJFCtcg4?7;Ma*~-9@EFmq)j4u#nb<%a1vMeXtMkU1j2XnT;=zlv!Xym5U?r=XksG*UWMOpWKS0 zGSRQyhE?4ROi6{R!ph<}hzYO8Z``AEcKhODi0!JeN9T-97XZazms2%~eB(|Ih^@w? z_WyXk)M4ry_FfW?Nr$Q1MP^}OX_96q02J3qSG_@ucWjy#hX7(#=?9@0V`osqDkkhkGiUj+oz77DKZr_8!Cn>Zj#YUtGsq zfZx0QbH`yk#3Ql(L=n{e+VeU z;;5hc4{pDlgjDK31k@rKSy6O1pI2L^;VdWUj1AH)J+xb;TV>O31Y}@cU)8{W447S6 zcW9!<9+Z4P18ux@x;10pJl)#EzD>G~kNuOC#Vvq+EBI3el%E0% z$-kQT$sL=MlUn#cxnpw1BqQZO^%Gkrsq2BZX*gL6Dx^)ittU(E((SUd)Si_=`*eE- z=$LNr0dz=r@ByHQfenh9|2+XYq93WMtEoK!XI-iJ-{a2J$^RZC{~gmES$2*{cl2bZ zQ@Rt+&N`UaShhQ-JF|F4raOD$9g#kwDxNIopV^W(Q_k>NH#D6t=`IZ4HQmL7KQet} z6`sXADt#1-*FAldCtlZd*Q$6joxQ$vc$0&~x~01@B|X#KJW9H!yK^O;vADRCw-@{p zFgVaYqt?$a?(m$YuGY^l?y#IO>ELib%X*J=55~H8x`&5#&vZ{8Yv^5lAgi@xIsEFj z0QH&j=Ih*E>0V4(zjQB;vfk<5RprPM?UU}q;`LAW@x<$!?pqa4rt_PxylK7mOZQ{= zf$4r8{L$&7vq=wT3HDF-XMmyU{vN=9^Z*|K`p+<#^6$Qu%QOv44`iB#rw4j84N4E< zns&h(4i@j2^f4^n$n-Iuc!Se}tKxYYfoZUpEBGu+&aNnWkWNCQD~jMrECvS+6c=V# zni03Csvcsm(nA+E7mtOb6gC%6@SLPzd(CR;NeYbRkn|A7a#DJThvm@pP|lJbB2-cI z5Q{o2J&Z-2k{;%XdTbhw?4v6>x)!C}DvPH{YDw?A3^-|l{|@W3#M|Dyr`S>s&pTb8 zB|cPR({_i)X59r2!<5sPnPQ(E=89cWRKd$(czQU?+>G>aPv%CXNAS#f`mVZ;GHV2E zMa5S^MMb=9Y6Prppf@ zsD0(K>|f>b|Jb_@_$Z1lzPks6WK%AMva}EqAPK#Rgla*$fHXl4kS-bxEb_SclxH1`YG%4#G#-6P>%e?bQm{r9R|TPiIn*S<+4>%Y+ASrk-v~H;G|2f$u9p_X)8>J0pGhAuI zuz6j1onZWv~oK`E{7*5@l?kuOZ zDyQ{2r~Ga>^-y|HP8*dT45v4hH(5@bRZd%VPEl?+^;CLNPTQ5945wa7FP2l1%4wI* zsel_!y_MdS(;lTa!>Nzbhvh^90c>|b=M?RRQ(vVo<#b5t%W!&2d5h)r0p-NJRTtxi zQ$M92<#bf($8hSe^k+GJsLFIwm#Lr|P6Lzyl+$Tt0K;jZGLYqTR^{Y+fwPbsPJ@&| zl+y)e5W{J(GMMFbS>^PJE>mGQoQ5bvD5tB+5QfuGWhl!DrpAcI_1Q5o)(xj&$}r05 zYh@V2X}B_+<#Zh&!R~0#r0WMs%c`JGLA9`QpPb1#w+7h z1~6W!6Q2|klBqqH?Ms`?yE2)1c8W5^#TSe@CSj^Fl|GkKnaVsjO_}C;j?Jv) z?NvSYOh`}ls9O7UWjf`WOPS7aouSNNB|RR$EhG{&2Q#VkRMil8waAqj66_^C)a-g3G(E`cePF70N)UJ`^4qeZSCDX^5sVG zVq25BQTd>5v$pKwzG^cV+b25=tepuQ5levgEK!zFg*8x?FbZ3$EOjZ2ZAm+m_sGbM zEO1<=ETbG>QI;_rmn+LXaeUpQZU{%&*|7GU7^bJtt1Vlhte|o zV=4$VZI!Z$vTUlXVpy(LR(oW*!-OT*AbUTLPZEf|0Pq15cOflw7wBLZBDh0|wp`+D zpXh%jo}79Id^+w4>8|~_JEVsVj`^>&C#1LY%zyO(__%lMp4>~oBTgTaeFJ3a33`zs^OHgr z!BL5D{!4IXI3sae$g*uAtCK?3LYwWu`$E~BZ4-#((r?Kk8gV z;AEGO^Q=XO({oPU>yw|x8BVvld3aLLYP_V@sLLAiFw+7LSSl;n|SJP(%*5d3W@#MH??2@wk_n| z9y^?)$Es@r9TT}%tUdF=z=?_e-^VA}{gUii6E-QE2te2aluZmkY*se2NM{e!(dKRT zs9xwZz>KoSYKsEl2&{sYEexxz%2t)t8D`UgIFWsIGyuMsWVdTQ<88_|$|g+N#<1D0 zKw!gsv9o7v&z|gf-pTABj+_xicC!JN?@)G7emRvL48KGrQ56d&-eGP$2nK!dY?1<~ z0ZquIBr(tKRCchuw4%nvP;=T6;eRi#VBOA0!XS(-mA)E8!*%4EN!}M zxSDd_qwJxaW0XA%=e^2a7iXTU$xGqvW-W21$xwh-^-PlyDWmF{$#l2crRvyZs^;FM zBoS&a24)GgN3zYCM>`Dett^vm6j}BKY;A6%1;g!dVvTDUFwbPgC#Vi&N?Is_FJf~1 z^xQ_xGt(mZ?AiE2o*fbDapIW0WTO8M>S)|v+AgyU=9?XQ&2AMD=bJ4P2q0W(yFm%_ zP2!235fCaoP`~QNOXPW%0U61-tEaQaXw=UlfDy6X{q(_ndryzW`D2vl(^r?=I|P|% zfUfCH=%(4r62wiimuH)`z+@qq41QolXMYxibe`|%UepC4GGC$P$2WHMrrT?f!FGR`gseF7k_4k>ts?|8@X9V5eFyGz1Ktb~ibW4PGJFz8E{ zgdD>q-Z5NaWC+{S$ebiqCA%?DTuNWmaUa_J7cZBZEP#@UOMd`T_N;uNULGT!%{+V=&+FcF zqE_$fEHxNT_bY;{Rau_P&Ay|=;3_%1j++(bnV3W$ckcXh6YD!+oSf2c4&%#B0EDDC z=j$KSbsl6ViV z(N$h&k5#7GL)ZN(qpD!=@V)}`EHIjSL3y9);_p-Tsa<@!Ifm@zwpZ8LtYQ1wWDo~z z_AC1-n;Ob~hRp#5W^D8=;jkoPua#u4P0hnB53e=MZxVh7m4lRDUF9Id?~rmRIY0Oe zDVW>dP?v9=8-9lsm@3v0CZ;Ho6h(m~xErYoi=v_#Ib{C+F8r<<~*y_nsSmA1W~W1{FxR3EEn&q;AJM{`vf*nyTiAnc$V3EK_Ox=E zvh1szW>|ite58q}FJh^mdmfW;MuAy7XjDJt3{&E)a+WRON@v@=JQ^!h+{R9D$j9jJ zI{P59yUsq0*qO7rOLOx^Ce17n8#HO0P9<9PGwVY*7 zYH(uCW#uxJa<+1rk@AXiMU_%rDk9TAc5X`Myvam$P#s+_=iSu!i2`%$fLU{uPna4% zRX$~F)VB%P7wF6`a7tDo^Qv-{GFzlvWte@Yz!bSl$u4F~VA-Iw;p^*HOiZkP%qrn? z<#SrgGUaoomTSs2trkAiuh2tU-Mc0q>Q_u=j+j~VD_oynZTS}pO!g09`@U zc8AzuhdnE!=TD=O_lT0&^s3oPGAtoOcz&gPMfJB)`HIos*9xqksGh^y^lGRu#$zLS zqr#)3JU+@;^(uSd4uqq&g7A&<4V7$@@(m-|b>%vhOj|+NrgkaF%-X+t(Qg%4;Q^=E zp?u2}{Z9FgE4s^7^uAv7d*yptbdT~qQ}l)ct3sd;t=9dnqHw?@>ED1Ve^7p)MGq=J zFhze<{G+rzxCknq)!KenZ_hdR(SvUJF{z=c}Ru)J**+Z-UNOB zf&FiliMH08OfLbXTR0}+j&g^p^@#Kfjv|2e?U{-%Wbm%xLI$ z!)S;|rwwsK;d7#fA?_`9_~)Dq`B(XuHae^FFVpCI$~~>oq}LL(M(>^6=JrQJ&j(J# z(W?whR^=b|aIh2eavmIqqd#s>_V^v+k?=p|KVCvA3DZTnYhs!p z_)7U6Vl#W5m1MekpaX(Q0*77x_PcDsdnP-`=rHVW{%Oza)HFQv@=tpnt&j?aKZ?_y^stP&i^LG#VJt z?hy!>353W*1uRJJH~}*QC9_LF=qTxNeV>IAm{B7lB?iC*I&F0pD42yZElln>rhY*2 zbNPk3kzN}%gtG7OOOi=KA?s10MM=XLy+H|bp0fKc5w{EjPck3TgU&k)LZXt?o$aCI z5BCyfqDO|f=TBbZ3@xtnV8zO0y3->uAOdQnipvVhfu(H-sFLK4Q=C6g{9V>?mIwf9 z04-6P+;Jsjpvbza>#)5&DT~Prd}tX~_$(%`Gr(L^Kz2>|K&UQ|ic*f;aiRnPB`BHj z!9WeBCCZaKu0#k>LR`YLZ<$JdUJLJ+g77)PW)ueFZ0@TGHktdS4dx6P zY;t%Od74f#8t2EPV0&keN~Ifb!b58&n@E9DUhcPnCq2KU!R-=*Cp{k@6C9ivkVjRj zeJo%hJEG<16HjNYQeR!jcsVS$=ryu z15`kR;e5a_AFZr0x#KD$oe&sHX;U9ytEOx<+07CzJK~VCn~vZT17bj$P?)IWj`x#t zn0B&RNphIXpOd6h$muxwp+Wg+V_T3ruCY--ft*en>zoEB9Uxe|3~j}9fC|7<1t^C$ zC-7uco z>>5wOF&q4d559)R55GXk`;tOCIdvTa+K8c=dV}0?nj)RYf-X(5rp%p!DPvs#7TT39 znAc2qFl$Uhs}NLNhzix6+;KvY&Szm=D0Z$w%4?!O+L43r2I=$H@U-XG`{>yntNEu} zd(0i=X)1Rt$QDcG?nUl6x#NHm=U#60tN_m)Q0}NuDWAz+Xxhp?tlas`W-*D}u%Ye% zIC%xOP$YF3_X3gh3LEPgMMj#WZf@aDiZsby+>8x0((}$9(#Q~Ye>?CkVQQSvw|IGL znm^s2eL6qw47%3^Rrf&t>0&0l6Jf57syy(N(_`YnE8?lg3?_G+#}old5#3|xNj@;P zD+<)2w8T(y$CW4slwz(DtY8I9w%qVpwSdXe8$s!!&L$jnHla9F3L_*K-V7&qoIoXj zQo<#WvjiCim82y`k~^+MDWH^cm0+6?Z8G5En-Fa>@k^ReoFuZ*@Q+=9mSRjwQA>|! zrHL`=p$8-;29%_ABnFgrHkyp&VEhScdYjyFjV=R}GFqcakBp*8S)i7sB_@$Ot^^s3 zmD5U)shiL#tZ=a=+vNG26Kj&a^$Cw>ptfhIB-6+pCkYwkmDeTV@Hp1QU`8p-r(J@$ zj2de)@oVJkc}KWw`b~=EGAcbAip=vo3r%~LHhTuS8W(69dd*4G`zG0ph$d zKmyd3KqZ+&?l?&*0;QrZ31@&fuMH4q(n%q1z#AaWYXiiYZ5@S3EK8yUUJK&8tnnt= zBk@aDIKe=bpy`#US{9HyPA!#zQdv`r9#d6-T7{NaMDDl}Re@5~RYD&V6*Iiju104y zc)A+pw3ys+oSp;9b1qKKcqY>Y&(ji1$sJeX1)#j3mC&bR$w2)@T4Fi5<4RNqN_D*i zXZGSI8yNWbC~h(~VB({=VNqPw02$xEM5S9v?l|dc0HuZ|9nn7Dhbdu}uy^a4FTw6) zQ}@Pz)oTLpnzY{4T3>88E4ujA3=1VQ43oVKwgiB z8Ygp3FH?;lBzK&~>jR}et8p6BPPZoWLk(!b!{m-D*bpcUwSwGUBw4LKSnG z+;NI&1e8WD#TcuvVdA`uuhno@Jvj=E^v1}QtX|%RUkBQM}ZFdq}hN?f&g{booQwNtlEL4QrDZm*L&PPff~(oEAWK)Ii@%&S0um6rLA+;L@^1Esmk z9n?KadV?F9AV1>`4UH0q-T?H0>AsNpkhD0{H8y$El`JaiE2CsWu>}?SM{>sr{TfhS z(}lj86#BC+abvrm3)F*PNEZq(IELQPe{X6JF#ett3d#+=K`xrcT0#XaY309@JFapE zP#k*YTMZg(W|G&qolH_QlTHAm+h*M6RX~o=+p2C!!+6~`H=EvJb=wM>(26$i4!Pr+ z*BU6T_2zN9ZEnyl{eC-*crtg}hBCZM?l^|81LbvJ8+EVU+lRJ)kJD{}F#C6O4HL7Qx`}3f>5=51{3=X4T1eI_)guWIX0#nTTAEEbH z&~9x4F#(C-B2d?Ve1TUyc2P+8C-gSd&KG#YV*#d5)0+JTCVAC{G~)~4r+;@tYQsN5 z-%SaF;}PTcg!#GNK9Sn8pXVSaKdac@9`xOw*dolI+;O((0F(~Y7D1)J(xh@-zwK#U zXjXvU4)vRkP@*H{Mi$FEa@;xrrIW@js8muYybq?UKP;I35%3SIqYfsgHZu{`ffI%3 z=smq#9Tt|XTiu!c3by+866CnfAYErFc?7xRB!2@aZ@7HY+14&V?LteCCBH6QiLOBD zs+CASNz}z;FvRy*x|n1}eUhjf)YgqkLKgnIagvZ}{O-CW++ekf$x^OS3ePW8B%h<` zV$!iU^7VX*J<}iS!i}3q&$?w&U>iV9?0eTz5APWEFfyd!)dP&#gBqGFs`lUv{U%V})C^5$U0@t@&Gm|~ z*=x;GPm|dQ?(-|~B>CWu`(ZL;vYv+3Y!x1Qf{Z<>{A3BYCntX|p!71z4>(IrtArt0i%vQ36pXK#~E1DS7o(Fr!aK|8&v z=JJy}PIG;L(nr;tx-d(_Lr3a9+$yAo)P12)U&@fI*!JZZz6F%Gj11fB4Eq`wQr(cl zCO}2pQ6^G9Q)MRxyaY2jWI!;NwPk;k#d*5J!B|WG6l$sI)L}npRzKQgvh>=IYjS^} z^mjGc!wUnXfn%M!=^i*hXT~40mD9=DxYv$*(#(T$eygQ!dDbIjQMxGPA<2k{=llJmy$7l%Xb_msb z1#-vfoh;T5rFwV1wHH=J9TNmSpBPYEd-V>CHw+#eMwyTmrePctvcNu^WAdVlNnNl) zO?o^J6=noHJA(2d>og-cK4jT_q~-*&E1XpvdDEhCAoV!fA~MrDj%(3)pp19lqG{f>XqvG_ zVKB!ZR5KH|xqQ0UEt>94iza~7Fs%tgelo#0fosv*KzZAJi>70m>BjV$SqV%$do=Y)$=x6?2w1Von87rcyD<{M}SeOtQ6PntL&4c_-$q zWMZ}>Vsc(Q+Z!>bgDBIfm}K&4Iw$4~pv-VD=4|i8oNW}7I@(O&JCoK)rl@9ebHJjE$CX{A#^^naaa}4#+$zZJ>d4QXG z<{9e=gGnd)ISCo2hv`sNmuUgr0jN#bL6X;>4eJ4a^fcz=g(fOx`VI@-uqDSMQO(YU zR?Vd?Cgaz+T#M%cWu9hDX5nZN+a~gwq%J3!uZ6B;@-E3@??hefMpWl3O7~RGus4wJ z>@4w)^AeAo$-E}WOg8=UoR@mXd8tRv_9adw&j&@$r%EPc`uUua7XW2}rev}ifEQx9 z$uu`J!Mfa|5aiu1+QTQE--S@wLMjLuX)ojiA$xunxddV1YlU~Syem8kVPBvQ<@lMq zl_u-1%v9h?Bij&orH?Fig>?l4#ygLKWMNn0m+t7sY#D{2`4q#Hnmijnwv#lYtrT5XM5M0Y&}v>mH{VP z1~o0CQjjk9GENGz6>GUCDPHzCEoqd(^9w+X&#z@+h)fZK_6V+l-gJ0d0rIS%vXXB7 z3QktCF>9rJS=X7ILBPwp&SY^_pZ#A2HLapjkm129PKwn)S?x)RYF=t=oykUaW@NgK z^-2QVA+TCYBMJOc9>9kD25%QO-v#;KrEMdFhj+QQtpUm!y=`11Z7@Vqk__+XhLqMr zW1}%NxUU=Oi&C;{U)p=z5(Kz|UV;V_Y%iv1R}ZGOAlzCiI2j|XBzY?|(ff>jt1~a4+i?lc{UojklOMJmWxH zj1Hvhm|Ll(-2jqrHiB#$soZ2Zu#uDdJ)pejUhb`4>v*eoI^OC=$F6>b?oFYjlR@O( z1hQ?Sa+C4FCQk0nK-uhG?rmPnz0Eth)#DGD9${#4HDF1!gf(FUc87_rxzx7>1jO8;4%^S4Ml0c$>cIW;lAJGZ6y-vRQ&xQ;(jVV>0s>V#6JL(11|BQ(cG@z z{V8m-*1vQMGArOMnj5TKBR)qIs5Uu@$+vn>mT&SQQzvFEf5_zfb$XKzLbDFiCX@7i zkZbZGpd4bGOqFyPsE26@l0*-4B|ZSk2d)ylH2FOS34i9sAb1ihGkMFDcbH=)V@O?lN1(k&s4hriKEmnZC{T{NbYXOuV-&;PkGgn$@CV~+@Occ_ zAEQ;1+mQcrnn_|E@3_~8y&UJ(py14;fWt{a zUA6^vhZ}oflDcO$2wwTs)(3SA`;gtM7Sx;W415JFzSE`plc3&{RP_YaPjae11(Z{q z>e&XIFxhnhr{(#o8<^S1&9f(X^xoi#a}gO7!?X6=S|K$}9I*AoNXTu8?4tfc2myoGdf^wKGQR#-Y`ujkP-xP$ZH z$x0rdvR z#2372!^a@!$FvP3wSLUC;T%xTxo^V-(>6H!F6W{AdCHq4;qx5t3qZNxiMN^MSjReV zGF?JmPkt3#lO~yqP}@Z+2}yw$IY}-7<&sMhfPmv{9p(omJNaJ*9+xS9lCmyy{I3Az ziq0Qiq76I6^8dtSg9blV_=M&H_ozswsPup*D-yKXpFq{0P_YQ^e8P$KDNsID#UiJ- z@FJP)mD$HXS=gh45|L!~Thr1fCczsFdud$9R$MXb8iQfs)gRixtI&w6w1Fhvu5u0h z3@D#zdM5+6uybq`S54MfnYSdba_d-ROryPL#=XV$naL+;;49(*Euml-c_)X=N_-BI zeNLq&zV|sN^);Ye)1=nlk^KUwU(gc7o4(*mdt?Js)wwABJ(w7%5O&1uwOivuA3a2%B$wONwYNTYfV&{f0}}1y+UMnVl*G^F4$0am9CBH^PoVs1sIsH8%CJA6mE1(wuijR97uepVRgwzsa#j8Xl)nsB zb|&WdD>0ypRy8a@gmJH3{cf@-&b9V$VE;F*`ag2VRs9c8{xMYD%^A!8!f*f5au3KI zSMDBA?y2R}8D-)!;UfIwwz1qYP0`Fe;eFtDpVSqencQ)85vl*Nu3zrTs@W~_)Vha zWOB!qvjN4X$woRoRI~7rN?x;fymUM%6Y$GK>k1)vTwS1RDKjUduGu^6`Vu{(mdHUg zD`kOFSt!R)a>sE5T}ytN^i;E4xcq6dhnw|TDJ$^FO6v$GcU&Dr*Z!Q;i2<-9hsqWJ zzXi~8*~lGNj_6v}WFwjl&!IQ>FT>)8`srfIG7yTvJPo*}Lhd-0K|l%8Su#6R_1PR| z`iN|Y3fl{qt!`6t&G@*UNea)M7|`3R3ZB#*W$2E$?KsK&XuC)MGEL%#A(u!$~VtZCLo7au9rO>DWTBEXq z;Mr-T3X?moQ8|E;gKLzga^C$irPL^`nA=8W^14xG2W%7f8w9}_N2hGVi?B-1VzR}P zVqtZ)P%*xc$!U-@hvzB|*f}ZdBuEsv2ma^HT$myC$edPPkE(pS_Vsp~&}O4rf-s1IsYcQJd9-pNZ4b zH5LA0Q%wZuD|R+NRug2;RCrmn5znyvvYKiFI#5n0fp46uiQiNCof7$@;(H9{tZtH-7HUSeb;0)99`)ebOb!wdsL_}Fp$qlB+B(>n9iG4m8)7mRC$ErD zr(i`0F$rvLp4S#)vU8XbHiYYD0@?-s%m~Z*qTN?v?OqFO_fA+lFYFo-ru@m-yv`Nc zPxN32=Oz_Nt4tg$!sNvy)xkJ5M3{I1?_d!o%X@AeEW+-2|1V>+2yRS7TE{vVCu}y8 z$tPaeY$jTu!V-L9T``*pvNFPE<84M9%#Fda8=i8Gc5*_OGAHeBRw8#?caseI6ur9% zonc>3nV0Rmub9^HAQ^$Q{R|SYLr;fjz43fdX+A2@^W=^bC=w`CyH!9z`H$(1gFti_y#D)72OEENJ<6{2=*K<+p@lG&xgMmyH#>=@&<9cy!Tj7iCkwYj7b z`XkO;t9>Lhi*W{~^z?W(~0a}niTi21?ajmNel!|)m*e@X3N`(reJ&NJl z{se8y1& zjZEf}s!>ICBX^vlo&(Br?iE$mS4EZeLQ!0(mNl7p=M!~Vv#vPlhS6~t)s@2Ps;tRW zDtk&FIpB{!f!0>m-q@pUygUKVR+|4@<5n@BP+X`iRFfS-OQE~aQ+9-x3V%MlI$W=Z z-wFRqc0|Y#c_JcZN4CGRXU#6ljvPTb^5uwvYo#3Zax{SJ;T#uoT$UX*Z>d z>vgzJ$+aZca=7l#bvD;|*^%2Xch20oWk;SKd4}g11=l-yGw01JJMv!3`)l4?vLoN@ ze5>=Vl^v0PXO3UFpy>jt-R_(FLQQiH35~9isb14}|O7=rz&n;rdnd zt>`$}A{GfNk`1nPinJ`!8m@DSyjx@) zT)!;xdyzk6N71;V2}LWzwNKG8MaRQ+Ptj9F&&ZBqnTlmAmJ_bCi>)pOdMtLS*!RVL zlpV!O7k{DnOK@#f{LSLM;X1MSqT);7x~=#J#gEC35?M?jjbCV!b|xXvrH zw#){&-Yj#k%>QIZxhdtAlmq)b)AX56&w%|B`X@|Cm;~3u2^SK;&no&?%vCWjT$@+y zQn5Q+$5xzMae?fpG`G^4N?@N#zgHG3XObN?FVy_DCiqvaT(yeSDh}5!wFcK32G>2c zPSt{T*A{Ds)dqdlZdki*?GA8VUVB^ZM7Z9nBh|?)JL+O2BdRb&g{jmDc^$WpuSN#+9Ps@%5@eL|Ar~=pi4JI@Ic^h17@M{C`&xXAk zj%qkocD%CnmBX)qeH+zj)UpxSr_s1Z^BOIL>!C*H8(o6y{l-C!?XshB`NlOH*MaMm z#y>RvNp>^|Xp*~0KDf4T@>UbjW79cJ-)#zZZT54s|6Ubj$Ey*q7JM~Ub~G>D{DtOV zuNH+{JlmooTu-#P+Txn*XeqbM(-PvhWx1BMTh@~uj%JQ-jyK`@cdMXQP+zNht=hJN z_O~9_dQs~oaNX7Vqt+kGjy5l}d9}@JaDA)I#5Pl8$LmdA@A5k6yKPY00&NSzwQt+E z+fJ4p?fz{a(mqUfv>(=fR{OcKql4Tbe+RH@2SU*Q-8)M&?AUnFQ=(@A(9=KlY`eWChWkHt)*|RkRAQ*_YdtKAv^k)>tDM+=x@Nw1KJJf2-lAWd^6xX*)b??P?bT? z!PPOS_aJER;IP4k2Sa^>rwv{;c#Z5B(qqWzA>-hBV93QGS7gV~yhBS5EhjsMtsAy~ z*de(7H9T-Q#QX5A!;cLIJQ{v|_}|0t$&L}-M~oUVR(6bPI;!ia9@)S9savP+kR8)rnD**4u=})|(;iHh zWXJRw)8CyA{x;*;8TDo~fa}H?hh_jy&WxBDH?yehn3ZK#?pffUv%Ah7F?%#z@67R^ z6DT|8{5LmjZZ_F5cl+EA=bn-s^D4}Hd0s=femC#mc_8QfuJcFChvyg6SkQ6-#KS^i zVYY=i;kt3*p@qPIQTs&$7Y&ge@8o%>)H`M2`uF0X#UStE>Wf<}cEI($#fKLkl^sj! zENQc(o$Ofp%F<3tyTJ9crN1u)yjvEztn4zt$z@+G`(xQ%*|GfG^6!@euC1`G$hji7 z>{uDHGG=9AxK3QTbS2n%<$;wKSAu<3C#ldtlM|Nz;y`kiWGH|`WF?1v7dE>T?$2XpY>$e;K z*?3=ey!YFtOq={<$EKJ~6*fV+O~W?L+B6rgTQ(it^r7t79Jo1Za|~P;Y~HkaD_l=) z{%Z4e*|DYYmP%Wy!u9S}d26uj*!sV1;oGvyj%~fRjobD%T)*A+&ox(4IJ4s%TyG_2N%WT;iH^kHiQun^n-h;D9+w?S z;YqPcMc`T|sZA2-GigcE_M{})u`|ccqB~2#b=JvCpVnjBs)&GI^E}VKiP4n(3y&706)*1IP=9Bh~JObeEj~$2V}=N@m%(E3S3v6 z+kNhR*>Pdig?SeMH!pmC;nsyavg2a##psKL;JV`C&WnH>mquKgb7?+Y|GXS-hsOsp zIr#)!C8CJeg&6&5=;0A#r*;k{8VX$LPBUt+}RqudRVv0 zP$AqK=2`_cs3~g;*}N@eESSTWg2uv%uZ4LAFABLIhJleu-iKvkWE7biMm)1vAu6@Z zG=?PdEn%idZZ#p=3gI*XRUeEM3R=ZfV@z6ZDN|ho<%Pml3abgMX(G;Q=2`_rBaei+ zu9<2=kw+oC)&Qy@v6WElQB|TPLI%<%Oz`QyH2^LXGq!7%yC;P%FI&rwK?xF0PO;Vl#xW?5J|F z&?qD5m(_8G5mP9k>Lc_z2%zFJfkU{ReXjNURVBh z;kAsYeAWONwgI{k>IsgFY6R908M+a=F$xH+GqN!>gQy9uitu_yZ;Y`)?Vf}N@r`;; z=ICP4K+5l*OT5@V}tuV4GlIn z`mLv>(Z+`Nf0`O@Z2Z8dt?@<$41O9FU{u1;r&S3?MGSwM6~QZ`iZJqNR|c<;=Y-Ly zkoNj39O|sdcwsCmMOBLCEo2D+l>#sN5QUI``ZD*k!gzERmtI(hLB%i*qdJZA{jJ8r z+vqgB)3A<%$}u<&=RDEEBy^tS&ciwoD#(ok8JuVeI+1%PVjT&U&W6vghwt0&ArzcTkL*0)euDfku#TAPJg=v*l~7wcfCFfSa8bFxCh9CR}8 zoQ!oeRGOELMwCV~W?&imuHtxM9{QX2{-*hyI`7+DSb)m&O?jFE$^0-X&xfETiqnHv zJqk(~BrHPz^WFb6A5?=lQdo>id^ja)iX_2|N_>c5)`D7l>s5>umZCF0yfd;6iHb~x zLlQ-@6DzfZ<>;5G^Gnt@QJJaqO{0Gf7gnNwrrtkUA4P>);G;yL>iMTvwG%~a3#-vp zt#MV>T~VnPxodKl6{`zt&}FT2S--&gaQ?F(JrDmL2>!x)xB`tR9{*XO15hPQkiY@X z0avM>9|$#s4X9&FeT&gC;Y*G)SEo}B3h$w+AEl}_b(2XKRJFB;Y4B>IYVAG#OgV+k z=-7|iu{GybvE+GSE2=y#RIaI=U<#`IkzeJNkiR$$iz@mkn==iC2cF?HK z!wbh}ogdZjQXQ+thrRbw{h8>j3{1?>GsVTM!fp%$-Gv`k_iQ;Y?ZActn&7d70x^M} z4;l)4F%TYCAh5xJW_WDDK+M4B2l=Y755wYdhJ_Xy>RenE;Q*TBahroTNe$r;nj}4# z#Auce&@Ac2EWBx|2uIO0>B%&_d1?s9(LCwRJVq0pKog}$6B*5P3eA*W&BU9kw(t>} zDm|NuH&>i+7R{C3&83-)Eb*eb9_y@*x2|F%U(a>E*SbzPhcV`@;=Fp!hou3p_%X{4 zuC1SkgbQdkU)5*&{3A3QsaM+#fM&}O5UIHe^J1oyL%4)7rzysg>m!aiE$-A=^~J&! zG@m7A(=t*Tn2$H%8^Wh(!i;D_-i$8_pP?Busu_7xI)rOz%8YDE&75TTj;72|eN%UC z#}4f$314Dtx>M3a)6%HJW0X%H_KW3(uhFDN^`z?W$7E6>vo7^|;x>8g-oV&3 zivyp3d(8P(lUIvhH187^zsY0xM~q?3?=88elNcs#(c&0Q{6xla@>u=}W7(1zPDg!d zwmn)rqnV%Bcs9oLJmD9NX*LE@eV>licw>*tK?PfsbZ?Y672_K7d4d@NGZ)r+xu*{Iacw|KJ-K7ObnAg0$os~|)Qe_`NT67Zl^$|nN^J{$aK{--YZ ziTUZkA5McO$v>O$4`RU6hyg4PpbI>eI6zzgjzXqDAp9)cLm+rsfj|QT_09MN!hh%r zPqQm7BgdCL(8?6Tr)Uk5FKc^fv$nL!QcjQjVxqevvGHGO_6pIoQu&JKcyi9v`dh$)^ih3%xEt01nJ;0kdSrn3@)z=FVH4lFFVpt~Tr zqyR3&UD(dc1u+yc1~DdOjA3yGT?TQ+3!E`x%?2?Xu?DfmJFH>x2Hghn#!I|0VonP& z8)6P(j`x_u;tskF;*JlvW56D9pqK-(2eHRD?9uRtZhR2>iwe3Bx{&WKq`48<7=bQ? zY0SqoriEN4f!u3$LdcdRbv zMNIN0_Pl=PDZ?b97Y&!tl@OOwflI`d=*~g?{Yra0J<1&pecTBDft$e_+HJ&0L@ck- z$QyG!g^0zX7P=FnmN#LN!ZZ5Dv#-P`1SkZkhnsaW>Wy@*)XB_pVl=vyQ9Y^p`zg(P zn$EOdJGvF-zZ7zt<}%(~v-rvVjBhE6dBuVVUfyWW>t~*F@FIHB01RCV0n9=GBd*16 z@}3|TM(pw$m%K3qViyfq4ZqO65Wl<$8y}xhF>EWHG~FP^A%-D_Su-bL)T4%D=wgUt zK4O&7l|22;V3|}xEh|Jn{jG+DA!`~0Nsq!Cp*S0C>BFZOSOZc zvvCe))Tf4P=xU~FGO8`bzY*7x>C>?Dd5l;B;Vnf!V&N;Ld-SmTK(8Il4Ewa-&94O9=XKK>=hj})efrR zr#c?$D%L_5MHfv!;~~}-`mkLbEY?9cWmS{vdqh%8kW{mS)+0qXwN$P6=8Uz-4BsrH zr^bnqVm$;@EqE=tBA{9u`OaZJ?WT$y#QNy2mbj@l@5f^$#Nf#A$)Db@Gr)oJS0#9kUeqbpmhdUR!L^_c=d6IV8Np3jS|5ua0y$*khh zsngu4S&T+^wpRV<&erOag$k2t54&2$H%|*Gq#6{-4W0&0dma(=;`Uo(^*hQ zSGU$Q=<3$$Q-hFHT-l>(J{R9aY)5Q=@}^ykHg%0pw~M{d<&Ek|)!&Hm=?>#Hd+Kg4 z78CoR+iPmEvf{*r)$^e-T!;BKe|7<|C8UxH`ZbNsTc zhyO%Bp*(DcC;Qr-;$dMgE1^@ zqYhoe-sqQY zqv+?HliDhd#T=5VoMAL321|wx7B-JyXjp4X3=M1bX@s6M_?wPD;6o_n6IDmW@t8X> zci>!=(Fe3~2!@BXc!&AJT79NLzA%Oc`J2xnZ(|N|r=*9bVURo#K|<`W;|1T=*O_19QwnQdeR_hX$3SOuO($^{<{Hd3I9KMa z50G(<`h~~W#5ou`-m1;3=P>6yu{lSxzbkyc6X#+0Xlk+KisAFbhY#@+ZDtL_$69k^ z_*kpY$1t+-21eo7NBSy^_^P-76OcC=^ZFT#pr;~&*d&A@WUa|DgsjzPI!!_(gtYUA zg(2c1OhjHM8E-6#QS{VA5u1!KjI1>~hLN@U^ai>f<1^~I&{ld*zhm$?9B;!bi(kN9KcN))f0(`tOrS|>owyW}l(!o6>N$+8r!KOH zUucO6!^v9nV>nr>&kT^LNI0>wNzY*xe9X?PWoBp1KPL>!^&EG#e8M0KGQ)S@+IUTXI*vf;u8jnt1)N!qP!HJ z#o&6XgNyiwmbWmptaSwpEo=3e!SWUfEjD+Z71vvl87MsXb`GfZYUd1$E*IHO)0kYR{f3&5Drtkq{aN>aXtA-@o|0dtwJ z3N(El0}TU>0S7IgVVGI#78qvM>XUIHh+*hM7-k_^keolhl{tUBytogOBPK_Sk;w6hqNkK*t1Wtv)ko zc=-Y``WFqii3cz-`l7iMpT%gzXnY6+(UK#EqqXjX;b^TsAHua$gv@lvGZPsF|EZV@j)$BVn|x+LKu?P>eC1JwiH^^s9rWC zGcz+g{piQZyWr#wPVQtxw|-J&rjt8IvDa#;JuyXMiu579k`zh)M|@E0wPHwG>p~ck z*6Py-_qG&T)2LoGAl**#^bn6@y0p}$7@HWIKEyQ}n_9|LPveLcPheN5j|n=f$VE;Ma^azC=uPVV+V>>-}Q-06!#Q+yT! z6a&-;P;nQaZ2rXXwAP(4JgwEI53Zgfbf!aIp2Cx!h~>9xLi0n@9cw#JynnDrsvy@^>i#bUTx>s}bH*6Py- z*S8dQ)2Lo=!_|;xhl-al&01=2j9ZLbA7b9yxMfoh&dL z;d2fWoi1)9Ucp3bskJd`F=~B?cweHHO|}@e*18#nt+o2}Ap|Ui-!!V%*RZvbEbCmN zohW{aIoDF7WAI||`VjcO1}~d;F?6kUH4I&A_31+xSPH>uRPV!tZf0lh4Y;ah;EUpC zn1L-dKZY@eu@4aNFk!4^Vf9Ryb>cM)VGLnB6UI^>NP`g8!kC;LgCT5f*1#-mtv-DS zhsPC$sj2s2voNWXozN;Meu=p_HHJu576Tar*$41RO&}BB(@rPGFt*n1FpRC$rw<{K z3{o>d+0=%yzKQZG-P`d$@oP-Wmiht4Gsd$IIFj0U)>5-}3i5RfXAEbY@v_th(m0&8 zkS4QV7|zya6U@%m>eGkNcw8ZwntH9s&ZK^N+HznS+U2e%eup_aHAYER7K0jt+6N%A zDyWGcYO`V(($=~lhP1W%^dUTw!D|L6Yh_65d$0?NH!x9K>J1px7}Y+YiIq{!CTk39 zYuymT+FE`35F(bsa~joaby(BSFu=xb_>_@QU;Ghswxv#i!HvP~129+}+-%;)(6-hU zF|@7Krw?IbDMY7Hy^kWa+1x!s{0VcnrH+9CjsfliI6R5~XY)6Px3%tw;ccxxeFzmx zVLFZKeN^Gi=J0~zFPOtEbq)-2400a;;!y=To5wN4t#wHZaclMIL%3K9)oE1kqYUv( z^fOU#2#PkH{u`!qOML`m9b?@GoOqP6&Zcw>b8Foa!`xbZ`Vcaf!gU(e`>4a*kk${2 zw=k_+>L(cQ81Ft{#iNdQEw!s}h29hYz;MTK$G1W)^?`I2?pnx`w?;ACt<6T5-L2K9 z525q8LN+z^rbTuq@?{}eT`1+8vI|V0J77DCe`2yvjrEe1#puWA_W`leD*B0^YOkMS z$Xn~881mNY(}(a$2EQ4gY+8oAhot`(CVfji2N3`fzz5_>O9WsOKZd=vZi-=Vtv-DS zAxq&qjp|M7uy>pMdx-yF^0(A`5Csqgd_a)2Mgg`1fT3@#t77O|t4|-o$WjPTqk11l z=)3I%6cO)XC%{qCYw@zV1R7>K?txm zYhf?IT7CKuPLC^$Q&aEb>ID#)v-rvVl5Gd7ENNzJp#6E$gPK029VBiA?J#H{y`UMCD z7SER<6d)92Feq@ppeWHU1Guvft-)ta&;*eIk->*pN)Md`t)t*vV3acBxWQ70Lr6eK z$bgWb!2&EeA|#k(d>>4!!wNzILV^!|lU{lW#DCo{KuUhtY0#tF2g`aag9w2L;e#Kg zCxjqA?Oc#VSip{hM~L&my^+Vm`B8d<1%83jANvfJIyUwhu+QKFsHQh?VEYXS4c59c zLW8yX^dZbFh4?h8H$6gwhXqU-I}w(87$OBCg%2o`9+5)pNT>^%FG)cN5eN|vH-NTO zZ$5<8lT>edg$NBM$O0!qgtb`@dlA;^^9hHJ^b8T1Nbdpuv&Yl-D!NG_*qyL6Jt0;g zR``H#=@~1uE`>VscvA{Rs6eQ|k%y%|@B~4H1{Y)mf>2>?7Q|kKwfgiS>>gLRr>5TY z-m4&Oqr(vLZuf^$ICd;jW9?*R5iJlcd_cI2fEL8ZwQZOP7uLEr!iBZ^^da<;L3aiy zn^E9`>0o5T4u++khKPZP;R8}-6vSXV83-BHx;R3HwfgiS{49n3G^#fvK?c*&$blUV zOT7(I15v{V#K}mg!FDzfHmr4Xgbi!;=|c!w3jb+TZ$^U+XNTin)-LzN%MXP7l7ih1 zOZ^V<1M$NL?8#{O!FD|mI;?edgbr)<=|dP=ngY_O-i!zx`g})0DK~aJEcH4>4@3_i zkS8Oe2iy5T_^{U95k9Qdrw^fMX&OkQdNV3~(1W)EuF^Ny>PvaC4`QkFA&4M|_y9l| z6-3y62ttUpE{_mmtv-DSM@v&d8r7STA%yLVjFBR-FJh?!B9I`E_y9r~8A#av2*QZ9 zZjUfxtv-DSNlVi~8r7T8VT4(riNX$vr5=b#f=J>63T1R8VLK%VCDyt=LW#Bd^dT%Q zO$ljK?~?!}>|{xODH{7GmO3H=3Id7`VDuya3fn(HII-6K5l*btrw^fNXf?fl)YSVV z&9|_62=J5p`32whvw!LrFvl<3diYQD6UxIIgybbc@tjl)yEUx7QhkrOgSg`ZRz9h? zL*hvLYz0D$wIP8JW34`Y2-j4nhsRLYlMFHD-5a5vR06v}+o$5P)#3_=X@0n45S3?lKRb$JkOtPKx@8*BCHL+DzXHqxlxrv+}zyFDuec5rgpQXfFr@tAtFQ5V9FM-@GkD`IcQT7CKu z!VhJy$ISm}>g^EwNMyG%>`NBLOBJxgW2wg?@*wi~fM!n{@{m~5Iz0$I)`ki~kG1;r zA&f0eA!$_a(+E8_((!SA*zKHD5&J%tIxYeb0+0{j^)vzy+y6oMu{K-~eyr7}520*n z8cCyipH}!``#_zg%Gd|8)Oitv5QKaHu%{J-w0@Af?w%l3MHoUD!gY5`eE?y|>r|vo zNh1t-tun7%6?;S0>eGji_R2o#jNjAT8zT1dv@05p6eFjI<&mDlZjz;bjrfH4WO2u0TF(}%FOG^M0by$D4qbeFPyC*)+pY>TGAY8$Os@&EGOZJ4XZk^ylevO0H}gbcUgpn)`B~zG1zGwFi?S>e z-pO)8SnQWoSmIYhSn4-USmt+BSe`YLup;XV!pf|pgjHD&39J1D;a&f#!W#c!!dm}* z!aD!^!uo)U!iIpJ!p4Bj!g~R~3Y+9;VYB?IutlCHY?Uty+XAx*+XEX5I|643iGk;Z zq@Yk?XHWxSSI~4}chFg3PjIlXH@Kege(+>rU+^hme@K9EAf%RXFl2&oDCD?s*q%lB zz+PQAVjm=+5Z-fhn5#U4DBzR2;C{1481Fy3M(g^4(lR(6t-SC6LwQL8y+uQ z4KE^G2p=h24BrmdYr>_7X2QjYk;3JO?QnlhxRNbIxSXwm@JY6=a6d=*G~02wza?DF zUPJgadoSU$>?`5^W8sS&<%Dl?yf0kO86td}v#s!5&P3sRMG|f(^@SglcZ45vWfyMd z8ZZ2mTNHlI-B0)>PdnlFyyt~m`KAcBBkKx(cbIFT6&~QTT$G zGd7o~#J(=(j@=;UiTzW|8&_4#7x%Up8FxXr@iti*Ah~Fwk$KMlUic}X17MUg% zD)OmVxM;K(TeQ0vS9FIMU-W-skz&=w62&HprHY*qOBXL9mMz{)ELVKASiXcPK3k%g zm{4N3Sh2)+VwIBl#i}J+i`7aF6kC`4NPN9iE3s|qkz%{D?Zpmd$B3QEZV)?{8!x_5 z?v&W&nHplRXX=Z+pBXIndFBhTfB7upfbs>zf#s`+gUYuM2bb?B4k zarm=U#1YS46-QR+CyuHxOB`Kci#VpjN8;EDe~A4P%83&adWdf)B#ILg?u(Nv))%K$ zsw_^g)J>dGX|g!8@>+3LU9-Q);lAfdbyN%`sEqonfig^+4|eW^9^Fe z3k`aSR~mK|uQqy4{JhZ+@miyu;uno>i(fV_CVthpvv|Gn1M%A?lg00wEER7wEiL}g z^rZNG(~rcPO}`RRmf@3*QfK4?{4l3M*w%G7$Ol%-9AT zDY)Hk$=>d^6xzO;6xRNM6yD*Gl)YnpDM!c6QqE3QB&E~0Qm)S7Qtr-!r2L%+OL^Z& zkn+7z1+JZ?d|mQOkzL+{>lG=oYi22bSAV#cf$L1EK({7RboZQ6O!pyD!R}+E*f*b% z;(D%-;(LA~73_W}q~0W?yN+%w^KTnSV)(X4RAy&srfZnRQ=UI=iW~eD-J3iaBkhm2-AVtLHv1 zy*sy;v}W!MY3;nT(z*qrv|+(yY2$*8(t8WOkTx%zD{WcyytH-EztXmMwn;k{SC*0% z&z5#Bc|qE>w6?T+>3nJLGFf_mS-7-s+3V8&<&C97D|$Ye!A#_KqK=JBcf#Ka*aN{z{r5-P;)=-QPLUChTf$6L*)j+4lI` zGVS@omSyihHotu~Th{&gZ2kvgZGi_$+JX*tv;`k}(H3&(md$>6xh?$gaa+U(t8Lki zykg6KWPmN#(RsE!$C7N3AFi-Pot$cmKHbz7b0(jy@R_!@*famw;?8!k#ee*@t?3O2!EjU16n|K8EE~17L@HzpbY?8V2&uD4Fp<94jE{J zfEJvi0ni2mEi^|0(1rlbp5rpmh5{`-$3dVC16o+lIG_y&TDF|wKpO$Hh@3-!HWFw# za&`pTD4=D}c@}7+fu`i#4YV;p%cR&s7p=Q-BtoD;LnF08AvoNE%$W&*8HuJb^f1+=(a?*nZ%&|-7v2HG5;70I0$Xmf!UpJx=%<^io( zo^C*!5456rvjS}a&`RXF4YY+oE1vfj&=vu$RNl{k_72cW=35K2#Xu{QZzj-|0IhUn zN1!bQTDiyuKwAd1viU0jZ8^}&=Z^;33ZOlczYEY-0W$iX!b@2ehhDq`m8bRwe2L&^7?=xv1?x+X%F31%iS09?)Kh z`WtAQfcAWWBS6~>wCV*m0c{J=UW^U}+E$>|C~yyG+ko~`G?8UH&}u~!S#|)eX7oUy zB?7HZbUUCW0j+lQdZ6tDTD|DmK-&ehy3u!lwi{^mqrU*!9-zG(LwsW|&>F@N-*_Kr z4Pp)hZ6DAY#cTxHexSV)1Mw4n0BB8Ot^n;I&>9y!3A95%YgTXv&<+EwX`wAZ`v7Ro z3oQiN5um+VxEs)p0`0ZJO@Vd{Xe|npI*tR)QJB>6A<$YDCUu+uTI<53j*~!Z66XzgM<0PPIW+QuFQ+F77=h}{gdkAc=cE(B=jfYvGYAE2EF zTF1ENK)V36H{xCZ+C`vsj#~+|OF-)yHw9>yfz~CC$Z`c}-Q$QXp8%~}e0iXK3bZ%l zqkwi5Xg%Ub0_`)P^@{Hbw9kRoGyW9Nt^uu2d?L`k09x-N*?{&X(B6uF0JN`w*0)G& zpnVOr{zYm5?Hi!=E3yt~*MT;$$Sk0J3$y`6{s7u{KpR}-8qmH6+MuG9fp!CELyHy$ z+7Cb*Qgl4fegxX^qP>826KKPVo&nlVKpRoUBQf(k(8d(|5oou7Hon*epxp-AxZ*DX?GK>6UA!dF?f`8<@!mlD6KIo)w*=Z< zpiL~k1ZaN&ZA$S8K>HhLlZzh%+CM;>R(uQ4{sr3962$-R0c}PJ;(zynHoe3}p#2B5 zSta%Z?SDXc$Xz!Fh2Q+`6EiJtlXaPW5QYIQ`GSHTn z2?AOm(3X|i0JI>Wtt>MKXu&{RQRaU@3jx~dGCuzyL}3JQgVeZmXEnsOzCyuyB= zzp%Dk1tDBG0C(%k0a`?aLWvFK04*ZIpv3xT0DU6Df%e`rfIblsK--uw3251XwmIP~ zpk)WzrUb|k5jlXiH32e2L{6Y>shAgN3edL0ZqKNQTtM4au{+Rm11+&)Goa-G+K!3~ zfR-0%J1dR`T0Wp9RRXk#hy>d1N`Mv-`GK~pawecf0c~%kUx8KtXnSfxHi(D@+P<2Q z4I*NI_I|D6Kr0Be1GRDjtq{=m*BS=2!azGzt25AIfp)MKcw$5x&_1XIo){4iw8OO_ zDk6#i?Px8Ciin~>J5sv?(24==c0%#{{F9ljjpnX^;Gtf!_?NsgG zfL0o4C+oZlv@$^ZsLu01D+{#KbtVF>9MI0z=?k=HfOe*CC7_iD+PS)gfc7lVKCYJq zXcd5Vq3-WMO90yW`h|d25onj{+ksXIXcz0B23lpHU8$c0v?@Tm+@K23ssioP2C+b^ z2DDEa5W77Gw9gt4yFCxIs|_GqMZ5sCYYiYfT6Lg(+3-!Ey#%x`UI8?V zr~$OEUja0Ws0p;M8Ub2F)B@V|Mt~L(wSo3cqlG}L1GMiNjR9I+pncou642@a?M9;m zKzkWz-#4}ctv=9xZ1gYC8UXEw|2JwMP*I!!A@<&|cTo`=i7_UkvBVN|UFfWgTRHv{)w#`wHtWd)mIK;R);E zjyKKr6^v40J&k&%(V@Srm&~Wb`?B6Lt7EXNkId2Go~*CTw_`V1w9M79p{$?G8M#c> zU*;bN-!BAj{n~PBvPW zt6Ndo7+KzKF4(HXKOvP%6r$(G8h_Iq8nOjf0TYgvk{djFcT<+5u1FUwZQYWB~R zt(4Um@TY8*toDF!WUFPhV!~x>WOZYLWNT%0Vg}3B$?C zfvn}QBeD-=E#mYqnXrAb)^WvUAIVz9@w(bCYa7Sw>SI}(5uBF;vUVdlFQ3RFMy!*4 zD(f&JNp?`ye&hsMrYv$~Z`mPP$B`Fghhl9yEc0|@CKDX?stn;V?vSYGt zqt?id%ep3bWuMD>jJhj3A?u!SM0QfvD`AW5l&ojMBiU(LpM>vaU&wloPL!RIMUU0ImX$fnG&WOrrB(|?xTlTDqmL3Up@ zeMYkEfo$5$_hf&_X3nf6`%^Y!=0VwCve`4&%O1*R%_=Q>B%3=cSoT;pXLbSE6WRRP zmh7o)-kfo=XR?KJdKmhuEn6_xV|Z*+ws_9(GE25-o-Ol{EuH(9%vZK#-Z7a&mNIXv z%qd$oznRP>TQR?~%ulv_zUIjGm#vzwIkE#}D;MZ~ZMSUA0`Au%TfHz+7ARY{uz@T{ zwsui2nOC-9;bU2_Z2clVUpqv$X_20<9V*+nc%&?cY|G+KvM|}^C6#2hZ0nL-vX^A3 zOEqtHPTBS)nm0R_Y}?WfvfQ#AOY6z<$kLW(%JRx~F5Mu@Cre+}MV4Q-d)ZsE0!saYMiWz>`LlqvZk_MQa8)qk^Q{2 znCxBIZ(IFj@5z4Mx?R>xc5UliS##Odtv|}%m)+QUSk^*zeOp~wOWCb$MP;pIH@64L zTFY*4yCZ8O`#tR?SzFoN?GI%UvO8&$W$k45)1qbVW%tr}z8z$Lr15+^${y?(DvOl; zwWFP^lkCqO`i!@uWRG^}Gv4kjdzj8^sEh2$4qiiDWslSKUCQnzdzP;6Qg(OQ)AZA_ z9`1O{Oy4Q%Y1Fffo&K_3GN1GtvfeUlr#`prJ~GEneQw!(WxhKP%c5njottF+WX@fs zWc_9SyS%aiGQVBCk78u*UA&J5$^v%nk`0mt?ph=pEc5IxCmSO3?#>~Ll?CnIBpWIV z**#r0OcuOnv~0L6$DXdTI9cf4ma-8tdvA5wNLg5hK3DB{Su?}CyK~s z$X-67?^pIrS*a8Her3;+g`e6ln=LDIYL#q`tn}&JvbnNyr=G~>$;zJoP&Qvy;q-FZ z0$KSpi)0IB70-;4Et0)@=ALY^tn!(QvL&)gXG_SI%Br3XkS&u{IjirYc8aX}S$!9^ zm&>Z1TOeB@t9fpuY^AKm`9Rq!S?zPTWvgYi&bN@Qk<~q4O}186=Yqbo+UsQXF6cX} zyovMz@6;YgH4gL%m~I3IT-VPHBRDvB(8Hid|GA^u z`X#reP5i@4W!=y2?C zM-H$v><@H@oSYnbf;>f6c!qt@FgUKxihWESXawp1!A6Mw-k!s-v;OX$OSieToL9H` zbX!2T1$A3kw?%YYOt-~#TQci7A^JOgDWkOZD62DFPIpv6x3B89l5Q*OwyIIxsG;p^ z8Fh@hMsEAK_OlFs`*Yp8wLU;U?m?RB6Ncg2#;9T*FibPU9d7u!bGh@o3%U!r3%iTz zr(l-Vao2O#e{S_LZGFdm_qpAbIo*G_AL{2(*1lQWcpU%S#^e9OHi6k}6Y{rhbX-rK zzb)&&Jw>wFr^E}}glDr&`4_gS?WyzM=b%y6V-D)@&;5d;{=T0(SI|?h@!$P4%G%Fc z)?4nmmE(MPD|)MVEB^0%xa)WudK*38rV;zOb9p1ZQO_;vKi13J`?>YbvO3e4dvUIGAEUC_ZtRQOnHk=v-e=E`_l)D28Nv1o&kHMHoV+3Z&XqA2ugqS0)eZ5+>Gd<#`!v`NE*M-gI3{>_aD4EX;O)V? zgZBl08hj+g5#kQp&_BQ^w=7QerKOFjF1JU;WOUT#M9K|!fOTw1WYpn zbGX}?fi6aYBv|oG^1osRHVCY423Au7l4b7s?nKj_>K<*n4>HOmhgm$y=oFirV|3nq z!SpnAE;j=*0zNQ3$vV7e7MV*Hkfq$mO4fd)1m=_l<{#Nu@lDc13Ah??&E$j740sao)O26s5hU=a#xt71C_>wL`g)>G&pVY7~&@3Np-m&c}wCpA;YkUEzjVm{Ac@loTVyNeR}LWb`tlR~UtpQlvB~L&}nJ zq&(YIAg_{&SS3=KR3TMKHBz0_AT>!X_NYzjkhARS2;5=lCdDAJj9 zCEZAO(u4FQy*N~F(uc*qB%1Ui{mB5<#xNR429d#J2#F;_*<=`_;UtcXAR}23Pe!qr zKt{7ThS69uj*KUXWCEE;CXvZx3P~bUNivy6rjr?DCYeQMlR0EAnMdZ61!N&vL>7}J zWGPujQpj?$f~+K~$ZE2NtR?FdXFLni z$-lYboZ?I}oa3E|hOx*0tYNhCFQjizT48MWyJr|tEOsTS*j6l(#V#a*#g1ePxxgmJ z$Vu`g`GOVa$XW6+c7n_x$H^&jfP79)lQV4G)Zb+oZ~5twF7;0_j3w9t)_z02RZM@G zX|Q58c}$*QK8ka(bEe@;(SP*loWW>5IpNerav0mKBbzwXX7U@0Ka*8tH5pG}i#Um|qW|Pln@nJI zkI`i^n#F!(C;1iIP3E&Woh;X)>BlIZ9AfQZlF8y25=};t&sZ^*(f4FM*+4du?^v6_ z=m?{6jQ-$RPG&Tf+-1dFMvKW`WD!|OT4`g`qmk)mu?-_Hd-P*DrC5dxb%nI)}#$-OCtQ*8Gh{kvXks0yIHY^>}4^7 ze8A#|jP{X_$bRxMIY2%kpOS+llN=(4$!FvUIZBR^<-E$nx4liVPE zS<#G(esj{8D}NKk+-2@ItWd?LIcZJWlStB)^dP-SG#Nk!DOOHKv19}pO%ll@l1yfi z`D77EQLH?SR+2SjJ=sK3$##-Xc9RUUU$OEtI!F$az zC7fs9D8+h(5hvTX7wJo42xr%qv+K**^&LkhkR-(_&1f2#N#>A+WC>Y8R+DvPGuf_K zpYgbA=XlMc?QgEQpd`8s&?4jzUh>!39l)g_#4#~X@OlhNCx zF?okHBb<9jYZ5^^kWQqFV%1^PoiGcIek6u43l3(%F^Vt?4qoGqtXXKlh*@yVCJV@7 zvWzeb4ral@EI2ljEsB-(__ndQlkh@!>?5C$O!66FJ{%{=X~k;F=q$NFz9Qd}OXNqw zq&R*fHwlwsHD~mI{6(HBPLnu^KVedwOo}s%Ynqy;e4cj z6}kLf0j4XELz&vn_>oVh0emvWC}seofn*TbN8abtY7V1|3I0vYp&^q=wXL@3FAQ$=*ux4UQQT14=!*~Lom1E+9SCqZ!( z2S*`jw7HzaEeL#hhG!ezhNl@vDw=SEdf`~jI7WNC#5a7w9oOofXL;N;+Tyo-#V7oq z?|3?3H5xEl?vl#JB4CMsN73Z)WfQSkB9EQ9%e* zBvC^abzGr=0-Dsq0BuZgk0m7xdJ_Mvi+3Q7(8Mqit7~~mE8B7?> R7(5uw8DbcXC$D6$1OQgz5HtV) diff --git a/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/el2_ccm_ext_in_pkt_t.class index 678ca3bb8ddaae73c6d56d3c62241825ee811bde..bce2084dcc138a80b8222f96c99dafba3904f9c4 100644 GIT binary patch delta 127 zcmaDQ@=9dG1-8k&>|&Fjv8hk?0@BLt>XX}nbOMk*0;J~xX+{pQ$+v*C9gr61P@7!E zAwD^TLw)iNAb%o$@@QXo?;WvX3!yg7WhQAC^4F4GN82&Rf XF)}brV`OAl#mL04kKyO!8=R8>7^^47 delta 122 zcmaDQ@=9dG1vbW?lP|K_OuoP-Hd&cneKIe**yIEt?FFRg0_k=jeG5n*0n*|eYLhs` zCx>vTPqyO_n>-OnR|DyD91k^rFmN&aWRPR{#bCtno579Y4?`5gUxqw}e+*3w{~4w+ SGBB)SWMtUK@MH1~&Pf2=uqa0W diff --git a/target/scala-2.12/classes/include/el2_class_pkt_t.class b/target/scala-2.12/classes/include/el2_class_pkt_t.class index 076efdf6e09deefed64561353590de05eb5e169f..38d93ddb45af0c787422c71225528ea095f04c7c 100644 GIT binary patch delta 51 zcmaFP`$2GV<2)ftN?KVhvCEMVYbC}fahC}J>TC}wbDD41N# GRssOYD-U`A delta 51 zcmaFP`XQSWwyxz>|&E&vZ+t@1=4El>XW;GbTW`W4x|?VX%-H#$#;RYBaoKjP@h}} zq{D&qZXi8{L!FUtvLL(YS&D@PyR delta 127 zcmaDW@>XQSWj03E$%5>nlV7r_Prl41Hd&2beX;<%*yLm&?F*zA0O>9ueHTa{2hvg; z>XTVG#3qLWX-6PE1xVKc>5Ci>HCY(A7+D$Q7}*$%7}*)z7&#cC7&#g87`Ygl7`Yjy TG4e31V&rAm$H+4IHs>S&4apzi diff --git a/target/scala-2.12/classes/include/el2_dec_pkt_t.class b/target/scala-2.12/classes/include/el2_dec_pkt_t.class index 47dfda951192b54f768bab321f6d2551c033cebd..ea1a4019ba4d68c9352de51b072bdd019bced86e 100644 GIT binary patch delta 622 zcmWN`J4};d7>42JMRah$zoq>s{k4e>en^~Dm`JRWICww@5)cy?@h}m^#R0`I5I_c# zmqX(O!c?VH>w%*R3KT_J3^(2WboaO=oF=*Jzg4YBfDZduapRpks7Tw$Y4is~6}&+C^*VD($B` zd`5rL3cBBCwVht3^R$P0{6^Pl3AKK!w`e6z(oVYB82wBSQ`cCnrR8*pw$eW|MGJF` zZp*QHl^&;Y+DO0Aahe}6x+!4wA`R1SdYyiu12mLt^cOut59C^n&?|I-#;7-F^ea6{ z^MY2J>3KRy@6s)<(G^-ux4Twv($jR9wz*c)>T&#uId^A9Z4_H^4?f&S2tCL{4ExZF zBE)e74{!<(QGo<1@d#CTjB9v;Iy^-)`p|}cbYK8c4Dt@)8HSN$Q+SRvUSJI)_>NKh z#Y@S=E6Ku`1TZeUFd=)9ltN5OxCF1|DBegZrsOQ%$|X!oHD;s+@1!2HavLeRgE{HO kyu`2|eOQ!HEXfq!%OaL#6(3|BALR$q@(Hy-nBXBDGmoJy}MpX$8GYZ_sZvPF-VlhcSAB?x(kC15MB& znvrdFiyo#W*+!db9UY@ln(Vi_PD8Z7Z}bX1PX}lx{X>7y;vB2N9HW=$DH@?+`jalv z{D4(&!01_el-{GQ^gErPJ6)@(uF;dUoVL?zu8A$Uxk(LONJBS#cz_@tA|E{{LIkDg z#Q{Wd43AKS$EZdO7x4s_@f6qb46S&McJ!eG{d^B_8N^ErA&wVFu)g3GR`D7e7{))0 zNDAIaI^K#OqmqX)Da5#xATFT_Ovph@%5hA|X-vxn%t$R}r502$q1HZ8t-KpA7lj|WeuNX6QAWjx?;n@O4$bClEc9O diff --git a/target/scala-2.12/classes/include/el2_dec_tlu_csr_pkt.class b/target/scala-2.12/classes/include/el2_dec_tlu_csr_pkt.class index 6452f0b022c6dbc1a31d698e2ca0e119113a4913..8bb5078995db26b574ba005116741284966ed30e 100644 GIT binary patch delta 851 zcmWN?Nl=b)90%~{`#jGZ)4>q_2i4o&zj|?KC`7bcTM@l)g=j^zB3cg)Ni+OrQkii` zGUJez8HXq{4k$AYC^HTy#=#QfV2Lrlm(QoWw7Yb$#8>)!l{ENjnc<_{>8Io;_wY4- zTDo{8pW*}D$6v`Op1~vhwY2jhKEZprms80bp2Yo}TAFz-ALE^To%EWgVGf|UH?d3E%-{1d9^_Io&kK00OUqSWSNEf%y;z%vU&Q&f$<{qR>(}Y(?RS6^|k-8^u;JO00U6S{*2}dQooO z!BJ}x$E?>lZhc3E?S&Ke3Y@f8qtZ@9m7RlXyBsxkBWmr-sI&WV${xjO`zg-Yv#7Uy ff8eac8|NHOG&rKs=txDA!;NM~1>#0L(c}0Jf<613 delta 851 zcmWN?Nl=b)90%~{`#jGZ)4>q_2i4o&zup&zhN6g8Yb&A^QN4v|MYJ9ql4khLq&hex znQ=(Vj6;+e2b38Hlo-@Ah{ghPkd_Ks#`6oWjBmA}a_$w*l8N82o@Hc#t`#H6EIhEw{B;Lha_;Wtamj-BA z;AuQ2KuJ5V<&XFOn#kT;&1sB_YcvsC`3sfPv%#7D}TW!__9zfe|S3I5US)Nuj7yT2zP{O`N|Xd z>M$kEyqw?T1N=9C$D_lw1cocA;e~vN_wq0NC3k5pE3}d_p2holC!gg{xHCe_;s_=A zJcW1jHa^YobDu~pe|ZMq7^$R#*Yim}%Dr4#zVRf!#-*f%SMYIulP~c1JjSgh$gQN7 z7rE8wu=}#3Io9w-oZ-YKBMO_1RKy#3*kV*-tI>u8qYH_~EhHHeNH(4!#rS|!V*%T+ z1ltje9f-zG+Jz$QMm5rK0qN*P1_qId2gt$YUznP8$W-)Tj z`ex*r?Z`K;p}-tLq4^L+<|`aD=W)m~aoAEQwp=)3#p9@zjS{OArB(yVtWJ2WK9pN` zP+?8snDrXRt?xKtd!f=^g_HJLoU#*9W#^#Uu0W05gj)Lw>g)m3+haIwKgAh)4rguO fA82rR>_k9t7x8p|yC(s)jk5o;$TlrXd24aH|%#=k?HK!}QFPOV z8eCupmhPT9#v=q_@4ahO5&sUNF{0r@7_(~XB!D^8)ak5%dl=$XevWHLjZdx%xxf%g zVqU>EDU#x_UFGj9y{~yKs|lPkr=yH2*Oub<<~mUbBqa<9;x=MfnQN1xk2y82<}j~j zQN(o&wa=ZX5zKLIf+p~RQN&Y0n{Rjz}Uus)*9wdq!T?pess`L zntZ@>{gV=9-Zy2u?vQnSF>V(&-1&Q&q6iYVKA?p;DH%va--Nj(O;P8c3;bGH(bTP^ z&4MYVH8NvpLYC}gB^Q%V)b4nBH<%EUTHr`uNt~^2k8(;fFc#gJsxEP%bs9GcZ)Cl0 z18urCo-GGe;?JslZ(dy7$(9Q-83(%K?{Xu{i;+Bvi>tTK(p^(rG}1F@?~K}-pk>Rw zGiSRqrOu2dln$QHo~`ywe&4`zvBZOP9lsOl8m(%invsTTo}E=pR%C9@E?1aotW{iQ zTh+wPZqC%JRS_hT(f{*A2qU!lkP+G&%!*z-)(?!t%e>_#L}*2bHVuhzi}dJ?Ut6)k z+js0TQ8(>ZtmGbw&_*?I6GI5Fj8h_fxiNEXG7@=^WlUSA5s_u8uI(7K4$G9-TLhkE zs3rWZZZe7p7OT!X!$N4OIksiKzi{JZh7RbIfCH75cc~^3?kxM)?IRiP z)MJw}#OvMz8M^9TN`~&b_k|2Sb?-|Vdh1?VhQ7L&m7%}xjnZysnZ?{El*V9c3!%S} z_h+tGgh|SEWo`cD^0NejdYQ^+;%UdzFeAYf)DE%WI;`j-Ok6vI&k%j2Kyy8YCn1{a zDMI()<|l!uXzcg@Qkjck#r+Oghhndf0!OAFTvOF z9O2$z{^}wd#G7)W_;y$hQTz%5zM|v0mN&Cp!?AQTz0VxSHPfCbiLnMRLU0?_Nnm=V zQWH=5Dph~d)jmA6%20sK5T*8#1eLQ(q}3=1%2+)u?-|afzGo5=Tej&T-_jjc>tBF! z-m(nGD_VNdAylwWouaWo<&6;EIJI0>Hnv!m5ks>q+tt0Ar|G>pqze92wDsYbKX{$>T6Vw@o6!7)cQ6 z?mrEEfZ22S>Nm)dx9|a$TFznh95&8j>sJ`KzyjB>`##v94>sh3J@mnbeXxuVHgbX8 zlCN!M>=(+RuJ2(8lV74@Fz8+1hY>h{1vrE^z`%kd_yLaLM=;?hD8ru=cU1?UF6uy_ zSfIayr#WPZP=Q84q2iS2^-<{IlHgl!H37aO8>aKC)s$F;7T6|Wg3dEU5A6idZ*mvt go1vz5*EA(HwHouPl>RC5YTBhgiJBb%;01tx0Xx?dUjP6A literal 2568 zcmaKt-FDhW5XWaEgb)@c!cJ^VJ}L(qAt$2QqIJ5wpw?Cv&VPiRjHM0_Uru6p+U8rWBSu7*BIKc|OUXtRv#AV+DQn zox%^RQ!f`fk2AZu=IG)8yD7YtBM)jj<>>Yy;xLEvOcn!IBV2xb90!?TV0pxNHG9~I zN$Duh@Lbu-1$Jkdz}rG&I>2?mq0r zEBVmyaa_y=#uj7}L#ii+mG>=Ot7=xZdDzl)b)#izO`{z>|CrU4cAE!*)balu4+988 zE-=F79@$c=2TDVYZsiRt%EKT+uB2zR}&MHuUP6Cy;q-lPauyWSlU zu64a>5w3T=8Cv6#W@y$UTJl7^jBum3#|w^@?Q`Ec$7#C4|VtN$K;ci}A7uDR|@u4?IQ~IZ5jsxg!N< zU1gqsuj)8p%b=cPmWmm%+``~m`Q)8{&~Z_Th& z(@^w8T{BHfPdEZ3q6lk#7>0EclhSJ0l1ZFy)g3xrhoejpzJ*OcZS5J!DBG-&E`uZ^ zb-i;~QO)N{MW;xp*rdC-teBepd>j<>hM}5HgVLo8{!+7JR@GH%WrXmvj$vtsYFTS* zM5GO)X(>*B)AY{0o;P%=k~iv2l6mi@2buKjpbeunuYc=!i=LtgeXJnDK9DYQQS&!%NV>fH&|X9KcVY!_Sm+D%nrR zlI38V=rLf47a>3$5Cn<(N1zKrqPsSik<^9aS#qfnej^QhV5yR)n&sp;UIq(iU diff --git a/target/scala-2.12/classes/include/el2_ic_data_ext_in_pkt_t.class b/target/scala-2.12/classes/include/el2_ic_data_ext_in_pkt_t.class index 89080cce45297f46482d64d8d237217801a4940a..4fa60a40275fea06d785420d48d5fb11ddd10799 100644 GIT binary patch delta 127 zcmew+@=avJ9k$7m>|&EYv8hiE1Je5J>XRn}=^P+^0Z6X|(!3mElb-=;FCeYVp+31C zNGAa4BS3mChdQJ52U8 diff --git a/target/scala-2.12/classes/include/el2_ic_tag_ext_in_pkt_t.class b/target/scala-2.12/classes/include/el2_ic_tag_ext_in_pkt_t.class index a6b1265f24291b11c19b5d02ed07c7cd5eda0317..144ad2fa412e0880abd81bb2d3d117ab0ab7180c 100644 GIT binary patch delta 127 zcmew?@>yiVO}5Em>|&GOv#C!G2GTn0>XRn`=}aJf7Dz7x(p(&3lOF?VcOb36p+30< zNXG){gFt!~hdQJBsV^m^@VpL|xV^m>iVpL_A T#;C@yicy_mAEVslhn$lDkzFDP delta 127 zcmew?@>yiVO*Tfk$rIT{C%7Dy{_ zs88nN5Stteq}_q^EFj$iq_1;4)Rbl5Vw7W$W0YqwVpL#oV^m~_VpL+tV^n5nVpL(6 T#;D4$icyVWAEWH#hn$lDm){}^ diff --git a/target/scala-2.12/classes/include/el2_lsu_error_pkt_t.class b/target/scala-2.12/classes/include/el2_lsu_error_pkt_t.class index 57ad43b1f55765013d3fdd6df32d7e8b307833bb..daa8b5a569ca44ea14f7b9aa1547450ef1208d6f 100644 GIT binary patch delta 79 zcmew&@I_#Q6Wio^HnGVOZ0eKu0O_ef`X`XS1fw)woAiW1j^Ruf@{t2Xg*e6OZWZ+_0 e#30A8n8Ao)34Bsv diff --git a/target/scala-2.12/classes/include/el2_lsu_pkt_t.class b/target/scala-2.12/classes/include/el2_lsu_pkt_t.class index 4d5bb3e7bbcc1bba54f5c6e901c620f1e607f9d2..c80bbc18571d3031fc5e3e58d97dcc23ce920c04 100644 GIT binary patch delta 163 zcmWN?Jq`gu00rQu+L@`DQbaQfl|-UY(@Jy_(P%U}iCP?hJb$~Et*CJW?IvnbJAf;A zU-RWY_qS@qQRLZ*0#iNHAN|nYc>Z)>*G=F`PxMP)wX>dI-PIKvxYR@a)QJs+jB8Wk q+g_T4!v;lcQN|86?9sphZN%sxK@Ud^kYbDzrZ{7c3=5EV7ykjnW-mDa delta 163 zcmWN?I}QP17>3bDHJ6&d6q#leDv3m)rj_U(8}vd)G~(0Z@fj)6B<;}}-O?cqJ6diuPveeJ=Rv{gtH&8^%<+H)qF5q@6`rw1 s85`8FMGHIhvBw9#Fu{Ry#1-Glj~^AnuZrPMWpGljII9X~k_!y~0lQL5)Bpeg delta 236 zcmWN^u}cDB90uU`+q~1OMZYnQ9KJDd2*O!~z#&{jusx85hG;&Tqxhi*{Q-eaL9}`} zi;IifU3I2rrQ#?ezSG0wyT1Ecu~Z~aRz|KYBNa=_3w@+99Z=UcV%u8kv_zljJsr^= zO(%`)=mpIuwLH)}+NbX{kutKT1$vUw;?V{TXq#^7gq}G@vW|Ycb(*Ri!bXH6d?1HU x6!C=`Vq9Yk58r5Ef)1wWVum4pxH&fXRR{P}$M{#LSg3O>)g@Ny2BB0BgFW6=Oy2+i diff --git a/target/scala-2.12/classes/include/el2_reg_pkt_t.class b/target/scala-2.12/classes/include/el2_reg_pkt_t.class index ace55dbb00db8fa73ac8fbe596cfc471a0487fa4..944fc6f10417068659d1c120f59355c8febc8297 100644 GIT binary patch delta 51 zcmcc3dz*JdEbHW1tYVXkS=A?B2htl@)fp=%-(am1EMwqeC})sks9-Q+sAOBi xy&6dWW8bBy$-u>^#URJ1&0xf+!{ElK%Mit=$B@UU&(OqZz%ZRrbMj4&4ggY|8|VN4