diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 9506f3e4..0733b67e 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -66828,81 +66828,81 @@ circuit quasar_wrapper : module dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} - wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 95:40] - _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] - io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 95:25] - io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 95:25] + wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38] + _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] + io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 97:23] + io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 97:23] wire leak1_i1_stall_in : UInt<1> leak1_i1_stall_in <= UInt<1>("h00") wire leak1_i0_stall_in : UInt<1> leak1_i0_stall_in <= UInt<1>("h00") - wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 99:37] - wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 100:37] - wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 101:37] - wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:37] - wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:37] - wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:37] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 105:37] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 106:37] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:37] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:37] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:37] - wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 110:37] - wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 111:37] - wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:37] + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 101:17] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:17] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:17] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:20] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 105:17] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 106:23] + wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:17] + wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:17] + wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:17] + wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 110:20] + wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 111:17] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:20] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 113:28] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 114:28] wire i0_rs1_depth_d : UInt<2> i0_rs1_depth_d <= UInt<1>("h00") wire i0_rs2_depth_d : UInt<2> i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 116:37] + wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 118:17] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") - wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 118:37] - wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 119:37] - wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 120:37] - wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 121:37] - wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 122:37] - wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 123:37] - wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 124:37] + wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 120:29] + wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 121:30] + wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 122:31] + wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 123:20] + wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 124:20] + wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 126:18] + wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 127:22] wire i0_rs1bypass : UInt<3> i0_rs1bypass <= UInt<1>("h00") wire i0_rs2bypass : UInt<3> @@ -67005,299 +67005,299 @@ circuit quasar_wrapper : i0_result_x <= UInt<1>("h00") wire i0_result_r : UInt<32> i0_result_r <= UInt<1>("h00") - node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 178:54] - node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 179:54] - node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 178:89] - node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 180:54] - node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 179:89] - node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 181:54] - node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 180:89] - node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 182:54] - node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 181:89] - node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 183:54] - node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 182:89] - node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 184:54] - node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 183:89] - node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 185:54] - node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 184:89] - node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 186:54] - node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 185:89] - node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 189:57] + node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 181:51] + node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 182:32] + node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 181:73] + node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 183:32] + node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 182:56] + node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 184:32] + node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 183:67] + node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 185:32] + node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 184:56] + node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 186:32] + node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 185:56] + node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 187:32] + node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 186:56] + node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 188:32] + node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 187:56] + node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 189:32] + node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 188:56] + node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 192:56] inst rvclkhdr of rvclkhdr_661 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_17 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 192:80] - node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 192:78] - io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 193:55] - io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 194:55] - io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 195:55] - io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 196:55] - io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 197:55] - io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 198:55] - io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 199:55] - io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 200:55] - io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 201:55] - node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 202:71] - io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 202:55] - node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 203:92] - node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 203:107] - node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 203:120] - node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 203:73] - node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 203:71] - node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 206:97] - node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 206:72] - node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 206:131] - node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 206:101] - node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 206:151] - node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 206:149] - node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 207:72] - node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 207:99] - node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 207:97] - node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 208:87] - node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 208:104] - node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 208:126] - node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 209:72] - node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 209:94] - node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 209:92] - io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 209:56] - node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 210:94] - node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 210:116] - node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 210:114] - io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 210:56] - io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 211:56] - io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 212:56] - node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 213:72] - node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:111] - node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 213:109] - io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 214:56] - io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 215:56] - io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 216:56] - node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43] - i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 224:23] - i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 224:23] - i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 224:23] - i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 224:23] - i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 224:23] - i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 224:23] - i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 224:23] - i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 224:23] - i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 224:23] - i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 224:23] - i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 224:23] - i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 224:23] - i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 224:23] - i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 224:23] - i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 224:23] - i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 224:23] - i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 224:23] - i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 224:23] - i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 224:23] - i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 224:23] - i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 224:23] - i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 224:23] - i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 224:23] - i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 224:23] - i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 224:23] - i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 224:23] - i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 224:23] - i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 224:23] - i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 224:23] - i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 224:23] - i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 224:23] - i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 224:23] - i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 224:23] - i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 224:23] - i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 224:23] - i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 224:23] - i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 224:23] - i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 224:23] - i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 224:23] - i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 224:23] - i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 224:23] - i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 224:23] - i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 224:23] - i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 224:23] - i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 224:23] - i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 224:23] - i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 224:23] - i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 224:23] - i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 224:23] - i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 224:23] - node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 225:25] - node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 225:43] - when _T_42 : @[dec_decode_ctl.scala 225:50] - wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 226:38] - _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] - i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 226:23] - i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 226:23] - i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 226:23] - i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 226:23] - i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 226:23] - i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 226:23] - i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 226:23] - i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 226:23] - i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 226:23] - i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 226:23] - i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 226:23] - i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 226:23] - i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 226:23] - i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 226:23] - i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 226:23] - i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 226:23] - i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 226:23] - i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 226:23] - i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 226:23] - i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 226:23] - i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 226:23] - i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 226:23] - i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 226:23] - i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 226:23] - i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 226:23] - i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 226:23] - i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 226:23] - i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 226:23] - i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 226:23] - i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 226:23] - i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 226:23] - i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 226:23] - i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 226:23] - i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 226:23] - i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 226:23] - i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 226:23] - i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 226:23] - i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 226:23] - i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 226:23] - i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 226:23] - i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 226:23] - i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 226:23] - i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 226:23] - i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 226:23] - i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 226:23] - i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 226:23] - i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 226:23] - i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 226:23] - i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 226:23] - i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 226:23] - i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 227:23] - i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 228:23] - i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 229:23] - i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 230:23] - i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 231:23] - i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 232:23] - skip @[dec_decode_ctl.scala 225:50] - io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 236:36] - node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 239:54] - node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 239:65] - node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 239:74] - node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 240:65] - node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 240:69] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 240:40] - node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 240:85] - node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 241:65] - node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 241:69] - node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 241:85] - node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 242:40] - io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 244:37] - io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 245:37] - io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 247:37] - io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 248:37] - io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 249:37] - io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 250:37] - io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 251:37] - io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 252:37] - io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 253:37] - io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 254:37] - io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 255:37] - io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 256:37] - io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 257:37] - io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 258:37] - io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 259:37] - io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 260:37] - io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 261:37] - io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 262:37] - io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 263:37] - node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] - node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 267:137] - node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 267:158] - node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] - node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 267:126] - node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 267:137] - node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 267:158] - node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] - node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 267:126] - node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 267:126] - node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 267:137] - node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 267:158] - node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] - node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 267:126] - node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 267:126] - node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 267:120] - node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 267:129] - node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 267:126] - node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 267:137] - node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 267:158] + node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 196:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 196:60] + io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 197:54] + io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 198:54] + io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 199:54] + io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 200:54] + io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 201:54] + io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 202:54] + io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 203:54] + io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 204:54] + io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 205:54] + node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 206:66] + io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 206:49] + node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 207:75] + node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 207:90] + node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 207:103] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 207:56] + node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 207:54] + node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 210:72] + node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 210:47] + node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 210:106] + node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 210:76] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 210:126] + node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 210:124] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 211:47] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 211:74] + node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 211:72] + node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 212:62] + node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 212:79] + node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 212:101] + node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 213:83] + node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:105] + node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 213:103] + io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 213:67] + node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 214:105] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 214:127] + node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 214:125] + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 214:67] + io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 215:43] + io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 216:43] + node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 217:47] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 217:86] + node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 217:84] + io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 218:60] + io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 219:43] + io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 220:67] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 226:36] + i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 229:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 229:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 229:9] + i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 229:9] + i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 229:9] + i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 229:9] + i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 229:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 229:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 229:9] + i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 229:9] + i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 229:9] + i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 229:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 229:9] + i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 229:9] + i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 229:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 229:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 229:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 229:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 229:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 229:9] + i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 229:9] + i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 229:9] + i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 229:9] + i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 229:9] + i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 229:9] + i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 229:9] + i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 229:9] + i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 229:9] + i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 229:9] + i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 229:9] + i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 229:9] + i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 229:9] + i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 229:9] + i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 229:9] + i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 229:9] + i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 229:9] + i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 229:9] + i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 229:9] + i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 229:9] + i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 229:9] + i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 229:9] + i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 229:9] + i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 229:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 229:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 229:9] + i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 229:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 229:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 229:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 229:9] + i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 229:9] + node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 230:25] + node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 230:43] + when _T_42 : @[dec_decode_ctl.scala 230:50] + wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 231:35] + _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] + i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 231:20] + i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 231:20] + i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 231:20] + i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 231:20] + i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 231:20] + i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 231:20] + i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 231:20] + i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 231:20] + i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 231:20] + i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 231:20] + i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 231:20] + i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 231:20] + i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 231:20] + i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 231:20] + i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 231:20] + i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 231:20] + i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 231:20] + i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 231:20] + i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 231:20] + i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 231:20] + i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 231:20] + i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 231:20] + i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 231:20] + i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 231:20] + i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 231:20] + i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 231:20] + i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 231:20] + i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 231:20] + i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 231:20] + i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 231:20] + i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 231:20] + i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 231:20] + i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 231:20] + i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 231:20] + i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 231:20] + i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 231:20] + i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 231:20] + i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 231:20] + i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 231:20] + i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 231:20] + i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 231:20] + i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 231:20] + i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 231:20] + i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 231:20] + i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 231:20] + i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 231:20] + i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 231:20] + i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 231:20] + i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 231:20] + i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 231:20] + i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 232:20] + i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 233:20] + i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 234:20] + i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 235:20] + i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 236:20] + i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 237:20] + skip @[dec_decode_ctl.scala 230:50] + io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 241:36] + node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 244:40] + node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 244:51] + node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 244:60] + node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 246:51] + node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 246:55] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 246:26] + node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 246:71] + node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 247:51] + node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 247:55] + node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 247:71] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 248:20] + io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 250:37] + io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 251:37] + io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 253:31] + io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 254:31] + io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 255:31] + io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 256:31] + io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 257:31] + io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 258:31] + io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 259:31] + io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 260:31] + io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 261:31] + io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 262:31] + io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 263:31] + io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 264:31] + io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 265:31] + io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 266:31] + io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 267:33] + io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 268:33] + io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 269:33] + node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] + node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 273:137] + node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 273:158] + node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] + node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 273:126] + node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 273:137] + node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 273:158] + node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] + node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 273:126] + node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 273:126] + node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 273:137] + node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 273:158] + node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] + node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 273:126] + node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 273:126] + node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 273:120] + node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 273:129] + node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 273:126] + node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 273:137] + node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 273:158] node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] @@ -67307,410 +67307,410 @@ circuit quasar_wrapper : node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72] wire _T_88 : UInt<4> @[Mux.scala 27:72] _T_88 <= _T_87 @[Mux.scala 27:72] - cam_wen <= _T_88 @[dec_decode_ctl.scala 267:11] - cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 269:25] - node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 270:67] - node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 275:76] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 278:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 278:31] - node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 282:129] + cam_wen <= _T_88 @[dec_decode_ctl.scala 273:11] + cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 275:25] + node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 276:67] + node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 281:76] + node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 284:48] + node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 284:31] + node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 288:129] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 283:56] - node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 285:66] - node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 285:45] - node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 285:87] - cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 285:26] - node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 286:67] - node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 286:45] - node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 286:88] - cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 286:27] - wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] - _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] - _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] - _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 287:14] - cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 287:14] - cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 287:14] - cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 287:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 288:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 288:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 288:11] - cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 288:11] - node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 290:32] - when _T_98 : @[dec_decode_ctl.scala 290:39] - cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] - skip @[dec_decode_ctl.scala 290:39] - node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 293:17] - node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 293:21] - when _T_100 : @[dec_decode_ctl.scala 293:28] - cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] - cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] - cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] - skip @[dec_decode_ctl.scala 293:28] - else : @[dec_decode_ctl.scala 298:131] - node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 298:37] - node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 298:85] - node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 298:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] - node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 298:105] - node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 298:44] - when _T_107 : @[dec_decode_ctl.scala 298:131] - cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] - skip @[dec_decode_ctl.scala 298:131] - else : @[dec_decode_ctl.scala 300:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 301:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 301:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 301:22] - cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 301:22] - skip @[dec_decode_ctl.scala 300:16] - node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] - node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 303:92] - node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 303:44] - node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] - node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 303:113] - when _T_112 : @[dec_decode_ctl.scala 303:135] - cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] - skip @[dec_decode_ctl.scala 303:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] - cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] - skip @[dec_decode_ctl.scala 307:32] - wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] - _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] - _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] - _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 311:47] - _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 311:47] - _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 311:47] - _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 311:47] - _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 311:47] - cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 311:15] - cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 311:15] - cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 311:15] - cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 311:15] - node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 312:46] - node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 312:71] - nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 312:28] - node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 285:66] - node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 285:45] - node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 285:87] - cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 285:26] - node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 286:67] - node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 286:45] - node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 286:88] - cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 286:27] - wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] - _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] - _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] - _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 287:14] - cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 287:14] - cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 287:14] - cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 287:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 288:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 288:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 288:11] - cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 288:11] - node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 290:32] - when _T_124 : @[dec_decode_ctl.scala 290:39] - cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] - skip @[dec_decode_ctl.scala 290:39] - node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 293:17] - node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 293:21] - when _T_126 : @[dec_decode_ctl.scala 293:28] - cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] - cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] - cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] - skip @[dec_decode_ctl.scala 293:28] - else : @[dec_decode_ctl.scala 298:131] - node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 298:37] - node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 298:85] - node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 298:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] - node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 298:105] - node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 298:44] - when _T_133 : @[dec_decode_ctl.scala 298:131] - cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] - skip @[dec_decode_ctl.scala 298:131] - else : @[dec_decode_ctl.scala 300:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 301:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 301:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 301:22] - cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 301:22] - skip @[dec_decode_ctl.scala 300:16] - node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] - node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 303:92] - node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 303:44] - node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] - node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 303:113] - when _T_138 : @[dec_decode_ctl.scala 303:135] - cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] - skip @[dec_decode_ctl.scala 303:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] - cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] - skip @[dec_decode_ctl.scala 307:32] - wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] - _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] - _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] - _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 311:47] - _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 311:47] - _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 311:47] - _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 311:47] - _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 311:47] - cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 311:15] - cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 311:15] - cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 311:15] - cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 311:15] - node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 312:46] - node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 312:71] - nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 312:28] - node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 285:66] - node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 285:45] - node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 285:87] - cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 285:26] - node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 286:67] - node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 286:45] - node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 286:88] - cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 286:27] - wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] - _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] - _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] - _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 287:14] - cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 287:14] - cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 287:14] - cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 287:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 288:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 288:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 288:11] - cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 288:11] - node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 290:32] - when _T_150 : @[dec_decode_ctl.scala 290:39] - cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] - skip @[dec_decode_ctl.scala 290:39] - node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 293:17] - node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 293:21] - when _T_152 : @[dec_decode_ctl.scala 293:28] - cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] - cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] - cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] - skip @[dec_decode_ctl.scala 293:28] - else : @[dec_decode_ctl.scala 298:131] - node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 298:37] - node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 298:85] - node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 298:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] - node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 298:105] - node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 298:44] - when _T_159 : @[dec_decode_ctl.scala 298:131] - cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] - skip @[dec_decode_ctl.scala 298:131] - else : @[dec_decode_ctl.scala 300:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 301:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 301:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 301:22] - cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 301:22] - skip @[dec_decode_ctl.scala 300:16] - node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] - node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 303:92] - node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 303:44] - node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] - node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 303:113] - when _T_164 : @[dec_decode_ctl.scala 303:135] - cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] - skip @[dec_decode_ctl.scala 303:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] - cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] - skip @[dec_decode_ctl.scala 307:32] - wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] - _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] - _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] - _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 311:47] - _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 311:47] - _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 311:47] - _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 311:47] - _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 311:47] - cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 311:15] - cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 311:15] - cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 311:15] - cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 311:15] - node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 312:46] - node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 312:71] - nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 312:28] - node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 285:66] - node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 285:45] - node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 285:87] - cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 285:26] - node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 286:67] - node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 286:45] - node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 286:88] - cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 286:27] - wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] - _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] - _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] - _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] - cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 287:14] - cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 287:14] - cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 287:14] - cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 287:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 288:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 288:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 288:11] - cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 288:11] - node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 290:32] - when _T_176 : @[dec_decode_ctl.scala 290:39] - cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] - skip @[dec_decode_ctl.scala 290:39] - node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 293:17] - node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 293:21] - when _T_178 : @[dec_decode_ctl.scala 293:28] - cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] - cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] - cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] - skip @[dec_decode_ctl.scala 293:28] - else : @[dec_decode_ctl.scala 298:131] - node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 298:37] - node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 298:85] - node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 298:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] - node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 298:105] - node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 298:44] - when _T_185 : @[dec_decode_ctl.scala 298:131] - cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] - skip @[dec_decode_ctl.scala 298:131] - else : @[dec_decode_ctl.scala 300:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 301:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 301:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 301:22] - cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 301:22] - skip @[dec_decode_ctl.scala 300:16] - node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] - node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 303:92] - node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 303:44] - node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] - node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 303:113] - when _T_190 : @[dec_decode_ctl.scala 303:135] - cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] - skip @[dec_decode_ctl.scala 303:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] - cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] - skip @[dec_decode_ctl.scala 307:32] - wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] - _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] - _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] - _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] - reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 311:47] - _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 311:47] - _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 311:47] - _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 311:47] - _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 311:47] - cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 311:15] - cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 311:15] - cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 311:15] - cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 311:15] - node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 312:46] - node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 312:71] - nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 312:28] - io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 315:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 317:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 317:81] - node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 318:108] - node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 318:108] - node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 318:108] - node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 318:112] - node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 318:77] - node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 318:122] - node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 318:119] - io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 318:28] - node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 319:54] - node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:66] - node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 319:110] - node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 319:161] - node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:173] - node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 319:217] - node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 319:142] - i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 321:26] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 289:56] + node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 291:66] + node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 291:45] + node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 291:87] + cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 291:26] + node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 292:67] + node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 292:45] + node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 292:88] + cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 292:27] + wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] + _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] + _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] + _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 293:14] + cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 293:14] + cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 293:14] + cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 293:14] + cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 294:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 294:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 294:11] + cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 294:11] + node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 296:32] + when _T_98 : @[dec_decode_ctl.scala 296:39] + cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] + skip @[dec_decode_ctl.scala 296:39] + node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 299:17] + node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 299:21] + when _T_100 : @[dec_decode_ctl.scala 299:28] + cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] + cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] + cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] + skip @[dec_decode_ctl.scala 299:28] + else : @[dec_decode_ctl.scala 304:131] + node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 304:37] + node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] + node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 304:85] + node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 304:64] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] + node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 304:105] + node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 304:44] + when _T_107 : @[dec_decode_ctl.scala 304:131] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] + skip @[dec_decode_ctl.scala 304:131] + else : @[dec_decode_ctl.scala 306:16] + cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 307:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 307:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 307:22] + cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 307:22] + skip @[dec_decode_ctl.scala 306:16] + node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] + node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 309:92] + node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 309:44] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] + node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 309:113] + when _T_112 : @[dec_decode_ctl.scala 309:135] + cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] + skip @[dec_decode_ctl.scala 309:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] + skip @[dec_decode_ctl.scala 313:32] + wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] + _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] + _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] + _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 317:47] + _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 317:47] + _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 317:47] + _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 317:47] + _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 317:47] + cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 317:15] + cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 317:15] + cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 317:15] + cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 317:15] + node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 318:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 318:71] + nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 318:28] + node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 291:66] + node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 291:45] + node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 291:87] + cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 291:26] + node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 292:67] + node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 292:45] + node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 292:88] + cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 292:27] + wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] + _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] + _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] + _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 293:14] + cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 293:14] + cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 293:14] + cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 293:14] + cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 294:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 294:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 294:11] + cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 294:11] + node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 296:32] + when _T_124 : @[dec_decode_ctl.scala 296:39] + cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] + skip @[dec_decode_ctl.scala 296:39] + node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 299:17] + node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 299:21] + when _T_126 : @[dec_decode_ctl.scala 299:28] + cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] + cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] + cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] + skip @[dec_decode_ctl.scala 299:28] + else : @[dec_decode_ctl.scala 304:131] + node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 304:37] + node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] + node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 304:85] + node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 304:64] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] + node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 304:105] + node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 304:44] + when _T_133 : @[dec_decode_ctl.scala 304:131] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] + skip @[dec_decode_ctl.scala 304:131] + else : @[dec_decode_ctl.scala 306:16] + cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 307:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 307:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 307:22] + cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 307:22] + skip @[dec_decode_ctl.scala 306:16] + node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] + node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 309:92] + node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 309:44] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] + node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 309:113] + when _T_138 : @[dec_decode_ctl.scala 309:135] + cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] + skip @[dec_decode_ctl.scala 309:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] + skip @[dec_decode_ctl.scala 313:32] + wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] + _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] + _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] + _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 317:47] + _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 317:47] + _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 317:47] + _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 317:47] + _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 317:47] + cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 317:15] + cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 317:15] + cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 317:15] + cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 317:15] + node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 318:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 318:71] + nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 318:28] + node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 291:66] + node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 291:45] + node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 291:87] + cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 291:26] + node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 292:67] + node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 292:45] + node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 292:88] + cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 292:27] + wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] + _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] + _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] + _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 293:14] + cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 293:14] + cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 293:14] + cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 293:14] + cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 294:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 294:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 294:11] + cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 294:11] + node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 296:32] + when _T_150 : @[dec_decode_ctl.scala 296:39] + cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] + skip @[dec_decode_ctl.scala 296:39] + node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 299:17] + node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 299:21] + when _T_152 : @[dec_decode_ctl.scala 299:28] + cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] + cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] + cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] + skip @[dec_decode_ctl.scala 299:28] + else : @[dec_decode_ctl.scala 304:131] + node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 304:37] + node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] + node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 304:85] + node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 304:64] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] + node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 304:105] + node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 304:44] + when _T_159 : @[dec_decode_ctl.scala 304:131] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] + skip @[dec_decode_ctl.scala 304:131] + else : @[dec_decode_ctl.scala 306:16] + cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 307:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 307:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 307:22] + cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 307:22] + skip @[dec_decode_ctl.scala 306:16] + node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] + node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 309:92] + node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 309:44] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] + node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 309:113] + when _T_164 : @[dec_decode_ctl.scala 309:135] + cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] + skip @[dec_decode_ctl.scala 309:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] + skip @[dec_decode_ctl.scala 313:32] + wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] + _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] + _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] + _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 317:47] + _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 317:47] + _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 317:47] + _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 317:47] + _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 317:47] + cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 317:15] + cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 317:15] + cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 317:15] + cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 317:15] + node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 318:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 318:71] + nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 318:28] + node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 291:66] + node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 291:45] + node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 291:87] + cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 291:26] + node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 292:67] + node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 292:45] + node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 292:88] + cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 292:27] + wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] + _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] + _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] + _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] + cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 293:14] + cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 293:14] + cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 293:14] + cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 293:14] + cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 294:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 294:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 294:11] + cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 294:11] + node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 296:32] + when _T_176 : @[dec_decode_ctl.scala 296:39] + cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] + skip @[dec_decode_ctl.scala 296:39] + node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 299:17] + node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 299:21] + when _T_178 : @[dec_decode_ctl.scala 299:28] + cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] + cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] + cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] + skip @[dec_decode_ctl.scala 299:28] + else : @[dec_decode_ctl.scala 304:131] + node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 304:37] + node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] + node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 304:85] + node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 304:64] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] + node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 304:105] + node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 304:44] + when _T_185 : @[dec_decode_ctl.scala 304:131] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] + skip @[dec_decode_ctl.scala 304:131] + else : @[dec_decode_ctl.scala 306:16] + cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 307:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 307:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 307:22] + cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 307:22] + skip @[dec_decode_ctl.scala 306:16] + node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] + node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 309:92] + node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 309:44] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] + node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 309:113] + when _T_190 : @[dec_decode_ctl.scala 309:135] + cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] + skip @[dec_decode_ctl.scala 309:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] + skip @[dec_decode_ctl.scala 313:32] + wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] + _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] + _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] + _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] + reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 317:47] + _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 317:47] + _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 317:47] + _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 317:47] + _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 317:47] + cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 317:15] + cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 317:15] + cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 317:15] + cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 317:15] + node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 318:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 318:71] + nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 318:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 321:29] + node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 323:49] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 323:81] + node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 324:108] + node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 324:108] + node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 324:108] + node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 324:112] + node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 324:77] + node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 324:122] + node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 324:119] + io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 324:28] + node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 325:54] + node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:66] + node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 325:110] + node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 325:161] + node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:173] + node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 325:217] + node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 325:142] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 327:26] node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 323:88] - node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:137] - node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] - node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 323:152] - node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:214] - node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] - node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 323:229] + node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 329:88] + node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:137] + node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] + node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 329:152] + node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:214] + node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] + node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 329:229] node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 323:88] - node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:137] - node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] - node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 323:152] - node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:214] - node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] - node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 323:229] + node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 329:88] + node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:137] + node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] + node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 329:152] + node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:214] + node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] + node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 329:229] node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 323:88] - node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:137] - node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] - node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 323:152] - node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:214] - node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] - node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 323:229] + node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 329:88] + node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:137] + node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] + node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 329:152] + node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:214] + node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] + node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 329:229] node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 323:88] - node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:137] - node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] - node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 323:152] - node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:214] - node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] - node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 323:229] - node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 324:69] - node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 324:69] - node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 324:69] - node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 324:102] - node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 324:102] - node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 324:102] - node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 324:134] - node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 324:134] - node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 324:134] - io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 325:29] - node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 326:38] - node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 326:51] - i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 326:25] - node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 335:34] - node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 335:32] + node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 329:88] + node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:137] + node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] + node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 329:152] + node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:214] + node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] + node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 329:229] + node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 330:69] + node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 330:69] + node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 330:69] + node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 330:102] + node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 330:102] + node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 330:102] + node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 330:134] + node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 330:134] + node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 330:134] + io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 331:29] + node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 332:38] + node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 332:51] + i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 332:25] + node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 341:34] + node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 341:32] node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 347:16] - node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 347:30] - node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 348:6] - node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 348:16] - node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 348:30] - node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 349:18] - node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 349:16] - node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 349:30] + node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 353:16] + node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 353:30] + node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 354:6] + node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 354:16] + node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 354:30] + node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 355:18] + node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 355:16] + node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 355:30] node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16] node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16] @@ -67725,244 +67725,244 @@ circuit quasar_wrapper : node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16] node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16] node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16] - node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 339:49] - d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 339:21] - inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 356:22] + node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 345:49] + d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 345:21] + inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 362:22] i0_dec.clock <= clock i0_dec.reset <= reset - i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 357:16] - i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 358:12] - i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 358:12] - i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 358:12] - i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 358:12] - i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 358:12] - i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 358:12] - i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 358:12] - i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 358:12] - i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 358:12] - i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 358:12] - i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 358:12] - i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 358:12] - i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 358:12] - i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 358:12] - i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 358:12] - i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 358:12] - i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 358:12] - i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 358:12] - i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 358:12] - i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 358:12] - i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 358:12] - i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 358:12] - i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 358:12] - i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 358:12] - i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 358:12] - i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 358:12] - i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 358:12] - i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 358:12] - i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 358:12] - i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 358:12] - i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 358:12] - i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 358:12] - i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 358:12] - i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 358:12] - i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 358:12] - i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 358:12] - i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 358:12] - i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 358:12] - i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 358:12] - i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 358:12] - i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 358:12] - i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 358:12] - i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 358:12] - i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 358:12] - i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 358:12] - reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 360:45] - _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 360:45] - lsu_idle <= _T_279 @[dec_decode_ctl.scala 360:11] - node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 363:73] - node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 363:71] - node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 363:53] - leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 363:21] - reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 364:56] - _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 364:56] - leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 364:21] - leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 365:14] - node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 366:53] - node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 366:91] - node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 366:89] - node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 366:71] - leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 366:21] - reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 367:56] - _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 367:56] - leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 367:21] - node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 371:29] - node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 371:36] - node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 371:46] - node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 371:53] + i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 363:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 364:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 364:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 364:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 364:12] + i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 364:12] + i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 364:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 364:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 364:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 364:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 364:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 364:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 364:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 364:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 364:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 364:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 364:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 364:12] + i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 364:12] + i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 364:12] + i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 364:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 364:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 364:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 364:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 364:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 364:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 364:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 364:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 364:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 364:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 364:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 364:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 364:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 364:12] + i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 364:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 364:12] + i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 364:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 364:12] + i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 364:12] + i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 364:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 364:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 364:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 364:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 364:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 364:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 364:12] + reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 366:45] + _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 366:45] + lsu_idle <= _T_279 @[dec_decode_ctl.scala 366:11] + node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 369:73] + node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 369:71] + node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 369:53] + leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 369:21] + reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 370:56] + _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 370:56] + leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 370:21] + leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 371:14] + node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 372:53] + node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 372:91] + node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 372:89] + node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 372:71] + leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 372:21] + reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 373:56] + _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 373:56] + leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 373:21] + node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 377:29] + node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 377:36] + node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 377:46] + node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 377:53] node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58] node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58] node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58] - node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 372:46] - node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 372:51] - node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:71] - node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 372:79] - node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:104] - node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 372:112] - node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 372:33] - node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 373:47] - node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 373:76] - node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 373:98] - node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 373:89] - node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 373:65] - node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 374:47] - node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 374:76] - node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 374:98] - node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 374:89] - node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 374:67] - node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 374:65] - node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 375:38] - i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 375:20] - node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 376:38] - i0_pcall <= _T_311 @[dec_decode_ctl.scala 376:20] - node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 377:38] - i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 377:20] - node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 378:38] - i0_pja <= _T_313 @[dec_decode_ctl.scala 378:20] - node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 379:41] - node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 379:55] - node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 379:75] - node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 379:90] - node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 379:97] - node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 379:103] - node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 379:113] + node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 378:46] + node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 378:51] + node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 378:79] + node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 378:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 378:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 379:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 379:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 379:98] + node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 379:89] + node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 379:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 380:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 380:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 380:98] + node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 380:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 380:67] + node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 380:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 381:38] + i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 381:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 382:38] + i0_pcall <= _T_311 @[dec_decode_ctl.scala 382:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 383:38] + i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 383:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 384:38] + i0_pja <= _T_313 @[dec_decode_ctl.scala 384:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 385:41] + node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 385:55] + node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 385:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 385:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 385:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 385:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 385:113] node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] - node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 379:26] - i0_br_offset <= _T_324 @[dec_decode_ctl.scala 379:20] - node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 381:37] - node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 381:65] - node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 381:55] - node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 381:89] - node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 381:111] - node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 381:101] - node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 381:79] - node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 382:32] - i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 382:15] - node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 383:32] - i0_pret <= _T_332 @[dec_decode_ctl.scala 383:15] - node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:35] - node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 384:32] - node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:52] - node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 384:50] - node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:67] - node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 384:65] - i0_jal <= _T_338 @[dec_decode_ctl.scala 384:15] - io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 387:29] - io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 388:34] - io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 389:34] - io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 391:32] - io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 392:37] - io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 393:37] - io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 394:37] - reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 396:69] - _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 396:69] - io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 396:34] - wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 398:27] - _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] - io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 398:12] - io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 398:12] - io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 398:12] - when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 399:40] - io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 400:29] - io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 401:29] - io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 402:29] - io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 403:24] - skip @[dec_decode_ctl.scala 399:40] - else : @[dec_decode_ctl.scala 404:15] - io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 405:35] - io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 406:40] - io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 407:40] - io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 408:40] - io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 409:40] - io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 410:40] - io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 411:40] - io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 412:40] - io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 413:40] - io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 414:40] - skip @[dec_decode_ctl.scala 404:15] - io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 418:29] - node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 419:56] - node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 419:36] - csr_read <= _T_342 @[dec_decode_ctl.scala 419:18] - node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 421:42] - node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 421:40] - node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 422:61] - node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 422:41] - node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 423:59] - node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 423:39] - node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 424:59] - node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 424:39] - node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 426:41] - node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 426:39] - i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 426:23] - node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 427:42] - node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 427:58] - io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 427:24] - node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 430:30] - io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 430:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 431:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 435:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 435:53] - node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 435:51] - io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 435:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 438:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 438:85] - node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 438:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 438:100] - node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 438:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 438:132] - node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 438:130] - io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 438:27] - reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 440:52] - csr_read_x <= csr_read @[dec_decode_ctl.scala 440:52] - reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 441:51] - csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 441:51] - reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:51] - csr_set_x <= csr_set_d @[dec_decode_ctl.scala 442:51] - reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 443:53] - csr_write_x <= csr_write_d @[dec_decode_ctl.scala 443:53] - reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:51] - csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 444:51] - node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 447:27] - node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 447:48] + node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 385:26] + i0_br_offset <= _T_324 @[dec_decode_ctl.scala 385:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 387:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 387:65] + node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 387:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 387:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 387:111] + node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 387:101] + node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 387:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 388:32] + i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 388:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 389:32] + i0_pret <= _T_332 @[dec_decode_ctl.scala 389:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:35] + node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 390:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:52] + node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 390:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:67] + node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 390:65] + i0_jal <= _T_338 @[dec_decode_ctl.scala 390:15] + io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 393:29] + io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 394:34] + io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 395:34] + io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 397:32] + io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 398:37] + io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 399:37] + io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 400:37] + reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 402:69] + _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 402:69] + io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 402:34] + wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 404:27] + _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] + io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 404:12] + io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 404:12] + io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 404:12] + when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 405:40] + io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 406:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 407:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 408:29] + io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 409:24] + skip @[dec_decode_ctl.scala 405:40] + else : @[dec_decode_ctl.scala 410:15] + io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 411:35] + io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 412:40] + io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 413:40] + io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 414:40] + io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 415:40] + io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 416:40] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 417:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 418:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 419:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 420:40] + skip @[dec_decode_ctl.scala 410:15] + io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 424:29] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 425:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 425:36] + csr_read <= _T_342 @[dec_decode_ctl.scala 425:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 427:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 427:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 428:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 428:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 429:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 429:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 430:59] + node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 430:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 432:41] + node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 432:39] + i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 432:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 433:42] + node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 433:58] + io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 433:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 436:30] + io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 436:24] + io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 437:23] + node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 441:39] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 441:53] + node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 441:51] + io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 441:20] + node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 444:50] + node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 444:85] + node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 444:64] + node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 444:100] + node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 444:118] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 444:132] + node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 444:130] + io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 444:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 446:52] + csr_read_x <= csr_read @[dec_decode_ctl.scala 446:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 447:51] + csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 447:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 448:51] + csr_set_x <= csr_set_d @[dec_decode_ctl.scala 448:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 449:53] + csr_write_x <= csr_write_d @[dec_decode_ctl.scala 449:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 450:51] + csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 450:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 453:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 453:48] inst rvclkhdr_1 of rvclkhdr_662 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -67971,7 +67971,7 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] csrimm_x <= _T_362 @[lib.scala 374:16] - node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 448:62] + node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 454:62] inst rvclkhdr_2 of rvclkhdr_663 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -67980,7 +67980,7 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] csr_rddata_x <= io.dec_csr_rddata_d @[lib.scala 374:16] - node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 451:15] + node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 457:15] wire _T_366 : UInt<1>[27] @[lib.scala 12:48] _T_366[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_366[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68035,18 +68035,18 @@ circuit quasar_wrapper : node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] - node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 451:53] + node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 457:53] node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] - node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 452:16] - node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 452:5] + node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 458:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 458:5] node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] node _T_398 = mux(_T_396, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] wire csr_mask_x : UInt<32> @[Mux.scala 27:72] csr_mask_x <= _T_399 @[Mux.scala 27:72] - node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 455:38] - node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 455:35] - node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 456:35] + node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 461:38] + node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 461:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 462:35] node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68054,42 +68054,42 @@ circuit quasar_wrapper : node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] wire write_csr_data_x : UInt @[Mux.scala 27:72] write_csr_data_x <= _T_407 @[Mux.scala 27:72] - node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 459:49] - node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 459:47] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 465:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 465:47] node _T_410 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 459:145] + node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 465:145] node _T_412 = cat(_T_410, _T_411) @[Cat.scala 29:58] - node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 459:109] - node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 459:91] - node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 459:76] - node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 460:44] - node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 460:61] - node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 460:59] - pause_state_in <= _T_417 @[dec_decode_ctl.scala 460:18] - reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 461:50] - _T_418 <= pause_state_in @[dec_decode_ctl.scala 461:50] - pause_stall <= _T_418 @[dec_decode_ctl.scala 461:15] - io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 462:22] - reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 463:55] - _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 463:55] - tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 463:19] - reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 464:55] - _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 464:55] - tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 464:19] - node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 466:44] - node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 466:64] - node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:61] - node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 466:41] - io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 466:25] - node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 469:59] - node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 469:59] - node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 470:8] - node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 469:30] - node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 471:34] - node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 471:46] - node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 471:61] - node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 471:75] - node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 471:99] + node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 465:109] + node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 465:91] + node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 465:76] + node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 466:44] + node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 466:61] + node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 466:59] + pause_state_in <= _T_417 @[dec_decode_ctl.scala 466:18] + reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 467:50] + _T_418 <= pause_state_in @[dec_decode_ctl.scala 467:50] + pause_stall <= _T_418 @[dec_decode_ctl.scala 467:15] + io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 468:22] + reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 469:55] + _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 469:55] + tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 469:19] + reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 470:55] + _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 470:55] + tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 470:19] + node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 472:44] + node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 472:64] + node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 472:61] + node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 472:41] + io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 472:25] + node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 475:59] + node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 475:59] + node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 476:8] + node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 475:30] + node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 477:34] + node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 477:46] + node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 477:61] + node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 477:75] + node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 477:99] inst rvclkhdr_3 of rvclkhdr_664 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -68098,33 +68098,33 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_432 <= write_csr_data_in @[lib.scala 374:16] - write_csr_data <= _T_432 @[dec_decode_ctl.scala 472:18] - node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 478:49] - node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 478:30] - io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 478:24] - node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 480:43] - node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 480:63] - node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 482:76] - node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 482:48] - node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 483:76] - node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 483:48] - node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 484:40] - debug_fence <= _T_438 @[dec_decode_ctl.scala 484:21] - node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 487:34] - node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 487:57] - node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 487:73] - node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 487:91] - node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 490:36] - node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 490:60] - node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 490:104] - node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 490:112] - node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 490:99] - node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 490:76] - node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 492:34] - io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 493:24] - node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 494:40] - node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 494:51] - node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 494:37] + write_csr_data <= _T_432 @[dec_decode_ctl.scala 478:18] + node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 484:49] + node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 484:30] + io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 484:24] + node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 486:43] + node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 486:63] + node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 488:76] + node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 488:48] + node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 489:76] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 489:48] + node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 490:40] + debug_fence <= _T_438 @[dec_decode_ctl.scala 490:21] + node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 493:34] + node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 493:57] + node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 493:73] + node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 493:91] + node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 496:36] + node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 496:60] + node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 496:104] + node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 496:112] + node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 496:99] + node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 496:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 498:34] + io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 499:24] + node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 500:40] + node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 500:51] + node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 500:37] wire _T_449 : UInt<1>[16] @[lib.scala 12:48] _T_449[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_449[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68158,11 +68158,11 @@ circuit quasar_wrapper : node _T_463 = cat(_T_462, _T_449[14]) @[Cat.scala 29:58] node _T_464 = cat(_T_463, _T_449[15]) @[Cat.scala 29:58] node _T_465 = cat(_T_464, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] - node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 495:27] - node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 498:57] - node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 498:55] - node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 499:44] - node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 499:42] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 501:27] + node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 504:57] + node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 504:55] + node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 505:44] + node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 505:42] inst rvclkhdr_4 of rvclkhdr_665 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -68171,94 +68171,94 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_468 <= i0_inst_d @[lib.scala 374:16] - io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 500:23] - node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 501:40] - node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 501:61] - node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 501:59] - illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 501:22] - reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 502:54] - _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 502:54] - illegal_lockout <= _T_472 @[dec_decode_ctl.scala 502:19] - node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 503:42] - node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 505:40] - node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 505:59] - node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 505:92] - node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 505:106] - node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 506:20] - node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 506:45] - node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 506:62] - node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 507:19] - node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 507:36] - node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 507:34] - node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 506:79] - node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 507:47] - node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 507:72] - node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 508:21] - node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 508:45] - node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 510:65] - node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 510:39] - node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 511:63] - node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 511:38] - node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 512:38] - node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 512:57] - node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 516:54] - node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 516:52] - node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:71] - node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 516:69] - node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:99] - node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 516:97] - io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 516:30] - node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 517:46] - node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 517:44] - node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:63] - node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 517:61] - node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:91] - node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 517:89] - node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 518:46] - io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 521:28] - node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:51] - node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 522:49] - io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 522:27] - node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 523:47] - io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 523:29] - node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 524:46] - io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 524:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 528:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 529:31] - node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 531:37] - presync_stall <= _T_505 @[dec_decode_ctl.scala 531:22] - reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 532:53] - _T_506 <= ps_stall_in @[dec_decode_ctl.scala 532:53] - postsync_stall <= _T_506 @[dec_decode_ctl.scala 532:18] - node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 534:64] - node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 534:62] - node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 534:47] - node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 534:96] - node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 534:77] - ps_stall_in <= _T_511 @[dec_decode_ctl.scala 534:15] - node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 536:58] - io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 536:34] - node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 538:40] - lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 538:16] - node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 539:40] - mul_decode_d <= _T_514 @[dec_decode_ctl.scala 539:16] - node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 540:40] - div_decode_d <= _T_515 @[dec_decode_ctl.scala 540:16] - node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 542:45] - node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 542:43] - io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 542:29] - d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 545:26] - node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 546:40] - d_t.icaf <= _T_518 @[dec_decode_ctl.scala 546:26] - node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 547:50] - d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 547:26] - d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 548:26] - node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 550:44] - node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 550:61] - d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 550:26] - d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 553:26] - d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 554:26] - d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 555:26] + io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 506:23] + node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 507:40] + node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 507:61] + node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 507:59] + illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 507:22] + reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 508:54] + _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 508:54] + illegal_lockout <= _T_472 @[dec_decode_ctl.scala 508:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 509:42] + node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 511:40] + node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 511:59] + node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 511:92] + node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 511:106] + node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 512:20] + node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 512:45] + node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 512:62] + node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 513:19] + node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 513:36] + node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 513:34] + node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 512:79] + node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 513:47] + node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 513:72] + node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 514:21] + node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 514:45] + node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 516:65] + node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 516:39] + node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 517:63] + node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 517:38] + node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 518:38] + node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 518:57] + node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:54] + node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 522:52] + node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:71] + node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 522:69] + node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:99] + node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 522:97] + io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 522:30] + node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 523:46] + node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 523:44] + node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:63] + node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 523:61] + node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:91] + node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 523:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 524:46] + io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 527:28] + node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 528:51] + node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 528:49] + io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 528:27] + node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 529:47] + io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 529:29] + node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 530:46] + io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 530:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 534:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 535:31] + node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 537:37] + presync_stall <= _T_505 @[dec_decode_ctl.scala 537:22] + reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 538:53] + _T_506 <= ps_stall_in @[dec_decode_ctl.scala 538:53] + postsync_stall <= _T_506 @[dec_decode_ctl.scala 538:18] + node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 540:64] + node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 540:62] + node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 540:47] + node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 540:96] + node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 540:77] + ps_stall_in <= _T_511 @[dec_decode_ctl.scala 540:15] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 542:58] + io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 542:34] + node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 544:40] + lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 544:16] + node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 545:40] + mul_decode_d <= _T_514 @[dec_decode_ctl.scala 545:16] + node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 546:40] + div_decode_d <= _T_515 @[dec_decode_ctl.scala 546:16] + node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 548:45] + node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 548:43] + io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 548:29] + d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 551:26] + node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 552:40] + d_t.icaf <= _T_518 @[dec_decode_ctl.scala 552:26] + node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 553:50] + d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 553:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 554:26] + node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 556:44] + node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 556:61] + d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 556:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 559:26] + d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 560:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 561:26] wire _T_522 : UInt<1>[4] @[lib.scala 12:48] _T_522[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] _T_522[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] @@ -68267,9 +68267,9 @@ circuit quasar_wrapper : node _T_523 = cat(_T_522[0], _T_522[1]) @[Cat.scala 29:58] node _T_524 = cat(_T_523, _T_522[2]) @[Cat.scala 29:58] node _T_525 = cat(_T_524, _T_522[3]) @[Cat.scala 29:58] - node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 557:56] - d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 557:26] - node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 560:33] + node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 563:56] + d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 563:26] + node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 566:33] inst rvclkhdr_5 of rvclkhdr_666 @[lib.scala 378:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -68298,26 +68298,26 @@ circuit quasar_wrapper : _T_529.icaf_f1 <= d_t.icaf_f1 @[lib.scala 384:16] _T_529.icaf <= d_t.icaf @[lib.scala 384:16] _T_529.legal <= d_t.legal @[lib.scala 384:16] - x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 560:7] - x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 560:7] - x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 560:7] - x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 560:7] - x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 560:7] - x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 560:7] - x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 560:7] - x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 560:7] - x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 560:7] - x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 560:7] - x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 562:10] - x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 562:10] - x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 562:10] - x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 562:10] - x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 562:10] - x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 562:10] - x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 562:10] - x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 562:10] - x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 562:10] - x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 562:10] + x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 566:7] + x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 566:7] + x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 566:7] + x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 566:7] + x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 566:7] + x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 566:7] + x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 566:7] + x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 566:7] + x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 566:7] + x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 566:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 568:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 568:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 568:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 568:10] + x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 568:10] + x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 568:10] + x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 568:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 568:10] + x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 568:10] + x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 568:10] wire _T_530 : UInt<1>[4] @[lib.scala 12:48] _T_530[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] _T_530[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] @@ -68326,10 +68326,10 @@ circuit quasar_wrapper : node _T_531 = cat(_T_530[0], _T_530[1]) @[Cat.scala 29:58] node _T_532 = cat(_T_531, _T_530[2]) @[Cat.scala 29:58] node _T_533 = cat(_T_532, _T_530[3]) @[Cat.scala 29:58] - node _T_534 = not(_T_533) @[dec_decode_ctl.scala 563:39] - node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 563:37] - x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 563:20] - node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 565:36] + node _T_534 = not(_T_533) @[dec_decode_ctl.scala 569:39] + node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 569:37] + x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 569:20] + node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 571:36] inst rvclkhdr_6 of rvclkhdr_667 @[lib.scala 378:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -68358,31 +68358,31 @@ circuit quasar_wrapper : _T_538.icaf_f1 <= x_t_in.icaf_f1 @[lib.scala 384:16] _T_538.icaf <= x_t_in.icaf @[lib.scala 384:16] _T_538.legal <= x_t_in.legal @[lib.scala 384:16] - r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 565:7] - r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 565:7] - r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 565:7] - r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 565:7] - r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 565:7] - r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 565:7] - r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 565:7] - r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 565:7] - r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 565:7] - r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 565:7] - reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 566:36] - lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 566:36] - reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 567:37] - lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 567:37] - r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 569:10] - r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 569:10] - r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 569:10] - r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 569:10] - r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 569:10] - r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 569:10] - r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 569:10] - r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 569:10] - r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 569:10] - r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 569:10] - node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 571:61] + r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 571:7] + r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 571:7] + r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 571:7] + r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 571:7] + r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 571:7] + r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 571:7] + r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 571:7] + r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 571:7] + r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 571:7] + r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 571:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 572:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 572:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 573:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 573:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 575:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 575:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 575:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 575:10] + r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 575:10] + r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 575:10] + r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 575:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 575:10] + r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 575:10] + r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 575:10] + node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 577:61] wire _T_540 : UInt<1>[4] @[lib.scala 12:48] _T_540[0] <= _T_539 @[lib.scala 12:48] _T_540[1] <= _T_539 @[lib.scala 12:48] @@ -68391,83 +68391,83 @@ circuit quasar_wrapper : node _T_541 = cat(_T_540[0], _T_540[1]) @[Cat.scala 29:58] node _T_542 = cat(_T_541, _T_540[2]) @[Cat.scala 29:58] node _T_543 = cat(_T_542, _T_540[3]) @[Cat.scala 29:58] - node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 571:82] - node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 571:105] - r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 571:33] - r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 572:33] - node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 574:35] - when _T_546 : @[dec_decode_ctl.scala 574:43] - wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 574:66] - _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] - r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 574:51] - r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 574:51] - r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 574:51] - r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 574:51] - r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 574:51] - r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 574:51] - r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 574:51] - r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 574:51] - r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 574:51] - r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 574:51] - skip @[dec_decode_ctl.scala 574:43] - io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 576:39] - io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 576:39] - node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 577:58] - io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 577:39] - reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 580:52] - _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 580:52] - flush_final_r <= _T_549 @[dec_decode_ctl.scala 580:17] - node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 582:54] - node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 582:52] - node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:68] - node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 582:66] - node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:96] - node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 582:94] - io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 582:30] - node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 584:16] - i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 584:11] - node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 585:16] - i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 585:11] - node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 586:16] - i0r.rd <= _T_558 @[dec_decode_ctl.scala 586:11] - node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 588:60] - node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 588:49] - io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 588:35] - node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 589:60] - node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 589:49] - io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 589:35] - node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 590:48] - node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 590:37] - io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 591:19] - io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 592:19] - node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 594:38] - node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 595:27] - node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 595:38] - node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 599:5] + node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 577:82] + node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 577:105] + r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 577:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 578:33] + node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 580:35] + when _T_546 : @[dec_decode_ctl.scala 580:43] + wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 580:66] + _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] + r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 580:51] + r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 580:51] + r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 580:51] + r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 580:51] + r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 580:51] + r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 580:51] + r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 580:51] + r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 580:51] + r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 580:51] + r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 580:51] + skip @[dec_decode_ctl.scala 580:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 582:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 582:39] + node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 583:58] + io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 583:39] + reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 586:52] + _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 586:52] + flush_final_r <= _T_549 @[dec_decode_ctl.scala 586:17] + node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 588:54] + node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 588:52] + node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:68] + node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 588:66] + node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:96] + node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 588:94] + io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 588:30] + node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 590:16] + i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 590:11] + node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 591:16] + i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 591:11] + node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 592:16] + i0r.rd <= _T_558 @[dec_decode_ctl.scala 592:11] + node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 594:60] + node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 594:49] + io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 594:35] + node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 595:60] + node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 595:49] + io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 595:35] + node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 596:48] + node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 596:37] + io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 597:19] + io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 598:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 600:38] + node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 601:27] + node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 601:38] + node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 605:5] node _T_566 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_567 = mux(_T_565, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72] wire _T_569 : UInt<32> @[Mux.scala 27:72] _T_569 <= _T_568 @[Mux.scala 27:72] - io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 597:32] - node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 602:38] + io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 603:32] + node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 608:38] wire _T_571 : UInt<1>[20] @[lib.scala 12:48] _T_571[0] <= _T_570 @[lib.scala 12:48] _T_571[1] <= _T_570 @[lib.scala 12:48] @@ -68508,7 +68508,7 @@ circuit quasar_wrapper : node _T_588 = cat(_T_587, _T_571[17]) @[Cat.scala 29:58] node _T_589 = cat(_T_588, _T_571[18]) @[Cat.scala 29:58] node _T_590 = cat(_T_589, _T_571[19]) @[Cat.scala 29:58] - node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 602:46] + node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 608:46] node _T_592 = cat(_T_590, _T_591) @[Cat.scala 29:58] wire _T_593 : UInt<1>[27] @[lib.scala 12:48] _T_593[0] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68564,9 +68564,9 @@ circuit quasar_wrapper : node _T_617 = cat(_T_616, _T_593[24]) @[Cat.scala 29:58] node _T_618 = cat(_T_617, _T_593[25]) @[Cat.scala 29:58] node _T_619 = cat(_T_618, _T_593[26]) @[Cat.scala 29:58] - node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 603:43] + node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 609:43] node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58] - node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 604:38] + node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 610:38] wire _T_623 : UInt<1>[12] @[lib.scala 12:48] _T_623[0] <= _T_622 @[lib.scala 12:48] _T_623[1] <= _T_622 @[lib.scala 12:48] @@ -68591,14 +68591,14 @@ circuit quasar_wrapper : node _T_632 = cat(_T_631, _T_623[9]) @[Cat.scala 29:58] node _T_633 = cat(_T_632, _T_623[10]) @[Cat.scala 29:58] node _T_634 = cat(_T_633, _T_623[11]) @[Cat.scala 29:58] - node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 604:46] - node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 604:56] - node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 604:63] + node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 610:46] + node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 610:56] + node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 610:63] node _T_638 = cat(_T_637, UInt<1>("h00")) @[Cat.scala 29:58] node _T_639 = cat(_T_634, _T_635) @[Cat.scala 29:58] node _T_640 = cat(_T_639, _T_636) @[Cat.scala 29:58] node _T_641 = cat(_T_640, _T_638) @[Cat.scala 29:58] - node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 605:30] + node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 611:30] wire _T_643 : UInt<1>[12] @[lib.scala 12:48] _T_643[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_643[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68624,8 +68624,8 @@ circuit quasar_wrapper : node _T_653 = cat(_T_652, _T_643[10]) @[Cat.scala 29:58] node _T_654 = cat(_T_653, _T_643[11]) @[Cat.scala 29:58] node _T_655 = cat(_T_642, _T_654) @[Cat.scala 29:58] - node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 606:26] - node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 606:43] + node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 612:26] + node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 612:43] wire _T_658 : UInt<1>[27] @[lib.scala 12:48] _T_658[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_658[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68680,7 +68680,7 @@ circuit quasar_wrapper : node _T_682 = cat(_T_681, _T_658[24]) @[Cat.scala 29:58] node _T_683 = cat(_T_682, _T_658[25]) @[Cat.scala 29:58] node _T_684 = cat(_T_683, _T_658[26]) @[Cat.scala 29:58] - node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 606:72] + node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 612:72] node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58] node _T_687 = mux(i0_dp.imm12, _T_592, UInt<1>("h00")) @[Mux.scala 27:72] node _T_688 = mux(i0_dp.shimm5, _T_621, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68693,87 +68693,87 @@ circuit quasar_wrapper : node _T_695 = or(_T_694, _T_691) @[Mux.scala 27:72] wire _T_696 : UInt<32> @[Mux.scala 27:72] _T_696 <= _T_695 @[Mux.scala 27:72] - i0_immed_d <= _T_696 @[dec_decode_ctl.scala 601:14] - node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 608:54] - i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 608:24] - node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 610:44] - i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 610:29] - node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 611:44] - i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 611:29] - node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 612:44] - i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 612:29] - wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 614:70] - _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] - _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] - _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] - node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 614:92] + i0_immed_d <= _T_696 @[dec_decode_ctl.scala 607:14] + node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 614:54] + i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 614:24] + node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 616:44] + i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 616:29] + node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 617:44] + i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 617:29] + node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 618:44] + i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 618:29] + wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 620:70] + _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70] + _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70] + _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70] + node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 620:92] reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_701)) @[Reg.scala 27:20] when _T_702 : @[Reg.scala 28:19] i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23] i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23] i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 615:70] - _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] - _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] - _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] - node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 615:92] + wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 621:70] + _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70] + _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70] + _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70] + node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 621:92] reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_703)) @[Reg.scala 27:20] when _T_704 : @[Reg.scala 28:19] i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23] i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23] i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 616:91] - reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 616:80] - _T_706 <= _T_705 @[dec_decode_ctl.scala 616:80] + node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 622:91] + reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 622:80] + _T_706 <= _T_705 @[dec_decode_ctl.scala 622:80] node _T_707 = cat(io.dec_aln.dec_i0_decode_d, _T_706) @[Cat.scala 29:58] - i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 616:14] - node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 618:43] - node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 618:49] - node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 618:53] - i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 618:29] - node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 619:43] - node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 619:49] - node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 619:53] - i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 619:29] - node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 620:43] - node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 620:49] - node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 620:53] - i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 620:29] - node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 621:44] - node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 621:50] - i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 621:29] - node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 622:44] - node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 622:50] - i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 622:29] - node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 623:44] - node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 623:50] - i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 623:29] - node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 624:44] - node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 624:50] - i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 624:29] + i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 622:14] + node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 624:43] + node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 624:49] + node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 624:53] + i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 624:29] + node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 625:43] + node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 625:49] + node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 625:53] + i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 625:29] + node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 626:43] + node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 626:49] + node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 626:53] + i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 626:29] + node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 627:44] + node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 627:50] + i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 627:29] + node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 628:44] + node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 628:50] + i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 628:29] + node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 629:44] + node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 629:50] + i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 629:29] + node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 630:44] + node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 630:50] + i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 630:29] node _T_725 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] - io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 626:38] + io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 632:38] node _T_726 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] - io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 627:38] - d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 629:34] - node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 630:50] - d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 630:34] - d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 631:27] - node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 633:50] - d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 633:34] - node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 634:50] - d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 634:34] - node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 635:50] - d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 635:34] - node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 637:61] - d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 637:34] - node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 638:58] - d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 638:34] - node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 639:40] - d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 639:34] - node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 641:34] + io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 633:38] + d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 635:34] + node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 636:50] + d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 636:34] + d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 637:27] + node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 639:50] + d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 639:34] + node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 640:50] + d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 640:34] + node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 641:50] + d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 641:34] + node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:61] + d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 643:34] + node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 644:58] + d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 644:34] + node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40] + d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 645:34] + node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34] inst rvclkhdr_7 of rvclkhdr_668 @[lib.scala 378:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -68800,36 +68800,36 @@ circuit quasar_wrapper : _T_736.bits.i0load <= d_d.bits.i0load @[lib.scala 384:16] _T_736.bits.i0rd <= d_d.bits.i0rd @[lib.scala 384:16] _T_736.valid <= d_d.valid @[lib.scala 384:16] - x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 641:7] - x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 641:7] - x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 641:7] - x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 641:7] - x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 641:7] - x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 641:7] - x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 641:7] - x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 641:7] - x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 641:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 642:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 643:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 643:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 643:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 643:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 643:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 643:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 643:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 643:10] - x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 643:10] - node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 644:49] - node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 644:47] - node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 644:78] - node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 644:76] - x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 644:27] - node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 645:35] - node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 645:33] - node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 645:64] - node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 645:62] - x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 645:20] - node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:36] + x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 647:7] + x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 647:7] + x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 647:7] + x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 647:7] + x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 647:7] + x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 647:7] + x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 647:7] + x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 647:7] + x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 647:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 648:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 649:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 649:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 649:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 649:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 649:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 649:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 649:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 649:10] + x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 649:10] + node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 650:49] + node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 650:47] + node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 650:78] + node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 650:76] + x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 650:27] + node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:35] + node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 651:33] + node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 651:64] + node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 651:62] + x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 651:20] + node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36] inst rvclkhdr_8 of rvclkhdr_669 @[lib.scala 378:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -68856,38 +68856,38 @@ circuit quasar_wrapper : _T_747.bits.i0load <= x_d_in.bits.i0load @[lib.scala 384:16] _T_747.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 384:16] _T_747.valid <= x_d_in.valid @[lib.scala 384:16] - r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 647:7] - r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 647:7] - r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 647:7] - r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 647:7] - r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 647:7] - r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 647:7] - r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 647:7] - r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 647:7] - r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 647:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 648:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 648:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 648:10] - r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 648:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 649:22] - node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:51] - node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 651:49] - r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 651:27] - node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 652:37] - node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 652:35] - r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 652:20] - node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 653:51] - node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 653:49] - r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 653:27] - node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 654:51] - node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 654:49] - r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 654:27] - node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 656:37] + r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 653:7] + r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 653:7] + r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 653:7] + r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 653:7] + r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 653:7] + r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 653:7] + r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 653:7] + r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 653:7] + r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 653:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 654:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 654:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 654:10] + r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 654:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 655:22] + node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 657:51] + node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 657:49] + r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 657:27] + node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 658:37] + node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 658:35] + r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 658:20] + node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 659:51] + node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 659:49] + r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 659:27] + node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 660:51] + node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 660:49] + r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 660:27] + node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37] inst rvclkhdr_9 of rvclkhdr_670 @[lib.scala 378:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -68914,26 +68914,26 @@ circuit quasar_wrapper : _T_758.bits.i0load <= r_d_in.bits.i0load @[lib.scala 384:16] _T_758.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 384:16] _T_758.valid <= r_d_in.valid @[lib.scala 384:16] - wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 656:7] - wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 656:7] - wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 656:7] - wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 656:7] - wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 656:7] - wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 656:7] - wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 656:7] - wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 656:7] - wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 656:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 658:27] - node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 659:47] - node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 659:45] - i0_wen_r <= _T_760 @[dec_decode_ctl.scala 659:25] - node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 660:49] - node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 660:47] - node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 660:70] - node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 660:68] - io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 660:32] - io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 661:26] - node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 663:57] + wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 662:7] + wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 662:7] + wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 662:7] + wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 662:7] + wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 662:7] + wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 662:7] + wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 662:7] + wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 662:7] + wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 662:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 664:27] + node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 665:47] + node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 665:45] + i0_wen_r <= _T_760 @[dec_decode_ctl.scala 665:25] + node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 666:49] + node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 666:47] + node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 666:70] + node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 666:68] + io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 666:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 667:26] + node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57] inst rvclkhdr_10 of rvclkhdr_671 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -68942,18 +68942,18 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_result_r_raw <= i0_result_x @[lib.scala 374:16] - node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 669:47] - node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 669:66] - node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 669:32] - i0_result_x <= _T_768 @[dec_decode_ctl.scala 669:26] - i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 670:26] - node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 674:42] - node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 674:61] - node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 674:27] - i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 674:21] - node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 675:73] - node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 675:71] - node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 675:85] + node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47] + node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 675:66] + node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32] + i0_result_x <= _T_768 @[dec_decode_ctl.scala 675:26] + i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 676:26] + node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 680:42] + node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 680:61] + node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 680:27] + i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 680:21] + node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73] + node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 681:71] + node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 681:85] wire _T_775 : UInt<1>[10] @[lib.scala 12:48] _T_775[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_775[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68976,11 +68976,11 @@ circuit quasar_wrapper : node _T_784 = cat(_T_783, _T_775[9]) @[Cat.scala 29:58] node _T_785 = cat(_T_784, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_786 = cat(_T_785, i0_ap_pc2) @[Cat.scala 29:58] - node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 675:38] - io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 675:32] + node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 681:38] + io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 681:32] wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") - node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 677:59] + node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59] wire _T_789 : UInt<1>[10] @[lib.scala 12:48] _T_789[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_789[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -69003,11 +69003,11 @@ circuit quasar_wrapper : node _T_798 = cat(_T_797, _T_789[9]) @[Cat.scala 29:58] node _T_799 = cat(_T_798, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_800 = cat(_T_799, i0_ap_pc2) @[Cat.scala 29:58] - node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 677:25] - last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 677:19] + node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 683:25] + last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 683:19] wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") - node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 679:58] + node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58] inst rvclkhdr_11 of rvclkhdr_672 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -69016,54 +69016,54 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_803 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_803 <= last_br_immed_d @[lib.scala 374:16] - last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 679:19] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 683:45] - node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 683:76] - node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 683:58] - node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 685:48] - node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 685:77] - node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 685:60] - node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 686:21] - node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 686:33] - node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 685:94] - node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 687:21] - node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 687:33] - node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 687:60] - node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 686:62] - node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 691:51] - node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 692:26] - node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 692:24] - node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 692:56] - node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 692:39] - node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 692:77] - node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 691:65] - node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 694:61] - io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 694:37] - node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 695:55] - node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 697:62] - node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 697:60] - node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 697:81] - node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 697:79] - node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 697:39] - reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 699:54] - _T_826 <= div_active_in @[dec_decode_ctl.scala 699:54] - io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 699:21] - node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 702:60] - node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 702:99] - node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 702:80] - node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 703:36] - node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 703:75] - node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 703:56] - node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 702:113] - i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 702:26] - node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 705:59] + last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 685:19] + node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45] + node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76] + node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 689:58] + node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 691:48] + node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 691:77] + node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 691:60] + node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 692:21] + node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 692:33] + node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 691:94] + node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 693:21] + node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 693:33] + node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 693:60] + node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 692:62] + node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 697:51] + node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 698:26] + node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 698:24] + node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 698:56] + node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 698:39] + node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 698:77] + node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 697:65] + node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 700:61] + io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 700:37] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 701:55] + node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 703:62] + node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 703:60] + node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 703:81] + node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 703:79] + node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 703:39] + reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 705:54] + _T_826 <= div_active_in @[dec_decode_ctl.scala 705:54] + io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 705:21] + node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 708:60] + node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 708:99] + node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 708:80] + node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 709:36] + node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 709:75] + node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 709:56] + node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 708:113] + i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 708:26] + node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 711:59] reg _T_835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_834 : @[Reg.scala 28:19] _T_835 <= i0r.rd @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 705:19] - node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 712:34] - node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 712:57] + io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 711:19] + node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34] + node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57] inst rvclkhdr_12 of rvclkhdr_673 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -69072,7 +69072,7 @@ circuit quasar_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] div_inst <= _T_836 @[lib.scala 374:16] - node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 713:49] + node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49] inst rvclkhdr_13 of rvclkhdr_674 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -69081,7 +69081,7 @@ circuit quasar_wrapper : rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_x <= i0_inst_d @[lib.scala 374:16] - node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 714:49] + node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49] inst rvclkhdr_14 of rvclkhdr_675 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -69090,7 +69090,7 @@ circuit quasar_wrapper : rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_r <= i0_inst_x @[lib.scala 374:16] - node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 716:50] + node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50] inst rvclkhdr_15 of rvclkhdr_676 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -69099,7 +69099,7 @@ circuit quasar_wrapper : rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_wb <= i0_inst_r @[lib.scala 374:16] - node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 717:53] + node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53] inst rvclkhdr_16 of rvclkhdr_677 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -69108,8 +69108,8 @@ circuit quasar_wrapper : rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_842 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_842 <= i0_inst_wb @[lib.scala 374:16] - io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 717:22] - node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 718:53] + io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 723:22] + node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53] inst rvclkhdr_17 of rvclkhdr_678 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -69118,7 +69118,7 @@ circuit quasar_wrapper : rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 374:16] - node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 720:49] + node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49] inst rvclkhdr_18 of rvclkhdr_679 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -69127,8 +69127,8 @@ circuit quasar_wrapper : rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_845 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_845 <= i0_pc_wb @[lib.scala 374:16] - io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 720:20] - node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 721:64] + io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 726:20] + node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64] inst rvclkhdr_19 of rvclkhdr_680 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -69137,7 +69137,7 @@ circuit quasar_wrapper : rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 374:16] - io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 723:27] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 729:27] node _T_847 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_848 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_849 = bits(_T_847, 12, 1) @[lib.scala 68:24] @@ -69173,124 +69173,124 @@ circuit quasar_wrapper : node _T_878 = bits(_T_851, 11, 0) @[lib.scala 74:94] node _T_879 = cat(_T_877, _T_878) @[Cat.scala 29:58] node temp_pred_correct_npc_x = cat(_T_879, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 728:62] - io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 728:36] - node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 732:59] - node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 732:91] - node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 732:74] - node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 733:59] - node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 733:91] - node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 733:74] - node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 735:59] - node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 735:91] - node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 735:74] - node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 736:59] - node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 736:91] - node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 736:74] - node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 738:44] - node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 738:81] - wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 738:109] - _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] - _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] - _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] - node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 738:61] - node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 738:24] - i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 738:18] - i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 738:18] - i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 738:18] - node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 739:44] - node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 739:83] - node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 739:63] - node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 739:24] - i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 739:18] - node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 740:44] - node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 740:81] - wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 740:109] - _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] - _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] - _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] - node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 740:61] - node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 740:24] - i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 740:18] - i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 740:18] - i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 740:18] - node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 741:44] - node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 741:83] - node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 741:63] - node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 741:24] - i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 741:18] - i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 751:21] - node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 752:43] - node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 752:74] - node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 752:58] - node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 752:78] - load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 752:27] - node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 753:59] - node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 753:43] - node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 753:63] - store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 753:25] - store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 754:25] - node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 758:73] - node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 758:130] - node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 758:100] - node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 760:73] - node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 760:130] - node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 760:100] - node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:41] - node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:66] - node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 763:45] - node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:104] - node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:108] - node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 763:149] - node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:175] - node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:196] - node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 763:153] + node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62] + io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 734:36] + node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 738:59] + node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 738:91] + node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 738:74] + node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 739:59] + node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 739:91] + node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 739:74] + node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 741:59] + node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 741:91] + node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 741:74] + node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 742:59] + node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 742:91] + node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 742:74] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 744:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 744:81] + wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 744:109] + _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] + _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] + _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] + node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 744:61] + node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 744:24] + i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 744:18] + i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 744:18] + i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 744:18] + node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 745:44] + node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 745:83] + node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 745:63] + node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 745:24] + i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 745:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 746:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 746:81] + wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 746:109] + _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] + _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] + _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] + node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 746:61] + node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 746:24] + i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 746:18] + i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 746:18] + i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 746:18] + node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 747:44] + node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 747:83] + node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 747:63] + node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 747:24] + i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 747:18] + i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 757:21] + node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 758:43] + node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 758:74] + node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 758:58] + node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 758:78] + load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 758:27] + node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 759:59] + node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 759:43] + node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 759:63] + store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 759:25] + store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 760:25] + node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 764:73] + node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 764:130] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 764:100] + node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 766:73] + node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 766:130] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 766:100] + node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:41] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:66] + node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 769:45] + node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:104] + node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:108] + node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 769:149] + node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:175] + node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:196] + node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 769:153] node _T_927 = cat(_T_920, _T_922) @[Cat.scala 29:58] node _T_928 = cat(_T_927, _T_926) @[Cat.scala 29:58] - i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 763:18] - node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:41] - node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:67] - node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 765:45] - node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:105] - node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:109] - node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 765:149] - node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:175] - node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:196] - node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 765:153] + i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 769:18] + node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:41] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:67] + node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 771:45] + node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:105] + node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:109] + node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 771:149] + node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:175] + node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:196] + node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 771:153] node _T_938 = cat(_T_931, _T_933) @[Cat.scala 29:58] node _T_939 = cat(_T_938, _T_937) @[Cat.scala 29:58] - i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 765:18] - node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:65] - node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 767:82] - node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 767:100] - node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 767:86] - node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:120] - node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 767:107] - node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 767:124] - node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 767:104] + i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 771:18] + node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:65] + node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 773:82] + node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:100] + node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 773:86] + node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:120] + node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 773:107] + node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 773:124] + node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 773:104] node _T_948 = cat(_T_940, _T_947) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 767:45] - node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:65] - node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 768:82] - node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 768:100] - node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 768:86] - node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:120] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 768:107] - node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 768:124] - node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 768:104] + io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 773:45] + node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:65] + node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 774:82] + node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 774:100] + node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 774:86] + node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:120] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 774:107] + node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:124] + node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 774:104] node _T_957 = cat(_T_949, _T_956) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 768:45] - node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 772:17] - node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 772:21] - node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:17] - node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 773:21] - node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 774:19] - node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 774:6] - node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 774:38] - node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 774:25] - node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 774:23] - node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:42] - node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 774:78] + io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 774:45] + node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 778:17] + node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 778:21] + node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 779:17] + node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 779:21] + node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 780:19] + node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 780:6] + node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 780:38] + node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 780:25] + node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 780:23] + node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 780:42] + node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 780:78] node _T_969 = mux(_T_959, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_970 = mux(_T_961, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_971 = mux(_T_968, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69298,18 +69298,18 @@ circuit quasar_wrapper : node _T_973 = or(_T_972, _T_971) @[Mux.scala 27:72] wire _T_974 : UInt<32> @[Mux.scala 27:72] _T_974 <= _T_973 @[Mux.scala 27:72] - io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 771:42] - node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 777:17] - node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 777:21] - node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 778:17] - node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 778:21] - node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 779:19] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 779:6] - node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 779:38] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 779:25] - node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 779:23] - node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 779:42] - node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 779:78] + io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 777:42] + node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 783:17] + node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 783:21] + node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 784:17] + node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 784:21] + node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 785:19] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 785:6] + node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 785:38] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 785:25] + node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 785:23] + node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 785:42] + node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 785:78] node _T_986 = mux(_T_976, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_987 = mux(_T_978, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_988 = mux(_T_985, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69317,33 +69317,33 @@ circuit quasar_wrapper : node _T_990 = or(_T_989, _T_988) @[Mux.scala 27:72] wire _T_991 : UInt<32> @[Mux.scala 27:72] _T_991 <= _T_990 @[Mux.scala 27:72] - io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 776:42] - node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 781:68] - node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 781:50] - node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 781:89] - node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 781:87] - node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 781:123] - node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 781:121] - node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 781:140] - io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 781:26] - node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 783:6] - node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 783:38] - node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 783:50] - node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 783:64] - node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 783:81] - node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 784:6] - node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 784:38] - node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 784:50] - node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 784:65] - node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 784:85] - node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 784:95] + io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 782:42] + node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68] + node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 787:50] + node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89] + node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:87] + node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123] + node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 787:121] + node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140] + io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 787:26] + node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 789:38] + node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 789:50] + node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 789:64] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 789:81] + node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 790:6] + node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 790:38] + node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 790:50] + node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 790:65] + node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 790:85] + node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 790:95] node _T_1010 = cat(_T_1008, _T_1009) @[Cat.scala 29:58] node _T_1011 = mux(_T_1002, _T_1003, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1012 = mux(_T_1007, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1013 = or(_T_1011, _T_1012) @[Mux.scala 27:72] wire _T_1014 : UInt<12> @[Mux.scala 27:72] _T_1014 <= _T_1013 @[Mux.scala 27:72] - io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 782:23] + io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 788:23] extmodule gated_latch_681 : output Q : Clock @@ -74040,12 +74040,12 @@ circuit quasar_wrapper : _T_748 <= _T_759 @[dec_tlu_ctl.scala 2131:13] node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] dicad1 <= _T_760 @[dec_tlu_ctl.scala 2132:9] - node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:69] - node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:83] - node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:97] + node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:74] + node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:88] + node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:102] node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2154:56] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2154:61] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] @@ -77867,9 +77867,9 @@ circuit quasar_wrapper : module dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} - wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 156:67] + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 155:67] wire pause_expired_wb : UInt<1> pause_expired_wb <= UInt<1>("h00") wire take_nmi_r_d1 : UInt<1> @@ -78096,30 +78096,30 @@ circuit quasar_wrapper : mtvec <= UInt<1>("h00") wire mip : UInt<6> mip <= UInt<1>("h00") - wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 271:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 270:41] wire dec_tlu_mpc_halted_only_ns : UInt<1> dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") - node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39] - node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57] - dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36] - inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:30] + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 273:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 273:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 273:36] + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 274:30] int_timers.clock <= clock int_timers.reset <= reset - int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:57] - int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:57] - int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49] - int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49] - int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49] - int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49] - int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:57] - int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:57] - int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:57] - int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:57] - int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:57] - int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:57] - int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:49] - int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49] - int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:47] + int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 275:57] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 276:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 277:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 278:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 279:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 280:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 281:57] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 282:57] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 283:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 284:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 285:57] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 286:57] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 287:49] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 288:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 289:47] node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] @@ -78130,103 +78130,101 @@ circuit quasar_wrapper : _T_8 <= _T_7 @[lib.scala 37:81] reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] syncro_ff <= _T_8 @[lib.scala 37:58] - node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:67] - node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:59] - node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:59] - node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:59] - node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:59] - node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:51] - node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:51] - node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:58] - node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:74] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 301:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 302:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 303:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 304:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 305:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 306:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 307:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 310:58] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 310:74] inst rvclkhdr of rvclkhdr_716 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_10 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:67] - node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:88] - node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:104] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 311:67] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:88] + node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 311:104] inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:30] - node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:50] - node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:69] - node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:89] - node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:112] - node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:128] - node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:146] - node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:165] - node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:177] - node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:192] - node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:207] - node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:225] - node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:49] - node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:65] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 314:30] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 315:50] + node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 315:69] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 315:89] + node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 315:112] + node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 315:128] + node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 315:146] + node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 315:165] + node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 315:177] + node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 315:192] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 315:207] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 315:225] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 317:49] + node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 317:65] inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:53] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:71] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 318:53] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 318:71] inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:80] - iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:80] - reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] - _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:89] - ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:57] - reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:89] - _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:89] - iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:57] - reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:97] - _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:97] - e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:65] - reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:81] - _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:81] - debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:49] - reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:80] - lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:80] - reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:72] - lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:72] - reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:80] - tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:80] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:73] - _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:73] - io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41] - reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:72] - internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:72] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89] - _T_33 <= force_halt @[dec_tlu_ctl.scala 331:89] - io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:41] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:88] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:88] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:88] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:64] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:49] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:72] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:72] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:72] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:72] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:72] - io.tlu_bp.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 343:42] - io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 344:43] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 320:80] + iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 320:80] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:89] + _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 321:89] + ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 321:57] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] + _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 322:89] + iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 322:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:97] + _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 323:97] + e5_valid <= _T_30 @[dec_tlu_ctl.scala 323:65] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:81] + _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 324:81] + debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 324:49] + reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:80] + lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 325:80] + reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:72] + lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 326:72] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:80] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 327:80] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:73] + _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 328:73] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 328:41] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:72] + internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 329:72] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:89] + _T_33 <= force_halt @[dec_tlu_ctl.scala 330:89] + io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 330:57] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 334:41] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 335:88] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 336:88] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 336:88] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 337:64] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 337:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 339:72] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 340:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 341:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 342:72] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 342:72] node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 346:32] node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 346:96] node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 346:49] @@ -78428,7 +78426,7 @@ circuit quasar_wrapper : node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 438:79] node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 440:53] node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 443:57] - node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 443:112] + node _T_181 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 443:112] node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 443:110] node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 443:83] node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 445:64] @@ -78601,11 +78599,11 @@ circuit quasar_wrapper : node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 517:90] node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 517:119] node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 517:146] - node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 519:58] + node _T_297 = or(io.tlu_bp.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 519:65] node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 519:23] - node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 519:84] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 519:91] node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 522:53] node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 522:73] node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 522:60] @@ -78751,7 +78749,7 @@ circuit quasar_wrapper : mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 605:57] reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 606:72] lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 606:72] - node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 608:57] + node _T_402 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 608:57] node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 608:55] lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 609:21] node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 610:40] @@ -79291,7 +79289,8 @@ circuit quasar_wrapper : node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 787:30] reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 798:64] tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 798:64] - io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 800:41] + io.tlu_bp.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 800:49] + io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 801:41] io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 802:49] io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 803:49] node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 806:45] @@ -81413,7 +81412,7 @@ circuit quasar_wrapper : decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 162:48] decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 163:48] decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 164:48] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 165:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.tlu_bp.dec_tlu_flush_lower_wb @[dec.scala 165:48] decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 166:48] decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 167:48] decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 168:48] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index e858aa73..73df7799 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -46049,9 +46049,6 @@ module dec_decode_ctl( input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, input [31:0] io_dctl_busbuff_lsu_nonblock_load_data, input io_dctl_dma_dma_dccm_stall_any, - output io_dec_aln_dec_i0_decode_d, - input [15:0] io_dec_aln_ifu_i0_cinst, - input [1:0] io_dbg_dctl_dbg_cmd_wrdata, input io_dec_tlu_flush_extint, input io_dec_tlu_force_halt, output [31:0] io_dec_i0_inst_wb1, @@ -46148,7 +46145,10 @@ module dec_decode_ctl( output io_dec_pause_state, output io_dec_pause_state_cg, output io_dec_div_active, - input io_scan_mode + input io_scan_mode, + output io_dec_aln_dec_i0_decode_d, + input [15:0] io_dec_aln_ifu_i0_cinst, + input [1:0] io_dbg_dctl_dbg_cmd_wrdata ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -46247,57 +46247,57 @@ module dec_decode_ctl( wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 356:22] - wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 356:22] + wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 362:22] + wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 362:22] wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] wire rvclkhdr_1_io_en; // @[lib.scala 368:23] @@ -46374,249 +46374,249 @@ module dec_decode_ctl( wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] wire rvclkhdr_19_io_en; // @[lib.scala 368:23] wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] - reg tlu_wr_pause_r1; // @[dec_decode_ctl.scala 463:55] - wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 178:54] - reg tlu_wr_pause_r2; // @[dec_decode_ctl.scala 464:55] - wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 179:54] - wire _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 178:89] - wire _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 180:54] - wire _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 179:89] - reg leak1_i1_stall; // @[dec_decode_ctl.scala 364:56] - wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 363:73] - wire _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 363:71] - wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 363:53] - wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 181:54] - wire _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 180:89] - wire _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 366:53] - reg leak1_i0_stall; // @[dec_decode_ctl.scala 367:56] - wire _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 366:89] - wire leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 366:71] - wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 182:54] - wire _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 181:89] - reg pause_stall; // @[dec_decode_ctl.scala 461:50] - wire _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 460:44] - wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 459:49] - wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 459:47] + reg tlu_wr_pause_r1; // @[dec_decode_ctl.scala 469:55] + wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 181:51] + reg tlu_wr_pause_r2; // @[dec_decode_ctl.scala 470:55] + wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 182:32] + wire _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 181:73] + wire _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 183:32] + wire _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 182:56] + reg leak1_i1_stall; // @[dec_decode_ctl.scala 370:56] + wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 369:73] + wire _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 369:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 369:53] + wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 184:32] + wire _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 183:67] + wire _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 372:53] + reg leak1_i0_stall; // @[dec_decode_ctl.scala 373:56] + wire _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 372:89] + wire leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 372:71] + wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 185:32] + wire _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 184:56] + reg pause_stall; // @[dec_decode_ctl.scala 467:50] + wire _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 466:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 465:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 465:47] reg [31:0] write_csr_data; // @[lib.scala 374:16] wire [31:0] _T_412 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58] - wire _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 459:109] - wire _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 459:91] - wire clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 459:76] - wire _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 460:61] - wire pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 460:59] - wire _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 183:54] - wire _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 182:89] - wire _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 192:80] - wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 192:78] - wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 465:109] + wire _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 465:91] + wire clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 465:76] + wire _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 466:61] + wire pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 466:59] + wire _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 186:32] + wire _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 185:56] + wire _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 196:62] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 196:60] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] - wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 372:79] - wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 372:112] - wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 372:33] - wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 373:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 586:16] - wire _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 373:76] - wire _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 373:98] - wire _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 373:89] - wire i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 373:65] - wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 375:38] - wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 203:92] - wire _T_309 = ~_T_304; // @[dec_decode_ctl.scala 374:67] - wire i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 374:65] - wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 377:38] - wire _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 203:107] - wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 381:37] - wire _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 381:65] - wire _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 381:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 584:16] - wire _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 381:89] - wire _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 381:111] - wire _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 381:101] - wire i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 381:79] - wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 382:32] - wire _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 203:120] - wire _T_23 = ~_T_22; // @[dec_decode_ctl.scala 203:73] - wire i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 203:71] - wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 208:87] - wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 206:72] - wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 379:41] + wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 378:79] + wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 378:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 378:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 379:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 592:16] + wire _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 379:76] + wire _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 379:98] + wire _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 379:89] + wire i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 379:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 381:38] + wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 207:75] + wire _T_309 = ~_T_304; // @[dec_decode_ctl.scala 380:67] + wire i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 380:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 383:38] + wire _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 207:90] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 387:37] + wire _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 387:65] + wire _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 387:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 590:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 387:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 387:111] + wire _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 387:101] + wire i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 387:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 388:32] + wire _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 207:103] + wire _T_23 = ~_T_22; // @[dec_decode_ctl.scala 207:56] + wire i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 207:54] + wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 212:62] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 210:47] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 385:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] - wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 379:26] - wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 206:131] - wire _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 206:101] - wire _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 206:151] - wire i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 206:149] - wire _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 208:104] - wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 207:72] - wire i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 207:97] - wire i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 208:126] - wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 213:72] - wire i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 213:109] - wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 222:43] - wire _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 225:25] - wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 225:50] - wire _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 490:36] - wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 482:48] - wire _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 490:60] - wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 225:50] - wire _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 421:42] - wire i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 421:40] - wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 225:50] - wire _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 426:41] - wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 426:39] - wire _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 490:112] - wire _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 490:99] - wire i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 490:76] - wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 225:50] - wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 492:34] - wire _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 494:40] - wire _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 494:51] - wire i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 494:37] - wire _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 534:64] - wire _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 534:62] - wire _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 534:47] - reg postsync_stall; // @[dec_decode_ctl.scala 532:53] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 385:26] + wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 210:106] + wire _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 210:76] + wire _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 210:126] + wire i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 210:124] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 212:79] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 211:47] + wire i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 211:72] + wire i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 212:101] + wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 217:47] + wire i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 217:84] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 226:36] + wire _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 230:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 230:50] + wire _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 496:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 488:48] + wire _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 496:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 230:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 427:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 427:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 230:50] + wire _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 432:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 432:39] + wire _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 496:112] + wire _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 496:99] + wire i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 496:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 230:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 498:34] + wire _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 500:40] + wire _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 500:51] + wire i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 500:37] + wire _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 540:64] + wire _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 540:62] + wire _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 540:47] + reg postsync_stall; // @[dec_decode_ctl.scala 538:53] reg x_d_valid; // @[lib.scala 384:16] - wire _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 534:96] - wire ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 534:77] - wire _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 184:54] - wire _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 183:89] - reg flush_final_r; // @[dec_decode_ctl.scala 580:52] - wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 185:54] - wire _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 184:89] - wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 498:55] - reg illegal_lockout; // @[dec_decode_ctl.scala 502:54] - wire _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 501:40] - wire _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 501:61] - wire illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 501:59] - wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 186:54] - wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 608:54] - wire _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 209:72] - wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 210:94] - wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 225:50] - wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] - wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 225:50] - wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 376:38] - wire _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 239:54] - wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 378:38] - wire _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 239:65] - wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 383:32] - wire i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 239:74] - wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 240:69] - wire _T_48 = ~_T_47; // @[dec_decode_ctl.scala 240:40] - wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 242:40] - wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 275:76] - reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 311:47] - wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 286:67] - wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 286:67] - wire _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 286:45] - reg cam_raw_0_valid; // @[dec_decode_ctl.scala 311:47] - wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 286:88] - wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 290:39] - wire _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 267:78] - reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 311:47] - wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 286:67] - wire _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 286:45] - reg cam_raw_1_valid; // @[dec_decode_ctl.scala 311:47] - wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 286:88] - wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 290:39] - wire _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 267:78] - wire _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 267:126] - wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 267:158] - reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 311:47] - wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 286:67] - wire _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 286:45] - reg cam_raw_2_valid; // @[dec_decode_ctl.scala 311:47] - wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 286:88] - wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 290:39] - wire _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 267:78] - wire _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 267:126] - wire _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 267:126] - wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 267:158] - reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 311:47] - wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 286:67] - wire _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 286:45] - reg cam_raw_3_valid; // @[dec_decode_ctl.scala 311:47] - wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 286:88] - wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 290:39] - wire _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 267:78] - wire _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 267:126] - wire _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 267:126] - wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 267:158] + wire _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 540:96] + wire ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 540:77] + wire _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 187:32] + wire _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 186:56] + reg flush_final_r; // @[dec_decode_ctl.scala 586:52] + wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 188:32] + wire _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 187:56] + wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 504:55] + reg illegal_lockout; // @[dec_decode_ctl.scala 508:54] + wire _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 507:40] + wire _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 507:61] + wire illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 507:59] + wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 189:32] + wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 614:54] + wire _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 213:83] + wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 214:105] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 230:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 230:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 382:38] + wire _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 244:40] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 384:38] + wire _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 244:51] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 389:32] + wire i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 244:60] + wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 246:55] + wire _T_48 = ~_T_47; // @[dec_decode_ctl.scala 246:26] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 248:20] + wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 281:76] + reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 317:47] + wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 292:67] + wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 292:67] + wire _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 292:45] + reg cam_raw_0_valid; // @[dec_decode_ctl.scala 317:47] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 292:88] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 296:39] + wire _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 273:78] + reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 317:47] + wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 292:67] + wire _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 292:45] + reg cam_raw_1_valid; // @[dec_decode_ctl.scala 317:47] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 292:88] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 296:39] + wire _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 273:78] + wire _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 273:126] + wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 273:158] + reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 317:47] + wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 292:67] + wire _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 292:45] + reg cam_raw_2_valid; // @[dec_decode_ctl.scala 317:47] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 292:88] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 296:39] + wire _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 273:78] + wire _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 273:126] + wire _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 273:126] + wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 273:158] + reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 317:47] + wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 292:67] + wire _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 292:45] + reg cam_raw_3_valid; // @[dec_decode_ctl.scala 317:47] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 292:88] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 296:39] + wire _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 273:78] + wire _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 273:126] + wire _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 273:126] + wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 273:158] wire _T_81 = _T_51 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72] @@ -46629,150 +46629,150 @@ module dec_decode_ctl( wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] reg x_d_bits_i0load; // @[lib.scala 384:16] reg [4:0] x_d_bits_i0rd; // @[lib.scala 384:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 278:31] - reg [2:0] _T_706; // @[dec_decode_ctl.scala 616:80] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31] + reg [2:0] _T_706; // @[dec_decode_ctl.scala 622:80] wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_706}; // @[Cat.scala 29:58] - wire _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 619:49] - wire i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 619:53] + wire _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49] + wire i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 625:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg r_d_bits_i0load; // @[lib.scala 384:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 283:56] - wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 285:66] - wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 285:66] - wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 285:45] - wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 285:87] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56] + wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 291:66] + wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 291:66] + wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87] reg r_d_bits_i0v; // @[lib.scala 384:16] - wire _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 651:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 651:49] - wire _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 659:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 659:45] + wire _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 657:49] + wire _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 665:45] reg [4:0] r_d_bits_i0rd; // @[lib.scala 384:16] - reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 311:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 298:85] - wire _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 298:64] - reg cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 311:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:105] - wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 298:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 298:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:131] - wire _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 293:28] - wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 293:28] - wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 303:44] - wire _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 303:113] - wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 312:71] - wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 285:66] - wire _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 285:45] - wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 285:87] - reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 311:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 298:85] - wire _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 298:64] - reg cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 311:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:105] - wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 298:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 298:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:131] - wire _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 293:28] - wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 293:28] - wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 303:44] - wire _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 303:113] - wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 312:71] - wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 285:66] - wire _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 285:45] - wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 285:87] - reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 311:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 298:85] - wire _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 298:64] - reg cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 311:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:105] - wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 298:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 298:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:131] - wire _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 293:28] - wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 293:28] - wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 303:44] - wire _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 303:113] - wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 312:71] - wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 285:66] - wire _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 285:45] - wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 285:87] - reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 311:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 298:85] - wire _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 298:64] - reg cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 311:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:105] - wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 298:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 298:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:131] - wire _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 293:28] - wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 293:28] - wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 303:44] - wire _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 303:113] - wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 312:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 317:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 317:81] - wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 318:108] - wire _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 318:108] - wire _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 318:108] - wire _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 318:77] - wire _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 318:122] - wire _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 319:54] - wire _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:66] - wire _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 319:110] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 585:16] - wire _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 319:161] - wire _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:173] - wire _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 319:217] - wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 319:142] + reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47] + wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85] + wire _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 304:64] + reg cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 317:47] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:105] + wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 304:44] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 304:131] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:131] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 299:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 299:28] + wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 309:44] + wire _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 309:113] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 318:71] + wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 291:66] + wire _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 291:45] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 291:87] + reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 317:47] + wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 304:85] + wire _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 304:64] + reg cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 317:47] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:105] + wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 304:44] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 304:131] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:131] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 299:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 299:28] + wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 309:44] + wire _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 309:113] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 318:71] + wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 291:66] + wire _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 291:45] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 291:87] + reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 317:47] + wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 304:85] + wire _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 304:64] + reg cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 317:47] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:105] + wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 304:44] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 304:131] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:131] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 299:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 299:28] + wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 309:44] + wire _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 309:113] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 318:71] + wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 291:66] + wire _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 291:45] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 291:87] + reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 317:47] + wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 304:85] + wire _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 304:64] + reg cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 317:47] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:105] + wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 304:44] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 304:131] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:131] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 299:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 299:28] + wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 309:44] + wire _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 309:113] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 318:71] + wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 323:49] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 323:81] + wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 324:108] + wire _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 324:108] + wire _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 324:108] + wire _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 324:77] + wire _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 324:122] + wire _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 325:54] + wire _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:66] + wire _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 325:110] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 591:16] + wire _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 325:161] + wire _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:173] + wire _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 325:217] + wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 325:142] wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 323:88] - wire _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:137] - wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] - wire _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 323:152] - wire _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:214] - wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] - wire _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 323:229] + wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 329:88] + wire _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:137] + wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] + wire _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 329:152] + wire _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:214] + wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] + wire _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 329:229] wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 323:88] - wire _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:137] - wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] - wire _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 323:152] - wire _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:214] - wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] - wire _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 323:229] + wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 329:88] + wire _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:137] + wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] + wire _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 329:152] + wire _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:214] + wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] + wire _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 329:229] wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 323:88] - wire _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:137] - wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] - wire _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 323:152] - wire _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:214] - wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] - wire _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 323:229] + wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 329:88] + wire _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:137] + wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] + wire _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 329:152] + wire _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:214] + wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] + wire _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 329:229] wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 323:88] - wire _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:137] - wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] - wire _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 323:152] - wire _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:214] - wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] - wire _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 323:229] - wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 324:69] - wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 324:69] - wire _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 324:102] - wire _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 324:102] - wire ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 324:102] - wire _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 324:134] - wire _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 324:134] - wire ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 324:134] - wire _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 326:38] - wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 326:51] - wire _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 335:34] + wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 329:88] + wire _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:137] + wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] + wire _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 329:152] + wire _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:214] + wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] + wire _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 329:229] + wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 330:69] + wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 330:69] + wire _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 330:102] + wire _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 330:102] + wire ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 330:102] + wire _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 330:134] + wire _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 330:134] + wire ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 330:134] + wire _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 332:38] + wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 332:51] + wire _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 341:34] wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 419:36] - wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 347:16] - wire _T_258 = ~csr_read; // @[dec_decode_ctl.scala 348:6] - wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 348:16] - wire _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 349:18] - wire _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 349:16] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 425:36] + wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 353:16] + wire _T_258 = ~csr_read; // @[dec_decode_ctl.scala 354:6] + wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 354:16] + wire _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 355:18] + wire _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 355:16] wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16] wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16] @@ -46787,143 +46787,143 @@ module dec_decode_ctl( wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16] wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16] wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16] - reg lsu_idle; // @[dec_decode_ctl.scala 360:45] - wire _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 384:35] - wire _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 384:32] - wire _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 384:52] - wire _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 384:50] - wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 384:67] - reg _T_339; // @[dec_decode_ctl.scala 396:69] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 538:40] - wire _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 752:43] + reg lsu_idle; // @[dec_decode_ctl.scala 366:45] + wire _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 390:35] + wire _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 390:32] + wire _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 390:52] + wire _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 390:50] + wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67] + reg _T_339; // @[dec_decode_ctl.scala 402:69] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40] + wire _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43] reg x_d_bits_i0v; // @[lib.scala 384:16] - wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 732:59] - wire _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 732:91] - wire i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 732:74] - wire _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 733:59] - wire _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 733:91] - wire i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 733:74] - wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 739:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 739:24] - wire _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 752:58] + wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59] + wire _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91] + wire i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 738:74] + wire _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59] + wire _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91] + wire i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 739:74] + wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 745:24] + wire _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58] reg i0_x_c_load; // @[Reg.scala 27:20] reg i0_r_c_load; // @[Reg.scala 27:20] - wire _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 738:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 738:24] - wire load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 752:78] - wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 735:59] - wire _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 735:91] - wire i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 735:74] - wire _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 736:59] - wire _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 736:91] - wire i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 736:74] - wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 741:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 741:24] - wire _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 753:43] - wire _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 740:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 740:24] - wire store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 753:63] - wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 427:42] + wire _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 744:24] + wire load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78] + wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59] + wire _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91] + wire i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 741:74] + wire _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59] + wire _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91] + wire i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 742:74] + wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 747:24] + wire _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43] + wire _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 746:24] + wire store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42] reg r_d_bits_csrwen; // @[lib.scala 384:16] reg r_d_valid; // @[lib.scala 384:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 435:39] + wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 441:39] reg [11:0] r_d_bits_csrwaddr; // @[lib.scala 384:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 438:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 438:85] - wire _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 438:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 438:100] - wire _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 438:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 438:132] - reg csr_read_x; // @[dec_decode_ctl.scala 440:52] - reg csr_clr_x; // @[dec_decode_ctl.scala 441:51] - reg csr_set_x; // @[dec_decode_ctl.scala 442:51] - reg csr_write_x; // @[dec_decode_ctl.scala 443:53] - reg csr_imm_x; // @[dec_decode_ctl.scala 444:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 621:50] + wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 444:50] + wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 444:85] + wire _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 444:64] + wire _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 444:100] + wire _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 444:118] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 444:132] + reg csr_read_x; // @[dec_decode_ctl.scala 446:52] + reg csr_clr_x; // @[dec_decode_ctl.scala 447:51] + reg csr_set_x; // @[dec_decode_ctl.scala 448:51] + reg csr_write_x; // @[dec_decode_ctl.scala 449:53] + reg csr_imm_x; // @[dec_decode_ctl.scala 450:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 627:50] reg [4:0] csrimm_x; // @[lib.scala 374:16] reg [31:0] csr_rddata_x; // @[lib.scala 374:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] - wire _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 452:5] + wire _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 458:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_398 = _T_396 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] - wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 455:38] - wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 455:35] - wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 456:35] + wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 461:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 461:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 462:35] wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] - wire _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 466:44] - wire _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 466:64] - wire _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 466:61] - wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 469:59] - wire _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 471:34] - wire _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 471:46] - wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 471:61] - wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 471:75] + wire _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 472:44] + wire _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 472:64] + wire _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 472:61] + wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 475:59] + wire _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 477:34] + wire _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 477:46] + wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61] + wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75] reg r_d_bits_csrwonly; // @[lib.scala 384:16] - wire _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 674:42] + wire _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42] reg [31:0] i0_result_r_raw; // @[lib.scala 374:16] - wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 674:27] + wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27] reg x_d_bits_csrwonly; // @[lib.scala 384:16] - wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 480:43] + wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43] reg wbd_bits_csrwonly; // @[lib.scala 384:16] - wire prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 480:63] - wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 483:48] - wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 484:40] - wire _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 487:34] - wire _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 487:57] - wire _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 487:73] - wire i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 487:91] + wire prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 486:63] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 489:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 490:40] + wire _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 493:34] + wire _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 493:57] + wire _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 493:73] + wire i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 493:91] wire [31:0] _T_465 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 499:44] + wire _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 505:44] reg [31:0] _T_468; // @[lib.scala 374:16] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 503:42] - wire _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 505:40] - wire _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 505:59] - wire _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 505:92] - wire _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 505:106] - wire _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 506:20] - wire _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 506:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 528:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 529:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 531:37] - wire _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 506:62] - wire _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 507:19] - wire _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 507:36] - wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 507:34] - wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 506:79] - wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 507:47] - wire _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 702:60] - wire _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 702:99] - wire _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 702:80] - wire _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 703:36] - wire _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 703:75] - wire _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 703:56] - wire i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 702:113] - wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 508:21] - wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 508:45] - wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 510:65] - wire i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 510:39] - wire _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 511:63] - wire i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 511:38] - wire _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 512:38] - wire i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 512:57] - wire _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 516:54] - wire _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 516:52] - wire _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 516:69] - wire _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 517:46] - wire _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 517:44] - wire _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 517:61] - wire i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 517:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 518:46] - wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 522:51] - wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 550:44] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 509:42] + wire _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 511:40] + wire _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 511:59] + wire _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 511:92] + wire _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 511:106] + wire _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 512:20] + wire _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 512:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 534:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 535:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 537:37] + wire _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 512:62] + wire _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 513:19] + wire _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 513:36] + wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34] + wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79] + wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47] + wire _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60] + wire _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99] + wire _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 708:80] + wire _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36] + wire _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75] + wire _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 709:56] + wire i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 708:113] + wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21] + wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45] + wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65] + wire i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 516:39] + wire _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 517:63] + wire i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 517:38] + wire _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 518:38] + wire i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 518:57] + wire _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 522:54] + wire _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 522:52] + wire _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 522:69] + wire _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 523:46] + wire _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 523:44] + wire _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 523:61] + wire i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 523:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 524:46] + wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51] + wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44] wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 618:49] - wire i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 618:53] + wire _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49] + wire i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 624:53] reg x_t_legal; // @[lib.scala 384:16] reg x_t_icaf; // @[lib.scala 384:16] reg x_t_icaf_f1; // @[lib.scala 384:16] @@ -46933,7 +46933,7 @@ module dec_decode_ctl( reg [3:0] x_t_pmu_i0_itype; // @[lib.scala 384:16] reg x_t_pmu_i0_br_unpred; // @[lib.scala 384:16] wire [3:0] _T_533 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 563:39] + wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 569:39] reg r_t_legal; // @[lib.scala 384:16] reg r_t_icaf; // @[lib.scala 384:16] reg r_t_icaf_f1; // @[lib.scala 384:16] @@ -46942,22 +46942,22 @@ module dec_decode_ctl( reg [3:0] r_t_i0trigger; // @[lib.scala 384:16] reg [3:0] r_t_pmu_i0_itype; // @[lib.scala 384:16] reg r_t_pmu_i0_br_unpred; // @[lib.scala 384:16] - reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 566:36] - reg lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 567:37] + reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 572:36] + reg lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 573:37] reg r_d_bits_i0store; // @[lib.scala 384:16] - wire _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 571:61] + wire _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 577:61] wire [3:0] _T_543 = {_T_539,_T_539,_T_539,_T_539}; // @[Cat.scala 29:58] - wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 571:82] - wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 571:105] + wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 577:82] + wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 577:105] reg r_d_bits_i0div; // @[lib.scala 384:16] - wire _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 577:58] - wire _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 588:60] - wire _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 589:60] - wire _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 590:48] - wire i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 590:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 594:38] - wire _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 595:27] - wire i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 595:38] + wire _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 583:58] + wire _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 594:60] + wire _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 595:60] + wire _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 596:48] + wire i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 596:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 600:38] + wire _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 601:27] + wire i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 601:38] wire [31:0] _T_566 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] wire [9:0] _T_580 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_589 = {_T_580,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] @@ -46972,55 +46972,55 @@ module dec_decode_ctl( wire [31:0] _T_655 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_690 = i0_uiimm20 ? _T_655 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_694 = _T_693 | _T_690; // @[Mux.scala 27:72] - wire _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 606:26] + wire _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 612:26] wire [31:0] _T_686 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_691 = _T_656 ? _T_686 : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_immed_d = _T_694 | _T_691; // @[Mux.scala 27:72] wire [31:0] _T_567 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 610:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 611:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 612:44] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44] reg i0_x_c_mul; // @[Reg.scala 27:20] reg i0_x_c_alu; // @[Reg.scala 27:20] reg i0_r_c_mul; // @[Reg.scala 27:20] reg i0_r_c_alu; // @[Reg.scala 27:20] - wire _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 620:49] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 622:50] + wire _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50] reg x_d_bits_i0store; // @[lib.scala 384:16] reg x_d_bits_i0div; // @[lib.scala 384:16] reg x_d_bits_csrwen; // @[lib.scala 384:16] reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 384:16] - wire _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 644:47] - wire _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 645:33] - wire _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 660:49] - wire _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 660:47] - wire _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 660:70] - wire _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 669:47] - wire _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 675:71] + wire _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 650:47] + wire _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 651:33] + wire _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49] + wire _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 666:47] + wire _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70] + wire _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47] + wire _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71] wire [11:0] _T_786 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[lib.scala 374:16] - wire _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 683:45] - wire div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 683:58] - wire _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 685:77] - wire _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 685:60] - wire _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 686:33] - wire _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 685:94] - wire _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 687:33] - wire _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 687:60] - wire div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 686:62] - wire _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 691:51] - wire _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 692:26] - wire _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 692:24] - wire _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 692:56] - wire _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 692:39] - wire _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 692:77] - wire nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 691:65] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 695:55] - wire _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 697:62] - wire _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 697:60] - wire _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 697:81] - wire _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 697:79] - reg _T_826; // @[dec_decode_ctl.scala 699:54] + wire _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45] + wire div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 689:58] + wire _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77] + wire _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 691:60] + wire _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33] + wire _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 691:94] + wire _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33] + wire _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60] + wire div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 692:62] + wire _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51] + wire _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26] + wire _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 698:24] + wire _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56] + wire _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 698:39] + wire _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 698:77] + wire nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 697:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55] + wire _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62] + wire _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 703:60] + wire _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81] + wire _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 703:79] + reg _T_826; // @[dec_decode_ctl.scala 705:54] reg [4:0] _T_835; // @[Reg.scala 27:20] reg [31:0] i0_inst_x; // @[lib.scala 374:16] reg [31:0] i0_inst_r; // @[lib.scala 374:16] @@ -47045,65 +47045,65 @@ module dec_decode_ctl( wire [18:0] _T_875 = _T_872 | _T_873; // @[Mux.scala 27:72] wire [18:0] _T_876 = _T_875 | _T_874; // @[Mux.scala 27:72] wire [31:0] temp_pred_correct_npc_x = {_T_876,_T_851[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 738:61] - wire _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 738:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 738:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 738:24] - wire _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 740:61] - wire _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 740:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 740:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 740:24] - wire _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 758:73] - wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 758:130] - wire i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 758:100] - wire _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 760:73] - wire _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 760:130] - wire i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 760:100] - wire _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 763:66] - wire _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 763:45] - wire _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:108] - wire _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:196] - wire _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 763:153] + wire _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61] + wire _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 744:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 744:24] + wire _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61] + wire _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 746:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 746:24] + wire _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73] + wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130] + wire i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 764:100] + wire _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73] + wire _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130] + wire i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 766:100] + wire _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66] + wire _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 769:45] + wire _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108] + wire _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196] + wire _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 769:153] wire [2:0] i0_rs1bypass = {_T_920,_T_922,_T_926}; // @[Cat.scala 29:58] - wire _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 765:67] - wire _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 765:45] - wire _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:109] - wire _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:196] - wire _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 765:153] + wire _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67] + wire _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 771:45] + wire _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109] + wire _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196] + wire _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 771:153] wire [2:0] i0_rs2bypass = {_T_931,_T_933,_T_937}; // @[Cat.scala 29:58] - wire _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 767:86] - wire _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 767:107] - wire _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 767:124] - wire _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 767:104] - wire _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 768:86] - wire _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 768:107] - wire _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 768:124] - wire _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 768:104] - wire _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 774:6] - wire _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 774:25] - wire _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 774:23] - wire _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:42] + wire _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86] + wire _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107] + wire _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124] + wire _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 773:104] + wire _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86] + wire _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107] + wire _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124] + wire _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 774:104] + wire _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6] + wire _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25] + wire _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 780:23] + wire _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42] wire [31:0] _T_969 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_970 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_971 = _T_967 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_972 = _T_969 | _T_970; // @[Mux.scala 27:72] - wire _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 779:6] - wire _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 779:25] - wire _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 779:23] - wire _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 779:42] + wire _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6] + wire _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25] + wire _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 785:23] + wire _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42] wire [31:0] _T_986 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_987 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_988 = _T_984 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72] - wire _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 781:68] - wire _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 781:50] - wire _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 781:89] - wire _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 781:87] - wire _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 781:121] - wire _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 783:6] - wire _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 783:38] - wire _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 783:50] - wire _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 784:50] + wire _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68] + wire _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 787:50] + wire _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89] + wire _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 787:87] + wire _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 787:121] + wire _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6] + wire _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38] + wire _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 789:50] + wire _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 790:50] wire [11:0] _T_1010 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1011 = _T_1001 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1012 = _T_1006 ? _T_1010 : 12'h0; // @[Mux.scala 27:72] @@ -47113,7 +47113,7 @@ module dec_decode_ctl( .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 356:22] + dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 362:22] .io_ins(i0_dec_io_ins), .io_out_alu(i0_dec_io_out_alu), .io_out_rs1(i0_dec_io_out_rs1), @@ -47280,116 +47280,116 @@ module dec_decode_ctl( .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 626:38] - assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 627:38] - assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 249:37] - assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 250:37] - assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 251:37] - assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 252:37] - assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 253:37] - assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 254:37] - assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 257:37] - assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 258:37] - assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 259:37] - assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 260:37] - assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 247:37] - assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 248:37] - assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 255:37] - assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 256:37] - assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 263:37] - assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 245:37] - assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 244:37] - assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 261:37] - assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 262:37] - assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 202:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 200:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 201:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 214:56] - assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 209:56] - assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 210:56] - assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 199:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 196:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 198:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 197:55] - assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 216:56] - assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 215:56] - assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 211:56] - assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 212:56] - assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 588:35] - assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 589:35] - assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 597:32] - assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 771:42] - assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 776:42] - assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 236:36] - assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 767:45] - assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 768:45] - assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 391:32] - assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 392:37] - assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 393:37] - assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 394:37] - assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 728:36] - assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 396:34] - assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 536:34] - assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 418:29] - assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 675:32] - assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 387:29] - assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 388:34] - assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 389:34] - assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 694:37] - assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 516:30 dec_decode_ctl.scala 582:30] - assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 717:22] - assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 720:20] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 591:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 592:19] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 658:27] - assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 660:32] - assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 661:26] - assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 403:24 dec_decode_ctl.scala 405:35] - assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 402:29] - assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 408:40] - assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 409:40] - assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 401:29 dec_decode_ctl.scala 410:40] - assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 400:29 dec_decode_ctl.scala 406:40] - assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 407:40] - assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 414:40] - assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 412:40] - assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 411:40] - assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 705:19] - assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 781:26] - assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 782:23] - assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 427:24] - assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 493:24] - assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 430:24] - assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 435:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 431:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 478:24] - assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 438:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 542:29] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 576:39 dec_decode_ctl.scala 577:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 576:39] - assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 723:27] - assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 500:23] - assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 521:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 522:27] - assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 524:29] - assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 523:29] - assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 318:28] - assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 315:29 dec_decode_ctl.scala 325:29] - assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 462:22] - assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 466:25] - assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 699:21] + assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 632:38] + assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 633:38] + assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 255:31] + assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 256:31] + assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 257:31] + assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 258:31] + assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 259:31] + assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 260:31] + assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 263:31] + assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 264:31] + assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 265:31] + assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 266:31] + assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 253:31] + assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 254:31] + assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 261:31] + assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 262:31] + assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 269:33] + assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 251:37] + assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 250:37] + assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 267:33] + assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 268:33] + assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 206:49] + assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 204:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 205:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 218:60] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 213:67] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 214:67] + assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 203:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 200:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 202:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 201:54] + assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 220:67] + assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 219:43] + assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 215:43] + assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 216:43] + assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35] + assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35] + assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32] + assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 777:42] + assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 782:42] + assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36] + assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 773:45] + assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 774:45] + assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32] + assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37] + assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37] + assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 400:37] + assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 734:36] + assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34] + assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34] + assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29] + assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 681:32] + assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29] + assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34] + assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34] + assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 700:37] + assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 723:22] + assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 726:20] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27] + assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 666:32] + assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26] + assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35] + assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29] + assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40] + assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 415:40] + assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 407:29 dec_decode_ctl.scala 416:40] + assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 406:29 dec_decode_ctl.scala 412:40] + assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 413:40] + assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40] + assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40] + assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 711:19] + assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26] + assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 788:23] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24] + assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 441:20] + assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23] + assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 548:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 582:39 dec_decode_ctl.scala 583:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 582:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 729:27] + assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 506:23] + assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 527:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 528:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 530:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 529:29] + assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 324:28] + assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29] + assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22] + assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25] + assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 705:21] + assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 357:16] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 363:16] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52606,7 +52606,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:56] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:61] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] @@ -54381,7 +54381,6 @@ module dec_tlu_ctl( output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, - output io_dec_tlu_flush_lower_wb, input io_ifu_pmu_instr_aligned, output io_tlu_bp_dec_tlu_br0_r_pkt_valid, output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist, @@ -54389,6 +54388,7 @@ module dec_tlu_ctl( output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle, + output io_tlu_bp_dec_tlu_flush_lower_wb, output io_tlu_bp_dec_tlu_flush_leak_one_wb, output io_tlu_bp_dec_tlu_bpred_disable, output io_tlu_ifc_dec_tlu_flush_noredir_wb, @@ -54509,26 +54509,26 @@ module dec_tlu_ctl( reg [31:0] _RAND_73; reg [31:0] _RAND_74; `endif // RANDOMIZE_REG_INIT - wire int_timers_clock; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_reset; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:30] - wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:30] - wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:30] - wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:30] - wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_clock; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_reset; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 274:30] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 274:30] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 274:30] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 274:30] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -54884,25 +54884,25 @@ module dec_tlu_ctl( wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1010:22] wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1010:22] reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 366:89] - wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 273:39] reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 361:89] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 37:81] reg [6:0] syncro_ff; // @[lib.scala 37:58] - wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:67] - wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:59] - wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:59] - wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:51] - wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:51] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 301:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 304:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 305:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 306:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 307:51] wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1003:31] reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 612:74] - wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:67] - reg e5_valid; // @[dec_tlu_ctl.scala 324:97] - wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:30] - reg debug_mode_status; // @[dec_tlu_ctl.scala 325:81] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 311:67] + reg e5_valid; // @[dec_tlu_ctl.scala 323:97] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 314:30] + reg debug_mode_status; // @[dec_tlu_ctl.scala 324:81] reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 572:80] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:72] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 339:72] wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 348:45] wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 348:43] reg mdseac_locked_f; // @[dec_tlu_ctl.scala 605:89] @@ -54910,7 +54910,7 @@ module dec_tlu_ctl( wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 346:96] wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 346:49] wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 348:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:72] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 340:72] reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 814:98] wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 348:106] wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 348:104] @@ -54943,7 +54943,7 @@ module dec_tlu_ctl( wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 599:216] wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 599:214] wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 599:45] - wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:50] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 315:50] wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 750:49] wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 750:47] wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 767:40] @@ -54964,9 +54964,9 @@ module dec_tlu_ctl( wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 399:69] wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 358:67] wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 402:50] - reg reset_detect; // @[dec_tlu_ctl.scala 334:88] - reg reset_detected; // @[dec_tlu_ctl.scala 335:88] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:64] + reg reset_detect; // @[dec_tlu_ctl.scala 335:88] + reg reset_detected; // @[dec_tlu_ctl.scala 336:88] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 337:64] wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 402:95] wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 402:93] wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 402:76] @@ -55072,15 +55072,15 @@ module dec_tlu_ctl( wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 771:62] wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 657:51] wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:64] - wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 519:58] + wire _T_297 = io_tlu_bp_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 519:65] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 519:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 517:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 509:57] @@ -55109,7 +55109,7 @@ module dec_tlu_ctl( wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 506:352] wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 517:146] - wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 519:84] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 519:91] wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 522:60] wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 522:89] wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 522:57] @@ -55126,12 +55126,12 @@ module dec_tlu_ctl( wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 657:88] wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 657:110] wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 657:108] - reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:80] + reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 327:80] wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 632:44] wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 632:42] wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 632:66] - reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:89] - reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:89] + reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 321:89] + reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 322:89] wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 632:154] wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 632:173] wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 632:137] @@ -55161,7 +55161,7 @@ module dec_tlu_ctl( wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 685:92] wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 685:90] wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 784:49] - wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 608:57] + wire _T_402 = ~io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 608:57] wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 608:55] wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 610:40] wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 610:62] @@ -55182,7 +55182,7 @@ module dec_tlu_ctl( wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 623:121] wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 623:119] wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 623:146] - reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:80] + reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 320:80] wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 641:52] wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 660:51] wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 660:64] @@ -55278,32 +55278,32 @@ module dec_tlu_ctl( wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 769:231] wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 769:247] wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 774:118] - wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:69] - wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:89] - wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:112] - wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:128] + wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 315:69] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 315:89] + wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 315:112] + wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 315:128] reg pause_expired_wb; // @[dec_tlu_ctl.scala 815:90] - wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:146] + wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 315:146] wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 663:51] wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 663:101] wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 663:72] wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 663:131] wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 663:129] - wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:165] - wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:177] + wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 315:165] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 315:177] wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 664:59] wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 664:80] wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 664:137] - wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:192] - wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:207] - wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:225] - reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:80] - reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:72] - reg _T_32; // @[dec_tlu_ctl.scala 329:73] - reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:72] - reg _T_33; // @[dec_tlu_ctl.scala 331:89] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:72] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:72] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 315:192] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 315:207] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 315:225] + reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 325:80] + reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 326:72] + reg _T_32; // @[dec_tlu_ctl.scala 328:73] + reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 329:72] + reg _T_33; // @[dec_tlu_ctl.scala 330:89] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 341:72] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 342:72] wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 350:48] wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 350:96] wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 350:94] @@ -55488,7 +55488,7 @@ module dec_tlu_ctl( reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 744:62] wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 749:46] wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 749:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 751:49] wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1007:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] @@ -55547,46 +55547,46 @@ module dec_tlu_ctl( wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 812:119] reg i0_valid_wb; // @[dec_tlu_ctl.scala 812:97] reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 813:89] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1014:42] wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1014:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1019:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1019:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1019:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1019:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1019:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1019:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1019:179] wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1019:36] wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1019:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1019:33] wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1019:223] wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1019:221] wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1021:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1021:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1021:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1021:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1021:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1021:193] wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1021:82] wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1021:59] - dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:30] + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 274:30] .clock(int_timers_clock), .reset(int_timers_reset), .io_free_clk(int_timers_io_free_clk), @@ -56023,8 +56023,8 @@ module dec_tlu_ctl( assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 395:31] assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 897:40] assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1021:20] - assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:41] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 328:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 334:41] assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 899:40] assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 479:34] assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1014:23] @@ -56045,20 +56045,20 @@ module dec_tlu_ctl( assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 894:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 895:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 896:40] - assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 800:41] assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 652:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 649:65] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 650:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 651:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 653:65] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 654:65] + assign io_tlu_bp_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 800:49] assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 483:45] assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 902:47] assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 474:45] assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 900:48] assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 484:41] assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 627:37] - assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:57] + assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 330:57] assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 672:39] assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 881:52] assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 881:52] @@ -56072,20 +56072,20 @@ module dec_tlu_ctl( assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 877:52] assign int_timers_clock = clock; assign int_timers_reset = reset; - assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:57] - assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:57] - assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 278:49] - assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 280:49] - assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 281:49] - assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:57] - assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:57] - assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:57] - assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:57] - assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:57] - assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:57] - assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:49] - assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 289:49] - assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:47] + assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 275:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 276:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 277:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 279:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 280:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 281:57] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 282:57] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 283:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 284:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 285:57] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 286:57] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 287:49] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 288:49] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 289:47] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -58226,9 +58226,6 @@ module dec( wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 118:22] wire [31:0] decode_io_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 118:22] wire decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 118:22] - wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] - wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] - wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire decode_io_dec_tlu_flush_extint; // @[dec.scala 118:22] wire decode_io_dec_tlu_force_halt; // @[dec.scala 118:22] wire [31:0] decode_io_dec_i0_inst_wb1; // @[dec.scala 118:22] @@ -58326,6 +58323,9 @@ module dec( wire decode_io_dec_pause_state_cg; // @[dec.scala 118:22] wire decode_io_dec_div_active; // @[dec.scala 118:22] wire decode_io_scan_mode; // @[dec.scala 118:22] + wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] + wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] + wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire gpr_clock; // @[dec.scala 119:19] wire gpr_reset; // @[dec.scala 119:19] wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19] @@ -58488,7 +58488,6 @@ module dec( wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] - wire tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 120:19] wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 120:19] wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 120:19] @@ -58496,6 +58495,7 @@ module dec( wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 120:19] wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 120:19] @@ -58678,9 +58678,6 @@ module dec( .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag), .io_dctl_busbuff_lsu_nonblock_load_data(decode_io_dctl_busbuff_lsu_nonblock_load_data), .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any), - .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d), - .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), - .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata), .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt), .io_dec_i0_inst_wb1(decode_io_dec_i0_inst_wb1), @@ -58777,7 +58774,10 @@ module dec( .io_dec_pause_state(decode_io_dec_pause_state), .io_dec_pause_state_cg(decode_io_dec_pause_state_cg), .io_dec_div_active(decode_io_dec_div_active), - .io_scan_mode(decode_io_scan_mode) + .io_scan_mode(decode_io_scan_mode), + .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d), + .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), + .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata) ); dec_gpr_ctl gpr ( // @[dec.scala 119:19] .clock(gpr_clock), @@ -58944,7 +58944,6 @@ module dec( .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), - .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned), .io_tlu_bp_dec_tlu_br0_r_pkt_valid(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist), @@ -58952,6 +58951,7 @@ module dec( .io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_way(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle), + .io_tlu_bp_dec_tlu_flush_lower_wb(tlu_io_tlu_bp_dec_tlu_flush_lower_wb), .io_tlu_bp_dec_tlu_flush_leak_one_wb(tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb), .io_tlu_bp_dec_tlu_bpred_disable(tlu_io_tlu_bp_dec_tlu_bpred_disable), .io_tlu_ifc_dec_tlu_flush_noredir_wb(tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb), @@ -59209,8 +59209,6 @@ module dec( assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 141:26] assign decode_io_dctl_busbuff_lsu_nonblock_load_data = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 141:26] assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 138:22] - assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21] - assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22] assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 139:48] assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 140:48] assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 142:48] @@ -59241,7 +59239,7 @@ module dec( assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 162:48] assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 163:48] assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 164:48] - assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 165:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 165:48] assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 166:48] assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 167:48] assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 168:48] @@ -59259,6 +59257,8 @@ module dec( assign decode_io_active_clk = io_active_clk; // @[dec.scala 180:48] assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 181:48] assign decode_io_scan_mode = io_scan_mode; // @[dec.scala 182:48] + assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21] + assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22] assign gpr_clock = clock; assign gpr_reset = reset; assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 189:23] diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index b4d0c6b7..e674d84b 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -162,7 +162,7 @@ class dec extends Module with param with RequireAsyncReset{ decode.io.lsu_store_stall_any := io.lsu_store_stall_any decode.io.exu_div_wren := io.exu_div_wren decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb - decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.tlu_bp.dec_tlu_flush_lower_wb decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r @@ -302,8 +302,4 @@ class dec extends Module with param with RequireAsyncReset{ // debug command read data io.dec_dbg_rddata := decode.io.dec_i0_wdata_r -} - -object dec_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new dec())) -} +} \ No newline at end of file diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala index 526f1c24..ba320a11 100644 --- a/src/main/scala/dec/dec_decode_ctl.scala +++ b/src/main/scala/dec/dec_decode_ctl.scala @@ -10,257 +10,263 @@ import lsu._ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ val io = IO(new Bundle{ - val decode_exu = Flipped(new decode_exu) //connection with exu top - val dec_alu = Flipped(new dec_alu) //connection with alu - val dec_div = Flipped(new dec_div) //connection with divider - val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer - val dctl_dma = new dctl_dma //connection with dma - val dec_aln = Flipped(new aln_dec) //connection with aligner - val dbg_dctl = new dbg_dctl() //connection with dbg - val dec_tlu_flush_extint = Input(Bool()) - val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event - val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder - val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder - val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches - val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r - val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only - val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches - val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign - val dec_tlu_debug_stall = Input(Bool()) // debug stall decode - val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction - val dec_debug_fence_d = Input(Bool()) // debug fence instruction - val dec_i0_icaf_d = Input(Bool()) // icache access fault - val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group - val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type - val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error - val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet - val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index - val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR - val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag - val dec_i0_pc_d = Input(UInt(31.W)) // pc - val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode - val lsu_load_stall_any = Input(Bool()) // stall any load at decode - val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 - val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. - val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state - val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush - val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state - val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush - val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush - val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd - val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd - val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B - val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb - val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation - val lsu_result_m = Input(UInt(32.W)) // load result - val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing - val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D - val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode - val dec_ib0_valid_d = Input(Bool()) // inst valid at decode - val free_clk = Input(Clock()) - val active_clk = Input(Clock()) // clk except for halt / pause - val clk_override = Input(Bool()) // test stuff - val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source - val dec_i0_rs2_d = Output(UInt(5.W)) - val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's - val dec_i0_wen_r = Output(Bool()) // i0 write enable - val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data - val lsu_p = Valid(new lsu_pkt_t) // load/store packet - val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR - val dec_lsu_valid_raw_d = Output(Bool()) - val dec_lsu_offset_d = Output(UInt(12.W)) - val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal - val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal - val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr - val dec_csr_wen_r = Output(Bool()) // csr write enable at r - val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr - val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r - val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus - val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c - val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet - val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc - val dec_illegal_inst = Output(UInt(32.W)) // illegal inst - val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded - val dec_pmu_decode_stall = Output(Bool()) // decode is stalled - val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall - val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall - val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load - val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load - val dec_pause_state = Output(Bool()) // core in pause state - val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating - val dec_div_active = Output(Bool()) // non-block divide is active - val scan_mode = Input(Bool()) + val decode_exu = Flipped(new decode_exu) + val dec_alu = Flipped(new dec_alu) + val dec_div = Flipped(new dec_div) + val dctl_busbuff = Flipped(new dctl_busbuff()) + val dctl_dma = new dctl_dma + val dec_tlu_flush_extint = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event + val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder + val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder + val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches + val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r + val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only + val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches + val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign + val dec_tlu_debug_stall = Input(Bool()) // debug stall decode + val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction + val dec_debug_fence_d = Input(Bool()) // debug fence instruction + val dec_i0_icaf_d = Input(Bool()) // icache access fault + val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type + val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error + val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet + val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_pc_d = Input(UInt(31.W)) // pc + val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode + val lsu_load_stall_any = Input(Bool()) // stall any load at decode + val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 + val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. + val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush + val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush + val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush + val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd + val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B + val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing + val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D + val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode + val dec_ib0_valid_d = Input(Bool()) // inst valid at decode + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) // clk except for halt / pause + val clk_override = Input(Bool()) // test stuff + val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source + val dec_i0_rs2_d = Output(UInt(5.W)) + val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's + val dec_i0_wen_r = Output(Bool()) // i0 write enable + val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data + val lsu_p = Valid(new lsu_pkt_t) // load/store packet + val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR + val dec_lsu_valid_raw_d = Output(Bool()) + val dec_lsu_offset_d = Output(UInt(12.W)) + val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal + val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr + val dec_csr_wen_r = Output(Bool()) // csr write enable at r + val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r + val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus + val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c + val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet + val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc + val dec_illegal_inst = Output(UInt(32.W)) // illegal inst + val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded + val dec_pmu_decode_stall = Output(Bool()) // decode is stalled + val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall + val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall + val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load + val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load + val dec_pause_state = Output(Bool()) // core in pause state + val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating + val dec_div_active = Output(Bool()) // non-block divide is active + val scan_mode = Input(Bool()) + + val dec_aln = Flipped(new aln_dec) + val dbg_dctl = new dbg_dctl() }) - //packets zero initialization - io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p) + ///////////////////////////////////////////////////////////////////////////////////////// +// //packets zero initialization + io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p) // Vals defined - val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) - val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) - val i0r = Wire(new reg_pkt_t) - val d_t = Wire(new trap_pkt_t) - val x_t = Wire(new trap_pkt_t) - val x_t_in = Wire(new trap_pkt_t) - val r_t = Wire(new trap_pkt_t) - val r_t_in = Wire(new trap_pkt_t) - val d_d = Wire(Valid(new dest_pkt_t)) - val x_d = Wire(Valid(new dest_pkt_t)) - val r_d = Wire(Valid(new dest_pkt_t)) - val r_d_in = Wire(Valid(new dest_pkt_t)) - val wbd = Wire(Valid(new dest_pkt_t)) - val i0_d_c = Wire(new class_pkt_t) - val i0_rs1_class_d = Wire(new class_pkt_t) - val i0_rs2_class_d = Wire(new class_pkt_t) - val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) - val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) - val cam_wen = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) - val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) - val cam_write = WireInit(UInt(1.W), 0.U) - val cam_inv_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) - val cam_data_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) - val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) - val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) - val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) - val i0_dp = Wire(new dec_pkt_t) - val i0_dp_raw = Wire(new dec_pkt_t) - val i0_rs1bypass = WireInit(UInt(3.W), 0.U) - val i0_rs2bypass = WireInit(UInt(3.W), 0.U) - val illegal_lockout = WireInit(UInt(1.W), 0.U) - val postsync_stall = WireInit(UInt(1.W), 0.U) - val ps_stall_in = WireInit(UInt(1.W), 0.U) - val i0_pipe_en = WireInit(UInt(4.W), 0.U) - val i0_load_block_d = WireInit(UInt(1.W), 0.U) - val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) - val store_data_bypass_d = WireInit(UInt(1.W), 0.U) - val store_data_bypass_m = WireInit(UInt(1.W), 0.U) - val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) - val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) - val leak1_i1_stall = WireInit(UInt(1.W), 0.U) - val leak1_i0_stall = WireInit(UInt(1.W), 0.U) - val pause_state = WireInit(Bool(), 0.B) - val flush_final_r = WireInit(UInt(1.W), 0.U) - val illegal_lockout_in = WireInit(UInt(1.W), 0.U) - val lsu_idle = WireInit(Bool(), 0.B) - val pause_state_in = WireInit(Bool(), 0.B) - val leak1_mode = WireInit(UInt(1.W), 0.U) - val i0_pcall = WireInit(UInt(1.W), 0.U) - val i0_pja = WireInit(UInt(1.W), 0.U) - val i0_pret = WireInit(UInt(1.W), 0.U) - val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) - val i0_pcall_raw = WireInit(UInt(1.W), 0.U) - val i0_pja_raw = WireInit(UInt(1.W), 0.U) - val i0_pret_raw = WireInit(UInt(1.W), 0.U) - val i0_br_offset = WireInit(UInt(12.W), 0.U) - val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) - val i0_jal = WireInit(UInt(1.W), 0.U) - val i0_wen_r = WireInit(UInt(1.W), 0.U) - val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) - val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) - val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) - val i0_x_data_en = WireInit(UInt(1.W), 0.U) - val i0_r_data_en = WireInit(UInt(1.W), 0.U) - val i0_wb_data_en = WireInit(UInt(1.W), 0.U) - val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) - val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) - val csr_ren_qual_d = WireInit(Bool(), 0.B) - val lsu_decode_d = WireInit(UInt(1.W), 0.U) - val mul_decode_d = WireInit(UInt(1.W), 0.U) - val div_decode_d = WireInit(UInt(1.W), 0.U) - val write_csr_data = WireInit(UInt(32.W),0.U) - val i0_result_corr_r = WireInit(UInt(32.W),0.U) - val presync_stall = WireInit(UInt(1.W), 0.U) - val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) - val debug_fence = WireInit(Bool(), 0.B) - val i0_immed_d = WireInit(UInt(32.W), 0.U) - val i0_result_x = WireInit(UInt(32.W), 0.U) - val i0_result_r = WireInit(UInt(32.W), 0.U) + val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) + val i0r = Wire(new reg_pkt_t) + val d_t = Wire(new trap_pkt_t) + val x_t = Wire(new trap_pkt_t) + val x_t_in = Wire(new trap_pkt_t) + val r_t = Wire(new trap_pkt_t) + val r_t_in = Wire(new trap_pkt_t) + val d_d = Wire(Valid(new dest_pkt_t)) + val x_d = Wire(Valid(new dest_pkt_t)) + val r_d = Wire(Valid(new dest_pkt_t)) + val r_d_in = Wire(Valid(new dest_pkt_t)) + val wbd = Wire(Valid(new dest_pkt_t)) + val i0_d_c = Wire(new class_pkt_t) + val i0_rs1_class_d = Wire(new class_pkt_t) + val i0_rs2_class_d = Wire(new class_pkt_t) + val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) + val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) + val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + val cam_write=WireInit(UInt(1.W), 0.U) + val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + //val i0_temp = Wire(new inst_pkt_t) + val i0_dp= Wire(new dec_pkt_t) + val i0_dp_raw= Wire(new dec_pkt_t) + val i0_rs1bypass = WireInit(UInt(3.W), 0.U) + val i0_rs2bypass = WireInit(UInt(3.W), 0.U) + val illegal_lockout = WireInit(UInt(1.W), 0.U) + val postsync_stall = WireInit(UInt(1.W), 0.U) + val ps_stall_in = WireInit(UInt(1.W), 0.U) + val i0_pipe_en = WireInit(UInt(4.W), 0.U) + val i0_load_block_d = WireInit(UInt(1.W), 0.U) + val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_m = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) + val leak1_i1_stall = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall = WireInit(UInt(1.W), 0.U) + val pause_state = WireInit(Bool(), 0.B) + val flush_final_r = WireInit(UInt(1.W), 0.U) + val illegal_lockout_in = WireInit(UInt(1.W), 0.U) + val lsu_idle = WireInit(Bool(), 0.B) + val pause_state_in = WireInit(Bool(), 0.B) + val leak1_mode = WireInit(UInt(1.W), 0.U) + val i0_pcall = WireInit(UInt(1.W), 0.U) + val i0_pja = WireInit(UInt(1.W), 0.U) + val i0_pret = WireInit(UInt(1.W), 0.U) + val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) + val i0_pcall_raw = WireInit(UInt(1.W), 0.U) + val i0_pja_raw = WireInit(UInt(1.W), 0.U) + val i0_pret_raw = WireInit(UInt(1.W), 0.U) + val i0_br_offset = WireInit(UInt(12.W), 0.U) + val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) + val i0_jal = WireInit(UInt(1.W), 0.U) + val i0_wen_r = WireInit(UInt(1.W), 0.U) + val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_x_data_en = WireInit(UInt(1.W), 0.U) + val i0_r_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) + val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) + val csr_ren_qual_d = WireInit(Bool(), 0.B) + val lsu_decode_d = WireInit(UInt(1.W), 0.U) + val mul_decode_d = WireInit(UInt(1.W), 0.U) + val div_decode_d = WireInit(UInt(1.W), 0.U) + val write_csr_data = WireInit(UInt(32.W),0.U) + val i0_result_corr_r = WireInit(UInt(32.W),0.U) + val presync_stall = WireInit(UInt(1.W), 0.U) + val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) + val debug_fence = WireInit(Bool(), 0.B) + val i0_immed_d = WireInit(UInt(32.W), 0.U) + val i0_result_x = WireInit(UInt(32.W), 0.U) + val i0_result_r = WireInit(UInt(32.W), 0.U) ////////////////////////////////////////////////////////////////////// // Start - Data gating {{ - val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk - (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk - (io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) | - (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk - (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk - (pause_state_in ^ pause_state ) | // replaces free_clk - (ps_stall_in ^ postsync_stall ) | // replaces free_clk - (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk - (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk + val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk + (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk + (io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) | + (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk + (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk + (pause_state_in ^ pause_state ) | // replaces free_clk + (ps_stall_in ^ postsync_stall ) | // replaces free_clk + (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk + (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk - val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode) - // End - Data gating + val data_gate_clk= rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode) - val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode - io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U - io.decode_exu.dec_i0_predict_p_d.bits.ataken := 0.U - io.decode_exu.dec_i0_predict_p_d.bits.boffset := 0.U - io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error - io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja - io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret - io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett - io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d - io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist - io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d - val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) + // End - Data gating }} + + val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode + io.decode_exu.dec_i0_predict_p_d.bits.misp :=0.U + io.decode_exu.dec_i0_predict_p_d.bits.ataken :=0.U + io.decode_exu.dec_i0_predict_p_d.bits.boffset :=0.U + io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error + io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja + io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret + io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett + io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d + io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist + io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d + val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) // no toffset error for a pret - val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw - val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; - val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error - io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode - io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode - io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index - io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag - val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode - io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset - io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr - io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way + val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw + val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; + val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error + io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode + io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index + io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag + val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode + io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset + io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr + io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way // end // on br error turn anything into a nop // on i0 instruction fetch access fault turn anything into a nop // nop => alu rs1 imm12 rd lor - val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d - val i0_instr_error = i0_icaf_d; - i0_dp := i0_dp_raw + val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d + + val i0_instr_error = i0_icaf_d; + i0_dp := i0_dp_raw when((i0_br_error_all | i0_instr_error).asBool){ - i0_dp := 0.U.asTypeOf(i0_dp) - i0_dp.alu := 1.B - i0_dp.rs1 := 1.B - i0_dp.rs2 := 1.B - i0_dp.lor := 1.B - i0_dp.legal := 1.B - i0_dp.postsync := 1.B + i0_dp := 0.U.asTypeOf(i0_dp) + i0_dp.alu := 1.B + i0_dp.rs1 := 1.B + i0_dp.rs2 := 1.B + i0_dp.lor := 1.B + i0_dp.legal := 1.B + i0_dp.postsync := 1.B } - val i0 = io.dec_i0_instr_d + val i0 = io.dec_i0_instr_d io.decode_exu.dec_i0_select_pc_d := i0_dp.pc // branches that can be predicted - val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; - val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br - val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br - val i0_ap_pc2 = !io.dec_i0_pc4_d - val i0_ap_pc4 = io.dec_i0_pc4_d + val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; + + val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br + val i0_ap_pc2 = !io.dec_i0_pc4_d + val i0_ap_pc4 = io.dec_i0_pc4_d io.decode_exu.i0_ap.predict_nt := i0_predict_nt io.decode_exu.i0_ap.predict_t := i0_predict_t - io.decode_exu.i0_ap.add := i0_dp.add - io.decode_exu.i0_ap.sub := i0_dp.sub - io.decode_exu.i0_ap.land := i0_dp.land - io.decode_exu.i0_ap.lor := i0_dp.lor - io.decode_exu.i0_ap.lxor := i0_dp.lxor - io.decode_exu.i0_ap.sll := i0_dp.sll - io.decode_exu.i0_ap.srl := i0_dp.srl - io.decode_exu.i0_ap.sra := i0_dp.sra - io.decode_exu.i0_ap.slt := i0_dp.slt - io.decode_exu.i0_ap.unsign := i0_dp.unsign - io.decode_exu.i0_ap.beq := i0_dp.beq - io.decode_exu.i0_ap.bne := i0_dp.bne - io.decode_exu.i0_ap.blt := i0_dp.blt - io.decode_exu.i0_ap.bge := i0_dp.bge - io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d - io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm - io.decode_exu.i0_ap.jal := i0_jal + io.decode_exu.i0_ap.add := i0_dp.add + io.decode_exu.i0_ap.sub := i0_dp.sub + io.decode_exu.i0_ap.land := i0_dp.land + io.decode_exu.i0_ap.lor := i0_dp.lor + io.decode_exu.i0_ap.lxor := i0_dp.lxor + io.decode_exu.i0_ap.sll := i0_dp.sll + io.decode_exu.i0_ap.srl := i0_dp.srl + io.decode_exu.i0_ap.sra := i0_dp.sra + io.decode_exu.i0_ap.slt := i0_dp.slt + io.decode_exu.i0_ap.unsign := i0_dp.unsign + io.decode_exu.i0_ap.beq := i0_dp.beq + io.decode_exu.i0_ap.bne := i0_dp.bne + io.decode_exu.i0_ap.blt := i0_dp.blt + io.decode_exu.i0_ap.bge := i0_dp.bge + io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d + io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm + io.decode_exu.i0_ap.jal := i0_jal // non block load cam logic // val found=Wire(UInt(1.W)) @@ -661,7 +667,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ io.dec_i0_wdata_r := i0_result_corr_r val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) - if ( LOAD_TO_USE_PLUS1) { + if ( LOAD_TO_USE_PLUS1 == 1 ) { i0_result_x := io.decode_exu.exu_i0_result_x i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) } @@ -741,7 +747,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) // stores will bypass load data in the lsu pipe - if (LOAD_TO_USE_PLUS1) { + if (LOAD_TO_USE_PLUS1 == 1) { i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index bc0c8d79..559a2ed2 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -48,18 +48,18 @@ class dec_tlu_ctl_IO extends Bundle with lib { val active_clk = Input(Clock()) val free_clk = Input(Clock()) val scan_mode = Input(Bool()) - val rst_vec = Input(UInt(31.W)) // reset vector, from core pins - val nmi_int = Input(UInt(1.W)) // nmi pin - val nmi_vec = Input(UInt(31.W)) // nmi vector - val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU - val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU + val rst_vec = Input(UInt(31.W)) // reset vector, from core pins + val nmi_int = Input(UInt(1.W)) // nmi pin + val nmi_vec = Input(UInt(31.W)) // nmi vector + val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU val lsu_fastint_stall_any = Input(UInt(1.W)) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle - val lsu_idle_any = Input(UInt(1.W)) // lsu is idle + val lsu_idle_any = Input(UInt(1.W)) // lsu is idle // perf counter inputs - val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions - val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall - val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst - val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst + val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions + val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall + val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst + val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst val lsu_store_stall_any = Input(UInt(1.W))// SB or WB is full, stall decode val lsu_fir_addr = Input(UInt(31.W)) // Fast int address val lsu_fir_error = Input(UInt(2.W)) // Fast int lookup error @@ -141,7 +141,6 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating - val dec_tlu_flush_lower_wb = Output(Bool()) val ifu_pmu_instr_aligned = Input(UInt(1.W)) val tlu_bp = Flipped(new dec_bp) val tlu_ifc = Flipped(new dec_ifc) @@ -227,16 +226,16 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U) val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U) val debug_halt_req_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) - val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) - val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) - val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) - val dbg_halt_req_held =WireInit(UInt(1.W),0.U) - val debug_halt_req_ns =WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) - val core_empty =WireInit(UInt(1.W),0.U) - val dbg_halt_req_final =WireInit(UInt(1.W),0.U) - val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) + val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) + val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) + val dbg_halt_req_held =WireInit(UInt(1.W),0.U) + val debug_halt_req_ns =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) + val core_empty =WireInit(UInt(1.W),0.U) + val dbg_halt_req_final =WireInit(UInt(1.W),0.U) + val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U) val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U) val mpc_halt_state_ns =WireInit(UInt(1.W),0.U) @@ -329,7 +328,9 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} io.tlu_mem.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} - + + + io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} @@ -340,8 +341,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} - io.tlu_bp.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb - io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb + // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared val nmi_lsu_detected = ~mdseac_locked_f & (io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any) @@ -440,7 +440,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) - val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb) + val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.tlu_bp.dec_tlu_flush_lower_wb) val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f @@ -516,7 +516,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled // Qual trigger hits - val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r + val i0_trigger_r = ~(Fill(4,io.tlu_bp.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r // chaining can mask raw trigger info val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) @@ -605,7 +605,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr - val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb + val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.tlu_bp.dec_tlu_flush_lower_wb lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r val lsu_exc_valid_r = lsu_i0_exc_r @@ -739,7 +739,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) - if(FAST_INTERRUPT_REDIRECT) { + if(FAST_INTERRUPT_REDIRECT==1) { take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} @@ -797,8 +797,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this - io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 -// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb + io.tlu_bp.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 + io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this @@ -1747,7 +1747,7 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); - if(BUILD_AXI4){ + if(BUILD_AXI4 == 1){ // flip poweron value of bit 6 for AXI build mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) @@ -2118,7 +2118,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) - if (ICACHE_ECC) { + if (ICACHE_ECC == 1) { // ---------------------------------------------------------------------- // DICAD1 (R/W) (Only accessible in debug mode) // [6:0] : ECC @@ -2151,7 +2151,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm // DICAGO (R/W) (Only accessible in debug mode) // [0] : Go - if (ICACHE_ECC) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) + if (ICACHE_ECC == 1) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 3a5a62c1..63278256 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -419,9 +419,9 @@ class quasar extends Module with RequireAsyncReset with lib { io.dmi_reg_rdata := 0.U } -object QUASAR extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new quasar())) -} +//object QUASAR extends App { + // println((new chisel3.stage.ChiselStage).emitVerilog(new quasar())) +//} diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index 327f4b50..9fe3ad98 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class index 5bdff0f4..9840b7a0 100644 Binary files a/target/scala-2.12/classes/dec/dec.class and b/target/scala-2.12/classes/dec/dec.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class index 2d1e1dbb..b78a0315 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class and b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl.class b/target/scala-2.12/classes/dec/dec_decode_ctl.class index df8af9a8..187bcf43 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl.class and b/target/scala-2.12/classes/dec/dec_decode_ctl.class differ diff --git a/target/scala-2.12/classes/dec/dec_main$.class b/target/scala-2.12/classes/dec/dec_main$.class deleted file mode 100644 index d34fba6c..00000000 Binary files a/target/scala-2.12/classes/dec/dec_main$.class and /dev/null differ diff --git a/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class b/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class deleted file mode 100644 index d85a14e8..00000000 Binary files a/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class and /dev/null differ diff --git a/target/scala-2.12/classes/dec/dec_main.class b/target/scala-2.12/classes/dec/dec_main.class deleted file mode 100644 index fb4d68aa..00000000 Binary files a/target/scala-2.12/classes/dec/dec_main.class and /dev/null differ diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl.class b/target/scala-2.12/classes/dec/dec_tlu_ctl.class index 1fab6346..6538178d 100644 Binary files a/target/scala-2.12/classes/dec/dec_tlu_ctl.class and b/target/scala-2.12/classes/dec/dec_tlu_ctl.class differ diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class index 6300180a..685af7ea 100644 Binary files a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class and b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class differ