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@ -27,6 +27,13 @@
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_o",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_legal",
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Load Diff
File diff suppressed because it is too large
Load Diff
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@ -352,7 +352,17 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
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val bht_rd_addr_hashed_p1_f = el2_btb_ghr_hash(btb_rd_addr_p1_f, fghr)
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val bht_wr_addr0 = mp_hashed
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//val bht_wr_addr2 =
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val bht_wr_addr2 = br0_hashed_wb
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val bht_rd_addr_f = bht_rd_addr_hashed_f
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val bht_rd_addr_p1_f = bht_rd_addr_hashed_p1_f
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// BTB
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// Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid
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val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way0).asBool))
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val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way1).asBool))
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}
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object ifu_bp extends App {
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@ -11,13 +11,14 @@ class el2_ifu_compress_ctl extends Module {
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val l2 = Output(UInt(32.W))
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val l3 = Output(UInt(32.W))
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val legal = Output(Bool())
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val o = Output(UInt(32.W))
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//val test = Output(Bool())
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})
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//io.dout := (0 until 32).map(i=> 0.U.asBool)
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def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
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val out = Wire(Vec(32, Bool()))
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val out = Wire(Vec(32, UInt(1.W)))
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out := (0 until 32).map(i=> 0.U.asBool)
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out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
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out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
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@ -27,17 +28,32 @@ class el2_ifu_compress_ctl extends Module {
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out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
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pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
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out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
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out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
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pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
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out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
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(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
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(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
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pat(List(-14, -13, 0))
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out(3) := pat(List(-14, 13))
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out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
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pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14,12,8,6,-5,-4,-3,-2,1)) | pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) |
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(pat(List(15,-14,-12,-6,-5,-4,-3,-2))&(!io.din(0))) | pat(List(-15,13,-8)) | pat(List(-15,13,7)) | pat(List(-15,13,9)) |
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pat(List(-15,13,10)) | pat(List(-15,13,11)) | pat(List(-14,13))
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out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
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pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
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pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
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pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
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pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
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(pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
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pat(List(-15,13,-8)) |
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pat(List(-15,13,7)) |
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pat(List(-15,13,9)) |
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pat(List(-15,13,10)) |
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pat(List(-15,13,11)) |
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pat(List(-14,13))
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out(1) := 1.U.asBool
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out(0) := 1.U.asBool
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@ -148,6 +164,7 @@ class el2_ifu_compress_ctl extends Module {
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io.l2 := l2
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io.l3 := l3
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io.legal := legal
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io.o := out.reverse.reduce(Cat(_,_))
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}
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/*
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class ExpandedInstruction extends Bundle {
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