diff --git a/dec.fir b/dec.fir index 56441765..90ec7f0a 100644 --- a/dec.fir +++ b/dec.fir @@ -6593,558 +6593,561 @@ circuit dec : node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 588:112] node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 588:99] node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 588:76] - node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 592:40] - node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 592:51] - node i0_legal = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 592:37] - wire _T_546 : UInt<1>[16] @[lib.scala 12:48] - _T_546[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[9] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[10] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[11] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[12] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[13] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[14] <= UInt<1>("h00") @[lib.scala 12:48] - _T_546[15] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_547 = cat(_T_546[0], _T_546[1]) @[Cat.scala 29:58] - node _T_548 = cat(_T_547, _T_546[2]) @[Cat.scala 29:58] - node _T_549 = cat(_T_548, _T_546[3]) @[Cat.scala 29:58] - node _T_550 = cat(_T_549, _T_546[4]) @[Cat.scala 29:58] - node _T_551 = cat(_T_550, _T_546[5]) @[Cat.scala 29:58] - node _T_552 = cat(_T_551, _T_546[6]) @[Cat.scala 29:58] - node _T_553 = cat(_T_552, _T_546[7]) @[Cat.scala 29:58] - node _T_554 = cat(_T_553, _T_546[8]) @[Cat.scala 29:58] - node _T_555 = cat(_T_554, _T_546[9]) @[Cat.scala 29:58] - node _T_556 = cat(_T_555, _T_546[10]) @[Cat.scala 29:58] - node _T_557 = cat(_T_556, _T_546[11]) @[Cat.scala 29:58] - node _T_558 = cat(_T_557, _T_546[12]) @[Cat.scala 29:58] - node _T_559 = cat(_T_558, _T_546[13]) @[Cat.scala 29:58] - node _T_560 = cat(_T_559, _T_546[14]) @[Cat.scala 29:58] - node _T_561 = cat(_T_560, _T_546[15]) @[Cat.scala 29:58] - node _T_562 = cat(_T_561, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] - node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_562) @[dec_decode_ctl.scala 593:27] - node _T_563 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 596:49] - node shift_illegal = and(io.dec_i0_decode_d, _T_563) @[dec_decode_ctl.scala 596:47] - node _T_564 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 597:44] - node illegal_inst_en = and(shift_illegal, _T_564) @[dec_decode_ctl.scala 597:42] + wire bitmanip_legal : UInt<1> + bitmanip_legal <= UInt<1>("h00") + node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 590:40] + node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 590:51] + node _T_546 = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 590:37] + node i0_legal = and(_T_546, bitmanip_legal) @[dec_decode_ctl.scala 590:73] + wire _T_547 : UInt<1>[16] @[lib.scala 12:48] + _T_547[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_547[15] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_548 = cat(_T_547[0], _T_547[1]) @[Cat.scala 29:58] + node _T_549 = cat(_T_548, _T_547[2]) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_547[3]) @[Cat.scala 29:58] + node _T_551 = cat(_T_550, _T_547[4]) @[Cat.scala 29:58] + node _T_552 = cat(_T_551, _T_547[5]) @[Cat.scala 29:58] + node _T_553 = cat(_T_552, _T_547[6]) @[Cat.scala 29:58] + node _T_554 = cat(_T_553, _T_547[7]) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547[8]) @[Cat.scala 29:58] + node _T_556 = cat(_T_555, _T_547[9]) @[Cat.scala 29:58] + node _T_557 = cat(_T_556, _T_547[10]) @[Cat.scala 29:58] + node _T_558 = cat(_T_557, _T_547[11]) @[Cat.scala 29:58] + node _T_559 = cat(_T_558, _T_547[12]) @[Cat.scala 29:58] + node _T_560 = cat(_T_559, _T_547[13]) @[Cat.scala 29:58] + node _T_561 = cat(_T_560, _T_547[14]) @[Cat.scala 29:58] + node _T_562 = cat(_T_561, _T_547[15]) @[Cat.scala 29:58] + node _T_563 = cat(_T_562, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_563) @[dec_decode_ctl.scala 591:27] + node _T_564 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 594:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_564) @[dec_decode_ctl.scala 594:47] + node _T_565 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 595:44] + node illegal_inst_en = and(shift_illegal, _T_565) @[dec_decode_ctl.scala 595:42] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] rvclkhdr_3.io.en <= illegal_inst_en @[lib.scala 407:17] rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] - reg _T_565 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_566 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when illegal_inst_en : @[Reg.scala 28:19] - _T_565 <= i0_inst_d @[Reg.scala 28:23] + _T_566 <= i0_inst_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_illegal_inst <= _T_565 @[dec_decode_ctl.scala 598:23] - node _T_566 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 599:40] - node _T_567 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 599:61] - node _T_568 = and(_T_566, _T_567) @[dec_decode_ctl.scala 599:59] - illegal_lockout_in <= _T_568 @[dec_decode_ctl.scala 599:22] - node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 600:42] - node _T_569 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 602:40] - node _T_570 = or(_T_569, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 602:59] - node _T_571 = or(_T_570, pause_stall) @[dec_decode_ctl.scala 602:92] - node _T_572 = or(_T_571, leak1_i0_stall) @[dec_decode_ctl.scala 602:106] - node _T_573 = or(_T_572, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 603:20] - node _T_574 = or(_T_573, postsync_stall) @[dec_decode_ctl.scala 603:45] - node _T_575 = or(_T_574, presync_stall) @[dec_decode_ctl.scala 603:62] - node _T_576 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 604:19] - node _T_577 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 604:36] - node _T_578 = and(_T_576, _T_577) @[dec_decode_ctl.scala 604:34] - node _T_579 = or(_T_575, _T_578) @[dec_decode_ctl.scala 603:79] - node _T_580 = or(_T_579, i0_nonblock_load_stall) @[dec_decode_ctl.scala 604:47] - node _T_581 = or(_T_580, i0_load_block_d) @[dec_decode_ctl.scala 604:72] - node _T_582 = or(_T_581, i0_nonblock_div_stall) @[dec_decode_ctl.scala 605:21] - node i0_block_raw_d = or(_T_582, i0_div_prior_div_stall) @[dec_decode_ctl.scala 605:45] - node _T_583 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 607:65] - node i0_store_stall_d = and(i0_dp.store, _T_583) @[dec_decode_ctl.scala 607:39] - node _T_584 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 608:63] - node i0_load_stall_d = and(i0_dp.load, _T_584) @[dec_decode_ctl.scala 608:38] - node _T_585 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 609:38] - node i0_block_d = or(_T_585, i0_load_stall_d) @[dec_decode_ctl.scala 609:57] - node _T_586 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 613:46] - node _T_587 = and(io.dec_ib0_valid_d, _T_586) @[dec_decode_ctl.scala 613:44] - node _T_588 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 613:63] - node _T_589 = and(_T_587, _T_588) @[dec_decode_ctl.scala 613:61] - node _T_590 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 613:91] - node _T_591 = and(_T_589, _T_590) @[dec_decode_ctl.scala 613:89] - io.dec_i0_decode_d <= _T_591 @[dec_decode_ctl.scala 613:22] - node _T_592 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 614:46] - node _T_593 = and(io.dec_ib0_valid_d, _T_592) @[dec_decode_ctl.scala 614:44] - node _T_594 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 614:63] - node _T_595 = and(_T_593, _T_594) @[dec_decode_ctl.scala 614:61] - node _T_596 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 614:91] - node i0_exudecode_d = and(_T_595, _T_596) @[dec_decode_ctl.scala 614:89] - node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 615:46] - io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[dec_decode_ctl.scala 618:28] - node _T_597 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 619:51] - node _T_598 = and(io.dec_ib0_valid_d, _T_597) @[dec_decode_ctl.scala 619:49] - io.dec_pmu_decode_stall <= _T_598 @[dec_decode_ctl.scala 619:27] - node _T_599 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 620:47] - node _T_600 = and(_T_599, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 620:54] - io.dec_pmu_postsync_stall <= _T_600 @[dec_decode_ctl.scala 620:29] - node _T_601 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 621:46] - node _T_602 = and(_T_601, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 621:53] - io.dec_pmu_presync_stall <= _T_602 @[dec_decode_ctl.scala 621:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 625:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 626:31] - node _T_603 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 628:37] - presync_stall <= _T_603 @[dec_decode_ctl.scala 628:22] - node _T_604 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 630:56] - node _T_605 = or(i0_postsync, _T_604) @[dec_decode_ctl.scala 630:54] - node _T_606 = and(io.dec_i0_decode_d, _T_605) @[dec_decode_ctl.scala 630:39] - node _T_607 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 630:88] - node _T_608 = or(_T_606, _T_607) @[dec_decode_ctl.scala 630:69] - ps_stall_in <= _T_608 @[dec_decode_ctl.scala 630:15] - node _T_609 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 632:58] - io.dec_alu.dec_i0_alu_decode_d <= _T_609 @[dec_decode_ctl.scala 632:34] - node _T_610 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 633:53] - node _T_611 = or(_T_610, i0_br_error_all) @[dec_decode_ctl.scala 633:65] - io.decode_exu.dec_i0_branch_d <= _T_611 @[dec_decode_ctl.scala 633:37] - node _T_612 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 635:40] - lsu_decode_d <= _T_612 @[dec_decode_ctl.scala 635:16] - node _T_613 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 636:40] - mul_decode_d <= _T_613 @[dec_decode_ctl.scala 636:16] - node _T_614 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 637:40] - div_decode_d <= _T_614 @[dec_decode_ctl.scala 637:16] - io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 638:32] - node _T_615 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 639:45] - node _T_616 = and(r_d.valid, _T_615) @[dec_decode_ctl.scala 639:43] - io.dec_tlu_i0_valid_r <= _T_616 @[dec_decode_ctl.scala 639:29] - d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 642:26] - node _T_617 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:40] - d_t.icaf <= _T_617 @[dec_decode_ctl.scala 643:26] - node _T_618 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 644:58] - d_t.icaf_second <= _T_618 @[dec_decode_ctl.scala 644:30] - d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 645:26] - node _T_619 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 647:44] - node _T_620 = and(_T_619, i0_legal_decode_d) @[dec_decode_ctl.scala 647:61] - d_t.fence_i <= _T_620 @[dec_decode_ctl.scala 647:26] - d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 650:26] - d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 651:26] - d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 652:26] - wire _T_621 : UInt<1>[4] @[lib.scala 12:48] - _T_621[0] <= io.dec_i0_decode_d @[lib.scala 12:48] - _T_621[1] <= io.dec_i0_decode_d @[lib.scala 12:48] - _T_621[2] <= io.dec_i0_decode_d @[lib.scala 12:48] - _T_621[3] <= io.dec_i0_decode_d @[lib.scala 12:48] - node _T_622 = cat(_T_621[0], _T_621[1]) @[Cat.scala 29:58] - node _T_623 = cat(_T_622, _T_621[2]) @[Cat.scala 29:58] - node _T_624 = cat(_T_623, _T_621[3]) @[Cat.scala 29:58] - node _T_625 = and(io.dec_i0_trigger_match_d, _T_624) @[dec_decode_ctl.scala 654:56] - d_t.i0trigger <= _T_625 @[dec_decode_ctl.scala 654:26] - node _T_626 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 657:60] - wire _T_627 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] - _T_627.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] - _T_627.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] - _T_627.fence_i <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] - _T_627.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.icaf <= UInt<1>("h00") @[lib.scala 630:37] - _T_627.legal <= UInt<1>("h00") @[lib.scala 630:37] - reg _T_628 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_627)) @[Reg.scala 27:20] - when _T_626 : @[Reg.scala 28:19] - _T_628.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[Reg.scala 28:23] - _T_628.pmu_divide <= d_t.pmu_divide @[Reg.scala 28:23] - _T_628.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[Reg.scala 28:23] - _T_628.pmu_i0_itype <= d_t.pmu_i0_itype @[Reg.scala 28:23] - _T_628.i0trigger <= d_t.i0trigger @[Reg.scala 28:23] - _T_628.fence_i <= d_t.fence_i @[Reg.scala 28:23] - _T_628.icaf_type <= d_t.icaf_type @[Reg.scala 28:23] - _T_628.icaf_second <= d_t.icaf_second @[Reg.scala 28:23] - _T_628.icaf <= d_t.icaf @[Reg.scala 28:23] - _T_628.legal <= d_t.legal @[Reg.scala 28:23] + io.dec_illegal_inst <= _T_566 @[dec_decode_ctl.scala 596:23] + node _T_567 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 597:40] + node _T_568 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 597:61] + node _T_569 = and(_T_567, _T_568) @[dec_decode_ctl.scala 597:59] + illegal_lockout_in <= _T_569 @[dec_decode_ctl.scala 597:22] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 598:42] + node _T_570 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 600:40] + node _T_571 = or(_T_570, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 600:59] + node _T_572 = or(_T_571, pause_stall) @[dec_decode_ctl.scala 600:92] + node _T_573 = or(_T_572, leak1_i0_stall) @[dec_decode_ctl.scala 600:106] + node _T_574 = or(_T_573, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 601:20] + node _T_575 = or(_T_574, postsync_stall) @[dec_decode_ctl.scala 601:45] + node _T_576 = or(_T_575, presync_stall) @[dec_decode_ctl.scala 601:62] + node _T_577 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 602:19] + node _T_578 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 602:36] + node _T_579 = and(_T_577, _T_578) @[dec_decode_ctl.scala 602:34] + node _T_580 = or(_T_576, _T_579) @[dec_decode_ctl.scala 601:79] + node _T_581 = or(_T_580, i0_nonblock_load_stall) @[dec_decode_ctl.scala 602:47] + node _T_582 = or(_T_581, i0_load_block_d) @[dec_decode_ctl.scala 602:72] + node _T_583 = or(_T_582, i0_nonblock_div_stall) @[dec_decode_ctl.scala 603:21] + node i0_block_raw_d = or(_T_583, i0_div_prior_div_stall) @[dec_decode_ctl.scala 603:45] + node _T_584 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 605:65] + node i0_store_stall_d = and(i0_dp.store, _T_584) @[dec_decode_ctl.scala 605:39] + node _T_585 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 606:63] + node i0_load_stall_d = and(i0_dp.load, _T_585) @[dec_decode_ctl.scala 606:38] + node _T_586 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 607:38] + node i0_block_d = or(_T_586, i0_load_stall_d) @[dec_decode_ctl.scala 607:57] + node _T_587 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 611:46] + node _T_588 = and(io.dec_ib0_valid_d, _T_587) @[dec_decode_ctl.scala 611:44] + node _T_589 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:63] + node _T_590 = and(_T_588, _T_589) @[dec_decode_ctl.scala 611:61] + node _T_591 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:91] + node _T_592 = and(_T_590, _T_591) @[dec_decode_ctl.scala 611:89] + io.dec_i0_decode_d <= _T_592 @[dec_decode_ctl.scala 611:22] + node _T_593 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 612:46] + node _T_594 = and(io.dec_ib0_valid_d, _T_593) @[dec_decode_ctl.scala 612:44] + node _T_595 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:63] + node _T_596 = and(_T_594, _T_595) @[dec_decode_ctl.scala 612:61] + node _T_597 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:91] + node i0_exudecode_d = and(_T_596, _T_597) @[dec_decode_ctl.scala 612:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 613:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[dec_decode_ctl.scala 616:28] + node _T_598 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 617:51] + node _T_599 = and(io.dec_ib0_valid_d, _T_598) @[dec_decode_ctl.scala 617:49] + io.dec_pmu_decode_stall <= _T_599 @[dec_decode_ctl.scala 617:27] + node _T_600 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 618:47] + node _T_601 = and(_T_600, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 618:54] + io.dec_pmu_postsync_stall <= _T_601 @[dec_decode_ctl.scala 618:29] + node _T_602 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 619:46] + node _T_603 = and(_T_602, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 619:53] + io.dec_pmu_presync_stall <= _T_603 @[dec_decode_ctl.scala 619:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 623:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 624:31] + node _T_604 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 626:37] + presync_stall <= _T_604 @[dec_decode_ctl.scala 626:22] + node _T_605 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 628:56] + node _T_606 = or(i0_postsync, _T_605) @[dec_decode_ctl.scala 628:54] + node _T_607 = and(io.dec_i0_decode_d, _T_606) @[dec_decode_ctl.scala 628:39] + node _T_608 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 628:88] + node _T_609 = or(_T_607, _T_608) @[dec_decode_ctl.scala 628:69] + ps_stall_in <= _T_609 @[dec_decode_ctl.scala 628:15] + node _T_610 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 630:58] + io.dec_alu.dec_i0_alu_decode_d <= _T_610 @[dec_decode_ctl.scala 630:34] + node _T_611 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 631:53] + node _T_612 = or(_T_611, i0_br_error_all) @[dec_decode_ctl.scala 631:65] + io.decode_exu.dec_i0_branch_d <= _T_612 @[dec_decode_ctl.scala 631:37] + node _T_613 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 633:40] + lsu_decode_d <= _T_613 @[dec_decode_ctl.scala 633:16] + node _T_614 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 634:40] + mul_decode_d <= _T_614 @[dec_decode_ctl.scala 634:16] + node _T_615 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 635:40] + div_decode_d <= _T_615 @[dec_decode_ctl.scala 635:16] + io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 636:32] + node _T_616 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 637:45] + node _T_617 = and(r_d.valid, _T_616) @[dec_decode_ctl.scala 637:43] + io.dec_tlu_i0_valid_r <= _T_617 @[dec_decode_ctl.scala 637:29] + d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 640:26] + node _T_618 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 641:40] + d_t.icaf <= _T_618 @[dec_decode_ctl.scala 641:26] + node _T_619 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 642:58] + d_t.icaf_second <= _T_619 @[dec_decode_ctl.scala 642:30] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 643:26] + node _T_620 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 645:44] + node _T_621 = and(_T_620, i0_legal_decode_d) @[dec_decode_ctl.scala 645:61] + d_t.fence_i <= _T_621 @[dec_decode_ctl.scala 645:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 648:26] + d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 649:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 650:26] + wire _T_622 : UInt<1>[4] @[lib.scala 12:48] + _T_622[0] <= io.dec_i0_decode_d @[lib.scala 12:48] + _T_622[1] <= io.dec_i0_decode_d @[lib.scala 12:48] + _T_622[2] <= io.dec_i0_decode_d @[lib.scala 12:48] + _T_622[3] <= io.dec_i0_decode_d @[lib.scala 12:48] + node _T_623 = cat(_T_622[0], _T_622[1]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_622[2]) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_622[3]) @[Cat.scala 29:58] + node _T_626 = and(io.dec_i0_trigger_match_d, _T_625) @[dec_decode_ctl.scala 652:56] + d_t.i0trigger <= _T_626 @[dec_decode_ctl.scala 652:26] + node _T_627 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 655:60] + wire _T_628 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_628.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_628.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_628.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_628.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_628.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_629 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_628)) @[Reg.scala 27:20] + when _T_627 : @[Reg.scala 28:19] + _T_629.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_629.pmu_divide <= d_t.pmu_divide @[Reg.scala 28:23] + _T_629.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_629.pmu_i0_itype <= d_t.pmu_i0_itype @[Reg.scala 28:23] + _T_629.i0trigger <= d_t.i0trigger @[Reg.scala 28:23] + _T_629.fence_i <= d_t.fence_i @[Reg.scala 28:23] + _T_629.icaf_type <= d_t.icaf_type @[Reg.scala 28:23] + _T_629.icaf_second <= d_t.icaf_second @[Reg.scala 28:23] + _T_629.icaf <= d_t.icaf @[Reg.scala 28:23] + _T_629.legal <= d_t.legal @[Reg.scala 28:23] skip @[Reg.scala 28:19] - x_t.pmu_lsu_misaligned <= _T_628.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:7] - x_t.pmu_divide <= _T_628.pmu_divide @[dec_decode_ctl.scala 657:7] - x_t.pmu_i0_br_unpred <= _T_628.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:7] - x_t.pmu_i0_itype <= _T_628.pmu_i0_itype @[dec_decode_ctl.scala 657:7] - x_t.i0trigger <= _T_628.i0trigger @[dec_decode_ctl.scala 657:7] - x_t.fence_i <= _T_628.fence_i @[dec_decode_ctl.scala 657:7] - x_t.icaf_type <= _T_628.icaf_type @[dec_decode_ctl.scala 657:7] - x_t.icaf_second <= _T_628.icaf_second @[dec_decode_ctl.scala 657:7] - x_t.icaf <= _T_628.icaf @[dec_decode_ctl.scala 657:7] - x_t.legal <= _T_628.legal @[dec_decode_ctl.scala 657:7] - x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 659:10] - x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 659:10] - x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 659:10] - x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 659:10] - x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 659:10] - x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 659:10] - x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 659:10] - x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 659:10] - x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 659:10] - x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 659:10] - wire _T_629 : UInt<1>[4] @[lib.scala 12:48] - _T_629[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] - _T_629[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] - _T_629[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] - _T_629[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] - node _T_630 = cat(_T_629[0], _T_629[1]) @[Cat.scala 29:58] - node _T_631 = cat(_T_630, _T_629[2]) @[Cat.scala 29:58] - node _T_632 = cat(_T_631, _T_629[3]) @[Cat.scala 29:58] - node _T_633 = not(_T_632) @[dec_decode_ctl.scala 660:39] - node _T_634 = and(x_t.i0trigger, _T_633) @[dec_decode_ctl.scala 660:37] - x_t_in.i0trigger <= _T_634 @[dec_decode_ctl.scala 660:20] - node _T_635 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:63] - wire _T_636 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] - _T_636.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] - _T_636.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] - _T_636.fence_i <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] - _T_636.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.icaf <= UInt<1>("h00") @[lib.scala 630:37] - _T_636.legal <= UInt<1>("h00") @[lib.scala 630:37] - reg _T_637 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_636)) @[Reg.scala 27:20] - when _T_635 : @[Reg.scala 28:19] - _T_637.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[Reg.scala 28:23] - _T_637.pmu_divide <= x_t_in.pmu_divide @[Reg.scala 28:23] - _T_637.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[Reg.scala 28:23] - _T_637.pmu_i0_itype <= x_t_in.pmu_i0_itype @[Reg.scala 28:23] - _T_637.i0trigger <= x_t_in.i0trigger @[Reg.scala 28:23] - _T_637.fence_i <= x_t_in.fence_i @[Reg.scala 28:23] - _T_637.icaf_type <= x_t_in.icaf_type @[Reg.scala 28:23] - _T_637.icaf_second <= x_t_in.icaf_second @[Reg.scala 28:23] - _T_637.icaf <= x_t_in.icaf @[Reg.scala 28:23] - _T_637.legal <= x_t_in.legal @[Reg.scala 28:23] + x_t.pmu_lsu_misaligned <= _T_629.pmu_lsu_misaligned @[dec_decode_ctl.scala 655:7] + x_t.pmu_divide <= _T_629.pmu_divide @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_br_unpred <= _T_629.pmu_i0_br_unpred @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_itype <= _T_629.pmu_i0_itype @[dec_decode_ctl.scala 655:7] + x_t.i0trigger <= _T_629.i0trigger @[dec_decode_ctl.scala 655:7] + x_t.fence_i <= _T_629.fence_i @[dec_decode_ctl.scala 655:7] + x_t.icaf_type <= _T_629.icaf_type @[dec_decode_ctl.scala 655:7] + x_t.icaf_second <= _T_629.icaf_second @[dec_decode_ctl.scala 655:7] + x_t.icaf <= _T_629.icaf @[dec_decode_ctl.scala 655:7] + x_t.legal <= _T_629.legal @[dec_decode_ctl.scala 655:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 657:10] + x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 657:10] + x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 657:10] + x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 657:10] + x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 657:10] + wire _T_630 : UInt<1>[4] @[lib.scala 12:48] + _T_630[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_630[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_630[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_630[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + node _T_631 = cat(_T_630[0], _T_630[1]) @[Cat.scala 29:58] + node _T_632 = cat(_T_631, _T_630[2]) @[Cat.scala 29:58] + node _T_633 = cat(_T_632, _T_630[3]) @[Cat.scala 29:58] + node _T_634 = not(_T_633) @[dec_decode_ctl.scala 658:39] + node _T_635 = and(x_t.i0trigger, _T_634) @[dec_decode_ctl.scala 658:37] + x_t_in.i0trigger <= _T_635 @[dec_decode_ctl.scala 658:20] + node _T_636 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 660:63] + wire _T_637 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_637.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_637.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_637.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_637.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_637.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_638 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_637)) @[Reg.scala 27:20] + when _T_636 : @[Reg.scala 28:19] + _T_638.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_638.pmu_divide <= x_t_in.pmu_divide @[Reg.scala 28:23] + _T_638.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_638.pmu_i0_itype <= x_t_in.pmu_i0_itype @[Reg.scala 28:23] + _T_638.i0trigger <= x_t_in.i0trigger @[Reg.scala 28:23] + _T_638.fence_i <= x_t_in.fence_i @[Reg.scala 28:23] + _T_638.icaf_type <= x_t_in.icaf_type @[Reg.scala 28:23] + _T_638.icaf_second <= x_t_in.icaf_second @[Reg.scala 28:23] + _T_638.icaf <= x_t_in.icaf @[Reg.scala 28:23] + _T_638.legal <= x_t_in.legal @[Reg.scala 28:23] skip @[Reg.scala 28:19] - r_t.pmu_lsu_misaligned <= _T_637.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:7] - r_t.pmu_divide <= _T_637.pmu_divide @[dec_decode_ctl.scala 662:7] - r_t.pmu_i0_br_unpred <= _T_637.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:7] - r_t.pmu_i0_itype <= _T_637.pmu_i0_itype @[dec_decode_ctl.scala 662:7] - r_t.i0trigger <= _T_637.i0trigger @[dec_decode_ctl.scala 662:7] - r_t.fence_i <= _T_637.fence_i @[dec_decode_ctl.scala 662:7] - r_t.icaf_type <= _T_637.icaf_type @[dec_decode_ctl.scala 662:7] - r_t.icaf_second <= _T_637.icaf_second @[dec_decode_ctl.scala 662:7] - r_t.icaf <= _T_637.icaf @[dec_decode_ctl.scala 662:7] - r_t.legal <= _T_637.legal @[dec_decode_ctl.scala 662:7] - r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 664:10] - r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 664:10] - r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 664:10] - r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 664:10] - r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 664:10] - r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 664:10] - r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 664:10] - r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 664:10] - r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 664:10] - r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 664:10] - node _T_638 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 666:61] - wire _T_639 : UInt<1>[4] @[lib.scala 12:48] - _T_639[0] <= _T_638 @[lib.scala 12:48] - _T_639[1] <= _T_638 @[lib.scala 12:48] - _T_639[2] <= _T_638 @[lib.scala 12:48] - _T_639[3] <= _T_638 @[lib.scala 12:48] - node _T_640 = cat(_T_639[0], _T_639[1]) @[Cat.scala 29:58] - node _T_641 = cat(_T_640, _T_639[2]) @[Cat.scala 29:58] - node _T_642 = cat(_T_641, _T_639[3]) @[Cat.scala 29:58] - node _T_643 = and(_T_642, lsu_trigger_match_r) @[dec_decode_ctl.scala 666:82] - node _T_644 = or(_T_643, r_t.i0trigger) @[dec_decode_ctl.scala 666:105] - r_t_in.i0trigger <= _T_644 @[dec_decode_ctl.scala 666:33] - r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 667:33] - node _T_645 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 669:35] - when _T_645 : @[dec_decode_ctl.scala 669:43] - wire _T_646 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 669:66] - _T_646.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - _T_646.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 669:66] - r_t_in.pmu_lsu_misaligned <= _T_646.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:51] - r_t_in.pmu_divide <= _T_646.pmu_divide @[dec_decode_ctl.scala 669:51] - r_t_in.pmu_i0_br_unpred <= _T_646.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:51] - r_t_in.pmu_i0_itype <= _T_646.pmu_i0_itype @[dec_decode_ctl.scala 669:51] - r_t_in.i0trigger <= _T_646.i0trigger @[dec_decode_ctl.scala 669:51] - r_t_in.fence_i <= _T_646.fence_i @[dec_decode_ctl.scala 669:51] - r_t_in.icaf_type <= _T_646.icaf_type @[dec_decode_ctl.scala 669:51] - r_t_in.icaf_second <= _T_646.icaf_second @[dec_decode_ctl.scala 669:51] - r_t_in.icaf <= _T_646.icaf @[dec_decode_ctl.scala 669:51] - r_t_in.legal <= _T_646.legal @[dec_decode_ctl.scala 669:51] - skip @[dec_decode_ctl.scala 669:43] - io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 671:39] - io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 671:39] - node _T_647 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 672:58] - io.dec_tlu_packet_r.pmu_divide <= _T_647 @[dec_decode_ctl.scala 672:39] - node _T_648 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 676:46] - node _T_649 = and(io.dec_ib0_valid_d, _T_648) @[dec_decode_ctl.scala 676:44] - node _T_650 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 676:60] - node _T_651 = and(_T_649, _T_650) @[dec_decode_ctl.scala 676:58] - node _T_652 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 676:88] - node _T_653 = and(_T_651, _T_652) @[dec_decode_ctl.scala 676:86] - io.dec_i0_decode_d <= _T_653 @[dec_decode_ctl.scala 676:22] - node _T_654 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 678:16] - i0r.rs1 <= _T_654 @[dec_decode_ctl.scala 678:11] - node _T_655 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 679:16] - i0r.rs2 <= _T_655 @[dec_decode_ctl.scala 679:11] - node _T_656 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 680:16] - i0r.rd <= _T_656 @[dec_decode_ctl.scala 680:11] - node _T_657 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 682:60] - node _T_658 = and(i0_dp.rs1, _T_657) @[dec_decode_ctl.scala 682:49] - io.decode_exu.dec_i0_rs1_en_d <= _T_658 @[dec_decode_ctl.scala 682:35] - node _T_659 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 683:60] - node _T_660 = and(i0_dp.rs2, _T_659) @[dec_decode_ctl.scala 683:49] - io.decode_exu.dec_i0_rs2_en_d <= _T_660 @[dec_decode_ctl.scala 683:35] - node _T_661 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 684:48] - node i0_rd_en_d = and(i0_dp.rd, _T_661) @[dec_decode_ctl.scala 684:37] - io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 685:19] - io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 686:19] - node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 688:38] - node _T_662 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 689:27] - node i0_uiimm20 = and(_T_662, i0_dp.imm20) @[dec_decode_ctl.scala 689:38] - node _T_663 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38] - wire _T_664 : UInt<1>[20] @[lib.scala 12:48] - _T_664[0] <= _T_663 @[lib.scala 12:48] - _T_664[1] <= _T_663 @[lib.scala 12:48] - _T_664[2] <= _T_663 @[lib.scala 12:48] - _T_664[3] <= _T_663 @[lib.scala 12:48] - _T_664[4] <= _T_663 @[lib.scala 12:48] - _T_664[5] <= _T_663 @[lib.scala 12:48] - _T_664[6] <= _T_663 @[lib.scala 12:48] - _T_664[7] <= _T_663 @[lib.scala 12:48] - _T_664[8] <= _T_663 @[lib.scala 12:48] - _T_664[9] <= _T_663 @[lib.scala 12:48] - _T_664[10] <= _T_663 @[lib.scala 12:48] - _T_664[11] <= _T_663 @[lib.scala 12:48] - _T_664[12] <= _T_663 @[lib.scala 12:48] - _T_664[13] <= _T_663 @[lib.scala 12:48] - _T_664[14] <= _T_663 @[lib.scala 12:48] - _T_664[15] <= _T_663 @[lib.scala 12:48] - _T_664[16] <= _T_663 @[lib.scala 12:48] - _T_664[17] <= _T_663 @[lib.scala 12:48] - _T_664[18] <= _T_663 @[lib.scala 12:48] - _T_664[19] <= _T_663 @[lib.scala 12:48] - node _T_665 = cat(_T_664[0], _T_664[1]) @[Cat.scala 29:58] - node _T_666 = cat(_T_665, _T_664[2]) @[Cat.scala 29:58] - node _T_667 = cat(_T_666, _T_664[3]) @[Cat.scala 29:58] - node _T_668 = cat(_T_667, _T_664[4]) @[Cat.scala 29:58] - node _T_669 = cat(_T_668, _T_664[5]) @[Cat.scala 29:58] - node _T_670 = cat(_T_669, _T_664[6]) @[Cat.scala 29:58] - node _T_671 = cat(_T_670, _T_664[7]) @[Cat.scala 29:58] - node _T_672 = cat(_T_671, _T_664[8]) @[Cat.scala 29:58] - node _T_673 = cat(_T_672, _T_664[9]) @[Cat.scala 29:58] - node _T_674 = cat(_T_673, _T_664[10]) @[Cat.scala 29:58] - node _T_675 = cat(_T_674, _T_664[11]) @[Cat.scala 29:58] - node _T_676 = cat(_T_675, _T_664[12]) @[Cat.scala 29:58] - node _T_677 = cat(_T_676, _T_664[13]) @[Cat.scala 29:58] - node _T_678 = cat(_T_677, _T_664[14]) @[Cat.scala 29:58] - node _T_679 = cat(_T_678, _T_664[15]) @[Cat.scala 29:58] - node _T_680 = cat(_T_679, _T_664[16]) @[Cat.scala 29:58] - node _T_681 = cat(_T_680, _T_664[17]) @[Cat.scala 29:58] - node _T_682 = cat(_T_681, _T_664[18]) @[Cat.scala 29:58] - node _T_683 = cat(_T_682, _T_664[19]) @[Cat.scala 29:58] - node _T_684 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 696:46] - node _T_685 = cat(_T_683, _T_684) @[Cat.scala 29:58] - wire _T_686 : UInt<1>[27] @[lib.scala 12:48] - _T_686[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[9] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[10] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[11] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[12] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[13] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[14] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[15] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[16] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[17] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[18] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[19] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[20] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[21] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[22] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[23] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[24] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[25] <= UInt<1>("h00") @[lib.scala 12:48] - _T_686[26] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_687 = cat(_T_686[0], _T_686[1]) @[Cat.scala 29:58] - node _T_688 = cat(_T_687, _T_686[2]) @[Cat.scala 29:58] - node _T_689 = cat(_T_688, _T_686[3]) @[Cat.scala 29:58] - node _T_690 = cat(_T_689, _T_686[4]) @[Cat.scala 29:58] - node _T_691 = cat(_T_690, _T_686[5]) @[Cat.scala 29:58] - node _T_692 = cat(_T_691, _T_686[6]) @[Cat.scala 29:58] - node _T_693 = cat(_T_692, _T_686[7]) @[Cat.scala 29:58] - node _T_694 = cat(_T_693, _T_686[8]) @[Cat.scala 29:58] - node _T_695 = cat(_T_694, _T_686[9]) @[Cat.scala 29:58] - node _T_696 = cat(_T_695, _T_686[10]) @[Cat.scala 29:58] - node _T_697 = cat(_T_696, _T_686[11]) @[Cat.scala 29:58] - node _T_698 = cat(_T_697, _T_686[12]) @[Cat.scala 29:58] - node _T_699 = cat(_T_698, _T_686[13]) @[Cat.scala 29:58] - node _T_700 = cat(_T_699, _T_686[14]) @[Cat.scala 29:58] - node _T_701 = cat(_T_700, _T_686[15]) @[Cat.scala 29:58] - node _T_702 = cat(_T_701, _T_686[16]) @[Cat.scala 29:58] - node _T_703 = cat(_T_702, _T_686[17]) @[Cat.scala 29:58] - node _T_704 = cat(_T_703, _T_686[18]) @[Cat.scala 29:58] - node _T_705 = cat(_T_704, _T_686[19]) @[Cat.scala 29:58] - node _T_706 = cat(_T_705, _T_686[20]) @[Cat.scala 29:58] - node _T_707 = cat(_T_706, _T_686[21]) @[Cat.scala 29:58] - node _T_708 = cat(_T_707, _T_686[22]) @[Cat.scala 29:58] - node _T_709 = cat(_T_708, _T_686[23]) @[Cat.scala 29:58] - node _T_710 = cat(_T_709, _T_686[24]) @[Cat.scala 29:58] - node _T_711 = cat(_T_710, _T_686[25]) @[Cat.scala 29:58] - node _T_712 = cat(_T_711, _T_686[26]) @[Cat.scala 29:58] - node _T_713 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 697:43] - node _T_714 = cat(_T_712, _T_713) @[Cat.scala 29:58] - node _T_715 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 698:38] - wire _T_716 : UInt<1>[12] @[lib.scala 12:48] - _T_716[0] <= _T_715 @[lib.scala 12:48] - _T_716[1] <= _T_715 @[lib.scala 12:48] - _T_716[2] <= _T_715 @[lib.scala 12:48] - _T_716[3] <= _T_715 @[lib.scala 12:48] - _T_716[4] <= _T_715 @[lib.scala 12:48] - _T_716[5] <= _T_715 @[lib.scala 12:48] - _T_716[6] <= _T_715 @[lib.scala 12:48] - _T_716[7] <= _T_715 @[lib.scala 12:48] - _T_716[8] <= _T_715 @[lib.scala 12:48] - _T_716[9] <= _T_715 @[lib.scala 12:48] - _T_716[10] <= _T_715 @[lib.scala 12:48] - _T_716[11] <= _T_715 @[lib.scala 12:48] - node _T_717 = cat(_T_716[0], _T_716[1]) @[Cat.scala 29:58] - node _T_718 = cat(_T_717, _T_716[2]) @[Cat.scala 29:58] - node _T_719 = cat(_T_718, _T_716[3]) @[Cat.scala 29:58] - node _T_720 = cat(_T_719, _T_716[4]) @[Cat.scala 29:58] - node _T_721 = cat(_T_720, _T_716[5]) @[Cat.scala 29:58] - node _T_722 = cat(_T_721, _T_716[6]) @[Cat.scala 29:58] - node _T_723 = cat(_T_722, _T_716[7]) @[Cat.scala 29:58] - node _T_724 = cat(_T_723, _T_716[8]) @[Cat.scala 29:58] - node _T_725 = cat(_T_724, _T_716[9]) @[Cat.scala 29:58] - node _T_726 = cat(_T_725, _T_716[10]) @[Cat.scala 29:58] - node _T_727 = cat(_T_726, _T_716[11]) @[Cat.scala 29:58] - node _T_728 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 698:46] - node _T_729 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 698:56] - node _T_730 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 698:63] - node _T_731 = cat(_T_730, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_732 = cat(_T_727, _T_728) @[Cat.scala 29:58] - node _T_733 = cat(_T_732, _T_729) @[Cat.scala 29:58] - node _T_734 = cat(_T_733, _T_731) @[Cat.scala 29:58] - node _T_735 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 699:30] - wire _T_736 : UInt<1>[12] @[lib.scala 12:48] - _T_736[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[9] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[10] <= UInt<1>("h00") @[lib.scala 12:48] - _T_736[11] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_737 = cat(_T_736[0], _T_736[1]) @[Cat.scala 29:58] - node _T_738 = cat(_T_737, _T_736[2]) @[Cat.scala 29:58] - node _T_739 = cat(_T_738, _T_736[3]) @[Cat.scala 29:58] - node _T_740 = cat(_T_739, _T_736[4]) @[Cat.scala 29:58] - node _T_741 = cat(_T_740, _T_736[5]) @[Cat.scala 29:58] - node _T_742 = cat(_T_741, _T_736[6]) @[Cat.scala 29:58] - node _T_743 = cat(_T_742, _T_736[7]) @[Cat.scala 29:58] - node _T_744 = cat(_T_743, _T_736[8]) @[Cat.scala 29:58] - node _T_745 = cat(_T_744, _T_736[9]) @[Cat.scala 29:58] - node _T_746 = cat(_T_745, _T_736[10]) @[Cat.scala 29:58] - node _T_747 = cat(_T_746, _T_736[11]) @[Cat.scala 29:58] - node _T_748 = cat(_T_735, _T_747) @[Cat.scala 29:58] - node _T_749 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 700:26] - node _T_750 = bits(_T_749, 0, 0) @[dec_decode_ctl.scala 700:43] - wire _T_751 : UInt<1>[27] @[lib.scala 12:48] - _T_751[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[9] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[10] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[11] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[12] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[13] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[14] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[15] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[16] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[17] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[18] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[19] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[20] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[21] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[22] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[23] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[24] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[25] <= UInt<1>("h00") @[lib.scala 12:48] - _T_751[26] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_752 = cat(_T_751[0], _T_751[1]) @[Cat.scala 29:58] - node _T_753 = cat(_T_752, _T_751[2]) @[Cat.scala 29:58] - node _T_754 = cat(_T_753, _T_751[3]) @[Cat.scala 29:58] - node _T_755 = cat(_T_754, _T_751[4]) @[Cat.scala 29:58] - node _T_756 = cat(_T_755, _T_751[5]) @[Cat.scala 29:58] - node _T_757 = cat(_T_756, _T_751[6]) @[Cat.scala 29:58] - node _T_758 = cat(_T_757, _T_751[7]) @[Cat.scala 29:58] - node _T_759 = cat(_T_758, _T_751[8]) @[Cat.scala 29:58] - node _T_760 = cat(_T_759, _T_751[9]) @[Cat.scala 29:58] - node _T_761 = cat(_T_760, _T_751[10]) @[Cat.scala 29:58] - node _T_762 = cat(_T_761, _T_751[11]) @[Cat.scala 29:58] - node _T_763 = cat(_T_762, _T_751[12]) @[Cat.scala 29:58] - node _T_764 = cat(_T_763, _T_751[13]) @[Cat.scala 29:58] - node _T_765 = cat(_T_764, _T_751[14]) @[Cat.scala 29:58] - node _T_766 = cat(_T_765, _T_751[15]) @[Cat.scala 29:58] - node _T_767 = cat(_T_766, _T_751[16]) @[Cat.scala 29:58] - node _T_768 = cat(_T_767, _T_751[17]) @[Cat.scala 29:58] - node _T_769 = cat(_T_768, _T_751[18]) @[Cat.scala 29:58] - node _T_770 = cat(_T_769, _T_751[19]) @[Cat.scala 29:58] - node _T_771 = cat(_T_770, _T_751[20]) @[Cat.scala 29:58] - node _T_772 = cat(_T_771, _T_751[21]) @[Cat.scala 29:58] - node _T_773 = cat(_T_772, _T_751[22]) @[Cat.scala 29:58] - node _T_774 = cat(_T_773, _T_751[23]) @[Cat.scala 29:58] - node _T_775 = cat(_T_774, _T_751[24]) @[Cat.scala 29:58] - node _T_776 = cat(_T_775, _T_751[25]) @[Cat.scala 29:58] - node _T_777 = cat(_T_776, _T_751[26]) @[Cat.scala 29:58] - node _T_778 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 700:72] - node _T_779 = cat(_T_777, _T_778) @[Cat.scala 29:58] - node _T_780 = mux(i0_dp.imm12, _T_685, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_781 = mux(i0_dp.shimm5, _T_714, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_782 = mux(i0_jalimm20, _T_734, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_783 = mux(i0_uiimm20, _T_748, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_784 = mux(_T_750, _T_779, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_785 = or(_T_780, _T_781) @[Mux.scala 27:72] - node _T_786 = or(_T_785, _T_782) @[Mux.scala 27:72] + r_t.pmu_lsu_misaligned <= _T_638.pmu_lsu_misaligned @[dec_decode_ctl.scala 660:7] + r_t.pmu_divide <= _T_638.pmu_divide @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_br_unpred <= _T_638.pmu_i0_br_unpred @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_itype <= _T_638.pmu_i0_itype @[dec_decode_ctl.scala 660:7] + r_t.i0trigger <= _T_638.i0trigger @[dec_decode_ctl.scala 660:7] + r_t.fence_i <= _T_638.fence_i @[dec_decode_ctl.scala 660:7] + r_t.icaf_type <= _T_638.icaf_type @[dec_decode_ctl.scala 660:7] + r_t.icaf_second <= _T_638.icaf_second @[dec_decode_ctl.scala 660:7] + r_t.icaf <= _T_638.icaf @[dec_decode_ctl.scala 660:7] + r_t.legal <= _T_638.legal @[dec_decode_ctl.scala 660:7] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 662:10] + r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 662:10] + r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 662:10] + r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 662:10] + r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 662:10] + node _T_639 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 664:61] + wire _T_640 : UInt<1>[4] @[lib.scala 12:48] + _T_640[0] <= _T_639 @[lib.scala 12:48] + _T_640[1] <= _T_639 @[lib.scala 12:48] + _T_640[2] <= _T_639 @[lib.scala 12:48] + _T_640[3] <= _T_639 @[lib.scala 12:48] + node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58] + node _T_644 = and(_T_643, lsu_trigger_match_r) @[dec_decode_ctl.scala 664:82] + node _T_645 = or(_T_644, r_t.i0trigger) @[dec_decode_ctl.scala 664:105] + r_t_in.i0trigger <= _T_645 @[dec_decode_ctl.scala 664:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 665:33] + node _T_646 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 667:35] + when _T_646 : @[dec_decode_ctl.scala 667:43] + wire _T_647 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 667:66] + _T_647.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_647.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + r_t_in.pmu_lsu_misaligned <= _T_647.pmu_lsu_misaligned @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_divide <= _T_647.pmu_divide @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_br_unpred <= _T_647.pmu_i0_br_unpred @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_itype <= _T_647.pmu_i0_itype @[dec_decode_ctl.scala 667:51] + r_t_in.i0trigger <= _T_647.i0trigger @[dec_decode_ctl.scala 667:51] + r_t_in.fence_i <= _T_647.fence_i @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_type <= _T_647.icaf_type @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_second <= _T_647.icaf_second @[dec_decode_ctl.scala 667:51] + r_t_in.icaf <= _T_647.icaf @[dec_decode_ctl.scala 667:51] + r_t_in.legal <= _T_647.legal @[dec_decode_ctl.scala 667:51] + skip @[dec_decode_ctl.scala 667:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 669:39] + node _T_648 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 670:58] + io.dec_tlu_packet_r.pmu_divide <= _T_648 @[dec_decode_ctl.scala 670:39] + node _T_649 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 674:46] + node _T_650 = and(io.dec_ib0_valid_d, _T_649) @[dec_decode_ctl.scala 674:44] + node _T_651 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:60] + node _T_652 = and(_T_650, _T_651) @[dec_decode_ctl.scala 674:58] + node _T_653 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:88] + node _T_654 = and(_T_652, _T_653) @[dec_decode_ctl.scala 674:86] + io.dec_i0_decode_d <= _T_654 @[dec_decode_ctl.scala 674:22] + node _T_655 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 676:16] + i0r.rs1 <= _T_655 @[dec_decode_ctl.scala 676:11] + node _T_656 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 677:16] + i0r.rs2 <= _T_656 @[dec_decode_ctl.scala 677:11] + node _T_657 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 678:16] + i0r.rd <= _T_657 @[dec_decode_ctl.scala 678:11] + node _T_658 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 680:60] + node _T_659 = and(i0_dp.rs1, _T_658) @[dec_decode_ctl.scala 680:49] + io.decode_exu.dec_i0_rs1_en_d <= _T_659 @[dec_decode_ctl.scala 680:35] + node _T_660 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 681:60] + node _T_661 = and(i0_dp.rs2, _T_660) @[dec_decode_ctl.scala 681:49] + io.decode_exu.dec_i0_rs2_en_d <= _T_661 @[dec_decode_ctl.scala 681:35] + node _T_662 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 682:48] + node i0_rd_en_d = and(i0_dp.rd, _T_662) @[dec_decode_ctl.scala 682:37] + io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 683:19] + io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 684:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 686:38] + node _T_663 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 687:27] + node i0_uiimm20 = and(_T_663, i0_dp.imm20) @[dec_decode_ctl.scala 687:38] + node _T_664 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 694:38] + wire _T_665 : UInt<1>[20] @[lib.scala 12:48] + _T_665[0] <= _T_664 @[lib.scala 12:48] + _T_665[1] <= _T_664 @[lib.scala 12:48] + _T_665[2] <= _T_664 @[lib.scala 12:48] + _T_665[3] <= _T_664 @[lib.scala 12:48] + _T_665[4] <= _T_664 @[lib.scala 12:48] + _T_665[5] <= _T_664 @[lib.scala 12:48] + _T_665[6] <= _T_664 @[lib.scala 12:48] + _T_665[7] <= _T_664 @[lib.scala 12:48] + _T_665[8] <= _T_664 @[lib.scala 12:48] + _T_665[9] <= _T_664 @[lib.scala 12:48] + _T_665[10] <= _T_664 @[lib.scala 12:48] + _T_665[11] <= _T_664 @[lib.scala 12:48] + _T_665[12] <= _T_664 @[lib.scala 12:48] + _T_665[13] <= _T_664 @[lib.scala 12:48] + _T_665[14] <= _T_664 @[lib.scala 12:48] + _T_665[15] <= _T_664 @[lib.scala 12:48] + _T_665[16] <= _T_664 @[lib.scala 12:48] + _T_665[17] <= _T_664 @[lib.scala 12:48] + _T_665[18] <= _T_664 @[lib.scala 12:48] + _T_665[19] <= _T_664 @[lib.scala 12:48] + node _T_666 = cat(_T_665[0], _T_665[1]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_665[2]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_665[3]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_665[4]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_665[5]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_665[6]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_665[7]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_665[8]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_665[9]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_665[10]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_665[11]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_665[12]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_665[13]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_665[14]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_665[15]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_665[16]) @[Cat.scala 29:58] + node _T_682 = cat(_T_681, _T_665[17]) @[Cat.scala 29:58] + node _T_683 = cat(_T_682, _T_665[18]) @[Cat.scala 29:58] + node _T_684 = cat(_T_683, _T_665[19]) @[Cat.scala 29:58] + node _T_685 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 694:46] + node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58] + wire _T_687 : UInt<1>[27] @[lib.scala 12:48] + _T_687[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_687[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_688 = cat(_T_687[0], _T_687[1]) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_687[2]) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_687[3]) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_687[4]) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_687[5]) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_687[6]) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_687[7]) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_687[8]) @[Cat.scala 29:58] + node _T_696 = cat(_T_695, _T_687[9]) @[Cat.scala 29:58] + node _T_697 = cat(_T_696, _T_687[10]) @[Cat.scala 29:58] + node _T_698 = cat(_T_697, _T_687[11]) @[Cat.scala 29:58] + node _T_699 = cat(_T_698, _T_687[12]) @[Cat.scala 29:58] + node _T_700 = cat(_T_699, _T_687[13]) @[Cat.scala 29:58] + node _T_701 = cat(_T_700, _T_687[14]) @[Cat.scala 29:58] + node _T_702 = cat(_T_701, _T_687[15]) @[Cat.scala 29:58] + node _T_703 = cat(_T_702, _T_687[16]) @[Cat.scala 29:58] + node _T_704 = cat(_T_703, _T_687[17]) @[Cat.scala 29:58] + node _T_705 = cat(_T_704, _T_687[18]) @[Cat.scala 29:58] + node _T_706 = cat(_T_705, _T_687[19]) @[Cat.scala 29:58] + node _T_707 = cat(_T_706, _T_687[20]) @[Cat.scala 29:58] + node _T_708 = cat(_T_707, _T_687[21]) @[Cat.scala 29:58] + node _T_709 = cat(_T_708, _T_687[22]) @[Cat.scala 29:58] + node _T_710 = cat(_T_709, _T_687[23]) @[Cat.scala 29:58] + node _T_711 = cat(_T_710, _T_687[24]) @[Cat.scala 29:58] + node _T_712 = cat(_T_711, _T_687[25]) @[Cat.scala 29:58] + node _T_713 = cat(_T_712, _T_687[26]) @[Cat.scala 29:58] + node _T_714 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 695:43] + node _T_715 = cat(_T_713, _T_714) @[Cat.scala 29:58] + node _T_716 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38] + wire _T_717 : UInt<1>[12] @[lib.scala 12:48] + _T_717[0] <= _T_716 @[lib.scala 12:48] + _T_717[1] <= _T_716 @[lib.scala 12:48] + _T_717[2] <= _T_716 @[lib.scala 12:48] + _T_717[3] <= _T_716 @[lib.scala 12:48] + _T_717[4] <= _T_716 @[lib.scala 12:48] + _T_717[5] <= _T_716 @[lib.scala 12:48] + _T_717[6] <= _T_716 @[lib.scala 12:48] + _T_717[7] <= _T_716 @[lib.scala 12:48] + _T_717[8] <= _T_716 @[lib.scala 12:48] + _T_717[9] <= _T_716 @[lib.scala 12:48] + _T_717[10] <= _T_716 @[lib.scala 12:48] + _T_717[11] <= _T_716 @[lib.scala 12:48] + node _T_718 = cat(_T_717[0], _T_717[1]) @[Cat.scala 29:58] + node _T_719 = cat(_T_718, _T_717[2]) @[Cat.scala 29:58] + node _T_720 = cat(_T_719, _T_717[3]) @[Cat.scala 29:58] + node _T_721 = cat(_T_720, _T_717[4]) @[Cat.scala 29:58] + node _T_722 = cat(_T_721, _T_717[5]) @[Cat.scala 29:58] + node _T_723 = cat(_T_722, _T_717[6]) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_717[7]) @[Cat.scala 29:58] + node _T_725 = cat(_T_724, _T_717[8]) @[Cat.scala 29:58] + node _T_726 = cat(_T_725, _T_717[9]) @[Cat.scala 29:58] + node _T_727 = cat(_T_726, _T_717[10]) @[Cat.scala 29:58] + node _T_728 = cat(_T_727, _T_717[11]) @[Cat.scala 29:58] + node _T_729 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 696:46] + node _T_730 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 696:56] + node _T_731 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 696:63] + node _T_732 = cat(_T_731, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_733 = cat(_T_728, _T_729) @[Cat.scala 29:58] + node _T_734 = cat(_T_733, _T_730) @[Cat.scala 29:58] + node _T_735 = cat(_T_734, _T_732) @[Cat.scala 29:58] + node _T_736 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 697:30] + wire _T_737 : UInt<1>[12] @[lib.scala 12:48] + _T_737[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_737[11] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_738 = cat(_T_737[0], _T_737[1]) @[Cat.scala 29:58] + node _T_739 = cat(_T_738, _T_737[2]) @[Cat.scala 29:58] + node _T_740 = cat(_T_739, _T_737[3]) @[Cat.scala 29:58] + node _T_741 = cat(_T_740, _T_737[4]) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_737[5]) @[Cat.scala 29:58] + node _T_743 = cat(_T_742, _T_737[6]) @[Cat.scala 29:58] + node _T_744 = cat(_T_743, _T_737[7]) @[Cat.scala 29:58] + node _T_745 = cat(_T_744, _T_737[8]) @[Cat.scala 29:58] + node _T_746 = cat(_T_745, _T_737[9]) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_737[10]) @[Cat.scala 29:58] + node _T_748 = cat(_T_747, _T_737[11]) @[Cat.scala 29:58] + node _T_749 = cat(_T_736, _T_748) @[Cat.scala 29:58] + node _T_750 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 698:26] + node _T_751 = bits(_T_750, 0, 0) @[dec_decode_ctl.scala 698:43] + wire _T_752 : UInt<1>[27] @[lib.scala 12:48] + _T_752[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_752[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_753 = cat(_T_752[0], _T_752[1]) @[Cat.scala 29:58] + node _T_754 = cat(_T_753, _T_752[2]) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_752[3]) @[Cat.scala 29:58] + node _T_756 = cat(_T_755, _T_752[4]) @[Cat.scala 29:58] + node _T_757 = cat(_T_756, _T_752[5]) @[Cat.scala 29:58] + node _T_758 = cat(_T_757, _T_752[6]) @[Cat.scala 29:58] + node _T_759 = cat(_T_758, _T_752[7]) @[Cat.scala 29:58] + node _T_760 = cat(_T_759, _T_752[8]) @[Cat.scala 29:58] + node _T_761 = cat(_T_760, _T_752[9]) @[Cat.scala 29:58] + node _T_762 = cat(_T_761, _T_752[10]) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_752[11]) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_752[12]) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_752[13]) @[Cat.scala 29:58] + node _T_766 = cat(_T_765, _T_752[14]) @[Cat.scala 29:58] + node _T_767 = cat(_T_766, _T_752[15]) @[Cat.scala 29:58] + node _T_768 = cat(_T_767, _T_752[16]) @[Cat.scala 29:58] + node _T_769 = cat(_T_768, _T_752[17]) @[Cat.scala 29:58] + node _T_770 = cat(_T_769, _T_752[18]) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, _T_752[19]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_752[20]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_752[21]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_752[22]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_752[23]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_752[24]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_752[25]) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, _T_752[26]) @[Cat.scala 29:58] + node _T_779 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 698:72] + node _T_780 = cat(_T_778, _T_779) @[Cat.scala 29:58] + node _T_781 = mux(i0_dp.imm12, _T_686, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_782 = mux(i0_dp.shimm5, _T_715, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_783 = mux(i0_jalimm20, _T_735, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_784 = mux(i0_uiimm20, _T_749, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_785 = mux(_T_751, _T_780, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_786 = or(_T_781, _T_782) @[Mux.scala 27:72] node _T_787 = or(_T_786, _T_783) @[Mux.scala 27:72] node _T_788 = or(_T_787, _T_784) @[Mux.scala 27:72] - wire _T_789 : UInt<32> @[Mux.scala 27:72] - _T_789 <= _T_788 @[Mux.scala 27:72] - io.decode_exu.dec_i0_immed_d <= _T_789 @[dec_decode_ctl.scala 695:32] + node _T_789 = or(_T_788, _T_785) @[Mux.scala 27:72] + wire _T_790 : UInt<32> @[Mux.scala 27:72] + _T_790 <= _T_789 @[Mux.scala 27:72] + io.decode_exu.dec_i0_immed_d <= _T_790 @[dec_decode_ctl.scala 693:32] wire bitmanip_zbb_legal : UInt<1> bitmanip_zbb_legal <= UInt<1>("h00") wire bitmanip_zbs_legal : UInt<1> @@ -7163,640 +7166,638 @@ circuit dec : bitmanip_zba_legal <= UInt<1>("h00") wire bitmanip_zbb_zbp_legal : UInt<1> bitmanip_zbb_zbp_legal <= UInt<1>("h00") - wire bitmanip_legal : UInt<1> - bitmanip_legal <= UInt<1>("h00") - bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 713:29] - bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 718:29] - node _T_790 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 725:32] - bitmanip_zbe_legal <= _T_790 @[dec_decode_ctl.scala 725:29] - node _T_791 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 730:32] - bitmanip_zbc_legal <= _T_791 @[dec_decode_ctl.scala 730:29] - node _T_792 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 735:46] - node _T_793 = and(i0_dp.zbp, _T_792) @[dec_decode_ctl.scala 735:44] - node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_decode_ctl.scala 735:32] - bitmanip_zbp_legal <= _T_794 @[dec_decode_ctl.scala 735:29] - node _T_795 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 740:32] - bitmanip_zbr_legal <= _T_795 @[dec_decode_ctl.scala 740:29] - node _T_796 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 745:32] - bitmanip_zbf_legal <= _T_796 @[dec_decode_ctl.scala 745:29] - node _T_797 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 750:32] - bitmanip_zba_legal <= _T_797 @[dec_decode_ctl.scala 750:29] - bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 753:29] - node _T_798 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 757:41] - node _T_799 = and(_T_798, bitmanip_zbe_legal) @[dec_decode_ctl.scala 757:62] - node _T_800 = and(_T_799, bitmanip_zbc_legal) @[dec_decode_ctl.scala 757:83] - node _T_801 = and(_T_800, bitmanip_zbp_legal) @[dec_decode_ctl.scala 757:104] - node _T_802 = and(_T_801, bitmanip_zbr_legal) @[dec_decode_ctl.scala 757:125] - node _T_803 = and(_T_802, bitmanip_zbf_legal) @[dec_decode_ctl.scala 757:146] - node _T_804 = and(_T_803, bitmanip_zba_legal) @[dec_decode_ctl.scala 757:167] - node _T_805 = and(_T_804, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 757:188] - bitmanip_legal <= _T_805 @[dec_decode_ctl.scala 757:18] - node _T_806 = and(io.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 758:46] - i0_legal_decode_d <= _T_806 @[dec_decode_ctl.scala 758:24] - node _T_807 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44] - i0_d_c.mul <= _T_807 @[dec_decode_ctl.scala 760:29] - node _T_808 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 761:44] - i0_d_c.load <= _T_808 @[dec_decode_ctl.scala 761:29] - node _T_809 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 762:44] - i0_d_c.alu <= _T_809 @[dec_decode_ctl.scala 762:29] - wire _T_810 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 764:70] - _T_810.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70] - _T_810.load <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70] - _T_810.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 764:70] - node _T_811 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 764:92] - reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_810)) @[Reg.scala 27:20] - when _T_811 : @[Reg.scala 28:19] + bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 711:29] + bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 716:29] + node _T_791 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 723:32] + bitmanip_zbe_legal <= _T_791 @[dec_decode_ctl.scala 723:29] + node _T_792 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 728:32] + bitmanip_zbc_legal <= _T_792 @[dec_decode_ctl.scala 728:29] + node _T_793 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 733:46] + node _T_794 = and(i0_dp.zbp, _T_793) @[dec_decode_ctl.scala 733:44] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_decode_ctl.scala 733:32] + bitmanip_zbp_legal <= _T_795 @[dec_decode_ctl.scala 733:29] + node _T_796 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 738:32] + bitmanip_zbr_legal <= _T_796 @[dec_decode_ctl.scala 738:29] + node _T_797 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 743:32] + bitmanip_zbf_legal <= _T_797 @[dec_decode_ctl.scala 743:29] + node _T_798 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 748:32] + bitmanip_zba_legal <= _T_798 @[dec_decode_ctl.scala 748:29] + bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 751:29] + node _T_799 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 755:41] + node _T_800 = and(_T_799, bitmanip_zbe_legal) @[dec_decode_ctl.scala 755:62] + node _T_801 = and(_T_800, bitmanip_zbc_legal) @[dec_decode_ctl.scala 755:83] + node _T_802 = and(_T_801, bitmanip_zbp_legal) @[dec_decode_ctl.scala 755:104] + node _T_803 = and(_T_802, bitmanip_zbr_legal) @[dec_decode_ctl.scala 755:125] + node _T_804 = and(_T_803, bitmanip_zbf_legal) @[dec_decode_ctl.scala 755:146] + node _T_805 = and(_T_804, bitmanip_zba_legal) @[dec_decode_ctl.scala 755:167] + node _T_806 = and(_T_805, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 755:188] + bitmanip_legal <= _T_806 @[dec_decode_ctl.scala 755:18] + node _T_807 = and(io.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 756:46] + i0_legal_decode_d <= _T_807 @[dec_decode_ctl.scala 756:24] + node _T_808 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 758:44] + i0_d_c.mul <= _T_808 @[dec_decode_ctl.scala 758:29] + node _T_809 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 759:44] + i0_d_c.load <= _T_809 @[dec_decode_ctl.scala 759:29] + node _T_810 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44] + i0_d_c.alu <= _T_810 @[dec_decode_ctl.scala 760:29] + wire _T_811 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 762:70] + _T_811.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_811.load <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_811.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + node _T_812 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 762:92] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_811)) @[Reg.scala 27:20] + when _T_812 : @[Reg.scala 28:19] i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23] i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23] i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wire _T_812 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 765:70] - _T_812.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70] - _T_812.load <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70] - _T_812.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 765:70] - node _T_813 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 765:92] - reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_812)) @[Reg.scala 27:20] - when _T_813 : @[Reg.scala 28:19] + wire _T_813 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 763:70] + _T_813.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_813.load <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_813.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + node _T_814 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 763:92] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_813)) @[Reg.scala 27:20] + when _T_814 : @[Reg.scala 28:19] i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23] i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23] i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_814 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 766:83] - reg _T_815 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 766:72] - _T_815 <= _T_814 @[dec_decode_ctl.scala 766:72] - node _T_816 = cat(io.dec_i0_decode_d, _T_815) @[Cat.scala 29:58] - i0_pipe_en <= _T_816 @[dec_decode_ctl.scala 766:14] - node _T_817 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 768:43] - node _T_818 = orr(_T_817) @[dec_decode_ctl.scala 768:49] - node _T_819 = or(_T_818, io.clk_override) @[dec_decode_ctl.scala 768:53] - i0_x_ctl_en <= _T_819 @[dec_decode_ctl.scala 768:29] - node _T_820 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 769:43] - node _T_821 = orr(_T_820) @[dec_decode_ctl.scala 769:49] - node _T_822 = or(_T_821, io.clk_override) @[dec_decode_ctl.scala 769:53] - i0_r_ctl_en <= _T_822 @[dec_decode_ctl.scala 769:29] - node _T_823 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 770:43] - node _T_824 = orr(_T_823) @[dec_decode_ctl.scala 770:49] - node _T_825 = or(_T_824, io.clk_override) @[dec_decode_ctl.scala 770:53] - i0_wb_ctl_en <= _T_825 @[dec_decode_ctl.scala 770:29] - node _T_826 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 771:44] - node _T_827 = or(_T_826, io.clk_override) @[dec_decode_ctl.scala 771:50] - i0_x_data_en <= _T_827 @[dec_decode_ctl.scala 771:29] - node _T_828 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 772:44] - node _T_829 = or(_T_828, io.clk_override) @[dec_decode_ctl.scala 772:50] - i0_r_data_en <= _T_829 @[dec_decode_ctl.scala 772:29] - node _T_830 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 773:44] - node _T_831 = or(_T_830, io.clk_override) @[dec_decode_ctl.scala 773:50] - i0_wb_data_en <= _T_831 @[dec_decode_ctl.scala 773:29] - node _T_832 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] - io.decode_exu.dec_data_en <= _T_832 @[dec_decode_ctl.scala 775:38] - node _T_833 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] - io.decode_exu.dec_ctl_en <= _T_833 @[dec_decode_ctl.scala 776:38] - d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 778:34] - node _T_834 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 779:50] - d_d.bits.i0v <= _T_834 @[dec_decode_ctl.scala 779:34] - d_d.valid <= io.dec_i0_decode_d @[dec_decode_ctl.scala 780:35] - node _T_835 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50] - d_d.bits.i0load <= _T_835 @[dec_decode_ctl.scala 782:34] - node _T_836 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 783:50] - d_d.bits.i0store <= _T_836 @[dec_decode_ctl.scala 783:34] - node _T_837 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 784:50] - d_d.bits.i0div <= _T_837 @[dec_decode_ctl.scala 784:34] - node _T_838 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 786:61] - d_d.bits.csrwen <= _T_838 @[dec_decode_ctl.scala 786:34] - node _T_839 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[dec_decode_ctl.scala 787:58] - d_d.bits.csrwonly <= _T_839 @[dec_decode_ctl.scala 787:34] - node _T_840 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44] - node _T_841 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 788:61] - node _T_842 = mux(_T_840, _T_841, UInt<1>("h00")) @[dec_decode_ctl.scala 788:41] - d_d.bits.csrwaddr <= _T_842 @[dec_decode_ctl.scala 788:34] - node _T_843 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 790:63] - wire _T_844 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] - _T_844.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] - _T_844.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] - _T_844.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] - _T_844.valid <= UInt<1>("h00") @[lib.scala 630:37] - reg _T_845 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_844)) @[Reg.scala 27:20] - when _T_843 : @[Reg.scala 28:19] - _T_845.bits.csrwaddr <= d_d.bits.csrwaddr @[Reg.scala 28:23] - _T_845.bits.csrwonly <= d_d.bits.csrwonly @[Reg.scala 28:23] - _T_845.bits.csrwen <= d_d.bits.csrwen @[Reg.scala 28:23] - _T_845.bits.i0v <= d_d.bits.i0v @[Reg.scala 28:23] - _T_845.bits.i0div <= d_d.bits.i0div @[Reg.scala 28:23] - _T_845.bits.i0store <= d_d.bits.i0store @[Reg.scala 28:23] - _T_845.bits.i0load <= d_d.bits.i0load @[Reg.scala 28:23] - _T_845.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23] - _T_845.valid <= d_d.valid @[Reg.scala 28:23] + node _T_815 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 764:83] + reg _T_816 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 764:72] + _T_816 <= _T_815 @[dec_decode_ctl.scala 764:72] + node _T_817 = cat(io.dec_i0_decode_d, _T_816) @[Cat.scala 29:58] + i0_pipe_en <= _T_817 @[dec_decode_ctl.scala 764:14] + node _T_818 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 766:43] + node _T_819 = orr(_T_818) @[dec_decode_ctl.scala 766:49] + node _T_820 = or(_T_819, io.clk_override) @[dec_decode_ctl.scala 766:53] + i0_x_ctl_en <= _T_820 @[dec_decode_ctl.scala 766:29] + node _T_821 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 767:43] + node _T_822 = orr(_T_821) @[dec_decode_ctl.scala 767:49] + node _T_823 = or(_T_822, io.clk_override) @[dec_decode_ctl.scala 767:53] + i0_r_ctl_en <= _T_823 @[dec_decode_ctl.scala 767:29] + node _T_824 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 768:43] + node _T_825 = orr(_T_824) @[dec_decode_ctl.scala 768:49] + node _T_826 = or(_T_825, io.clk_override) @[dec_decode_ctl.scala 768:53] + i0_wb_ctl_en <= _T_826 @[dec_decode_ctl.scala 768:29] + node _T_827 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 769:44] + node _T_828 = or(_T_827, io.clk_override) @[dec_decode_ctl.scala 769:50] + i0_x_data_en <= _T_828 @[dec_decode_ctl.scala 769:29] + node _T_829 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 770:44] + node _T_830 = or(_T_829, io.clk_override) @[dec_decode_ctl.scala 770:50] + i0_r_data_en <= _T_830 @[dec_decode_ctl.scala 770:29] + node _T_831 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 771:44] + node _T_832 = or(_T_831, io.clk_override) @[dec_decode_ctl.scala 771:50] + i0_wb_data_en <= _T_832 @[dec_decode_ctl.scala 771:29] + node _T_833 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.decode_exu.dec_data_en <= _T_833 @[dec_decode_ctl.scala 773:38] + node _T_834 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.decode_exu.dec_ctl_en <= _T_834 @[dec_decode_ctl.scala 774:38] + d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 776:34] + node _T_835 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 777:50] + d_d.bits.i0v <= _T_835 @[dec_decode_ctl.scala 777:34] + d_d.valid <= io.dec_i0_decode_d @[dec_decode_ctl.scala 778:35] + node _T_836 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 780:50] + d_d.bits.i0load <= _T_836 @[dec_decode_ctl.scala 780:34] + node _T_837 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 781:50] + d_d.bits.i0store <= _T_837 @[dec_decode_ctl.scala 781:34] + node _T_838 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50] + d_d.bits.i0div <= _T_838 @[dec_decode_ctl.scala 782:34] + node _T_839 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 784:61] + d_d.bits.csrwen <= _T_839 @[dec_decode_ctl.scala 784:34] + node _T_840 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[dec_decode_ctl.scala 785:58] + d_d.bits.csrwonly <= _T_840 @[dec_decode_ctl.scala 785:34] + node _T_841 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44] + node _T_842 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 786:61] + node _T_843 = mux(_T_841, _T_842, UInt<1>("h00")) @[dec_decode_ctl.scala 786:41] + d_d.bits.csrwaddr <= _T_843 @[dec_decode_ctl.scala 786:34] + node _T_844 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 788:63] + wire _T_845 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_845.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_845.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_845.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_845.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_846 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_845)) @[Reg.scala 27:20] + when _T_844 : @[Reg.scala 28:19] + _T_846.bits.csrwaddr <= d_d.bits.csrwaddr @[Reg.scala 28:23] + _T_846.bits.csrwonly <= d_d.bits.csrwonly @[Reg.scala 28:23] + _T_846.bits.csrwen <= d_d.bits.csrwen @[Reg.scala 28:23] + _T_846.bits.i0v <= d_d.bits.i0v @[Reg.scala 28:23] + _T_846.bits.i0div <= d_d.bits.i0div @[Reg.scala 28:23] + _T_846.bits.i0store <= d_d.bits.i0store @[Reg.scala 28:23] + _T_846.bits.i0load <= d_d.bits.i0load @[Reg.scala 28:23] + _T_846.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23] + _T_846.valid <= d_d.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - x_d.bits.csrwaddr <= _T_845.bits.csrwaddr @[dec_decode_ctl.scala 790:7] - x_d.bits.csrwonly <= _T_845.bits.csrwonly @[dec_decode_ctl.scala 790:7] - x_d.bits.csrwen <= _T_845.bits.csrwen @[dec_decode_ctl.scala 790:7] - x_d.bits.i0v <= _T_845.bits.i0v @[dec_decode_ctl.scala 790:7] - x_d.bits.i0div <= _T_845.bits.i0div @[dec_decode_ctl.scala 790:7] - x_d.bits.i0store <= _T_845.bits.i0store @[dec_decode_ctl.scala 790:7] - x_d.bits.i0load <= _T_845.bits.i0load @[dec_decode_ctl.scala 790:7] - x_d.bits.i0rd <= _T_845.bits.i0rd @[dec_decode_ctl.scala 790:7] - x_d.valid <= _T_845.valid @[dec_decode_ctl.scala 790:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 791:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 792:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 792:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 792:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 792:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 792:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 792:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 792:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 792:10] - x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 792:10] - node _T_846 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 793:49] - node _T_847 = and(x_d.bits.i0v, _T_846) @[dec_decode_ctl.scala 793:47] - node _T_848 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 793:78] - node _T_849 = and(_T_847, _T_848) @[dec_decode_ctl.scala 793:76] - x_d_in.bits.i0v <= _T_849 @[dec_decode_ctl.scala 793:27] - node _T_850 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 794:35] - node _T_851 = and(x_d.valid, _T_850) @[dec_decode_ctl.scala 794:33] - node _T_852 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 794:64] - node _T_853 = and(_T_851, _T_852) @[dec_decode_ctl.scala 794:62] - x_d_in.valid <= _T_853 @[dec_decode_ctl.scala 794:20] - node _T_854 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 796:65] - wire _T_855 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] - _T_855.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] - _T_855.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] - _T_855.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] - _T_855.valid <= UInt<1>("h00") @[lib.scala 630:37] - reg _T_856 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_855)) @[Reg.scala 27:20] - when _T_854 : @[Reg.scala 28:19] - _T_856.bits.csrwaddr <= x_d_in.bits.csrwaddr @[Reg.scala 28:23] - _T_856.bits.csrwonly <= x_d_in.bits.csrwonly @[Reg.scala 28:23] - _T_856.bits.csrwen <= x_d_in.bits.csrwen @[Reg.scala 28:23] - _T_856.bits.i0v <= x_d_in.bits.i0v @[Reg.scala 28:23] - _T_856.bits.i0div <= x_d_in.bits.i0div @[Reg.scala 28:23] - _T_856.bits.i0store <= x_d_in.bits.i0store @[Reg.scala 28:23] - _T_856.bits.i0load <= x_d_in.bits.i0load @[Reg.scala 28:23] - _T_856.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23] - _T_856.valid <= x_d_in.valid @[Reg.scala 28:23] + x_d.bits.csrwaddr <= _T_846.bits.csrwaddr @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwonly <= _T_846.bits.csrwonly @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwen <= _T_846.bits.csrwen @[dec_decode_ctl.scala 788:7] + x_d.bits.i0v <= _T_846.bits.i0v @[dec_decode_ctl.scala 788:7] + x_d.bits.i0div <= _T_846.bits.i0div @[dec_decode_ctl.scala 788:7] + x_d.bits.i0store <= _T_846.bits.i0store @[dec_decode_ctl.scala 788:7] + x_d.bits.i0load <= _T_846.bits.i0load @[dec_decode_ctl.scala 788:7] + x_d.bits.i0rd <= _T_846.bits.i0rd @[dec_decode_ctl.scala 788:7] + x_d.valid <= _T_846.valid @[dec_decode_ctl.scala 788:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 789:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 790:10] + x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 790:10] + node _T_847 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 791:49] + node _T_848 = and(x_d.bits.i0v, _T_847) @[dec_decode_ctl.scala 791:47] + node _T_849 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 791:78] + node _T_850 = and(_T_848, _T_849) @[dec_decode_ctl.scala 791:76] + x_d_in.bits.i0v <= _T_850 @[dec_decode_ctl.scala 791:27] + node _T_851 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 792:35] + node _T_852 = and(x_d.valid, _T_851) @[dec_decode_ctl.scala 792:33] + node _T_853 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 792:64] + node _T_854 = and(_T_852, _T_853) @[dec_decode_ctl.scala 792:62] + x_d_in.valid <= _T_854 @[dec_decode_ctl.scala 792:20] + node _T_855 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 794:65] + wire _T_856 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_856.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_856.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_856.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_856.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_857 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_856)) @[Reg.scala 27:20] + when _T_855 : @[Reg.scala 28:19] + _T_857.bits.csrwaddr <= x_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_857.bits.csrwonly <= x_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_857.bits.csrwen <= x_d_in.bits.csrwen @[Reg.scala 28:23] + _T_857.bits.i0v <= x_d_in.bits.i0v @[Reg.scala 28:23] + _T_857.bits.i0div <= x_d_in.bits.i0div @[Reg.scala 28:23] + _T_857.bits.i0store <= x_d_in.bits.i0store @[Reg.scala 28:23] + _T_857.bits.i0load <= x_d_in.bits.i0load @[Reg.scala 28:23] + _T_857.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23] + _T_857.valid <= x_d_in.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - r_d.bits.csrwaddr <= _T_856.bits.csrwaddr @[dec_decode_ctl.scala 796:7] - r_d.bits.csrwonly <= _T_856.bits.csrwonly @[dec_decode_ctl.scala 796:7] - r_d.bits.csrwen <= _T_856.bits.csrwen @[dec_decode_ctl.scala 796:7] - r_d.bits.i0v <= _T_856.bits.i0v @[dec_decode_ctl.scala 796:7] - r_d.bits.i0div <= _T_856.bits.i0div @[dec_decode_ctl.scala 796:7] - r_d.bits.i0store <= _T_856.bits.i0store @[dec_decode_ctl.scala 796:7] - r_d.bits.i0load <= _T_856.bits.i0load @[dec_decode_ctl.scala 796:7] - r_d.bits.i0rd <= _T_856.bits.i0rd @[dec_decode_ctl.scala 796:7] - r_d.valid <= _T_856.valid @[dec_decode_ctl.scala 796:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 797:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 797:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 797:10] - r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 797:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 798:22] - node _T_857 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51] - node _T_858 = and(r_d.bits.i0v, _T_857) @[dec_decode_ctl.scala 800:49] - r_d_in.bits.i0v <= _T_858 @[dec_decode_ctl.scala 800:27] - node _T_859 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:37] - node _T_860 = and(r_d.valid, _T_859) @[dec_decode_ctl.scala 801:35] - r_d_in.valid <= _T_860 @[dec_decode_ctl.scala 801:20] - node _T_861 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 802:51] - node _T_862 = and(r_d.bits.i0load, _T_861) @[dec_decode_ctl.scala 802:49] - r_d_in.bits.i0load <= _T_862 @[dec_decode_ctl.scala 802:27] - node _T_863 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 803:51] - node _T_864 = and(r_d.bits.i0store, _T_863) @[dec_decode_ctl.scala 803:49] - r_d_in.bits.i0store <= _T_864 @[dec_decode_ctl.scala 803:27] - node _T_865 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 805:66] - wire _T_866 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] - _T_866.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] - _T_866.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] - _T_866.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] - _T_866.valid <= UInt<1>("h00") @[lib.scala 630:37] - reg _T_867 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_866)) @[Reg.scala 27:20] - when _T_865 : @[Reg.scala 28:19] - _T_867.bits.csrwaddr <= r_d_in.bits.csrwaddr @[Reg.scala 28:23] - _T_867.bits.csrwonly <= r_d_in.bits.csrwonly @[Reg.scala 28:23] - _T_867.bits.csrwen <= r_d_in.bits.csrwen @[Reg.scala 28:23] - _T_867.bits.i0v <= r_d_in.bits.i0v @[Reg.scala 28:23] - _T_867.bits.i0div <= r_d_in.bits.i0div @[Reg.scala 28:23] - _T_867.bits.i0store <= r_d_in.bits.i0store @[Reg.scala 28:23] - _T_867.bits.i0load <= r_d_in.bits.i0load @[Reg.scala 28:23] - _T_867.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23] - _T_867.valid <= r_d_in.valid @[Reg.scala 28:23] + r_d.bits.csrwaddr <= _T_857.bits.csrwaddr @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwonly <= _T_857.bits.csrwonly @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwen <= _T_857.bits.csrwen @[dec_decode_ctl.scala 794:7] + r_d.bits.i0v <= _T_857.bits.i0v @[dec_decode_ctl.scala 794:7] + r_d.bits.i0div <= _T_857.bits.i0div @[dec_decode_ctl.scala 794:7] + r_d.bits.i0store <= _T_857.bits.i0store @[dec_decode_ctl.scala 794:7] + r_d.bits.i0load <= _T_857.bits.i0load @[dec_decode_ctl.scala 794:7] + r_d.bits.i0rd <= _T_857.bits.i0rd @[dec_decode_ctl.scala 794:7] + r_d.valid <= _T_857.valid @[dec_decode_ctl.scala 794:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 795:10] + r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 796:22] + node _T_858 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 798:51] + node _T_859 = and(r_d.bits.i0v, _T_858) @[dec_decode_ctl.scala 798:49] + r_d_in.bits.i0v <= _T_859 @[dec_decode_ctl.scala 798:27] + node _T_860 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 799:37] + node _T_861 = and(r_d.valid, _T_860) @[dec_decode_ctl.scala 799:35] + r_d_in.valid <= _T_861 @[dec_decode_ctl.scala 799:20] + node _T_862 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51] + node _T_863 = and(r_d.bits.i0load, _T_862) @[dec_decode_ctl.scala 800:49] + r_d_in.bits.i0load <= _T_863 @[dec_decode_ctl.scala 800:27] + node _T_864 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:51] + node _T_865 = and(r_d.bits.i0store, _T_864) @[dec_decode_ctl.scala 801:49] + r_d_in.bits.i0store <= _T_865 @[dec_decode_ctl.scala 801:27] + node _T_866 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 803:66] + wire _T_867 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_867.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_867.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_867.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_867.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_868 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_867)) @[Reg.scala 27:20] + when _T_866 : @[Reg.scala 28:19] + _T_868.bits.csrwaddr <= r_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_868.bits.csrwonly <= r_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_868.bits.csrwen <= r_d_in.bits.csrwen @[Reg.scala 28:23] + _T_868.bits.i0v <= r_d_in.bits.i0v @[Reg.scala 28:23] + _T_868.bits.i0div <= r_d_in.bits.i0div @[Reg.scala 28:23] + _T_868.bits.i0store <= r_d_in.bits.i0store @[Reg.scala 28:23] + _T_868.bits.i0load <= r_d_in.bits.i0load @[Reg.scala 28:23] + _T_868.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23] + _T_868.valid <= r_d_in.valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wbd.bits.csrwaddr <= _T_867.bits.csrwaddr @[dec_decode_ctl.scala 805:7] - wbd.bits.csrwonly <= _T_867.bits.csrwonly @[dec_decode_ctl.scala 805:7] - wbd.bits.csrwen <= _T_867.bits.csrwen @[dec_decode_ctl.scala 805:7] - wbd.bits.i0v <= _T_867.bits.i0v @[dec_decode_ctl.scala 805:7] - wbd.bits.i0div <= _T_867.bits.i0div @[dec_decode_ctl.scala 805:7] - wbd.bits.i0store <= _T_867.bits.i0store @[dec_decode_ctl.scala 805:7] - wbd.bits.i0load <= _T_867.bits.i0load @[dec_decode_ctl.scala 805:7] - wbd.bits.i0rd <= _T_867.bits.i0rd @[dec_decode_ctl.scala 805:7] - wbd.valid <= _T_867.valid @[dec_decode_ctl.scala 805:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 807:27] - node _T_868 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 808:47] - node _T_869 = and(r_d_in.bits.i0v, _T_868) @[dec_decode_ctl.scala 808:45] - i0_wen_r <= _T_869 @[dec_decode_ctl.scala 808:25] - node _T_870 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 809:49] - node _T_871 = and(i0_wen_r, _T_870) @[dec_decode_ctl.scala 809:47] - node _T_872 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 809:70] - node _T_873 = and(_T_871, _T_872) @[dec_decode_ctl.scala 809:68] - io.dec_i0_wen_r <= _T_873 @[dec_decode_ctl.scala 809:32] - io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 810:26] - node _T_874 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 813:74] - node _T_875 = or(_T_874, debug_valid_x) @[dec_decode_ctl.scala 813:92] - node _T_876 = and(i0_r_data_en, _T_875) @[dec_decode_ctl.scala 813:58] - node _T_877 = eq(_T_876, UInt<1>("h01")) @[dec_decode_ctl.scala 813:110] + wbd.bits.csrwaddr <= _T_868.bits.csrwaddr @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwonly <= _T_868.bits.csrwonly @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwen <= _T_868.bits.csrwen @[dec_decode_ctl.scala 803:7] + wbd.bits.i0v <= _T_868.bits.i0v @[dec_decode_ctl.scala 803:7] + wbd.bits.i0div <= _T_868.bits.i0div @[dec_decode_ctl.scala 803:7] + wbd.bits.i0store <= _T_868.bits.i0store @[dec_decode_ctl.scala 803:7] + wbd.bits.i0load <= _T_868.bits.i0load @[dec_decode_ctl.scala 803:7] + wbd.bits.i0rd <= _T_868.bits.i0rd @[dec_decode_ctl.scala 803:7] + wbd.valid <= _T_868.valid @[dec_decode_ctl.scala 803:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 805:27] + node _T_869 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 806:47] + node _T_870 = and(r_d_in.bits.i0v, _T_869) @[dec_decode_ctl.scala 806:45] + i0_wen_r <= _T_870 @[dec_decode_ctl.scala 806:25] + node _T_871 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 807:49] + node _T_872 = and(i0_wen_r, _T_871) @[dec_decode_ctl.scala 807:47] + node _T_873 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 807:70] + node _T_874 = and(_T_872, _T_873) @[dec_decode_ctl.scala 807:68] + io.dec_i0_wen_r <= _T_874 @[dec_decode_ctl.scala 807:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 808:26] + node _T_875 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 811:74] + node _T_876 = or(_T_875, debug_valid_x) @[dec_decode_ctl.scala 811:92] + node _T_877 = and(i0_r_data_en, _T_876) @[dec_decode_ctl.scala 811:58] + node _T_878 = eq(_T_877, UInt<1>("h01")) @[dec_decode_ctl.scala 811:110] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_4.io.en <= _T_877 @[lib.scala 407:17] + rvclkhdr_4.io.en <= _T_878 @[lib.scala 407:17] rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_result_r_raw : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_877 : @[Reg.scala 28:19] + when _T_878 : @[Reg.scala 28:19] i0_result_r_raw <= i0_result_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_878 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 819:47] - node _T_879 = bits(_T_878, 0, 0) @[dec_decode_ctl.scala 819:66] - node _T_880 = mux(_T_879, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 819:32] - i0_result_x <= _T_880 @[dec_decode_ctl.scala 819:26] - i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 820:26] - node _T_881 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 824:42] - node _T_882 = bits(_T_881, 0, 0) @[dec_decode_ctl.scala 824:61] - node _T_883 = mux(_T_882, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 824:27] - i0_result_corr_r <= _T_883 @[dec_decode_ctl.scala 824:21] - node _T_884 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 825:73] - node _T_885 = and(io.decode_exu.i0_ap.predict_nt, _T_884) @[dec_decode_ctl.scala 825:71] - node _T_886 = bits(_T_885, 0, 0) @[dec_decode_ctl.scala 825:85] - wire _T_887 : UInt<1>[10] @[lib.scala 12:48] - _T_887[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_887[9] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_888 = cat(_T_887[0], _T_887[1]) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_887[2]) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887[3]) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_887[4]) @[Cat.scala 29:58] - node _T_892 = cat(_T_891, _T_887[5]) @[Cat.scala 29:58] - node _T_893 = cat(_T_892, _T_887[6]) @[Cat.scala 29:58] - node _T_894 = cat(_T_893, _T_887[7]) @[Cat.scala 29:58] - node _T_895 = cat(_T_894, _T_887[8]) @[Cat.scala 29:58] - node _T_896 = cat(_T_895, _T_887[9]) @[Cat.scala 29:58] - node _T_897 = cat(_T_896, io.dec_i0_pc4_d) @[Cat.scala 29:58] - node _T_898 = cat(_T_897, i0_ap_pc2) @[Cat.scala 29:58] - node _T_899 = mux(_T_886, i0_br_offset, _T_898) @[dec_decode_ctl.scala 825:38] - io.dec_alu.dec_i0_br_immed_d <= _T_899 @[dec_decode_ctl.scala 825:32] + node _T_879 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 817:47] + node _T_880 = bits(_T_879, 0, 0) @[dec_decode_ctl.scala 817:66] + node _T_881 = mux(_T_880, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 817:32] + i0_result_x <= _T_881 @[dec_decode_ctl.scala 817:26] + i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 818:26] + node _T_882 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 822:42] + node _T_883 = bits(_T_882, 0, 0) @[dec_decode_ctl.scala 822:61] + node _T_884 = mux(_T_883, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 822:27] + i0_result_corr_r <= _T_884 @[dec_decode_ctl.scala 822:21] + node _T_885 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 823:73] + node _T_886 = and(io.decode_exu.i0_ap.predict_nt, _T_885) @[dec_decode_ctl.scala 823:71] + node _T_887 = bits(_T_886, 0, 0) @[dec_decode_ctl.scala 823:85] + wire _T_888 : UInt<1>[10] @[lib.scala 12:48] + _T_888[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_888[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_889 = cat(_T_888[0], _T_888[1]) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_888[2]) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_888[3]) @[Cat.scala 29:58] + node _T_892 = cat(_T_891, _T_888[4]) @[Cat.scala 29:58] + node _T_893 = cat(_T_892, _T_888[5]) @[Cat.scala 29:58] + node _T_894 = cat(_T_893, _T_888[6]) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, _T_888[7]) @[Cat.scala 29:58] + node _T_896 = cat(_T_895, _T_888[8]) @[Cat.scala 29:58] + node _T_897 = cat(_T_896, _T_888[9]) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, i0_ap_pc2) @[Cat.scala 29:58] + node _T_900 = mux(_T_887, i0_br_offset, _T_899) @[dec_decode_ctl.scala 823:38] + io.dec_alu.dec_i0_br_immed_d <= _T_900 @[dec_decode_ctl.scala 823:32] wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") - node _T_900 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 827:59] - wire _T_901 : UInt<1>[10] @[lib.scala 12:48] - _T_901[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_901[9] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_902 = cat(_T_901[0], _T_901[1]) @[Cat.scala 29:58] - node _T_903 = cat(_T_902, _T_901[2]) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_901[3]) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_901[4]) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_901[5]) @[Cat.scala 29:58] - node _T_907 = cat(_T_906, _T_901[6]) @[Cat.scala 29:58] - node _T_908 = cat(_T_907, _T_901[7]) @[Cat.scala 29:58] - node _T_909 = cat(_T_908, _T_901[8]) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, _T_901[9]) @[Cat.scala 29:58] - node _T_911 = cat(_T_910, io.dec_i0_pc4_d) @[Cat.scala 29:58] - node _T_912 = cat(_T_911, i0_ap_pc2) @[Cat.scala 29:58] - node _T_913 = mux(_T_900, _T_912, i0_br_offset) @[dec_decode_ctl.scala 827:25] - last_br_immed_d <= _T_913 @[dec_decode_ctl.scala 827:19] + node _T_901 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 825:59] + wire _T_902 : UInt<1>[10] @[lib.scala 12:48] + _T_902[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_902[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_903 = cat(_T_902[0], _T_902[1]) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_902[2]) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_902[3]) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_902[4]) @[Cat.scala 29:58] + node _T_907 = cat(_T_906, _T_902[5]) @[Cat.scala 29:58] + node _T_908 = cat(_T_907, _T_902[6]) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, _T_902[7]) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, _T_902[8]) @[Cat.scala 29:58] + node _T_911 = cat(_T_910, _T_902[9]) @[Cat.scala 29:58] + node _T_912 = cat(_T_911, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_913 = cat(_T_912, i0_ap_pc2) @[Cat.scala 29:58] + node _T_914 = mux(_T_901, _T_913, i0_br_offset) @[dec_decode_ctl.scala 825:25] + last_br_immed_d <= _T_914 @[dec_decode_ctl.scala 825:19] wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") - node _T_914 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 829:58] + node _T_915 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 827:58] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_5.io.en <= _T_914 @[lib.scala 407:17] + rvclkhdr_5.io.en <= _T_915 @[lib.scala 407:17] rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] - reg _T_915 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_914 : @[Reg.scala 28:19] - _T_915 <= last_br_immed_d @[Reg.scala 28:23] + reg _T_916 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_915 : @[Reg.scala 28:19] + _T_916 <= last_br_immed_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_br_immed_x <= _T_915 @[dec_decode_ctl.scala 829:19] - node _T_916 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:45] - node _T_917 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 833:76] - node div_e1_to_r = or(_T_916, _T_917) @[dec_decode_ctl.scala 833:58] - node _T_918 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 835:48] - node _T_919 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 835:77] - node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 835:60] - node _T_921 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 836:21] - node _T_922 = and(_T_921, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 836:33] - node _T_923 = or(_T_920, _T_922) @[dec_decode_ctl.scala 835:94] - node _T_924 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 837:21] - node _T_925 = and(_T_924, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 837:33] - node _T_926 = and(_T_925, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 837:60] - node div_flush = or(_T_923, _T_926) @[dec_decode_ctl.scala 836:62] - node _T_927 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 841:51] - node _T_928 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 842:26] - node _T_929 = and(io.dec_div_active, _T_928) @[dec_decode_ctl.scala 842:24] - node _T_930 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 842:56] - node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 842:39] - node _T_932 = and(_T_931, i0_wen_r) @[dec_decode_ctl.scala 842:77] - node nonblock_div_cancel = or(_T_927, _T_932) @[dec_decode_ctl.scala 841:65] - node _T_933 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 844:61] - io.dec_div.dec_div_cancel <= _T_933 @[dec_decode_ctl.scala 844:37] - node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 845:55] - node _T_934 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 847:59] - node _T_935 = and(io.dec_div_active, _T_934) @[dec_decode_ctl.scala 847:57] - node _T_936 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 847:78] - node _T_937 = and(_T_935, _T_936) @[dec_decode_ctl.scala 847:76] - node _T_938 = or(i0_div_decode_d, _T_937) @[dec_decode_ctl.scala 847:36] - div_active_in <= _T_938 @[dec_decode_ctl.scala 847:17] - node _T_939 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 852:60] - node _T_940 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 852:99] - node _T_941 = and(_T_939, _T_940) @[dec_decode_ctl.scala 852:80] - node _T_942 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 853:36] - node _T_943 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 853:75] - node _T_944 = and(_T_942, _T_943) @[dec_decode_ctl.scala 853:56] - node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 852:113] - i0_nonblock_div_stall <= _T_945 @[dec_decode_ctl.scala 852:26] - node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 860:22] - node _T_946 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 862:58] + last_br_immed_x <= _T_916 @[dec_decode_ctl.scala 827:19] + node _T_917 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 831:45] + node _T_918 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 831:76] + node div_e1_to_r = or(_T_917, _T_918) @[dec_decode_ctl.scala 831:58] + node _T_919 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:48] + node _T_920 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 833:77] + node _T_921 = and(_T_919, _T_920) @[dec_decode_ctl.scala 833:60] + node _T_922 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 834:21] + node _T_923 = and(_T_922, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 834:33] + node _T_924 = or(_T_921, _T_923) @[dec_decode_ctl.scala 833:94] + node _T_925 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 835:21] + node _T_926 = and(_T_925, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 835:33] + node _T_927 = and(_T_926, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 835:60] + node div_flush = or(_T_924, _T_927) @[dec_decode_ctl.scala 834:62] + node _T_928 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 839:51] + node _T_929 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 840:26] + node _T_930 = and(io.dec_div_active, _T_929) @[dec_decode_ctl.scala 840:24] + node _T_931 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 840:56] + node _T_932 = and(_T_930, _T_931) @[dec_decode_ctl.scala 840:39] + node _T_933 = and(_T_932, i0_wen_r) @[dec_decode_ctl.scala 840:77] + node nonblock_div_cancel = or(_T_928, _T_933) @[dec_decode_ctl.scala 839:65] + node _T_934 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 842:61] + io.dec_div.dec_div_cancel <= _T_934 @[dec_decode_ctl.scala 842:37] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 843:55] + node _T_935 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 845:59] + node _T_936 = and(io.dec_div_active, _T_935) @[dec_decode_ctl.scala 845:57] + node _T_937 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 845:78] + node _T_938 = and(_T_936, _T_937) @[dec_decode_ctl.scala 845:76] + node _T_939 = or(i0_div_decode_d, _T_938) @[dec_decode_ctl.scala 845:36] + div_active_in <= _T_939 @[dec_decode_ctl.scala 845:17] + node _T_940 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 850:60] + node _T_941 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 850:99] + node _T_942 = and(_T_940, _T_941) @[dec_decode_ctl.scala 850:80] + node _T_943 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 851:36] + node _T_944 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 851:75] + node _T_945 = and(_T_943, _T_944) @[dec_decode_ctl.scala 851:56] + node _T_946 = or(_T_942, _T_945) @[dec_decode_ctl.scala 850:113] + i0_nonblock_div_stall <= _T_946 @[dec_decode_ctl.scala 850:26] + node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 858:22] + node _T_947 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 860:58] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_6.io.en <= _T_946 @[lib.scala 407:17] + rvclkhdr_6.io.en <= _T_947 @[lib.scala 407:17] rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] - reg _T_947 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_946 : @[Reg.scala 28:19] - _T_947 <= i0r.rd @[Reg.scala 28:23] + reg _T_948 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_947 : @[Reg.scala 28:19] + _T_948 <= i0r.rd @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.div_waddr_wb <= _T_947 @[dec_decode_ctl.scala 862:19] - node _T_948 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 864:50] - node _T_949 = bits(_T_948, 0, 0) @[lib.scala 8:44] + io.div_waddr_wb <= _T_948 @[dec_decode_ctl.scala 860:19] + node _T_949 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 862:50] + node _T_950 = bits(_T_949, 0, 0) @[lib.scala 8:44] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_7.io.en <= _T_949 @[lib.scala 407:17] + rvclkhdr_7.io.en <= _T_950 @[lib.scala 407:17] rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_inst_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_949 : @[Reg.scala 28:19] + when _T_950 : @[Reg.scala 28:19] i0_inst_x <= i0_inst_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_950 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 865:50] - node _T_951 = bits(_T_950, 0, 0) @[lib.scala 8:44] + node _T_951 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 863:50] + node _T_952 = bits(_T_951, 0, 0) @[lib.scala 8:44] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_8.io.en <= _T_951 @[lib.scala 407:17] + rvclkhdr_8.io.en <= _T_952 @[lib.scala 407:17] rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_inst_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_951 : @[Reg.scala 28:19] + when _T_952 : @[Reg.scala 28:19] i0_inst_r <= i0_inst_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_952 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 867:51] - node _T_953 = bits(_T_952, 0, 0) @[lib.scala 8:44] + node _T_953 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 865:51] + node _T_954 = bits(_T_953, 0, 0) @[lib.scala 8:44] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_9.io.en <= _T_953 @[lib.scala 407:17] + rvclkhdr_9.io.en <= _T_954 @[lib.scala 407:17] rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_inst_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_953 : @[Reg.scala 28:19] + when _T_954 : @[Reg.scala 28:19] i0_inst_wb <= i0_inst_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_954 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 868:54] - node _T_955 = bits(_T_954, 0, 0) @[lib.scala 8:44] + node _T_955 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 866:54] + node _T_956 = bits(_T_955, 0, 0) @[lib.scala 8:44] inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] - rvclkhdr_10.io.en <= _T_955 @[lib.scala 407:17] + rvclkhdr_10.io.en <= _T_956 @[lib.scala 407:17] rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] reg i0_pc_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_955 : @[Reg.scala 28:19] + when _T_956 : @[Reg.scala 28:19] i0_pc_wb <= io.dec_tlu_i0_pc_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 870:21] - io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 871:19] - node _T_956 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 872:67] - wire _T_957 : UInt<31> @[lib.scala 648:38] - _T_957 <= UInt<1>("h00") @[lib.scala 648:38] - reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_957)) @[Reg.scala 27:20] - when _T_956 : @[Reg.scala 28:19] + io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 868:21] + io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 869:19] + node _T_957 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 870:67] + wire _T_958 : UInt<31> @[lib.scala 648:38] + _T_958 <= UInt<1>("h00") @[lib.scala 648:38] + reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_958)) @[Reg.scala 27:20] + when _T_957 : @[Reg.scala 28:19] dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 874:27] - node _T_958 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_959 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_960 = bits(_T_958, 12, 1) @[lib.scala 68:24] - node _T_961 = bits(_T_959, 12, 1) @[lib.scala 68:40] - node _T_962 = add(_T_960, _T_961) @[lib.scala 68:31] - node _T_963 = bits(_T_958, 31, 13) @[lib.scala 69:20] - node _T_964 = add(_T_963, UInt<1>("h01")) @[lib.scala 69:27] - node _T_965 = tail(_T_964, 1) @[lib.scala 69:27] - node _T_966 = bits(_T_958, 31, 13) @[lib.scala 70:20] - node _T_967 = sub(_T_966, UInt<1>("h01")) @[lib.scala 70:27] - node _T_968 = tail(_T_967, 1) @[lib.scala 70:27] - node _T_969 = bits(_T_959, 12, 12) @[lib.scala 71:22] - node _T_970 = bits(_T_962, 12, 12) @[lib.scala 72:39] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[lib.scala 72:28] - node _T_972 = xor(_T_969, _T_971) @[lib.scala 72:26] - node _T_973 = bits(_T_972, 0, 0) @[lib.scala 72:64] - node _T_974 = bits(_T_958, 31, 13) @[lib.scala 72:76] - node _T_975 = eq(_T_969, UInt<1>("h00")) @[lib.scala 73:20] - node _T_976 = bits(_T_962, 12, 12) @[lib.scala 73:39] - node _T_977 = and(_T_975, _T_976) @[lib.scala 73:26] - node _T_978 = bits(_T_977, 0, 0) @[lib.scala 73:64] - node _T_979 = bits(_T_962, 12, 12) @[lib.scala 74:39] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[lib.scala 74:28] - node _T_981 = and(_T_969, _T_980) @[lib.scala 74:26] - node _T_982 = bits(_T_981, 0, 0) @[lib.scala 74:64] - node _T_983 = mux(_T_973, _T_974, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_984 = mux(_T_978, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_985 = mux(_T_982, _T_968, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_986 = or(_T_983, _T_984) @[Mux.scala 27:72] - node _T_987 = or(_T_986, _T_985) @[Mux.scala 27:72] - wire _T_988 : UInt<19> @[Mux.scala 27:72] - _T_988 <= _T_987 @[Mux.scala 27:72] - node _T_989 = bits(_T_962, 11, 0) @[lib.scala 74:94] - node _T_990 = cat(_T_988, _T_989) @[Cat.scala 29:58] - node temp_pred_correct_npc_x = cat(_T_990, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_991 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 879:62] - io.decode_exu.pred_correct_npc_x <= _T_991 @[dec_decode_ctl.scala 879:36] - node _T_992 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 883:59] - node _T_993 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 883:91] - node i0_rs1_depend_i0_x = and(_T_992, _T_993) @[dec_decode_ctl.scala 883:74] - node _T_994 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 884:59] - node _T_995 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 884:91] - node i0_rs1_depend_i0_r = and(_T_994, _T_995) @[dec_decode_ctl.scala 884:74] - node _T_996 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 886:59] - node _T_997 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 886:91] - node i0_rs2_depend_i0_x = and(_T_996, _T_997) @[dec_decode_ctl.scala 886:74] - node _T_998 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 887:59] - node _T_999 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 887:91] - node i0_rs2_depend_i0_r = and(_T_998, _T_999) @[dec_decode_ctl.scala 887:74] - node _T_1000 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44] - node _T_1001 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81] - wire _T_1002 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109] - _T_1002.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] - _T_1002.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] - _T_1002.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] - node _T_1003 = mux(_T_1001, i0_r_c, _T_1002) @[dec_decode_ctl.scala 889:61] - node _T_1004 = mux(_T_1000, i0_x_c, _T_1003) @[dec_decode_ctl.scala 889:24] - i0_rs1_class_d.alu <= _T_1004.alu @[dec_decode_ctl.scala 889:18] - i0_rs1_class_d.load <= _T_1004.load @[dec_decode_ctl.scala 889:18] - i0_rs1_class_d.mul <= _T_1004.mul @[dec_decode_ctl.scala 889:18] - node _T_1005 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44] - node _T_1006 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83] - node _T_1007 = mux(_T_1006, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63] - node _T_1008 = mux(_T_1005, UInt<2>("h01"), _T_1007) @[dec_decode_ctl.scala 890:24] - i0_rs1_depth_d <= _T_1008 @[dec_decode_ctl.scala 890:18] - node _T_1009 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 891:44] - node _T_1010 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 891:81] - wire _T_1011 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 891:109] - _T_1011.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109] - _T_1011.load <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109] - _T_1011.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 891:109] - node _T_1012 = mux(_T_1010, i0_r_c, _T_1011) @[dec_decode_ctl.scala 891:61] - node _T_1013 = mux(_T_1009, i0_x_c, _T_1012) @[dec_decode_ctl.scala 891:24] - i0_rs2_class_d.alu <= _T_1013.alu @[dec_decode_ctl.scala 891:18] - i0_rs2_class_d.load <= _T_1013.load @[dec_decode_ctl.scala 891:18] - i0_rs2_class_d.mul <= _T_1013.mul @[dec_decode_ctl.scala 891:18] - node _T_1014 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 892:44] - node _T_1015 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 892:83] - node _T_1016 = mux(_T_1015, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 892:63] - node _T_1017 = mux(_T_1014, UInt<2>("h01"), _T_1016) @[dec_decode_ctl.scala 892:24] - i0_rs2_depth_d <= _T_1017 @[dec_decode_ctl.scala 892:18] - i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 902:21] - node _T_1018 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 903:43] - node _T_1019 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 903:74] - node _T_1020 = and(_T_1018, _T_1019) @[dec_decode_ctl.scala 903:58] - node _T_1021 = and(_T_1020, i0_rs1_class_d.load) @[dec_decode_ctl.scala 903:78] - load_ldst_bypass_d <= _T_1021 @[dec_decode_ctl.scala 903:27] - node _T_1022 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 904:59] - node _T_1023 = and(i0_dp.store, _T_1022) @[dec_decode_ctl.scala 904:43] - node _T_1024 = and(_T_1023, i0_rs2_class_d.load) @[dec_decode_ctl.scala 904:63] - store_data_bypass_d <= _T_1024 @[dec_decode_ctl.scala 904:25] - store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 905:25] - node _T_1025 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73] - node _T_1026 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 909:130] - node i0_rs1_nonblock_load_bypass_en_d = and(_T_1025, _T_1026) @[dec_decode_ctl.scala 909:100] - node _T_1027 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 911:73] - node _T_1028 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 911:130] - node i0_rs2_nonblock_load_bypass_en_d = and(_T_1027, _T_1028) @[dec_decode_ctl.scala 911:100] - node _T_1029 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41] - node _T_1030 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 914:66] - node _T_1031 = and(_T_1029, _T_1030) @[dec_decode_ctl.scala 914:45] - node _T_1032 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 914:104] - node _T_1033 = and(_T_1032, i0_rs1_class_d.load) @[dec_decode_ctl.scala 914:108] - node _T_1034 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149] - node _T_1035 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 914:175] - node _T_1036 = or(_T_1035, i0_rs1_class_d.load) @[dec_decode_ctl.scala 914:196] - node _T_1037 = and(_T_1034, _T_1036) @[dec_decode_ctl.scala 914:153] - node _T_1038 = cat(_T_1031, _T_1033) @[Cat.scala 29:58] - node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 29:58] - i0_rs1bypass <= _T_1039 @[dec_decode_ctl.scala 914:18] - node _T_1040 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 916:41] - node _T_1041 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 916:67] - node _T_1042 = and(_T_1040, _T_1041) @[dec_decode_ctl.scala 916:45] - node _T_1043 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 916:105] - node _T_1044 = and(_T_1043, i0_rs2_class_d.load) @[dec_decode_ctl.scala 916:109] - node _T_1045 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 916:149] - node _T_1046 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 916:175] - node _T_1047 = or(_T_1046, i0_rs2_class_d.load) @[dec_decode_ctl.scala 916:196] - node _T_1048 = and(_T_1045, _T_1047) @[dec_decode_ctl.scala 916:153] - node _T_1049 = cat(_T_1042, _T_1044) @[Cat.scala 29:58] - node _T_1050 = cat(_T_1049, _T_1048) @[Cat.scala 29:58] - i0_rs2bypass <= _T_1050 @[dec_decode_ctl.scala 916:18] - node _T_1051 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 918:66] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_decode_ctl.scala 918:53] - node _T_1053 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 918:85] - node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[dec_decode_ctl.scala 918:72] - node _T_1055 = and(_T_1052, _T_1054) @[dec_decode_ctl.scala 918:70] - node _T_1056 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 918:104] - node _T_1057 = eq(_T_1056, UInt<1>("h00")) @[dec_decode_ctl.scala 918:91] - node _T_1058 = and(_T_1055, _T_1057) @[dec_decode_ctl.scala 918:89] - node _T_1059 = and(_T_1058, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 918:108] - node _T_1060 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 918:155] - node _T_1061 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 918:171] - node _T_1062 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 918:187] - node _T_1063 = cat(_T_1061, _T_1062) @[Cat.scala 29:58] - node _T_1064 = cat(_T_1059, _T_1060) @[Cat.scala 29:58] - node _T_1065 = cat(_T_1064, _T_1063) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1065 @[dec_decode_ctl.scala 918:45] - node _T_1066 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 919:66] - node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_decode_ctl.scala 919:53] - node _T_1068 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 919:85] - node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[dec_decode_ctl.scala 919:72] - node _T_1070 = and(_T_1067, _T_1069) @[dec_decode_ctl.scala 919:70] - node _T_1071 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 919:104] - node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_decode_ctl.scala 919:91] - node _T_1073 = and(_T_1070, _T_1072) @[dec_decode_ctl.scala 919:89] - node _T_1074 = and(_T_1073, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 919:108] - node _T_1075 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 919:155] - node _T_1076 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 919:171] - node _T_1077 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 919:187] - node _T_1078 = cat(_T_1076, _T_1077) @[Cat.scala 29:58] - node _T_1079 = cat(_T_1074, _T_1075) @[Cat.scala 29:58] - node _T_1080 = cat(_T_1079, _T_1078) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1080 @[dec_decode_ctl.scala 919:45] - io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 921:41] - node _T_1081 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 923:68] - node _T_1082 = and(io.dec_ib0_valid_d, _T_1081) @[dec_decode_ctl.scala 923:50] - node _T_1083 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 923:89] - node _T_1084 = and(_T_1082, _T_1083) @[dec_decode_ctl.scala 923:87] - node _T_1085 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 923:123] - node _T_1086 = and(_T_1084, _T_1085) @[dec_decode_ctl.scala 923:121] - node _T_1087 = or(_T_1086, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 923:140] - io.dec_lsu_valid_raw_d <= _T_1087 @[dec_decode_ctl.scala 923:26] - node _T_1088 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 925:6] - node _T_1089 = and(_T_1088, i0_dp.lsu) @[dec_decode_ctl.scala 925:38] - node _T_1090 = and(_T_1089, i0_dp.load) @[dec_decode_ctl.scala 925:50] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_decode_ctl.scala 925:64] - node _T_1092 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 925:81] - node _T_1093 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 926:6] - node _T_1094 = and(_T_1093, i0_dp.lsu) @[dec_decode_ctl.scala 926:38] - node _T_1095 = and(_T_1094, i0_dp.store) @[dec_decode_ctl.scala 926:50] - node _T_1096 = bits(_T_1095, 0, 0) @[dec_decode_ctl.scala 926:65] - node _T_1097 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 926:85] - node _T_1098 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 926:95] - node _T_1099 = cat(_T_1097, _T_1098) @[Cat.scala 29:58] - node _T_1100 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1101 = mux(_T_1096, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1102 = or(_T_1100, _T_1101) @[Mux.scala 27:72] - wire _T_1103 : UInt<12> @[Mux.scala 27:72] - _T_1103 <= _T_1102 @[Mux.scala 27:72] - io.dec_lsu_offset_d <= _T_1103 @[dec_decode_ctl.scala 924:23] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 872:27] + node _T_959 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_960 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_961 = bits(_T_959, 12, 1) @[lib.scala 68:24] + node _T_962 = bits(_T_960, 12, 1) @[lib.scala 68:40] + node _T_963 = add(_T_961, _T_962) @[lib.scala 68:31] + node _T_964 = bits(_T_959, 31, 13) @[lib.scala 69:20] + node _T_965 = add(_T_964, UInt<1>("h01")) @[lib.scala 69:27] + node _T_966 = tail(_T_965, 1) @[lib.scala 69:27] + node _T_967 = bits(_T_959, 31, 13) @[lib.scala 70:20] + node _T_968 = sub(_T_967, UInt<1>("h01")) @[lib.scala 70:27] + node _T_969 = tail(_T_968, 1) @[lib.scala 70:27] + node _T_970 = bits(_T_960, 12, 12) @[lib.scala 71:22] + node _T_971 = bits(_T_963, 12, 12) @[lib.scala 72:39] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[lib.scala 72:28] + node _T_973 = xor(_T_970, _T_972) @[lib.scala 72:26] + node _T_974 = bits(_T_973, 0, 0) @[lib.scala 72:64] + node _T_975 = bits(_T_959, 31, 13) @[lib.scala 72:76] + node _T_976 = eq(_T_970, UInt<1>("h00")) @[lib.scala 73:20] + node _T_977 = bits(_T_963, 12, 12) @[lib.scala 73:39] + node _T_978 = and(_T_976, _T_977) @[lib.scala 73:26] + node _T_979 = bits(_T_978, 0, 0) @[lib.scala 73:64] + node _T_980 = bits(_T_963, 12, 12) @[lib.scala 74:39] + node _T_981 = eq(_T_980, UInt<1>("h00")) @[lib.scala 74:28] + node _T_982 = and(_T_970, _T_981) @[lib.scala 74:26] + node _T_983 = bits(_T_982, 0, 0) @[lib.scala 74:64] + node _T_984 = mux(_T_974, _T_975, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_985 = mux(_T_979, _T_966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_986 = mux(_T_983, _T_969, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_987 = or(_T_984, _T_985) @[Mux.scala 27:72] + node _T_988 = or(_T_987, _T_986) @[Mux.scala 27:72] + wire _T_989 : UInt<19> @[Mux.scala 27:72] + _T_989 <= _T_988 @[Mux.scala 27:72] + node _T_990 = bits(_T_963, 11, 0) @[lib.scala 74:94] + node _T_991 = cat(_T_989, _T_990) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_991, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_992 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 877:62] + io.decode_exu.pred_correct_npc_x <= _T_992 @[dec_decode_ctl.scala 877:36] + node _T_993 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 881:59] + node _T_994 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 881:91] + node i0_rs1_depend_i0_x = and(_T_993, _T_994) @[dec_decode_ctl.scala 881:74] + node _T_995 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 882:59] + node _T_996 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 882:91] + node i0_rs1_depend_i0_r = and(_T_995, _T_996) @[dec_decode_ctl.scala 882:74] + node _T_997 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 884:59] + node _T_998 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 884:91] + node i0_rs2_depend_i0_x = and(_T_997, _T_998) @[dec_decode_ctl.scala 884:74] + node _T_999 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 885:59] + node _T_1000 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 885:91] + node i0_rs2_depend_i0_r = and(_T_999, _T_1000) @[dec_decode_ctl.scala 885:74] + node _T_1001 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 887:44] + node _T_1002 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 887:81] + wire _T_1003 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 887:109] + _T_1003.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1003.load <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1003.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + node _T_1004 = mux(_T_1002, i0_r_c, _T_1003) @[dec_decode_ctl.scala 887:61] + node _T_1005 = mux(_T_1001, i0_x_c, _T_1004) @[dec_decode_ctl.scala 887:24] + i0_rs1_class_d.alu <= _T_1005.alu @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.load <= _T_1005.load @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.mul <= _T_1005.mul @[dec_decode_ctl.scala 887:18] + node _T_1006 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 888:44] + node _T_1007 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 888:83] + node _T_1008 = mux(_T_1007, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 888:63] + node _T_1009 = mux(_T_1006, UInt<2>("h01"), _T_1008) @[dec_decode_ctl.scala 888:24] + i0_rs1_depth_d <= _T_1009 @[dec_decode_ctl.scala 888:18] + node _T_1010 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44] + node _T_1011 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81] + wire _T_1012 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109] + _T_1012.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1012.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1012.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + node _T_1013 = mux(_T_1011, i0_r_c, _T_1012) @[dec_decode_ctl.scala 889:61] + node _T_1014 = mux(_T_1010, i0_x_c, _T_1013) @[dec_decode_ctl.scala 889:24] + i0_rs2_class_d.alu <= _T_1014.alu @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.load <= _T_1014.load @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.mul <= _T_1014.mul @[dec_decode_ctl.scala 889:18] + node _T_1015 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44] + node _T_1016 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83] + node _T_1017 = mux(_T_1016, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63] + node _T_1018 = mux(_T_1015, UInt<2>("h01"), _T_1017) @[dec_decode_ctl.scala 890:24] + i0_rs2_depth_d <= _T_1018 @[dec_decode_ctl.scala 890:18] + i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 900:21] + node _T_1019 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 901:43] + node _T_1020 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 901:74] + node _T_1021 = and(_T_1019, _T_1020) @[dec_decode_ctl.scala 901:58] + node _T_1022 = and(_T_1021, i0_rs1_class_d.load) @[dec_decode_ctl.scala 901:78] + load_ldst_bypass_d <= _T_1022 @[dec_decode_ctl.scala 901:27] + node _T_1023 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 902:59] + node _T_1024 = and(i0_dp.store, _T_1023) @[dec_decode_ctl.scala 902:43] + node _T_1025 = and(_T_1024, i0_rs2_class_d.load) @[dec_decode_ctl.scala 902:63] + store_data_bypass_d <= _T_1025 @[dec_decode_ctl.scala 902:25] + store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 903:25] + node _T_1026 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 907:73] + node _T_1027 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 907:130] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_1026, _T_1027) @[dec_decode_ctl.scala 907:100] + node _T_1028 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73] + node _T_1029 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 909:130] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_1028, _T_1029) @[dec_decode_ctl.scala 909:100] + node _T_1030 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:41] + node _T_1031 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:66] + node _T_1032 = and(_T_1030, _T_1031) @[dec_decode_ctl.scala 912:45] + node _T_1033 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:104] + node _T_1034 = and(_T_1033, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:108] + node _T_1035 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 912:149] + node _T_1036 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:175] + node _T_1037 = or(_T_1036, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:196] + node _T_1038 = and(_T_1035, _T_1037) @[dec_decode_ctl.scala 912:153] + node _T_1039 = cat(_T_1032, _T_1034) @[Cat.scala 29:58] + node _T_1040 = cat(_T_1039, _T_1038) @[Cat.scala 29:58] + i0_rs1bypass <= _T_1040 @[dec_decode_ctl.scala 912:18] + node _T_1041 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41] + node _T_1042 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:67] + node _T_1043 = and(_T_1041, _T_1042) @[dec_decode_ctl.scala 914:45] + node _T_1044 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:105] + node _T_1045 = and(_T_1044, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:109] + node _T_1046 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149] + node _T_1047 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:175] + node _T_1048 = or(_T_1047, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:196] + node _T_1049 = and(_T_1046, _T_1048) @[dec_decode_ctl.scala 914:153] + node _T_1050 = cat(_T_1043, _T_1045) @[Cat.scala 29:58] + node _T_1051 = cat(_T_1050, _T_1049) @[Cat.scala 29:58] + i0_rs2bypass <= _T_1051 @[dec_decode_ctl.scala 914:18] + node _T_1052 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:66] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[dec_decode_ctl.scala 916:53] + node _T_1054 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:85] + node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[dec_decode_ctl.scala 916:72] + node _T_1056 = and(_T_1053, _T_1055) @[dec_decode_ctl.scala 916:70] + node _T_1057 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:104] + node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[dec_decode_ctl.scala 916:91] + node _T_1059 = and(_T_1056, _T_1058) @[dec_decode_ctl.scala 916:89] + node _T_1060 = and(_T_1059, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 916:108] + node _T_1061 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:155] + node _T_1062 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:171] + node _T_1063 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:187] + node _T_1064 = cat(_T_1062, _T_1063) @[Cat.scala 29:58] + node _T_1065 = cat(_T_1060, _T_1061) @[Cat.scala 29:58] + node _T_1066 = cat(_T_1065, _T_1064) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1066 @[dec_decode_ctl.scala 916:45] + node _T_1067 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:66] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_decode_ctl.scala 917:53] + node _T_1069 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:85] + node _T_1070 = eq(_T_1069, UInt<1>("h00")) @[dec_decode_ctl.scala 917:72] + node _T_1071 = and(_T_1068, _T_1070) @[dec_decode_ctl.scala 917:70] + node _T_1072 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:104] + node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[dec_decode_ctl.scala 917:91] + node _T_1074 = and(_T_1071, _T_1073) @[dec_decode_ctl.scala 917:89] + node _T_1075 = and(_T_1074, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 917:108] + node _T_1076 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:155] + node _T_1077 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:171] + node _T_1078 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:187] + node _T_1079 = cat(_T_1077, _T_1078) @[Cat.scala 29:58] + node _T_1080 = cat(_T_1075, _T_1076) @[Cat.scala 29:58] + node _T_1081 = cat(_T_1080, _T_1079) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1081 @[dec_decode_ctl.scala 917:45] + io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 919:41] + node _T_1082 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 921:68] + node _T_1083 = and(io.dec_ib0_valid_d, _T_1082) @[dec_decode_ctl.scala 921:50] + node _T_1084 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 921:89] + node _T_1085 = and(_T_1083, _T_1084) @[dec_decode_ctl.scala 921:87] + node _T_1086 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 921:123] + node _T_1087 = and(_T_1085, _T_1086) @[dec_decode_ctl.scala 921:121] + node _T_1088 = or(_T_1087, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 921:140] + io.dec_lsu_valid_raw_d <= _T_1088 @[dec_decode_ctl.scala 921:26] + node _T_1089 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 923:6] + node _T_1090 = and(_T_1089, i0_dp.lsu) @[dec_decode_ctl.scala 923:38] + node _T_1091 = and(_T_1090, i0_dp.load) @[dec_decode_ctl.scala 923:50] + node _T_1092 = bits(_T_1091, 0, 0) @[dec_decode_ctl.scala 923:64] + node _T_1093 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 923:81] + node _T_1094 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 924:6] + node _T_1095 = and(_T_1094, i0_dp.lsu) @[dec_decode_ctl.scala 924:38] + node _T_1096 = and(_T_1095, i0_dp.store) @[dec_decode_ctl.scala 924:50] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_decode_ctl.scala 924:65] + node _T_1098 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 924:85] + node _T_1099 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 924:95] + node _T_1100 = cat(_T_1098, _T_1099) @[Cat.scala 29:58] + node _T_1101 = mux(_T_1092, _T_1093, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1097, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1101, _T_1102) @[Mux.scala 27:72] + wire _T_1104 : UInt<12> @[Mux.scala 27:72] + _T_1104 <= _T_1103 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1104 @[dec_decode_ctl.scala 922:23] extmodule gated_latch_11 : output Q : Clock @@ -14103,22 +14104,22 @@ circuit dec : node mcgc = cat(_T_376, _T_377) @[Cat.scala 29:58] node _T_378 = bits(mcgc, 9, 9) @[dec_tlu_ctl.scala 1756:46] io.dec_tlu_picio_clk_override <= _T_378 @[dec_tlu_ctl.scala 1756:39] - node _T_379 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1757:45] - io.dec_tlu_misc_clk_override <= _T_379 @[dec_tlu_ctl.scala 1757:38] - node _T_380 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1758:45] - io.dec_tlu_dec_clk_override <= _T_380 @[dec_tlu_ctl.scala 1758:38] - node _T_381 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1759:45] - io.dec_tlu_ifu_clk_override <= _T_381 @[dec_tlu_ctl.scala 1759:38] - node _T_382 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1760:45] - io.dec_tlu_lsu_clk_override <= _T_382 @[dec_tlu_ctl.scala 1760:38] - node _T_383 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1761:45] - io.dec_tlu_bus_clk_override <= _T_383 @[dec_tlu_ctl.scala 1761:38] - node _T_384 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1762:45] - io.dec_tlu_pic_clk_override <= _T_384 @[dec_tlu_ctl.scala 1762:38] - node _T_385 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1763:45] - io.dec_tlu_dccm_clk_override <= _T_385 @[dec_tlu_ctl.scala 1763:38] - node _T_386 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1764:45] - io.dec_tlu_icm_clk_override <= _T_386 @[dec_tlu_ctl.scala 1764:38] + node _T_379 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1757:46] + io.dec_tlu_misc_clk_override <= _T_379 @[dec_tlu_ctl.scala 1757:39] + node _T_380 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1758:46] + io.dec_tlu_dec_clk_override <= _T_380 @[dec_tlu_ctl.scala 1758:39] + node _T_381 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1759:46] + io.dec_tlu_ifu_clk_override <= _T_381 @[dec_tlu_ctl.scala 1759:39] + node _T_382 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1760:46] + io.dec_tlu_lsu_clk_override <= _T_382 @[dec_tlu_ctl.scala 1760:39] + node _T_383 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1761:46] + io.dec_tlu_bus_clk_override <= _T_383 @[dec_tlu_ctl.scala 1761:39] + node _T_384 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_pic_clk_override <= _T_384 @[dec_tlu_ctl.scala 1762:39] + node _T_385 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_dccm_clk_override <= _T_385 @[dec_tlu_ctl.scala 1763:39] + node _T_386 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_icm_clk_override <= _T_386 @[dec_tlu_ctl.scala 1764:39] node _T_387 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1785:68] node _T_388 = eq(_T_387, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1785:75] node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_388) @[dec_tlu_ctl.scala 1785:46] diff --git a/dec.v b/dec.v index c8ac23c8..f8bf2257 100644 --- a/dec.v +++ b/dec.v @@ -2075,7 +2075,7 @@ module dec_decode_ctl( wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 454:33] wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 455:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 680:16] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16] wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 455:76] wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 455:98] wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 455:89] @@ -2090,7 +2090,7 @@ module dec_decode_ctl( wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 463:37] wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 463:65] wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 463:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 678:16] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16] wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 463:89] wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 463:111] wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 463:101] @@ -2124,16 +2124,44 @@ module dec_decode_ctl( wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 521:42] wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 521:40] wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 529:34] - wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 592:40] - wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 592:51] - wire i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 592:37] - wire _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 596:49] - wire shift_illegal = io_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 596:47] + wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40] + wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51] + wire _T_546 = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37] + wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50] + wire bitmanip_zbe_legal = ~i0_dp_zbe; // @[dec_decode_ctl.scala 723:32] + wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50] + wire bitmanip_zbc_legal = ~i0_dp_zbc; // @[dec_decode_ctl.scala 728:32] + wire _T_801 = bitmanip_zbe_legal & bitmanip_zbc_legal; // @[dec_decode_ctl.scala 755:83] + wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50] + wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50] + wire _T_793 = ~i0_dp_zbb; // @[dec_decode_ctl.scala 733:46] + wire _T_794 = i0_dp_zbp & _T_793; // @[dec_decode_ctl.scala 733:44] + wire bitmanip_zbp_legal = ~_T_794; // @[dec_decode_ctl.scala 733:32] + wire _T_802 = _T_801 & bitmanip_zbp_legal; // @[dec_decode_ctl.scala 755:104] + wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50] + wire bitmanip_zbr_legal = ~i0_dp_zbr; // @[dec_decode_ctl.scala 738:32] + wire _T_803 = _T_802 & bitmanip_zbr_legal; // @[dec_decode_ctl.scala 755:125] + wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50] + wire bitmanip_zbf_legal = ~i0_dp_zbf; // @[dec_decode_ctl.scala 743:32] + wire _T_804 = _T_803 & bitmanip_zbf_legal; // @[dec_decode_ctl.scala 755:146] + wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] + wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50] + wire bitmanip_zba_legal = ~i0_dp_zba; // @[dec_decode_ctl.scala 748:32] + wire bitmanip_legal = _T_804 & bitmanip_zba_legal; // @[dec_decode_ctl.scala 755:167] + wire i0_legal = _T_546 & bitmanip_legal; // @[dec_decode_ctl.scala 590:73] + wire _T_564 = ~i0_legal; // @[dec_decode_ctl.scala 594:49] + wire shift_illegal = io_dec_i0_decode_d & _T_564; // @[dec_decode_ctl.scala 594:47] reg illegal_lockout; // @[Reg.scala 27:20] - wire _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 599:40] + wire _T_567 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40] reg flush_final_r; // @[Reg.scala 27:20] - wire _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 599:61] - wire illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 599:59] + wire _T_568 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61] + wire illegal_lockout_in = _T_567 & _T_568; // @[dec_decode_ctl.scala 597:59] wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21] wire _T_27 = |_T_26; // @[lib.scala 448:29] wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] @@ -2146,12 +2174,12 @@ module dec_decode_ctl( wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 588:112] wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 588:99] wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 588:76] - wire _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 630:54] - wire _T_606 = io_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 630:39] + wire _T_606 = i0_postsync | _T_564; // @[dec_decode_ctl.scala 628:54] + wire _T_607 = io_dec_i0_decode_d & _T_606; // @[dec_decode_ctl.scala 628:39] reg postsync_stall; // @[Reg.scala 27:20] reg x_d_valid; // @[Reg.scala 27:20] - wire _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 630:88] - wire ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 630:69] + wire _T_608 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:88] + wire ps_stall_in = _T_607 | _T_608; // @[dec_decode_ctl.scala 628:69] wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21] wire _T_31 = |_T_30; // @[lib.scala 448:29] reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20] @@ -2160,42 +2188,42 @@ module dec_decode_ctl( reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20] wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21] wire _T_37 = |_T_36; // @[lib.scala 470:29] - wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 758:46] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:46] wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 282:50] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 845:55] - wire _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 847:59] - wire _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 847:57] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55] + wire _T_935 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59] + wire _T_936 = io_dec_div_active & _T_935; // @[dec_decode_ctl.scala 845:57] reg x_d_bits_i0div; // @[Reg.scala 27:20] - wire _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 835:48] + wire _T_919 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48] reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20] - wire _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 835:77] - wire _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 835:60] - wire _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 836:33] - wire _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 835:94] + wire _T_920 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77] + wire _T_921 = _T_919 & _T_920; // @[dec_decode_ctl.scala 833:60] + wire _T_923 = _T_919 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33] + wire _T_924 = _T_921 | _T_923; // @[dec_decode_ctl.scala 833:94] reg r_d_bits_i0div; // @[Reg.scala 27:20] reg r_d_valid; // @[Reg.scala 27:20] - wire _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 837:21] - wire _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 837:33] - wire _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 837:60] - wire div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 836:62] - wire _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 841:51] - wire div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 833:58] - wire _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 842:26] - wire _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 842:24] + wire _T_925 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21] + wire _T_926 = _T_925 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33] + wire _T_927 = _T_926 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60] + wire div_flush = _T_924 | _T_927; // @[dec_decode_ctl.scala 834:62] + wire _T_928 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51] + wire div_e1_to_r = _T_919 | _T_925; // @[dec_decode_ctl.scala 831:58] + wire _T_929 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26] + wire _T_930 = io_dec_div_active & _T_929; // @[dec_decode_ctl.scala 840:24] reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20] - wire _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 842:56] - wire _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 842:39] + wire _T_931 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56] + wire _T_932 = _T_930 & _T_931; // @[dec_decode_ctl.scala 840:39] reg r_d_bits_i0v; // @[Reg.scala 27:20] - wire _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 800:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 800:49] - wire _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 808:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 808:45] - wire _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 842:77] - wire nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 841:65] - wire _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 847:78] - wire _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 847:76] - wire div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 847:36] + wire _T_858 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 798:49] + wire _T_869 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_869; // @[dec_decode_ctl.scala 806:45] + wire _T_933 = _T_932 & i0_wen_r; // @[dec_decode_ctl.scala 840:77] + wire nonblock_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 839:65] + wire _T_937 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78] + wire _T_938 = _T_936 & _T_937; // @[dec_decode_ctl.scala 845:76] + wire div_active_in = i0_div_decode_d | _T_938; // @[dec_decode_ctl.scala 845:36] reg _T_42; // @[Reg.scala 27:20] wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21] wire _T_41 = |_T_40; // @[lib.scala 470:29] @@ -2274,33 +2302,21 @@ module dec_decode_ctl( wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 282:50] - wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] @@ -2309,8 +2325,6 @@ module dec_decode_ctl( wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] - wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50] wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] @@ -2386,10 +2400,10 @@ module dec_decode_ctl( wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72] reg x_d_bits_i0load; // @[Reg.scala 27:20] wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 361:31] - reg [2:0] _T_815; // @[dec_decode_ctl.scala 766:72] - wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58] - wire _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 769:49] - wire i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 769:53] + reg [2:0] _T_816; // @[dec_decode_ctl.scala 764:72] + wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_816}; // @[Cat.scala 29:58] + wire _T_822 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49] + wire i0_r_ctl_en = _T_822 | io_clk_override; // @[dec_decode_ctl.scala 767:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg r_d_bits_i0load; // @[Reg.scala 27:20] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 366:56] @@ -2520,7 +2534,7 @@ module dec_decode_ctl( wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 402:54] wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:66] wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 402:110] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 679:16] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16] wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 402:161] wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:173] wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 402:217] @@ -2606,35 +2620,35 @@ module dec_decode_ctl( wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 466:50] wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 466:67] wire _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 510:41] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 635:40] - wire _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 903:43] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40] + wire _T_1019 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43] reg x_d_bits_i0v; // @[Reg.scala 27:20] - wire _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 883:59] - wire _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 883:91] - wire i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 883:74] - wire _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 884:59] - wire _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 884:91] - wire i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 884:74] - wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 890:24] - wire _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 903:58] + wire _T_993 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59] + wire _T_994 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91] + wire i0_rs1_depend_i0_x = _T_993 & _T_994; // @[dec_decode_ctl.scala 881:74] + wire _T_995 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59] + wire _T_996 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91] + wire i0_rs1_depend_i0_r = _T_995 & _T_996; // @[dec_decode_ctl.scala 882:74] + wire [1:0] _T_1008 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1008; // @[dec_decode_ctl.scala 888:24] + wire _T_1021 = _T_1019 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58] reg i0_x_c_load; // @[Reg.scala 27:20] reg i0_r_c_load; // @[Reg.scala 27:20] - wire _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 889:24] - wire load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 903:78] - wire _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 886:59] - wire _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 886:91] - wire i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 886:74] - wire _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 887:59] - wire _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 887:91] - wire i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 887:74] - wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 892:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 892:24] - wire _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 904:43] - wire _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 891:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 891:24] - wire store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 904:63] + wire _T_1004_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1004_load; // @[dec_decode_ctl.scala 887:24] + wire load_ldst_bypass_d = _T_1021 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78] + wire _T_997 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59] + wire _T_998 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91] + wire i0_rs2_depend_i0_x = _T_997 & _T_998; // @[dec_decode_ctl.scala 884:74] + wire _T_999 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59] + wire _T_1000 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91] + wire i0_rs2_depend_i0_r = _T_999 & _T_1000; // @[dec_decode_ctl.scala 885:74] + wire [1:0] _T_1017 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1017; // @[dec_decode_ctl.scala 890:24] + wire _T_1024 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43] + wire _T_1013_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1013_load; // @[dec_decode_ctl.scala 889:24] + wire store_data_bypass_d = _T_1024 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63] wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 527:42] wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 527:58] wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] @@ -2653,7 +2667,7 @@ module dec_decode_ctl( reg csr_set_x; // @[dec_decode_ctl.scala 543:51] reg csr_write_x; // @[dec_decode_ctl.scala 544:53] reg csr_imm_x; // @[dec_decode_ctl.scala 545:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 771:50] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50] wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 548:48] reg [4:0] csrimm_x; // @[Reg.scala 27:20] reg [31:0] csr_rddata_x; // @[Reg.scala 27:20] @@ -2681,9 +2695,9 @@ module dec_decode_ctl( wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 569:99] reg r_d_bits_csrwonly; // @[Reg.scala 27:20] wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 576:50] - wire _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 824:42] + wire _T_882 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42] reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20] - wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 824:27] + wire [31:0] i0_result_corr_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27] reg x_d_bits_csrwonly; // @[Reg.scala 27:20] wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 578:43] reg wbd_bits_csrwonly; // @[Reg.scala 27:20] @@ -2694,59 +2708,59 @@ module dec_decode_ctl( wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 585:57] wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 585:73] wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 585:91] - wire [31:0] _T_562 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 597:44] - wire illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 597:42] - reg [31:0] _T_565; // @[Reg.scala 27:20] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 600:42] - wire _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 602:40] - wire _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 602:59] - wire _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 602:92] - wire _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 602:106] - wire _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 603:20] - wire _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 603:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 625:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 626:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 628:37] - wire _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 603:62] - wire _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 604:19] - wire _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 604:36] - wire _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 604:34] - wire _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 603:79] - wire _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 604:47] - wire _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 852:60] - wire _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 852:99] - wire _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 852:80] - wire _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 853:36] - wire _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 853:75] - wire _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 853:56] - wire i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 852:113] - wire _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 605:21] - wire i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 605:45] - wire _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 607:65] - wire i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 607:39] - wire _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 608:63] - wire i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 608:38] - wire _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 609:38] - wire i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 609:57] - wire _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 613:46] - wire _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 613:44] - wire _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 613:61] - wire _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 614:46] - wire _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 614:44] - wire _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 614:61] - wire i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 614:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 615:46] - wire _T_597 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 619:51] - wire _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 633:53] - wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 643:40] - wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 644:58] - wire _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 647:44] - wire d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 647:61] - wire [3:0] _T_624 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 654:56] - wire _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 768:49] - wire i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 768:53] + wire [31:0] _T_563 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] + wire _T_565 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44] + wire illegal_inst_en = shift_illegal & _T_565; // @[dec_decode_ctl.scala 595:42] + reg [31:0] _T_566; // @[Reg.scala 27:20] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42] + wire _T_570 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40] + wire _T_571 = _T_570 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59] + wire _T_572 = _T_571 | pause_stall; // @[dec_decode_ctl.scala 600:92] + wire _T_573 = _T_572 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106] + wire _T_574 = _T_573 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20] + wire _T_575 = _T_574 | postsync_stall; // @[dec_decode_ctl.scala 601:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37] + wire _T_576 = _T_575 | presync_stall; // @[dec_decode_ctl.scala 601:62] + wire _T_577 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19] + wire _T_578 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36] + wire _T_579 = _T_577 & _T_578; // @[dec_decode_ctl.scala 602:34] + wire _T_580 = _T_576 | _T_579; // @[dec_decode_ctl.scala 601:79] + wire _T_581 = _T_580 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47] + wire _T_940 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60] + wire _T_941 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99] + wire _T_942 = _T_940 & _T_941; // @[dec_decode_ctl.scala 850:80] + wire _T_943 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36] + wire _T_944 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75] + wire _T_945 = _T_943 & _T_944; // @[dec_decode_ctl.scala 851:56] + wire i0_nonblock_div_stall = _T_942 | _T_945; // @[dec_decode_ctl.scala 850:113] + wire _T_583 = _T_581 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21] + wire i0_block_raw_d = _T_583 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45] + wire _T_584 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65] + wire i0_store_stall_d = i0_dp_store & _T_584; // @[dec_decode_ctl.scala 605:39] + wire _T_585 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63] + wire i0_load_stall_d = i0_dp_load & _T_585; // @[dec_decode_ctl.scala 606:38] + wire _T_586 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38] + wire i0_block_d = _T_586 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57] + wire _T_587 = ~i0_block_d; // @[dec_decode_ctl.scala 611:46] + wire _T_588 = io_dec_ib0_valid_d & _T_587; // @[dec_decode_ctl.scala 611:44] + wire _T_590 = _T_588 & _T_367; // @[dec_decode_ctl.scala 611:61] + wire _T_593 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46] + wire _T_594 = io_dec_ib0_valid_d & _T_593; // @[dec_decode_ctl.scala 612:44] + wire _T_596 = _T_594 & _T_367; // @[dec_decode_ctl.scala 612:61] + wire i0_exudecode_d = _T_596 & _T_568; // @[dec_decode_ctl.scala 612:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46] + wire _T_598 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51] + wire _T_611 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53] + wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40] + wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58] + wire _T_620 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44] + wire d_t_fence_i = _T_620 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61] + wire [3:0] _T_625 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] + wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_625; // @[dec_decode_ctl.scala 652:56] + wire _T_819 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49] + wire i0_x_ctl_en = _T_819 | io_clk_override; // @[dec_decode_ctl.scala 766:53] reg x_t_legal; // @[Reg.scala 27:20] reg x_t_icaf; // @[Reg.scala 27:20] reg x_t_icaf_second; // @[Reg.scala 27:20] @@ -2755,9 +2769,9 @@ module dec_decode_ctl( reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20] reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20] reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] - wire [3:0] _T_632 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 660:39] - wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 660:37] + wire [3:0] _T_633 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] + wire [3:0] _T_634 = ~_T_633; // @[dec_decode_ctl.scala 658:39] + wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_634; // @[dec_decode_ctl.scala 658:37] reg r_t_legal; // @[Reg.scala 27:20] reg r_t_icaf; // @[Reg.scala 27:20] reg r_t_icaf_second; // @[Reg.scala 27:20] @@ -2767,146 +2781,146 @@ module dec_decode_ctl( reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20] reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] reg r_d_bits_i0store; // @[Reg.scala 27:20] - wire _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 666:61] - wire [3:0] _T_642 = {_T_638,_T_638,_T_638,_T_638}; // @[Cat.scala 29:58] - wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 666:82] - wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 666:105] - wire _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 682:60] - wire _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 683:60] - wire _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 684:48] - wire i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 684:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 688:38] - wire _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 689:27] - wire i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 689:38] - wire [9:0] _T_673 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] - wire [18:0] _T_682 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] - wire [31:0] _T_685 = {_T_682,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] - wire [31:0] _T_714 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] - wire [31:0] _T_734 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_748 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] - wire _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 700:26] - wire [31:0] _T_779 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] - wire [31:0] _T_780 = i0_dp_imm12 ? _T_685 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_781 = i0_dp_shimm5 ? _T_714 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_782 = i0_jalimm20 ? _T_734 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_783 = i0_uiimm20 ? _T_748 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_784 = _T_749 ? _T_779 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_785 = _T_780 | _T_781; // @[Mux.scala 27:72] - wire [31:0] _T_786 = _T_785 | _T_782; // @[Mux.scala 27:72] + wire _T_639 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61] + wire [3:0] _T_643 = {_T_639,_T_639,_T_639,_T_639}; // @[Cat.scala 29:58] + wire [3:0] _T_644 = _T_643 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82] + wire [3:0] _T_645 = _T_644 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105] + wire _T_658 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60] + wire _T_660 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60] + wire _T_662 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48] + wire i0_rd_en_d = i0_dp_rd & _T_662; // @[dec_decode_ctl.scala 682:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38] + wire _T_663 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27] + wire i0_uiimm20 = _T_663 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38] + wire [9:0] _T_674 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_683 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [31:0] _T_686 = {_T_683,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] + wire [31:0] _T_715 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] + wire [31:0] _T_735 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_749 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] + wire _T_750 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26] + wire [31:0] _T_780 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] + wire [31:0] _T_781 = i0_dp_imm12 ? _T_686 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_782 = i0_dp_shimm5 ? _T_715 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_783 = i0_jalimm20 ? _T_735 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_784 = i0_uiimm20 ? _T_749 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_750 ? _T_780 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_781 | _T_782; // @[Mux.scala 27:72] wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 761:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 762:44] + wire [31:0] _T_788 = _T_787 | _T_784; // @[Mux.scala 27:72] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44] reg i0_x_c_mul; // @[Reg.scala 27:20] reg i0_x_c_alu; // @[Reg.scala 27:20] reg i0_r_c_mul; // @[Reg.scala 27:20] reg i0_r_c_alu; // @[Reg.scala 27:20] - wire _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 770:49] - wire i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 770:53] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 772:50] - wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 773:50] - wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 779:50] - wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 783:50] - wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:50] - wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 786:61] - wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 787:58] + wire _T_825 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49] + wire i0_wb_ctl_en = _T_825 | io_clk_override; // @[dec_decode_ctl.scala 768:53] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50] + wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50] + wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50] + wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50] + wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50] + wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61] + wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58] reg x_d_bits_i0store; // @[Reg.scala 27:20] reg x_d_bits_csrwen; // @[Reg.scala 27:20] reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20] - wire _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 793:47] - wire x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 793:76] - wire _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 794:33] - wire x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 794:62] - wire _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 809:49] - wire _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 809:47] - wire _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 809:70] - wire _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 813:74] - wire _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 813:92] - wire _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 813:58] - wire _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 819:47] - wire _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 825:71] - wire [11:0] _T_898 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + wire _T_848 = x_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 791:47] + wire x_d_in_bits_i0v = _T_848 & _T_367; // @[dec_decode_ctl.scala 791:76] + wire _T_852 = x_d_valid & _T_858; // @[dec_decode_ctl.scala 792:33] + wire x_d_in_valid = _T_852 & _T_367; // @[dec_decode_ctl.scala 792:62] + wire _T_871 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49] + wire _T_872 = i0_wen_r & _T_871; // @[dec_decode_ctl.scala 807:47] + wire _T_873 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70] + wire _T_875 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74] + wire _T_876 = _T_875 | debug_valid_x; // @[dec_decode_ctl.scala 811:92] + wire _T_877 = i0_r_data_en & _T_876; // @[dec_decode_ctl.scala 811:58] + wire _T_879 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47] + wire _T_886 = io_decode_exu_i0_ap_predict_nt & _T_663; // @[dec_decode_ctl.scala 823:71] + wire [11:0] _T_899 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[Reg.scala 27:20] - wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 860:22] - reg [4:0] _T_947; // @[Reg.scala 27:20] - wire _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 864:50] + wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22] + reg [4:0] _T_948; // @[Reg.scala 27:20] + wire _T_949 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50] reg [31:0] i0_inst_x; // @[Reg.scala 27:20] - wire _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 865:50] + wire _T_951 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50] reg [31:0] i0_inst_r; // @[Reg.scala 27:20] - wire _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 867:51] + wire _T_953 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51] reg [31:0] i0_inst_wb; // @[Reg.scala 27:20] reg [30:0] i0_pc_wb; // @[Reg.scala 27:20] reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20] - wire [31:0] _T_958 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_959 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_962 = _T_958[12:1] + _T_959[12:1]; // @[lib.scala 68:31] - wire [18:0] _T_965 = _T_958[31:13] + 19'h1; // @[lib.scala 69:27] - wire [18:0] _T_968 = _T_958[31:13] - 19'h1; // @[lib.scala 70:27] - wire _T_971 = ~_T_962[12]; // @[lib.scala 72:28] - wire _T_972 = _T_959[12] ^ _T_971; // @[lib.scala 72:26] - wire _T_975 = ~_T_959[12]; // @[lib.scala 73:20] - wire _T_977 = _T_975 & _T_962[12]; // @[lib.scala 73:26] - wire _T_981 = _T_959[12] & _T_971; // @[lib.scala 74:26] - wire [18:0] _T_983 = _T_972 ? _T_958[31:13] : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_984 = _T_977 ? _T_965 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_985 = _T_981 ? _T_968 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_986 = _T_983 | _T_984; // @[Mux.scala 27:72] - wire [18:0] _T_987 = _T_986 | _T_985; // @[Mux.scala 27:72] - wire [31:0] temp_pred_correct_npc_x = {_T_987,_T_962[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61] - wire _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 889:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 889:24] - wire _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 891:61] - wire _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 891:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 891:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 891:24] - wire _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73] - wire _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 909:130] - wire i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 909:100] - wire _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 911:73] - wire _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 911:130] - wire i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 911:100] - wire _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 914:66] - wire _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 914:45] - wire _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:108] - wire _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:196] - wire _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 914:153] - wire [2:0] i0_rs1bypass = {_T_1031,_T_1033,_T_1037}; // @[Cat.scala 29:58] - wire _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 916:67] - wire _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 916:45] - wire _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:109] - wire _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:196] - wire _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 916:153] - wire [2:0] i0_rs2bypass = {_T_1042,_T_1044,_T_1048}; // @[Cat.scala 29:58] - wire _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 918:53] - wire _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 918:72] - wire _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 918:70] - wire _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 918:91] - wire _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 918:89] - wire _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 918:108] - wire [1:0] _T_1063 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_1064 = {_T_1059,i0_rs1bypass[2]}; // @[Cat.scala 29:58] - wire _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 919:53] - wire _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 919:72] - wire _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 919:70] - wire _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 919:91] - wire _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 919:89] - wire _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 919:108] - wire [1:0] _T_1078 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_1079 = {_T_1074,i0_rs2bypass[2]}; // @[Cat.scala 29:58] - wire _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 923:68] - wire _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 923:50] - wire _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 923:89] - wire _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 923:87] - wire _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 923:121] - wire _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 925:6] - wire _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 925:38] - wire _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 925:50] - wire _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 926:50] - wire [11:0] _T_1099 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] - wire [11:0] _T_1100 = _T_1090 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] - wire [11:0] _T_1101 = _T_1095 ? _T_1099 : 12'h0; // @[Mux.scala 27:72] + wire [31:0] _T_959 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_960 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_963 = _T_959[12:1] + _T_960[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_966 = _T_959[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_969 = _T_959[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_972 = ~_T_963[12]; // @[lib.scala 72:28] + wire _T_973 = _T_960[12] ^ _T_972; // @[lib.scala 72:26] + wire _T_976 = ~_T_960[12]; // @[lib.scala 73:20] + wire _T_978 = _T_976 & _T_963[12]; // @[lib.scala 73:26] + wire _T_982 = _T_960[12] & _T_972; // @[lib.scala 74:26] + wire [18:0] _T_984 = _T_973 ? _T_959[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_985 = _T_978 ? _T_966 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_986 = _T_982 ? _T_969 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72] + wire [18:0] _T_988 = _T_987 | _T_986; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_988,_T_963[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_1004_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61] + wire _T_1004_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1004_mul; // @[dec_decode_ctl.scala 887:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1004_alu; // @[dec_decode_ctl.scala 887:24] + wire _T_1013_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61] + wire _T_1013_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1013_mul; // @[dec_decode_ctl.scala 889:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1013_alu; // @[dec_decode_ctl.scala 889:24] + wire _T_1026 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73] + wire _T_1027 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130] + wire i0_rs1_nonblock_load_bypass_en_d = _T_1026 & _T_1027; // @[dec_decode_ctl.scala 907:100] + wire _T_1028 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73] + wire _T_1029 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130] + wire i0_rs2_nonblock_load_bypass_en_d = _T_1028 & _T_1029; // @[dec_decode_ctl.scala 909:100] + wire _T_1031 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66] + wire _T_1032 = i0_rs1_depth_d[0] & _T_1031; // @[dec_decode_ctl.scala 912:45] + wire _T_1034 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108] + wire _T_1037 = _T_1031 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196] + wire _T_1038 = i0_rs1_depth_d[1] & _T_1037; // @[dec_decode_ctl.scala 912:153] + wire [2:0] i0_rs1bypass = {_T_1032,_T_1034,_T_1038}; // @[Cat.scala 29:58] + wire _T_1042 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67] + wire _T_1043 = i0_rs2_depth_d[0] & _T_1042; // @[dec_decode_ctl.scala 914:45] + wire _T_1045 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109] + wire _T_1048 = _T_1042 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196] + wire _T_1049 = i0_rs2_depth_d[1] & _T_1048; // @[dec_decode_ctl.scala 914:153] + wire [2:0] i0_rs2bypass = {_T_1043,_T_1045,_T_1049}; // @[Cat.scala 29:58] + wire _T_1053 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53] + wire _T_1055 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72] + wire _T_1056 = _T_1053 & _T_1055; // @[dec_decode_ctl.scala 916:70] + wire _T_1058 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91] + wire _T_1059 = _T_1056 & _T_1058; // @[dec_decode_ctl.scala 916:89] + wire _T_1060 = _T_1059 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108] + wire [1:0] _T_1064 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1065 = {_T_1060,i0_rs1bypass[2]}; // @[Cat.scala 29:58] + wire _T_1068 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53] + wire _T_1070 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72] + wire _T_1071 = _T_1068 & _T_1070; // @[dec_decode_ctl.scala 917:70] + wire _T_1073 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91] + wire _T_1074 = _T_1071 & _T_1073; // @[dec_decode_ctl.scala 917:89] + wire _T_1075 = _T_1074 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108] + wire [1:0] _T_1079 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1080 = {_T_1075,i0_rs2bypass[2]}; // @[Cat.scala 29:58] + wire _T_1082 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68] + wire _T_1083 = io_dec_ib0_valid_d & _T_1082; // @[dec_decode_ctl.scala 921:50] + wire _T_1084 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89] + wire _T_1085 = _T_1083 & _T_1084; // @[dec_decode_ctl.scala 921:87] + wire _T_1087 = _T_1085 & _T_593; // @[dec_decode_ctl.scala 921:121] + wire _T_1089 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6] + wire _T_1090 = _T_1089 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38] + wire _T_1091 = _T_1090 & i0_dp_load; // @[dec_decode_ctl.scala 923:50] + wire _T_1096 = _T_1090 & i0_dp_store; // @[dec_decode_ctl.scala 924:50] + wire [11:0] _T_1100 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1101 = _T_1091 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1102 = _T_1096 ? _T_1100 : 12'h0; // @[Mux.scala 27:72] dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 440:22] .io_ins(i0_dec_io_ins), .io_out_clz(i0_dec_io_out_clz), @@ -3049,8 +3063,8 @@ module dec_decode_ctl( .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en) ); - assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 775:38] - assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 776:38] + assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38] + assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38] assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 319:33] assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 320:33] assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 321:33] @@ -3109,15 +3123,15 @@ module dec_decode_ctl( assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 247:58] assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 243:58] assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 244:58] - assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 682:35] - assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 633:37] - assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 683:35] - assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 695:32] - assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 921:41] - assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 638:32] + assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_658; // @[dec_decode_ctl.scala 680:35] + assign io_decode_exu_dec_i0_branch_d = _T_611 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37] + assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_660; // @[dec_decode_ctl.scala 681:35] + assign io_decode_exu_dec_i0_immed_d = _T_788 | _T_785; // @[dec_decode_ctl.scala 693:32] + assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41] + assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:32] assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 293:36] - assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 918:45] - assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 919:45] + assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1065,_T_1064}; // @[dec_decode_ctl.scala 916:45] + assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1080,_T_1079}; // @[dec_decode_ctl.scala 917:45] assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 473:32] assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 474:37] assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 475:37] @@ -3138,22 +3152,22 @@ module dec_decode_ctl( assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 490:37] assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 491:37] assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 492:37] - assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 879:36] + assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36] assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 210:35] - assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 632:34] + assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34] assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 518:29] - assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 825:32] + assign io_dec_alu_dec_i0_br_immed_d = _T_886 ? i0_br_offset : _T_899; // @[dec_decode_ctl.scala 823:32] assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 469:29] assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 470:34] assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 471:34] - assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 844:37] - assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 870:21] - assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 871:19] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 685:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 686:19] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 807:27] - assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 809:32] - assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 810:26] + assign io_dec_div_dec_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 842:37] + assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21] + assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27] + assign io_dec_i0_wen_r = _T_872 & _T_873; // @[dec_decode_ctl.scala 807:32] + assign io_dec_i0_wdata_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26] assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 500:24 dec_decode_ctl.scala 504:35] assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 499:29] assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 510:29] @@ -3165,39 +3179,39 @@ module dec_decode_ctl( assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 514:40] assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 512:40] assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 511:40] - assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 862:19] - assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:26] - assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 924:23] + assign io_div_waddr_wb = _T_948; // @[dec_decode_ctl.scala 860:19] + assign io_dec_lsu_valid_raw_d = _T_1087 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26] + assign io_dec_lsu_offset_d = _T_1101 | _T_1102; // @[dec_decode_ctl.scala 922:23] assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 527:24] assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 530:24] assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 531:24] - assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 536:20] + assign io_dec_csr_wen_r = _T_443 & _T_869; // @[dec_decode_ctl.scala 536:20] assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 532:24] assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 576:24] assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 539:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 639:29] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 671:39 dec_decode_ctl.scala 672:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 671:39] - assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 874:27] - assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 598:23] - assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 618:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 619:27] - assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 621:29] - assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 620:29] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_858; // @[dec_decode_ctl.scala 637:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_645; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27] + assign io_dec_illegal_inst = _T_566; // @[dec_decode_ctl.scala 596:23] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_598; // @[dec_decode_ctl.scala 617:27] + assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29] + assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29] assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 401:28] assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 398:29 dec_decode_ctl.scala 408:29] assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 562:22] assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 564:25] assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 219:35] - assign io_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 613:22 dec_decode_ctl.scala 676:22] + assign io_dec_i0_decode_d = _T_590 & _T_568; // @[dec_decode_ctl.scala 611:22 dec_decode_ctl.scala 674:22] assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 441:16] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] @@ -3206,9 +3220,9 @@ module dec_decode_ctl( assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 407:17] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] - assign rvclkhdr_3_io_en = shift_illegal & _T_564; // @[lib.scala 407:17] + assign rvclkhdr_3_io_en = shift_illegal & _T_565; // @[lib.scala 407:17] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] - assign rvclkhdr_4_io_en = i0_r_data_en & _T_875; // @[lib.scala 407:17] + assign rvclkhdr_4_io_en = i0_r_data_en & _T_876; // @[lib.scala 407:17] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 407:17] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] @@ -3317,7 +3331,7 @@ initial begin _RAND_29 = {1{`RANDOM}}; x_d_bits_i0load = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - _T_815 = _RAND_30[2:0]; + _T_816 = _RAND_30[2:0]; _RAND_31 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_31[0:0]; _RAND_32 = {1{`RANDOM}}; @@ -3373,7 +3387,7 @@ initial begin _RAND_57 = {1{`RANDOM}}; wbd_bits_csrwonly = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - _T_565 = _RAND_58[31:0]; + _T_566 = _RAND_58[31:0]; _RAND_59 = {1{`RANDOM}}; x_t_legal = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; @@ -3425,7 +3439,7 @@ initial begin _RAND_83 = {1{`RANDOM}}; last_br_immed_x = _RAND_83[11:0]; _RAND_84 = {1{`RANDOM}}; - _T_947 = _RAND_84[4:0]; + _T_948 = _RAND_84[4:0]; _RAND_85 = {1{`RANDOM}}; i0_inst_x = _RAND_85[31:0]; _RAND_86 = {1{`RANDOM}}; @@ -3528,7 +3542,7 @@ initial begin x_d_bits_i0load = 1'h0; end if (reset) begin - _T_815 = 3'h0; + _T_816 = 3'h0; end if (reset) begin nonblock_load_valid_m_delay = 1'h0; @@ -3612,7 +3626,7 @@ initial begin wbd_bits_csrwonly = 1'h0; end if (reset) begin - _T_565 = 32'h0; + _T_566 = 32'h0; end if (reset) begin x_t_legal = 1'h0; @@ -3690,7 +3704,7 @@ initial begin last_br_immed_x = 12'h0; end if (reset) begin - _T_947 = 5'h0; + _T_948 = 5'h0; end if (reset) begin i0_inst_x = 32'h0; @@ -3963,9 +3977,9 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_815 <= 3'h0; + _T_816 <= 3'h0; end else begin - _T_815 <= i0_pipe_en[3:1]; + _T_816 <= i0_pipe_en[3:1]; end end always @(posedge io_active_clk or posedge reset) begin @@ -4173,8 +4187,8 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin i0_result_r_raw <= 32'h0; - end else if (_T_876) begin - if (_T_878) begin + end else if (_T_877) begin + if (_T_879) begin i0_result_r_raw <= io_lsu_result_m; end else begin i0_result_r_raw <= io_decode_exu_exu_i0_result_x; @@ -4197,12 +4211,12 @@ end // initial end always @(posedge clock or posedge reset) begin if (reset) begin - _T_565 <= 32'h0; + _T_566 <= 32'h0; end else if (illegal_inst_en) begin if (io_dec_i0_pc4_d) begin - _T_565 <= io_dec_i0_instr_d; + _T_566 <= io_dec_i0_instr_d; end else begin - _T_565 <= _T_562; + _T_566 <= _T_563; end end end @@ -4383,7 +4397,7 @@ end // initial last_br_immed_x <= 12'h0; end else if (i0_x_data_en) begin if (io_decode_exu_i0_ap_predict_nt) begin - last_br_immed_x <= _T_898; + last_br_immed_x <= _T_899; end else if (_T_399) begin last_br_immed_x <= i0_pcall_imm[11:0]; end else begin @@ -4393,40 +4407,40 @@ end // initial end always @(posedge clock or posedge reset) begin if (reset) begin - _T_947 <= 5'h0; + _T_948 <= 5'h0; end else if (i0_div_decode_d) begin - _T_947 <= i0r_rd; + _T_948 <= i0r_rd; end end always @(posedge clock or posedge reset) begin if (reset) begin i0_inst_x <= 32'h0; - end else if (_T_948) begin + end else if (_T_949) begin if (io_dec_i0_pc4_d) begin i0_inst_x <= io_dec_i0_instr_d; end else begin - i0_inst_x <= _T_562; + i0_inst_x <= _T_563; end end end always @(posedge clock or posedge reset) begin if (reset) begin i0_inst_r <= 32'h0; - end else if (_T_950) begin + end else if (_T_951) begin i0_inst_r <= i0_inst_x; end end always @(posedge clock or posedge reset) begin if (reset) begin i0_inst_wb <= 32'h0; - end else if (_T_952) begin + end else if (_T_953) begin i0_inst_wb <= i0_inst_r; end end always @(posedge clock or posedge reset) begin if (reset) begin i0_pc_wb <= 31'h0; - end else if (_T_952) begin + end else if (_T_953) begin i0_pc_wb <= io_dec_tlu_i0_pc_r; end end @@ -9632,15 +9646,15 @@ module csr_tlu( assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29] assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29] assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:38] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:39] assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39] - assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:38] - assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:38] - assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:38] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:38] - assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:38] - assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:38] - assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:38] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:39] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:39] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:39] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:39] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:39] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:39] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:39] assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46] assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31] diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index 16bc5bc1..03ab5d1b 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -84,7 +84,7 @@ class dec_IO extends Bundle with lib { val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc - val dec_tlu_flush_lower_wb = Output(Bool()) + val dec_tlu_flush_lower_wb = Output(Bool()) val dec_lsu_valid_raw_d = Output(Bool()) val trace_rv_trace_pkt = Output(new trace_pkt_t) // trace packet diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala index 4b01aca9..2e53d5b4 100644 --- a/src/main/scala/dec/dec_decode_ctl.scala +++ b/src/main/scala/dec/dec_decode_ctl.scala @@ -586,10 +586,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ // some CSR writes need to be postsync'd val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) - - - - val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) + val bitmanip_legal = WireInit(Bool(),0.B) + val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) & bitmanip_legal val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst)) // illegal inst handling @@ -708,7 +706,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ val bitmanip_zbf_legal = WireInit(Bool(),0.B) val bitmanip_zba_legal = WireInit(Bool(),0.B) val bitmanip_zbb_zbp_legal = WireInit(Bool(),0.B) - val bitmanip_legal = WireInit(Bool(),0.B) + if (BITMANIP_ZBB == 1) bitmanip_zbb_legal := 1.B else diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 6b141736..947077de 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -1754,14 +1754,14 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset { mcgc_int := rvdffe(mcgc_ns,wr_mcgc_r.asBool,clock,io.scan_mode) val mcgc = Cat(~mcgc_int(9), mcgc_int(8,0)) io.dec_tlu_picio_clk_override := mcgc(9) - io.dec_tlu_misc_clk_override := mcgc(8) - io.dec_tlu_dec_clk_override := mcgc(7) - io.dec_tlu_ifu_clk_override := mcgc(5) - io.dec_tlu_lsu_clk_override := mcgc(4) - io.dec_tlu_bus_clk_override := mcgc(3) - io.dec_tlu_pic_clk_override := mcgc(2) - io.dec_tlu_dccm_clk_override := mcgc(1) - io.dec_tlu_icm_clk_override := mcgc(0) + io.dec_tlu_misc_clk_override := mcgc(8) + io.dec_tlu_dec_clk_override := mcgc(7) + io.dec_tlu_ifu_clk_override := mcgc(5) + io.dec_tlu_lsu_clk_override := mcgc(4) + io.dec_tlu_bus_clk_override := mcgc(3) + io.dec_tlu_pic_clk_override := mcgc(2) + io.dec_tlu_dccm_clk_override := mcgc(1) + io.dec_tlu_icm_clk_override := mcgc(0) // ---------------------------------------------------------------------- // MFDC (RW) Feature Disable Control diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index 71129d91..9997f01d 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl.class b/target/scala-2.12/classes/dec/dec_decode_ctl.class index fd3195c3..07b5122c 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl.class and b/target/scala-2.12/classes/dec/dec_decode_ctl.class differ