EXU final

exu.fir

@@ -45051,26 +45051,26 @@ circuit exu :
     i_mul.clock <= clock
     i_mul.reset <= reset
     i_mul.io.scan_mode <= io.scan_mode @[exu.scala 149:25]
-    i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:18]
-    i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:18]
-    i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:18]
+    i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 150:23]
+    i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 150:23]
+    i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 150:23]
     node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
     node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
     node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 152:57]

exu.v

@@ -2675,10 +2675,10 @@ module exu(
   assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 134:45]
   assign i_mul_clock = clock;
   assign i_mul_reset = reset;
-  assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:18]
-  assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:18]
-  assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:18]
-  assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:18]
+  assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 150:23]
+  assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 150:23]
+  assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 150:23]
+  assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 150:23]
   assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 152:41]
   assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 153:41]
   assign i_div_clock = clock;

src/main/scala/exu/exu.scala

@@ -147,7 +147,7 @@ class exu extends Module with lib with RequireAsyncReset{
 
   val i_mul = Module(new exu_mul_ctl())
   i_mul.io.scan_mode	:= io.scan_mode
-  i_mul.io.mul_p := io.dec_exu.decode_exu.mul_p
+  i_mul.io.mul_p      := io.dec_exu.decode_exu.mul_p
   //i_mul.io.mul_p	:= VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid
   i_mul.io.rs1_in			:= muldiv_rs1_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)
   i_mul.io.rs2_in			:=  i0_rs2_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)