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Bus-buffer testing start

This commit is contained in:
waleed-lm 2020-11-09 12:10:58 +05:00
parent f3e4572e1c
commit 65c83526ed
4 changed files with 19 additions and 21 deletions
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18
el2_lsu_bus_buffer.fir
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@ -2689,7 +2689,7 @@ circuit el2_lsu_bus_buffer :
obuf_wr_timer <= _T_1873 @[el2_lsu_bus_buffer.scala 421:17] obuf_wr_timer <= _T_1873 @[el2_lsu_bus_buffer.scala 421:17]
wire WrPtr0_m : UInt<2> wire WrPtr0_m : UInt<2>
WrPtr0_m <= UInt<1>("h00") WrPtr0_m <= UInt<1>("h00")
node _T_1874 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] node _T_1874 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:70]
node _T_1875 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:30] node _T_1875 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:30]
node _T_1876 = and(ibuf_valid, _T_1875) @[el2_lsu_bus_buffer.scala 425:19] node _T_1876 = and(ibuf_valid, _T_1875) @[el2_lsu_bus_buffer.scala 425:19]
node _T_1877 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:18] node _T_1877 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:18]
@ -2699,8 +2699,8 @@ circuit el2_lsu_bus_buffer :
node _T_1881 = and(io.lsu_busreq_r, _T_1880) @[el2_lsu_bus_buffer.scala 425:58] node _T_1881 = and(io.lsu_busreq_r, _T_1880) @[el2_lsu_bus_buffer.scala 425:58]
node _T_1882 = or(_T_1876, _T_1881) @[el2_lsu_bus_buffer.scala 425:39] node _T_1882 = or(_T_1876, _T_1881) @[el2_lsu_bus_buffer.scala 425:39]
node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5] node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5]
node _T_1884 = and(_T_1874, _T_1883) @[el2_lsu_bus_buffer.scala 424:76] node _T_1884 = and(_T_1874, _T_1883) @[el2_lsu_bus_buffer.scala 424:81]
node _T_1885 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] node _T_1885 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:70]
node _T_1886 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:30] node _T_1886 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:30]
node _T_1887 = and(ibuf_valid, _T_1886) @[el2_lsu_bus_buffer.scala 425:19] node _T_1887 = and(ibuf_valid, _T_1886) @[el2_lsu_bus_buffer.scala 425:19]
node _T_1888 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:18] node _T_1888 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:18]
@ -2710,8 +2710,8 @@ circuit el2_lsu_bus_buffer :
node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[el2_lsu_bus_buffer.scala 425:58] node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[el2_lsu_bus_buffer.scala 425:58]
node _T_1893 = or(_T_1887, _T_1892) @[el2_lsu_bus_buffer.scala 425:39] node _T_1893 = or(_T_1887, _T_1892) @[el2_lsu_bus_buffer.scala 425:39]
node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5] node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5]
node _T_1895 = and(_T_1885, _T_1894) @[el2_lsu_bus_buffer.scala 424:76] node _T_1895 = and(_T_1885, _T_1894) @[el2_lsu_bus_buffer.scala 424:81]
node _T_1896 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] node _T_1896 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:70]
node _T_1897 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:30] node _T_1897 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:30]
node _T_1898 = and(ibuf_valid, _T_1897) @[el2_lsu_bus_buffer.scala 425:19] node _T_1898 = and(ibuf_valid, _T_1897) @[el2_lsu_bus_buffer.scala 425:19]
node _T_1899 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:18] node _T_1899 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:18]
@ -2721,8 +2721,8 @@ circuit el2_lsu_bus_buffer :
node _T_1903 = and(io.lsu_busreq_r, _T_1902) @[el2_lsu_bus_buffer.scala 425:58] node _T_1903 = and(io.lsu_busreq_r, _T_1902) @[el2_lsu_bus_buffer.scala 425:58]
node _T_1904 = or(_T_1898, _T_1903) @[el2_lsu_bus_buffer.scala 425:39] node _T_1904 = or(_T_1898, _T_1903) @[el2_lsu_bus_buffer.scala 425:39]
node _T_1905 = eq(_T_1904, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5] node _T_1905 = eq(_T_1904, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5]
node _T_1906 = and(_T_1896, _T_1905) @[el2_lsu_bus_buffer.scala 424:76] node _T_1906 = and(_T_1896, _T_1905) @[el2_lsu_bus_buffer.scala 424:81]
node _T_1907 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:65] node _T_1907 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 424:70]
node _T_1908 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:30] node _T_1908 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:30]
node _T_1909 = and(ibuf_valid, _T_1908) @[el2_lsu_bus_buffer.scala 425:19] node _T_1909 = and(ibuf_valid, _T_1908) @[el2_lsu_bus_buffer.scala 425:19]
node _T_1910 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:18] node _T_1910 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:18]
@ -2732,8 +2732,8 @@ circuit el2_lsu_bus_buffer :
node _T_1914 = and(io.lsu_busreq_r, _T_1913) @[el2_lsu_bus_buffer.scala 425:58] node _T_1914 = and(io.lsu_busreq_r, _T_1913) @[el2_lsu_bus_buffer.scala 425:58]
node _T_1915 = or(_T_1909, _T_1914) @[el2_lsu_bus_buffer.scala 425:39] node _T_1915 = or(_T_1909, _T_1914) @[el2_lsu_bus_buffer.scala 425:39]
node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5] node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:5]
node _T_1917 = and(_T_1907, _T_1916) @[el2_lsu_bus_buffer.scala 424:76] node _T_1917 = and(_T_1907, _T_1916) @[el2_lsu_bus_buffer.scala 424:81]
node _T_1918 = mux(_T_1917, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_1918 = mux(_T_1917, UInt<2>("h03"), WrPtr0_r) @[Mux.scala 98:16]
node _T_1919 = mux(_T_1906, UInt<2>("h02"), _T_1918) @[Mux.scala 98:16] node _T_1919 = mux(_T_1906, UInt<2>("h02"), _T_1918) @[Mux.scala 98:16]
node _T_1920 = mux(_T_1895, UInt<1>("h01"), _T_1919) @[Mux.scala 98:16] node _T_1920 = mux(_T_1895, UInt<1>("h01"), _T_1919) @[Mux.scala 98:16]
node _T_1921 = mux(_T_1884, UInt<1>("h00"), _T_1920) @[Mux.scala 98:16] node _T_1921 = mux(_T_1884, UInt<1>("h00"), _T_1920) @[Mux.scala 98:16]

20
el2_lsu_bus_buffer.v
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@ -1500,7 +1500,7 @@ module el2_lsu_bus_buffer(
reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [1:0] obuf_sz; // @[Reg.scala 27:20]
reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
reg [63:0] obuf_data; // @[el2_lib.scala 491:16] reg [63:0] obuf_data; // @[el2_lib.scala 491:16]
wire _T_1874 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:65] wire _T_1874 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:70]
wire _T_1875 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 425:30] wire _T_1875 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 425:30]
wire _T_1876 = ibuf_valid & _T_1875; // @[el2_lsu_bus_buffer.scala 425:19] wire _T_1876 = ibuf_valid & _T_1875; // @[el2_lsu_bus_buffer.scala 425:19]
wire _T_1877 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 426:18] wire _T_1877 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 426:18]
@ -1510,8 +1510,8 @@ module el2_lsu_bus_buffer(
wire _T_1881 = io_lsu_busreq_r & _T_1880; // @[el2_lsu_bus_buffer.scala 425:58] wire _T_1881 = io_lsu_busreq_r & _T_1880; // @[el2_lsu_bus_buffer.scala 425:58]
wire _T_1882 = _T_1876 | _T_1881; // @[el2_lsu_bus_buffer.scala 425:39] wire _T_1882 = _T_1876 | _T_1881; // @[el2_lsu_bus_buffer.scala 425:39]
wire _T_1883 = ~_T_1882; // @[el2_lsu_bus_buffer.scala 425:5] wire _T_1883 = ~_T_1882; // @[el2_lsu_bus_buffer.scala 425:5]
wire _T_1884 = _T_1874 & _T_1883; // @[el2_lsu_bus_buffer.scala 424:76] wire _T_1884 = _T_1874 & _T_1883; // @[el2_lsu_bus_buffer.scala 424:81]
wire _T_1885 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:65] wire _T_1885 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:70]
wire _T_1886 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 425:30] wire _T_1886 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 425:30]
wire _T_1887 = ibuf_valid & _T_1886; // @[el2_lsu_bus_buffer.scala 425:19] wire _T_1887 = ibuf_valid & _T_1886; // @[el2_lsu_bus_buffer.scala 425:19]
wire _T_1888 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 426:18] wire _T_1888 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 426:18]
@ -1521,8 +1521,8 @@ module el2_lsu_bus_buffer(
wire _T_1892 = io_lsu_busreq_r & _T_1891; // @[el2_lsu_bus_buffer.scala 425:58] wire _T_1892 = io_lsu_busreq_r & _T_1891; // @[el2_lsu_bus_buffer.scala 425:58]
wire _T_1893 = _T_1887 | _T_1892; // @[el2_lsu_bus_buffer.scala 425:39] wire _T_1893 = _T_1887 | _T_1892; // @[el2_lsu_bus_buffer.scala 425:39]
wire _T_1894 = ~_T_1893; // @[el2_lsu_bus_buffer.scala 425:5] wire _T_1894 = ~_T_1893; // @[el2_lsu_bus_buffer.scala 425:5]
wire _T_1895 = _T_1885 & _T_1894; // @[el2_lsu_bus_buffer.scala 424:76] wire _T_1895 = _T_1885 & _T_1894; // @[el2_lsu_bus_buffer.scala 424:81]
wire _T_1896 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:65] wire _T_1896 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:70]
wire _T_1897 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 425:30] wire _T_1897 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 425:30]
wire _T_1898 = ibuf_valid & _T_1897; // @[el2_lsu_bus_buffer.scala 425:19] wire _T_1898 = ibuf_valid & _T_1897; // @[el2_lsu_bus_buffer.scala 425:19]
wire _T_1899 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 426:18] wire _T_1899 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 426:18]
@ -1532,8 +1532,8 @@ module el2_lsu_bus_buffer(
wire _T_1903 = io_lsu_busreq_r & _T_1902; // @[el2_lsu_bus_buffer.scala 425:58] wire _T_1903 = io_lsu_busreq_r & _T_1902; // @[el2_lsu_bus_buffer.scala 425:58]
wire _T_1904 = _T_1898 | _T_1903; // @[el2_lsu_bus_buffer.scala 425:39] wire _T_1904 = _T_1898 | _T_1903; // @[el2_lsu_bus_buffer.scala 425:39]
wire _T_1905 = ~_T_1904; // @[el2_lsu_bus_buffer.scala 425:5] wire _T_1905 = ~_T_1904; // @[el2_lsu_bus_buffer.scala 425:5]
wire _T_1906 = _T_1896 & _T_1905; // @[el2_lsu_bus_buffer.scala 424:76] wire _T_1906 = _T_1896 & _T_1905; // @[el2_lsu_bus_buffer.scala 424:81]
wire _T_1907 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:65] wire _T_1907 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 424:70]
wire _T_1908 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 425:30] wire _T_1908 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 425:30]
wire _T_1909 = ibuf_valid & _T_1908; // @[el2_lsu_bus_buffer.scala 425:19] wire _T_1909 = ibuf_valid & _T_1908; // @[el2_lsu_bus_buffer.scala 425:19]
wire _T_1910 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 426:18] wire _T_1910 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 426:18]
@ -1543,8 +1543,8 @@ module el2_lsu_bus_buffer(
wire _T_1914 = io_lsu_busreq_r & _T_1913; // @[el2_lsu_bus_buffer.scala 425:58] wire _T_1914 = io_lsu_busreq_r & _T_1913; // @[el2_lsu_bus_buffer.scala 425:58]
wire _T_1915 = _T_1909 | _T_1914; // @[el2_lsu_bus_buffer.scala 425:39] wire _T_1915 = _T_1909 | _T_1914; // @[el2_lsu_bus_buffer.scala 425:39]
wire _T_1916 = ~_T_1915; // @[el2_lsu_bus_buffer.scala 425:5] wire _T_1916 = ~_T_1915; // @[el2_lsu_bus_buffer.scala 425:5]
wire _T_1917 = _T_1907 & _T_1916; // @[el2_lsu_bus_buffer.scala 424:76] wire _T_1917 = _T_1907 & _T_1916; // @[el2_lsu_bus_buffer.scala 424:81]
wire [1:0] _T_1918 = _T_1917 ? 2'h3 : 2'h0; // @[Mux.scala 98:16] wire [1:0] _T_1918 = _T_1917 ? 2'h3 : WrPtr0_r; // @[Mux.scala 98:16]
wire [1:0] _T_1919 = _T_1906 ? 2'h2 : _T_1918; // @[Mux.scala 98:16] wire [1:0] _T_1919 = _T_1906 ? 2'h2 : _T_1918; // @[Mux.scala 98:16]
wire [1:0] _T_1920 = _T_1895 ? 2'h1 : _T_1919; // @[Mux.scala 98:16] wire [1:0] _T_1920 = _T_1895 ? 2'h1 : _T_1919; // @[Mux.scala 98:16]
wire [1:0] WrPtr0_m = _T_1884 ? 2'h0 : _T_1920; // @[Mux.scala 98:16] wire [1:0] WrPtr0_m = _T_1884 ? 2'h0 : _T_1920; // @[Mux.scala 98:16]
@ -4022,8 +4022,6 @@ end // initial
WrPtr0_r <= 2'h2; WrPtr0_r <= 2'h2;
end else if (_T_1917) begin end else if (_T_1917) begin
WrPtr0_r <= 2'h3; WrPtr0_r <= 2'h3;
end else begin
WrPtr0_r <= 2'h0;
end end
end end
always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin

2
src/main/scala/lsu/el2_lsu_bus_buffer.scala
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@ -421,7 +421,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)} obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
WrPtr0_m := MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & WrPtr0_m := MuxCase(WrPtr0_r, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) &
!((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r &
((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U))
io.buf_state := buf_state.reverse.reduce(Cat(_,_)) io.buf_state := buf_state.reverse.reduce(Cat(_,_))

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target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class
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