Update el2_lsu_addrcheck.scala
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2b6bfabc4f
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@ -42,13 +42,13 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset
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//DCCM check
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// Start address check
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if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
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val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt.DCCM_SADR,pt1.DCCM_SIZE))
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start_addr_dccm_rangecheck.io.addr := io.start_addr_d
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start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
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start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
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// End address check
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val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt.DCCM_SADR,pt1.DCCM_SIZE))
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end_addr_dccm_rangecheck.io.addr := io.end_addr_d
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end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
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end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
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@ -71,13 +71,13 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset
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//PIC memory check
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//start address check
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val start_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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val start_addr_pic_rangecheck = Module(new rvrangecheck(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
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start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
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val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
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val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
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//End address check
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val end_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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val end_addr_pic_rangecheck = Module(new rvrangecheck(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
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end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
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val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
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val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
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