colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

divider 4 added

This commit is contained in:
​Laraib Khan 2021-01-06 15:43:04 +05:00
parent 92cf822089
commit 675d53d37f
4 changed files with 206 additions and 203 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

255
exu_div_new_3bit_fullshortq.fir
View File

@ -1118,8 +1118,8 @@ circuit exu_div_new_3bit_fullshortq :
node _T_62 = add(count_ff, _T_61) @[exu_div_ctl.scala 663:63] node _T_62 = add(count_ff, _T_61) @[exu_div_ctl.scala 663:63]
node _T_63 = tail(_T_62, 1) @[exu_div_ctl.scala 663:63] node _T_63 = tail(_T_62, 1) @[exu_div_ctl.scala 663:63]
node _T_64 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58] node _T_64 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
node _T_65 = add(_T_63, _T_64) @[exu_div_ctl.scala 663:83] node _T_65 = add(_T_63, _T_64) @[exu_div_ctl.scala 663:88]
node _T_66 = tail(_T_65, 1) @[exu_div_ctl.scala 663:83] node _T_66 = tail(_T_65, 1) @[exu_div_ctl.scala 663:88]
node count_in = and(_T_60, _T_66) @[exu_div_ctl.scala 663:51] node count_in = and(_T_60, _T_66) @[exu_div_ctl.scala 663:51]
node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 664:43] node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 664:43]
node _T_67 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 665:47] node _T_67 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 665:47]
@ -1176,7 +1176,7 @@ circuit exu_div_new_3bit_fullshortq :
node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 679:45] node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 679:45]
node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 679:72] node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 679:72]
node r_adder6_sel = and(_T_104, _T_105) @[exu_div_ctl.scala 679:70] node r_adder6_sel = and(_T_104, _T_105) @[exu_div_ctl.scala 679:70]
node _T_106 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 680:61] node _T_106 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 680:61]
node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 680:45] node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 680:45]
node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 680:72] node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 680:72]
node r_adder7_sel = and(_T_107, _T_108) @[exu_div_ctl.scala 680:70] node r_adder7_sel = and(_T_107, _T_108) @[exu_div_ctl.scala 680:70]
@ -1315,13 +1315,13 @@ circuit exu_div_new_3bit_fullshortq :
node _T_234 = cat(_T_233, _T_232) @[Cat.scala 29:58] node _T_234 = cat(_T_233, _T_232) @[Cat.scala 29:58]
node _T_235 = cat(_T_234, _T_231) @[Cat.scala 29:58] node _T_235 = cat(_T_234, _T_231) @[Cat.scala 29:58]
quotient_raw <= _T_235 @[exu_div_ctl.scala 688:16] quotient_raw <= _T_235 @[exu_div_ctl.scala 688:16]
node _T_236 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 695:39] node _T_236 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 695:37]
node _T_237 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 695:58] node _T_237 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 695:56]
node _T_238 = or(_T_236, _T_237) @[exu_div_ctl.scala 695:43] node _T_238 = or(_T_236, _T_237) @[exu_div_ctl.scala 695:41]
node _T_239 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 695:76] node _T_239 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 695:74]
node _T_240 = or(_T_238, _T_239) @[exu_div_ctl.scala 695:62] node _T_240 = or(_T_238, _T_239) @[exu_div_ctl.scala 695:60]
node _T_241 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 695:95] node _T_241 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 695:93]
node _T_242 = or(_T_240, _T_241) @[exu_div_ctl.scala 695:80] node _T_242 = or(_T_240, _T_241) @[exu_div_ctl.scala 695:78]
node _T_243 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 696:38] node _T_243 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 696:38]
node _T_244 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 696:57] node _T_244 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 696:57]
node _T_245 = or(_T_243, _T_244) @[exu_div_ctl.scala 696:42] node _T_245 = or(_T_243, _T_244) @[exu_div_ctl.scala 696:42]
@ -1352,7 +1352,7 @@ circuit exu_div_new_3bit_fullshortq :
node _T_270 = or(_T_265, _T_269) @[exu_div_ctl.scala 697:117] node _T_270 = or(_T_265, _T_269) @[exu_div_ctl.scala 697:117]
node _T_271 = cat(_T_242, _T_255) @[Cat.scala 29:58] node _T_271 = cat(_T_242, _T_255) @[Cat.scala 29:58]
node _T_272 = cat(_T_271, _T_270) @[Cat.scala 29:58] node _T_272 = cat(_T_271, _T_270) @[Cat.scala 29:58]
quotient_new <= _T_272 @[exu_div_ctl.scala 695:18] quotient_new <= _T_272 @[exu_div_ctl.scala 695:16]
node _T_273 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 700:48] node _T_273 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 700:48]
node _T_274 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_274 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_275 = mux(twos_comp_b_sel, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] node _T_275 = mux(twos_comp_b_sel, _T_273, UInt<1>("h00")) @[Mux.scala 27:72]
@ -2163,7 +2163,8 @@ circuit exu_div_new_3bit_fullshortq :
node _T_1035 = cat(_T_588, _T_619) @[Cat.scala 29:58] node _T_1035 = cat(_T_588, _T_619) @[Cat.scala 29:58]
node _T_1036 = cat(_T_1035, _T_1034) @[Cat.scala 29:58] node _T_1036 = cat(_T_1035, _T_1034) @[Cat.scala 29:58]
smallnum <= _T_1036 @[exu_div_ctl.scala 743:12] smallnum <= _T_1036 @[exu_div_ctl.scala 743:12]
node shortq_dividend = cat(dividend_sign_ff, a_ff) @[Cat.scala 29:58] node _T_1037 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 762:50]
node shortq_dividend = cat(dividend_sign_ff, _T_1037) @[Cat.scala 29:58]
inst a_enc of exu_div_cls @[exu_div_ctl.scala 763:21] inst a_enc of exu_div_cls @[exu_div_ctl.scala 763:21]
a_enc.clock <= clock a_enc.clock <= clock
a_enc.reset <= reset a_enc.reset <= reset
@ -2171,96 +2172,95 @@ circuit exu_div_new_3bit_fullshortq :
inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 766:20] inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 766:20]
b_enc.clock <= clock b_enc.clock <= clock
b_enc.reset <= reset b_enc.reset <= reset
node _T_1037 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 767:27] node _T_1038 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 767:27]
b_enc.io.operand <= _T_1037 @[exu_div_ctl.scala 767:20] b_enc.io.operand <= _T_1038 @[exu_div_ctl.scala 767:20]
node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58] node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58] node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
node _T_1038 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58] node _T_1039 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
node _T_1039 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58] node _T_1040 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
node _T_1040 = sub(_T_1038, _T_1039) @[exu_div_ctl.scala 771:41] node _T_1041 = sub(_T_1039, _T_1040) @[exu_div_ctl.scala 771:41]
node _T_1041 = tail(_T_1040, 1) @[exu_div_ctl.scala 771:41] node _T_1042 = tail(_T_1041, 1) @[exu_div_ctl.scala 771:41]
node _T_1042 = add(_T_1041, UInt<7>("h01")) @[exu_div_ctl.scala 771:61] node _T_1043 = add(_T_1042, UInt<7>("h01")) @[exu_div_ctl.scala 771:61]
node dw_shortq_raw = tail(_T_1042, 1) @[exu_div_ctl.scala 771:61] node dw_shortq_raw = tail(_T_1043, 1) @[exu_div_ctl.scala 771:61]
node _T_1043 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 772:33] node _T_1044 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 772:33]
node _T_1044 = bits(_T_1043, 0, 0) @[exu_div_ctl.scala 772:43] node _T_1045 = bits(_T_1044, 0, 0) @[exu_div_ctl.scala 772:43]
node _T_1045 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 772:63] node _T_1046 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 772:63]
node shortq = mux(_T_1044, UInt<1>("h00"), _T_1045) @[exu_div_ctl.scala 772:19] node shortq = mux(_T_1045, UInt<1>("h00"), _T_1046) @[exu_div_ctl.scala 772:19]
node _T_1046 = bits(shortq, 5, 5) @[exu_div_ctl.scala 773:38] node _T_1047 = bits(shortq, 5, 5) @[exu_div_ctl.scala 773:38]
node _T_1047 = eq(_T_1046, UInt<1>("h00")) @[exu_div_ctl.scala 773:31] node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[exu_div_ctl.scala 773:31]
node _T_1048 = and(valid_ff, _T_1047) @[exu_div_ctl.scala 773:29] node _T_1049 = and(valid_ff, _T_1048) @[exu_div_ctl.scala 773:29]
node _T_1049 = bits(shortq, 4, 2) @[exu_div_ctl.scala 773:52] node _T_1050 = bits(shortq, 4, 2) @[exu_div_ctl.scala 773:52]
node _T_1050 = eq(_T_1049, UInt<3>("h07")) @[exu_div_ctl.scala 773:58] node _T_1051 = eq(_T_1050, UInt<3>("h07")) @[exu_div_ctl.scala 773:58]
node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[exu_div_ctl.scala 773:44] node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[exu_div_ctl.scala 773:44]
node _T_1052 = and(_T_1048, _T_1051) @[exu_div_ctl.scala 773:42] node _T_1053 = and(_T_1049, _T_1052) @[exu_div_ctl.scala 773:42]
node _T_1053 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 773:75] node _T_1054 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 773:75]
node _T_1054 = and(_T_1052, _T_1053) @[exu_div_ctl.scala 773:73] node _T_1055 = and(_T_1053, _T_1054) @[exu_div_ctl.scala 773:73]
shortq_enable <= _T_1054 @[exu_div_ctl.scala 773:17] shortq_enable <= _T_1055 @[exu_div_ctl.scala 773:17]
node _T_1055 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 775:58] node _T_1056 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 775:58]
node _T_1056 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 775:58] node _T_1057 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 775:58]
node _T_1057 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 775:58] node _T_1058 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 775:58]
node _T_1058 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 775:58] node _T_1059 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 775:58]
node _T_1059 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 775:58] node _T_1060 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 775:58]
node _T_1060 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 775:58] node _T_1061 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 775:58]
node _T_1061 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 775:58] node _T_1062 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 775:58]
node _T_1062 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 775:58] node _T_1063 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 775:58]
node _T_1063 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 775:58] node _T_1064 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 775:58]
node _T_1064 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 775:58] node _T_1065 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 775:58]
node _T_1065 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 775:58] node _T_1066 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 775:58]
node _T_1066 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 775:58] node _T_1067 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 775:58]
node _T_1067 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 775:58] node _T_1068 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 775:58]
node _T_1068 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 775:58] node _T_1069 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 775:58]
node _T_1069 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 775:58] node _T_1070 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 775:58]
node _T_1070 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 775:58] node _T_1071 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 775:58]
node _T_1071 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 775:58] node _T_1072 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 775:58]
node _T_1072 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 775:58] node _T_1073 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 775:58]
node _T_1073 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 775:58] node _T_1074 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 775:58]
node _T_1074 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 775:58] node _T_1075 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 775:58]
node _T_1075 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 775:58] node _T_1076 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 775:58]
node _T_1076 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 775:58] node _T_1077 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 775:58]
node _T_1077 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 775:58] node _T_1078 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 775:58]
node _T_1078 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 775:58] node _T_1079 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 775:58]
node _T_1079 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 775:58] node _T_1080 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 775:58]
node _T_1080 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 775:58] node _T_1081 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 775:58]
node _T_1081 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 775:58] node _T_1082 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 775:58]
node _T_1082 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 775:58] node _T_1083 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 775:58]
node _T_1083 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 775:58] node _T_1084 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 775:58]
node _T_1084 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 775:58] node _T_1085 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 775:58]
node _T_1085 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 775:58] node _T_1086 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 775:58]
node _T_1086 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 775:58] node _T_1087 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 775:58]
node _T_1087 = mux(_T_1055, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1088 = mux(_T_1056, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1088 = mux(_T_1056, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1089 = mux(_T_1057, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1089 = mux(_T_1057, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1090 = mux(_T_1058, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1090 = mux(_T_1058, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1091 = mux(_T_1059, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1091 = mux(_T_1059, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1092 = mux(_T_1060, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1092 = mux(_T_1060, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1093 = mux(_T_1061, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1093 = mux(_T_1061, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1094 = mux(_T_1062, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1094 = mux(_T_1062, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1095 = mux(_T_1063, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1095 = mux(_T_1063, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1096 = mux(_T_1064, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1096 = mux(_T_1064, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1097 = mux(_T_1065, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1097 = mux(_T_1065, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1098 = mux(_T_1066, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1098 = mux(_T_1066, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1099 = mux(_T_1067, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1099 = mux(_T_1067, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1100 = mux(_T_1068, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1100 = mux(_T_1068, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1101 = mux(_T_1069, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1101 = mux(_T_1069, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1102 = mux(_T_1070, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1102 = mux(_T_1070, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1103 = mux(_T_1071, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1103 = mux(_T_1071, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1104 = mux(_T_1072, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1104 = mux(_T_1072, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1105 = mux(_T_1073, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1105 = mux(_T_1073, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1106 = mux(_T_1074, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1106 = mux(_T_1074, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1107 = mux(_T_1075, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1107 = mux(_T_1075, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1108 = mux(_T_1076, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1108 = mux(_T_1076, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1109 = mux(_T_1077, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1109 = mux(_T_1077, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1110 = mux(_T_1078, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1110 = mux(_T_1078, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1111 = mux(_T_1079, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1111 = mux(_T_1079, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1112 = mux(_T_1080, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1112 = mux(_T_1080, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1113 = mux(_T_1081, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1113 = mux(_T_1081, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1114 = mux(_T_1082, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1114 = mux(_T_1082, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1115 = mux(_T_1083, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1115 = mux(_T_1083, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1116 = mux(_T_1084, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1116 = mux(_T_1084, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1117 = mux(_T_1085, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1117 = mux(_T_1085, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1118 = mux(_T_1086, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1118 = mux(_T_1086, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1119 = or(_T_1087, _T_1088) @[Mux.scala 27:72] node _T_1119 = mux(_T_1087, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1120 = or(_T_1119, _T_1089) @[Mux.scala 27:72] node _T_1120 = or(_T_1088, _T_1089) @[Mux.scala 27:72]
node _T_1121 = or(_T_1120, _T_1090) @[Mux.scala 27:72] node _T_1121 = or(_T_1120, _T_1090) @[Mux.scala 27:72]
node _T_1122 = or(_T_1121, _T_1091) @[Mux.scala 27:72] node _T_1122 = or(_T_1121, _T_1091) @[Mux.scala 27:72]
node _T_1123 = or(_T_1122, _T_1092) @[Mux.scala 27:72] node _T_1123 = or(_T_1122, _T_1092) @[Mux.scala 27:72]
@ -2290,141 +2290,142 @@ circuit exu_div_new_3bit_fullshortq :
node _T_1147 = or(_T_1146, _T_1116) @[Mux.scala 27:72] node _T_1147 = or(_T_1146, _T_1116) @[Mux.scala 27:72]
node _T_1148 = or(_T_1147, _T_1117) @[Mux.scala 27:72] node _T_1148 = or(_T_1147, _T_1117) @[Mux.scala 27:72]
node _T_1149 = or(_T_1148, _T_1118) @[Mux.scala 27:72] node _T_1149 = or(_T_1148, _T_1118) @[Mux.scala 27:72]
wire _T_1150 : UInt<5> @[Mux.scala 27:72] node _T_1150 = or(_T_1149, _T_1119) @[Mux.scala 27:72]
_T_1150 <= _T_1149 @[Mux.scala 27:72] wire _T_1151 : UInt<5> @[Mux.scala 27:72]
shortq_decode <= _T_1150 @[exu_div_ctl.scala 775:17] _T_1151 <= _T_1150 @[Mux.scala 27:72]
node _T_1151 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 776:26] shortq_decode <= _T_1151 @[exu_div_ctl.scala 775:17]
node shortq_shift = mux(_T_1151, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 776:25] node _T_1152 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 776:26]
node _T_1152 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:20] node shortq_shift = mux(_T_1152, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 776:25]
node _T_1153 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:30] node _T_1153 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:20]
node _T_1154 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:40] node _T_1154 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:30]
node _T_1155 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:50] node _T_1155 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:40]
node _T_1156 = cat(_T_1155, b_ff1) @[Cat.scala 29:58] node _T_1156 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 777:50]
node _T_1157 = cat(_T_1152, _T_1153) @[Cat.scala 29:58] node _T_1157 = cat(_T_1156, b_ff1) @[Cat.scala 29:58]
node _T_1158 = cat(_T_1157, _T_1154) @[Cat.scala 29:58] node _T_1158 = cat(_T_1153, _T_1154) @[Cat.scala 29:58]
node _T_1159 = cat(_T_1158, _T_1156) @[Cat.scala 29:58] node _T_1159 = cat(_T_1158, _T_1155) @[Cat.scala 29:58]
b_ff <= _T_1159 @[exu_div_ctl.scala 777:8] node _T_1160 = cat(_T_1159, _T_1157) @[Cat.scala 29:58]
b_ff <= _T_1160 @[exu_div_ctl.scala 777:8]
inst rvclkhdr of rvclkhdr @[lib.scala 390:23] inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock rvclkhdr.clock <= clock
rvclkhdr.reset <= reset rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18] rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1160 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1161 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1160 <= valid_ff_in @[Reg.scala 28:23] _T_1161 <= valid_ff_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
valid_ff <= _T_1160 @[exu_div_ctl.scala 778:12] valid_ff <= _T_1161 @[exu_div_ctl.scala 778:12]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18] rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1161 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1161 <= control_in @[Reg.scala 28:23] _T_1162 <= control_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
control_ff <= _T_1161 @[exu_div_ctl.scala 779:16] control_ff <= _T_1162 @[exu_div_ctl.scala 779:16]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18] rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1162 <= by_zero_case @[Reg.scala 28:23] _T_1163 <= by_zero_case @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
by_zero_case_ff <= _T_1162 @[exu_div_ctl.scala 780:19] by_zero_case_ff <= _T_1163 @[exu_div_ctl.scala 780:19]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
rvclkhdr_3.clock <= clock rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 392:18] rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1164 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1163 <= shortq_enable @[Reg.scala 28:23] _T_1164 <= shortq_enable @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
shortq_enable_ff <= _T_1163 @[exu_div_ctl.scala 781:20] shortq_enable_ff <= _T_1164 @[exu_div_ctl.scala 781:20]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
rvclkhdr_4.clock <= clock rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 392:18] rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1164 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1164 <= shortq_shift @[Reg.scala 28:23] _T_1165 <= shortq_shift @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_1165 = cat(_T_1164, UInt<1>("h00")) @[Cat.scala 29:58] node _T_1166 = cat(_T_1165, UInt<1>("h00")) @[Cat.scala 29:58]
shortq_shift_ff <= _T_1165 @[exu_div_ctl.scala 782:19] shortq_shift_ff <= _T_1166 @[exu_div_ctl.scala 782:19]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
rvclkhdr_5.clock <= clock rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 392:18] rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1166 <= finish @[Reg.scala 28:23] _T_1167 <= finish @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
finish_ff <= _T_1166 @[exu_div_ctl.scala 783:13] finish_ff <= _T_1167 @[exu_div_ctl.scala 783:13]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
rvclkhdr_6.clock <= clock rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 392:18] rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when misc_enable : @[Reg.scala 28:19] when misc_enable : @[Reg.scala 28:19]
_T_1167 <= count_in @[Reg.scala 28:23] _T_1168 <= count_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
count_ff <= _T_1167 @[exu_div_ctl.scala 784:12] count_ff <= _T_1168 @[exu_div_ctl.scala 784:12]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
rvclkhdr_7.clock <= clock rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 392:18] rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17] rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1169 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when a_enable : @[Reg.scala 28:19] when a_enable : @[Reg.scala 28:19]
_T_1168 <= a_in @[Reg.scala 28:23] _T_1169 <= a_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
a_ff <= _T_1168 @[exu_div_ctl.scala 786:8] a_ff <= _T_1169 @[exu_div_ctl.scala 786:8]
node _T_1169 = bits(b_in, 32, 0) @[exu_div_ctl.scala 787:23] node _T_1170 = bits(b_in, 32, 0) @[exu_div_ctl.scala 787:23]
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
rvclkhdr_8.clock <= clock rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 392:18] rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17] rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1171 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when b_enable : @[Reg.scala 28:19] when b_enable : @[Reg.scala 28:19]
_T_1170 <= _T_1169 @[Reg.scala 28:23] _T_1171 <= _T_1170 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
b_ff1 <= _T_1170 @[exu_div_ctl.scala 787:9] b_ff1 <= _T_1171 @[exu_div_ctl.scala 787:9]
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
rvclkhdr_9.clock <= clock rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 392:18] rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17] rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1171 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when rq_enable : @[Reg.scala 28:19] when rq_enable : @[Reg.scala 28:19]
_T_1171 <= r_in @[Reg.scala 28:23] _T_1172 <= r_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
r_ff <= _T_1171 @[exu_div_ctl.scala 788:8] r_ff <= _T_1172 @[exu_div_ctl.scala 788:8]
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23] inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
rvclkhdr_10.clock <= clock rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 392:18] rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17] rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_1172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_1173 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when rq_enable : @[Reg.scala 28:19] when rq_enable : @[Reg.scala 28:19]
_T_1172 <= q_in @[Reg.scala 28:23] _T_1173 <= q_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
q_ff <= _T_1172 @[exu_div_ctl.scala 789:8] q_ff <= _T_1173 @[exu_div_ctl.scala 789:8]

146
exu_div_new_3bit_fullshortq.v
View File

@ -318,26 +318,26 @@ module exu_div_new_3bit_fullshortq(
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 662:69] wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 662:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 662:67] wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 662:67]
wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 662:80] wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 662:80]
wire [6:0] _T_1038 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58] wire [6:0] _T_1039 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_1039 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58] wire [6:0] _T_1040 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_1041 = _T_1038 - _T_1039; // @[exu_div_ctl.scala 771:41] wire [6:0] _T_1042 = _T_1039 - _T_1040; // @[exu_div_ctl.scala 771:41]
wire [6:0] dw_shortq_raw = _T_1041 + 7'h1; // @[exu_div_ctl.scala 771:61] wire [6:0] dw_shortq_raw = _T_1042 + 7'h1; // @[exu_div_ctl.scala 771:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 772:19] wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 772:19]
wire _T_1047 = ~shortq[5]; // @[exu_div_ctl.scala 773:31] wire _T_1048 = ~shortq[5]; // @[exu_div_ctl.scala 773:31]
wire _T_1048 = valid_ff & _T_1047; // @[exu_div_ctl.scala 773:29] wire _T_1049 = valid_ff & _T_1048; // @[exu_div_ctl.scala 773:29]
wire _T_1050 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 773:58] wire _T_1051 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 773:58]
wire _T_1051 = ~_T_1050; // @[exu_div_ctl.scala 773:44] wire _T_1052 = ~_T_1051; // @[exu_div_ctl.scala 773:44]
wire _T_1052 = _T_1048 & _T_1051; // @[exu_div_ctl.scala 773:42] wire _T_1053 = _T_1049 & _T_1052; // @[exu_div_ctl.scala 773:42]
wire shortq_enable = _T_1052 & _T; // @[exu_div_ctl.scala 773:73] wire shortq_enable = _T_1053 & _T; // @[exu_div_ctl.scala 773:73]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 662:95] wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 662:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 662:93] wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 662:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h3; // @[exu_div_ctl.scala 663:63] wire [6:0] _T_63 = count_ff + 7'h3; // @[exu_div_ctl.scala 663:63]
reg [4:0] _T_1164; // @[Reg.scala 27:20] reg [4:0] _T_1165; // @[Reg.scala 27:20]
wire [5:0] _T_1165 = {_T_1164,1'h0}; // @[Cat.scala 29:58] wire [5:0] _T_1166 = {_T_1165,1'h0}; // @[Cat.scala 29:58]
wire [4:0] shortq_shift_ff = _T_1165[4:0]; // @[exu_div_ctl.scala 782:19] wire [4:0] shortq_shift_ff = _T_1166[4:0]; // @[exu_div_ctl.scala 782:19]
wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58] wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 663:83] wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 663:88]
wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 663:51] wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 663:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 664:43] wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 664:43]
wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 665:47] wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 665:47]
@ -413,9 +413,9 @@ module exu_div_new_3bit_fullshortq(
wire _T_227 = _T_177 & _T_226; // @[exu_div_ctl.scala 694:83] wire _T_227 = _T_177 & _T_226; // @[exu_div_ctl.scala 694:83]
wire _T_228 = _T_223 | _T_227; // @[exu_div_ctl.scala 694:59] wire _T_228 = _T_223 | _T_227; // @[exu_div_ctl.scala 694:59]
wire [7:0] quotient_raw = {_T_180,_T_188,_T_196,_T_204,_T_212,_T_220,_T_228,1'h0}; // @[Cat.scala 29:58] wire [7:0] quotient_raw = {_T_180,_T_188,_T_196,_T_204,_T_212,_T_220,_T_228,1'h0}; // @[Cat.scala 29:58]
wire _T_238 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 695:43] wire _T_238 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 695:41]
wire _T_240 = _T_238 | quotient_raw[5]; // @[exu_div_ctl.scala 695:62] wire _T_240 = _T_238 | quotient_raw[5]; // @[exu_div_ctl.scala 695:60]
wire _T_242 = _T_240 | quotient_raw[4]; // @[exu_div_ctl.scala 695:80] wire _T_242 = _T_240 | quotient_raw[4]; // @[exu_div_ctl.scala 695:78]
wire _T_247 = ~quotient_raw[4]; // @[exu_div_ctl.scala 696:63] wire _T_247 = ~quotient_raw[4]; // @[exu_div_ctl.scala 696:63]
wire _T_249 = _T_247 & quotient_raw[3]; // @[exu_div_ctl.scala 696:80] wire _T_249 = _T_247 & quotient_raw[3]; // @[exu_div_ctl.scala 696:80]
wire _T_250 = _T_238 | _T_249; // @[exu_div_ctl.scala 696:61] wire _T_250 = _T_238 | _T_249; // @[exu_div_ctl.scala 696:61]
@ -450,6 +450,9 @@ module exu_div_new_3bit_fullshortq(
wire _T_103 = quotient_new == 3'h6; // @[exu_div_ctl.scala 679:61] wire _T_103 = quotient_new == 3'h6; // @[exu_div_ctl.scala 679:61]
wire _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 679:45] wire _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 679:45]
wire r_adder6_sel = _T_104 & _T_67; // @[exu_div_ctl.scala 679:70] wire r_adder6_sel = _T_104 & _T_67; // @[exu_div_ctl.scala 679:70]
wire _T_106 = quotient_new == 3'h7; // @[exu_div_ctl.scala 680:61]
wire _T_107 = running_state & _T_106; // @[exu_div_ctl.scala 680:45]
wire r_adder7_sel = _T_107 & _T_67; // @[exu_div_ctl.scala 680:70]
reg [31:0] q_ff; // @[Reg.scala 27:20] reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_274 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_274 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_275 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_275 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
@ -581,7 +584,7 @@ module exu_div_new_3bit_fullshortq(
wire [32:0] _T_540 = r_adder4_sel ? _T_167[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_540 = r_adder4_sel ? _T_167[32:0] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_541 = r_adder5_sel ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_541 = r_adder5_sel ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_542 = r_adder6_sel ? _T_171[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_542 = r_adder6_sel ? _T_171[32:0] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_543 = r_adder6_sel ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_543 = r_adder7_sel ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_544 = shortq_enable_ff ? ar_shifted[65:33] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_544 = shortq_enable_ff ? ar_shifted[65:33] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_545 = by_zero_case ? _T_534 : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_545 = by_zero_case ? _T_534 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_546 = _T_535 | _T_536; // @[Mux.scala 27:72] wire [32:0] _T_546 = _T_535 | _T_536; // @[Mux.scala 27:72]
@ -736,70 +739,68 @@ module exu_div_new_3bit_fullshortq(
wire [31:0] _T_574 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_574 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_575 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_575 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_576 = _T_573 | _T_574; // @[Mux.scala 27:72] wire [31:0] _T_576 = _T_573 | _T_574; // @[Mux.scala 27:72]
wire [33:0] shortq_dividend = {control_ff[2],a_ff}; // @[Cat.scala 29:58] wire _T_1060 = shortq == 6'h1b; // @[exu_div_ctl.scala 775:58]
wire _T_1059 = shortq == 6'h1b; // @[exu_div_ctl.scala 775:58] wire _T_1061 = shortq == 6'h1a; // @[exu_div_ctl.scala 775:58]
wire _T_1060 = shortq == 6'h1a; // @[exu_div_ctl.scala 775:58] wire _T_1062 = shortq == 6'h19; // @[exu_div_ctl.scala 775:58]
wire _T_1061 = shortq == 6'h19; // @[exu_div_ctl.scala 775:58] wire _T_1063 = shortq == 6'h18; // @[exu_div_ctl.scala 775:58]
wire _T_1062 = shortq == 6'h18; // @[exu_div_ctl.scala 775:58] wire _T_1064 = shortq == 6'h17; // @[exu_div_ctl.scala 775:58]
wire _T_1063 = shortq == 6'h17; // @[exu_div_ctl.scala 775:58] wire _T_1065 = shortq == 6'h16; // @[exu_div_ctl.scala 775:58]
wire _T_1064 = shortq == 6'h16; // @[exu_div_ctl.scala 775:58] wire _T_1066 = shortq == 6'h15; // @[exu_div_ctl.scala 775:58]
wire _T_1065 = shortq == 6'h15; // @[exu_div_ctl.scala 775:58] wire _T_1067 = shortq == 6'h14; // @[exu_div_ctl.scala 775:58]
wire _T_1066 = shortq == 6'h14; // @[exu_div_ctl.scala 775:58] wire _T_1068 = shortq == 6'h13; // @[exu_div_ctl.scala 775:58]
wire _T_1067 = shortq == 6'h13; // @[exu_div_ctl.scala 775:58] wire _T_1069 = shortq == 6'h12; // @[exu_div_ctl.scala 775:58]
wire _T_1068 = shortq == 6'h12; // @[exu_div_ctl.scala 775:58] wire _T_1070 = shortq == 6'h11; // @[exu_div_ctl.scala 775:58]
wire _T_1069 = shortq == 6'h11; // @[exu_div_ctl.scala 775:58] wire _T_1071 = shortq == 6'h10; // @[exu_div_ctl.scala 775:58]
wire _T_1070 = shortq == 6'h10; // @[exu_div_ctl.scala 775:58] wire _T_1072 = shortq == 6'hf; // @[exu_div_ctl.scala 775:58]
wire _T_1071 = shortq == 6'hf; // @[exu_div_ctl.scala 775:58] wire _T_1073 = shortq == 6'he; // @[exu_div_ctl.scala 775:58]
wire _T_1072 = shortq == 6'he; // @[exu_div_ctl.scala 775:58] wire _T_1074 = shortq == 6'hd; // @[exu_div_ctl.scala 775:58]
wire _T_1073 = shortq == 6'hd; // @[exu_div_ctl.scala 775:58] wire _T_1075 = shortq == 6'hc; // @[exu_div_ctl.scala 775:58]
wire _T_1074 = shortq == 6'hc; // @[exu_div_ctl.scala 775:58] wire _T_1076 = shortq == 6'hb; // @[exu_div_ctl.scala 775:58]
wire _T_1075 = shortq == 6'hb; // @[exu_div_ctl.scala 775:58] wire _T_1077 = shortq == 6'ha; // @[exu_div_ctl.scala 775:58]
wire _T_1076 = shortq == 6'ha; // @[exu_div_ctl.scala 775:58] wire _T_1078 = shortq == 6'h9; // @[exu_div_ctl.scala 775:58]
wire _T_1077 = shortq == 6'h9; // @[exu_div_ctl.scala 775:58] wire _T_1079 = shortq == 6'h8; // @[exu_div_ctl.scala 775:58]
wire _T_1078 = shortq == 6'h8; // @[exu_div_ctl.scala 775:58] wire _T_1080 = shortq == 6'h7; // @[exu_div_ctl.scala 775:58]
wire _T_1079 = shortq == 6'h7; // @[exu_div_ctl.scala 775:58] wire _T_1081 = shortq == 6'h6; // @[exu_div_ctl.scala 775:58]
wire _T_1080 = shortq == 6'h6; // @[exu_div_ctl.scala 775:58] wire _T_1082 = shortq == 6'h5; // @[exu_div_ctl.scala 775:58]
wire _T_1081 = shortq == 6'h5; // @[exu_div_ctl.scala 775:58] wire _T_1083 = shortq == 6'h4; // @[exu_div_ctl.scala 775:58]
wire _T_1082 = shortq == 6'h4; // @[exu_div_ctl.scala 775:58] wire _T_1084 = shortq == 6'h3; // @[exu_div_ctl.scala 775:58]
wire _T_1083 = shortq == 6'h3; // @[exu_div_ctl.scala 775:58] wire _T_1085 = shortq == 6'h2; // @[exu_div_ctl.scala 775:58]
wire _T_1084 = shortq == 6'h2; // @[exu_div_ctl.scala 775:58] wire _T_1086 = shortq == 6'h1; // @[exu_div_ctl.scala 775:58]
wire _T_1085 = shortq == 6'h1; // @[exu_div_ctl.scala 775:58] wire _T_1087 = shortq == 6'h0; // @[exu_div_ctl.scala 775:58]
wire _T_1086 = shortq == 6'h0; // @[exu_div_ctl.scala 775:58] wire [1:0] _T_1092 = _T_1060 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1091 = _T_1059 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_1092 = _T_1060 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_1093 = _T_1061 ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1093 = _T_1061 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_1094 = _T_1062 ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1094 = _T_1062 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1095 = _T_1063 ? 4'h9 : 4'h0; // @[Mux.scala 27:72] wire [2:0] _T_1095 = _T_1063 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1096 = _T_1064 ? 4'h9 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1096 = _T_1064 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1097 = _T_1065 ? 4'h9 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1097 = _T_1065 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1098 = _T_1066 ? 4'hc : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1098 = _T_1066 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1099 = _T_1067 ? 4'hc : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1099 = _T_1067 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1100 = _T_1068 ? 4'hc : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1100 = _T_1068 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1101 = _T_1069 ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1101 = _T_1069 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1102 = _T_1070 ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1102 = _T_1070 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_1103 = _T_1071 ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1103 = _T_1071 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1104 = _T_1072 ? 5'h12 : 5'h0; // @[Mux.scala 27:72] wire [3:0] _T_1104 = _T_1072 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1105 = _T_1073 ? 5'h12 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1105 = _T_1073 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1106 = _T_1074 ? 5'h12 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1106 = _T_1074 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1107 = _T_1075 ? 5'h15 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1107 = _T_1075 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1108 = _T_1076 ? 5'h15 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1108 = _T_1076 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1109 = _T_1077 ? 5'h15 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1109 = _T_1077 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1110 = _T_1078 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1110 = _T_1078 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1111 = _T_1079 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1111 = _T_1079 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1112 = _T_1080 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1112 = _T_1080 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1113 = _T_1081 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1113 = _T_1081 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1114 = _T_1082 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1114 = _T_1082 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1115 = _T_1083 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1115 = _T_1083 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1116 = _T_1084 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1116 = _T_1084 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1117 = _T_1085 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1117 = _T_1085 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1118 = _T_1086 ? 5'h1b : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_1118 = _T_1086 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [2:0] _GEN_12 = {{1'd0}, _T_1091}; // @[Mux.scala 27:72] wire [4:0] _T_1119 = _T_1087 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [2:0] _T_1123 = _GEN_12 | _T_1092; // @[Mux.scala 27:72] wire [2:0] _GEN_12 = {{1'd0}, _T_1092}; // @[Mux.scala 27:72]
wire [2:0] _T_1124 = _T_1123 | _T_1093; // @[Mux.scala 27:72] wire [2:0] _T_1124 = _GEN_12 | _T_1093; // @[Mux.scala 27:72]
wire [2:0] _T_1125 = _T_1124 | _T_1094; // @[Mux.scala 27:72] wire [2:0] _T_1125 = _T_1124 | _T_1094; // @[Mux.scala 27:72]
wire [3:0] _GEN_13 = {{1'd0}, _T_1125}; // @[Mux.scala 27:72] wire [2:0] _T_1126 = _T_1125 | _T_1095; // @[Mux.scala 27:72]
wire [3:0] _T_1126 = _GEN_13 | _T_1095; // @[Mux.scala 27:72] wire [3:0] _GEN_13 = {{1'd0}, _T_1126}; // @[Mux.scala 27:72]
wire [3:0] _T_1127 = _T_1126 | _T_1096; // @[Mux.scala 27:72] wire [3:0] _T_1127 = _GEN_13 | _T_1096; // @[Mux.scala 27:72]
wire [3:0] _T_1128 = _T_1127 | _T_1097; // @[Mux.scala 27:72] wire [3:0] _T_1128 = _T_1127 | _T_1097; // @[Mux.scala 27:72]
wire [3:0] _T_1129 = _T_1128 | _T_1098; // @[Mux.scala 27:72] wire [3:0] _T_1129 = _T_1128 | _T_1098; // @[Mux.scala 27:72]
wire [3:0] _T_1130 = _T_1129 | _T_1099; // @[Mux.scala 27:72] wire [3:0] _T_1130 = _T_1129 | _T_1099; // @[Mux.scala 27:72]
@ -807,9 +808,9 @@ module exu_div_new_3bit_fullshortq(
wire [3:0] _T_1132 = _T_1131 | _T_1101; // @[Mux.scala 27:72] wire [3:0] _T_1132 = _T_1131 | _T_1101; // @[Mux.scala 27:72]
wire [3:0] _T_1133 = _T_1132 | _T_1102; // @[Mux.scala 27:72] wire [3:0] _T_1133 = _T_1132 | _T_1102; // @[Mux.scala 27:72]
wire [3:0] _T_1134 = _T_1133 | _T_1103; // @[Mux.scala 27:72] wire [3:0] _T_1134 = _T_1133 | _T_1103; // @[Mux.scala 27:72]
wire [4:0] _GEN_14 = {{1'd0}, _T_1134}; // @[Mux.scala 27:72] wire [3:0] _T_1135 = _T_1134 | _T_1104; // @[Mux.scala 27:72]
wire [4:0] _T_1135 = _GEN_14 | _T_1104; // @[Mux.scala 27:72] wire [4:0] _GEN_14 = {{1'd0}, _T_1135}; // @[Mux.scala 27:72]
wire [4:0] _T_1136 = _T_1135 | _T_1105; // @[Mux.scala 27:72] wire [4:0] _T_1136 = _GEN_14 | _T_1105; // @[Mux.scala 27:72]
wire [4:0] _T_1137 = _T_1136 | _T_1106; // @[Mux.scala 27:72] wire [4:0] _T_1137 = _T_1136 | _T_1106; // @[Mux.scala 27:72]
wire [4:0] _T_1138 = _T_1137 | _T_1107; // @[Mux.scala 27:72] wire [4:0] _T_1138 = _T_1137 | _T_1107; // @[Mux.scala 27:72]
wire [4:0] _T_1139 = _T_1138 | _T_1108; // @[Mux.scala 27:72] wire [4:0] _T_1139 = _T_1138 | _T_1108; // @[Mux.scala 27:72]
@ -822,7 +823,8 @@ module exu_div_new_3bit_fullshortq(
wire [4:0] _T_1146 = _T_1145 | _T_1115; // @[Mux.scala 27:72] wire [4:0] _T_1146 = _T_1145 | _T_1115; // @[Mux.scala 27:72]
wire [4:0] _T_1147 = _T_1146 | _T_1116; // @[Mux.scala 27:72] wire [4:0] _T_1147 = _T_1146 | _T_1116; // @[Mux.scala 27:72]
wire [4:0] _T_1148 = _T_1147 | _T_1117; // @[Mux.scala 27:72] wire [4:0] _T_1148 = _T_1147 | _T_1117; // @[Mux.scala 27:72]
wire [4:0] shortq_decode = _T_1148 | _T_1118; // @[Mux.scala 27:72] wire [4:0] _T_1149 = _T_1148 | _T_1118; // @[Mux.scala 27:72]
wire [4:0] shortq_decode = _T_1149 | _T_1119; // @[Mux.scala 27:72]
exu_div_cls a_enc ( // @[exu_div_ctl.scala 763:21] exu_div_cls a_enc ( // @[exu_div_ctl.scala 763:21]
.io_operand(a_enc_io_operand), .io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls) .io_cls(a_enc_io_cls)
@ -877,7 +879,7 @@ module exu_div_new_3bit_fullshortq(
); );
assign io_data_out = _T_576 | _T_575; // @[exu_div_ctl.scala 733:15] assign io_data_out = _T_576 | _T_575; // @[exu_div_ctl.scala 733:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 732:16] assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 732:16]
assign a_enc_io_operand = shortq_dividend[32:0]; // @[exu_div_ctl.scala 764:20] assign a_enc_io_operand = {control_ff[2],a_ff[31:0]}; // @[exu_div_ctl.scala 764:20]
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 767:20] assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 767:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17] assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
@ -951,7 +953,7 @@ initial begin
_RAND_6 = {1{`RANDOM}}; _RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0]; finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}}; _RAND_7 = {1{`RANDOM}};
_T_1164 = _RAND_7[4:0]; _T_1165 = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}}; _RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0]; by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {2{`RANDOM}}; _RAND_9 = {2{`RANDOM}};
@ -981,7 +983,7 @@ initial begin
finish_ff = 1'h0; finish_ff = 1'h0;
end end
if (reset) begin if (reset) begin
_T_1164 = 5'h0; _T_1165 = 5'h0;
end end
if (reset) begin if (reset) begin
by_zero_case_ff = 1'h0; by_zero_case_ff = 1'h0;
@ -1049,12 +1051,12 @@ end // initial
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
_T_1164 <= 5'h0; _T_1165 <= 5'h0;
end else if (misc_enable) begin end else if (misc_enable) begin
if (_T_58) begin if (_T_58) begin
_T_1164 <= 5'h0; _T_1165 <= 5'h0;
end else begin end else begin
_T_1164 <= shortq_decode; _T_1165 <= shortq_decode;
end end
end end
end end

6
src/main/scala/exu/exu_div_ctl.scala
View File

@ -660,7 +660,7 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
val finish_raw = smallnum_case | by_zero_case | (count_ff === 33.U) val finish_raw = smallnum_case | by_zero_case | (count_ff === 33.U)
val finish = finish_raw & !io.cancel val finish = finish_raw & !io.cancel
val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
val count_in = Fill(7,count_enable) & (count_ff + Cat(0.U(5.W),3.U) + Cat(0.U(2.W),shortq_shift_ff)) val count_in = Fill(7,count_enable) & (count_ff + Cat(0.U(5.W),3.U(2.W)) + Cat(0.U(2.W),shortq_shift_ff))
val a_enable = io.valid_in | running_state val a_enable = io.valid_in | running_state
val a_shift = running_state & !shortq_enable_ff val a_shift = running_state & !shortq_enable_ff
ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff) << shortq_shift_ff ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff) << shortq_shift_ff
@ -677,7 +677,7 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff
val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff
val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff
val r_adder7_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff
val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0) val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U) val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0) val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
@ -759,7 +759,7 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) | pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0)) pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
val shortq_dividend = Cat(dividend_sign_ff,a_ff) val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
val a_enc = Module(new exu_div_cls) val a_enc = Module(new exu_div_cls)
a_enc.io.operand := shortq_dividend a_enc.io.operand := shortq_dividend
val dw_a_enc1 = a_enc.io.cls val dw_a_enc1 = a_enc.io.cls

BIN
target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class
View File

Binary file not shown.