miss state update

2020-10-23 16:24:56 +05:00 · 2020-10-23 16:24:56 +05:00 · 6761b7a5fc
parent 0a577090a2
commit 6761b7a5fc
4 changed files with 14305 additions and 14302 deletions
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@ -448,7 +448,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
    (ic_miss_buff_data_valid_bypass_index & (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2) === Fill(ICACHE_BEAT_BITS,1.U)))

  stream_hit_f := (miss_state===stream_C) & (miss_buff_hit_unq_f & !miss_wrap_f)
-  stream_miss_f := (miss_state===stream_C) & (miss_buff_hit_unq_f & !miss_wrap_f) & ifc_fetch_req_f
+  stream_miss_f := (miss_state===stream_C) & !(miss_buff_hit_unq_f & !miss_wrap_f) & ifc_fetch_req_f
  stream_eol_f := (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,1)===Fill(ICACHE_BEAT_BITS, 1.U)) & ifc_fetch_req_f & stream_hit_f
  crit_byp_hit_f := miss_buff_hit_unq_f & ((miss_state===crit_wrd_rdy_C) | (miss_state===crit_byp_ok_C))

--- a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
+++ b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class