From 68653daa2c121f7834ce846a5427efe63f52d853 Mon Sep 17 00:00:00 2001
From: colin <lianghongkey@gmail.com>
Date: Tue, 15 Mar 2022 11:38:18 +0000
Subject: [PATCH] Add clk out for fpga.

---
 soc/soc_sim.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/soc/soc_sim.sv b/soc/soc_sim.sv
index 490b9b39..3ce71d79 100644
--- a/soc/soc_sim.sv
+++ b/soc/soc_sim.sv
@@ -1,7 +1,7 @@
 module soc_sim (
     input bit core_clk
 );
-
+  wire          clk_out;
   logic         rst_l;
   logic         dbg_rst_l;
 
@@ -363,6 +363,7 @@ module soc_sim (
 
   soc_top rvsoc (
       .clk(core_clk),
+      .clk_o(clk_out),
       .rst(rst_l),
       .dbg_rst(dbg_rst_l),