Bus Buffer Skeleton
This commit is contained in:
Jahanzaib Rasheed
GitHub
parent
1b50c01e9f
commit
6928b8d554
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package lsu
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import chisel3._
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import chisel3.util._
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import lib._
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import include._
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import snapshot._
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class el2_lsu_bus_buffer extends Module
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{
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val io = IO (new Bundle {
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//val clk = Input(Clock()) //implicit
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//val rst_l = Input(1.W) //implicit
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val scan_mode = Input(Bool())
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val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals
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val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing
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val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus
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val dec_tlu_force_halt = Input(Bool())
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// various clocks needed for the bus reads and writes
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// val lsu_c1_m_clk = Input(Clock())
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// val lsu_c1_r_clk = Input(Clock())
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val lsu_c2_r_clk = Input(Clock())
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val lsu_bus_ibuf_c1_clk = Input(Clock())
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val lsu_bus_obuf_c1_clk = Input(Clock())
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val lsu_bus_buf_c1_clk = Input(Clock())
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val lsu_free_c2_clk = Input(Clock())
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// val free_clk = Input(Clock())
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val lsu_busm_clk = Input(Clock())
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val dec_lsu_valid_raw_d = Input(Bool())
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// val lsu_pkt_m = new el2_lsu_pkt_t
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// val lsu_pkt_r = new el2_lsu_pkt_t
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val lsu_addr_m = Input(UInt(32.W))
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val end_addr_m = Input(UInt(32.W))
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val lsu_addr_r = Input(UInt(32.W))
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val end_addr_r = Input(UInt(32.W))
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val store_data_r = Input(UInt(32.W))
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// val dec_tlu_force_halt = Input(Bool())
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val no_word_merge_r = Input(Bool())
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val no_dword_merge_r = Input(Bool())
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val lsu_busreq_m = Input(Bool())
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val lsu_busreq_r = Output(Bool())
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val ld_full_hit_m = Input(Bool())
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val flush_m_up = Input(Bool())
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val flush_r = Input(Bool())
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val lsu_commit_r = Input(Bool())
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val is_sideeffects_r = Input(Bool())
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val ldst_dual_d = Input(Bool())
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val ldst_dual_m = Input(Bool())
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val ldst_dual_r = Input(Bool())
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val ldst_byteen_ext_m = Input(UInt(8.W))
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val lsu_bus_buffer_pend_any = Output(Bool())
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val lsu_bus_buffer_full_any = Output(Bool())
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val lsu_bus_buffer_empty_any = Output(Bool())
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val lsu_bus_idle_any = Output(Bool())
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val ld_byte_hit_buf_lo = Output((UInt(8.W)))
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val ld_byte_hit_buf_hi = Output((UInt(8.W)))
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val ld_fwddata_buf_lo = Output((UInt(32.W)))
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val ld_fwddata_buf_hi = Output((UInt(32.W)))
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val lsu_imprecise_error_load_any = Output(Bool())
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val lsu_imprecise_error_store_any = Output(Bool())
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val lsu_imprecise_error_addr_any = Output(UInt(32.W))
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val lsu_nonblock_load_valid_m = Output(Bool())
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val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_inv_r = Output(Bool())
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val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_data_valid = Output(Bool())
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val lsu_nonblock_load_data_error = Output(UInt(32.W))
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val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_data = Output(UInt(32.W))
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val lsu_pmu_bus_trxn = Output(Bool())
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val lsu_pmu_bus_misaligned = Output(Bool())
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val lsu_pmu_bus_error = Output(Bool())
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val lsu_pmu_bus_busy = Output(Bool())
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val lsu_axi_awvalid = Output(Bool())
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val lsu_axi_awready = Input(Bool())
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val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_awaddr = Output(UInt(32.W))
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val lsu_axi_awregion = Output(UInt(4.W))
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val lsu_axi_awlen = Output(UInt(8.W))
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val lsu_axi_awsize = Output(UInt(3.W))
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val lsu_axi_awburst = Output(UInt(2.W))
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val lsu_axi_awlock = Output(Bool())
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val lsu_axi_awcache = Output(UInt(4.W))
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val lsu_axi_awprot = Output(UInt(3.W))
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val lsu_axi_awqos = Output(UInt(4.W))
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val lsu_axi_wvalid = Output(Bool())
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val lsu_axi_wready = Input(Bool())
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val lsu_axi_wdata = Output(UInt(64.W))
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val lsu_axi_wstrb = Output(UInt(8.W))
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val lsu_axi_wlast = Output(Bool())
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val lsu_axi_bvalid = Input(Bool())
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val lsu_axi_bready = Output(Bool())
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val lsu_axi_bresp = Input(UInt(2.W))
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val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_arvalid = Output(Bool())
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val lsu_axi_arready = Input(Bool())
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val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_araddr = Output(UInt(32.W))
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val lsu_axi_arregion = Output(UInt(4.W))
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val lsu_axi_arlen = Output(UInt(8.W))
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val lsu_axi_arsize = Output(UInt(3.W))
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val lsu_axi_arburst = Output(UInt(2.W))
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val lsu_axi_arlock = Output(Bool())
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val lsu_axi_arcache = Output(UInt(4.W))
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val lsu_axi_arprot = Output(UInt(3.W))
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val lsu_axi_arqos = Output(UInt(4.W))
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val lsu_axi_rvalid = Input(Bool())
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val lsu_axi_rready = Output(Bool())
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val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_rdata = Input(UInt(64.W))
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val lsu_axi_rresp = Input(UInt(2.W))
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val lsu_axi_rlast = Input(Bool())
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val lsu_bus_clk_en = Input(Bool())
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val lsu_bus_clk_en_q = Input(Bool())
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})
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val lsu_pkt_m = new el2_lsu_pkt_t()
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val lsu_pkt_r = new el2_lsu_pkt_t()
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io.lsu_busreq_r := 0.U
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io.lsu_bus_buffer_pend_any := 0.U
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io.lsu_bus_buffer_full_any := 0.U
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io.lsu_bus_buffer_empty_any := 0.U
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io.lsu_bus_idle_any := 0.U
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io.ld_byte_hit_buf_lo := 0.U
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io.ld_byte_hit_buf_hi := 0.U
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io.ld_fwddata_buf_lo := 0.U
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io.ld_fwddata_buf_hi := 0.U
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io.lsu_imprecise_error_load_any := 0.U
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io.lsu_imprecise_error_store_any := 0.U
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io.lsu_imprecise_error_addr_any := 0.U
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io.lsu_nonblock_load_valid_m := 0.U
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io.lsu_nonblock_load_tag_m := 0.U
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io.lsu_nonblock_load_inv_r := 0.U
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io.lsu_nonblock_load_inv_tag_r := 0.U
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io.lsu_nonblock_load_data_valid := 0.U
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io.lsu_nonblock_load_data_error := 0.U
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io.lsu_nonblock_load_data_tag := 0.U
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io.lsu_nonblock_load_data := 0.U
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io.lsu_pmu_bus_trxn := 0.U
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io.lsu_pmu_bus_misaligned := 0.U
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io.lsu_pmu_bus_error := 0.U
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io.lsu_pmu_bus_busy := 0.U
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io.lsu_axi_awvalid := 0.U
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io.lsu_axi_awid := 0.U
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io.lsu_axi_awaddr := 0.U
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io.lsu_axi_awregion := 0.U
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io.lsu_axi_awlen := 0.U
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io.lsu_axi_awsize := 0.U
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io.lsu_axi_awburst := 0.U
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io.lsu_axi_awlock := 0.U
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io.lsu_axi_awcache := 0.U
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io.lsu_axi_awprot := 0.U
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io.lsu_axi_awqos := 0.U
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io.lsu_axi_wvalid := 0.U
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io.lsu_axi_wdata := 0.U
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io.lsu_axi_wstrb := 0.U
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io.lsu_axi_wlast := 0.U
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io.lsu_axi_bready := 0.U
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io.lsu_axi_arvalid := 0.U
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io.lsu_axi_arid := 0.U
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io.lsu_axi_araddr := 0.U
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io.lsu_axi_arregion := 0.U
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io.lsu_axi_arlen := 0.U
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io.lsu_axi_arsize := 0.U
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io.lsu_axi_arburst := 0.U
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io.lsu_axi_arlock := 0.U
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io.lsu_axi_arcache := 0.U
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io.lsu_axi_arprot := 0.U
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io.lsu_axi_arqos := 0.U
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io.lsu_axi_rready := 0.U
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}
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object busbufferMain extends App {
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println(chisel3.Driver.emitVerilog(new el2_lsu_bus_buffer))
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}
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