ifu bundlized
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|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar">
|
<library name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar">
|
<library name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar">
|
<library name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
|
<library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar">
|
<library name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar">
|
<library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar">
|
<library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar">
|
<library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar">
|
<library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar">
|
<library name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar">
|
<library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar">
|
<library name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: joda-time:joda-time:2.10.1:jar">
|
<library name="sbt: joda-time:joda-time:2.10.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: junit:junit:4.13:jar">
|
<library name="sbt: junit:junit:4.13:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
|
<library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.antlr:antlr4-runtime:4.7.1:jar">
|
<library name="sbt: org.antlr:antlr4-runtime:4.7.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.apache.commons:commons-lang3:3.9:jar">
|
<library name="sbt: org.apache.commons:commons-lang3:3.9:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.apache.commons:commons-text:1.8:jar">
|
<library name="sbt: org.apache.commons:commons-text:1.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.fusesource.jansi:jansi:1.11:jar">
|
<library name="sbt: org.fusesource.jansi:jansi:1.11:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.hamcrest:hamcrest-core:1.3:jar">
|
<library name="sbt: org.hamcrest:hamcrest-core:1.3:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.joda:joda-convert:2.2.0:jar">
|
<library name="sbt: org.joda:joda-convert:2.2.0:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar">
|
<library name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar">
|
<library name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar">
|
<library name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar">
|
<library name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar">
|
<library name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar">
|
<library name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar">
|
<library name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -15,9 +15,11 @@
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -5,9 +5,11 @@
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scala-sbt:test-interface:1.0:jar">
|
<library name="sbt: org.scala-sbt:test-interface:1.0:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar">
|
<library name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar">
|
<library name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar">
|
<library name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
|
@ -2,12 +2,15 @@
|
||||||
<library name="sbt: org.yaml:snakeyaml:1.26:jar">
|
<library name="sbt: org.yaml:snakeyaml:1.26:jar">
|
||||||
<CLASSES>
|
<CLASSES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
|
||||||
</CLASSES>
|
</CLASSES>
|
||||||
<JAVADOC>
|
<JAVADOC>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
|
||||||
</JAVADOC>
|
</JAVADOC>
|
||||||
<SOURCES>
|
<SOURCES>
|
||||||
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
|
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
|
||||||
|
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
|
||||||
</SOURCES>
|
</SOURCES>
|
||||||
</library>
|
</library>
|
||||||
</component>
|
</component>
|
836
.idea/misc.xml
836
.idea/misc.xml
|
@ -1,4 +1,840 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<project version="4">
|
<project version="4">
|
||||||
<component name="ProjectRootManager" version="2" languageLevel="JDK_1_8" default="false" project-jdk-name="11" project-jdk-type="JavaSDK" />
|
<component name="ProjectRootManager" version="2" languageLevel="JDK_1_8" default="false" project-jdk-name="11" project-jdk-type="JavaSDK" />
|
||||||
|
<component name="SVCompilerDirectivesDefines">
|
||||||
|
<option name="define">
|
||||||
|
<map>
|
||||||
|
<entry key="RANDOM">
|
||||||
|
<value>
|
||||||
|
<Define>
|
||||||
|
<option name="definitions">
|
||||||
|
<list>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="153357" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="248582" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="266739" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="418463" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="619760" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="17721" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_exu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="152503" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec_decode_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="9366" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec_tlu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="13807" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="axi4_to_ahb.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="159032" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_pic_ctrl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="477" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="top.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="67095" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_dec_gpr_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="17145" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_exu_alu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="10031" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="offset" value="411371" />
|
||||||
|
<option name="replacementList" value="$random" />
|
||||||
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="dependencies">
|
||||||
|
<set>
|
||||||
|
<option value="el2_exu.v" />
|
||||||
|
<option value="el2_dec_decode_ctl.v" />
|
||||||
|
<option value="el2_dec_tlu_ctl.v" />
|
||||||
|
<option value="axi4_to_ahb.v" />
|
||||||
|
<option value="el2_pic_ctrl.v" />
|
||||||
|
<option value="top.v" />
|
||||||
|
<option value="el2_dec_gpr_ctl.v" />
|
||||||
|
<option value="el2_exu_alu_ctl.v" />
|
||||||
|
<option value="el2_lsu.v" />
|
||||||
|
<option value="el2_ifu_mem_ctl.v" />
|
||||||
|
</set>
|
||||||
|
</option>
|
||||||
|
</Define>
|
||||||
|
</value>
|
||||||
|
</entry>
|
||||||
|
<entry key="RANDOMIZE">
|
||||||
|
<value>
|
||||||
|
<Define>
|
||||||
|
<option name="definitions">
|
||||||
|
<list>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="153158" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="153215" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="153266" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="153317" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="248383" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="248440" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="248491" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="248542" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="266540" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="266597" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="266648" />
|
||||||
|
<option name="source" value="el2_dec.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
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<option name="source" value="top.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="66896" />
|
||||||
|
<option name="source" value="el2_dec_gpr_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="66953" />
|
||||||
|
<option name="source" value="el2_dec_gpr_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="67004" />
|
||||||
|
<option name="source" value="el2_dec_gpr_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="67055" />
|
||||||
|
<option name="source" value="el2_dec_gpr_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="16946" />
|
||||||
|
<option name="source" value="el2_exu_alu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="17003" />
|
||||||
|
<option name="source" value="el2_exu_alu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="17054" />
|
||||||
|
<option name="source" value="el2_exu_alu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="17105" />
|
||||||
|
<option name="source" value="el2_exu_alu_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9832" />
|
||||||
|
<option name="source" value="el2_lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9889" />
|
||||||
|
<option name="source" value="el2_lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9940" />
|
||||||
|
<option name="source" value="el2_lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="9991" />
|
||||||
|
<option name="source" value="el2_lsu.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="411172" />
|
||||||
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="411229" />
|
||||||
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_REG_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="411280" />
|
||||||
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
<Body>
|
||||||
|
<option name="inclusionDependencies">
|
||||||
|
<list>
|
||||||
|
<InclusionDependency>
|
||||||
|
<option name="name" value="RANDOMIZE_MEM_INIT" />
|
||||||
|
<option name="rule" value="DEFINED" />
|
||||||
|
</InclusionDependency>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
<option name="offset" value="411331" />
|
||||||
|
<option name="source" value="el2_ifu_mem_ctl.v" />
|
||||||
|
</Body>
|
||||||
|
</list>
|
||||||
|
</option>
|
||||||
|
</Define>
|
||||||
|
</value>
|
||||||
|
</entry>
|
||||||
|
</map>
|
||||||
|
</option>
|
||||||
|
<option name="version" value="195" />
|
||||||
|
</component>
|
||||||
</project>
|
</project>
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
|
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, /home/abdulhameed.akram/.ivy2/cache|ivy|Local cache, https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, file:/home/abdulhameed.akram/.sbt/preloaded|maven|local-preloaded, https://repo1.maven.org/maven2/|maven|public" type="SBT_MODULE" version="4">
|
||||||
<component name="NewModuleRootManager">
|
<component name="NewModuleRootManager">
|
||||||
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
|
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
|
||||||
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
|
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<module external.linked.project.id="swerv-chislified-master [file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
|
<module external.linked.project.id="swerv-chislified_withlsu [file:/home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
|
||||||
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
|
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
|
||||||
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
|
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
|
||||||
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
|
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
|
||||||
|
|
181
README.md
181
README.md
|
@ -1,181 +0,0 @@
|
||||||
# Quasar RISC-V Core from Lampro Mellon
|
|
||||||
|
|
||||||
This repository contains the Quasar Core design in CHISEL.
|
|
||||||
|
|
||||||
## Background
|
|
||||||
|
|
||||||
Quasar is a Chiselified version of EL2 SweRV RISC-V Core.
|
|
||||||
|
|
||||||
## Directory Structure
|
|
||||||
|
|
||||||
├── project
|
|
||||||
│ ├── project
|
|
||||||
│ └── target
|
|
||||||
├── src
|
|
||||||
│ ├── main
|
|
||||||
│ ├── resource
|
|
||||||
│ └── vsrc # Blackbox files
|
|
||||||
│ └── scala # Design root dir
|
|
||||||
│ ├── dbg # Debugger
|
|
||||||
│ ├── dec # Decode, Registers and Exceptions
|
|
||||||
│ ├── dmi # DMI block
|
|
||||||
│ ├── exu # EXU (ALU/MUL/DIV)
|
|
||||||
│ ├── ifu # Fetch & Branch Prediction
|
|
||||||
│ ├── include # Bundles file
|
|
||||||
│ ├── lib # Bridges and Libraries
|
|
||||||
│ ├── lsu # Load/Store
|
|
||||||
│ ├── snapshot # Configurations Dir
|
|
||||||
│ ├── el2_dma_ctrl.scala #
|
|
||||||
│ ├── el2_pic_ctl.scala #
|
|
||||||
│ └── el2_swerv.scala #
|
|
||||||
│ └── test
|
|
||||||
│ └── scala
|
|
||||||
│ └── lib
|
|
||||||
├── Docs # Spec. document
|
|
||||||
├── rtl # Chisel generated verilog
|
|
||||||
│ ├── ***** #
|
|
||||||
│ └── ***** #
|
|
||||||
├── target
|
|
||||||
│ ├── scala-2.12
|
|
||||||
│ └── streams
|
|
||||||
├── test_run_dir
|
|
||||||
└── build.sbt # Scala-based DSL
|
|
||||||
|
|
||||||
|
|
||||||
## Dependencies
|
|
||||||
|
|
||||||
- Verilator **(4.030 or later)** must be installed on the system if running with verilator.
|
|
||||||
- RISCV tool chain (based on gcc version 7.3 or higher) must be
|
|
||||||
installed so that it can be used to prepare RISCV binaries to run.
|
|
||||||
- Sbt **(1.3.13 or later)** must be installed on the system.
|
|
||||||
|
|
||||||
## Quickstart guide
|
|
||||||
|
|
||||||
1. Clone the repository
|
|
||||||
2. Setup RV_ROOT to point to the path in your local filesystem
|
|
||||||
3. Determine your configuration {optional}
|
|
||||||
4. Run make with Makefile
|
|
||||||
|
|
||||||
## Release Notes for this version
|
|
||||||
Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar.
|
|
||||||
|
|
||||||
### Configurations
|
|
||||||
|
|
||||||
Quasar can be configured by running the `****************************` script:
|
|
||||||
|
|
||||||
`% ****************************` for detailed help options
|
|
||||||
|
|
||||||
For example to build with a DCCM of size 64 Kb:
|
|
||||||
|
|
||||||
`% *******************************`
|
|
||||||
|
|
||||||
This will update the **default** snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM.
|
|
||||||
|
|
||||||
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
|
|
||||||
|
|
||||||
There are 4 predefined target configurations: `default`, `default_mt`, `typical_pd` and `high_perf` that can be selected via
|
|
||||||
the `-target=name` option to swerv.config.
|
|
||||||
|
|
||||||
This script derives the following consistent set of include files :
|
|
||||||
|
|
||||||
$RV_ROOT/configs/snapshots/default
|
|
||||||
├── common_defines.vh # `defines for testbench or design
|
|
||||||
├── defines.h # defines for C/assembly headers
|
|
||||||
├── eh2_param.vh # Design parameters
|
|
||||||
├── eh2_pdef.vh # Parameter structure
|
|
||||||
├── pd_defines.vh # `defines for physical design
|
|
||||||
├── perl_configs.pl # Perl %configs hash for scripting
|
|
||||||
├── pic_map_auto.h # PIC memory map based on configure size
|
|
||||||
└── whisper.json # JSON file for swerv-iss
|
|
||||||
|
|
||||||
### Building a model
|
|
||||||
|
|
||||||
while in a work directory:
|
|
||||||
|
|
||||||
##### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
|
|
||||||
|
|
||||||
Example for bash shell:
|
|
||||||
`export RV_ROOT=/path/to/quasar`
|
|
||||||
Example for csh or its derivatives:
|
|
||||||
`setenv RV_ROOT /path/to/quasar`
|
|
||||||
|
|
||||||
##### 2. Create your specific configuration
|
|
||||||
|
|
||||||
*(Skip if default is sufficient)*
|
|
||||||
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
|
|
||||||
|
|
||||||
set BUILD_PATH environment variable:
|
|
||||||
|
|
||||||
`setenv BUILD_PATH snapshots/mybuild`
|
|
||||||
|
|
||||||
`$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild`
|
|
||||||
|
|
||||||
Snapshots are placed in `$BUILD_PATH` directory
|
|
||||||
|
|
||||||
##### 3. Running a simple Hello World program (verilator)
|
|
||||||
|
|
||||||
`make -f $RV_ROOT/Makefile`
|
|
||||||
|
|
||||||
This command will build a verilator model of Quasar with AXI bus, and
|
|
||||||
execute a short sequence of instructions that writes out "HELLO WORLD"
|
|
||||||
to the bus.
|
|
||||||
|
|
||||||
The simulation produces output on the screen like:
|
|
||||||
|
|
||||||
`***********************************************************************`
|
|
||||||
|
|
||||||
|
|
||||||
The simulation generates following files:
|
|
||||||
|
|
||||||
`console.log` contains what the cpu writes to the console address of 0xd0580000.
|
|
||||||
`exec.log` shows instruction trace with GPR updates.
|
|
||||||
`trace_port.csv` contains a log of the trace port.
|
|
||||||
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
|
|
||||||
|
|
||||||
You can re-execute simulation using:
|
|
||||||
`make -f $RV_ROOT/Makefile verilator`
|
|
||||||
|
|
||||||
The simulation run/build command has following generic form:
|
|
||||||
|
|
||||||
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
|
|
||||||
|
|
||||||
where:
|
|
||||||
```
|
|
||||||
<simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa
|
|
||||||
'riviera'- Aldec Riviera-PRO. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
|
|
||||||
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
|
|
||||||
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'
|
|
||||||
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default
|
|
||||||
TEST_DIR - alternative to test source directory testbench/asm or testbench/tests
|
|
||||||
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument
|
|
||||||
for runs on custom configurations.
|
|
||||||
CONF_PARAMS - allows to provide -set options to swerv.conf script to alter predefined EL2 targets parameters
|
|
||||||
```
|
|
||||||
Example:
|
|
||||||
|
|
||||||
make -f $RV_ROOT/Makefile verilator TEST=cmark
|
|
||||||
|
|
||||||
will build and simulate testbench/asm/cmark.c program with verilator
|
|
||||||
|
|
||||||
|
|
||||||
If you want to compile a test only, you can run:
|
|
||||||
|
|
||||||
make -f $RV_ROOT/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
|
|
||||||
|
|
||||||
|
|
||||||
The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
|
|
||||||
```
|
|
||||||
hello_world - default tes to run, prints Hello World message to screen and console.log
|
|
||||||
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
|
|
||||||
hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
|
|
||||||
it from there. Runs on EL2 with AXI4 buses only.
|
|
||||||
cmark - coremark benchmark running with code and data in external memories
|
|
||||||
cmark_dccm - the same as above, running data and stack from DCCM (faster)
|
|
||||||
cmark_iccm - the same as above with preloaded code to ICCM.
|
|
||||||
```
|
|
||||||
|
|
||||||
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
|
|
||||||
|
|
||||||
**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.
|
|
||||||
|
|
||||||
|
|
|
@ -1,248 +0,0 @@
|
||||||
[
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_ic_premux_data",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_bus_clk_en",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_axi_rid",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_axi_rvalid",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_iccm_rw_addr",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data_ecc",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_wr_addr_lo",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_iccm_wren",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data_ecc",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_wr_addr_hi",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_ic_tag_valid",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_rd_addr_hi",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_rden",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_wren",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_rd_addr_lo",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_wr_data_lo",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_dccm_wr_data_hi",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_ic_rd_en",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_iccm_wr_size",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data_ecc",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_iccm_rden",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data_ecc",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_core_rst_l",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>reset",
|
|
||||||
"~el2_swerv|el2_swerv>io_scan_mode"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_ic_rw_addr",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_ic_sel_premux_data",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_bus_clk_en",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_axi_rid",
|
|
||||||
"~el2_swerv|el2_swerv>io_ifu_axi_rvalid",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_swerv|el2_swerv>io_iccm_wr_data",
|
|
||||||
"sources":[
|
|
||||||
"~el2_swerv|el2_swerv>io_iccm_rd_data_ecc",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_hit",
|
|
||||||
"~el2_swerv|el2_swerv>io_ic_rd_data",
|
|
||||||
"~el2_swerv|el2_swerv>io_mpc_reset_run_req",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_hi",
|
|
||||||
"~el2_swerv|el2_swerv>io_dccm_rd_data_lo",
|
|
||||||
"~el2_swerv|el2_swerv>io_rst_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_nmi_vec",
|
|
||||||
"~el2_swerv|el2_swerv>io_core_id"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.EmitCircuitAnnotation",
|
|
||||||
"emitter":"firrtl.VerilogEmitter"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
|
||||||
"target":"el2_swerv.TEC_RV_ICG",
|
|
||||||
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.DontTouchAnnotation",
|
|
||||||
"target":"~el2_swerv|el2_dec_trigger>io_dec_i0_trigger_match_d"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.options.TargetDirAnnotation",
|
|
||||||
"directory":"."
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
|
||||||
"file":"el2_swerv"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
|
||||||
"targetDir":"."
|
|
||||||
}
|
|
||||||
]
|
|
107885
el2_swerv.fir
107885
el2_swerv.fir
File diff suppressed because one or more lines are too long
78619
el2_swerv.v
78619
el2_swerv.v
File diff suppressed because it is too large
Load Diff
|
@ -1 +1 @@
|
||||||
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/TEC_RV_ICG.v
|
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/gated_latch.v
|
|
@ -1,14 +1,14 @@
|
||||||
module TEC_RV_ICG(
|
module gated_latch
|
||||||
(
|
(
|
||||||
input logic SE, EN, CK,
|
input wire SE, EN, CK,
|
||||||
output Q
|
output Q
|
||||||
);
|
);
|
||||||
logic en_ff;
|
reg en_ff;
|
||||||
logic enable;
|
wire enable;
|
||||||
assign enable = EN | SE;
|
assign enable = EN | SE;
|
||||||
always @(CK, enable) begin
|
always @(CK, enable) begin
|
||||||
if(!CK)
|
if(!CK)
|
||||||
en_ff = enable;
|
en_ff = enable;
|
||||||
end
|
end
|
||||||
assign Q = CK & en_ff;
|
assign Q = CK & en_ff;
|
||||||
endmodule
|
endmodule
|
|
@ -0,0 +1,367 @@
|
||||||
|
[
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_wr_size",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_sz",
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_rden",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_rd_en",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ic_eccerr",
|
||||||
|
"~ifu|ifu>io_ic_tag_perr",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_dma_sb_error",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_wr_data",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_rd_en",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_wr_en",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_addr",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_wr_data",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_wdata",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_tag_array",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_ready",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_sel_premux_data",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_premux_data",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_iccm_rd_data",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_debug_way",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_tag_valid",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_final"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_wren",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_iccm_rw_addr",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_addr",
|
||||||
|
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
|
||||||
|
"~ifu|ifu>io_iccm_rd_data_ecc",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
|
||||||
|
"~ifu|ifu>io_ic_rd_data",
|
||||||
|
"~ifu|ifu>io_ifu_r_bits_id",
|
||||||
|
"~ifu|ifu>io_ifu_r_valid",
|
||||||
|
"~ifu|ifu>io_ifu_bus_clk_en"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~ifu|ifu>io_ic_rw_addr",
|
||||||
|
"sources":[
|
||||||
|
"~ifu|ifu>io_exu_flush_path_final",
|
||||||
|
"~ifu|ifu>io_exu_flush_final",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||||
|
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
|
||||||
|
"~ifu|ifu>io_ic_rd_hit",
|
||||||
|
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"ifu.gated_latch",
|
||||||
|
"resourceId":"/vsrc/gated_latch.v"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"ifu"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
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@ -0,0 +1,4 @@
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mdownloaded https://repo1.maven.org/maven2/org/jetbrains/scala/scala-compiler-indices-protocol_2.12/1.0.8/scala-compiler-indices-protocol_2.12-1.0.8.pom[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mdownloaded https://repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.5/spray-json_2.12-1.3.5.pom[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mdownloaded https://repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.5/spray-json_2.12-1.3.5.jar[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mdownloaded https://repo1.maven.org/maven2/org/jetbrains/scala/scala-compiler-indices-protocol_2.12/1.0.8/scala-compiler-indices-protocol_2.12-1.0.8.jar[0m
|
|
@ -0,0 +1,2 @@
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
@ -1,5 +0,0 @@
|
||||||
# Quasar RISC-V Core 1.0 from Lampro Mellon
|
|
||||||
|
|
||||||
## Release Notes
|
|
||||||
|
|
||||||
Initial release
|
|
|
@ -1,110 +0,0 @@
|
||||||
<scalastyle>
|
|
||||||
<name>Scalastyle standard configuration</name>
|
|
||||||
<check level="warning" class="org.scalastyle.file.FileTabChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.FileLengthChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxFileLength"><![CDATA[800]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.HeaderMatchesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="header"><![CDATA[// See README.md for license details.]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.SpacesAfterPlusChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.WhitespaceEndOfLineChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.SpacesBeforePlusChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.FileLineLengthChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxLineLength"><![CDATA[120]]></parameter>
|
|
||||||
<parameter name="tabSize"><![CDATA[4]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.ClassNamesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.ObjectNamesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.PackageObjectNamesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[^[a-z][A-Za-z]*$]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.EqualsHashCodeChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.IllegalImportsChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="illegalImports"><![CDATA[sun._,java.awt._]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.ParameterNumberChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxParameters"><![CDATA[8]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.MagicNumberChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="ignore"><![CDATA[-1,0,1,2,8,10,16]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NoWhitespaceBeforeLeftBracketChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NoWhitespaceAfterLeftBracketChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.ReturnChecker" enabled="false"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NullChecker" enabled="false"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NoCloneChecker" enabled="false"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NoFinalizeChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.CovariantEqualsChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.StructuralTypeChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.RegexChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[;(\r|)\n]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
<customMessage>No lines ending with a ;</customMessage>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.RegexChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[println]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NumberOfTypesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxTypes"><![CDATA[30]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.CyclomaticComplexityChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maximum"><![CDATA[10]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.UppercaseLChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.SimplifyBooleanExpressionChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.IfBraceChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="singleLineAllowed"><![CDATA[true]]></parameter>
|
|
||||||
<parameter name="doubleLineAllowed"><![CDATA[false]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.MethodLengthChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxLength"><![CDATA[50]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.MethodNamesChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="regex"><![CDATA[^[a-z][A-Za-z0-9]*$]]></parameter>
|
|
||||||
<parameter name="ignoreRegex"><![CDATA[^(\+[&%]?|\-[&%]?|\*|/|%|&|\||\^|<|>|\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NumberOfMethodsInTypeChecker" enabled="true">
|
|
||||||
<parameters>
|
|
||||||
<parameter name="maxMethods"><![CDATA[30]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.PublicMethodsHaveTypeChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.NewLineAtEofChecker" enabled="true"></check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.NoNewLineAtEofChecker" enabled="false"></check>
|
|
||||||
</scalastyle>
|
|
|
@ -1,109 +0,0 @@
|
||||||
<scalastyle>
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|
||||||
<name>Scalastyle configuration for Chisel3 unit tests</name>
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|
||||||
<check level="warning" class="org.scalastyle.file.FileTabChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.file.FileLengthChecker" enabled="true">
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<parameters>
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<parameter name="maxFileLength"><![CDATA[800]]></parameter>
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</parameters>
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</check>
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<check level="warning" class="org.scalastyle.file.HeaderMatchesChecker" enabled="true">
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<parameters>
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|
||||||
<parameter name="header"><![CDATA[// See README.md for license details.]]></parameter>
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|
||||||
</parameters>
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</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.SpacesAfterPlusChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.file.WhitespaceEndOfLineChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.file.FileLineLengthChecker" enabled="true">
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<parameters>
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<parameter name="maxLineLength"><![CDATA[120]]></parameter>
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<parameter name="tabSize"><![CDATA[4]]></parameter>
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</parameters>
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<check level="warning" class="org.scalastyle.scalariform.ClassNamesChecker" enabled="true">
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<parameters>
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<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
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</check>
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<check level="warning" class="org.scalastyle.scalariform.ObjectNamesChecker" enabled="true">
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<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
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||||||
</parameters>
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||||||
</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.PackageObjectNamesChecker" enabled="true">
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||||||
<parameters>
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||||||
<parameter name="regex"><![CDATA[^[a-z][A-Za-z]*$]]></parameter>
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||||||
</parameters>
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||||||
</check>
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||||||
<check level="warning" class="org.scalastyle.scalariform.EqualsHashCodeChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.scalariform.IllegalImportsChecker" enabled="true">
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|
||||||
<parameters>
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||||||
<parameter name="illegalImports"><![CDATA[sun._,java.awt._]]></parameter>
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|
||||||
</parameters>
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||||||
</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.ParameterNumberChecker" enabled="true">
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||||||
<parameters>
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|
||||||
<parameter name="maxParameters"><![CDATA[8]]></parameter>
|
|
||||||
</parameters>
|
|
||||||
</check>
|
|
||||||
<!-- Numerical constants are used a lot in test setups, it would be burdensome to require each one be its own val
|
|
||||||
declaration. -->
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.MagicNumberChecker" enabled="false"></check>
|
|
||||||
<!-- Scalatest's exception checking syntax looks like "a [ChiselException] should be thrownBy". -->
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||||||
<check level="warning" class="org.scalastyle.scalariform.NoWhitespaceBeforeLeftBracketChecker" enabled="false"></check>
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<check level="warning" class="org.scalastyle.scalariform.NoWhitespaceAfterLeftBracketChecker" enabled="true"></check>
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<check level="warning" class="org.scalastyle.scalariform.ReturnChecker" enabled="false"></check>
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||||||
<check level="warning" class="org.scalastyle.scalariform.NoCloneChecker" enabled="false"></check>
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<check level="warning" class="org.scalastyle.scalariform.NoFinalizeChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.scalariform.CovariantEqualsChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.scalariform.StructuralTypeChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.file.RegexChecker" enabled="true">
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||||||
<parameters>
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||||||
<parameter name="regex"><![CDATA[^.*;(\r|)\n]]></parameter>
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||||||
</parameters>
|
|
||||||
<customMessage>No lines ending with a ;</customMessage>
|
|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.file.RegexChecker" enabled="true">
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||||||
<parameters>
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|
||||||
<parameter name="regex"><![CDATA[println]]></parameter>
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||||||
</parameters>
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|
||||||
</check>
|
|
||||||
<check level="warning" class="org.scalastyle.scalariform.NumberOfTypesChecker" enabled="true">
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||||||
<parameters>
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||||||
<parameter name="maxTypes"><![CDATA[30]]></parameter>
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</parameters>
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|
||||||
</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.CyclomaticComplexityChecker" enabled="true">
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||||||
<parameters>
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||||||
<parameter name="maximum"><![CDATA[10]]></parameter>
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</parameters>
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</check>
|
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<check level="warning" class="org.scalastyle.scalariform.UppercaseLChecker" enabled="true"></check>
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<check level="warning" class="org.scalastyle.scalariform.IfBraceChecker" enabled="true">
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<parameters>
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||||||
<parameter name="singleLineAllowed"><![CDATA[true]]></parameter>
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<parameter name="doubleLineAllowed"><![CDATA[false]]></parameter>
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</parameters>
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</check>
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<check level="warning" class="org.scalastyle.scalariform.MethodLengthChecker" enabled="true">
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<parameters>
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<parameter name="maxLength"><![CDATA[50]]></parameter>
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</check>
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<check level="warning" class="org.scalastyle.scalariform.MethodNamesChecker" enabled="true">
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||||||
<parameters>
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|
||||||
<parameter name="regex"><![CDATA[^[a-z][A-Za-z0-9]*$]]></parameter>
|
|
||||||
<parameter name="ignoreRegex"><![CDATA[^(\+[&%]?|\-[&%]?|\*|/|%|&|\||\^|<|>|\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]></parameter>
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|
||||||
</parameters>
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|
||||||
</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.NumberOfMethodsInTypeChecker" enabled="true">
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||||||
<parameters>
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|
||||||
<parameter name="maxMethods"><![CDATA[30]]></parameter>
|
|
||||||
</parameters>
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|
||||||
</check>
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|
||||||
<check level="warning" class="org.scalastyle.scalariform.PublicMethodsHaveTypeChecker" enabled="true"></check>
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<check level="warning" class="org.scalastyle.file.NewLineAtEofChecker" enabled="true"></check>
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||||||
<check level="warning" class="org.scalastyle.file.NoNewLineAtEofChecker" enabled="false"></check>
|
|
||||||
</scalastyle>
|
|
|
@ -1,64 +0,0 @@
|
||||||
// SPDX-License-Identifier: Apache-2.0
|
|
||||||
// Copyright 2018 Western Digital Corporation or it's affiliates.
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
//------------------------------------------------------------------------------------
|
|
||||||
//
|
|
||||||
// Copyright Western Digital, 2019
|
|
||||||
// Owner : Alex Grobman
|
|
||||||
// Description:
|
|
||||||
// This module Synchronizes the signals between JTAG (TCK) and
|
|
||||||
// processor (Core_clk)
|
|
||||||
//
|
|
||||||
//-------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
module dmi_jtag_to_core_sync (
|
|
||||||
// JTAG signals
|
|
||||||
input rd_en, // 1 bit Read Enable from JTAG
|
|
||||||
input wr_en, // 1 bit Write enable from JTAG
|
|
||||||
|
|
||||||
// Processor Signals
|
|
||||||
input rst_n, // Core reset
|
|
||||||
input clk, // Core clock
|
|
||||||
|
|
||||||
output reg_en, // 1 bit Write interface bit to Processor
|
|
||||||
output reg_wr_en // 1 bit Write enable to Processor
|
|
||||||
);
|
|
||||||
|
|
||||||
wire c_rd_en;
|
|
||||||
wire c_wr_en;
|
|
||||||
reg [2:0] rden, wren;
|
|
||||||
|
|
||||||
|
|
||||||
// Outputs
|
|
||||||
assign reg_en = c_wr_en | c_rd_en;
|
|
||||||
assign reg_wr_en = c_wr_en;
|
|
||||||
|
|
||||||
|
|
||||||
// synchronizers
|
|
||||||
always @ ( posedge clk or negedge rst_n) begin
|
|
||||||
if(!rst_n) begin
|
|
||||||
rden <= '0;
|
|
||||||
wren <= '0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
rden <= {rden[1:0], rd_en};
|
|
||||||
wren <= {wren[1:0], wr_en};
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
assign c_rd_en = rden[1] & ~rden[2];
|
|
||||||
assign c_wr_en = wren[1] & ~wren[2];
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
|
@ -1,90 +0,0 @@
|
||||||
// SPDX-License-Identifier: Apache-2.0
|
|
||||||
// Copyright 2018 Western Digital Corporation or it's affiliates.
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
//------------------------------------------------------------------------------------
|
|
||||||
//
|
|
||||||
// Copyright Western Digital, 2018
|
|
||||||
// Owner : Anusha Narayanamoorthy
|
|
||||||
// Description:
|
|
||||||
// Wrapper module for JTAG_TAP and DMI synchronizer
|
|
||||||
//
|
|
||||||
//-------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
module dmi_wrapper(
|
|
||||||
|
|
||||||
// JTAG signals
|
|
||||||
input trst_n, // JTAG reset
|
|
||||||
input tck, // JTAG clock
|
|
||||||
input tms, // Test mode select
|
|
||||||
input tdi, // Test Data Input
|
|
||||||
output tdo, // Test Data Output
|
|
||||||
output tdoEnable, // Test Data Output enable
|
|
||||||
|
|
||||||
// Processor Signals
|
|
||||||
input core_rst_n, // Core reset
|
|
||||||
input core_clk, // Core clock
|
|
||||||
input [31:1] jtag_id, // JTAG ID
|
|
||||||
input [31:0] rd_data, // 32 bit Read data from Processor
|
|
||||||
output [31:0] reg_wr_data, // 32 bit Write data to Processor
|
|
||||||
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
|
|
||||||
output reg_en, // 1 bit Read enable to Processor
|
|
||||||
output reg_wr_en, // 1 bit Write enable to Processor
|
|
||||||
output dmi_hard_reset
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Wire Declaration
|
|
||||||
wire rd_en;
|
|
||||||
wire wr_en;
|
|
||||||
wire dmireset;
|
|
||||||
|
|
||||||
|
|
||||||
//jtag_tap instantiation
|
|
||||||
rvjtag_tap i_jtag_tap(
|
|
||||||
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
|
||||||
.tck(tck), // dedicated JTAG TCK pad signal
|
|
||||||
.tms(tms), // dedicated JTAG TMS pad signal
|
|
||||||
.tdi(tdi), // dedicated JTAG TDI pad signal
|
|
||||||
.tdo(tdo), // dedicated JTAG TDO pad signal
|
|
||||||
.tdoEnable(tdoEnable), // enable for TDO pad
|
|
||||||
.wr_data(reg_wr_data), // 32 bit Write data
|
|
||||||
.wr_addr(reg_wr_addr), // 7 bit Write address
|
|
||||||
.rd_en(rd_en), // 1 bit read enable
|
|
||||||
.wr_en(wr_en), // 1 bit Write enable
|
|
||||||
.rd_data(rd_data), // 32 bit Read data
|
|
||||||
.rd_status(2'b0),
|
|
||||||
.idle(3'h0), // no need to wait to sample data
|
|
||||||
.dmi_stat(2'b0), // no need to wait or error possible
|
|
||||||
.version(4'h1), // debug spec 0.13 compliant
|
|
||||||
.jtag_id(jtag_id),
|
|
||||||
.dmi_hard_reset(dmi_hard_reset),
|
|
||||||
.dmi_reset(dmireset)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
// dmi_jtag_to_core_sync instantiation
|
|
||||||
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
|
|
||||||
.wr_en(wr_en), // 1 bit Write enable
|
|
||||||
.rd_en(rd_en), // 1 bit Read enable
|
|
||||||
|
|
||||||
.rst_n(core_rst_n),
|
|
||||||
.clk(core_clk),
|
|
||||||
.reg_en(reg_en), // 1 bit Write interface bit
|
|
||||||
.reg_wr_en(reg_wr_en) // 1 bit Write enable
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
|
@ -1,14 +1,14 @@
|
||||||
module TEC_RV_ICG(
|
module gated_latch
|
||||||
(
|
(
|
||||||
input logic SE, EN, CK,
|
input wire SE, EN, CK,
|
||||||
output Q
|
output Q
|
||||||
);
|
);
|
||||||
logic en_ff;
|
reg en_ff;
|
||||||
logic enable;
|
wire enable;
|
||||||
assign enable = EN | SE;
|
assign enable = EN | SE;
|
||||||
always @(CK, enable) begin
|
always @(CK, enable) begin
|
||||||
if(!CK)
|
if(!CK)
|
||||||
en_ff = enable;
|
en_ff = enable;
|
||||||
end
|
end
|
||||||
assign Q = CK & en_ff;
|
assign Q = CK & en_ff;
|
||||||
endmodule
|
endmodule
|
|
@ -17,7 +17,7 @@
|
||||||
////////////////////////////////////////////////////
|
////////////////////////////////////////////////////
|
||||||
// ICACHE DATA & TAG MODULE WRAPPER //
|
// ICACHE DATA & TAG MODULE WRAPPER //
|
||||||
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
||||||
module el2_ifu_ic_mem
|
module ifu_ic_mem
|
||||||
#(
|
#(
|
||||||
parameter ICACHE_BEAT_BITS,
|
parameter ICACHE_BEAT_BITS,
|
||||||
parameter ICACHE_NUM_WAYS,
|
parameter ICACHE_NUM_WAYS,
|
||||||
|
@ -54,7 +54,7 @@ module el2_ifu_ic_mem
|
||||||
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
|
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
|
||||||
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||||
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||||
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
|
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
|
||||||
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
||||||
|
|
||||||
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
||||||
|
@ -67,7 +67,7 @@ module el2_ifu_ic_mem
|
||||||
) ;
|
) ;
|
||||||
|
|
||||||
|
|
||||||
EL2_IC_TAG #(
|
IC_TAG #(
|
||||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
||||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
||||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
||||||
|
@ -90,7 +90,7 @@ module el2_ifu_ic_mem
|
||||||
.ic_rw_addr (ic_rw_addr[31:3])
|
.ic_rw_addr (ic_rw_addr[31:3])
|
||||||
) ;
|
) ;
|
||||||
|
|
||||||
EL2_IC_DATA #(
|
IC_DATA #(
|
||||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
||||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
||||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
||||||
|
@ -119,7 +119,7 @@ module el2_ifu_ic_mem
|
||||||
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
||||||
////// ICACHE DATA MODULE ////////////////////
|
////// ICACHE DATA MODULE ////////////////////
|
||||||
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
||||||
module EL2_IC_DATA
|
module IC_DATA
|
||||||
#(
|
#(
|
||||||
parameter ICACHE_BEAT_BITS,
|
parameter ICACHE_BEAT_BITS,
|
||||||
parameter ICACHE_NUM_WAYS,
|
parameter ICACHE_NUM_WAYS,
|
||||||
|
@ -990,7 +990,7 @@ endmodule // EL2_IC_DATA
|
||||||
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
||||||
////// ICACHE TAG MODULE ////////////////////
|
////// ICACHE TAG MODULE ////////////////////
|
||||||
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
||||||
module EL2_IC_TAG
|
module IC_TAG
|
||||||
#(
|
#(
|
||||||
parameter ICACHE_BEAT_BITS,
|
parameter ICACHE_BEAT_BITS,
|
||||||
parameter ICACHE_NUM_WAYS,
|
parameter ICACHE_NUM_WAYS,
|
||||||
|
@ -1025,7 +1025,7 @@ module EL2_IC_TAG
|
||||||
input logic ic_debug_tag_array, // Debug tag array
|
input logic ic_debug_tag_array, // Debug tag array
|
||||||
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
||||||
|
|
||||||
output logic [25:0] ictag_debug_rd_data,
|
output logic [25:0] ic_tag_debug_rd_data,
|
||||||
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
||||||
|
|
||||||
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
|
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
|
||||||
|
@ -1853,9 +1853,9 @@ end // block: OTHERS
|
||||||
|
|
||||||
|
|
||||||
always_comb begin : tag_rd_out
|
always_comb begin : tag_rd_out
|
||||||
ictag_debug_rd_data[25:0] = '0;
|
ic_tag_debug_rd_data[25:0] = '0;
|
||||||
for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out
|
for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out
|
||||||
ictag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])};
|
ic_tag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
@ -19,7 +19,7 @@
|
||||||
// Icache closely coupled memory --- ICCM
|
// Icache closely coupled memory --- ICCM
|
||||||
//********************************************************************************
|
//********************************************************************************
|
||||||
|
|
||||||
module el2_ifu_iccm_mem
|
module ifu_iccm_mem
|
||||||
#(
|
#(
|
||||||
parameter ICCM_BITS,
|
parameter ICCM_BITS,
|
||||||
parameter ICCM_BANK_INDEX_LO,
|
parameter ICCM_BANK_INDEX_LO,
|
|
@ -1,5 +1,5 @@
|
||||||
|
|
||||||
module el2_mem #(
|
module mem #(
|
||||||
parameter ICACHE_BEAT_BITS,
|
parameter ICACHE_BEAT_BITS,
|
||||||
parameter ICCM_BITS,
|
parameter ICCM_BITS,
|
||||||
parameter ICACHE_NUM_WAYS,
|
parameter ICACHE_NUM_WAYS,
|
||||||
|
@ -87,7 +87,7 @@ module el2_mem #(
|
||||||
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
||||||
|
|
||||||
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||||
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
|
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
|
||||||
|
|
||||||
|
|
||||||
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
||||||
|
@ -102,7 +102,7 @@ module el2_mem #(
|
||||||
|
|
||||||
// DCCM Instantiation
|
// DCCM Instantiation
|
||||||
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
||||||
el2_lsu_dccm_mem #(
|
lsu_dccm_mem #(
|
||||||
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
|
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
|
||||||
.DCCM_BITS(DCCM_BITS),
|
.DCCM_BITS(DCCM_BITS),
|
||||||
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
|
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
|
||||||
|
@ -118,7 +118,7 @@ module el2_mem #(
|
||||||
end
|
end
|
||||||
|
|
||||||
if ( ICACHE_ENABLE ) begin: icache
|
if ( ICACHE_ENABLE ) begin: icache
|
||||||
el2_ifu_ic_mem #(
|
ifu_ic_mem #(
|
||||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
||||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
||||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
||||||
|
@ -142,13 +142,13 @@ else begin
|
||||||
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
|
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
|
||||||
assign ic_tag_perr = '0 ;
|
assign ic_tag_perr = '0 ;
|
||||||
assign ic_rd_data = '0 ;
|
assign ic_rd_data = '0 ;
|
||||||
assign ictag_debug_rd_data = '0 ;
|
assign ic_stag_debug_rd_data = '0 ;
|
||||||
end // else: !if( ICACHE_ENABLE )
|
end // else: !if( ICACHE_ENABLE )
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
if (ICCM_ENABLE) begin : iccm
|
if (ICCM_ENABLE) begin : iccm
|
||||||
el2_ifu_iccm_mem #(
|
ifu_iccm_mem #(
|
||||||
.ICCM_BITS(ICCM_BITS),
|
.ICCM_BITS(ICCM_BITS),
|
||||||
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
|
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
|
||||||
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
|
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
|
|
@ -1,223 +0,0 @@
|
||||||
// SPDX-License-Identifier: Apache-2.0
|
|
||||||
// Copyright 2019 Western Digital Corporation or it's affiliates.
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License
|
|
||||||
|
|
||||||
module rvjtag_tap #(
|
|
||||||
parameter AWIDTH = 7
|
|
||||||
)
|
|
||||||
(
|
|
||||||
input trst,
|
|
||||||
input tck,
|
|
||||||
input tms,
|
|
||||||
input tdi,
|
|
||||||
output reg tdo,
|
|
||||||
output tdoEnable,
|
|
||||||
|
|
||||||
output [31:0] wr_data,
|
|
||||||
output [AWIDTH-1:0] wr_addr,
|
|
||||||
output wr_en,
|
|
||||||
output rd_en,
|
|
||||||
|
|
||||||
input [31:0] rd_data,
|
|
||||||
input [1:0] rd_status,
|
|
||||||
|
|
||||||
output reg dmi_reset,
|
|
||||||
output reg dmi_hard_reset,
|
|
||||||
|
|
||||||
input [2:0] idle,
|
|
||||||
input [1:0] dmi_stat,
|
|
||||||
/*
|
|
||||||
-- revisionCode : 4'h0;
|
|
||||||
-- manufacturersIdCode : 11'h45;
|
|
||||||
-- deviceIdCode : 16'h0001;
|
|
||||||
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
|
|
||||||
*/
|
|
||||||
input [31:1] jtag_id,
|
|
||||||
input [3:0] version
|
|
||||||
);
|
|
||||||
|
|
||||||
localparam USER_DR_LENGTH = AWIDTH + 34;
|
|
||||||
|
|
||||||
|
|
||||||
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
// Tap controller
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
logic[3:0] state, nstate;
|
|
||||||
logic [4:0] ir;
|
|
||||||
wire jtag_reset;
|
|
||||||
wire shift_dr;
|
|
||||||
wire pause_dr;
|
|
||||||
wire update_dr;
|
|
||||||
wire capture_dr;
|
|
||||||
wire shift_ir;
|
|
||||||
wire pause_ir ;
|
|
||||||
wire update_ir ;
|
|
||||||
wire capture_ir;
|
|
||||||
wire[1:0] dr_en;
|
|
||||||
wire devid_sel;
|
|
||||||
wire [5:0] abits;
|
|
||||||
|
|
||||||
assign abits = AWIDTH[5:0];
|
|
||||||
|
|
||||||
|
|
||||||
localparam TEST_LOGIC_RESET_STATE = 0;
|
|
||||||
localparam RUN_TEST_IDLE_STATE = 1;
|
|
||||||
localparam SELECT_DR_SCAN_STATE = 2;
|
|
||||||
localparam CAPTURE_DR_STATE = 3;
|
|
||||||
localparam SHIFT_DR_STATE = 4;
|
|
||||||
localparam EXIT1_DR_STATE = 5;
|
|
||||||
localparam PAUSE_DR_STATE = 6;
|
|
||||||
localparam EXIT2_DR_STATE = 7;
|
|
||||||
localparam UPDATE_DR_STATE = 8;
|
|
||||||
localparam SELECT_IR_SCAN_STATE = 9;
|
|
||||||
localparam CAPTURE_IR_STATE = 10;
|
|
||||||
localparam SHIFT_IR_STATE = 11;
|
|
||||||
localparam EXIT1_IR_STATE = 12;
|
|
||||||
localparam PAUSE_IR_STATE = 13;
|
|
||||||
localparam EXIT2_IR_STATE = 14;
|
|
||||||
localparam UPDATE_IR_STATE = 15;
|
|
||||||
|
|
||||||
always_comb begin
|
|
||||||
nstate = state;
|
|
||||||
case(state)
|
|
||||||
TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
|
|
||||||
RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
|
||||||
SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
|
|
||||||
CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
|
|
||||||
SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
|
|
||||||
EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;
|
|
||||||
PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;
|
|
||||||
EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;
|
|
||||||
UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
|
||||||
SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;
|
|
||||||
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
|
||||||
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
|
||||||
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
|
|
||||||
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
|
|
||||||
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
|
|
||||||
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
|
||||||
default: nstate = TEST_LOGIC_RESET_STATE;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
always @ (posedge tck or negedge trst) begin
|
|
||||||
if(!trst) state <= TEST_LOGIC_RESET_STATE;
|
|
||||||
else state <= nstate;
|
|
||||||
end
|
|
||||||
|
|
||||||
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
|
|
||||||
assign shift_dr = state == SHIFT_DR_STATE;
|
|
||||||
assign pause_dr = state == PAUSE_DR_STATE;
|
|
||||||
assign update_dr = state == UPDATE_DR_STATE;
|
|
||||||
assign capture_dr = state == CAPTURE_DR_STATE;
|
|
||||||
assign shift_ir = state == SHIFT_IR_STATE;
|
|
||||||
assign pause_ir = state == PAUSE_IR_STATE;
|
|
||||||
assign update_ir = state == UPDATE_IR_STATE;
|
|
||||||
assign capture_ir = state == CAPTURE_IR_STATE;
|
|
||||||
|
|
||||||
assign tdoEnable = shift_dr | shift_ir;
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
// IR register
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
always @ (negedge tck or negedge trst) begin
|
|
||||||
if (!trst) ir <= 5'b1;
|
|
||||||
else begin
|
|
||||||
if (jtag_reset) ir <= 5'b1;
|
|
||||||
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
assign devid_sel = ir == 5'b00001;
|
|
||||||
assign dr_en[0] = ir == 5'b10000;
|
|
||||||
assign dr_en[1] = ir == 5'b10001;
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
// Shift register
|
|
||||||
///////////////////////////////////////////////////////
|
|
||||||
always @ (posedge tck or negedge trst) begin
|
|
||||||
if(!trst)begin
|
|
||||||
sr <= '0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
sr <= nsr;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// SR next value
|
|
||||||
always_comb begin
|
|
||||||
nsr = sr;
|
|
||||||
case(1)
|
|
||||||
shift_dr: begin
|
|
||||||
case(1)
|
|
||||||
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
|
|
||||||
|
|
||||||
dr_en[0],
|
|
||||||
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
|
|
||||||
default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
capture_dr: begin
|
|
||||||
case(1)
|
|
||||||
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
|
|
||||||
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
|
|
||||||
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
|
|
||||||
capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
// TDO retiming
|
|
||||||
always @ (negedge tck ) tdo <= sr[0];
|
|
||||||
|
|
||||||
// DMI CS register
|
|
||||||
always @ (posedge tck or negedge trst) begin
|
|
||||||
if(!trst) begin
|
|
||||||
dmi_hard_reset <= 1'b0;
|
|
||||||
dmi_reset <= 1'b0;
|
|
||||||
end
|
|
||||||
else if (update_dr & dr_en[0]) begin
|
|
||||||
dmi_hard_reset <= sr[17];
|
|
||||||
dmi_reset <= sr[16];
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
dmi_hard_reset <= 1'b0;
|
|
||||||
dmi_reset <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// DR register
|
|
||||||
always @ (posedge tck or negedge trst) begin
|
|
||||||
if(!trst)
|
|
||||||
dr <= '0;
|
|
||||||
else begin
|
|
||||||
if (update_dr & dr_en[1])
|
|
||||||
dr <= sr;
|
|
||||||
else
|
|
||||||
dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
assign {wr_addr, wr_data, wr_en, rd_en} = dr;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
|
@ -0,0 +1,5 @@
|
||||||
|
{
|
||||||
|
"files.watcherExclude": {
|
||||||
|
"**/target": true
|
||||||
|
}
|
||||||
|
}
|
|
@ -2,7 +2,15 @@ package dbg
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
import lib._
|
import lib._
|
||||||
|
import dec._
|
||||||
|
|
||||||
|
class dbg_dma extends Bundle {
|
||||||
|
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
|
||||||
|
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
object state_t {
|
object state_t {
|
||||||
val idle = 0.U(3.W)
|
val idle = 0.U(3.W)
|
||||||
|
@ -27,20 +35,13 @@ object sb_state_t {
|
||||||
val done = 9.U(4.W)
|
val done = 9.U(4.W)
|
||||||
}
|
}
|
||||||
|
|
||||||
class el2_dbg extends Module with el2_lib with RequireAsyncReset {
|
class dbg extends Module with lib with RequireAsyncReset {
|
||||||
val io = IO(new Bundle {
|
val io = IO(new Bundle {
|
||||||
val dbg_cmd_addr = Output(UInt(32.W))
|
|
||||||
val dbg_cmd_wrdata = Output(UInt(32.W))
|
|
||||||
val dbg_cmd_valid = Output(Bool())
|
|
||||||
val dbg_cmd_write = Output(Bool())
|
|
||||||
val dbg_cmd_type = Output(UInt(2.W))
|
|
||||||
val dbg_cmd_size = Output(UInt(2.W))
|
val dbg_cmd_size = Output(UInt(2.W))
|
||||||
val dbg_core_rst_l = Output(Bool())
|
val dbg_core_rst_l = Output(Bool())
|
||||||
val core_dbg_rddata = Input(UInt(32.W))
|
val core_dbg_rddata = Input(UInt(32.W))
|
||||||
val core_dbg_cmd_done = Input(Bool())
|
val core_dbg_cmd_done = Input(Bool())
|
||||||
val core_dbg_cmd_fail = Input(Bool())
|
val core_dbg_cmd_fail = Input(Bool())
|
||||||
val dbg_dma_bubble = Output(Bool())
|
|
||||||
val dma_dbg_ready = Input(Bool())
|
|
||||||
val dbg_halt_req = Output(Bool())
|
val dbg_halt_req = Output(Bool())
|
||||||
val dbg_resume_req = Output(Bool())
|
val dbg_resume_req = Output(Bool())
|
||||||
val dec_tlu_debug_mode = Input(Bool())
|
val dec_tlu_debug_mode = Input(Bool())
|
||||||
|
@ -52,42 +53,10 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
|
||||||
val dmi_reg_wr_en = Input(Bool())
|
val dmi_reg_wr_en = Input(Bool())
|
||||||
val dmi_reg_wdata = Input(UInt(32.W))
|
val dmi_reg_wdata = Input(UInt(32.W))
|
||||||
val dmi_reg_rdata = Output(UInt(32.W))
|
val dmi_reg_rdata = Output(UInt(32.W))
|
||||||
val sb_axi_awvalid = Output(Bool())
|
val sb_axi = new axi_channels(SB_BUS_TAG)
|
||||||
val sb_axi_awready = Input(Bool())
|
val dbg_dec = Flipped(new dec_dbg)
|
||||||
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
|
val dbg_dma = Flipped(new dec_dbg)
|
||||||
val sb_axi_awaddr = Output(UInt(32.W))
|
val dbg_dma_io = Flipped(new dbg_dma)
|
||||||
val sb_axi_awregion = Output(UInt(4.W))
|
|
||||||
val sb_axi_awlen = Output(UInt(8.W))
|
|
||||||
val sb_axi_awsize = Output(UInt(3.W))
|
|
||||||
val sb_axi_awburst = Output(UInt(2.W))
|
|
||||||
val sb_axi_awlock = Output(Bool())
|
|
||||||
val sb_axi_awcache = Output(UInt(4.W))
|
|
||||||
val sb_axi_awprot = Output(UInt(3.W))
|
|
||||||
val sb_axi_awqos = Output(UInt(4.W))
|
|
||||||
val sb_axi_wvalid = Output(Bool())
|
|
||||||
val sb_axi_wready = Input(Bool())
|
|
||||||
val sb_axi_wdata = Output(UInt(64.W))
|
|
||||||
val sb_axi_wstrb = Output(UInt(8.W))
|
|
||||||
val sb_axi_wlast = Output(Bool())
|
|
||||||
val sb_axi_bvalid = Input(Bool())
|
|
||||||
val sb_axi_bready = Output(Bool())
|
|
||||||
val sb_axi_bresp = Input(UInt(2.W))
|
|
||||||
val sb_axi_arvalid = Output(Bool())
|
|
||||||
val sb_axi_arready = Input(Bool())
|
|
||||||
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
|
|
||||||
val sb_axi_araddr = Output(UInt(32.W))
|
|
||||||
val sb_axi_arregion = Output(UInt(4.W))
|
|
||||||
val sb_axi_arlen = Output(UInt(8.W))
|
|
||||||
val sb_axi_arsize = Output(UInt(3.W))
|
|
||||||
val sb_axi_arburst = Output(UInt(2.W))
|
|
||||||
val sb_axi_arlock = Output(Bool())
|
|
||||||
val sb_axi_arcache = Output(UInt(4.W))
|
|
||||||
val sb_axi_arprot = Output(UInt(3.W))
|
|
||||||
val sb_axi_arqos = Output(UInt(4.W))
|
|
||||||
val sb_axi_rvalid = Input(Bool())
|
|
||||||
val sb_axi_rready = Output(Bool())
|
|
||||||
val sb_axi_rdata = Input(UInt(64.W))
|
|
||||||
val sb_axi_rresp = Input(UInt(2.W))
|
|
||||||
val dbg_bus_clk_en = Input(Bool())
|
val dbg_bus_clk_en = Input(Bool())
|
||||||
val dbg_rst_l = Input(Bool())
|
val dbg_rst_l = Input(Bool())
|
||||||
val clk_override = Input(Bool())
|
val clk_override = Input(Bool())
|
||||||
|
@ -315,7 +284,7 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
|
||||||
}
|
}
|
||||||
is(state_t.cmd_start) {
|
is(state_t.cmd_start) {
|
||||||
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, Mux(abstractcs_reg(10, 8).orR, state_t.cmd_done, state_t.cmd_wait))
|
dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, Mux(abstractcs_reg(10, 8).orR, state_t.cmd_done, state_t.cmd_wait))
|
||||||
dbg_state_en := io.dbg_cmd_valid | abstractcs_reg(10, 8).orR | dmcontrol_reg(1)
|
dbg_state_en := io.dbg_dec.dbg_ib.dbg_cmd_valid | abstractcs_reg(10, 8).orR | dmcontrol_reg(1)
|
||||||
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
|
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool()
|
||||||
}
|
}
|
||||||
is(state_t.cmd_wait) {
|
is(state_t.cmd_wait) {
|
||||||
|
@ -352,13 +321,13 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
|
||||||
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
|
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
|
||||||
} // dmi_rddata_reg
|
} // dmi_rddata_reg
|
||||||
|
|
||||||
io.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0)))
|
io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0)))
|
||||||
io.dbg_cmd_wrdata := data0_reg(31, 0)
|
io.dbg_dec.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0)
|
||||||
io.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dma_dbg_ready).asBool()
|
io.dbg_dec.dbg_ib.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dbg_dma_io.dma_dbg_ready).asBool()
|
||||||
io.dbg_cmd_write := command_reg(16).asBool()
|
io.dbg_dec.dbg_ib.dbg_cmd_write := command_reg(16).asBool()
|
||||||
io.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U)))
|
io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U)))
|
||||||
io.dbg_cmd_size := command_reg(21, 20)
|
io.dbg_cmd_size := command_reg(21, 20)
|
||||||
io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool()
|
io.dbg_dma_io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool()
|
||||||
|
|
||||||
val sb_nxtstate = WireInit(sb_state_t.sbidle)
|
val sb_nxtstate = WireInit(sb_state_t.sbidle)
|
||||||
sb_nxtstate := sb_state_t.sbidle
|
sb_nxtstate := sb_state_t.sbidle
|
||||||
|
@ -429,52 +398,55 @@ class el2_dbg extends Module with el2_lib with RequireAsyncReset {
|
||||||
RegEnable(sb_nxtstate, 0.U, sb_state_en)
|
RegEnable(sb_nxtstate, 0.U, sb_state_en)
|
||||||
} // sb_state_reg
|
} // sb_state_reg
|
||||||
|
|
||||||
sb_bus_cmd_read := io.sb_axi_arvalid & io.sb_axi_arready
|
sb_bus_cmd_read := io.sb_axi.ar.valid & io.sb_axi.ar.ready
|
||||||
sb_bus_cmd_write_addr := io.sb_axi_awvalid & io.sb_axi_awready
|
sb_bus_cmd_write_addr := io.sb_axi.aw.valid & io.sb_axi.aw.ready
|
||||||
sb_bus_cmd_write_data := io.sb_axi_wvalid & io.sb_axi_wready
|
sb_bus_cmd_write_data := io.sb_axi.w.valid & io.sb_axi.w.ready
|
||||||
sb_bus_rsp_read := io.sb_axi_rvalid & io.sb_axi_rready
|
sb_bus_rsp_read := io.sb_axi.r.valid & io.sb_axi.r.ready
|
||||||
sb_bus_rsp_write := io.sb_axi_bvalid & io.sb_axi_bready
|
sb_bus_rsp_write := io.sb_axi.b.valid & io.sb_axi.b.ready
|
||||||
sb_bus_rsp_error := sb_bus_rsp_read & io.sb_axi_rresp(1, 0).orR | sb_bus_rsp_write & io.sb_axi_bresp(1, 0).orR
|
sb_bus_rsp_error := sb_bus_rsp_read & io.sb_axi.r.bits.resp(1, 0).orR | sb_bus_rsp_write & io.sb_axi.b.bits.resp(1, 0).orR
|
||||||
io.sb_axi_awvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr)).asBool()
|
io.sb_axi.aw.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr)).asBool()
|
||||||
io.sb_axi_awaddr := sbaddress0_reg
|
io.sb_axi.aw.bits.addr := sbaddress0_reg
|
||||||
io.sb_axi_awid := 0.U
|
io.sb_axi.aw.bits.id := 0.U
|
||||||
io.sb_axi_awsize := sbcs_reg(19, 17)
|
io.sb_axi.aw.bits.size := sbcs_reg(19, 17)
|
||||||
io.sb_axi_awprot := 0.U
|
io.sb_axi.aw.bits.prot := 0.U
|
||||||
io.sb_axi_awcache := "b1111".U
|
io.sb_axi.aw.bits.cache := "b1111".U
|
||||||
io.sb_axi_awregion := sbaddress0_reg(31, 28)
|
io.sb_axi.aw.bits.region := sbaddress0_reg(31, 28)
|
||||||
io.sb_axi_awlen := 0.U
|
io.sb_axi.aw.bits.len := 0.U
|
||||||
io.sb_axi_awburst := "b01".U
|
io.sb_axi.aw.bits.burst := "b01".U
|
||||||
io.sb_axi_awqos := 0.U
|
io.sb_axi.aw.bits.qos := 0.U
|
||||||
io.sb_axi_awlock := false.B
|
io.sb_axi.aw.bits.lock := false.B
|
||||||
io.sb_axi_wvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool()
|
io.sb_axi.w.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool()
|
||||||
io.sb_axi_wdata := Fill(64, (sbcs_reg(19, 17) === 0.U)) & Fill(8, (sbdata0_reg(7, 0))) | Fill(64, (sbcs_reg(19, 17) === "h1".U)) & Fill(4, sbdata0_reg(15, 0)) |
|
io.sb_axi.w.bits.data := Fill(64, (sbcs_reg(19, 17) === 0.U)) & Fill(8, (sbdata0_reg(7, 0))) | Fill(64, (sbcs_reg(19, 17) === "h1".U)) & Fill(4, sbdata0_reg(15, 0)) |
|
||||||
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & Fill(2, (sbdata0_reg(31, 0))) | Fill(64, (sbcs_reg(19, 17) === "h3".U)) & Cat(sbdata1_reg(31, 0), sbdata0_reg(31, 0))
|
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & Fill(2, (sbdata0_reg(31, 0))) | Fill(64, (sbcs_reg(19, 17) === "h3".U)) & Cat(sbdata1_reg(31, 0), sbdata0_reg(31, 0))
|
||||||
|
|
||||||
io.sb_axi_wstrb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) |
|
io.sb_axi.w.bits.strb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) |
|
||||||
Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) |
|
Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) |
|
||||||
Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) |
|
Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) |
|
||||||
Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U
|
Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U
|
||||||
|
|
||||||
io.sb_axi_wlast := true.B
|
io.sb_axi.w.bits.last := true.B
|
||||||
io.sb_axi_arvalid := (sb_state === sb_state_t.cmd_rd).asBool()
|
io.sb_axi.ar.valid := (sb_state === sb_state_t.cmd_rd).asBool()
|
||||||
io.sb_axi_araddr := sbaddress0_reg
|
io.sb_axi.ar.bits.addr := sbaddress0_reg
|
||||||
io.sb_axi_arid := 0.U
|
io.sb_axi.ar.bits.id := 0.U
|
||||||
io.sb_axi_arsize := sbcs_reg(19, 17)
|
io.sb_axi.ar.bits.size := sbcs_reg(19, 17)
|
||||||
io.sb_axi_arprot := 0.U
|
io.sb_axi.ar.bits.prot := 0.U
|
||||||
io.sb_axi_arcache := 0.U
|
io.sb_axi.ar.bits.cache := 0.U
|
||||||
io.sb_axi_arregion := sbaddress0_reg(31, 28)
|
io.sb_axi.ar.bits.region := sbaddress0_reg(31, 28)
|
||||||
io.sb_axi_arlen := 0.U
|
io.sb_axi.ar.bits.len := 0.U
|
||||||
io.sb_axi_arburst := "b01".U
|
io.sb_axi.ar.bits.burst := "b01".U
|
||||||
io.sb_axi_arqos := 0.U
|
io.sb_axi.ar.bits.qos := 0.U
|
||||||
io.sb_axi_arlock := false.B
|
io.sb_axi.ar.bits.lock := false.B
|
||||||
io.sb_axi_bready := true.B
|
io.sb_axi.b.ready := true.B
|
||||||
io.sb_axi_rready := true.B
|
io.sb_axi.r.ready := true.B
|
||||||
sb_bus_rdata := Fill(64, (sbcs_reg(19, 17) === "h0".U)) & ((io.sb_axi_rdata(63, 0) >> 8.U * sbaddress0_reg(2, 0)) & "hff".U(64.W)) |
|
sb_bus_rdata := Fill(64, (sbcs_reg(19, 17) === "h0".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 8.U * sbaddress0_reg(2, 0)) & "hff".U(64.W)) |
|
||||||
Fill(64, (sbcs_reg(19, 17) === "h1".U)) & ((io.sb_axi_rdata(63, 0) >> 16.U * sbaddress0_reg(2, 1)) & "hffff".U(64.W)) |
|
Fill(64, (sbcs_reg(19, 17) === "h1".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 16.U * sbaddress0_reg(2, 1)) & "hffff".U(64.W)) |
|
||||||
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & ((io.sb_axi_rdata(63, 0) >> 32.U * sbaddress0_reg(2)) & "hffff_ffff".U(64.W)) |
|
Fill(64, (sbcs_reg(19, 17) === "h2".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 32.U * sbaddress0_reg(2)) & "hffff_ffff".U(64.W)) |
|
||||||
Fill(64, (sbcs_reg(19, 17) === "h3".U)) & io.sb_axi_rdata(63, 0)
|
Fill(64, (sbcs_reg(19, 17) === "h3".U)) & io.sb_axi.r.bits.data(63, 0)
|
||||||
}
|
|
||||||
|
|
||||||
object debug extends App {
|
|
||||||
chisel3.Driver.emitVerilog(new el2_dbg)
|
io.dbg_dma.dbg_ib.dbg_cmd_addr := io.dbg_dec.dbg_ib.dbg_cmd_addr
|
||||||
|
io.dbg_dma.dbg_dctl.dbg_cmd_wrdata := io.dbg_dec.dbg_dctl.dbg_cmd_wrdata
|
||||||
|
io.dbg_dma.dbg_ib.dbg_cmd_valid := io.dbg_dec.dbg_ib.dbg_cmd_valid
|
||||||
|
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
|
||||||
|
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
|
||||||
}
|
}
|
|
@ -0,0 +1,318 @@
|
||||||
|
package dec
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
import lsu._
|
||||||
|
|
||||||
|
class dec_IO extends Bundle with lib {
|
||||||
|
val free_clk = Input(Clock())
|
||||||
|
val active_clk = Input(Clock())
|
||||||
|
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
|
||||||
|
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
|
||||||
|
val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
|
||||||
|
|
||||||
|
val nmi_int = Input(Bool()) // NMI pin
|
||||||
|
val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
|
||||||
|
|
||||||
|
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
|
||||||
|
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
|
||||||
|
|
||||||
|
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
|
||||||
|
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
|
||||||
|
val o_cpu_run_ack = Output(Bool()) // Run request ack
|
||||||
|
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
|
||||||
|
|
||||||
|
val core_id = Input(UInt(28.W)) // [31:4] CORE ID
|
||||||
|
|
||||||
|
val mpc_debug_halt_req = Input(Bool()) // Async halt request
|
||||||
|
val mpc_debug_run_req = Input(Bool()) // Async run request
|
||||||
|
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
|
||||||
|
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
|
||||||
|
val mpc_debug_run_ack = Output(Bool()) // Run ack
|
||||||
|
val debug_brkpt_status = Output(Bool()) // debug breakpoint
|
||||||
|
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
|
||||||
|
val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read
|
||||||
|
val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write
|
||||||
|
val dma_pmu_any_read = Input(Bool()) // DMA read
|
||||||
|
val dma_pmu_any_write = Input(Bool()) // DMA write
|
||||||
|
|
||||||
|
val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
|
||||||
|
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
|
||||||
|
|
||||||
|
val lsu_trigger_match_m = Input(UInt(4.W))
|
||||||
|
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||||
|
val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
|
||||||
|
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
||||||
|
val exu_div_result = Input(UInt(32.W)) // final div result
|
||||||
|
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
|
||||||
|
val lsu_result_m = Input(UInt(32.W)) // load result
|
||||||
|
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
|
||||||
|
|
||||||
|
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
|
||||||
|
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
|
||||||
|
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event
|
||||||
|
val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event
|
||||||
|
|
||||||
|
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
|
||||||
|
|
||||||
|
val exu_flush_final = Input(Bool()) // slot0 flush
|
||||||
|
val mexintpend = Input(Bool()) // External interrupt pending
|
||||||
|
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
|
||||||
|
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
|
||||||
|
|
||||||
|
val pic_claimid = Input(UInt(8.W)) // PIC claimid
|
||||||
|
val pic_pl = Input(UInt(4.W)) // PIC priv level
|
||||||
|
val mhwakeup = Input(Bool()) // High priority wakeup
|
||||||
|
|
||||||
|
val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level
|
||||||
|
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
|
||||||
|
|
||||||
|
// Debug start
|
||||||
|
val dbg_halt_req = Input(Bool()) // DM requests a halt
|
||||||
|
val dbg_resume_req = Input(Bool()) // DM requests a resume
|
||||||
|
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
|
||||||
|
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
|
||||||
|
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
|
||||||
|
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
|
||||||
|
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
|
||||||
|
|
||||||
|
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
|
||||||
|
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
|
||||||
|
|
||||||
|
val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
|
||||||
|
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
|
||||||
|
val lsu_p = Valid(new lsu_pkt_t) // lsu packet
|
||||||
|
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
||||||
|
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||||
|
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||||
|
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||||
|
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
||||||
|
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
||||||
|
val dec_lsu_valid_raw_d = Output(Bool())
|
||||||
|
val rv_trace_pkt = Output(new trace_pkt_t) // trace packet
|
||||||
|
val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16]
|
||||||
|
|
||||||
|
// clock gating overrides from mcgc
|
||||||
|
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
|
||||||
|
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
|
||||||
|
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
|
||||||
|
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
|
||||||
|
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
|
||||||
|
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
|
||||||
|
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
|
||||||
|
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
val ifu_dec = Flipped(new ifu_dec)
|
||||||
|
val dec_exu = Flipped(new dec_exu)
|
||||||
|
val lsu_dec = Flipped (new lsu_dec)
|
||||||
|
val lsu_tlu = Flipped (new lsu_tlu)
|
||||||
|
val dec_dbg = new dec_dbg
|
||||||
|
}
|
||||||
|
class dec extends Module with param with RequireAsyncReset{
|
||||||
|
val io = IO(new dec_IO)
|
||||||
|
|
||||||
|
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
|
||||||
|
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
|
||||||
|
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||||
|
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||||
|
|
||||||
|
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
|
||||||
|
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
|
||||||
|
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
|
||||||
|
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------//
|
||||||
|
val instbuff = Module(new dec_ib_ctl)
|
||||||
|
val decode = Module(new dec_decode_ctl)
|
||||||
|
val gpr = Module(new dec_gpr_ctl)
|
||||||
|
val tlu = Module(new dec_tlu_ctl)
|
||||||
|
val dec_trigger = Module(new dec_trigger)
|
||||||
|
|
||||||
|
//connections for dec_Ib
|
||||||
|
//inputs
|
||||||
|
instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
|
||||||
|
instbuff.io.ib_exu <> io.dec_exu.ib_exu
|
||||||
|
instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
|
||||||
|
dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
|
||||||
|
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||||
|
|
||||||
|
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
||||||
|
dontTouch(dec_i0_trigger_match_d)
|
||||||
|
decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
|
||||||
|
decode.io.decode_exu<> io.dec_exu.decode_exu
|
||||||
|
decode.io.dec_alu<> io.dec_exu.dec_alu
|
||||||
|
decode.io.dec_div<> io.dec_exu.dec_div
|
||||||
|
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||||
|
decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
|
||||||
|
decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
|
||||||
|
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
|
||||||
|
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
||||||
|
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
|
||||||
|
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
|
||||||
|
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
|
||||||
|
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
||||||
|
decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
|
||||||
|
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
|
||||||
|
decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
|
||||||
|
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
|
||||||
|
decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
|
||||||
|
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
|
||||||
|
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
|
||||||
|
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
|
||||||
|
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
|
||||||
|
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
|
||||||
|
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
|
||||||
|
decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
|
||||||
|
decode.io.lsu_idle_any := io.lsu_idle_any
|
||||||
|
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
|
||||||
|
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||||
|
decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
||||||
|
decode.io.exu_div_wren := io.exu_div_wren
|
||||||
|
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||||
|
decode.io.dec_tlu_flush_lower_wb := tlu.io.tlu_bp.dec_tlu_flush_lower_wb
|
||||||
|
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||||
|
decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
|
||||||
|
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
||||||
|
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
||||||
|
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
||||||
|
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
|
||||||
|
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||||
|
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||||
|
decode.io.lsu_result_m := io.lsu_result_m
|
||||||
|
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
|
||||||
|
decode.io.exu_flush_final := io.exu_flush_final
|
||||||
|
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
|
||||||
|
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
||||||
|
decode.io.free_clk := io.free_clk
|
||||||
|
decode.io.active_clk := io.active_clk
|
||||||
|
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
||||||
|
decode.io.scan_mode := io.scan_mode
|
||||||
|
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
|
||||||
|
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
|
||||||
|
io.lsu_p := decode.io.lsu_p
|
||||||
|
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
|
||||||
|
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
|
||||||
|
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
|
||||||
|
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
||||||
|
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
||||||
|
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
||||||
|
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
||||||
|
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
||||||
|
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
|
||||||
|
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
|
||||||
|
gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data
|
||||||
|
gpr.io.wen2 := io.exu_div_wren
|
||||||
|
gpr.io.waddr2 := decode.io.div_waddr_wb
|
||||||
|
gpr.io.wd2 := io.exu_div_result
|
||||||
|
gpr.io.scan_mode := io.scan_mode
|
||||||
|
io.dec_exu.gpr_exu <> gpr.io.gpr_exu
|
||||||
|
tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
|
||||||
|
tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
|
||||||
|
tlu.io.tlu_bp <> io.ifu_dec.dec_bp
|
||||||
|
tlu.io.tlu_exu <> io.dec_exu.tlu_exu
|
||||||
|
tlu.io.active_clk := io.active_clk
|
||||||
|
tlu.io.free_clk := io.free_clk
|
||||||
|
tlu.io.scan_mode := io.scan_mode
|
||||||
|
tlu.io.rst_vec := io.rst_vec
|
||||||
|
tlu.io.nmi_int := io.nmi_int
|
||||||
|
tlu.io.nmi_vec := io.nmi_vec
|
||||||
|
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||||
|
tlu.io.i_cpu_run_req := io.i_cpu_run_req
|
||||||
|
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
|
||||||
|
tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
|
||||||
|
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
|
||||||
|
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
|
||||||
|
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
|
||||||
|
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
||||||
|
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||||
|
tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
||||||
|
tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any
|
||||||
|
io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
|
||||||
|
io.lsu_tlu <> tlu.io.lsu_tlu
|
||||||
|
tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read
|
||||||
|
tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write
|
||||||
|
tlu.io.dma_pmu_any_read := io.dma_pmu_any_read
|
||||||
|
tlu.io.dma_pmu_any_write := io.dma_pmu_any_write
|
||||||
|
tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
||||||
|
tlu.io.lsu_fir_error := io.lsu_fir_error
|
||||||
|
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
||||||
|
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
||||||
|
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
||||||
|
tlu.io.dec_pause_state := decode.io.dec_pause_state
|
||||||
|
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
||||||
|
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
||||||
|
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
||||||
|
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
||||||
|
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
||||||
|
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
||||||
|
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
||||||
|
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
||||||
|
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
||||||
|
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
||||||
|
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
||||||
|
tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
|
||||||
|
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
|
||||||
|
tlu.io.dbg_halt_req := io.dbg_halt_req
|
||||||
|
tlu.io.dbg_resume_req := io.dbg_resume_req
|
||||||
|
tlu.io.lsu_idle_any := io.lsu_idle_any
|
||||||
|
tlu.io.dec_div_active := decode.io.dec_div_active
|
||||||
|
tlu.io.pic_claimid := io.pic_claimid
|
||||||
|
tlu.io.pic_pl := io.pic_pl
|
||||||
|
tlu.io.mhwakeup := io.mhwakeup
|
||||||
|
tlu.io.mexintpend := io.mexintpend
|
||||||
|
tlu.io.timer_int := io.timer_int
|
||||||
|
tlu.io.soft_int := io.soft_int
|
||||||
|
tlu.io.core_id := io.core_id
|
||||||
|
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||||
|
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||||
|
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||||
|
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
|
||||||
|
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
|
||||||
|
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
|
||||||
|
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
|
||||||
|
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
|
||||||
|
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
|
||||||
|
io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||||
|
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
||||||
|
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
||||||
|
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
||||||
|
io.o_debug_mode_status := tlu.io.o_debug_mode_status
|
||||||
|
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
|
||||||
|
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
|
||||||
|
io.debug_brkpt_status := tlu.io.debug_brkpt_status
|
||||||
|
io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
|
||||||
|
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
|
||||||
|
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||||
|
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
|
||||||
|
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
|
||||||
|
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
|
||||||
|
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
|
||||||
|
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||||
|
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
|
||||||
|
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
|
||||||
|
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
|
||||||
|
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
|
||||||
|
io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty
|
||||||
|
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
|
||||||
|
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
|
||||||
|
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
|
||||||
|
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
|
||||||
|
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
|
||||||
|
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
|
||||||
|
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------//
|
||||||
|
|
||||||
|
io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1
|
||||||
|
io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U)
|
||||||
|
io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1)
|
||||||
|
io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1)
|
||||||
|
io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
|
||||||
|
io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U)
|
||||||
|
io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
|
||||||
|
|
||||||
|
|
||||||
|
// debug command read data
|
||||||
|
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||||
|
}
|
|
@ -0,0 +1,121 @@
|
||||||
|
package dec
|
||||||
|
import chisel3._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
class dec_dec_ctl extends Module with lib{
|
||||||
|
val io = IO (new Bundle{
|
||||||
|
val ins = Input(UInt(32.W))
|
||||||
|
val out = Output(new dec_pkt_t)
|
||||||
|
})
|
||||||
|
|
||||||
|
def pattern(y : List[Int]) : UInt = {
|
||||||
|
val pat : Array[UInt] = new Array[UInt](y.size)
|
||||||
|
for (i <- 0 until y.size){
|
||||||
|
pat(i) = if(y(i)>=0) io.ins(y(i)) else !io.ins(y(i).abs)
|
||||||
|
}
|
||||||
|
pat.reduce(_&_)
|
||||||
|
}
|
||||||
|
|
||||||
|
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
|
||||||
|
io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) |
|
||||||
|
pattern(List(19,13,-2)) | pattern(List(-13,10,-2)) |
|
||||||
|
pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) |
|
||||||
|
pattern(List(17,13,-2)) | pattern(List(-13,8,-2)) |
|
||||||
|
pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) |
|
||||||
|
pattern(List(15,13,-2)) |pattern(List(-4,-3)) | pattern(List(-6,-2))
|
||||||
|
io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2))
|
||||||
|
io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) |
|
||||||
|
pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2))
|
||||||
|
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
|
||||||
|
io.out.shimm5 := pattern(List(-13,12,-5,4,-2))
|
||||||
|
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
|
||||||
|
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
|
||||||
|
io.out.load := pattern(List(-5,-4,-2))
|
||||||
|
io.out.store := pattern(List(-6,5,-4))
|
||||||
|
io.out.lsu := pattern(List(-6,-4,-2))
|
||||||
|
io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) |
|
||||||
|
pattern(List(-30,-25,-14,-13,-12,-6,4,-2))
|
||||||
|
io.out.sub := pattern(List(30,-12,-6,5,4,-2)) | pattern(List(-25,-14,13,-6,4,-2)) |
|
||||||
|
pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2))
|
||||||
|
io.out.land := pattern(List(14,13,12,-5,-2)) | pattern(List(-25,14,13,12,-6,-2))
|
||||||
|
io.out.lor := pattern(List(-6,3)) | pattern(List(-25,14,13,-12,-6,-2)) |
|
||||||
|
pattern(List(5,4,2)) | pattern(List(-13,-12,6,4)) |
|
||||||
|
pattern(List(14,13,-12,-5,-2))
|
||||||
|
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2))
|
||||||
|
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2))
|
||||||
|
io.out.sra := pattern(List(30,-13,12,-6,4,-2))
|
||||||
|
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2))
|
||||||
|
io.out.slt := pattern(List(-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2))
|
||||||
|
io.out.unsign := pattern(List(-14,13,12,-5,-2)) | pattern(List(13,6,-4,-2)) |
|
||||||
|
pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) |
|
||||||
|
pattern(List(25,14,12,-6,5,-2))
|
||||||
|
io.out.condbr := pattern(List(6,-4,-2))
|
||||||
|
io.out.beq := pattern(List(-14,-12,6,-4,-2))
|
||||||
|
io.out.bne := pattern(List(-14,12,6,-4,-2))
|
||||||
|
io.out.bge := pattern(List(14,12,5,-4,-2))
|
||||||
|
io.out.blt := pattern(List(14,-12,5,-4,-2))
|
||||||
|
io.out.jal := pattern(List(6,2))
|
||||||
|
io.out.by := pattern(List(-13,-12,-6,-4,-2))
|
||||||
|
io.out.half := pattern(List(12,-6,-4,-2))
|
||||||
|
io.out.word := pattern(List(13,-6,-4))
|
||||||
|
io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) |
|
||||||
|
pattern(List(8,6,4)) | pattern(List(9,6,4)) | pattern(List(10,6,4)) |
|
||||||
|
pattern(List(11,6,4))
|
||||||
|
io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) |
|
||||||
|
pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) |
|
||||||
|
pattern(List(19,13,12,6,4))
|
||||||
|
io.out.csr_write := pattern(List(-13,12,6,4))
|
||||||
|
io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) |
|
||||||
|
pattern(List(16,14,6,4)) | pattern(List(17,14,6,4)) |
|
||||||
|
pattern(List(18,14,6,4)) | pattern(List(19,14,6,4))
|
||||||
|
io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) |
|
||||||
|
pattern(List(17,-12,6,4)) | pattern(List(18,-12,6,4)) |
|
||||||
|
pattern(List(19,-12,6,4))
|
||||||
|
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4))
|
||||||
|
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4))
|
||||||
|
io.out.mret := pattern(List(29,-13,-12,6,4))
|
||||||
|
io.out.mul := pattern(List(25,-14,-6,5,4,-2))
|
||||||
|
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)) |
|
||||||
|
pattern(List(25,-14,-13,12,-6,4,-2))
|
||||||
|
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2))
|
||||||
|
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2))
|
||||||
|
io.out.div := pattern(List(25,14,-6,5,-2))
|
||||||
|
io.out.rem := pattern(List(25,14,13,-6,5,-2))
|
||||||
|
io.out.fence := pattern(List(-5,3))
|
||||||
|
io.out.fence_i := pattern(List(12,-5,3))
|
||||||
|
io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(4,2)) |
|
||||||
|
pattern(List(-25,-6,4)) | pattern(List(-5,4))
|
||||||
|
io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) |
|
||||||
|
pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) |
|
||||||
|
pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) |
|
||||||
|
pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) |
|
||||||
|
pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) |
|
||||||
|
pattern(List(19,13,6,4))
|
||||||
|
io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) |
|
||||||
|
pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) |
|
||||||
|
pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) |
|
||||||
|
pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) |
|
||||||
|
pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
|
||||||
|
pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
|
||||||
|
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)) |
|
||||||
|
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)) |
|
||||||
|
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) |
|
||||||
|
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) |
|
||||||
|
pattern(List(14,6,5,-4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-12,-6,-5,4,-3,1,0)) |
|
||||||
|
pattern(List(-14,-13,5,-4,-3,-2,1,0)) |
|
||||||
|
pattern(List(12,6,5,4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
|
||||||
|
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
|
||||||
|
pattern(List(13,6,5,4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-13,-6,-5,-4,-3,-2,1,0)) |
|
||||||
|
pattern(List(6,5,-4,3,2,1,0)) |
|
||||||
|
pattern(List(13,-6,-5,4,-3,1,0)) |
|
||||||
|
pattern(List(-14,-12,-6,-4,-3,-2,1,0)) |
|
||||||
|
pattern(List(-6,4,-3,2,1,0))
|
||||||
|
}
|
|
@ -1,27 +1,23 @@
|
||||||
package dec
|
package dec
|
||||||
import chisel3._
|
import chisel3._
|
||||||
|
|
||||||
import scala.collection._
|
import scala.collection._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
import include._
|
import include._
|
||||||
import lib._
|
import lib._
|
||||||
|
import exu._
|
||||||
|
import lsu._
|
||||||
|
|
||||||
class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
class dec_decode_ctl extends Module with lib with RequireAsyncReset{
|
||||||
val io = IO(new Bundle{
|
val io = IO(new Bundle{
|
||||||
|
val decode_exu = Flipped(new decode_exu)
|
||||||
|
val dec_alu = Flipped(new dec_alu)
|
||||||
|
val dec_div = Flipped(new dec_div)
|
||||||
|
val dctl_busbuff = Flipped(new dctl_busbuff())
|
||||||
val dec_tlu_flush_extint = Input(Bool())
|
val dec_tlu_flush_extint = Input(Bool())
|
||||||
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
|
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
|
||||||
val dec_extint_stall = Output(Bool())
|
|
||||||
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
|
|
||||||
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
|
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
|
||||||
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
|
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
|
||||||
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
|
|
||||||
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
|
|
||||||
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
|
|
||||||
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
|
|
||||||
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
|
|
||||||
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
|
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
|
||||||
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
|
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
|
||||||
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
|
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
|
||||||
|
@ -30,12 +26,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val dec_tlu_debug_stall = Input(Bool()) // debug stall decode
|
val dec_tlu_debug_stall = Input(Bool()) // debug stall decode
|
||||||
val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction
|
val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction
|
||||||
val dec_debug_fence_d = Input(Bool()) // debug fence instruction
|
val dec_debug_fence_d = Input(Bool()) // debug fence instruction
|
||||||
val dbg_cmd_wrdata = Input(UInt(2.W)) // disambiguate fence, fence_i
|
|
||||||
val dec_i0_icaf_d = Input(Bool()) // icache access fault
|
val dec_i0_icaf_d = Input(Bool()) // icache access fault
|
||||||
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
|
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
|
||||||
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
|
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
|
||||||
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
|
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
|
||||||
val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
|
val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet
|
||||||
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||||
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||||
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||||
|
@ -55,43 +50,23 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
|
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
|
||||||
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
|
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
|
||||||
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
|
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
|
||||||
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr
|
|
||||||
val lsu_result_m = Input(UInt(32.W)) // load result
|
val lsu_result_m = Input(UInt(32.W)) // load result
|
||||||
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
|
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
|
||||||
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
|
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
|
||||||
val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1
|
|
||||||
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
|
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
|
||||||
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
|
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
|
||||||
val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's
|
|
||||||
val free_clk = Input(Clock())
|
val free_clk = Input(Clock())
|
||||||
val active_clk = Input(Clock()) // clk except for halt / pause
|
val active_clk = Input(Clock()) // clk except for halt / pause
|
||||||
val clk_override = Input(Bool()) // test stuff
|
val clk_override = Input(Bool()) // test stuff
|
||||||
|
|
||||||
val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode
|
|
||||||
val dec_i0_rs2_en_d = Output(Bool())
|
|
||||||
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
|
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
|
||||||
val dec_i0_rs2_d = Output(UInt(5.W))
|
val dec_i0_rs2_d = Output(UInt(5.W))
|
||||||
val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode
|
|
||||||
val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate
|
|
||||||
val i0_ap = Output(new el2_alu_pkt_t) // alu packets
|
|
||||||
val dec_i0_decode_d = Output(Bool()) // i0 decode
|
|
||||||
val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu
|
|
||||||
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data
|
|
||||||
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data
|
|
||||||
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
|
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
|
||||||
val dec_i0_wen_r = Output(Bool()) // i0 write enable
|
val dec_i0_wen_r = Output(Bool()) // i0 write enable
|
||||||
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
|
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
|
||||||
val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches
|
val lsu_p = Valid(new lsu_pkt_t) // load/store packet
|
||||||
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable
|
|
||||||
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable
|
|
||||||
val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet
|
|
||||||
val mul_p = Output(new el2_mul_pkt_t) // multiply packet
|
|
||||||
val div_p = Output(new el2_div_pkt_t) // divide packet
|
|
||||||
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
|
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
|
||||||
val dec_div_cancel = Output(Bool()) // cancel the divide operation
|
|
||||||
val dec_lsu_valid_raw_d = Output(Bool())
|
val dec_lsu_valid_raw_d = Output(Bool())
|
||||||
val dec_lsu_offset_d = Output(UInt(12.W))
|
val dec_lsu_offset_d = Output(UInt(12.W))
|
||||||
val dec_csr_ren_d = Output(Bool()) // valid csr decode
|
|
||||||
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
|
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
|
||||||
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
|
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
|
||||||
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
|
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
|
||||||
|
@ -100,16 +75,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r
|
val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r
|
||||||
val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus
|
val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus
|
||||||
val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c
|
val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c
|
||||||
val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet
|
val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet
|
||||||
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
|
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
|
||||||
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
|
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
|
||||||
val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct
|
|
||||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode
|
|
||||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr
|
|
||||||
val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index
|
|
||||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag
|
|
||||||
val dec_data_en = Output(UInt(2.W)) // clock-gating logic
|
|
||||||
val dec_ctl_en = Output(UInt(2.W))
|
|
||||||
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
|
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
|
||||||
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
|
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
|
||||||
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
|
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
|
||||||
|
@ -120,40 +88,43 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
|
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
|
||||||
val dec_div_active = Output(Bool()) // non-block divide is active
|
val dec_div_active = Output(Bool()) // non-block divide is active
|
||||||
val scan_mode = Input(Bool())
|
val scan_mode = Input(Bool())
|
||||||
})
|
|
||||||
|
val dec_aln = Flipped(new aln_dec)
|
||||||
|
val dbg_dctl = new dbg_dctl()
|
||||||
|
})
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// //packets zero initialization
|
// //packets zero initialization
|
||||||
io.mul_p := 0.U.asTypeOf(io.mul_p)
|
io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
|
||||||
// Vals defined
|
// Vals defined
|
||||||
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
|
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
|
||||||
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
|
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
|
||||||
val i0r = Wire(new el2_reg_pkt_t)
|
val i0r = Wire(new reg_pkt_t)
|
||||||
val d_t = Wire(new el2_trap_pkt_t)
|
val d_t = Wire(new trap_pkt_t)
|
||||||
val x_t = Wire(new el2_trap_pkt_t)
|
val x_t = Wire(new trap_pkt_t)
|
||||||
val x_t_in = Wire(new el2_trap_pkt_t)
|
val x_t_in = Wire(new trap_pkt_t)
|
||||||
val r_t = Wire(new el2_trap_pkt_t)
|
val r_t = Wire(new trap_pkt_t)
|
||||||
val r_t_in = Wire(new el2_trap_pkt_t)
|
val r_t_in = Wire(new trap_pkt_t)
|
||||||
val d_d = Wire(new el2_dest_pkt_t)
|
val d_d = Wire(Valid(new dest_pkt_t))
|
||||||
val x_d = Wire(new el2_dest_pkt_t)
|
val x_d = Wire(Valid(new dest_pkt_t))
|
||||||
val r_d = Wire(new el2_dest_pkt_t)
|
val r_d = Wire(Valid(new dest_pkt_t))
|
||||||
val r_d_in = Wire(new el2_dest_pkt_t)
|
val r_d_in = Wire(Valid(new dest_pkt_t))
|
||||||
val wbd = Wire(new el2_dest_pkt_t)
|
val wbd = Wire(Valid(new dest_pkt_t))
|
||||||
val i0_d_c = Wire(new el2_class_pkt_t)
|
val i0_d_c = Wire(new class_pkt_t)
|
||||||
val i0_rs1_class_d = Wire(new el2_class_pkt_t)
|
val i0_rs1_class_d = Wire(new class_pkt_t)
|
||||||
val i0_rs2_class_d = Wire(new el2_class_pkt_t)
|
val i0_rs2_class_d = Wire(new class_pkt_t)
|
||||||
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
||||||
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
||||||
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
val cam_write=WireInit(UInt(1.W), 0.U)
|
val cam_write=WireInit(UInt(1.W), 0.U)
|
||||||
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
|
||||||
//val i0_temp = Wire(new el2_inst_pkt_t)
|
//val i0_temp = Wire(new inst_pkt_t)
|
||||||
val i0_dp= Wire(new el2_dec_pkt_t)
|
val i0_dp= Wire(new dec_pkt_t)
|
||||||
val i0_dp_raw= Wire(new el2_dec_pkt_t)
|
val i0_dp_raw= Wire(new dec_pkt_t)
|
||||||
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
|
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
|
||||||
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
|
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
|
||||||
val illegal_lockout = WireInit(UInt(1.W), 0.U)
|
val illegal_lockout = WireInit(UInt(1.W), 0.U)
|
||||||
|
@ -207,10 +178,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val i0_result_r = WireInit(UInt(32.W), 0.U)
|
val i0_result_r = WireInit(UInt(32.W), 0.U)
|
||||||
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
||||||
// Start - Data gating {{
|
// Start - Data gating {{
|
||||||
|
|
||||||
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
|
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
|
||||||
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
|
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
|
||||||
(io.dec_tlu_flush_extint ^ io.dec_extint_stall) |
|
(io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) |
|
||||||
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
|
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
|
||||||
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
|
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
|
||||||
(pause_state_in ^ pause_state ) | // replaces free_clk
|
(pause_state_in ^ pause_state ) | // replaces free_clk
|
||||||
|
@ -218,39 +188,36 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk
|
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk
|
||||||
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
|
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
|
||||||
|
|
||||||
val data_gated_cgc= Module(new rvclkhdr)
|
|
||||||
data_gated_cgc.io.en := data_gate_en
|
val data_gate_clk= rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
|
||||||
data_gated_cgc.io.scan_mode :=io.scan_mode
|
|
||||||
data_gated_cgc.io.clk :=clock
|
|
||||||
val data_gate_clk =data_gated_cgc.io.l1clk
|
|
||||||
|
|
||||||
// End - Data gating }}
|
// End - Data gating }}
|
||||||
|
|
||||||
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
||||||
io.dec_i0_predict_p_d.misp :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.misp :=0.U
|
||||||
io.dec_i0_predict_p_d.ataken :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.ataken :=0.U
|
||||||
io.dec_i0_predict_p_d.boffset :=0.U
|
io.decode_exu.dec_i0_predict_p_d.bits.boffset :=0.U
|
||||||
io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error
|
io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
|
||||||
io.dec_i0_predict_p_d.pja := i0_pja
|
io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja
|
||||||
io.dec_i0_predict_p_d.pret := i0_pret
|
io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret
|
||||||
io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett
|
io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett
|
||||||
io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d
|
io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
|
||||||
io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist
|
io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist
|
||||||
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
|
io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
|
||||||
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
|
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
|
||||||
|
|
||||||
// no toffset error for a pret
|
// no toffset error for a pret
|
||||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
|
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
|
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
|
||||||
val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||||
io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
||||||
io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
|
io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||||
io.i0_predict_index_d := io.dec_i0_bp_index
|
io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index
|
||||||
io.i0_predict_btag_d := io.dec_i0_bp_btag
|
io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag
|
||||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
|
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
|
||||||
io.dec_i0_predict_p_d.toffset := i0_br_offset
|
io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset
|
||||||
io.i0_predict_fghr_d := io.dec_i0_bp_fghr
|
io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr
|
||||||
io.dec_i0_predict_p_d.way := io.dec_i0_brp.way
|
io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way
|
||||||
// end
|
// end
|
||||||
|
|
||||||
// on br error turn anything into a nop
|
// on br error turn anything into a nop
|
||||||
|
@ -271,58 +238,58 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
}
|
}
|
||||||
|
|
||||||
val i0 = io.dec_i0_instr_d
|
val i0 = io.dec_i0_instr_d
|
||||||
io.dec_i0_select_pc_d := i0_dp.pc;
|
io.decode_exu.dec_i0_select_pc_d := i0_dp.pc
|
||||||
|
|
||||||
// branches that can be predicted
|
// branches that can be predicted
|
||||||
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
||||||
|
|
||||||
val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||||
val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||||
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
||||||
val i0_ap_pc4 = io.dec_i0_pc4_d
|
val i0_ap_pc4 = io.dec_i0_pc4_d
|
||||||
io.i0_ap.predict_nt := i0_predict_nt
|
io.decode_exu.i0_ap.predict_nt := i0_predict_nt
|
||||||
io.i0_ap.predict_t := i0_predict_t
|
io.decode_exu.i0_ap.predict_t := i0_predict_t
|
||||||
|
|
||||||
io.i0_ap.add := i0_dp.add
|
|
||||||
io.i0_ap.sub := i0_dp.sub
|
|
||||||
io.i0_ap.land := i0_dp.land
|
|
||||||
io.i0_ap.lor := i0_dp.lor
|
|
||||||
io.i0_ap.lxor := i0_dp.lxor
|
|
||||||
io.i0_ap.sll := i0_dp.sll
|
|
||||||
io.i0_ap.srl := i0_dp.srl
|
|
||||||
io.i0_ap.sra := i0_dp.sra
|
|
||||||
io.i0_ap.slt := i0_dp.slt
|
|
||||||
io.i0_ap.unsign := i0_dp.unsign
|
|
||||||
io.i0_ap.beq := i0_dp.beq
|
|
||||||
io.i0_ap.bne := i0_dp.bne
|
|
||||||
io.i0_ap.blt := i0_dp.blt
|
|
||||||
io.i0_ap.bge := i0_dp.bge
|
|
||||||
io.i0_ap.csr_write := i0_csr_write_only_d
|
|
||||||
io.i0_ap.csr_imm := i0_dp.csr_imm
|
|
||||||
io.i0_ap.jal := i0_jal
|
|
||||||
|
|
||||||
|
io.decode_exu.i0_ap.add := i0_dp.add
|
||||||
|
io.decode_exu.i0_ap.sub := i0_dp.sub
|
||||||
|
io.decode_exu.i0_ap.land := i0_dp.land
|
||||||
|
io.decode_exu.i0_ap.lor := i0_dp.lor
|
||||||
|
io.decode_exu.i0_ap.lxor := i0_dp.lxor
|
||||||
|
io.decode_exu.i0_ap.sll := i0_dp.sll
|
||||||
|
io.decode_exu.i0_ap.srl := i0_dp.srl
|
||||||
|
io.decode_exu.i0_ap.sra := i0_dp.sra
|
||||||
|
io.decode_exu.i0_ap.slt := i0_dp.slt
|
||||||
|
io.decode_exu.i0_ap.unsign := i0_dp.unsign
|
||||||
|
io.decode_exu.i0_ap.beq := i0_dp.beq
|
||||||
|
io.decode_exu.i0_ap.bne := i0_dp.bne
|
||||||
|
io.decode_exu.i0_ap.blt := i0_dp.blt
|
||||||
|
io.decode_exu.i0_ap.bge := i0_dp.bge
|
||||||
|
io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d
|
||||||
|
io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm
|
||||||
|
io.decode_exu.i0_ap.jal := i0_jal
|
||||||
|
|
||||||
// non block load cam logic
|
// non block load cam logic
|
||||||
// val found=Wire(UInt(1.W))
|
// val found=Wire(UInt(1.W))
|
||||||
cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i)))
|
cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i)))
|
||||||
|
|
||||||
cam_write := io.lsu_nonblock_load_valid_m
|
cam_write := io.dctl_busbuff.lsu_nonblock_load_valid_m
|
||||||
val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0)
|
val cam_write_tag = io.dctl_busbuff.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0)
|
||||||
|
|
||||||
val cam_inv_reset = io.lsu_nonblock_load_inv_r
|
val cam_inv_reset = io.dctl_busbuff.lsu_nonblock_load_inv_r
|
||||||
val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r(LSU_NUM_NBLOAD_WIDTH-1,0)
|
val cam_inv_reset_tag = io.dctl_busbuff.lsu_nonblock_load_inv_tag_r
|
||||||
|
|
||||||
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error
|
val cam_data_reset = io.dctl_busbuff.lsu_nonblock_load_data_valid | io.dctl_busbuff.lsu_nonblock_load_data_error
|
||||||
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0)
|
val cam_data_reset_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag
|
||||||
|
|
||||||
val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data
|
val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data
|
||||||
val load_data_tag = io.lsu_nonblock_load_data_tag
|
val load_data_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag
|
||||||
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
|
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
|
||||||
// don't writeback a nonblock load
|
// don't writeback a nonblock load
|
||||||
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
|
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.dctl_busbuff.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
|
||||||
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
|
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load
|
||||||
for(i <- 0 until LSU_NUM_NBLOAD){
|
for(i <- 0 until LSU_NUM_NBLOAD){
|
||||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
|
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid
|
||||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
|
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid
|
||||||
cam_in(i):=0.U.asTypeOf(cam(0))
|
cam_in(i):=0.U.asTypeOf(cam(0))
|
||||||
cam(i):=cam_raw(i)
|
cam(i):=cam_raw(i)
|
||||||
|
|
||||||
|
@ -331,16 +298,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
}
|
}
|
||||||
when(cam_wen(i).asBool){
|
when(cam_wen(i).asBool){
|
||||||
cam_in(i).valid := 1.U(1.W)
|
cam_in(i).valid := 1.U(1.W)
|
||||||
cam_in(i).wb := 0.U(1.W)
|
cam_in(i).bits.wb := 0.U(1.W)
|
||||||
cam_in(i).tag := cam_write_tag
|
cam_in(i).bits.tag := cam_write_tag
|
||||||
cam_in(i).rd := nonblock_load_rd
|
cam_in(i).bits.rd := nonblock_load_rd
|
||||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
|
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){
|
||||||
cam_in(i).valid := 0.U
|
cam_in(i).valid := 0.U
|
||||||
}.otherwise{
|
}.otherwise{
|
||||||
cam_in(i) := cam(i)
|
cam_in(i) := cam(i)
|
||||||
}
|
}
|
||||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
|
when(nonblock_load_valid_m_delay===1.U && (io.dctl_busbuff.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){
|
||||||
cam_in(i).wb := 1.U
|
cam_in(i).bits.wb := 1.U
|
||||||
}
|
}
|
||||||
// force debug halt forces cam valids to 0; highest priority
|
// force debug halt forces cam valids to 0; highest priority
|
||||||
when(io.dec_tlu_force_halt){
|
when(io.dec_tlu_force_halt){
|
||||||
|
@ -348,18 +315,18 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
}
|
}
|
||||||
|
|
||||||
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
|
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
|
||||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
|
nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid
|
||||||
}
|
}
|
||||||
|
|
||||||
io.dec_nonblock_load_waddr:=0.U(5.W)
|
io.dec_nonblock_load_waddr:=0.U(5.W)
|
||||||
// cancel if any younger inst (including another nonblock) committing this cycle
|
// cancel if any younger inst (including another nonblock) committing this cycle
|
||||||
val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
|
val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
|
||||||
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
|
io.dec_nonblock_load_wen := (io.dctl_busbuff.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
|
||||||
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d)
|
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs2_en_d)
|
||||||
|
|
||||||
i0_nonblock_load_stall := i0_nonblock_boundary_stall
|
i0_nonblock_load_stall := i0_nonblock_boundary_stall
|
||||||
|
|
||||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
|
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.decode_exu.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.decode_exu.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2))
|
||||||
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
|
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
|
||||||
io.dec_nonblock_load_waddr:=waddr
|
io.dec_nonblock_load_waddr:=waddr
|
||||||
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
|
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
|
||||||
|
@ -374,7 +341,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val i0_br_unpred = i0_dp.jal & !i0_predict_br
|
val i0_br_unpred = i0_dp.jal & !i0_predict_br
|
||||||
|
|
||||||
// the classes must be mutually exclusive with one another
|
// the classes must be mutually exclusive with one another
|
||||||
import el2_inst_pkt_t._
|
import inst_pkt_t._
|
||||||
d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array(
|
d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array(
|
||||||
i0_dp.jal -> JAL,
|
i0_dp.jal -> JAL,
|
||||||
i0_dp.condbr -> CONDBR,
|
i0_dp.condbr -> CONDBR,
|
||||||
|
@ -392,7 +359,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
i0_dp.mul -> MUL))
|
i0_dp.mul -> MUL))
|
||||||
// end pmu
|
// end pmu
|
||||||
|
|
||||||
val i0_dec =Module(new el2_dec_dec_ctl)
|
val i0_dec =Module(new dec_dec_ctl)
|
||||||
i0_dec.io.ins:= i0
|
i0_dec.io.ins:= i0
|
||||||
i0_dp_raw:=i0_dec.io.out
|
i0_dp_raw:=i0_dec.io.out
|
||||||
|
|
||||||
|
@ -402,20 +369,20 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
|
leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
|
||||||
leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)}
|
leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)}
|
||||||
leak1_mode := leak1_i1_stall
|
leak1_mode := leak1_i1_stall
|
||||||
leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
|
leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
|
||||||
leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)}
|
leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)}
|
||||||
|
|
||||||
// 12b jal's can be predicted - these are calls
|
// 12b jal's can be predicted - these are calls
|
||||||
|
|
||||||
val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21),0.U(1.W))
|
val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21))
|
||||||
val i0_pcall_12b_offset = Mux(i0_pcall_imm(12).asBool, i0_pcall_imm(20,13) === 0xff.U , i0_pcall_imm(20,13) === 0.U(8.W))
|
val i0_pcall_12b_offset = Mux(i0_pcall_imm(11).asBool, i0_pcall_imm(19,12) === 0xff.U , i0_pcall_imm(19,12) === 0.U(8.W))
|
||||||
val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
||||||
val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
||||||
i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja
|
i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja
|
||||||
i0_pcall := i0_dp.jal & i0_pcall_case
|
i0_pcall := i0_dp.jal & i0_pcall_case
|
||||||
i0_pja_raw := i0_dp_raw.jal & i0_pja_case
|
i0_pja_raw := i0_dp_raw.jal & i0_pja_case
|
||||||
i0_pja := i0_dp.jal & i0_pja_case
|
i0_pja := i0_dp.jal & i0_pja_case
|
||||||
i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(12,1) , Cat(i0(31),i0(7),i0(30,25),i0(11,8)))
|
i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(11,0) , Cat(i0(31),i0(7),i0(30,25),i0(11,8)))
|
||||||
// jalr with rd==0, rs1==1 or rs1==5 is a ret
|
// jalr with rd==0, rs1==1 or rs1==5 is a ret
|
||||||
val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W)))
|
val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W)))
|
||||||
i0_pret_raw := i0_dp_raw.jal & i0_pret_case
|
i0_pret_raw := i0_dp_raw.jal & i0_pret_case
|
||||||
|
@ -423,38 +390,38 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case
|
i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case
|
||||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
io.div_p.valid := div_decode_d
|
io.dec_div.div_p.valid := div_decode_d
|
||||||
io.div_p.unsign := i0_dp.unsign
|
io.dec_div.div_p.bits.unsign := i0_dp.unsign
|
||||||
io.div_p.rem := i0_dp.rem
|
io.dec_div.div_p.bits.rem := i0_dp.rem
|
||||||
|
|
||||||
io.mul_p.valid := mul_decode_d
|
io.decode_exu.mul_p.valid := mul_decode_d
|
||||||
io.mul_p.rs1_sign := i0_dp.rs1_sign
|
io.decode_exu.mul_p.bits.rs1_sign := i0_dp.rs1_sign
|
||||||
io.mul_p.rs2_sign := i0_dp.rs2_sign
|
io.decode_exu.mul_p.bits.rs2_sign := i0_dp.rs2_sign
|
||||||
io.mul_p.low := i0_dp.low
|
io.decode_exu.mul_p.bits.low := i0_dp.low
|
||||||
|
|
||||||
io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
|
io.decode_exu.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
|
||||||
|
|
||||||
io.lsu_p := 0.U.asTypeOf(io.lsu_p)
|
io.lsu_p := 0.U.asTypeOf(io.lsu_p)
|
||||||
when (io.dec_extint_stall){
|
when (io.decode_exu.dec_extint_stall){
|
||||||
io.lsu_p.load := 1.U(1.W)
|
io.lsu_p.bits.load := 1.U(1.W)
|
||||||
io.lsu_p.word := 1.U(1.W)
|
io.lsu_p.bits.word := 1.U(1.W)
|
||||||
io.lsu_p.fast_int := 1.U(1.W)
|
io.lsu_p.bits.fast_int := 1.U(1.W)
|
||||||
io.lsu_p.valid := 1.U(1.W)
|
io.lsu_p.valid := 1.U(1.W)
|
||||||
}.otherwise {
|
}.otherwise {
|
||||||
io.lsu_p.valid := lsu_decode_d
|
io.lsu_p.valid := lsu_decode_d
|
||||||
io.lsu_p.load := i0_dp.load
|
io.lsu_p.bits.load := i0_dp.load
|
||||||
io.lsu_p.store := i0_dp.store
|
io.lsu_p.bits.store := i0_dp.store
|
||||||
io.lsu_p.by := i0_dp.by
|
io.lsu_p.bits.by := i0_dp.by
|
||||||
io.lsu_p.half := i0_dp.half
|
io.lsu_p.bits.half := i0_dp.half
|
||||||
io.lsu_p.word := i0_dp.word
|
io.lsu_p.bits.word := i0_dp.word
|
||||||
io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d
|
io.lsu_p.bits.load_ldst_bypass_d := load_ldst_bypass_d
|
||||||
io.lsu_p.store_data_bypass_d := store_data_bypass_d
|
io.lsu_p.bits.store_data_bypass_d := store_data_bypass_d
|
||||||
io.lsu_p.store_data_bypass_m := store_data_bypass_m
|
io.lsu_p.bits.store_data_bypass_m := store_data_bypass_m
|
||||||
io.lsu_p.unsign := i0_dp.unsign
|
io.lsu_p.bits.unsign := i0_dp.unsign
|
||||||
}
|
}
|
||||||
|
|
||||||
//////////////////////////////////////
|
//////////////////////////////////////
|
||||||
io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU
|
io.dec_alu.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU
|
||||||
csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above
|
csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above
|
||||||
|
|
||||||
val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d
|
val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d
|
||||||
|
@ -467,14 +434,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
//dec_csr_wen_unq_d assigned as csr_write above
|
//dec_csr_wen_unq_d assigned as csr_write above
|
||||||
|
|
||||||
io.dec_csr_rdaddr_d := i0(31,20)
|
io.dec_csr_rdaddr_d := i0(31,20)
|
||||||
io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt
|
io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a dest_pkt
|
||||||
|
|
||||||
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
|
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
|
||||||
// also use valid so it's flushable
|
// also use valid so it's flushable
|
||||||
io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r;
|
io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r;
|
||||||
|
|
||||||
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
|
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
|
||||||
io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb;
|
io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb;
|
||||||
|
|
||||||
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
|
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
|
||||||
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
|
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
|
||||||
|
@ -488,19 +455,19 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
|
|
||||||
val csr_mask_x = Mux1H(Seq(
|
val csr_mask_x = Mux1H(Seq(
|
||||||
csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)),
|
csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)),
|
||||||
!csr_imm_x.asBool -> io.exu_csr_rs1_x))
|
!csr_imm_x.asBool -> io.decode_exu.exu_csr_rs1_x))
|
||||||
|
|
||||||
val write_csr_data_x = Mux1H(Seq(
|
val write_csr_data_x = Mux1H(Seq(
|
||||||
csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt),
|
csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt),
|
||||||
csr_set_x -> (csr_rddata_x | csr_mask_x),
|
csr_set_x -> (csr_rddata_x | csr_mask_x),
|
||||||
csr_write_x -> ( csr_mask_x)))
|
csr_write_x -> ( csr_mask_x)))
|
||||||
// pause instruction
|
// pause instruction
|
||||||
val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause
|
val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === Cat(Fill(31,0.U),write_csr_data(0)))) // if 0 or 1 then exit pause state - 1 cycle pause
|
||||||
pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause
|
pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause
|
||||||
pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)}
|
pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)}
|
||||||
io.dec_pause_state := pause_state
|
io.dec_pause_state := pause_state
|
||||||
tlu_wr_pause_r1 := RegNext(io.dec_tlu_wr_pause_r, 0.U)
|
tlu_wr_pause_r1 := withClock(data_gate_clk){RegNext(io.dec_tlu_wr_pause_r, 0.U)}
|
||||||
tlu_wr_pause_r2 := RegNext(tlu_wr_pause_r1, 0.U)
|
tlu_wr_pause_r2 := withClock(data_gate_clk){RegNext(tlu_wr_pause_r1, 0.U)}
|
||||||
//pause for clock gating
|
//pause for clock gating
|
||||||
io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2))
|
io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2))
|
||||||
// end pause
|
// end pause
|
||||||
|
@ -514,12 +481,12 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val pause_stall = pause_state
|
val pause_stall = pause_state
|
||||||
|
|
||||||
// for csr write only data is produced by the alu
|
// for csr write only data is produced by the alu
|
||||||
io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data)
|
io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data)
|
||||||
|
|
||||||
val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly;
|
val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly;
|
||||||
|
|
||||||
val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0)
|
val debug_fence_i = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(0)
|
||||||
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1)
|
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(1)
|
||||||
debug_fence := debug_fence_raw | debug_fence_i
|
debug_fence := debug_fence_raw | debug_fence_i
|
||||||
|
|
||||||
// some CSR reads need to be presync'd
|
// some CSR reads need to be presync'd
|
||||||
|
@ -531,17 +498,17 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val any_csr_d = i0_dp.csr_read | i0_csr_write
|
val any_csr_d = i0_dp.csr_read | i0_csr_write
|
||||||
io.dec_csr_any_unq_d := any_csr_d
|
io.dec_csr_any_unq_d := any_csr_d
|
||||||
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
|
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
|
||||||
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst))
|
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst))
|
||||||
// illegal inst handling
|
// illegal inst handling
|
||||||
|
|
||||||
val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal
|
val shift_illegal = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal
|
||||||
val illegal_inst_en = shift_illegal & !illegal_lockout
|
val illegal_inst_en = shift_illegal & !illegal_lockout
|
||||||
io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
|
io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
|
||||||
illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
|
illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
|
||||||
illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)}
|
illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)}
|
||||||
val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active
|
val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active
|
||||||
//stalls signals
|
//stalls signals
|
||||||
val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall |
|
val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.decode_exu.dec_extint_stall | pause_stall |
|
||||||
leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall |
|
leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall |
|
||||||
((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
|
((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
|
||||||
i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
|
i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
|
||||||
|
@ -552,33 +519,33 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val i0_exublock_d = i0_block_raw_d
|
val i0_exublock_d = i0_block_raw_d
|
||||||
|
|
||||||
//decode valid
|
//decode valid
|
||||||
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||||
val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||||
val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
|
val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
|
||||||
|
|
||||||
// performance monitor signals
|
// performance monitor signals
|
||||||
io.dec_pmu_instr_decoded := io.dec_i0_decode_d
|
io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d
|
||||||
io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d
|
io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d
|
||||||
io.dec_pmu_postsync_stall := postsync_stall.asBool
|
io.dec_pmu_postsync_stall := postsync_stall.asBool
|
||||||
io.dec_pmu_presync_stall := presync_stall.asBool
|
io.dec_pmu_presync_stall := presync_stall.asBool
|
||||||
|
|
||||||
val prior_inflight_x = x_d.i0valid
|
val prior_inflight_x = x_d.valid
|
||||||
val prior_inflight_wb = r_d.i0valid
|
val prior_inflight_wb = r_d.valid
|
||||||
val prior_inflight = prior_inflight_x | prior_inflight_wb
|
val prior_inflight = prior_inflight_x | prior_inflight_wb
|
||||||
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
|
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
|
||||||
|
|
||||||
presync_stall := (i0_presync & prior_inflight_eff)
|
presync_stall := (i0_presync & prior_inflight_eff)
|
||||||
postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)}
|
postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)}
|
||||||
// illegals will postsync
|
// illegals will postsync
|
||||||
ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
|
ps_stall_in := (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
|
||||||
|
|
||||||
io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
|
io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
|
||||||
|
|
||||||
lsu_decode_d := i0_legal_decode_d & i0_dp.lsu
|
lsu_decode_d := i0_legal_decode_d & i0_dp.lsu
|
||||||
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
|
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
|
||||||
div_decode_d := i0_exulegal_decode_d & i0_dp.div
|
div_decode_d := i0_exulegal_decode_d & i0_dp.div
|
||||||
|
|
||||||
io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb
|
io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb
|
||||||
|
|
||||||
//traps for TLU (tlu stuff)
|
//traps for TLU (tlu stuff)
|
||||||
d_t.legal := i0_legal_decode_d
|
d_t.legal := i0_legal_decode_d
|
||||||
|
@ -593,7 +560,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
d_t.pmu_divide := 0.U(1.W)
|
d_t.pmu_divide := 0.U(1.W)
|
||||||
d_t.pmu_lsu_misaligned := 0.U(1.W)
|
d_t.pmu_lsu_misaligned := 0.U(1.W)
|
||||||
|
|
||||||
d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d)
|
d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d)
|
||||||
|
|
||||||
|
|
||||||
x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode)
|
x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
@ -607,25 +574,25 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
|
|
||||||
r_t_in := r_t
|
r_t_in := r_t
|
||||||
|
|
||||||
r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
|
r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
|
||||||
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
|
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
|
||||||
|
|
||||||
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
|
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
|
||||||
|
|
||||||
io.dec_tlu_packet_r := r_t_in
|
io.dec_tlu_packet_r := r_t_in
|
||||||
io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid
|
io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid
|
||||||
// end tlu stuff
|
// end tlu stuff
|
||||||
|
|
||||||
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
|
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
|
||||||
|
|
||||||
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||||
|
|
||||||
i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits
|
i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits
|
||||||
i0r.rs2 := i0(24,20)
|
i0r.rs2 := i0(24,20)
|
||||||
i0r.rd := i0(11,7)
|
i0r.rd := i0(11,7)
|
||||||
|
|
||||||
io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's
|
io.decode_exu.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's
|
||||||
io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W))
|
io.decode_exu.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W))
|
||||||
val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W))
|
val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W))
|
||||||
io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile
|
io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile
|
||||||
io.dec_i0_rs2_d := i0r.rs2
|
io.dec_i0_rs2_d := i0r.rs2
|
||||||
|
@ -633,7 +600,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915)
|
val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915)
|
||||||
val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20
|
val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20
|
||||||
|
|
||||||
io.dec_i0_immed_d := Mux1H(Seq(
|
io.decode_exu.dec_i0_immed_d := Mux1H(Seq(
|
||||||
i0_dp.csr_read -> io.dec_csr_rddata_d,
|
i0_dp.csr_read -> io.dec_csr_rddata_d,
|
||||||
!i0_dp.csr_read -> i0_immed_d))
|
!i0_dp.csr_read -> i0_immed_d))
|
||||||
|
|
||||||
|
@ -644,7 +611,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)),
|
i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)),
|
||||||
(i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write
|
(i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write
|
||||||
|
|
||||||
i0_legal_decode_d := io.dec_i0_decode_d & i0_legal
|
i0_legal_decode_d := io.dec_aln.dec_i0_decode_d & i0_legal
|
||||||
|
|
||||||
i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
|
i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
|
||||||
i0_d_c.load := i0_dp.load & i0_legal_decode_d
|
i0_d_c.load := i0_dp.load & i0_legal_decode_d
|
||||||
|
@ -652,7 +619,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
|
|
||||||
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
|
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
|
||||||
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
|
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
|
||||||
i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
|
i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
|
||||||
|
|
||||||
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
|
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
|
||||||
i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
|
i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
|
||||||
|
@ -662,75 +629,75 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override)
|
i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override)
|
||||||
i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override)
|
i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override)
|
||||||
|
|
||||||
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
|
io.decode_exu.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
|
||||||
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
|
io.decode_exu.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
|
||||||
|
|
||||||
d_d.i0rd := i0r.rd
|
d_d.bits.i0rd := i0r.rd
|
||||||
d_d.i0v := i0_rd_en_d & i0_legal_decode_d
|
d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d
|
||||||
d_d.i0valid := io.dec_i0_decode_d // has flush_final_r
|
d_d.valid := io.dec_aln.dec_i0_decode_d // has flush_final_r
|
||||||
|
|
||||||
d_d.i0load := i0_dp.load & i0_legal_decode_d
|
d_d.bits.i0load := i0_dp.load & i0_legal_decode_d
|
||||||
d_d.i0store := i0_dp.store & i0_legal_decode_d
|
d_d.bits.i0store := i0_dp.store & i0_legal_decode_d
|
||||||
d_d.i0div := i0_dp.div & i0_legal_decode_d
|
d_d.bits.i0div := i0_dp.div & i0_legal_decode_d
|
||||||
|
|
||||||
d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
|
d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
|
||||||
d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
|
d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d
|
||||||
d_d.csrwaddr := i0(31,20)
|
d_d.bits.csrwaddr := i0(31,20)
|
||||||
|
|
||||||
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
|
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
val x_d_in = Wire(new el2_dest_pkt_t)
|
val x_d_in = Wire(Valid(new dest_pkt_t))
|
||||||
x_d_in := x_d
|
x_d_in := x_d
|
||||||
x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||||
x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||||
|
|
||||||
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
|
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
|
||||||
r_d_in := r_d
|
r_d_in := r_d
|
||||||
r_d_in.i0rd := r_d.i0rd
|
r_d_in.bits.i0rd := r_d.bits.i0rd
|
||||||
|
|
||||||
r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb)
|
r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb)
|
||||||
r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb)
|
r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb)
|
||||||
r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb
|
r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb
|
||||||
r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb
|
r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb
|
||||||
|
|
||||||
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
|
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
io.dec_i0_waddr_r := r_d_in.i0rd
|
io.dec_i0_waddr_r := r_d_in.bits.i0rd
|
||||||
i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r
|
i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r
|
||||||
io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
|
io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
|
||||||
io.dec_i0_wdata_r := i0_result_corr_r
|
io.dec_i0_wdata_r := i0_result_corr_r
|
||||||
|
|
||||||
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||||
if ( LOAD_TO_USE_PLUS1 == 1 ) {
|
if ( LOAD_TO_USE_PLUS1 == 1 ) {
|
||||||
i0_result_x := io.exu_i0_result_x
|
i0_result_x := io.decode_exu.exu_i0_result_x
|
||||||
i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
|
i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
|
i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.decode_exu.exu_i0_result_x)
|
||||||
i0_result_r := i0_result_r_raw
|
i0_result_r := i0_result_r_raw
|
||||||
}
|
}
|
||||||
|
|
||||||
// correct lsu load data - don't use for bypass, do pass down the pipe
|
// correct lsu load data - don't use for bypass, do pass down the pipe
|
||||||
i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
|
i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
|
||||||
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
|
io.dec_alu.dec_i0_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
|
||||||
val last_br_immed_d = WireInit(UInt(12.W),0.U)
|
val last_br_immed_d = WireInit(UInt(12.W),0.U)
|
||||||
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
|
last_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
|
||||||
val last_br_immed_x = WireInit(UInt(12.W),0.U)
|
val last_br_immed_x = WireInit(UInt(12.W),0.U)
|
||||||
last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode)
|
last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
// divide stuff
|
// divide stuff
|
||||||
|
|
||||||
val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid)
|
val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid)
|
||||||
|
|
||||||
val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) |
|
val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) |
|
||||||
(x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) |
|
(x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) |
|
||||||
(r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
|
(r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
|
||||||
|
|
||||||
// cancel if any younger inst committing this cycle to same dest as nonblock divide
|
// cancel if any younger inst committing this cycle to same dest as nonblock divide
|
||||||
|
|
||||||
val nonblock_div_cancel = (io.dec_div_active & div_flush) |
|
val nonblock_div_cancel = (io.dec_div_active & div_flush) |
|
||||||
(io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r)
|
(io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r)
|
||||||
|
|
||||||
io.dec_div_cancel := nonblock_div_cancel.asBool
|
io.dec_div.dec_div_cancel := nonblock_div_cancel.asBool
|
||||||
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
|
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
|
||||||
|
|
||||||
val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel)
|
val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel)
|
||||||
|
@ -738,8 +705,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)}
|
io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)}
|
||||||
|
|
||||||
// nonblocking div scheme
|
// nonblocking div scheme
|
||||||
i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) |
|
i0_nonblock_div_stall := (io.decode_exu.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) |
|
||||||
(io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2))
|
(io.decode_exu.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2))
|
||||||
|
|
||||||
io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool)
|
io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool)
|
||||||
///div end
|
///div end
|
||||||
|
@ -757,22 +724,22 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode)
|
val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode)
|
io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode)
|
||||||
val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
val dec_i0_pc_r = rvdffe(io.dec_alu.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
io.dec_tlu_i0_pc_r := dec_i0_pc_r
|
io.dec_tlu_i0_pc_r := dec_i0_pc_r
|
||||||
|
|
||||||
//end tracing
|
//end tracing
|
||||||
|
|
||||||
val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U))
|
val temp_pred_correct_npc_x = rvbradder(Cat(io.dec_alu.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U))
|
||||||
io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1)
|
io.decode_exu.pred_correct_npc_x := temp_pred_correct_npc_x(31,1)
|
||||||
|
|
||||||
// scheduling logic for primary alu's
|
// scheduling logic for primary alu's
|
||||||
|
|
||||||
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1)
|
val i0_rs1_depend_i0_x = io.decode_exu.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1)
|
||||||
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1)
|
val i0_rs1_depend_i0_r = io.decode_exu.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1)
|
||||||
|
|
||||||
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2)
|
val i0_rs2_depend_i0_x = io.decode_exu.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2)
|
||||||
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2)
|
val i0_rs2_depend_i0_r = io.decode_exu.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2)
|
||||||
// order the producers as follows: , i0_x, i0_r, i0_wb
|
// order the producers as follows: , i0_x, i0_r, i0_wb
|
||||||
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
|
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
|
||||||
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
|
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
|
||||||
|
@ -794,34 +761,31 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
}
|
}
|
||||||
// add nonblock load rs1/rs2 bypass cases
|
// add nonblock load rs1/rs2 bypass cases
|
||||||
|
|
||||||
val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1)
|
val i0_rs1_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1)
|
||||||
|
|
||||||
val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2)
|
val i0_rs2_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2)
|
||||||
|
|
||||||
// bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r
|
// bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r
|
||||||
i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load)))
|
i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load)))
|
||||||
|
|
||||||
i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load)))
|
i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load)))
|
||||||
|
|
||||||
io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d)))
|
io.decode_exu.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d)))
|
||||||
io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d)))
|
io.decode_exu.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d)))
|
||||||
|
|
||||||
io.dec_i0_rs1_bypass_data_d := Mux1H(Seq(
|
|
||||||
|
io.decode_exu.dec_i0_rs1_bypass_data_d := Mux1H(Seq(
|
||||||
i0_rs1bypass(1).asBool -> io.lsu_result_m,
|
i0_rs1bypass(1).asBool -> io.lsu_result_m,
|
||||||
i0_rs1bypass(0).asBool -> i0_result_r,
|
i0_rs1bypass(0).asBool -> i0_result_r,
|
||||||
(!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
|
(!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data,
|
||||||
))
|
))
|
||||||
io.dec_i0_rs2_bypass_data_d := Mux1H(Seq(
|
io.decode_exu.dec_i0_rs2_bypass_data_d := Mux1H(Seq(
|
||||||
i0_rs2bypass(1).asBool -> io.lsu_result_m,
|
i0_rs2bypass(1).asBool -> io.lsu_result_m,
|
||||||
i0_rs2bypass(0).asBool -> i0_result_r,
|
i0_rs2bypass(0).asBool -> i0_result_r,
|
||||||
(!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
|
(!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data,
|
||||||
))
|
))
|
||||||
io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall)
|
io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall)
|
||||||
io.dec_lsu_offset_d := Mux1H(Seq(
|
io.dec_lsu_offset_d := Mux1H(Seq(
|
||||||
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
|
(!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
|
||||||
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
|
(!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
|
||||||
}
|
}
|
||||||
|
|
||||||
object dec_decode extends App{
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_decode_ctl)))
|
|
||||||
}
|
|
|
@ -0,0 +1,67 @@
|
||||||
|
package dec
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
class dec_gpr_ctl_IO extends Bundle{
|
||||||
|
val raddr0=Input(UInt(5.W)) // logical read addresses
|
||||||
|
val raddr1=Input(UInt(5.W))
|
||||||
|
val wen0=Input(UInt(1.W)) // write enable
|
||||||
|
val waddr0=Input(UInt(5.W)) // write address
|
||||||
|
val wd0=Input(UInt(32.W)) // write data
|
||||||
|
val wen1=Input(UInt(1.W)) // write enable
|
||||||
|
val waddr1=Input(UInt(5.W)) // write address
|
||||||
|
val wd1=Input(UInt(32.W)) // write data
|
||||||
|
val wen2=Input(UInt(1.W)) // write enable
|
||||||
|
val waddr2=Input(UInt(5.W)) // write address
|
||||||
|
val wd2=Input(UInt(32.W)) // write data
|
||||||
|
|
||||||
|
val scan_mode=Input(Bool())
|
||||||
|
val gpr_exu = Flipped(new gpr_exu())
|
||||||
|
}
|
||||||
|
|
||||||
|
class dec_gpr_ctl extends Module with lib with RequireAsyncReset{
|
||||||
|
val io =IO(new dec_gpr_ctl_IO)
|
||||||
|
val w0v =Wire(Vec(32,UInt(1.W)))
|
||||||
|
w0v := (0 until 32).map(i => 0.U)
|
||||||
|
|
||||||
|
val w1v =Wire(Vec(32,UInt(1.W)))
|
||||||
|
w1v := (0 until 32).map(i => 0.U)
|
||||||
|
|
||||||
|
val w2v =Wire(Vec(32,UInt(1.W)))
|
||||||
|
w2v := (0 until 32).map(i => 0.U)
|
||||||
|
|
||||||
|
val gpr_in =Wire(Vec(32,UInt(32.W)))
|
||||||
|
gpr_in := (0 until 32).map(i => 0.U)
|
||||||
|
|
||||||
|
val gpr_out =Wire(Vec(32,UInt(32.W)))
|
||||||
|
gpr_out := (0 until 32).map(i => 0.U)
|
||||||
|
|
||||||
|
val gpr_wr_en =WireInit(UInt(32.W),0.U)
|
||||||
|
w0v(0):=0.U
|
||||||
|
w1v(0):=0.U
|
||||||
|
w2v(0):=0.U
|
||||||
|
gpr_out(0):=0.U
|
||||||
|
gpr_in(0):=0.U
|
||||||
|
io.gpr_exu.gpr_i0_rs1_d:=0.U
|
||||||
|
io.gpr_exu.gpr_i0_rs2_d:=0.U
|
||||||
|
// GPR Write logic
|
||||||
|
for (j <-1 until 32){
|
||||||
|
w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
|
||||||
|
w1v(j) := io.wen1 & (io.waddr1===j.asUInt)
|
||||||
|
w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
|
||||||
|
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
|
||||||
|
}
|
||||||
|
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
|
||||||
|
|
||||||
|
// GPR Write Enables for power savings
|
||||||
|
for (j <-1 until 32){
|
||||||
|
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
|
||||||
|
}
|
||||||
|
// GPR Read logic
|
||||||
|
io.gpr_exu.gpr_i0_rs1_d:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i)))
|
||||||
|
io.gpr_exu.gpr_i0_rs2_d:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i)))
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,81 @@
|
||||||
|
package dec
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import exu._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
class dec_ib_ctl_IO extends Bundle with param{
|
||||||
|
val ifu_ib = Flipped(new aln_ib)
|
||||||
|
val ib_exu = Flipped(new ib_exu)
|
||||||
|
val dbg_ib = new dbg_ib
|
||||||
|
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
|
||||||
|
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
|
||||||
|
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
||||||
|
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
|
||||||
|
val dec_i0_brp =Valid(new br_pkt_t) // i0 branch packet at decode
|
||||||
|
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||||
|
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||||
|
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||||
|
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
|
||||||
|
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
|
||||||
|
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
|
||||||
|
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
|
||||||
|
}
|
||||||
|
|
||||||
|
class dec_ib_ctl extends Module with param{
|
||||||
|
val io=IO(new dec_ib_ctl_IO)
|
||||||
|
io.dec_i0_icaf_f1_d :=io.ifu_ib.ifu_i0_icaf_f1
|
||||||
|
io.dec_i0_dbecc_d :=io.ifu_ib.ifu_i0_dbecc
|
||||||
|
io.dec_i0_icaf_d :=io.ifu_ib.ifu_i0_icaf
|
||||||
|
io.ib_exu.dec_i0_pc_d :=io.ifu_ib.ifu_i0_pc
|
||||||
|
io.dec_i0_pc4_d :=io.ifu_ib.ifu_i0_pc4
|
||||||
|
io.dec_i0_icaf_type_d :=io.ifu_ib.ifu_i0_icaf_type
|
||||||
|
io.dec_i0_brp :=io.ifu_ib.i0_brp
|
||||||
|
io.dec_i0_bp_index :=io.ifu_ib.ifu_i0_bp_index
|
||||||
|
io.dec_i0_bp_fghr :=io.ifu_ib.ifu_i0_bp_fghr
|
||||||
|
io.dec_i0_bp_btag :=io.ifu_ib.ifu_i0_bp_btag
|
||||||
|
|
||||||
|
// GPR accesses
|
||||||
|
// put reg to read on rs1
|
||||||
|
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
|
||||||
|
// put write date on rs1
|
||||||
|
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
|
||||||
|
// CSR accesses
|
||||||
|
// csr is of form rd, csr, rs1
|
||||||
|
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
|
||||||
|
// put write data on rs1
|
||||||
|
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
|
||||||
|
|
||||||
|
|
||||||
|
val debug_valid =io.dbg_ib.dbg_cmd_valid & (io.dbg_ib.dbg_cmd_type =/= 2.U)
|
||||||
|
val debug_read =debug_valid & !io.dbg_ib.dbg_cmd_write
|
||||||
|
val debug_write =debug_valid & io.dbg_ib.dbg_cmd_write
|
||||||
|
|
||||||
|
val debug_read_gpr = debug_read & (io.dbg_ib.dbg_cmd_type===0.U)
|
||||||
|
val debug_write_gpr = debug_write & (io.dbg_ib.dbg_cmd_type===0.U)
|
||||||
|
val debug_read_csr = debug_read & (io.dbg_ib.dbg_cmd_type===1.U)
|
||||||
|
val debug_write_csr = debug_write & (io.dbg_ib.dbg_cmd_type===1.U)
|
||||||
|
|
||||||
|
val dreg = io.dbg_ib.dbg_cmd_addr(4,0)
|
||||||
|
val dcsr = io.dbg_ib.dbg_cmd_addr(11,0)
|
||||||
|
|
||||||
|
val ib0_debug_in =Mux1H(Seq(
|
||||||
|
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
|
||||||
|
debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)),
|
||||||
|
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)),
|
||||||
|
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W))
|
||||||
|
))
|
||||||
|
|
||||||
|
// machine is in halted state, pipe empty, write will always happen next cycle
|
||||||
|
io.ib_exu.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr
|
||||||
|
|
||||||
|
// special fence csr for use only in debug mode
|
||||||
|
io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U)
|
||||||
|
|
||||||
|
io.dec_ib0_valid_d := io.ifu_ib.ifu_i0_valid | debug_valid
|
||||||
|
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_ib.ifu_i0_instr)
|
||||||
|
|
||||||
|
|
||||||
|
}
|
File diff suppressed because it is too large
Load Diff
|
@ -2,19 +2,16 @@ package dec
|
||||||
|
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import include.el2_trigger_pkt_t
|
import include.trigger_pkt_t
|
||||||
import lib._
|
import lib._
|
||||||
|
|
||||||
class el2_dec_trigger extends Module with el2_lib {
|
class dec_trigger extends Module with lib {
|
||||||
val io = IO(new Bundle {
|
val io = IO(new Bundle {
|
||||||
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
|
val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t))
|
||||||
val dec_i0_pc_d = Input(UInt(31.W))
|
val dec_i0_pc_d = Input(UInt(31.W))
|
||||||
val dec_i0_trigger_match_d = Output(UInt(4.W))
|
val dec_i0_trigger_match_d = Output(UInt(4.W))
|
||||||
})
|
})
|
||||||
val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
|
val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
|
||||||
io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_))
|
io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_pkt.asBool())).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
}
|
}
|
||||||
object dec_trig extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger())))
|
|
||||||
}
|
|
|
@ -1,713 +0,0 @@
|
||||||
package dec
|
|
||||||
import chisel3._
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_dec_IO extends Bundle with el2_lib {
|
|
||||||
//val clk = Input(Clock())
|
|
||||||
val free_clk = Input(Clock())
|
|
||||||
val active_clk = Input(Clock())
|
|
||||||
|
|
||||||
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
|
|
||||||
|
|
||||||
val dec_extint_stall = Output(Bool())
|
|
||||||
|
|
||||||
val dec_i0_decode_d = Output(Bool())
|
|
||||||
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
|
|
||||||
|
|
||||||
// val rst_l = Input(Bool()) // reset, active low
|
|
||||||
val rst_vec = Input(UInt(32.W)) // [31:1] reset vector, from core pins
|
|
||||||
|
|
||||||
val nmi_int = Input(Bool()) // NMI pin
|
|
||||||
val nmi_vec = Input(UInt(32.W)) // [31:1] NMI vector, from pins
|
|
||||||
|
|
||||||
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
|
|
||||||
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
|
|
||||||
|
|
||||||
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
|
|
||||||
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
|
|
||||||
val o_cpu_run_ack = Output(Bool()) // Run request ack
|
|
||||||
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
|
|
||||||
|
|
||||||
val core_id = Input(UInt(32.W)) // [31:4] CORE ID
|
|
||||||
|
|
||||||
// external MPC halt/run interface
|
|
||||||
val mpc_debug_halt_req = Input(Bool()) // Async halt request
|
|
||||||
val mpc_debug_run_req = Input(Bool()) // Async run request
|
|
||||||
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
|
|
||||||
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
|
|
||||||
val mpc_debug_run_ack = Output(Bool()) // Run ack
|
|
||||||
val debug_brkpt_status = Output(Bool()) // debug breakpoint
|
|
||||||
|
|
||||||
val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp
|
|
||||||
val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken
|
|
||||||
val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch
|
|
||||||
|
|
||||||
|
|
||||||
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
|
|
||||||
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
|
|
||||||
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
|
|
||||||
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
|
|
||||||
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
|
||||||
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
|
|
||||||
|
|
||||||
val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction
|
|
||||||
val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned
|
|
||||||
val lsu_pmu_bus_error = Input(Bool()) // D side bus error
|
|
||||||
val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy
|
|
||||||
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
|
|
||||||
val lsu_pmu_load_external_m = Input(Bool()) // D side bus load
|
|
||||||
val lsu_pmu_store_external_m = Input(Bool()) // D side bus store
|
|
||||||
val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read
|
|
||||||
val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write
|
|
||||||
val dma_pmu_any_read = Input(Bool()) // DMA read
|
|
||||||
val dma_pmu_any_write = Input(Bool()) // DMA write
|
|
||||||
|
|
||||||
val lsu_fir_addr = Input(UInt(32.W)) //[31:1] Fast int address
|
|
||||||
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
|
|
||||||
|
|
||||||
val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions
|
|
||||||
val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled
|
|
||||||
val ifu_pmu_ic_miss = Input(Bool()) // icache miss
|
|
||||||
val ifu_pmu_ic_hit = Input(Bool()) // icache hit
|
|
||||||
val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error
|
|
||||||
val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy
|
|
||||||
val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction
|
|
||||||
|
|
||||||
val ifu_ic_error_start = Input(Bool()) // IC single bit error
|
|
||||||
val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error
|
|
||||||
|
|
||||||
val lsu_trigger_match_m = Input(UInt(4.W))
|
|
||||||
val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
|
|
||||||
val dbg_cmd_write = Input(Bool()) // command is a write
|
|
||||||
val dbg_cmd_type = Input(UInt(2.W)) // command type
|
|
||||||
val dbg_cmd_addr = Input(UInt(32.W)) // command address
|
|
||||||
val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i
|
|
||||||
|
|
||||||
|
|
||||||
val ifu_i0_icaf = Input(Bool()) // icache access fault
|
|
||||||
val ifu_i0_icaf_type = Input(UInt(2.W))
|
|
||||||
|
|
||||||
val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group
|
|
||||||
val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error
|
|
||||||
|
|
||||||
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
|
||||||
|
|
||||||
val i0_brp = Input(new el2_br_pkt_t) // branch packet
|
|
||||||
val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index
|
|
||||||
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
|
||||||
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
|
||||||
|
|
||||||
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet
|
|
||||||
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
|
||||||
|
|
||||||
val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error
|
|
||||||
val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error
|
|
||||||
val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address
|
|
||||||
|
|
||||||
val exu_div_result = Input(UInt(32.W)) // final div result
|
|
||||||
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
|
|
||||||
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction
|
|
||||||
val lsu_result_m = Input(UInt(32.W)) // load result
|
|
||||||
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
|
|
||||||
|
|
||||||
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
|
|
||||||
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
|
|
||||||
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event
|
|
||||||
val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event
|
|
||||||
|
|
||||||
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
|
|
||||||
|
|
||||||
val exu_flush_final = Input(Bool()) // slot0 flush
|
|
||||||
|
|
||||||
val exu_npc_r = Input(UInt(32.W)) // next PC
|
|
||||||
|
|
||||||
val exu_i0_result_x = Input(UInt(32.W)) // alu result x
|
|
||||||
|
|
||||||
|
|
||||||
val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer
|
|
||||||
val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer
|
|
||||||
val ifu_i0_pc = Input(UInt(32.W)) // pc's for instruction buffer
|
|
||||||
val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst
|
|
||||||
val exu_i0_pc_x = Input(UInt(32.W)) // pc's for e1 from the alu's
|
|
||||||
|
|
||||||
val mexintpend = Input(Bool()) // External interrupt pending
|
|
||||||
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
|
|
||||||
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
|
|
||||||
|
|
||||||
val pic_claimid = Input(UInt(8.W)) // PIC claimid
|
|
||||||
val pic_pl = Input(UInt(4.W)) // PIC priv level
|
|
||||||
val mhwakeup = Input(Bool()) // High priority wakeup
|
|
||||||
|
|
||||||
val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level
|
|
||||||
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
|
|
||||||
|
|
||||||
val ifu_ic_debug_rd_data = Input(UInt(70.W)) // diagnostic icache read data
|
|
||||||
val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid
|
|
||||||
val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
|
|
||||||
|
|
||||||
|
|
||||||
// Debug start
|
|
||||||
val dbg_halt_req = Input(Bool()) // DM requests a halt
|
|
||||||
val dbg_resume_req = Input(Bool()) // DM requests a resume
|
|
||||||
val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty
|
|
||||||
|
|
||||||
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
|
|
||||||
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
|
|
||||||
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
|
|
||||||
val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush
|
|
||||||
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
|
|
||||||
val dec_tlu_flush_leak_one_r = Output(Bool()) // single step
|
|
||||||
val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc
|
|
||||||
val dec_tlu_meihap = Output(UInt(32.W)) // Fast ext int base
|
|
||||||
|
|
||||||
val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode
|
|
||||||
|
|
||||||
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
|
|
||||||
|
|
||||||
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
|
|
||||||
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
|
|
||||||
|
|
||||||
val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks
|
|
||||||
|
|
||||||
val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced
|
|
||||||
// Debug end
|
|
||||||
// branch info from pipe0 for errors or counter updates
|
|
||||||
val exu_i0_br_hist_r = Input(UInt(2.W)) // history
|
|
||||||
val exu_i0_br_error_r = Input(Bool()) // error
|
|
||||||
val exu_i0_br_start_error_r = Input(Bool()) // start error
|
|
||||||
val exu_i0_br_valid_r = Input(Bool()) // valid
|
|
||||||
val exu_i0_br_mp_r = Input(Bool()) // mispredict
|
|
||||||
val exu_i0_br_middle_r = Input(Bool()) // middle of bank
|
|
||||||
|
|
||||||
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
|
|
||||||
|
|
||||||
val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data
|
|
||||||
val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data
|
|
||||||
val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data
|
|
||||||
val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data
|
|
||||||
|
|
||||||
val dec_i0_immed_d = Output(UInt(32.W)) // immediate data
|
|
||||||
val dec_i0_br_immed_d = Output(UInt(13.W)) // br immediate data
|
|
||||||
|
|
||||||
val i0_ap = Output(new el2_alu_pkt_t)// alu packet
|
|
||||||
|
|
||||||
val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu
|
|
||||||
|
|
||||||
val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's
|
|
||||||
|
|
||||||
val dec_i0_pc_d = Output(UInt(32.W)) // pc's at decode
|
|
||||||
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable
|
|
||||||
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable
|
|
||||||
|
|
||||||
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
|
|
||||||
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
|
|
||||||
|
|
||||||
val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet
|
|
||||||
val mul_p = Output(new el2_mul_pkt_t) // mul packet
|
|
||||||
val div_p = Output(new el2_div_pkt_t) // div packet
|
|
||||||
val dec_div_cancel = Output(Bool()) // cancel divide operation
|
|
||||||
|
|
||||||
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
|
||||||
|
|
||||||
val dec_csr_ren_d = Output(Bool()) // csr read enable
|
|
||||||
|
|
||||||
|
|
||||||
val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int
|
|
||||||
val dec_tlu_flush_path_r = Output(UInt(32.W)) // tlu flush target
|
|
||||||
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
|
|
||||||
val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache
|
|
||||||
|
|
||||||
val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage
|
|
||||||
|
|
||||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
|
||||||
|
|
||||||
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
|
||||||
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
|
||||||
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
|
||||||
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
|
||||||
|
|
||||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus
|
|
||||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
|
||||||
val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index
|
|
||||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
|
||||||
|
|
||||||
val dec_lsu_valid_raw_d = Output(Bool())
|
|
||||||
|
|
||||||
val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control
|
|
||||||
|
|
||||||
val dec_data_en = Output(UInt(2.W)) // clock-gate control logic
|
|
||||||
val dec_ctl_en = Output(UInt(2.W))
|
|
||||||
|
|
||||||
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
|
|
||||||
|
|
||||||
// val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet
|
|
||||||
|
|
||||||
// feature disable from mfdc
|
|
||||||
val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding
|
|
||||||
val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address
|
|
||||||
val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC
|
|
||||||
val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction
|
|
||||||
val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing
|
|
||||||
val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16]
|
|
||||||
|
|
||||||
// clock gating overrides from mcgc
|
|
||||||
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
|
|
||||||
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
|
|
||||||
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
|
|
||||||
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
|
|
||||||
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
|
|
||||||
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
|
|
||||||
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
|
|
||||||
|
|
||||||
val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction
|
|
||||||
val scan_mode = Input(Bool())
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
class el2_dec extends Module with param with RequireAsyncReset{
|
|
||||||
val io = IO(new el2_dec_IO)
|
|
||||||
io.dec_i0_pc_d := 0.U
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// val dec_ib0_valid_d = WireInit(Bool(),0.B)
|
|
||||||
//
|
|
||||||
// val dec_pmu_instr_decoded = WireInit(Bool(),0.B)
|
|
||||||
// val dec_pmu_decode_stall = WireInit(Bool(),0.B)
|
|
||||||
// val dec_pmu_presync_stall = WireInit(Bool(),0.B)
|
|
||||||
// val dec_pmu_postsync_stall = WireInit(Bool(),0.B)
|
|
||||||
//
|
|
||||||
// val dec_tlu_wr_pause_r = WireInit(UInt(1.W),0.U) // CSR write to pause reg is at R.
|
|
||||||
//
|
|
||||||
// val dec_i0_rs1_d = WireInit(UInt(5.W),0.U)
|
|
||||||
// val dec_i0_rs2_d = WireInit(UInt(5.W),0.U)
|
|
||||||
//
|
|
||||||
// val dec_i0_instr_d = WireInit(UInt(32.W),0.U)
|
|
||||||
//
|
|
||||||
// val dec_tlu_pipelining_disable = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_i0_waddr_r = WireInit(UInt(5.W),0.U)
|
|
||||||
// val dec_i0_wen_r = WireInit(UInt(5.W),0.U)
|
|
||||||
// val dec_i0_wdata_r = WireInit(UInt(32.W),0.U)
|
|
||||||
// val dec_csr_wen_r = WireInit(UInt(1.W),0.U) // csr write enable at wb
|
|
||||||
// val dec_csr_wraddr_r = WireInit(UInt(12.W),0.U) // write address for csryes
|
|
||||||
// val dec_csr_wrdata_r = WireInit(UInt(32.W),0.U) // csr write data at wb
|
|
||||||
//
|
|
||||||
// val dec_csr_rdaddr_d = WireInit(UInt(12.W),0.U) // read address for csr
|
|
||||||
// val dec_csr_rddata_d = WireInit(UInt(32.W),0.U) // csr read data at wb
|
|
||||||
// val dec_csr_legal_d = WireInit(Bool(),0.B) // csr indicates legal operation
|
|
||||||
//
|
|
||||||
// val dec_csr_wen_unq_d = WireInit(Bool(),0.B) // valid csr with write - for csr legal
|
|
||||||
// val dec_csr_any_unq_d = WireInit(Bool(),0.B) // valid csr - for csr legal
|
|
||||||
// val dec_csr_stall_int_ff = WireInit(Bool(),0.B) // csr is mie/mstatus
|
|
||||||
//
|
|
||||||
// val dec_tlu_packet_r = Wire(new el2_trap_pkt_t)
|
|
||||||
//
|
|
||||||
// val dec_i0_pc4_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_tlu_presync_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_tlu_postsync_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_tlu_debug_stall = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_illegal_inst = WireInit(UInt(32.W),0.U)
|
|
||||||
// val dec_i0_icaf_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_i0_dbecc_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_i0_icaf_f1_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_i0_trigger_match_d = WireInit(UInt(4.W),0.U)
|
|
||||||
// val dec_debug_fence_d = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_nonblock_load_wen = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_nonblock_load_waddr = WireInit(UInt(5.W),0.U)
|
|
||||||
// val dec_tlu_flush_pause_r = WireInit(UInt(1.W),0.U)
|
|
||||||
// val dec_i0_brp = Wire(new el2_br_pkt_t)
|
|
||||||
// val dec_i0_bp_index = WireInit(UInt(BTB_ADDR_HI.W),0.U)
|
|
||||||
// val dec_i0_bp_fghr = WireInit(UInt(BHT_GHR_SIZE.W),0.U)
|
|
||||||
// val dec_i0_bp_btag = WireInit(UInt(BTB_BTAG_SIZE.W),0.U)
|
|
||||||
//
|
|
||||||
// val dec_tlu_i0_pc_r = WireInit(UInt(32.W),0.U)
|
|
||||||
// val dec_tlu_i0_kill_writeb_wb = WireInit(Bool(),0.B)
|
|
||||||
// val dec_tlu_flush_lower_wb = WireInit(Bool(),0.B)
|
|
||||||
// val dec_tlu_i0_valid_r = WireInit(Bool(),0.B)
|
|
||||||
//
|
|
||||||
// val dec_pause_state = WireInit(Bool(),0.B)
|
|
||||||
//
|
|
||||||
// val dec_i0_icaf_type_d = WireInit(UInt(2.W),0.U) // i0 instruction access fault type
|
|
||||||
//
|
|
||||||
// val dec_tlu_flush_extint = WireInit(Bool(),0.B)// Fast ext int started
|
|
||||||
//
|
|
||||||
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
|
|
||||||
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
|
|
||||||
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
|
|
||||||
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
|
|
||||||
|
|
||||||
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
|
|
||||||
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
|
|
||||||
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
|
|
||||||
//
|
|
||||||
// val div_waddr_wb = WireInit(UInt(5.W),0.U)
|
|
||||||
//
|
|
||||||
// val dec_div_active = WireInit(Bool(),0.B)
|
|
||||||
|
|
||||||
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
val instbuff = Module(new el2_dec_ib_ctl)
|
|
||||||
val decode = Module(new el2_dec_decode_ctl)
|
|
||||||
val gpr = Module(new el2_dec_gpr_ctl)
|
|
||||||
val tlu = Module(new el2_dec_tlu_ctl)
|
|
||||||
val dec_trigger = Module(new el2_dec_trigger)
|
|
||||||
|
|
||||||
//instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO("
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
//connections for el2_dec_Ib
|
|
||||||
//inputs
|
|
||||||
instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid
|
|
||||||
instbuff.io.dbg_cmd_write := io.dbg_cmd_write
|
|
||||||
instbuff.io.dbg_cmd_type := io.dbg_cmd_type
|
|
||||||
instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr
|
|
||||||
instbuff.io.i0_brp := io.i0_brp
|
|
||||||
instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index
|
|
||||||
instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr
|
|
||||||
instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag
|
|
||||||
instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4
|
|
||||||
instbuff.io.ifu_i0_valid := io.ifu_i0_valid
|
|
||||||
instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf
|
|
||||||
instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type
|
|
||||||
instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1
|
|
||||||
instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc
|
|
||||||
instbuff.io.ifu_i0_instr := io.ifu_i0_instr
|
|
||||||
instbuff.io.ifu_i0_pc := io.ifu_i0_pc
|
|
||||||
//outputs
|
|
||||||
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
|
||||||
decode.io.dec_i0_icaf_type_d :=instbuff.io.dec_i0_icaf_type_d
|
|
||||||
decode.io.dec_i0_instr_d :=instbuff.io.dec_i0_instr_d
|
|
||||||
decode.io.dec_i0_pc_d :=instbuff.io.dec_i0_pc_d
|
|
||||||
decode.io.dec_i0_pc4_d :=instbuff.io.dec_i0_pc4_d
|
|
||||||
decode.io.dec_i0_brp :=instbuff.io.dec_i0_brp
|
|
||||||
decode.io.dec_i0_bp_index :=instbuff.io.dec_i0_bp_index
|
|
||||||
decode.io.dec_i0_bp_fghr :=instbuff.io.dec_i0_bp_fghr
|
|
||||||
decode.io.dec_i0_bp_btag :=instbuff.io.dec_i0_bp_btag
|
|
||||||
decode.io.dec_i0_icaf_d :=instbuff.io.dec_i0_icaf_d
|
|
||||||
decode.io.dec_i0_icaf_f1_d :=instbuff.io.dec_i0_icaf_f1_d
|
|
||||||
decode.io.dec_i0_dbecc_d :=instbuff.io.dec_i0_dbecc_d
|
|
||||||
io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d
|
|
||||||
decode.io.dec_debug_fence_d :=instbuff.io.dec_debug_fence_d
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
//connections for dec_trigger
|
|
||||||
//dec_trigger.io <> io
|
|
||||||
//inputs
|
|
||||||
dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
|
|
||||||
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
|
||||||
//output
|
|
||||||
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
|
||||||
dontTouch(dec_i0_trigger_match_d)
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
//connections for el2_dec_decode
|
|
||||||
// decode.io <> io
|
|
||||||
//inputs
|
|
||||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
|
||||||
decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
|
|
||||||
decode.io.ifu_i0_cinst := io.ifu_i0_cinst
|
|
||||||
decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m
|
|
||||||
decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m
|
|
||||||
decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r
|
|
||||||
decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r
|
|
||||||
decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid
|
|
||||||
decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error
|
|
||||||
decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag
|
|
||||||
decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data
|
|
||||||
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
|
|
||||||
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
|
||||||
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
|
|
||||||
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
|
|
||||||
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned
|
|
||||||
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
|
||||||
decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
|
|
||||||
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
|
|
||||||
decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata
|
|
||||||
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
|
|
||||||
decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
|
|
||||||
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
|
|
||||||
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
|
|
||||||
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
|
|
||||||
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
|
|
||||||
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
|
|
||||||
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
|
|
||||||
decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
|
|
||||||
decode.io.lsu_idle_any := io.lsu_idle_any
|
|
||||||
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
|
|
||||||
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
|
|
||||||
decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
|
||||||
decode.io.exu_div_wren := io.exu_div_wren
|
|
||||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
|
||||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
|
||||||
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
|
||||||
decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
|
|
||||||
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
|
||||||
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
|
||||||
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
|
||||||
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc_d
|
|
||||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
|
||||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
|
||||||
decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x
|
|
||||||
decode.io.lsu_result_m := io.lsu_result_m
|
|
||||||
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
|
|
||||||
decode.io.exu_flush_final := io.exu_flush_final
|
|
||||||
decode.io.exu_i0_pc_x := io.exu_i0_pc_x
|
|
||||||
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
|
|
||||||
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
|
||||||
decode.io.exu_i0_result_x := io.exu_i0_result_x
|
|
||||||
//decode.io.clk := io.clk
|
|
||||||
decode.io.free_clk := io.free_clk
|
|
||||||
decode.io.active_clk := io.active_clk
|
|
||||||
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
|
||||||
// decode.io.rst_l := io.rst_l
|
|
||||||
decode.io.scan_mode := io.scan_mode
|
|
||||||
//outputs
|
|
||||||
io.dec_extint_stall := decode.io.dec_extint_stall
|
|
||||||
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
|
|
||||||
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
|
|
||||||
io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d
|
|
||||||
io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d
|
|
||||||
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
|
||||||
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
|
||||||
io.dec_i0_immed_d := decode.io.dec_i0_immed_d
|
|
||||||
io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d
|
|
||||||
io.i0_ap := decode.io.i0_ap
|
|
||||||
io.dec_i0_decode_d := decode.io.dec_i0_decode_d
|
|
||||||
io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d
|
|
||||||
io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d
|
|
||||||
io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d
|
|
||||||
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
|
||||||
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
|
||||||
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
|
||||||
io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d
|
|
||||||
io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d
|
|
||||||
io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d
|
|
||||||
io.lsu_p := decode.io.lsu_p
|
|
||||||
io.mul_p := decode.io.mul_p
|
|
||||||
io.div_p := decode.io.div_p
|
|
||||||
gpr.io.waddr2 := decode.io.div_waddr_wb
|
|
||||||
io.dec_div_cancel := decode.io.dec_div_cancel
|
|
||||||
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
|
|
||||||
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
|
|
||||||
io.dec_csr_ren_d := decode.io.dec_csr_ren_d
|
|
||||||
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
|
||||||
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
|
||||||
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
|
||||||
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
|
||||||
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
|
||||||
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
|
||||||
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
|
||||||
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
|
||||||
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
|
||||||
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
|
||||||
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
|
||||||
io.pred_correct_npc_x := decode.io.pred_correct_npc_x
|
|
||||||
io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d
|
|
||||||
io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d
|
|
||||||
io.i0_predict_index_d := decode.io.i0_predict_index_d
|
|
||||||
io.i0_predict_btag_d := decode.io.i0_predict_btag_d
|
|
||||||
io.dec_data_en := decode.io.dec_data_en
|
|
||||||
io.dec_ctl_en := decode.io.dec_ctl_en
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_instr_decoded
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_decode_stall
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_presync_stall
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_wen
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_waddr
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pause_state
|
|
||||||
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
|
|
||||||
tlu.io.dec_div_active := decode.io.dec_div_active
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
|
|
||||||
//connections for gprfile
|
|
||||||
// gpr.io <> io
|
|
||||||
//inputs
|
|
||||||
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
|
||||||
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
|
||||||
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
|
||||||
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
|
||||||
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
|
||||||
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
|
|
||||||
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
|
|
||||||
gpr.io.wd1 := io.lsu_nonblock_load_data
|
|
||||||
gpr.io.wen2 := io.exu_div_wren
|
|
||||||
gpr.io.waddr2 := decode.io.div_waddr_wb
|
|
||||||
gpr.io.wd2 := io.exu_div_result
|
|
||||||
//gpr.io.clk := io.clk
|
|
||||||
//gpr.io.rst_l := io.rst_l
|
|
||||||
gpr.io.scan_mode := io.scan_mode
|
|
||||||
// outputs
|
|
||||||
io.gpr_i0_rs1_d := gpr.io.rd0
|
|
||||||
io.gpr_i0_rs2_d := gpr.io.rd1
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//connection for dec_tlu
|
|
||||||
// tlu.io <> io
|
|
||||||
//inputs
|
|
||||||
//tlu.io.clk := io.clk
|
|
||||||
tlu.io.active_clk := io.active_clk
|
|
||||||
tlu.io.free_clk := io.free_clk
|
|
||||||
// tlu.io.rst_l := io.rst_l
|
|
||||||
tlu.io.scan_mode := io.scan_mode
|
|
||||||
tlu.io.rst_vec := io.rst_vec
|
|
||||||
tlu.io.nmi_int := io.nmi_int
|
|
||||||
tlu.io.nmi_vec := io.nmi_vec
|
|
||||||
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
|
|
||||||
tlu.io.i_cpu_run_req := io.i_cpu_run_req
|
|
||||||
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
|
|
||||||
tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned
|
|
||||||
tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall
|
|
||||||
tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss
|
|
||||||
tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit
|
|
||||||
tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error
|
|
||||||
tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy
|
|
||||||
tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn
|
|
||||||
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
|
|
||||||
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
|
|
||||||
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
|
|
||||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
|
||||||
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
|
|
||||||
tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
|
||||||
tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any
|
|
||||||
tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp
|
|
||||||
tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken
|
|
||||||
tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4
|
|
||||||
tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn
|
|
||||||
tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned
|
|
||||||
tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error
|
|
||||||
tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy
|
|
||||||
tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m
|
|
||||||
tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m
|
|
||||||
tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read
|
|
||||||
tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write
|
|
||||||
tlu.io.dma_pmu_any_read := io.dma_pmu_any_read
|
|
||||||
tlu.io.dma_pmu_any_write := io.dma_pmu_any_write
|
|
||||||
tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
|
||||||
tlu.io.lsu_fir_error := io.lsu_fir_error
|
|
||||||
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
|
||||||
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
|
||||||
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
|
||||||
tlu.io.dec_pause_state := decode.io.dec_pause_state
|
|
||||||
tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
|
|
||||||
tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any
|
|
||||||
tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any
|
|
||||||
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
|
||||||
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
|
||||||
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
|
||||||
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
|
||||||
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
|
||||||
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
|
||||||
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
|
||||||
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
|
||||||
tlu.io.exu_npc_r := io.exu_npc_r
|
|
||||||
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
|
||||||
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
|
||||||
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
|
||||||
tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d
|
|
||||||
tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r
|
|
||||||
tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r
|
|
||||||
tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r
|
|
||||||
tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r
|
|
||||||
tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r
|
|
||||||
tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r
|
|
||||||
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
|
|
||||||
tlu.io.dbg_halt_req := io.dbg_halt_req
|
|
||||||
tlu.io.dbg_resume_req := io.dbg_resume_req
|
|
||||||
tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle
|
|
||||||
tlu.io.lsu_idle_any := io.lsu_idle_any
|
|
||||||
tlu.io.dec_div_active := decode.io.dec_div_active
|
|
||||||
tlu.io.ifu_ic_error_start := io.ifu_ic_error_start
|
|
||||||
tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err
|
|
||||||
tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data
|
|
||||||
tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid
|
|
||||||
tlu.io.pic_claimid := io.pic_claimid
|
|
||||||
tlu.io.pic_pl := io.pic_pl
|
|
||||||
tlu.io.mhwakeup := io.mhwakeup
|
|
||||||
tlu.io.mexintpend := io.mexintpend
|
|
||||||
tlu.io.timer_int := io.timer_int
|
|
||||||
tlu.io.soft_int := io.soft_int
|
|
||||||
tlu.io.core_id := io.core_id
|
|
||||||
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
|
||||||
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
|
|
||||||
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
|
|
||||||
//outputs
|
|
||||||
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
|
|
||||||
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
|
|
||||||
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
|
|
||||||
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
|
|
||||||
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
|
|
||||||
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
|
||||||
io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r
|
|
||||||
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
|
|
||||||
io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
|
|
||||||
io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r
|
|
||||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
|
||||||
io.dec_tlu_meihap := tlu.io.dec_tlu_meihap
|
|
||||||
io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
|
||||||
io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt
|
|
||||||
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
|
||||||
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
|
||||||
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
|
||||||
io.o_debug_mode_status := tlu.io.o_debug_mode_status
|
|
||||||
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
|
|
||||||
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
|
|
||||||
io.debug_brkpt_status := tlu.io.debug_brkpt_status
|
|
||||||
io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
|
|
||||||
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
|
|
||||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
|
||||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
|
||||||
io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt
|
|
||||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
|
||||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
|
||||||
io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt
|
|
||||||
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
|
||||||
io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
|
|
||||||
io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r
|
|
||||||
io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r
|
|
||||||
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
|
||||||
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
|
||||||
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
|
||||||
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
|
||||||
io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff
|
|
||||||
io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
|
|
||||||
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
|
|
||||||
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
|
|
||||||
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
|
|
||||||
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
|
|
||||||
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
|
|
||||||
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
|
|
||||||
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
|
|
||||||
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
|
|
||||||
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
|
|
||||||
io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable
|
|
||||||
io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable
|
|
||||||
io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable
|
|
||||||
io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable
|
|
||||||
io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable
|
|
||||||
// := tlu.io.dec_tlu_pipelining_disable
|
|
||||||
io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty
|
|
||||||
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
|
|
||||||
//decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
|
||||||
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
|
|
||||||
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
|
|
||||||
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
|
|
||||||
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
|
|
||||||
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
|
|
||||||
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
|
|
||||||
|
|
||||||
//--------------------------------------------------------------------------//
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// debug command read data
|
|
||||||
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
|
||||||
}
|
|
||||||
object dec_main extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec()))
|
|
||||||
}
|
|
|
@ -1,173 +0,0 @@
|
||||||
package dec
|
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
|
|
||||||
class el2_dec_pkt_t extends Bundle{
|
|
||||||
val alu = Bool()
|
|
||||||
val rs1 = Bool()
|
|
||||||
val rs2 = Bool()
|
|
||||||
val imm12 = Bool()
|
|
||||||
val rd = Bool()
|
|
||||||
val shimm5 = Bool()
|
|
||||||
val imm20 = Bool()
|
|
||||||
val pc = Bool()
|
|
||||||
val load = Bool()
|
|
||||||
val store = Bool()
|
|
||||||
val lsu = Bool()
|
|
||||||
val add = Bool()
|
|
||||||
val sub = Bool()
|
|
||||||
val land = Bool()
|
|
||||||
val lor = Bool()
|
|
||||||
val lxor = Bool()
|
|
||||||
val sll = Bool()
|
|
||||||
val sra = Bool()
|
|
||||||
val srl = Bool()
|
|
||||||
val slt = Bool()
|
|
||||||
val unsign = Bool()
|
|
||||||
val condbr = Bool()
|
|
||||||
val beq = Bool()
|
|
||||||
val bne = Bool()
|
|
||||||
val bge = Bool()
|
|
||||||
val blt = Bool()
|
|
||||||
val jal = Bool()
|
|
||||||
val by = Bool()
|
|
||||||
val half = Bool()
|
|
||||||
val word = Bool()
|
|
||||||
val csr_read = Bool()
|
|
||||||
val csr_clr = Bool()
|
|
||||||
val csr_set = Bool()
|
|
||||||
val csr_write = Bool()
|
|
||||||
val csr_imm = Bool()
|
|
||||||
val presync = Bool()
|
|
||||||
val postsync = Bool()
|
|
||||||
val ebreak = Bool()
|
|
||||||
val ecall = Bool()
|
|
||||||
val mret = Bool()
|
|
||||||
val mul = Bool()
|
|
||||||
val rs1_sign = Bool()
|
|
||||||
val rs2_sign = Bool()
|
|
||||||
val low = Bool()
|
|
||||||
val div = Bool()
|
|
||||||
val rem = Bool()
|
|
||||||
val fence = Bool()
|
|
||||||
val fence_i = Bool()
|
|
||||||
val pm_alu = Bool()
|
|
||||||
val legal = Bool()
|
|
||||||
}
|
|
||||||
|
|
||||||
class el2_dec_dec_ctl extends Module{
|
|
||||||
val io = IO (new Bundle{
|
|
||||||
val ins = Input(UInt(32.W))
|
|
||||||
val out = Output(new el2_dec_pkt_t)
|
|
||||||
})
|
|
||||||
|
|
||||||
def pattern(y : List[Int]) : Array[UInt] = {
|
|
||||||
val pat : Array[UInt] = new Array[UInt](y.size)
|
|
||||||
for (i <- 0 until y.size){
|
|
||||||
pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs)
|
|
||||||
}
|
|
||||||
pat
|
|
||||||
}
|
|
||||||
|
|
||||||
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
|
|
||||||
io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) |
|
|
||||||
pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) |
|
|
||||||
pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) |
|
|
||||||
pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) |
|
|
||||||
pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) |
|
|
||||||
pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_)
|
|
||||||
io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_)
|
|
||||||
io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) |
|
|
||||||
pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_)
|
|
||||||
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
|
|
||||||
io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_)
|
|
||||||
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
|
|
||||||
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
|
|
||||||
io.out.load := pattern(List(-5,-4,-2)).reduce(_&_)
|
|
||||||
io.out.store := pattern(List(-6,5,-4)).reduce(_&_)
|
|
||||||
io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) |
|
|
||||||
pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) |
|
|
||||||
pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_)
|
|
||||||
io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) |
|
|
||||||
pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(14,13,-12,-5,-2)).reduce(_&_)
|
|
||||||
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_)
|
|
||||||
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_)
|
|
||||||
io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) |
|
|
||||||
pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) |
|
|
||||||
pattern(List(25,14,12,-6,5,-2)).reduce(_&_)
|
|
||||||
io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_)
|
|
||||||
io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_)
|
|
||||||
io.out.jal := pattern(List(6,2)).reduce(_&_)
|
|
||||||
io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_)
|
|
||||||
io.out.word := pattern(List(13,-6,-4)).reduce(_&_)
|
|
||||||
io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(11,6,4)).reduce(_&_)
|
|
||||||
io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(19,-12,6,4)).reduce(_&_)
|
|
||||||
io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_)
|
|
||||||
io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_)
|
|
||||||
io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(19,-12,6,4)).reduce(_&_)
|
|
||||||
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_)
|
|
||||||
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_)
|
|
||||||
io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_)
|
|
||||||
io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_)
|
|
||||||
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) |
|
|
||||||
pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
|
|
||||||
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_)
|
|
||||||
io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_)
|
|
||||||
io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_)
|
|
||||||
io.out.fence := pattern(List(-5,3)).reduce(_&_)
|
|
||||||
io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_)
|
|
||||||
io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) |
|
|
||||||
pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_)
|
|
||||||
io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
|
|
||||||
io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
|
|
||||||
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
|
|
||||||
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) |
|
|
||||||
pattern(List(-6,4,-3,-2,1,0)).reduce(_&_)
|
|
||||||
}
|
|
||||||
|
|
||||||
//object dec extends App {
|
|
||||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl()))
|
|
||||||
//}
|
|
|
@ -1,58 +0,0 @@
|
||||||
package dec
|
|
||||||
import chisel3._
|
|
||||||
import scala.collection._
|
|
||||||
import chisel3.util._
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib {
|
|
||||||
val io =IO(new el2_dec_gpr_ctl_IO)
|
|
||||||
val w0v =Wire(Vec(32,UInt(1.W)))
|
|
||||||
val w1v =Wire(Vec(32,UInt(1.W)))
|
|
||||||
val w2v =Wire(Vec(32,UInt(1.W)))
|
|
||||||
val gpr_in =Wire(Vec(32,UInt(32.W)))
|
|
||||||
val gpr_out =Wire(Vec(32,UInt(32.W)))
|
|
||||||
val gpr_wr_en =Wire(UInt(32.W))
|
|
||||||
w0v(0):=0.U
|
|
||||||
w1v(0):=0.U
|
|
||||||
w2v(0):=0.U
|
|
||||||
gpr_out(0):=0.U
|
|
||||||
gpr_in(0):=0.U
|
|
||||||
io.rd0:=0.U
|
|
||||||
io.rd1:=0.U
|
|
||||||
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
|
|
||||||
// GPR Write logic
|
|
||||||
for (j <-1 until 32){
|
|
||||||
w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
|
|
||||||
w1v(j) := io.wen1 & (io.waddr1===j.asUInt)
|
|
||||||
w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
|
|
||||||
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
|
|
||||||
}
|
|
||||||
// GPR Write Enables for power savings
|
|
||||||
for (j <-1 until 32){
|
|
||||||
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
|
|
||||||
}
|
|
||||||
// GPR Read logic
|
|
||||||
io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i)))
|
|
||||||
io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i)))
|
|
||||||
}
|
|
||||||
|
|
||||||
class el2_dec_gpr_ctl_IO extends Bundle{
|
|
||||||
val raddr0=Input(UInt(5.W)) // logical read addresses
|
|
||||||
val raddr1=Input(UInt(5.W))
|
|
||||||
val wen0=Input(UInt(1.W)) // write enable
|
|
||||||
val waddr0=Input(UInt(5.W)) // write address
|
|
||||||
val wd0=Input(UInt(32.W)) // write data
|
|
||||||
val wen1=Input(UInt(1.W)) // write enable
|
|
||||||
val waddr1=Input(UInt(5.W)) // write address
|
|
||||||
val wd1=Input(UInt(32.W)) // write data
|
|
||||||
val wen2=Input(UInt(1.W)) // write enable
|
|
||||||
val waddr2=Input(UInt(5.W)) // write address
|
|
||||||
val wd2=Input(UInt(32.W)) // write data
|
|
||||||
val rd0=Output(UInt(32.W)) // read data
|
|
||||||
val rd1=Output(UInt(32.W))
|
|
||||||
val scan_mode=Input(Bool())
|
|
||||||
}
|
|
||||||
object gpr_gen extends App{
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl)))
|
|
||||||
}
|
|
|
@ -1,99 +0,0 @@
|
||||||
package dec
|
|
||||||
import include._
|
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_dec_ib_ctl_IO extends Bundle with param{
|
|
||||||
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
|
|
||||||
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
|
|
||||||
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
|
|
||||||
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
|
|
||||||
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
|
|
||||||
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
|
|
||||||
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
|
|
||||||
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
|
|
||||||
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
|
|
||||||
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
|
|
||||||
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
|
|
||||||
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
|
|
||||||
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
|
|
||||||
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
|
|
||||||
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
|
|
||||||
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
|
|
||||||
|
|
||||||
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
|
|
||||||
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
|
|
||||||
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
|
||||||
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
|
|
||||||
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
|
|
||||||
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
|
|
||||||
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
|
||||||
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
|
||||||
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
|
||||||
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
|
|
||||||
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
|
|
||||||
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
|
|
||||||
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
|
|
||||||
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
|
|
||||||
}
|
|
||||||
|
|
||||||
class el2_dec_ib_ctl extends Module with param{
|
|
||||||
val io=IO(new el2_dec_ib_ctl_IO)
|
|
||||||
io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1
|
|
||||||
io.dec_i0_dbecc_d :=io.ifu_i0_dbecc
|
|
||||||
io.dec_i0_icaf_d :=io.ifu_i0_icaf
|
|
||||||
io.dec_i0_pc_d :=io.ifu_i0_pc
|
|
||||||
io.dec_i0_pc4_d :=io.ifu_i0_pc4
|
|
||||||
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type
|
|
||||||
io.dec_i0_brp :=io.i0_brp
|
|
||||||
io.dec_i0_bp_index :=io.ifu_i0_bp_index
|
|
||||||
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr
|
|
||||||
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag
|
|
||||||
|
|
||||||
// GPR accesses
|
|
||||||
// put reg to read on rs1
|
|
||||||
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
|
|
||||||
// put write date on rs1
|
|
||||||
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
|
|
||||||
// CSR accesses
|
|
||||||
// csr is of form rd, csr, rs1
|
|
||||||
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
|
|
||||||
// put write data on rs1
|
|
||||||
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
|
|
||||||
|
|
||||||
|
|
||||||
val debug_valid =io.dbg_cmd_valid & (io.dbg_cmd_type =/= 2.U)
|
|
||||||
val debug_read =debug_valid & !io.dbg_cmd_write
|
|
||||||
val debug_write =debug_valid & io.dbg_cmd_write
|
|
||||||
|
|
||||||
val debug_read_gpr = debug_read & (io.dbg_cmd_type===0.U)
|
|
||||||
val debug_write_gpr = debug_write & (io.dbg_cmd_type===0.U)
|
|
||||||
val debug_read_csr = debug_read & (io.dbg_cmd_type===1.U)
|
|
||||||
val debug_write_csr = debug_write & (io.dbg_cmd_type===1.U)
|
|
||||||
|
|
||||||
val dreg = io.dbg_cmd_addr(4,0)
|
|
||||||
val dcsr = io.dbg_cmd_addr(11,0)
|
|
||||||
|
|
||||||
val ib0_debug_in =Mux1H(Seq(
|
|
||||||
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
|
|
||||||
debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)),
|
|
||||||
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)),
|
|
||||||
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W))
|
|
||||||
))
|
|
||||||
|
|
||||||
// machine is in halted state, pipe empty, write will always happen next cycle
|
|
||||||
io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr
|
|
||||||
|
|
||||||
// special fence csr for use only in debug mode
|
|
||||||
io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U)
|
|
||||||
|
|
||||||
io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid
|
|
||||||
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr)
|
|
||||||
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
object ib_gen extends App{
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl)))
|
|
||||||
}
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,89 +1,39 @@
|
||||||
|
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import chisel3.util._
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import dbg._
|
||||||
import scala.collection._
|
import scala.collection._
|
||||||
import lib._
|
import lib._
|
||||||
|
|
||||||
class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
class dma_ctrl extends Module with lib with RequireAsyncReset {
|
||||||
val io = IO(new Bundle {
|
val io = IO(new Bundle {
|
||||||
val free_clk = Input(Clock())
|
val free_clk = Input(Clock())
|
||||||
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
||||||
val clk_override = Input(Bool())
|
val clk_override = Input(Bool())
|
||||||
val scan_mode = Input(Bool())
|
val scan_mode = Input(Bool())
|
||||||
|
|
||||||
// Debug signals
|
|
||||||
val dbg_cmd_addr = Input(UInt(32.W))
|
|
||||||
val dbg_cmd_wrdata = Input(UInt(32.W))
|
|
||||||
val dbg_cmd_valid = Input(Bool())
|
|
||||||
val dbg_cmd_write = Input(Bool()) // 1: write command, 0: read_command
|
|
||||||
val dbg_cmd_type = Input(UInt(2.W)) // 0:gpr 1:csr 2: memory
|
|
||||||
val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
|
val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
|
||||||
|
val dma_dbg_rddata = Output(UInt(32.W))
|
||||||
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
|
|
||||||
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
|
|
||||||
val dma_dbg_cmd_done = Output(Bool())
|
val dma_dbg_cmd_done = Output(Bool())
|
||||||
val dma_dbg_cmd_fail = Output(Bool())
|
val dma_dbg_cmd_fail = Output(Bool())
|
||||||
val dma_dbg_rddata = Output(UInt(32.W))
|
val dbg_dma = new dec_dbg()
|
||||||
|
val dbg_dma_io = new dbg_dma()
|
||||||
// Core side signals
|
|
||||||
val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set)
|
|
||||||
val dma_iccm_req = Output(Bool()) // DMA iccm request
|
|
||||||
val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number
|
|
||||||
val dma_mem_addr = Output(UInt(32.W))// DMA request address
|
|
||||||
val dma_mem_sz = Output(UInt(3.W)) // DMA request size
|
|
||||||
val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm
|
|
||||||
val dma_mem_wdata = Output(UInt(64.W))// DMA write data
|
|
||||||
val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read
|
|
||||||
val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
|
||||||
val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
|
||||||
val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read
|
|
||||||
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
|
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
|
||||||
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
||||||
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
||||||
val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
|
val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
|
||||||
|
|
||||||
val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed
|
val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed
|
||||||
val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed
|
|
||||||
val dccm_ready = Input(Bool()) // dccm ready to accept DMA request
|
|
||||||
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
|
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
|
||||||
val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15]
|
val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15]
|
||||||
|
|
||||||
// PMU signals
|
// PMU signals
|
||||||
val dma_pmu_dccm_read = Output(Bool())
|
val dma_pmu_dccm_read = Output(Bool())
|
||||||
val dma_pmu_dccm_write = Output(Bool())
|
val dma_pmu_dccm_write = Output(Bool())
|
||||||
val dma_pmu_any_read = Output(Bool())
|
val dma_pmu_any_read = Output(Bool())
|
||||||
val dma_pmu_any_write = Output(Bool())
|
val dma_pmu_any_write = Output(Bool())
|
||||||
|
|
||||||
// AXI Write Channels
|
// AXI Write Channels
|
||||||
val dma_axi_awvalid = Input(Bool())
|
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||||
val dma_axi_awready = Output(Bool())
|
val lsu_dma = Flipped(new lsu_dma)
|
||||||
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
|
val ifu_dma = Flipped(new ifu_dma)
|
||||||
val dma_axi_awaddr = Input(UInt(32.W))
|
|
||||||
val dma_axi_awsize = Input(UInt(3.W))
|
|
||||||
|
|
||||||
val dma_axi_wvalid = Input(Bool())
|
|
||||||
val dma_axi_wready = Output(Bool())
|
|
||||||
val dma_axi_wdata = Input(UInt(64.W))
|
|
||||||
val dma_axi_wstrb = Input(UInt(8.W))
|
|
||||||
|
|
||||||
val dma_axi_bvalid = Output(Bool())
|
|
||||||
val dma_axi_bready = Input(Bool())
|
|
||||||
val dma_axi_bresp = Output(UInt(2.W))
|
|
||||||
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
|
|
||||||
|
|
||||||
// AXI Read Channels
|
|
||||||
val dma_axi_arvalid = Input(Bool())
|
|
||||||
val dma_axi_arready = Output(Bool())
|
|
||||||
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
|
|
||||||
|
|
||||||
val dma_axi_araddr = Input(UInt(32.W))
|
|
||||||
val dma_axi_arsize = Input(UInt(3.W))
|
|
||||||
|
|
||||||
val dma_axi_rvalid = Output(Bool())
|
|
||||||
val dma_axi_rready = Input(Bool())
|
|
||||||
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
|
|
||||||
val dma_axi_rdata = Output(UInt(64.W))
|
|
||||||
val dma_axi_rresp = Output(UInt(2.W))
|
|
||||||
val dma_axi_rlast = Output(Bool())
|
|
||||||
})
|
})
|
||||||
|
|
||||||
|
|
||||||
|
@ -234,50 +184,50 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
|
||||||
// DCCM Address check
|
// DCCM Address check
|
||||||
|
|
||||||
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE)
|
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)
|
||||||
|
|
||||||
// PIC memory address check
|
// PIC memory address check
|
||||||
|
|
||||||
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
|
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)
|
||||||
|
|
||||||
// ICCM Address check
|
// ICCM Address check
|
||||||
|
|
||||||
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U)
|
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE) else (0.U,0.U)
|
||||||
|
|
||||||
// FIFO inputs
|
// FIFO inputs
|
||||||
|
|
||||||
val fifo_addr_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
|
val fifo_addr_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
|
||||||
|
|
||||||
fifo_byteen_in := Mux(io.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
|
fifo_byteen_in := Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_dma.dbg_ib.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
|
||||||
|
|
||||||
val fifo_sz_in = Mux(io.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
|
val fifo_sz_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
|
||||||
|
|
||||||
val fifo_write_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_write, bus_cmd_write)
|
val fifo_write_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write)
|
||||||
|
|
||||||
val fifo_posted_write_in = !io.dbg_cmd_valid & bus_cmd_posted_write
|
val fifo_posted_write_in = !io.dbg_dma.dbg_ib.dbg_cmd_valid & bus_cmd_posted_write
|
||||||
|
|
||||||
val fifo_dbg_in = io.dbg_cmd_valid
|
val fifo_dbg_in = io.dbg_dma.dbg_ib.dbg_cmd_valid
|
||||||
|
|
||||||
|
|
||||||
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
|
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1) & io.dbg_dma.dbg_ib.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
||||||
|
|
||||||
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
|
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, Fill(2, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
|
||||||
|
|
||||||
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
@ -321,7 +271,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
|
||||||
val WrPtrEn = fifo_cmd_en.orR
|
val WrPtrEn = fifo_cmd_en.orR
|
||||||
|
|
||||||
val RdPtrEn = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
|
val RdPtrEn = (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
|
||||||
|
|
||||||
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
||||||
|
|
||||||
|
@ -362,16 +312,17 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
||||||
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
||||||
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
||||||
(dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
(dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
||||||
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
||||||
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
||||||
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
||||||
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
|
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
|
||||||
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
||||||
|
|
||||||
|
|
||||||
//Dbg outputs
|
//Dbg outputs
|
||||||
|
|
||||||
io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
|
io.dbg_dma_io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
|
||||||
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
||||||
io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
|
io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
|
||||||
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
||||||
|
@ -381,7 +332,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
// Block the decode if fifo full
|
// Block the decode if fifo full
|
||||||
|
|
||||||
io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
||||||
io.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
|
io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
|
||||||
|
|
||||||
// Used to indicate ready to debug
|
// Used to indicate ready to debug
|
||||||
|
|
||||||
|
@ -390,7 +341,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
// Nack counter, stall the lsu pipe if 7 nacks
|
// Nack counter, stall the lsu pipe if 7 nacks
|
||||||
|
|
||||||
dma_nack_count_csr := io.dec_tlu_dma_qos_prty
|
dma_nack_count_csr := io.dec_tlu_dma_qos_prty
|
||||||
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
|
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
|
||||||
|
|
||||||
dma_nack_count := withClock(dma_free_clk) {
|
dma_nack_count := withClock(dma_free_clk) {
|
||||||
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
|
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
|
||||||
|
@ -399,23 +350,23 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
// Core outputs
|
// Core outputs
|
||||||
|
|
||||||
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||||
io.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready;
|
io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready
|
||||||
io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
|
io.ifu_dma.dma_mem_ctl.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
|
||||||
io.dma_mem_tag := RdPtr
|
io.lsu_dma.dma_mem_tag := RdPtr
|
||||||
dma_mem_addr_int := fifo_addr(RdPtr)
|
dma_mem_addr_int := fifo_addr(RdPtr)
|
||||||
dma_mem_sz_int := fifo_sz(RdPtr)
|
dma_mem_sz_int := fifo_sz(RdPtr)
|
||||||
io.dma_mem_addr := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
|
io.lsu_dma.dma_lsc_ctl.dma_mem_addr := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
|
||||||
io.dma_mem_sz := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
|
io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
|
||||||
dma_mem_byteen := fifo_byteen(RdPtr)
|
dma_mem_byteen := fifo_byteen(RdPtr)
|
||||||
io.dma_mem_write := fifo_write(RdPtr)
|
io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
|
||||||
io.dma_mem_wdata := fifo_data(RdPtr)
|
io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := fifo_data(RdPtr)
|
||||||
|
|
||||||
// PMU outputs
|
// PMU outputs
|
||||||
|
|
||||||
io.dma_pmu_dccm_read := io.dma_dccm_req & !io.dma_mem_write;
|
io.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||||
io.dma_pmu_dccm_write := io.dma_dccm_req & io.dma_mem_write;
|
io.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||||
io.dma_pmu_any_read := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write;
|
io.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||||
io.dma_pmu_any_write := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write;
|
io.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||||
|
|
||||||
// Inputs
|
// Inputs
|
||||||
|
|
||||||
|
@ -424,7 +375,7 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
}
|
}
|
||||||
|
|
||||||
dbg_dma_bubble_bus := withClock(dma_bus_clk) {
|
dbg_dma_bubble_bus := withClock(dma_bus_clk) {
|
||||||
RegNext(io.dbg_dma_bubble, 0.U)
|
RegNext(io.dbg_dma_io.dbg_dma_bubble, 0.U)
|
||||||
}
|
}
|
||||||
|
|
||||||
dma_dbg_cmd_done_q := withClock(io.free_clk) {
|
dma_dbg_cmd_done_q := withClock(io.free_clk) {
|
||||||
|
@ -433,8 +384,8 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
|
||||||
// Clock Gating logic
|
// Clock Gating logic
|
||||||
|
|
||||||
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_cmd_valid | io.clk_override
|
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||||
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||||
|
|
||||||
val dma_buffer_c1cgc = Module(new rvclkhdr)
|
val dma_buffer_c1cgc = Module(new rvclkhdr)
|
||||||
dma_buffer_c1cgc.io.en := dma_buffer_c1_clken
|
dma_buffer_c1cgc.io.en := dma_buffer_c1_clken
|
||||||
|
@ -456,8 +407,8 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
|
||||||
// Write channel buffer
|
// Write channel buffer
|
||||||
|
|
||||||
val wrbuf_en = io.dma_axi_awvalid & io.dma_axi_awready
|
val wrbuf_en = io.dma_axi.aw.valid & io.dma_axi.aw.ready
|
||||||
val wrbuf_data_en = io.dma_axi_wvalid & io.dma_axi_wready
|
val wrbuf_data_en = io.dma_axi.w.valid & io.dma_axi.w.ready
|
||||||
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
||||||
val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
|
val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
|
||||||
val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
|
val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
|
||||||
|
@ -467,42 +418,42 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
|
wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
|
||||||
|
|
||||||
val wrbuf_tag = withClock(dma_bus_clk) {
|
val wrbuf_tag = withClock(dma_bus_clk) {
|
||||||
RegEnable(io.dma_axi_awid, 0.U, wrbuf_en)
|
RegEnable(io.dma_axi.aw.bits.id, 0.U, wrbuf_en)
|
||||||
}
|
}
|
||||||
|
|
||||||
val wrbuf_sz = withClock(dma_bus_clk) {
|
val wrbuf_sz = withClock(dma_bus_clk) {
|
||||||
RegEnable(io.dma_axi_awsize, 0.U, wrbuf_en)
|
RegEnable(io.dma_axi.aw.bits.size, 0.U, wrbuf_en)
|
||||||
}
|
}
|
||||||
|
|
||||||
val wrbuf_addr = rvdffe(io.dma_axi_awaddr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
val wrbuf_addr = rvdffe(io.dma_axi.aw.bits.addr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||||
|
|
||||||
val wrbuf_data = rvdffe(io.dma_axi_wdata, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
val wrbuf_data = rvdffe(io.dma_axi.w.bits.data, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||||
|
|
||||||
val wrbuf_byteen = withClock(dma_bus_clk) {
|
val wrbuf_byteen = withClock(dma_bus_clk) {
|
||||||
RegEnable(io.dma_axi_wstrb, 0.U, wrbuf_data_en)
|
RegEnable(io.dma_axi.w.bits.strb, 0.U, wrbuf_data_en)
|
||||||
}
|
}
|
||||||
|
|
||||||
// Read channel buffer
|
// Read channel buffer
|
||||||
|
|
||||||
val rdbuf_en = io.dma_axi_arvalid & io.dma_axi_arready
|
val rdbuf_en = io.dma_axi.ar.valid & io.dma_axi.ar.ready
|
||||||
val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
|
val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
|
||||||
val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
|
val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
|
||||||
|
|
||||||
rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
|
rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
|
||||||
|
|
||||||
val rdbuf_tag = withClock(dma_bus_clk) {
|
val rdbuf_tag = withClock(dma_bus_clk) {
|
||||||
RegEnable(io.dma_axi_arid, 0.U, rdbuf_en)
|
RegEnable(io.dma_axi.ar.bits.id, 0.U, rdbuf_en)
|
||||||
}
|
}
|
||||||
|
|
||||||
val rdbuf_sz = withClock(dma_bus_clk) {
|
val rdbuf_sz = withClock(dma_bus_clk) {
|
||||||
RegEnable(io.dma_axi_arsize, 0.U, rdbuf_en)
|
RegEnable(io.dma_axi.ar.bits.size, 0.U, rdbuf_en)
|
||||||
}
|
}
|
||||||
|
|
||||||
val rdbuf_addr = rvdffe(io.dma_axi_araddr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
val rdbuf_addr = rvdffe(io.dma_axi.ar.bits.addr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||||
|
|
||||||
io.dma_axi_awready := ~(wrbuf_vld & !wrbuf_cmd_sent)
|
io.dma_axi.aw.ready := ~(wrbuf_vld & !wrbuf_cmd_sent)
|
||||||
io.dma_axi_wready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
|
io.dma_axi.w.ready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
|
||||||
io.dma_axi_arready := ~(rdbuf_vld & !rdbuf_cmd_sent)
|
io.dma_axi.ar.ready := ~(rdbuf_vld & !rdbuf_cmd_sent)
|
||||||
|
|
||||||
//Generate a single request from read/write channel
|
//Generate a single request from read/write channel
|
||||||
|
|
||||||
|
@ -537,20 +488,24 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
|
||||||
// AXI response channel signals
|
// AXI response channel signals
|
||||||
|
|
||||||
io.dma_axi_bvalid := axi_rsp_valid & axi_rsp_write
|
io.dma_axi.b.valid := axi_rsp_valid & axi_rsp_write
|
||||||
io.dma_axi_bresp := axi_rsp_error(1,0)
|
io.dma_axi.b.bits.resp := axi_rsp_error(1,0)
|
||||||
io.dma_axi_bid := axi_rsp_tag
|
io.dma_axi.b.bits.id := axi_rsp_tag
|
||||||
|
|
||||||
io.dma_axi_rvalid := axi_rsp_valid & !axi_rsp_write
|
io.dma_axi.r.valid := axi_rsp_valid & !axi_rsp_write
|
||||||
io.dma_axi_rresp := axi_rsp_error
|
io.dma_axi.r.bits.resp := axi_rsp_error
|
||||||
io.dma_axi_rdata := axi_rsp_rdata(63,0)
|
io.dma_axi.r.bits.data := axi_rsp_rdata(63,0)
|
||||||
io.dma_axi_rlast := 1.U
|
io.dma_axi.r.bits.last := 1.U
|
||||||
io.dma_axi_rid := axi_rsp_tag
|
io.dma_axi.r.bits.id := axi_rsp_tag
|
||||||
|
|
||||||
bus_posted_write_done := 0.U
|
bus_posted_write_done := 0.U
|
||||||
bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid)
|
bus_rsp_valid := (io.dma_axi.b.valid | io.dma_axi.r.valid)
|
||||||
bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
|
bus_rsp_sent := ((io.dma_axi.b.valid & io.dma_axi.b.ready) | (io.dma_axi.r.valid & io.dma_axi.r.ready))
|
||||||
|
io.lsu_dma.dma_dccm_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||||
|
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||||
|
io.ifu_dma.dma_mem_ctl.dma_mem_sz := io.lsu_dma.dma_lsc_ctl.dma_mem_sz
|
||||||
|
io.ifu_dma.dma_mem_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||||
|
io.ifu_dma.dma_mem_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||||
|
io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||||
|
io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||||
}
|
}
|
||||||
object dma extends App{
|
|
||||||
chisel3.Driver.emitVerilog(new el2_dma_ctrl)
|
|
||||||
}
|
|
|
@ -1,44 +1,48 @@
|
||||||
package dmi
|
package dmi
|
||||||
import chisel3._
|
import chisel3._
|
||||||
import lib._
|
import chisel3.util._
|
||||||
|
import lib._
|
||||||
class dmi_wrapper extends Module with el2_lib {
|
|
||||||
val io = IO(new Bundle{
|
class dmi_wrapper extends BlackBox with HasBlackBoxResource{
|
||||||
val trst_n = Input(Bool())
|
val io = IO(new Bundle{
|
||||||
val tck = Input(Clock())
|
val trst_n = Input(Bool())
|
||||||
val tms = Input(UInt(1.W))
|
val tck = Input(Clock())
|
||||||
val tdi = Input(UInt(1.W))
|
val tms = Input(UInt(1.W))
|
||||||
val tdo = Output(UInt(1.W))
|
val tdi = Input(UInt(1.W))
|
||||||
val tdoEnable = Output(UInt(1.W))
|
val tdo = Output(UInt(1.W))
|
||||||
val core_rst_n = Input(AsyncReset())
|
val tdoEnable = Output(UInt(1.W))
|
||||||
val core_clk = Input(Clock())
|
val core_rst_n = Input(AsyncReset())
|
||||||
val jtag_id = Input(UInt(32.W))
|
val core_clk = Input(Clock())
|
||||||
val rd_data = Input(UInt(32.W))
|
val jtag_id = Input(UInt(31.W))
|
||||||
val reg_wr_data = Output(UInt(32.W))
|
val rd_data = Input(UInt(32.W))
|
||||||
val reg_wr_addr = Output(UInt(7.W))
|
val reg_wr_data = Output(UInt(32.W))
|
||||||
val reg_en = Output(UInt(1.W))
|
val reg_wr_addr = Output(UInt(7.W))
|
||||||
val reg_wr_en = Output(UInt(1.W))
|
val reg_en = Output(UInt(1.W))
|
||||||
val dmi_hard_reset = Output(UInt(1.W))
|
val reg_wr_en = Output(UInt(1.W))
|
||||||
})
|
val dmi_hard_reset = Output(UInt(1.W))
|
||||||
val dwrap = {Module(new dmi_wrapper)}
|
})
|
||||||
|
addResource("/vsrc/dmi_wrapper.sv")
|
||||||
dwrap.io.trst_n := io.trst_n
|
}
|
||||||
dwrap.io.tck := io.tck
|
class dmi_wrapper_module extends Module{
|
||||||
dwrap.io.tms := io.tms
|
val io = IO(new Bundle{
|
||||||
dwrap.io.tdi := io.tdi
|
val trst_n = Input(Bool())
|
||||||
io.tdo := dwrap.io.tdo
|
val tck = Input(Clock())
|
||||||
io.tdoEnable := dwrap.io.tdoEnable
|
val tms = Input(UInt(1.W))
|
||||||
dwrap.io.core_rst_n := io.core_rst_n
|
val tdi = Input(UInt(1.W))
|
||||||
dwrap.io.core_clk := io.core_clk
|
val tdo = Output(UInt(1.W))
|
||||||
dwrap.io.jtag_id := io.jtag_id
|
val tdoEnable = Output(UInt(1.W))
|
||||||
dwrap.io.rd_data := io.rd_data
|
val core_rst_n = Input(AsyncReset())
|
||||||
io.reg_wr_data := dwrap.io.reg_wr_data
|
val core_clk = Input(Clock())
|
||||||
io.reg_wr_addr := dwrap.io.reg_wr_addr
|
val jtag_id = Input(UInt(32.W))
|
||||||
io.reg_en := dwrap.io.reg_en
|
val rd_data = Input(UInt(32.W))
|
||||||
io.reg_wr_en := dwrap.io.reg_wr_en
|
val reg_wr_data = Output(UInt(32.W))
|
||||||
io.dmi_hard_reset := dwrap.io.dmi_hard_reset
|
val reg_wr_addr = Output(UInt(7.W))
|
||||||
}
|
val reg_en = Output(UInt(1.W))
|
||||||
object dmiwrapper_main extends App{
|
val reg_wr_en = Output(UInt(1.W))
|
||||||
println("Generate Verilog")
|
val dmi_hard_reset = Output(UInt(1.W))
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
|
})
|
||||||
}
|
//addResource("/vsrc/dmi_wrapper.v")
|
||||||
|
val dwrap = Module(new dmi_wrapper)
|
||||||
|
dwrap.io <> io
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,351 +0,0 @@
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
|
|
||||||
val io = IO (new Bundle {
|
|
||||||
val scan_mode = Input(Bool())
|
|
||||||
val free_clk = Input(Clock () )
|
|
||||||
val active_clk = Input(Clock () )
|
|
||||||
val clk_override = Input(Bool () )
|
|
||||||
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
|
|
||||||
val picm_rdaddr = Input(UInt(32.W))
|
|
||||||
val picm_wraddr = Input(UInt(32.W))
|
|
||||||
val picm_wr_data = Input(UInt(32.W))
|
|
||||||
val picm_wren = Input(Bool())
|
|
||||||
val picm_rden = Input(Bool())
|
|
||||||
val picm_mken = Input(Bool())
|
|
||||||
val meicurpl = Input(UInt(4.W))
|
|
||||||
val meipt = Input(UInt(4.W))
|
|
||||||
|
|
||||||
val mexintpend = Output(Bool())
|
|
||||||
val claimid = Output(UInt(8.W))
|
|
||||||
val pl = Output(UInt(4.W))
|
|
||||||
val picm_rd_data = Output(UInt(32.W))
|
|
||||||
val mhwakeup = Output(Bool())
|
|
||||||
|
|
||||||
val test = Output(UInt())
|
|
||||||
})
|
|
||||||
|
|
||||||
io.mexintpend := 0.U
|
|
||||||
io.claimid := 0.U
|
|
||||||
io.pl := 0.U
|
|
||||||
io.picm_rd_data := 0.U
|
|
||||||
io.mhwakeup := 0.U
|
|
||||||
|
|
||||||
val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1)
|
|
||||||
val INTPRIORITY_BASE_ADDR = PIC_BASE_ADDR.U
|
|
||||||
val INTPEND_BASE_ADDR = (PIC_BASE_ADDR + 0x00001000L).U
|
|
||||||
val INTENABLE_BASE_ADDR = (PIC_BASE_ADDR + 0x00002000L).U
|
|
||||||
val EXT_INTR_PIC_CONFIG = (PIC_BASE_ADDR + 0x00003000L).U
|
|
||||||
val EXT_INTR_GW_CONFIG = (PIC_BASE_ADDR + 0x00004000L).U
|
|
||||||
val EXT_INTR_GW_CLEAR = (PIC_BASE_ADDR + 0x00005000L).U
|
|
||||||
|
|
||||||
val INTPEND_SIZE = PIC_TOTAL_INT_PLUS1 match {
|
|
||||||
case x if x < 32 => 32
|
|
||||||
case x if x < 64 => 64
|
|
||||||
case x if x < 128 => 128
|
|
||||||
case x if x < 256 => 256
|
|
||||||
case x if x < 512 => 512
|
|
||||||
case _ => 1024
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
val INT_GRPS = INTPEND_SIZE / 32
|
|
||||||
val INTPRIORITY_BITS = 4
|
|
||||||
val ID_BITS = 8
|
|
||||||
val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
|
|
||||||
|
|
||||||
// ---- Clock gating section ------
|
|
||||||
// c1 clock enables
|
|
||||||
val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override
|
|
||||||
val pic_data_c1_clken = io.picm_wren | io.clk_override
|
|
||||||
val waddr_intpriority_base_match = WireInit(Bool(), false.B)
|
|
||||||
val picm_wren_ff = WireInit(Bool(), false.B)
|
|
||||||
val raddr_intpriority_base_match = WireInit(Bool(), false.B)
|
|
||||||
val picm_rden_ff = WireInit(Bool(), false.B)
|
|
||||||
val raddr_intenable_base_match = WireInit(Bool(), false.B)
|
|
||||||
val waddr_config_gw_base_match = WireInit(Bool(), false.B)
|
|
||||||
val raddr_config_gw_base_match = WireInit(Bool(), false.B)
|
|
||||||
val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override
|
|
||||||
val pic_int_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override
|
|
||||||
val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
|
|
||||||
|
|
||||||
// C1 - 1 clock pulse for data
|
|
||||||
val pic_raddr_c1_clk = rvclkhdr(clock,pic_raddr_c1_clken,io.scan_mode)
|
|
||||||
val pic_data_c1_clk = rvclkhdr(clock,pic_data_c1_clken,io.scan_mode)
|
|
||||||
val pic_pri_c1_clk = rvclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode)
|
|
||||||
val pic_int_c1_clk = rvclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode)
|
|
||||||
val gw_config_c1_clk = rvclkhdr(clock,gw_config_c1_clken.asBool,io.scan_mode)
|
|
||||||
|
|
||||||
|
|
||||||
val picm_raddr_ff = WireInit(UInt(32.W), 0.U)
|
|
||||||
raddr_intenable_base_match := picm_raddr_ff(31,NUM_LEVELS+2)===INTENABLE_BASE_ADDR(31,NUM_LEVELS+2)//// (31,NUM_LEVELS+2)
|
|
||||||
io.test := INTENABLE_BASE_ADDR
|
|
||||||
|
|
||||||
val picm_waddr_ff = WireInit(UInt(32.W), 0.U)
|
|
||||||
raddr_intpriority_base_match := picm_raddr_ff(31,NUM_LEVELS+2) === INTPRIORITY_BASE_ADDR(31,NUM_LEVELS+2)// (31,NUM_LEVELS+2)
|
|
||||||
raddr_config_gw_base_match := picm_raddr_ff(31,NUM_LEVELS+2) === EXT_INTR_GW_CONFIG(31,NUM_LEVELS+2)// EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2)
|
|
||||||
val raddr_config_pic_match = picm_raddr_ff(31,0) === EXT_INTR_PIC_CONFIG
|
|
||||||
val addr_intpend_base_match = picm_raddr_ff(31,6) === INTPEND_BASE_ADDR(31,6)
|
|
||||||
val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0)
|
|
||||||
|
|
||||||
val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === EXT_INTR_GW_CLEAR(31, NUM_LEVELS+2)
|
|
||||||
waddr_intpriority_base_match := picm_waddr_ff(31,NUM_LEVELS+2) === INTPRIORITY_BASE_ADDR(31,NUM_LEVELS+2)
|
|
||||||
val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === INTENABLE_BASE_ADDR(31, NUM_LEVELS+2)
|
|
||||||
waddr_config_gw_base_match := picm_waddr_ff(31,NUM_LEVELS+2) === EXT_INTR_GW_CONFIG(31, NUM_LEVELS+2)
|
|
||||||
|
|
||||||
val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff)
|
|
||||||
|
|
||||||
picm_raddr_ff := withClock(pic_raddr_c1_clk){RegNext(io.picm_rdaddr, 0.U)}
|
|
||||||
picm_waddr_ff := withClock(pic_data_c1_clk){RegNext(io.picm_wraddr, 0.U)}
|
|
||||||
picm_wren_ff := withClock(io.active_clk){RegNext(io.picm_wren, false.B)}
|
|
||||||
picm_rden_ff := withClock(io.active_clk){RegNext(io.picm_rden, false.B)}
|
|
||||||
val picm_mken_ff = withClock(io.active_clk){RegNext(io.picm_mken, false.B)}
|
|
||||||
val picm_wr_data_ff = withClock(pic_data_c1_clk){RegNext(io.picm_wr_data, 0.U)}
|
|
||||||
|
|
||||||
|
|
||||||
def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
|
|
||||||
(Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
|
|
||||||
|
|
||||||
// ------ end clock gating section ------------------------
|
|
||||||
val extintsrc_req_sync = Cat(rvsyncss(io.extintsrc_req(PIC_TOTAL_INT_PLUS1-1,1),io.free_clk),io.extintsrc_req(0))
|
|
||||||
|
|
||||||
val intpriority_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intpriority_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
|
|
||||||
val intpriority_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intpriority_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
|
|
||||||
val intenable_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intenable_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
|
|
||||||
val intenable_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intenable_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
|
|
||||||
val gw_config_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_config_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
|
|
||||||
val gw_config_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_config_gw_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
|
|
||||||
val gw_clear_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){addr_clear_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
|
|
||||||
val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
|
|
||||||
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ intpriority_reg(i) := withClock(pic_pri_c1_clk){RegEnable(picm_wr_data_ff(INTPRIORITY_BITS-1,0),0.U,intpriority_reg_we(i).asBool)}} else intpriority_reg(i) := 0.U(INTPRIORITY_BITS.W))
|
|
||||||
val intenable_reg = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){withClock(pic_int_c1_clk){RegEnable(picm_wr_data_ff(0),0.U,intenable_reg_we(i).asBool)}} else 0.U)
|
|
||||||
val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W)))
|
|
||||||
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ gw_config_reg(i) := withClock(gw_config_c1_clk){RegEnable(picm_wr_data_ff(1,0),0.U,gw_config_reg_we(i).asBool)}} else gw_config_reg(i) := 0.U)
|
|
||||||
|
|
||||||
|
|
||||||
val extintsrc_req_gw = (0 until PIC_TOTAL_INT_PLUS1).map(i=>if(i>0) el2_configurable_gw(clock, reset.asAsyncReset(), extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool()) else 0.U)
|
|
||||||
|
|
||||||
|
|
||||||
val intpriord = WireInit(Bool(), false.B)
|
|
||||||
val intpriority_reg_inv = (0 until PIC_TOTAL_INT_PLUS1).map(i=>Mux(intpriord.asBool, !intpriority_reg(i), intpriority_reg(i)))
|
|
||||||
val intpend_w_prior_en = (0 until PIC_TOTAL_INT_PLUS1).map(i=>Fill(INTPRIORITY_BITS, extintsrc_req_gw(i) & intenable_reg(i)) & intpriority_reg_inv(i))
|
|
||||||
val intpend_id = (0 until PIC_TOTAL_INT_PLUS1).map(_.U)
|
|
||||||
|
|
||||||
val selected_int_priority = WireInit(UInt(INTPRIORITY_BITS.W), 0.U)
|
|
||||||
val pl_in = selected_int_priority
|
|
||||||
|
|
||||||
|
|
||||||
val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W))))
|
|
||||||
val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W))))
|
|
||||||
for(i<-1 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){
|
|
||||||
level_intpend_w_prior_en(i)(j) := 0.U
|
|
||||||
level_intpend_id(i)(j) := 0.U
|
|
||||||
}
|
|
||||||
level_intpend_w_prior_en(0) := IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W)) ++ (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i))
|
|
||||||
level_intpend_id(0) := IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W)) ++ (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i))
|
|
||||||
|
|
||||||
for(l<- 0 until NUM_LEVELS/2; m<- 0 to PIC_TOTAL_INT_PLUS1/math.pow(2, l+1).asInstanceOf[Int]){
|
|
||||||
if(m == PIC_TOTAL_INT_PLUS1/math.pow(2, l+1).asInstanceOf[Int]) {
|
|
||||||
level_intpend_w_prior_en(l+1)(m+1) := 0.U
|
|
||||||
level_intpend_id(l+1)(m+1) := 0.U}
|
|
||||||
else{ val a = 0.U}
|
|
||||||
val (out_id, out_priority) = el2_cmp_and_mux(level_intpend_id(l)(2*m), level_intpend_w_prior_en(l)(2*m), level_intpend_id(l)((2*m)+1), level_intpend_w_prior_en(l)((2*m)+1))
|
|
||||||
level_intpend_id(l+1)(m) := out_id
|
|
||||||
level_intpend_w_prior_en(l+1)(m) := out_priority
|
|
||||||
}
|
|
||||||
val temp = PIC_TOTAL_INT_PLUS1/math.pow(2, 1).asInstanceOf[Int]
|
|
||||||
|
|
||||||
/*
|
|
||||||
val pl_in = selected_int_priority
|
|
||||||
val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1 ,Vec((PIC_TOTAL_INT_PLUS1+2)+1,UInt(INTPRIORITY_BITS.W))))
|
|
||||||
for(i<- 0 until (NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1+2)+1) level_intpend_w_prior_en(i)(j) := 0.U //(0 until (NUM_LEVELS/2)+1).map(i => (0 until (PIC_TOTAL_INT_PLUS1+2)+1).map(j => 0.U(INTPRIORITY_BITS.W)))
|
|
||||||
val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1 ,Vec((PIC_TOTAL_INT_PLUS1+2)+1,UInt(ID_BITS.W))))
|
|
||||||
for(i<- 0 until (NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1+2)+1) level_intpend_id(i)(j) := 0.U
|
|
||||||
|
|
||||||
if (PIC_2CYCLE == 1) {
|
|
||||||
|
|
||||||
level_intpend_w_prior_en(0) := intpend_w_prior_en
|
|
||||||
level_intpend_id(0) := intpend_id
|
|
||||||
|
|
||||||
levelx_intpend_w_prior_en(NUM_LEVELS/2) := l2_intpend_w_prior_en_ff
|
|
||||||
levelx_intpend_id(NUM_LEVELS/2) := /*Cat((1.U((1*ID_BITS).W)),*/l2_intpend_id_ff//)
|
|
||||||
/// Do the prioritization of the interrupts here ////////////
|
|
||||||
for (l <-0 until NUM_LEVELS/2 ; m <- 0 until ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(l+1)).asInstanceOf[Int])) {
|
|
||||||
|
|
||||||
if ( m == (PIC_TOTAL_INT_PLUS1)/math.pow(2,(l+1)).asInstanceOf[Int]) {
|
|
||||||
level_intpend_w_prior_en(l+1)(m+1) := 0.U
|
|
||||||
level_intpend_id(l+1)(m+1) := 0.U
|
|
||||||
}
|
|
||||||
val cmp_l1 = Module (new el2_cmp_and_mux(ID_BITS,INTPRIORITY_BITS))
|
|
||||||
cmp_l1.io.a_id := (level_intpend_id(l)(2*m) )
|
|
||||||
cmp_l1.io.a_priority := (level_intpend_w_prior_en(l)(2*m))
|
|
||||||
cmp_l1.io.b_id := (level_intpend_id(l)(2*m+1))
|
|
||||||
cmp_l1.io.b_priority := (level_intpend_w_prior_en(l)(2*m+1))
|
|
||||||
(level_intpend_id(l+1)(m)) := cmp_l1.io.out_id
|
|
||||||
(level_intpend_w_prior_en(l+1)(m)) := cmp_l1.io.out_priority
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
(0 until PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int]).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))})
|
|
||||||
(0 until PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int]).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))})
|
|
||||||
|
|
||||||
|
|
||||||
for (j <-0 until NUM_LEVELS/2 ; k <- 0 until ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).asInstanceOf[Int])) {
|
|
||||||
|
|
||||||
if ( k == (PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).asInstanceOf[Int]) {
|
|
||||||
levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U
|
|
||||||
levelx_intpend_id(j + 1)(k + 1) := 0.U
|
|
||||||
}
|
|
||||||
val cmp_l1 = Module (new el2_cmp_and_mux(ID_BITS,INTPRIORITY_BITS))
|
|
||||||
cmp_l1.io.a_id := (levelx_intpend_id(j)(2*k))
|
|
||||||
cmp_l1.io.a_priority := (levelx_intpend_w_prior_en(j)(2*k))
|
|
||||||
cmp_l1.io.b_id := (levelx_intpend_id(j)(2*k+1))
|
|
||||||
cmp_l1.io.b_priority := (levelx_intpend_w_prior_en(j)(2*k+1))
|
|
||||||
(levelx_intpend_id(j+1)(k)) := cmp_l1.io.out_id
|
|
||||||
(levelx_intpend_w_prior_en(j+1)(k)) := cmp_l1.io.out_priority
|
|
||||||
|
|
||||||
}
|
|
||||||
claimid_in := levelx_intpend_id((NUM_LEVELS - NUM_LEVELS/2)+1)(0) // This is the last level output
|
|
||||||
selected_int_priority := levelx_intpend_w_prior_en((NUM_LEVELS - NUM_LEVELS/2)+1)(0)
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
//TODO: concatenate zeroes and ones in the vector see orignal code LINES 270, 274, 325, 395, 426, 176
|
|
||||||
//level_intpend_w_prior_en(0) := VecInit.tabulate(PIC_TOTAL_INT_PLUS1)(i=>Cat(0.U(3.W),intpend_w_prior_en(i)) )
|
|
||||||
//val t = VecInit.tabulate(4)(i=> Cat(0.U(3.W),intpend_w_prior_en))
|
|
||||||
val t = Wire(Vec((PIC_TOTAL_INT_PLUS1+2)+1,UInt(INTPRIORITY_BITS.W)))
|
|
||||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1+2)+1) t(i) := 0.U
|
|
||||||
val t2 = Wire(Vec((PIC_TOTAL_INT_PLUS1+2)+1,UInt(ID_BITS.W)))
|
|
||||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1+2)+1) t2(i) := 0.U
|
|
||||||
level_intpend_w_prior_en(0) := t//intpend_w_prior_en
|
|
||||||
level_intpend_id(0) := t2//intpend_id
|
|
||||||
|
|
||||||
/// Do the prioritization of the interrupts here ////////////
|
|
||||||
for (l <-0 until NUM_LEVELS/2 ; m <- 0 until ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(l+1)).asInstanceOf[Int])) {
|
|
||||||
if ( m == (PIC_TOTAL_INT_PLUS1)/math.pow(2,(l+1)).asInstanceOf[Int]) {
|
|
||||||
level_intpend_w_prior_en(l+1)(m+1) := 0.U
|
|
||||||
level_intpend_id(l+1)(m+1) := 0.U
|
|
||||||
}
|
|
||||||
val cmp_l1 = Module (new el2_cmp_and_mux(ID_BITS,INTPRIORITY_BITS))
|
|
||||||
cmp_l1.io.a_id := (level_intpend_id(l)(2*m) )
|
|
||||||
cmp_l1.io.a_priority := (level_intpend_w_prior_en(l)(2*m))
|
|
||||||
cmp_l1.io.b_id := (level_intpend_id(l)(2*m+1))
|
|
||||||
cmp_l1.io.b_priority := (level_intpend_w_prior_en(l)(2*m+1))
|
|
||||||
(level_intpend_id(l+1)(m)) := cmp_l1.io.out_id
|
|
||||||
(level_intpend_w_prior_en(l+1)(m)) := cmp_l1.io.out_priority
|
|
||||||
}
|
|
||||||
claimid_in := levelx_intpend_id((NUM_LEVELS - NUM_LEVELS/2))(0) // This is the last level output
|
|
||||||
selected_int_priority := levelx_intpend_w_prior_en((NUM_LEVELS - NUM_LEVELS/2))(0)
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////
|
|
||||||
// Config Reg`
|
|
||||||
///////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
val config_reg_we = waddr_config_pic_match & picm_wren_ff
|
|
||||||
val config_reg_re = raddr_config_pic_match & picm_rden_ff
|
|
||||||
val config_reg_in = picm_wr_data_ff(0)
|
|
||||||
withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)}
|
|
||||||
intpriord := config_reg
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////
|
|
||||||
/// ClaimId Reg and Corresponding PL
|
|
||||||
///////////////////////////////////////////////////////////
|
|
||||||
val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt
|
|
||||||
withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)}
|
|
||||||
withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)}
|
|
||||||
val meipt_inv = Mux(intpriord.asBool,!io.meipt,io.meipt)
|
|
||||||
val meicurpl_inv = Mux(intpriord.asBool,!io.meicurpl,io.meicurpl)
|
|
||||||
val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv)
|
|
||||||
withClock(io.free_clk){io.mexintpend := RegNext(mexintpend_in,0.U)}
|
|
||||||
val maxint = Mux(intpriord.asBool,0.U,15.U)
|
|
||||||
val mhwakeup_in = pl_in_q === maxint
|
|
||||||
withClock(io.free_clk){io.mhwakeup := RegNext(mhwakeup_in,0.U)}
|
|
||||||
|
|
||||||
//////////////////////////////////////////////////////////////////////////
|
|
||||||
// Reads of register.
|
|
||||||
// 1- intpending
|
|
||||||
//////////////////////////////////////////////////////////////////////////
|
|
||||||
val intpend_reg_read = addr_intpend_base_match & picm_rden_ff
|
|
||||||
val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff
|
|
||||||
val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff
|
|
||||||
val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff
|
|
||||||
|
|
||||||
intpend_reg_extended := Cat(0.U(32.W),(0 until extintsrc_req_gw.size).map(i => extintsrc_req_gw(i)).reverse.reduce(Cat(_,_)))
|
|
||||||
|
|
||||||
val intpend_rd_part_out = (0 until INT_GRPS).map (i=> Fill(32,intpend_reg_read & picm_raddr_ff(5,2) === i.asUInt) & intpend_reg_extended(((32*i)+31),(32*i))).reverse.reduce(Cat(_,_))
|
|
||||||
intpend_rd_out := (0 until INT_GRPS).map (i=>intpend_rd_part_out(i)).reduce (_|_)
|
|
||||||
for(i <- 0 until PIC_TOTAL_INT_PLUS1) { when (intenable_reg_re(i).asBool){ intenable_rd_out := intenable_reg(i)}.otherwise {intenable_rd_out :=0.U} }
|
|
||||||
|
|
||||||
val intpriority_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intpriority_reg_re(i).asBool -> intpriority_reg(i)))
|
|
||||||
val gw_config_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> gw_config_reg_re(i).asBool -> gw_config_reg(i)))
|
|
||||||
//////////////////////////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
val picm_rd_data_in = WireInit(UInt(32.W),0.U)
|
|
||||||
picm_rd_data_in := Mux1H(Seq(
|
|
||||||
intpend_reg_read.asBool -> intpend_rd_out,
|
|
||||||
intpriority_reg_read.asBool -> intpriority_rd_out ,
|
|
||||||
intenable_reg_read.asBool -> intenable_rd_out,
|
|
||||||
gw_config_reg_read.asBool -> gw_config_rd_out ,
|
|
||||||
config_reg_re.asBool -> config_reg ,
|
|
||||||
(picm_mken_ff & mask(3)).asBool -> Cat("b0".U(30.W) , "b11".U(2.W)) ,
|
|
||||||
(picm_mken_ff & mask(2)).asBool -> Cat("b0".U(31.W) , "b1".U(1.W)),
|
|
||||||
(picm_mken_ff & mask(1)).asBool -> Cat("b0".U(28.W) , "b1111".U(4.W)) ,
|
|
||||||
(picm_mken_ff & mask(0)).asBool -> "b0".U(32.W) ))
|
|
||||||
|
|
||||||
|
|
||||||
val picm_rd_data = Mux(picm_bypass_ff.asBool, picm_wr_data_ff, picm_rd_data_in)
|
|
||||||
val address = picm_raddr_ff(14,0)
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
class el2_cmp_and_mux(ID_BITS:Int=8,INTPRIORITY_BITS:Int=4) extends Module{
|
|
||||||
val io = IO(new Bundle{
|
|
||||||
val a_id = Input (UInt(ID_BITS.W))
|
|
||||||
val a_priority = Input (UInt(INTPRIORITY_BITS.W))
|
|
||||||
val b_id = Input (UInt(ID_BITS.W))
|
|
||||||
val b_priority = Input (UInt(INTPRIORITY_BITS.W))
|
|
||||||
val out_id = Output (UInt(ID_BITS.W))
|
|
||||||
val out_priority = Output (UInt(INTPRIORITY_BITS.W))
|
|
||||||
})
|
|
||||||
//logic a_is_lt_b ;
|
|
||||||
|
|
||||||
val a_is_lt_b = ( io.a_priority(INTPRIORITY_BITS-1,0) < io.b_priority(INTPRIORITY_BITS-1,0) )
|
|
||||||
|
|
||||||
io.out_id := Mux(a_is_lt_b, io.b_id , io.a_id)
|
|
||||||
io.out_priority := Mux(a_is_lt_b ,io.b_priority ,io.a_priority)
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
class el2_configurable_gw extends Module{
|
|
||||||
val io = IO(new Bundle{
|
|
||||||
val extintsrc_req_sync = Input(UInt(1.W))
|
|
||||||
val meigwctrl_polarity = Input(UInt(1.W))
|
|
||||||
val meigwctrl_type = Input(UInt(1.W))
|
|
||||||
val meigwclr = Input(UInt(1.W))
|
|
||||||
val extintsrc_req_config = Output(UInt(1.W))
|
|
||||||
})
|
|
||||||
|
|
||||||
val gw_int_pending = WireInit(UInt(1.W),0.U)
|
|
||||||
|
|
||||||
val gw_int_pending_in = (io.extintsrc_req_sync ^ io.meigwctrl_polarity) | (gw_int_pending & !io.meigwclr)
|
|
||||||
gw_int_pending := RegNext(gw_int_pending_in,0.U)
|
|
||||||
|
|
||||||
io.extintsrc_req_config := Mux(io.meigwctrl_type.asBool(), ((io.extintsrc_req_sync ^ io.meigwctrl_polarity) | gw_int_pending), (io.extintsrc_req_sync ^ io.meigwctrl_polarity))
|
|
||||||
*/
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
object pic_main extends App{
|
|
||||||
println("Generate Verilog")
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_pic_ctrl()))
|
|
||||||
}
|
|
|
@ -1,858 +0,0 @@
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
import ifu._
|
|
||||||
import dec._
|
|
||||||
import exu._
|
|
||||||
import lsu._
|
|
||||||
import lib._
|
|
||||||
import include._
|
|
||||||
import dbg._
|
|
||||||
|
|
||||||
class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|
||||||
val io = IO (new Bundle{
|
|
||||||
val dbg_rst_l = Input(Bool())
|
|
||||||
val rst_vec = Input(UInt(31.W))
|
|
||||||
val nmi_int = Input(Bool())
|
|
||||||
val nmi_vec = Input(UInt(31.W))
|
|
||||||
val core_rst_l = Output(AsyncReset())
|
|
||||||
// val trace_rv_i_insn_ip = Output(UInt(32.W))
|
|
||||||
// val trace_rv_i_address_ip = Output(UInt(32.W))
|
|
||||||
// val trace_rv_i_valid_ip = Output(UInt(2.W))
|
|
||||||
// val trace_rv_i_exception_ip = Output(UInt(2.W))
|
|
||||||
// val trace_rv_i_ecause_ip = Output(UInt(5.W))
|
|
||||||
// val trace_rv_i_interrupt_ip = Output(UInt(2.W))
|
|
||||||
// val trace_rv_i_tval_ip = Output(UInt(32.W))
|
|
||||||
val dccm_clk_override = Output(Bool())
|
|
||||||
val icm_clk_override = Output(Bool())
|
|
||||||
val dec_tlu_core_ecc_disable = Output(Bool())
|
|
||||||
val i_cpu_halt_req = Input(Bool())
|
|
||||||
val i_cpu_run_req = Input(Bool())
|
|
||||||
val o_cpu_halt_ack = Output(Bool())
|
|
||||||
val o_cpu_halt_status = Output(Bool())
|
|
||||||
val o_cpu_run_ack = Output(Bool())
|
|
||||||
val o_debug_mode_status = Output(Bool())
|
|
||||||
val core_id = Input(UInt(28.W))
|
|
||||||
val mpc_debug_halt_req = Input(Bool())
|
|
||||||
val mpc_debug_run_req = Input(Bool())
|
|
||||||
val mpc_reset_run_req = Input(Bool())
|
|
||||||
val mpc_debug_halt_ack = Output(Bool())
|
|
||||||
val mpc_debug_run_ack = Output(Bool())
|
|
||||||
val debug_brkpt_status = Output(Bool())
|
|
||||||
val dec_tlu_perfcnt0 = Output(Bool())
|
|
||||||
val dec_tlu_perfcnt1 = Output(Bool())
|
|
||||||
val dec_tlu_perfcnt2 = Output(Bool())
|
|
||||||
val dec_tlu_perfcnt3 = Output(Bool())
|
|
||||||
val dccm_wren = Output(Bool())
|
|
||||||
val dccm_rden = Output(Bool())
|
|
||||||
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
|
||||||
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
|
||||||
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
|
||||||
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
|
||||||
|
|
||||||
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
|
||||||
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
|
||||||
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
|
||||||
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
|
||||||
|
|
||||||
val iccm_rw_addr = Output(UInt(ICCM_BITS.W))
|
|
||||||
val iccm_wren = Output(Bool())
|
|
||||||
val iccm_rden = Output(Bool())
|
|
||||||
val iccm_wr_size = Output(UInt(3.W))
|
|
||||||
val iccm_wr_data = Output(UInt(78.W))
|
|
||||||
val iccm_buf_correct_ecc = Output(Bool())
|
|
||||||
val iccm_correction_state = Output(Bool())
|
|
||||||
|
|
||||||
val iccm_rd_data = Input(UInt(64.W))
|
|
||||||
val iccm_rd_data_ecc = Input(UInt(78.W))
|
|
||||||
|
|
||||||
val ic_rw_addr = Output(UInt(31.W))
|
|
||||||
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
|
|
||||||
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
|
|
||||||
val ic_rd_en = Output(Bool())
|
|
||||||
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
|
|
||||||
val ic_rd_data = Input(UInt(64.W))
|
|
||||||
val ic_debug_rd_data = Input(UInt(71.W))
|
|
||||||
val ictag_debug_rd_data = Input(UInt(26.W))
|
|
||||||
val ic_debug_wr_data = Output(UInt(71.W))
|
|
||||||
|
|
||||||
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
|
||||||
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
|
|
||||||
val ic_premux_data = Output(UInt(64.W))
|
|
||||||
val ic_sel_premux_data = Output(Bool())
|
|
||||||
|
|
||||||
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
|
|
||||||
val ic_debug_rd_en = Output(Bool())
|
|
||||||
val ic_debug_wr_en = Output(Bool())
|
|
||||||
val ic_debug_tag_array = Output(Bool())
|
|
||||||
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
|
|
||||||
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
|
|
||||||
val ic_tag_perr = Input(Bool())
|
|
||||||
|
|
||||||
// AXI Signals
|
|
||||||
val lsu_axi_awvalid = Output(Bool())
|
|
||||||
val lsu_axi_awready = Input(Bool())
|
|
||||||
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
|
||||||
val lsu_axi_awaddr = Output(UInt(32.W))
|
|
||||||
val lsu_axi_awregion = Output(UInt(4.W))
|
|
||||||
val lsu_axi_awlen = Output(UInt(8.W))
|
|
||||||
val lsu_axi_awsize = Output(UInt(3.W))
|
|
||||||
val lsu_axi_awburst = Output(UInt(2.W))
|
|
||||||
val lsu_axi_awlock = Output(Bool())
|
|
||||||
val lsu_axi_awcache = Output(UInt(4.W))
|
|
||||||
val lsu_axi_awprot = Output(UInt(3.W))
|
|
||||||
val lsu_axi_awqos = Output(UInt(4.W))
|
|
||||||
val lsu_axi_wvalid = Output(Bool())
|
|
||||||
val lsu_axi_wready = Input(Bool())
|
|
||||||
val lsu_axi_wdata = Output(UInt(64.W))
|
|
||||||
val lsu_axi_wstrb = Output(UInt(8.W))
|
|
||||||
val lsu_axi_wlast = Output(Bool())
|
|
||||||
val lsu_axi_bvalid = Input(Bool())
|
|
||||||
val lsu_axi_bready = Output(Bool())
|
|
||||||
val lsu_axi_bresp = Input(UInt(2.W))
|
|
||||||
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
|
||||||
|
|
||||||
|
|
||||||
val lsu_axi_arvalid = Output(Bool())
|
|
||||||
val lsu_axi_arready = Input(Bool())
|
|
||||||
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
|
||||||
val lsu_axi_araddr = Output(UInt(32.W))
|
|
||||||
val lsu_axi_arregion = Output(UInt(4.W))
|
|
||||||
val lsu_axi_arlen = Output(UInt(8.W))
|
|
||||||
val lsu_axi_arsize = Output(UInt(3.W))
|
|
||||||
val lsu_axi_arburst = Output(UInt(2.W))
|
|
||||||
val lsu_axi_arlock = Output(Bool())
|
|
||||||
val lsu_axi_arcache = Output(UInt(4.W))
|
|
||||||
val lsu_axi_arprot = Output(UInt(3.W))
|
|
||||||
val lsu_axi_arqos = Output(UInt(4.W))
|
|
||||||
val lsu_axi_rvalid = Input(Bool())
|
|
||||||
val lsu_axi_rready = Output(Bool())
|
|
||||||
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
|
||||||
val lsu_axi_rdata = Input(UInt(64.W))
|
|
||||||
val lsu_axi_rresp = Input(UInt(2.W))
|
|
||||||
val lsu_axi_rlast = Input(Bool())
|
|
||||||
|
|
||||||
|
|
||||||
// AXI IFU Signals
|
|
||||||
val ifu_axi_awvalid = Output(Bool())
|
|
||||||
val ifu_axi_awready = Input(Bool())
|
|
||||||
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
|
|
||||||
val ifu_axi_awaddr = Output(UInt(32.W))
|
|
||||||
val ifu_axi_awregion = Output(UInt(4.W))
|
|
||||||
val ifu_axi_awlen = Output(UInt(8.W))
|
|
||||||
val ifu_axi_awsize = Output(UInt(3.W))
|
|
||||||
val ifu_axi_awburst = Output(UInt(2.W))
|
|
||||||
val ifu_axi_awlock = Output(Bool())
|
|
||||||
val ifu_axi_awcache = Output(UInt(4.W))
|
|
||||||
val ifu_axi_awprot = Output(UInt(3.W))
|
|
||||||
val ifu_axi_awqos = Output(UInt(4.W))
|
|
||||||
val ifu_axi_wvalid = Output(Bool())
|
|
||||||
val ifu_axi_wready = Output(Bool())
|
|
||||||
val ifu_axi_wdata = Output(UInt(64.W))
|
|
||||||
val ifu_axi_wstrb = Output(UInt(8.W))
|
|
||||||
val ifu_axi_wlast = Output(Bool())
|
|
||||||
val ifu_axi_bvalid = Input(Bool())
|
|
||||||
val ifu_axi_bready = Output(Bool())
|
|
||||||
val ifu_axi_bresp = Input(UInt(2.W))
|
|
||||||
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
|
|
||||||
val ifu_axi_arvalid = Output(Bool())
|
|
||||||
val ifu_axi_arready = Input(Bool())
|
|
||||||
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
|
|
||||||
val ifu_axi_araddr = Output(UInt(32.W))
|
|
||||||
val ifu_axi_arregion = Output(UInt(4.W))
|
|
||||||
val ifu_axi_arlen = Output(UInt(8.W))
|
|
||||||
val ifu_axi_arsize = Output(UInt(3.W))
|
|
||||||
val ifu_axi_arburst = Output(UInt(2.W))
|
|
||||||
val ifu_axi_arlock = Output(Bool())
|
|
||||||
val ifu_axi_arcache = Output(UInt(4.W))
|
|
||||||
val ifu_axi_arprot = Output(UInt(3.W))
|
|
||||||
val ifu_axi_arqos = Output(UInt(4.W))
|
|
||||||
val ifu_axi_rvalid = Input(Bool())
|
|
||||||
val ifu_axi_rready = Output(Bool())
|
|
||||||
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
|
|
||||||
val ifu_axi_rdata = Input(UInt(64.W))
|
|
||||||
val ifu_axi_rresp = Input(UInt(2.W))
|
|
||||||
val ifu_axi_rlast = Input(Bool())
|
|
||||||
|
|
||||||
// SB AXI Signals
|
|
||||||
val sb_axi_awvalid = Output(Bool())
|
|
||||||
val sb_axi_awready = Input(Bool())
|
|
||||||
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
|
|
||||||
val sb_axi_awaddr = Output(UInt(32.W))
|
|
||||||
val sb_axi_awregion = Output(UInt(4.W))
|
|
||||||
val sb_axi_awlen = Output(UInt(8.W))
|
|
||||||
val sb_axi_awsize = Output(UInt(3.W))
|
|
||||||
val sb_axi_awburst = Output(UInt(2.W))
|
|
||||||
val sb_axi_awlock = Output(Bool())
|
|
||||||
val sb_axi_awcache = Output(UInt(4.W))
|
|
||||||
val sb_axi_awprot = Output(UInt(3.W))
|
|
||||||
val sb_axi_awqos = Output(UInt(4.W))
|
|
||||||
val sb_axi_wvalid = Output(Bool())
|
|
||||||
val sb_axi_wready = Input(Bool())
|
|
||||||
val sb_axi_wdata = Output(UInt(64.W))
|
|
||||||
val sb_axi_wstrb = Output(UInt(8.W))
|
|
||||||
val sb_axi_wlast = Output(Bool())
|
|
||||||
val sb_axi_bvalid = Input(Bool())
|
|
||||||
val sb_axi_bready = Output(Bool())
|
|
||||||
val sb_axi_bresp = Input(UInt(2.W))
|
|
||||||
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
|
|
||||||
val sb_axi_arvalid = Output(Bool())
|
|
||||||
val sb_axi_arready = Input(Bool())
|
|
||||||
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
|
|
||||||
val sb_axi_araddr = Output(UInt(32.W))
|
|
||||||
val sb_axi_arregion = Output(UInt(4.W))
|
|
||||||
val sb_axi_arlen = Output(UInt(8.W))
|
|
||||||
val sb_axi_arsize = Output(UInt(3.W))
|
|
||||||
val sb_axi_arburst = Output(UInt(2.W))
|
|
||||||
val sb_axi_arlock = Output(Bool())
|
|
||||||
val sb_axi_arcache = Output(UInt(4.W))
|
|
||||||
val sb_axi_arprot = Output(UInt(3.W))
|
|
||||||
val sb_axi_arqos = Output(UInt(4.W))
|
|
||||||
val sb_axi_rvalid = Input(Bool())
|
|
||||||
val sb_axi_rready = Output(Bool())
|
|
||||||
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
|
|
||||||
val sb_axi_rdata = Input(UInt(64.W))
|
|
||||||
val sb_axi_rresp = Input(UInt(2.W))
|
|
||||||
val sb_axi_rlast = Input(Bool())
|
|
||||||
// DMA signals
|
|
||||||
val dma_axi_awvalid = Input(Bool())
|
|
||||||
val dma_axi_awready = Output(Bool())
|
|
||||||
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
|
|
||||||
val dma_axi_awaddr = Input(UInt(32.W))
|
|
||||||
val dma_axi_awsize = Input(UInt(3.W))
|
|
||||||
val dma_axi_awprot = Input(UInt(3.W))
|
|
||||||
val dma_axi_awlen = Input(UInt(8.W))
|
|
||||||
val dma_axi_awburst = Input(UInt(2.W))
|
|
||||||
val dma_axi_wvalid = Input(Bool())
|
|
||||||
val dma_axi_wready = Output(Bool())
|
|
||||||
val dma_axi_wdata = Input(UInt(64.W))
|
|
||||||
val dma_axi_wstrb = Input(UInt(8.W))
|
|
||||||
val dma_axi_wlast = Input(Bool())
|
|
||||||
val dma_axi_bvalid = Output(Bool())
|
|
||||||
val dma_axi_bready = Input(Bool())
|
|
||||||
val dma_axi_bresp = Output(UInt(2.W))
|
|
||||||
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
|
|
||||||
|
|
||||||
// AXI Read Channels
|
|
||||||
val dma_axi_arvalid = Input(Bool())
|
|
||||||
val dma_axi_arready = Output(Bool())
|
|
||||||
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
|
|
||||||
|
|
||||||
val dma_axi_araddr = Input(UInt(32.W))
|
|
||||||
val dma_axi_arsize = Input(UInt(3.W))
|
|
||||||
|
|
||||||
val dma_axi_arprot = Input(UInt(3.W))
|
|
||||||
val dma_axi_arlen = Input(UInt(8.W))
|
|
||||||
val dma_axi_arburst = Input(UInt(2.W))
|
|
||||||
val dma_axi_rvalid = Output(Bool())
|
|
||||||
val dma_axi_rready = Input(Bool())
|
|
||||||
|
|
||||||
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
|
|
||||||
val dma_axi_rdata = Output(UInt(64.W))
|
|
||||||
val dma_axi_rresp = Output(UInt(2.W))
|
|
||||||
val dma_axi_rlast = Output(Bool())
|
|
||||||
|
|
||||||
// AHB Lite Bus
|
|
||||||
val haddr = Output(UInt(32.W))
|
|
||||||
val hburst = Output(UInt(3.W))
|
|
||||||
val hmastlock = Output(Bool())
|
|
||||||
val hprot = Output(UInt(4.W))
|
|
||||||
val hsize = Output(UInt(3.W))
|
|
||||||
val htrans = Output(UInt(2.W))
|
|
||||||
val hwrite = Output(Bool())
|
|
||||||
val hrdata = Input(UInt(64.W))
|
|
||||||
val hready = Input(Bool())
|
|
||||||
val hresp = Input(Bool())
|
|
||||||
|
|
||||||
// AHB Master
|
|
||||||
val lsu_haddr = Output(UInt(32.W))
|
|
||||||
val lsu_hburst = Output(UInt(3.W))
|
|
||||||
val lsu_hmastlock = Output(Bool())
|
|
||||||
val lsu_hprot = Output(UInt(4.W))
|
|
||||||
val lsu_hsize = Output(UInt(3.W))
|
|
||||||
val lsu_htrans = Output(UInt(2.W))
|
|
||||||
val lsu_hwrite = Output(Bool())
|
|
||||||
val lsu_hwdata = Output(UInt(64.W))
|
|
||||||
val lsu_hrdata = Input(UInt(64.W))
|
|
||||||
val lsu_hready = Input(Bool())
|
|
||||||
val lsu_hresp = Input(Bool())
|
|
||||||
|
|
||||||
// System Bus Debug Master
|
|
||||||
val sb_haddr = Output(UInt(32.W))
|
|
||||||
val sb_hburst = Output(UInt(3.W))
|
|
||||||
val sb_hmastlock = Output(Bool())
|
|
||||||
val sb_hprot = Output(UInt(4.W))
|
|
||||||
val sb_hsize = Output(UInt(3.W))
|
|
||||||
val sb_htrans = Output(UInt(2.W))
|
|
||||||
val sb_hwrite = Output(Bool())
|
|
||||||
val sb_hwdata = Output(UInt(64.W))
|
|
||||||
val sb_hrdata = Input(UInt(64.W))
|
|
||||||
val sb_hready = Input(Bool())
|
|
||||||
val sb_hresp = Input(Bool())
|
|
||||||
|
|
||||||
// DMA slave
|
|
||||||
val dma_hsel = Input(Bool())
|
|
||||||
val dma_haddr = Input(UInt(32.W))
|
|
||||||
val dma_hburst = Input(UInt(3.W))
|
|
||||||
val dma_hmastlock = Input(Bool())
|
|
||||||
val dma_hprot = Input(UInt(4.W))
|
|
||||||
val dma_hsize = Input(UInt(3.W))
|
|
||||||
val dma_htrans = Input(UInt(2.W))
|
|
||||||
val dma_hwrite = Input(Bool())
|
|
||||||
val dma_hwdata = Input(UInt(64.W))
|
|
||||||
val dma_hreadyin = Input(Bool())
|
|
||||||
val dma_hrdata = Output(UInt(64.W))
|
|
||||||
val dma_hreadyout = Output(Bool())
|
|
||||||
val dma_hresp = Output(Bool())
|
|
||||||
val lsu_bus_clk_en = Input(Bool())
|
|
||||||
val ifu_bus_clk_en = Input(Bool())
|
|
||||||
val dbg_bus_clk_en = Input(Bool())
|
|
||||||
val dma_bus_clk_en = Input(Bool())
|
|
||||||
val dmi_reg_en = Input(Bool())
|
|
||||||
val dmi_reg_addr = Input(UInt(7.W))
|
|
||||||
val dmi_reg_wr_en = Input(Bool())
|
|
||||||
val dmi_reg_wdata = Input(UInt(32.W))
|
|
||||||
val dmi_reg_rdata = Output(UInt(32.W))
|
|
||||||
val dmi_hard_reset = Input(Bool())
|
|
||||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
|
||||||
val timer_int = Input(Bool())
|
|
||||||
val soft_int = Input(Bool())
|
|
||||||
val scan_mode = Input(Bool())
|
|
||||||
})
|
|
||||||
|
|
||||||
|
|
||||||
val ifu = Module(new el2_ifu)
|
|
||||||
val dec = Module(new el2_dec)
|
|
||||||
val dbg = Module(new el2_dbg)
|
|
||||||
val exu = Module(new el2_exu)
|
|
||||||
val lsu = Module(new el2_lsu)
|
|
||||||
val pic_ctl_inst = Module(new el2_pic_ctrl)
|
|
||||||
val dma_ctrl = Module(new el2_dma_ctrl)
|
|
||||||
//val lsu_axi4_to_ahb = Module(new axi4_to_ahb)
|
|
||||||
//val ifu_axi4_to_ahb = Module(new axi4_to_ahb)
|
|
||||||
//val sb_axi4_to_ahb = Module(new axi4_to_ahb)
|
|
||||||
|
|
||||||
io.core_rst_l := (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset()
|
|
||||||
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
|
||||||
val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
|
||||||
val active_clk = rvclkhdr(clock, active_state, io.scan_mode)
|
|
||||||
val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
|
||||||
val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
|
||||||
val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
|
||||||
|
|
||||||
// AHB to AXI-4 still remaining
|
|
||||||
|
|
||||||
|
|
||||||
// Lets start with IFU
|
|
||||||
ifu.reset := io.core_rst_l
|
|
||||||
ifu.io.scan_mode := io.scan_mode
|
|
||||||
ifu.io.free_clk := free_clk
|
|
||||||
ifu.io.active_clk := active_clk
|
|
||||||
ifu.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc
|
|
||||||
ifu.io.dec_i0_decode_d := dec.io.dec_i0_decode_d
|
|
||||||
ifu.io.exu_flush_final := dec.io.exu_flush_final
|
|
||||||
ifu.io.dec_tlu_i0_commit_cmt := dec.io.dec_tlu_i0_commit_cmt
|
|
||||||
ifu.io.dec_tlu_flush_err_wb := dec.io.dec_tlu_flush_err_r
|
|
||||||
ifu.io.dec_tlu_flush_noredir_wb := dec.io.dec_tlu_flush_noredir_r
|
|
||||||
ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
|
|
||||||
ifu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
|
|
||||||
ifu.io.dec_tlu_fence_i_wb := dec.io.dec_tlu_fence_i_r
|
|
||||||
ifu.io.dec_tlu_flush_leak_one_wb := dec.io.dec_tlu_flush_leak_one_r
|
|
||||||
ifu.io.dec_tlu_bpred_disable := dec.io.dec_tlu_bpred_disable
|
|
||||||
ifu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
|
|
||||||
ifu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
|
|
||||||
ifu.io.ifu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_arready)
|
|
||||||
ifu.io.ifu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rvalid)
|
|
||||||
ifu.io.ifu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rid)
|
|
||||||
ifu.io.ifu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rdata)
|
|
||||||
ifu.io.ifu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rresp)
|
|
||||||
ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
|
||||||
ifu.io.dma_iccm_req := dma_ctrl.io.dma_iccm_req
|
|
||||||
ifu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
|
|
||||||
ifu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
|
|
||||||
ifu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
|
|
||||||
ifu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
|
|
||||||
ifu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
|
|
||||||
ifu.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
|
|
||||||
ifu.io.ic_rd_data := io.ic_rd_data
|
|
||||||
ifu.io.ic_debug_rd_data := io.ic_debug_rd_data
|
|
||||||
ifu.io.ictag_debug_rd_data := io.ictag_debug_rd_data
|
|
||||||
ifu.io.ic_eccerr := io.ic_eccerr
|
|
||||||
ifu.io.ic_parerr := io.ic_parerr
|
|
||||||
ifu.io.ic_rd_hit := io.ic_rd_hit
|
|
||||||
ifu.io.ic_tag_perr := io.ic_tag_perr
|
|
||||||
ifu.io.iccm_rd_data := io.iccm_rd_data
|
|
||||||
ifu.io.exu_mp_pkt <> exu.io.exu_mp_pkt
|
|
||||||
ifu.io.exu_mp_eghr := exu.io.exu_mp_eghr
|
|
||||||
ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
|
|
||||||
ifu.io.exu_mp_index := exu.io.exu_mp_index
|
|
||||||
ifu.io.exu_mp_btag := exu.io.exu_mp_btag
|
|
||||||
ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt
|
|
||||||
ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
|
|
||||||
ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
|
|
||||||
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r
|
|
||||||
ifu.io.dec_tlu_ic_diag_pkt <> dec.io.dec_tlu_ic_diag_pkt
|
|
||||||
|
|
||||||
// Lets start with Dec
|
|
||||||
dec.reset := io.core_rst_l
|
|
||||||
dec.io.free_clk := free_clk
|
|
||||||
dec.io.active_clk := active_clk
|
|
||||||
dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
|
|
||||||
dec.io.rst_vec := io.rst_vec
|
|
||||||
dec.io.nmi_int := io.nmi_int
|
|
||||||
dec.io.nmi_vec := io.nmi_vec
|
|
||||||
dec.io.i_cpu_halt_req := io.i_cpu_halt_req
|
|
||||||
dec.io.i_cpu_run_req := io.i_cpu_run_req
|
|
||||||
dec.io.core_id := io.core_id
|
|
||||||
dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
|
||||||
dec.io.mpc_debug_run_req := io.mpc_debug_run_req
|
|
||||||
dec.io.mpc_reset_run_req := io.mpc_reset_run_req
|
|
||||||
dec.io.exu_pmu_i0_br_misp := exu.io.exu_pmu_i0_br_misp
|
|
||||||
dec.io.exu_pmu_i0_br_ataken := exu.io.exu_pmu_i0_br_ataken
|
|
||||||
dec.io.exu_pmu_i0_pc4 := exu.io.exu_pmu_i0_pc4
|
|
||||||
dec.io.lsu_nonblock_load_valid_m := lsu.io.lsu_nonblock_load_valid_m
|
|
||||||
dec.io.lsu_nonblock_load_tag_m := lsu.io.lsu_nonblock_load_tag_m
|
|
||||||
dec.io.lsu_nonblock_load_inv_r := lsu.io.lsu_nonblock_load_inv_r
|
|
||||||
dec.io.lsu_nonblock_load_inv_tag_r := lsu.io.lsu_nonblock_load_inv_tag_r
|
|
||||||
dec.io.lsu_nonblock_load_data_valid := lsu.io.lsu_nonblock_load_data_valid
|
|
||||||
dec.io.lsu_nonblock_load_data_error := lsu.io.lsu_nonblock_load_data_error
|
|
||||||
dec.io.lsu_nonblock_load_data_tag := lsu.io.lsu_nonblock_load_data_tag
|
|
||||||
dec.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data
|
|
||||||
dec.io.lsu_pmu_bus_trxn := lsu.io.lsu_pmu_bus_trxn
|
|
||||||
dec.io.lsu_pmu_bus_misaligned := lsu.io.lsu_pmu_bus_misaligned
|
|
||||||
dec.io.lsu_pmu_bus_error := lsu.io.lsu_pmu_bus_error
|
|
||||||
dec.io.lsu_pmu_bus_busy := lsu.io.lsu_pmu_bus_busy
|
|
||||||
dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
|
|
||||||
dec.io.lsu_pmu_load_external_m := lsu.io.lsu_pmu_load_external_m
|
|
||||||
dec.io.lsu_pmu_store_external_m := lsu.io.lsu_pmu_store_external_m
|
|
||||||
dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read
|
|
||||||
dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write
|
|
||||||
dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read
|
|
||||||
dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write
|
|
||||||
dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
|
|
||||||
dec.io.lsu_fir_error := lsu.io.lsu_fir_error
|
|
||||||
dec.io.ifu_pmu_instr_aligned := ifu.io.ifu_pmu_instr_aligned
|
|
||||||
dec.io.ifu_pmu_fetch_stall := ifu.io.ifu_pmu_fetch_stall
|
|
||||||
dec.io.ifu_pmu_ic_miss := ifu.io.ifu_pmu_ic_miss
|
|
||||||
dec.io.ifu_pmu_ic_hit := ifu.io.ifu_pmu_ic_hit
|
|
||||||
dec.io.ifu_pmu_bus_error := ifu.io.ifu_pmu_bus_error
|
|
||||||
dec.io.ifu_pmu_bus_busy := ifu.io.ifu_pmu_bus_busy
|
|
||||||
dec.io.ifu_pmu_bus_trxn := ifu.io.ifu_pmu_bus_trxn
|
|
||||||
dec.io.ifu_ic_error_start := ifu.io.ifu_ic_error_start
|
|
||||||
dec.io.ifu_iccm_rd_ecc_single_err := ifu.io.ifu_iccm_rd_ecc_single_err
|
|
||||||
dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
|
|
||||||
dec.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
|
|
||||||
dec.io.dbg_cmd_write := dbg.io.dbg_cmd_write
|
|
||||||
dec.io.dbg_cmd_type := dbg.io.dbg_cmd_type
|
|
||||||
dec.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
|
|
||||||
dec.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
|
|
||||||
dec.io.ifu_i0_icaf := ifu.io.ifu_i0_icaf
|
|
||||||
dec.io.ifu_i0_icaf_type := ifu.io.ifu_i0_icaf_type
|
|
||||||
dec.io.ifu_i0_icaf_f1 := ifu.io.ifu_i0_icaf_f1
|
|
||||||
dec.io.ifu_i0_dbecc := ifu.io.ifu_i0_dbecc
|
|
||||||
dec.io.lsu_idle_any := lsu.io.lsu_idle_any
|
|
||||||
dec.io.i0_brp := ifu.io.i0_brp
|
|
||||||
dec.io.ifu_i0_bp_index := ifu.io.ifu_i0_bp_index
|
|
||||||
dec.io.ifu_i0_bp_fghr := ifu.io.ifu_i0_bp_fghr
|
|
||||||
dec.io.ifu_i0_bp_btag := ifu.io.ifu_i0_bp_btag
|
|
||||||
dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
|
|
||||||
dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
|
|
||||||
dec.io.lsu_imprecise_error_load_any := lsu.io.lsu_imprecise_error_load_any
|
|
||||||
dec.io.lsu_imprecise_error_store_any := lsu.io.lsu_imprecise_error_store_any
|
|
||||||
dec.io.lsu_imprecise_error_addr_any := lsu.io.lsu_imprecise_error_addr_any
|
|
||||||
dec.io.exu_div_result := exu.io.exu_div_result
|
|
||||||
dec.io.exu_div_wren := exu.io.exu_div_wren
|
|
||||||
dec.io.exu_csr_rs1_x := exu.io.exu_csr_rs1_x
|
|
||||||
dec.io.lsu_result_m := lsu.io.lsu_result_m
|
|
||||||
dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
|
|
||||||
dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
|
|
||||||
dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
|
|
||||||
dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any
|
|
||||||
dec.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any
|
|
||||||
dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
|
|
||||||
dec.io.exu_flush_final := exu.io.exu_flush_final
|
|
||||||
dec.io.exu_npc_r := exu.io.exu_npc_r
|
|
||||||
dec.io.exu_i0_result_x := exu.io.exu_i0_result_x
|
|
||||||
dec.io.ifu_i0_valid := ifu.io.ifu_i0_valid
|
|
||||||
dec.io.ifu_i0_instr := ifu.io.ifu_i0_instr
|
|
||||||
dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc
|
|
||||||
dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4
|
|
||||||
dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x
|
|
||||||
dec.io.mexintpend := pic_ctl_inst.io.mexintpend
|
|
||||||
dec.io.soft_int := io.soft_int
|
|
||||||
dec.io.pic_claimid := pic_ctl_inst.io.claimid
|
|
||||||
dec.io.pic_pl := pic_ctl_inst.io.pl
|
|
||||||
dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup
|
|
||||||
dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data
|
|
||||||
dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid
|
|
||||||
dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
|
||||||
dec.io.dbg_resume_req := dbg.io.dbg_resume_req
|
|
||||||
dec.io.ifu_miss_state_idle := ifu.io.ifu_miss_state_idle
|
|
||||||
dec.io.exu_i0_br_hist_r := exu.io.exu_i0_br_hist_r
|
|
||||||
dec.io.exu_i0_br_error_r := exu.io.exu_i0_br_error_r
|
|
||||||
dec.io.exu_i0_br_start_error_r := exu.io.exu_i0_br_start_error_r
|
|
||||||
dec.io.exu_i0_br_valid_r := exu.io.exu_i0_br_valid_r
|
|
||||||
dec.io.exu_i0_br_mp_r := exu.io.exu_i0_br_mp_r
|
|
||||||
dec.io.exu_i0_br_middle_r := exu.io.exu_i0_br_middle_r
|
|
||||||
dec.io.exu_i0_br_way_r := exu.io.exu_i0_br_way_r
|
|
||||||
dec.io.ifu_i0_cinst := ifu.io.ifu_i0_cinst
|
|
||||||
dec.io.timer_int := io.timer_int
|
|
||||||
dec.io.scan_mode := io.scan_mode
|
|
||||||
|
|
||||||
// EXU lets go
|
|
||||||
exu.reset := io.core_rst_l
|
|
||||||
exu.io.scan_mode := io.scan_mode
|
|
||||||
exu.io.dec_data_en := dec.io.dec_data_en
|
|
||||||
exu.io.dec_ctl_en := dec.io.dec_ctl_en
|
|
||||||
exu.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
|
|
||||||
exu.io.i0_ap := dec.io.i0_ap
|
|
||||||
exu.io.dec_debug_wdata_rs1_d := dec.io.dec_debug_wdata_rs1_d
|
|
||||||
exu.io.dec_i0_predict_p_d <> dec.io.dec_i0_predict_p_d
|
|
||||||
exu.io.i0_predict_fghr_d := dec.io.i0_predict_fghr_d
|
|
||||||
exu.io.i0_predict_index_d := dec.io.i0_predict_index_d
|
|
||||||
exu.io.i0_predict_btag_d := dec.io.i0_predict_btag_d
|
|
||||||
exu.io.dec_i0_rs1_en_d := dec.io.dec_i0_rs1_en_d
|
|
||||||
exu.io.dec_i0_rs2_en_d := dec.io.dec_i0_rs2_en_d
|
|
||||||
exu.io.gpr_i0_rs1_d := dec.io.gpr_i0_rs1_d
|
|
||||||
exu.io.gpr_i0_rs2_d := dec.io.gpr_i0_rs2_d
|
|
||||||
exu.io.dec_i0_immed_d := dec.io.dec_i0_immed_d
|
|
||||||
exu.io.dec_i0_rs1_bypass_data_d := dec.io.dec_i0_rs1_bypass_data_d
|
|
||||||
exu.io.dec_i0_rs2_bypass_data_d := dec.io.dec_i0_rs2_bypass_data_d
|
|
||||||
exu.io.dec_i0_br_immed_d := dec.io.dec_i0_br_immed_d
|
|
||||||
exu.io.dec_i0_alu_decode_d := dec.io.dec_i0_alu_decode_d
|
|
||||||
exu.io.dec_i0_select_pc_d := dec.io.dec_i0_select_pc_d
|
|
||||||
exu.io.dec_i0_pc_d := dec.io.dec_i0_pc_d
|
|
||||||
exu.io.dec_i0_rs1_bypass_en_d := dec.io.dec_i0_rs1_bypass_en_d
|
|
||||||
exu.io.dec_i0_rs2_bypass_en_d := dec.io.dec_i0_rs2_bypass_en_d
|
|
||||||
exu.io.dec_csr_ren_d := dec.io.dec_csr_ren_d
|
|
||||||
exu.io.mul_p <> dec.io.mul_p
|
|
||||||
exu.io.div_p <> dec.io.div_p
|
|
||||||
exu.io.dec_div_cancel := dec.io.dec_div_cancel
|
|
||||||
exu.io.pred_correct_npc_x := dec.io.pred_correct_npc_x
|
|
||||||
exu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
|
|
||||||
exu.io.dec_tlu_flush_path_r := dec.io.dec_tlu_flush_path_r
|
|
||||||
exu.io.dec_extint_stall := dec.io.dec_extint_stall
|
|
||||||
exu.io.dec_tlu_meihap := dec.io.dec_tlu_meihap
|
|
||||||
|
|
||||||
|
|
||||||
// LSU Lets go
|
|
||||||
lsu.reset := io.core_rst_l
|
|
||||||
lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
|
|
||||||
lsu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r
|
|
||||||
lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
|
|
||||||
lsu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt
|
|
||||||
lsu.io.dec_tlu_external_ldfwd_disable := dec.io.dec_tlu_external_ldfwd_disable
|
|
||||||
lsu.io.dec_tlu_wb_coalescing_disable := dec.io.dec_tlu_wb_coalescing_disable
|
|
||||||
lsu.io.dec_tlu_sideeffect_posted_disable := dec.io.dec_tlu_sideeffect_posted_disable
|
|
||||||
lsu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
|
|
||||||
lsu.io.exu_lsu_rs1_d := exu.io.exu_lsu_rs1_d
|
|
||||||
lsu.io.exu_lsu_rs2_d := exu.io.exu_lsu_rs2_d
|
|
||||||
lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
|
|
||||||
lsu.io.lsu_p <> dec.io.lsu_p
|
|
||||||
lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
|
|
||||||
lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff
|
|
||||||
lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
|
|
||||||
lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo
|
|
||||||
lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi
|
|
||||||
lsu.io.lsu_axi_awready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_awready)
|
|
||||||
lsu.io.lsu_axi_wready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_wready)
|
|
||||||
lsu.io.lsu_axi_bvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bvalid)
|
|
||||||
lsu.io.lsu_axi_bresp := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bresp)
|
|
||||||
lsu.io.lsu_axi_bid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_bid)
|
|
||||||
lsu.io.lsu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_arready)
|
|
||||||
lsu.io.lsu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rvalid)
|
|
||||||
lsu.io.lsu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rid)
|
|
||||||
lsu.io.lsu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rdata)
|
|
||||||
lsu.io.lsu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rresp)
|
|
||||||
lsu.io.lsu_axi_rlast := Mux(BUILD_AHB_LITE.B, 0.U, io.lsu_axi_rlast)
|
|
||||||
lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
|
||||||
lsu.io.dma_dccm_req := dma_ctrl.io.dma_dccm_req
|
|
||||||
lsu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag
|
|
||||||
lsu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr
|
|
||||||
lsu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz
|
|
||||||
lsu.io.dma_mem_write := dma_ctrl.io.dma_mem_write
|
|
||||||
lsu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata
|
|
||||||
lsu.io.scan_mode := io.scan_mode
|
|
||||||
lsu.io.free_clk := free_clk
|
|
||||||
|
|
||||||
// Debug lets go
|
|
||||||
dbg.reset := io.core_rst_l
|
|
||||||
dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
|
||||||
dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
|
||||||
dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
|
||||||
dbg.io.dma_dbg_ready := dma_ctrl.io.dma_dbg_ready
|
|
||||||
dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
|
|
||||||
dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
|
|
||||||
dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
|
|
||||||
dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
|
|
||||||
dbg.io.dmi_reg_en := io.dmi_reg_en
|
|
||||||
dbg.io.dmi_reg_addr := io.dmi_reg_addr
|
|
||||||
dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
|
|
||||||
dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
|
|
||||||
dbg.io.sb_axi_awready := io.sb_axi_awready
|
|
||||||
dbg.io.sb_axi_wready := io.sb_axi_wready
|
|
||||||
dbg.io.sb_axi_bvalid := io.sb_axi_bvalid
|
|
||||||
dbg.io.sb_axi_bresp := io.sb_axi_bresp
|
|
||||||
dbg.io.sb_axi_arready := io.sb_axi_arready
|
|
||||||
dbg.io.sb_axi_rvalid := io.sb_axi_rvalid
|
|
||||||
dbg.io.sb_axi_rdata := io.sb_axi_rdata
|
|
||||||
dbg.io.sb_axi_rresp := io.sb_axi_rresp
|
|
||||||
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
|
||||||
dbg.io.dbg_rst_l := io.dbg_rst_l
|
|
||||||
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
|
||||||
dbg.io.scan_mode := io.scan_mode
|
|
||||||
|
|
||||||
|
|
||||||
// DMA Lets go
|
|
||||||
dma_ctrl.reset := io.core_rst_l
|
|
||||||
dma_ctrl.io.free_clk := free_clk
|
|
||||||
dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
|
|
||||||
dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
|
||||||
dma_ctrl.io.scan_mode := io.scan_mode
|
|
||||||
dma_ctrl.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr
|
|
||||||
dma_ctrl.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata
|
|
||||||
dma_ctrl.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid
|
|
||||||
dma_ctrl.io.dbg_cmd_write := dbg.io.dbg_cmd_write
|
|
||||||
dma_ctrl.io.dbg_cmd_type := dbg.io.dbg_cmd_type
|
|
||||||
dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
|
|
||||||
dma_ctrl.io.dbg_dma_bubble := dbg.io.dbg_dma_bubble
|
|
||||||
dma_ctrl.io.dccm_dma_rvalid := lsu.io.dccm_dma_rvalid
|
|
||||||
dma_ctrl.io.dccm_dma_ecc_error := lsu.io.dccm_dma_ecc_error
|
|
||||||
dma_ctrl.io.dccm_dma_rtag := lsu.io.dccm_dma_rtag
|
|
||||||
dma_ctrl.io.dccm_dma_rdata := lsu.io.dccm_dma_rdata
|
|
||||||
dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
|
|
||||||
dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
|
|
||||||
dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
|
|
||||||
dma_ctrl.io.dccm_ready := lsu.io.dccm_ready
|
|
||||||
dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
|
|
||||||
dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty
|
|
||||||
dma_ctrl.io.dma_axi_awvalid := io.dma_axi_awvalid
|
|
||||||
dma_ctrl.io.dma_axi_awid := io.dma_axi_awid
|
|
||||||
dma_ctrl.io.dma_axi_awaddr := io.dma_axi_awaddr
|
|
||||||
dma_ctrl.io.dma_axi_awsize := io.dma_axi_awsize
|
|
||||||
dma_ctrl.io.dma_axi_wvalid := io.dma_axi_wvalid
|
|
||||||
dma_ctrl.io.dma_axi_wdata := io.dma_axi_wdata
|
|
||||||
dma_ctrl.io.dma_axi_wstrb := io.dma_axi_wstrb
|
|
||||||
dma_ctrl.io.dma_axi_bready := io.dma_axi_bready
|
|
||||||
dma_ctrl.io.dma_axi_arvalid := io.dma_axi_arvalid
|
|
||||||
dma_ctrl.io.dma_axi_arid := io.dma_axi_arid
|
|
||||||
dma_ctrl.io.dma_axi_araddr := io.dma_axi_araddr
|
|
||||||
dma_ctrl.io.dma_axi_arsize := io.dma_axi_arsize
|
|
||||||
dma_ctrl.io.dma_axi_rready := io.dma_axi_rready
|
|
||||||
dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
|
|
||||||
|
|
||||||
|
|
||||||
// PIC lets go
|
|
||||||
pic_ctl_inst.io.scan_mode := io.scan_mode
|
|
||||||
pic_ctl_inst.reset := io.core_rst_l
|
|
||||||
pic_ctl_inst.io.free_clk := free_clk
|
|
||||||
pic_ctl_inst.io.active_clk := active_clk
|
|
||||||
pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
|
||||||
pic_ctl_inst.io.extintsrc_req := io.extintsrc_req
|
|
||||||
pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr
|
|
||||||
pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr
|
|
||||||
pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data
|
|
||||||
pic_ctl_inst.io.picm_wren := lsu.io.picm_wren
|
|
||||||
pic_ctl_inst.io.picm_rden := lsu.io.picm_rden
|
|
||||||
pic_ctl_inst.io.picm_mken := lsu.io.picm_mken
|
|
||||||
pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl
|
|
||||||
pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt
|
|
||||||
lsu.io.picm_rd_data := pic_ctl_inst.io.picm_rd_data
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// Trace Packet
|
|
||||||
// ???
|
|
||||||
|
|
||||||
// Outputs
|
|
||||||
io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
|
|
||||||
io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
|
|
||||||
io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable
|
|
||||||
io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
|
|
||||||
io.o_cpu_halt_status := dec.io.o_cpu_halt_status
|
|
||||||
io.o_cpu_run_ack := dec.io.o_cpu_run_ack
|
|
||||||
io.o_debug_mode_status := dec.io.o_debug_mode_status
|
|
||||||
io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
|
|
||||||
io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
|
|
||||||
io.debug_brkpt_status := dec.io.debug_brkpt_status
|
|
||||||
io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
|
|
||||||
io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
|
|
||||||
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
|
|
||||||
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
|
|
||||||
// LSU Outputs
|
|
||||||
io.dccm_wren := lsu.io.dccm_wren
|
|
||||||
io.dccm_rden := lsu.io.dccm_rden
|
|
||||||
io.dccm_wr_addr_lo := lsu.io.dccm_wr_addr_lo
|
|
||||||
io.dccm_wr_addr_hi := lsu.io.dccm_wr_addr_hi
|
|
||||||
io.dccm_rd_addr_lo := lsu.io.dccm_rd_addr_lo
|
|
||||||
io.dccm_rd_addr_hi := lsu.io.dccm_rd_addr_hi
|
|
||||||
io.dccm_wr_data_lo := lsu.io.dccm_wr_data_lo
|
|
||||||
io.dccm_wr_data_hi := lsu.io.dccm_wr_data_hi
|
|
||||||
// IFU Outputs
|
|
||||||
io.iccm_rw_addr := ifu.io.iccm_rw_addr
|
|
||||||
io.iccm_wren := ifu.io.iccm_wren
|
|
||||||
io.iccm_rden := ifu.io.iccm_rden
|
|
||||||
io.iccm_wr_size := ifu.io.iccm_wr_size
|
|
||||||
io.iccm_wr_data := ifu.io.iccm_wr_data
|
|
||||||
io.iccm_buf_correct_ecc := ifu.io.iccm_buf_correct_ecc
|
|
||||||
io.iccm_correction_state := ifu.io.iccm_correction_state
|
|
||||||
io.ic_rw_addr := ifu.io.ic_rw_addr
|
|
||||||
io.ic_tag_valid := ifu.io.ic_tag_valid
|
|
||||||
io.ic_wr_en := ifu.io.ic_wr_en
|
|
||||||
io.ic_rd_en := ifu.io.ic_rd_en
|
|
||||||
io.ic_wr_data := ifu.io.ic_wr_data
|
|
||||||
io.ic_debug_wr_data := ifu.io.ic_debug_wr_data
|
|
||||||
io.ic_premux_data := ifu.io.ic_premux_data
|
|
||||||
io.ic_sel_premux_data := ifu.io.ic_sel_premux_data
|
|
||||||
io.ic_debug_addr := ifu.io.ic_debug_addr
|
|
||||||
io.ic_debug_rd_en := ifu.io.ic_debug_rd_en
|
|
||||||
io.ic_debug_wr_en := ifu.io.ic_debug_wr_en
|
|
||||||
io.ic_debug_tag_array := ifu.io.ic_debug_tag_array
|
|
||||||
io.ic_debug_way := ifu.io.ic_debug_way
|
|
||||||
|
|
||||||
// AXI LSU SIDE
|
|
||||||
io.lsu_axi_awvalid := lsu.io.lsu_axi_awvalid
|
|
||||||
io.lsu_axi_awid := lsu.io.lsu_axi_awid
|
|
||||||
io.lsu_axi_awaddr := lsu.io.lsu_axi_awaddr
|
|
||||||
io.lsu_axi_awregion := lsu.io.lsu_axi_awregion
|
|
||||||
io.lsu_axi_awlen := lsu.io.lsu_axi_awlen
|
|
||||||
io.lsu_axi_awsize := lsu.io.lsu_axi_awsize
|
|
||||||
io.lsu_axi_awburst := lsu.io.lsu_axi_awburst
|
|
||||||
io.lsu_axi_awlock := lsu.io.lsu_axi_awlock
|
|
||||||
io.lsu_axi_awcache := lsu.io.lsu_axi_awcache
|
|
||||||
io.lsu_axi_awprot := lsu.io.lsu_axi_awprot
|
|
||||||
io.lsu_axi_awqos := lsu.io.lsu_axi_awqos
|
|
||||||
io.lsu_axi_wvalid := lsu.io.lsu_axi_wvalid
|
|
||||||
io.lsu_axi_wdata := lsu.io.lsu_axi_wdata
|
|
||||||
io.lsu_axi_wstrb := lsu.io.lsu_axi_wstrb
|
|
||||||
io.lsu_axi_wlast := lsu.io.lsu_axi_wlast
|
|
||||||
io.lsu_axi_bready := lsu.io.lsu_axi_bready
|
|
||||||
io.lsu_axi_arvalid := lsu.io.lsu_axi_arvalid
|
|
||||||
io.lsu_axi_arid := lsu.io.lsu_axi_arid
|
|
||||||
io.lsu_axi_araddr := lsu.io.lsu_axi_araddr
|
|
||||||
io.lsu_axi_arregion := lsu.io.lsu_axi_arregion
|
|
||||||
io.lsu_axi_arlen := lsu.io.lsu_axi_arlen
|
|
||||||
io.lsu_axi_arsize := lsu.io.lsu_axi_arsize
|
|
||||||
io.lsu_axi_arburst := lsu.io.lsu_axi_arburst
|
|
||||||
io.lsu_axi_arlock := lsu.io.lsu_axi_arlock
|
|
||||||
io.lsu_axi_arcache := lsu.io.lsu_axi_arcache
|
|
||||||
io.lsu_axi_arprot := lsu.io.lsu_axi_arprot
|
|
||||||
io.lsu_axi_arqos := lsu.io.lsu_axi_arqos
|
|
||||||
io.lsu_axi_rready := lsu.io.lsu_axi_rready
|
|
||||||
|
|
||||||
// AXI IFU
|
|
||||||
io.ifu_axi_awvalid := ifu.io.ifu_axi_awvalid
|
|
||||||
io.ifu_axi_awid := ifu.io.ifu_axi_awid
|
|
||||||
io.ifu_axi_awaddr := ifu.io.ifu_axi_awaddr
|
|
||||||
io.ifu_axi_awregion := ifu.io.ifu_axi_awregion
|
|
||||||
io.ifu_axi_awlen := ifu.io.ifu_axi_awlen
|
|
||||||
io.ifu_axi_awsize := ifu.io.ifu_axi_awsize
|
|
||||||
io.ifu_axi_awburst := ifu.io.ifu_axi_awburst
|
|
||||||
io.ifu_axi_awlock := ifu.io.ifu_axi_awlock
|
|
||||||
io.ifu_axi_awcache := ifu.io.ifu_axi_awcache
|
|
||||||
io.ifu_axi_awprot := ifu.io.ifu_axi_awprot
|
|
||||||
io.ifu_axi_awqos := ifu.io.ifu_axi_awqos
|
|
||||||
io.ifu_axi_wvalid := ifu.io.ifu_axi_wvalid
|
|
||||||
io.ifu_axi_wdata := ifu.io.ifu_axi_wdata
|
|
||||||
io.ifu_axi_wstrb := ifu.io.ifu_axi_wstrb
|
|
||||||
io.ifu_axi_wlast := ifu.io.ifu_axi_wlast
|
|
||||||
io.ifu_axi_bready := ifu.io.ifu_axi_bready
|
|
||||||
io.ifu_axi_arvalid := ifu.io.ifu_axi_arvalid
|
|
||||||
io.ifu_axi_arid := ifu.io.ifu_axi_arid
|
|
||||||
io.ifu_axi_araddr := ifu.io.ifu_axi_araddr
|
|
||||||
io.ifu_axi_arregion := ifu.io.ifu_axi_arregion
|
|
||||||
io.ifu_axi_arlen := ifu.io.ifu_axi_arlen
|
|
||||||
io.ifu_axi_arsize := ifu.io.ifu_axi_arsize
|
|
||||||
io.ifu_axi_arburst := ifu.io.ifu_axi_arburst
|
|
||||||
io.ifu_axi_arlock := ifu.io.ifu_axi_arlock
|
|
||||||
io.ifu_axi_arcache := ifu.io.ifu_axi_arcache
|
|
||||||
io.ifu_axi_arprot := ifu.io.ifu_axi_arprot
|
|
||||||
io.ifu_axi_arqos := ifu.io.ifu_axi_arqos
|
|
||||||
io.ifu_axi_rready := ifu.io.ifu_axi_rready
|
|
||||||
|
|
||||||
|
|
||||||
// AXI SB Signals
|
|
||||||
io.sb_axi_awvalid := dbg.io.sb_axi_awvalid
|
|
||||||
io.sb_axi_awid := dbg.io.sb_axi_awid
|
|
||||||
io.sb_axi_awaddr := dbg.io.sb_axi_awaddr
|
|
||||||
io.sb_axi_awregion := dbg.io.sb_axi_awregion
|
|
||||||
io.sb_axi_awlen := dbg.io.sb_axi_awlen
|
|
||||||
io.sb_axi_awsize := dbg.io.sb_axi_awsize
|
|
||||||
io.sb_axi_awburst := dbg.io.sb_axi_awburst
|
|
||||||
io.sb_axi_awlock := dbg.io.sb_axi_awlock
|
|
||||||
io.sb_axi_awcache := dbg.io.sb_axi_awcache
|
|
||||||
io.sb_axi_awprot := dbg.io.sb_axi_awprot
|
|
||||||
io.sb_axi_awqos := dbg.io.sb_axi_awqos
|
|
||||||
io.sb_axi_wvalid := dbg.io.sb_axi_wvalid
|
|
||||||
io.sb_axi_wdata := dbg.io.sb_axi_wdata
|
|
||||||
io.sb_axi_wstrb := dbg.io.sb_axi_wstrb
|
|
||||||
io.sb_axi_wlast := dbg.io.sb_axi_wlast
|
|
||||||
io.sb_axi_bready := dbg.io.sb_axi_bready
|
|
||||||
io.sb_axi_arvalid := dbg.io.sb_axi_arvalid
|
|
||||||
io.sb_axi_arid := dbg.io.sb_axi_arid
|
|
||||||
io.sb_axi_araddr := dbg.io.sb_axi_araddr
|
|
||||||
io.sb_axi_arregion := dbg.io.sb_axi_arregion
|
|
||||||
io.sb_axi_arlen := dbg.io.sb_axi_arlen
|
|
||||||
io.sb_axi_arsize := dbg.io.sb_axi_arsize
|
|
||||||
io.sb_axi_arburst := dbg.io.sb_axi_arburst
|
|
||||||
io.sb_axi_arlock := dbg.io.sb_axi_arlock
|
|
||||||
io.sb_axi_arcache := dbg.io.sb_axi_arcache
|
|
||||||
io.sb_axi_arprot := dbg.io.sb_axi_arprot
|
|
||||||
io.sb_axi_arqos := dbg.io.sb_axi_arqos
|
|
||||||
io.sb_axi_rready := dbg.io.sb_axi_rready
|
|
||||||
|
|
||||||
// DMA Output Signals
|
|
||||||
io.dma_axi_awready := dma_ctrl.io.dma_axi_awready
|
|
||||||
io.dma_axi_wready := dma_ctrl.io.dma_axi_wready
|
|
||||||
io.dma_axi_bvalid := dma_ctrl.io.dma_axi_bvalid
|
|
||||||
io.dma_axi_bresp := dma_ctrl.io.dma_axi_bresp
|
|
||||||
io.dma_axi_bid := dma_ctrl.io.dma_axi_bid
|
|
||||||
io.dma_axi_arready := dma_ctrl.io.dma_axi_arready
|
|
||||||
io.dma_axi_rvalid := dma_ctrl.io.dma_axi_rvalid
|
|
||||||
io.dma_axi_rid := dma_ctrl.io.dma_axi_rid
|
|
||||||
io.dma_axi_rdata := dma_ctrl.io.dma_axi_rdata
|
|
||||||
io.dma_axi_rresp := dma_ctrl.io.dma_axi_rresp
|
|
||||||
io.dma_axi_rlast := dma_ctrl.io.dma_axi_rlast
|
|
||||||
|
|
||||||
// AHB Signals
|
|
||||||
io.hburst := 0.U
|
|
||||||
io.hmastlock := 0.U
|
|
||||||
io.hprot := 0.U
|
|
||||||
io.hsize := 0.U
|
|
||||||
io.htrans := 0.U
|
|
||||||
io.hwrite := 0.U
|
|
||||||
io.haddr := 0.U
|
|
||||||
|
|
||||||
io.lsu_haddr := 0.U
|
|
||||||
io.lsu_hburst := 0.U
|
|
||||||
io.lsu_hmastlock := 0.U
|
|
||||||
io.lsu_hprot := 0.U
|
|
||||||
io.lsu_hsize := 0.U
|
|
||||||
io.lsu_htrans := 0.U
|
|
||||||
io.lsu_hwrite := 0.U
|
|
||||||
io.lsu_hwdata := 0.U
|
|
||||||
|
|
||||||
|
|
||||||
io.sb_haddr := 0.U
|
|
||||||
io.sb_hburst := 0.U
|
|
||||||
io.sb_hmastlock := 0.U
|
|
||||||
io.sb_hprot := 0.U
|
|
||||||
io.sb_hsize := 0.U
|
|
||||||
io.sb_htrans := 0.U
|
|
||||||
io.sb_hwrite := 0.U
|
|
||||||
io.sb_hwdata := 0.U
|
|
||||||
|
|
||||||
io.dma_hrdata := 0.U
|
|
||||||
io.dma_hreadyout := 0.U
|
|
||||||
io.dma_hresp := 0.U
|
|
||||||
|
|
||||||
io.ifu_axi_wready := 0.U
|
|
||||||
|
|
||||||
io.dma_hresp := 0.U //dbg.io.dma_hresp
|
|
||||||
|
|
||||||
io.dmi_reg_rdata := 0.U
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
object SWERV extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_swerv()))
|
|
||||||
}
|
|
|
@ -1,295 +0,0 @@
|
||||||
package exu
|
|
||||||
import chisel3._
|
|
||||||
import scala.collection._
|
|
||||||
import chisel3.util._
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|
||||||
val io=IO(new el2_exu_IO)
|
|
||||||
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
|
|
||||||
val ghr_x_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
|
||||||
val ghr_d_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
|
||||||
val ghr_d = Wire(UInt(BHT_GHR_SIZE.W))
|
|
||||||
val i0_taken_d =Wire(UInt(1.W))
|
|
||||||
val mul_valid_x =Wire(UInt(1.W))
|
|
||||||
val i0_valid_d =Wire(UInt(1.W))
|
|
||||||
val flush_lower_ff =Wire(UInt(1.W))
|
|
||||||
val data_gate_en =Wire(UInt(1.W))
|
|
||||||
val csr_rs1_in_d =Wire(UInt(32.W))
|
|
||||||
val i0_predict_newp_d =Wire(new el2_predict_pkt_t)
|
|
||||||
val i0_flush_path_d =Wire(UInt(32.W))
|
|
||||||
val i0_predict_p_d =Wire(new el2_predict_pkt_t)
|
|
||||||
val i0_pp_r =Wire(new el2_predict_pkt_t)
|
|
||||||
val i0_predict_p_x =Wire(new el2_predict_pkt_t)
|
|
||||||
val final_predict_mp =Wire(new el2_predict_pkt_t)
|
|
||||||
val pred_correct_npc_r =Wire(UInt(32.W))
|
|
||||||
val i0_pred_correct_upper_d =Wire(UInt(1.W))
|
|
||||||
val i0_flush_upper_d =Wire(UInt(1.W))
|
|
||||||
io.exu_mp_pkt.prett :=0.U
|
|
||||||
io.exu_mp_pkt.br_start_error:=0.U
|
|
||||||
io.exu_mp_pkt.br_error :=0.U
|
|
||||||
io.exu_mp_pkt.valid :=0.U
|
|
||||||
val x_data_en = io.dec_data_en(1)
|
|
||||||
val r_data_en = io.dec_data_en(0)
|
|
||||||
val x_ctl_en = io.dec_ctl_en(1)
|
|
||||||
val r_ctl_en = io.dec_ctl_en(0)
|
|
||||||
val predpipe_d = Cat(io.i0_predict_fghr_d, io.i0_predict_index_d, io.i0_predict_btag_d)
|
|
||||||
|
|
||||||
|
|
||||||
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode)
|
|
||||||
io.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode)
|
|
||||||
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode)
|
|
||||||
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
|
|
||||||
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
|
|
||||||
val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val pred_temp1 =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode)
|
|
||||||
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode)
|
|
||||||
val pred_temp2 =rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode)
|
|
||||||
pred_correct_npc_r :=Cat(pred_temp2,pred_temp1)
|
|
||||||
|
|
||||||
when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){
|
|
||||||
ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)
|
|
||||||
mul_valid_x :=RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool)
|
|
||||||
flush_lower_ff :=RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
|
|
||||||
}.otherwise{
|
|
||||||
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
|
|
||||||
mul_valid_x :=rvdffe(io.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
|
|
||||||
flush_lower_ff :=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.mul_p.valid =/= mul_valid_x) | ( io.dec_tlu_flush_lower_r =/= flush_lower_ff)
|
|
||||||
val i0_rs1_bypass_en_d = io.dec_i0_rs1_bypass_en_d(0) | io.dec_i0_rs1_bypass_en_d(1)
|
|
||||||
val i0_rs2_bypass_en_d = io.dec_i0_rs2_bypass_en_d(0) | io.dec_i0_rs2_bypass_en_d(1)
|
|
||||||
|
|
||||||
val i0_rs1_bypass_data_d = Mux1H(Seq(
|
|
||||||
io.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_i0_rs1_bypass_data_d,
|
|
||||||
io.dec_i0_rs1_bypass_en_d(1).asBool -> io.exu_i0_result_x
|
|
||||||
))
|
|
||||||
|
|
||||||
val i0_rs2_bypass_data_d = Mux1H(Seq(
|
|
||||||
io.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_i0_rs2_bypass_data_d,
|
|
||||||
io.dec_i0_rs2_bypass_en_d(1).asBool -> io.exu_i0_result_x
|
|
||||||
))
|
|
||||||
|
|
||||||
val i0_rs1_d = Mux1H(Seq(
|
|
||||||
i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d,
|
|
||||||
(~i0_rs1_bypass_en_d & io.dec_i0_select_pc_d).asBool -> Cat(io.dec_i0_pc_d,0.U(1.W)),
|
|
||||||
(~i0_rs1_bypass_en_d & io.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
|
|
||||||
(~i0_rs1_bypass_en_d & ~io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d
|
|
||||||
))
|
|
||||||
|
|
||||||
val i0_rs2_d=Mux1H(Seq(
|
|
||||||
(~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
|
||||||
(~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
|
||||||
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
|
||||||
))
|
|
||||||
|
|
||||||
io.exu_lsu_rs1_d:=Mux1H(Seq(
|
|
||||||
(~i0_rs1_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
|
||||||
(i0_rs1_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs1_bypass_data_d,
|
|
||||||
(io.dec_extint_stall).asBool -> Cat(io.dec_tlu_meihap,0.U(2.W))
|
|
||||||
))
|
|
||||||
|
|
||||||
io.exu_lsu_rs2_d:=Mux1H(Seq(
|
|
||||||
(~i0_rs2_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
|
||||||
(i0_rs2_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs2_bypass_data_d
|
|
||||||
))
|
|
||||||
|
|
||||||
val muldiv_rs1_d=Mux1H(Seq(
|
|
||||||
(~i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
|
||||||
(i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d
|
|
||||||
))
|
|
||||||
|
|
||||||
val muldiv_rs2_d=Mux1H(Seq(
|
|
||||||
(~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
|
||||||
(~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
|
||||||
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
|
||||||
))
|
|
||||||
|
|
||||||
csr_rs1_in_d := Mux( io.dec_csr_ren_d.asBool, i0_rs1_d, io.exu_csr_rs1_x)
|
|
||||||
|
|
||||||
|
|
||||||
val i_alu=Module(new el2_exu_alu_ctl)
|
|
||||||
i_alu.io.scan_mode :=io.scan_mode
|
|
||||||
i_alu.io.enable :=x_ctl_en
|
|
||||||
i_alu.io.pp_in :=i0_predict_newp_d
|
|
||||||
i_alu.io.valid_in :=io.dec_i0_alu_decode_d
|
|
||||||
i_alu.io.flush_upper_x :=i0_flush_upper_x
|
|
||||||
i_alu.io.flush_lower_r :=io.dec_tlu_flush_lower_r
|
|
||||||
i_alu.io.a_in :=i0_rs1_d.asSInt
|
|
||||||
i_alu.io.b_in :=i0_rs2_d
|
|
||||||
i_alu.io.pc_in :=io.dec_i0_pc_d
|
|
||||||
i_alu.io.brimm_in :=io.dec_i0_br_immed_d
|
|
||||||
i_alu.io.ap :=io.i0_ap
|
|
||||||
i_alu.io.csr_ren_in :=io.dec_csr_ren_d
|
|
||||||
val alu_result_x =i_alu.io.result_ff
|
|
||||||
i0_flush_upper_d :=i_alu.io.flush_upper_out
|
|
||||||
io.exu_flush_final :=i_alu.io.flush_final_out
|
|
||||||
i0_flush_path_d :=i_alu.io.flush_path_out
|
|
||||||
i0_predict_p_d :=i_alu.io.predict_p_out
|
|
||||||
i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
|
|
||||||
io.exu_i0_pc_x :=i_alu.io.pc_ff
|
|
||||||
|
|
||||||
val i_mul=Module(new el2_exu_mul_ctl)
|
|
||||||
i_mul.io.scan_mode :=io.scan_mode
|
|
||||||
i_mul.io.mul_p :=io.mul_p
|
|
||||||
i_mul.io.rs1_in :=muldiv_rs1_d
|
|
||||||
i_mul.io.rs2_in :=muldiv_rs2_d
|
|
||||||
val mul_result_x =i_mul.io.result_x
|
|
||||||
|
|
||||||
val i_div=Module(new el2_exu_div_ctl)
|
|
||||||
i_div.io.scan_mode :=io.scan_mode
|
|
||||||
i_div.io.cancel :=io.dec_div_cancel
|
|
||||||
i_div.io.dp :=io.div_p
|
|
||||||
i_div.io.dividend :=muldiv_rs1_d
|
|
||||||
i_div.io.divisor :=muldiv_rs2_d
|
|
||||||
io.exu_div_wren :=i_div.io.finish_dly
|
|
||||||
io.exu_div_result :=i_div.io.out
|
|
||||||
|
|
||||||
io.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x)
|
|
||||||
i0_predict_newp_d := io.dec_i0_predict_p_d
|
|
||||||
i0_predict_newp_d.boffset := io.dec_i0_pc_d(0) // from the start of inst
|
|
||||||
|
|
||||||
io.exu_pmu_i0_br_misp := i0_pp_r.misp
|
|
||||||
io.exu_pmu_i0_br_ataken := i0_pp_r.ataken
|
|
||||||
io.exu_pmu_i0_pc4 := i0_pp_r.pc4
|
|
||||||
|
|
||||||
|
|
||||||
i0_valid_d := i0_predict_p_d.valid & io.dec_i0_alu_decode_d & ~io.dec_tlu_flush_lower_r
|
|
||||||
i0_taken_d := (i0_predict_p_d.ataken & io.dec_i0_alu_decode_d)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// maintain GHR at D
|
|
||||||
ghr_d_ns:=Mux1H(Seq(
|
|
||||||
(~io.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
|
|
||||||
(~io.dec_tlu_flush_lower_r & ~i0_valid_d).asBool -> ghr_d,
|
|
||||||
(io.dec_tlu_flush_lower_r).asBool -> ghr_x
|
|
||||||
))
|
|
||||||
|
|
||||||
// maintain GHR at X
|
|
||||||
ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x )
|
|
||||||
|
|
||||||
io.exu_i0_br_valid_r := i0_pp_r.valid
|
|
||||||
io.exu_i0_br_mp_r := i0_pp_r.misp
|
|
||||||
io.exu_i0_br_way_r := i0_pp_r.way
|
|
||||||
io.exu_i0_br_hist_r := i0_pp_r.hist
|
|
||||||
io.exu_i0_br_error_r := i0_pp_r.br_error
|
|
||||||
io.exu_i0_br_middle_r := i0_pp_r.pc4 ^ i0_pp_r.boffset
|
|
||||||
io.exu_i0_br_start_error_r := i0_pp_r.br_start_error
|
|
||||||
io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
|
|
||||||
io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
|
|
||||||
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
|
|
||||||
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
|
|
||||||
|
|
||||||
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & ~(io.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
|
|
||||||
|
|
||||||
|
|
||||||
io.exu_mp_pkt.way := final_predict_mp.way
|
|
||||||
io.exu_mp_pkt.misp := final_predict_mp.misp
|
|
||||||
io.exu_mp_pkt.pcall := final_predict_mp.pcall
|
|
||||||
io.exu_mp_pkt.pja := final_predict_mp.pja
|
|
||||||
io.exu_mp_pkt.pret := final_predict_mp.pret
|
|
||||||
io.exu_mp_pkt.ataken := final_predict_mp.ataken
|
|
||||||
io.exu_mp_pkt.boffset := final_predict_mp.boffset
|
|
||||||
io.exu_mp_pkt.pc4 := final_predict_mp.pc4
|
|
||||||
io.exu_mp_pkt.hist := final_predict_mp.hist(1,0)
|
|
||||||
io.exu_mp_pkt.toffset := final_predict_mp.toffset(11,0)
|
|
||||||
io.exu_mp_fghr := after_flush_eghr
|
|
||||||
io.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE)
|
|
||||||
io.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0)
|
|
||||||
io.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write
|
|
||||||
io.exu_flush_path_final := Mux(io.dec_tlu_flush_lower_r.asBool, io.dec_tlu_flush_path_r, i0_flush_path_d)
|
|
||||||
io.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
|
|
||||||
}
|
|
||||||
class el2_exu_IO extends Bundle with param{
|
|
||||||
val scan_mode =Input(Bool()) // Scan control
|
|
||||||
|
|
||||||
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse
|
|
||||||
val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse
|
|
||||||
val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1
|
|
||||||
val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes}
|
|
||||||
|
|
||||||
val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1
|
|
||||||
val dec_i0_predict_p_d =Input(new el2_predict_pkt_t) // DEC branch predict packet
|
|
||||||
|
|
||||||
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
|
||||||
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
|
|
||||||
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
|
||||||
|
|
||||||
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
|
|
||||||
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
|
|
||||||
val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr
|
|
||||||
val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr
|
|
||||||
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
|
|
||||||
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
|
||||||
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
|
||||||
val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate
|
|
||||||
val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU
|
|
||||||
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
|
|
||||||
val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC
|
|
||||||
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
|
||||||
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
|
||||||
val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary
|
|
||||||
|
|
||||||
val mul_p =Input(new el2_mul_pkt_t) // DEC {valid, operand signs, low, operand bypass}
|
|
||||||
val div_p =Input(new el2_div_pkt_t) // DEC {valid, unsigned, rem}
|
|
||||||
val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation
|
|
||||||
|
|
||||||
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
|
|
||||||
|
|
||||||
val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs
|
|
||||||
val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target
|
|
||||||
|
|
||||||
|
|
||||||
val dec_extint_stall =Input(UInt(1.W)) // External stall mux select
|
|
||||||
val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data
|
|
||||||
|
|
||||||
|
|
||||||
val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand
|
|
||||||
val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand
|
|
||||||
|
|
||||||
val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle
|
|
||||||
val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source
|
|
||||||
|
|
||||||
val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC
|
|
||||||
val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC
|
|
||||||
val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction
|
|
||||||
|
|
||||||
val exu_npc_r =Output(UInt(31.W)) // Divide NPC
|
|
||||||
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
|
|
||||||
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
|
|
||||||
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
|
|
||||||
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
|
|
||||||
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
|
|
||||||
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
|
|
||||||
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
|
|
||||||
val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr
|
|
||||||
val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way
|
|
||||||
val exu_mp_pkt =Output(new el2_predict_pkt_t) // Mispredict branch packet
|
|
||||||
val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history
|
|
||||||
val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr
|
|
||||||
val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index
|
|
||||||
val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag
|
|
||||||
|
|
||||||
|
|
||||||
val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict
|
|
||||||
val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken
|
|
||||||
val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC
|
|
||||||
|
|
||||||
|
|
||||||
val exu_div_result =Output(UInt(32.W)) // Divide result
|
|
||||||
val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR
|
|
||||||
}
|
|
||||||
|
|
||||||
object exu_gen extends App{
|
|
||||||
println(chisel3.Driver.emitVerilog(new el2_exu()))
|
|
||||||
}
|
|
|
@ -1,134 +0,0 @@
|
||||||
package exu
|
|
||||||
|
|
||||||
import chisel3._
|
|
||||||
import chisel3.util._
|
|
||||||
import include._
|
|
||||||
import lib._
|
|
||||||
|
|
||||||
class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|
||||||
val io = IO(new Bundle{
|
|
||||||
////////// Inputs /////////
|
|
||||||
// val clk = Input(Clock()) // Top level clock
|
|
||||||
// val rst_l = Input(UInt(1.W)) // Reset
|
|
||||||
val scan_mode = Input(UInt(1.W)) // Scan control
|
|
||||||
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
|
|
||||||
val flush_lower_r = Input(UInt(1.W)) // Master flush of entire pipeline
|
|
||||||
val enable = Input(Bool()) // Clock enable
|
|
||||||
val valid_in = Input(UInt(1.W)) // Valid
|
|
||||||
val ap = Input( new el2_alu_pkt_t ) // predecodes
|
|
||||||
val csr_ren_in = Input(UInt(1.W)) // extra decode
|
|
||||||
val a_in = Input(SInt(32.W)) // A operand
|
|
||||||
val b_in = Input(UInt(32.W)) // B operand
|
|
||||||
val pc_in = Input(UInt(31.W)) // for pc=pc+2,4 calculations
|
|
||||||
val pp_in = Input(new el2_predict_pkt_t) // Predicted branch structure
|
|
||||||
val brimm_in = Input(UInt(12.W)) // Branch offset
|
|
||||||
////////// Outputs /////////
|
|
||||||
val result_ff = Output(UInt(32.W)) // final result
|
|
||||||
val flush_upper_out = Output(UInt(1.W)) // Branch flush
|
|
||||||
val flush_final_out = Output(UInt(1.W)) // Branch flush or flush entire pipeline
|
|
||||||
val flush_path_out = Output(UInt(31.W)) // Branch flush PC
|
|
||||||
val pc_ff = Output(UInt(31.W)) // flopped PC
|
|
||||||
val pred_correct_out = Output(UInt(1.W)) // NPC control
|
|
||||||
val predict_p_out = Output(new el2_predict_pkt_t) // Predicted branch structure
|
|
||||||
})
|
|
||||||
|
|
||||||
io.pc_ff := rvdffe(io.pc_in,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
|
|
||||||
val result = WireInit(UInt(32.W),0.U)
|
|
||||||
io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool)
|
|
||||||
|
|
||||||
val bm = Mux( io.ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified
|
|
||||||
|
|
||||||
val aout = WireInit(UInt(33.W),0.U)
|
|
||||||
aout := Mux(io.ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.ap.sub)))
|
|
||||||
val cout = aout(32)
|
|
||||||
|
|
||||||
val ov = (~io.a_in(31) & ~bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & ~aout(31) ) //overflow check from last bits
|
|
||||||
|
|
||||||
val eq = (io.a_in === io.b_in.asSInt)
|
|
||||||
val ne = ~eq
|
|
||||||
val neg = aout(31)// check for the last signed bit (for neg)
|
|
||||||
val lt = (~io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & ~cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
|
|
||||||
val ge = ~lt // if not less then
|
|
||||||
|
|
||||||
|
|
||||||
val lout = Mux1H(Seq(
|
|
||||||
io.csr_ren_in.asBool -> io.b_in.asSInt, //read enable read rs2
|
|
||||||
io.ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
|
|
||||||
io.ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
|
|
||||||
io.ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
|
|
||||||
|
|
||||||
val shift_amount = Mux1H(Seq (
|
|
||||||
io.ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
|
|
||||||
io.ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
|
|
||||||
io.ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ))
|
|
||||||
|
|
||||||
val shift_mask = WireInit(UInt(32.W),0.U)
|
|
||||||
shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.ap.sll) & io.b_in(4,0)) )
|
|
||||||
|
|
||||||
val shift_extend = WireInit(UInt(63.W),0.U)
|
|
||||||
shift_extend := Cat((repl(31,io.ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.ap.sll) & io.a_in(30,0)),io.a_in)
|
|
||||||
|
|
||||||
val shift_long = WireInit(UInt(63.W),0.U)
|
|
||||||
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused
|
|
||||||
|
|
||||||
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1
|
|
||||||
|
|
||||||
|
|
||||||
val sel_shift = io.ap.sll | io.ap.srl | io.ap.sra
|
|
||||||
val sel_adder = (io.ap.add | io.ap.sub) & ~io.ap.slt
|
|
||||||
val sel_pc = io.ap.jal | io.pp_in.pcall | io.pp_in.pja | io.pp_in.pret
|
|
||||||
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
|
|
||||||
|
|
||||||
val slt_one = io.ap.slt & lt
|
|
||||||
|
|
||||||
// for a conditional br pcout[] will be the opposite of the branch prediction
|
|
||||||
// for jal or pcall, it will be the link address pc+2 or pc+4
|
|
||||||
val pcout = rvbradder(Cat(io.pc_in,0.U),Cat(io.brimm_in,0.U))
|
|
||||||
|
|
||||||
result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq(
|
|
||||||
sel_shift.asBool -> sout(31,0),
|
|
||||||
sel_adder.asBool -> aout(31,0),
|
|
||||||
sel_pc.asBool -> pcout,
|
|
||||||
io.ap.csr_write.asBool -> csr_write_data(31,0))))
|
|
||||||
|
|
||||||
// *** branch handling ***
|
|
||||||
|
|
||||||
val any_jal = io.ap.jal | //jal
|
|
||||||
io.pp_in.pcall | //branch is a call inst
|
|
||||||
io.pp_in.pja | //branch is a jump always
|
|
||||||
io.pp_in.pret //return inst
|
|
||||||
|
|
||||||
val actual_taken = (io.ap.beq & eq) | (io.ap.bne & ne.asUInt) | (io.ap.blt & lt) | (io.ap.bge & ge) | any_jal
|
|
||||||
|
|
||||||
// pred_correct is for the npc logic
|
|
||||||
// pred_correct indicates not to use the flush_path
|
|
||||||
// for any_jal pred_correct==0
|
|
||||||
io.pred_correct_out := (io.valid_in & io.ap.predict_nt & !actual_taken & !any_jal) | (io.valid_in & io.ap.predict_t & actual_taken & !any_jal)
|
|
||||||
// for any_jal adder output is the flush path
|
|
||||||
io.flush_path_out := Mux(any_jal.asBool, aout(31,1), pcout(31,1))
|
|
||||||
|
|
||||||
// pcall and pret are included here
|
|
||||||
val cond_mispredict = (io.ap.predict_t & !actual_taken) | (io.ap.predict_nt & actual_taken.asUInt)
|
|
||||||
|
|
||||||
// target mispredicts on ret's
|
|
||||||
val target_mispredict = io.pp_in.pret & (io.pp_in.prett =/= aout(31,1)) //predicted return target != aout
|
|
||||||
|
|
||||||
io.flush_upper_out := (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x & !io.flush_lower_r
|
|
||||||
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
|
|
||||||
io.flush_final_out := ( (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x ) | io.flush_lower_r
|
|
||||||
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
|
||||||
|
|
||||||
val newhist = WireInit(UInt(2.W),0.U)
|
|
||||||
newhist := Cat((io.pp_in.hist(1) & io.pp_in.hist(0)) | (~io.pp_in.hist(0) & actual_taken),//newhist[1]
|
|
||||||
(~io.pp_in.hist(1) & ~actual_taken) | (io.pp_in.hist(1) & actual_taken)) //newhist[0]
|
|
||||||
|
|
||||||
io.predict_p_out := io.pp_in
|
|
||||||
io.predict_p_out.misp := ~io.flush_upper_x & ~io.flush_lower_r & (cond_mispredict | target_mispredict);// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
|
|
||||||
io.predict_p_out.ataken := actual_taken; // send a control signal telling it branch taken or not
|
|
||||||
io.predict_p_out.hist := newhist
|
|
||||||
}
|
|
||||||
|
|
||||||
object alu extends App{
|
|
||||||
chisel3.Driver execute(args, () =>new el2_exu_alu_ctl())
|
|
||||||
}
|
|
||||||
|
|
|
@ -0,0 +1,234 @@
|
||||||
|
package exu
|
||||||
|
import chisel3._
|
||||||
|
|
||||||
|
import scala.collection._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class exu extends Module with lib with RequireAsyncReset{
|
||||||
|
val io=IO(new Bundle{
|
||||||
|
|
||||||
|
val scan_mode = Input(Bool()) // Scan control
|
||||||
|
val dec_exu = new dec_exu()
|
||||||
|
val exu_bp = new exu_bp()
|
||||||
|
//ifc-bp-mem-aln-decode
|
||||||
|
val exu_flush_final = Output(UInt(1.W)) // Branch flush or flush entire pipeline
|
||||||
|
//gpr
|
||||||
|
val exu_div_result = Output(UInt(32.W)) // Divide result
|
||||||
|
val exu_div_wren = Output(UInt(1.W)) // Divide write enable to GPR
|
||||||
|
//debug
|
||||||
|
val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1
|
||||||
|
//lsu
|
||||||
|
val lsu_exu = Flipped(new lsu_exu())
|
||||||
|
//ifu_ifc
|
||||||
|
val exu_flush_path_final = Output(UInt(31.W)) // Target for the oldest flush source
|
||||||
|
|
||||||
|
})
|
||||||
|
|
||||||
|
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
|
||||||
|
val ghr_x_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
||||||
|
val ghr_d_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
||||||
|
val ghr_d = Wire(UInt(BHT_GHR_SIZE.W))
|
||||||
|
val i0_taken_d = Wire(UInt(1.W))
|
||||||
|
val mul_valid_x = Wire(UInt(1.W))
|
||||||
|
val i0_valid_d = Wire(UInt(1.W))
|
||||||
|
val flush_lower_ff = Wire(UInt(1.W))
|
||||||
|
val data_gate_en = Wire(UInt(1.W))
|
||||||
|
val csr_rs1_in_d = Wire(UInt(32.W))
|
||||||
|
val i0_predict_newp_d = Wire(Valid(new predict_pkt_t()))
|
||||||
|
val i0_flush_path_d = Wire(UInt(31.W))
|
||||||
|
val i0_predict_p_d = Wire(Valid(new predict_pkt_t()))
|
||||||
|
val i0_pp_r = Wire(Valid(new predict_pkt_t()))
|
||||||
|
val i0_predict_p_x = Wire(Valid(new predict_pkt_t()))
|
||||||
|
val final_predict_mp = Wire(Valid(new predict_pkt_t()))
|
||||||
|
val pred_correct_npc_r = Wire(UInt(32.W))
|
||||||
|
val i0_pred_correct_upper_d = Wire(UInt(1.W))
|
||||||
|
val i0_flush_upper_d = Wire(UInt(1.W))
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.prett :=0.U
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.br_start_error:=0.U
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.br_error :=0.U
|
||||||
|
io.exu_bp.exu_mp_pkt.valid :=0.U
|
||||||
|
i0_pp_r.bits.toffset := 0.U
|
||||||
|
|
||||||
|
val x_data_en = io.dec_exu.decode_exu.dec_data_en(1)
|
||||||
|
val r_data_en = io.dec_exu.decode_exu.dec_data_en(0)
|
||||||
|
val x_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(1)
|
||||||
|
val r_ctl_en = io.dec_exu.decode_exu.dec_ctl_en(0)
|
||||||
|
val predpipe_d = Cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d, io.dec_exu.decode_exu.i0_predict_btag_d)
|
||||||
|
|
||||||
|
|
||||||
|
val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode)
|
||||||
|
io.dec_exu.decode_exu.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode)
|
||||||
|
i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode)
|
||||||
|
val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode)
|
||||||
|
val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode)
|
||||||
|
val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val pred_temp1 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode)
|
||||||
|
val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode)
|
||||||
|
val pred_temp2 =rvdffe(io.dec_exu.decode_exu.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode)
|
||||||
|
pred_correct_npc_r :=Cat(pred_temp2,pred_temp1)
|
||||||
|
|
||||||
|
when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){
|
||||||
|
ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool)
|
||||||
|
mul_valid_x :=RegEnable(io.dec_exu.decode_exu.mul_p.valid,0.U,data_gate_en.asBool)
|
||||||
|
flush_lower_ff :=RegEnable(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool)
|
||||||
|
}.otherwise{
|
||||||
|
ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode)
|
||||||
|
mul_valid_x :=rvdffe(io.dec_exu.decode_exu.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode)
|
||||||
|
flush_lower_ff :=rvdffe(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode)
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.dec_exu.decode_exu.mul_p.valid =/= mul_valid_x) | ( io.dec_exu.tlu_exu.dec_tlu_flush_lower_r =/= flush_lower_ff)
|
||||||
|
val i0_rs1_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1)
|
||||||
|
val i0_rs2_bypass_en_d = io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0) | io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1)
|
||||||
|
|
||||||
|
val i0_rs1_bypass_data_d = Mux1H(Seq(
|
||||||
|
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d,
|
||||||
|
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x
|
||||||
|
))
|
||||||
|
|
||||||
|
val i0_rs2_bypass_data_d = Mux1H(Seq(
|
||||||
|
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d,
|
||||||
|
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d(1).asBool -> io.dec_exu.decode_exu.exu_i0_result_x
|
||||||
|
))
|
||||||
|
|
||||||
|
val i0_rs1_d = Mux1H(Seq(
|
||||||
|
i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d,
|
||||||
|
(!i0_rs1_bypass_en_d & io.dec_exu.decode_exu.dec_i0_select_pc_d).asBool -> Cat(io.dec_exu.ib_exu.dec_i0_pc_d,0.U(1.W)),
|
||||||
|
(!i0_rs1_bypass_en_d & io.dec_exu.ib_exu.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
|
||||||
|
(!i0_rs1_bypass_en_d & !io.dec_exu.ib_exu.dec_debug_wdata_rs1_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d
|
||||||
|
))
|
||||||
|
|
||||||
|
val i0_rs2_d = Mux1H(Seq(
|
||||||
|
(!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
|
||||||
|
(!i0_rs2_bypass_en_d).asBool -> io.dec_exu.decode_exu.dec_i0_immed_d,
|
||||||
|
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
||||||
|
))
|
||||||
|
dontTouch(i0_rs2_d)
|
||||||
|
|
||||||
|
io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq(
|
||||||
|
(!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
|
||||||
|
(i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs1_bypass_data_d,
|
||||||
|
(io.dec_exu.decode_exu.dec_extint_stall).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W))
|
||||||
|
))
|
||||||
|
|
||||||
|
io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq(
|
||||||
|
(!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
|
||||||
|
(i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall).asBool -> i0_rs2_bypass_data_d
|
||||||
|
))
|
||||||
|
|
||||||
|
val muldiv_rs1_d=Mux1H(Seq(
|
||||||
|
(!i0_rs1_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs1_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
|
||||||
|
(i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d
|
||||||
|
))
|
||||||
|
|
||||||
|
val muldiv_rs2_d=Mux1H(Seq(
|
||||||
|
(!i0_rs2_bypass_en_d & io.dec_exu.decode_exu.dec_i0_rs2_en_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
|
||||||
|
(!i0_rs2_bypass_en_d).asBool -> io.dec_exu.decode_exu.dec_i0_immed_d,
|
||||||
|
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
||||||
|
))
|
||||||
|
|
||||||
|
csr_rs1_in_d := Mux( io.dec_exu.dec_alu.dec_csr_ren_d.asBool, i0_rs1_d, io.dec_exu.decode_exu.exu_csr_rs1_x)
|
||||||
|
|
||||||
|
|
||||||
|
val i_alu=Module(new exu_alu_ctl)
|
||||||
|
i_alu.io.dec_alu <> io.dec_exu.dec_alu
|
||||||
|
i_alu.io.scan_mode :=io.scan_mode
|
||||||
|
i_alu.io.enable :=x_ctl_en
|
||||||
|
i_alu.io.pp_in :=i0_predict_newp_d
|
||||||
|
i_alu.io.flush_upper_x :=i0_flush_upper_x
|
||||||
|
i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||||
|
i_alu.io.a_in :=i0_rs1_d.asSInt
|
||||||
|
i_alu.io.b_in :=i0_rs2_d
|
||||||
|
i_alu.io.dec_i0_pc_d :=io.dec_exu.ib_exu.dec_i0_pc_d
|
||||||
|
i_alu.io.i0_ap :=io.dec_exu.decode_exu.i0_ap
|
||||||
|
val alu_result_x =i_alu.io.result_ff
|
||||||
|
i0_flush_upper_d :=i_alu.io.flush_upper_out
|
||||||
|
i0_flush_path_d :=i_alu.io.flush_path_out
|
||||||
|
io.exu_flush_final := i_alu.io.flush_final_out
|
||||||
|
i0_predict_p_d :=i_alu.io.predict_p_out
|
||||||
|
i0_pred_correct_upper_d :=i_alu.io.pred_correct_out
|
||||||
|
|
||||||
|
val i_mul=Module(new exu_mul_ctl)
|
||||||
|
i_mul.io.scan_mode :=io.scan_mode
|
||||||
|
i_mul.io.mul_p :=io.dec_exu.decode_exu.mul_p
|
||||||
|
i_mul.io.rs1_in :=muldiv_rs1_d
|
||||||
|
i_mul.io.rs2_in :=muldiv_rs2_d
|
||||||
|
val mul_result_x =i_mul.io.result_x
|
||||||
|
|
||||||
|
val i_div=Module(new exu_div_ctl)
|
||||||
|
i_div.io.dec_div <> io.dec_exu.dec_div
|
||||||
|
i_div.io.scan_mode :=io.scan_mode
|
||||||
|
|
||||||
|
i_div.io.dividend :=muldiv_rs1_d
|
||||||
|
i_div.io.divisor :=muldiv_rs2_d
|
||||||
|
io.exu_div_wren :=i_div.io.exu_div_wren
|
||||||
|
io.exu_div_result :=i_div.io.exu_div_result
|
||||||
|
|
||||||
|
io.dec_exu.decode_exu.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x)
|
||||||
|
i0_predict_newp_d := io.dec_exu.decode_exu.dec_i0_predict_p_d
|
||||||
|
i0_predict_newp_d.bits.boffset := io.dec_exu.ib_exu.dec_i0_pc_d(0) // from the start of inst
|
||||||
|
|
||||||
|
io.dec_exu.tlu_exu.exu_pmu_i0_br_misp := i0_pp_r.bits.misp
|
||||||
|
io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken := i0_pp_r.bits.ataken
|
||||||
|
io.dec_exu.tlu_exu.exu_pmu_i0_pc4 := i0_pp_r.bits.pc4
|
||||||
|
|
||||||
|
|
||||||
|
i0_valid_d := i0_predict_p_d.valid & io.dec_exu.dec_alu.dec_i0_alu_decode_d & !io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||||
|
i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_exu.dec_alu.dec_i0_alu_decode_d)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// maintain GHR at D
|
||||||
|
ghr_d_ns:=Mux1H(Seq(
|
||||||
|
(!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
|
||||||
|
(!io.dec_exu.tlu_exu.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d,
|
||||||
|
(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r).asBool -> ghr_x
|
||||||
|
))
|
||||||
|
|
||||||
|
// maintain GHR at X
|
||||||
|
ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x )
|
||||||
|
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_valid_r := i0_pp_r.valid
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_mp_r := i0_pp_r.bits.misp
|
||||||
|
io.exu_bp.exu_i0_br_way_r := i0_pp_r.bits.way
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_hist_r := i0_pp_r.bits.hist
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_error_r := i0_pp_r.bits.br_error
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error
|
||||||
|
io.exu_bp.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
|
||||||
|
io.dec_exu.tlu_exu.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
|
||||||
|
io.exu_bp.exu_i0_br_index_r := io.dec_exu.tlu_exu.exu_i0_br_index_r
|
||||||
|
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
|
||||||
|
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
|
||||||
|
|
||||||
|
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
|
||||||
|
|
||||||
|
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.way := final_predict_mp.bits.way
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.pja := final_predict_mp.bits.pja
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.pret := final_predict_mp.bits.pret
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1,0)
|
||||||
|
io.exu_bp.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11,0)
|
||||||
|
io.exu_bp.exu_mp_fghr := after_flush_eghr
|
||||||
|
io.exu_bp.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE)
|
||||||
|
io.exu_bp.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0)
|
||||||
|
io.exu_bp.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write
|
||||||
|
io.exu_flush_path_final := Mux(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r.asBool, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, i0_flush_path_d)
|
||||||
|
io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
|
||||||
|
}
|
|
@ -0,0 +1,126 @@
|
||||||
|
package exu
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
class exu_alu_ctl extends Module with lib with RequireAsyncReset{
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
val dec_alu = new dec_alu()
|
||||||
|
|
||||||
|
val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations
|
||||||
|
val scan_mode = Input(UInt(1.W)) // Scan control
|
||||||
|
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
|
||||||
|
val dec_tlu_flush_lower_r = Input(UInt(1.W)) // Master flush of entire pipeline
|
||||||
|
val enable = Input(Bool()) // Clock enable
|
||||||
|
val i0_ap = Input( new alu_pkt_t ) // predecodes
|
||||||
|
val a_in = Input(SInt(32.W)) // A operand
|
||||||
|
val b_in = Input(UInt(32.W)) // B operand
|
||||||
|
val pp_in = Flipped(Valid(new predict_pkt_t)) // Predicted branch structure
|
||||||
|
////////// Outputs /////////
|
||||||
|
val result_ff = Output(UInt(32.W)) // final result
|
||||||
|
val flush_upper_out = Output(UInt(1.W)) // Branch flush
|
||||||
|
val flush_final_out = Output(UInt(1.W)) // Branch flush or flush entire pipeline
|
||||||
|
val flush_path_out = Output(UInt(31.W)) // Branch flush PC
|
||||||
|
val pred_correct_out = Output(UInt(1.W)) // NPC control
|
||||||
|
val predict_p_out = Valid(new predict_pkt_t) // Predicted branch structure
|
||||||
|
})
|
||||||
|
|
||||||
|
io.dec_alu.exu_i0_pc_x := rvdffe(io.dec_i0_pc_d,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
|
||||||
|
val result = WireInit(UInt(32.W),0.U)
|
||||||
|
io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool)
|
||||||
|
|
||||||
|
val bm = Mux( io.i0_ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified
|
||||||
|
|
||||||
|
val aout = WireInit(UInt(33.W),0.U)
|
||||||
|
aout := Mux(io.i0_ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.i0_ap.sub)))
|
||||||
|
val cout = aout(32)
|
||||||
|
|
||||||
|
val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits
|
||||||
|
|
||||||
|
val eq = (io.a_in === io.b_in.asSInt)
|
||||||
|
val ne = ~eq
|
||||||
|
val neg = aout(31)// check for the last signed bit (for neg)
|
||||||
|
val lt = (!io.i0_ap.unsign & (neg ^ ov)) | ( io.i0_ap.unsign & !cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
|
||||||
|
val ge = !lt // if not less then
|
||||||
|
|
||||||
|
|
||||||
|
val lout = Mux1H(Seq(
|
||||||
|
io.dec_alu.dec_csr_ren_d.asBool -> io.b_in.asSInt, //read enable read rs2
|
||||||
|
io.i0_ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
|
||||||
|
io.i0_ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
|
||||||
|
io.i0_ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
|
||||||
|
|
||||||
|
val shift_amount = Mux1H(Seq (
|
||||||
|
io.i0_ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
|
||||||
|
io.i0_ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
|
||||||
|
io.i0_ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ))
|
||||||
|
|
||||||
|
val shift_mask = WireInit(UInt(32.W),0.U)
|
||||||
|
shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.i0_ap.sll) & io.b_in(4,0)) )
|
||||||
|
|
||||||
|
val shift_extend = WireInit(UInt(63.W),0.U)
|
||||||
|
shift_extend := Cat((repl(31,io.i0_ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.i0_ap.sll) & io.a_in(30,0)),io.a_in)
|
||||||
|
|
||||||
|
val shift_long = WireInit(UInt(63.W),0.U)
|
||||||
|
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused
|
||||||
|
|
||||||
|
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1
|
||||||
|
|
||||||
|
|
||||||
|
val sel_shift = io.i0_ap.sll | io.i0_ap.srl | io.i0_ap.sra
|
||||||
|
val sel_adder = (io.i0_ap.add | io.i0_ap.sub) & !io.i0_ap.slt
|
||||||
|
val sel_pc = io.i0_ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret
|
||||||
|
val csr_write_data = Mux(io.i0_ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
|
||||||
|
|
||||||
|
val slt_one = io.i0_ap.slt & lt
|
||||||
|
|
||||||
|
// for a conditional br pcout[] will be the opposite of the branch prediction
|
||||||
|
// for jal or pcall, it will be the link address pc+2 or pc+4
|
||||||
|
val pcout = rvbradder(Cat(io.dec_i0_pc_d,0.U),Cat(io.dec_alu.dec_i0_br_immed_d,0.U))
|
||||||
|
|
||||||
|
result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq(
|
||||||
|
sel_shift.asBool -> sout(31,0),
|
||||||
|
sel_adder.asBool -> aout(31,0),
|
||||||
|
sel_pc.asBool -> pcout,
|
||||||
|
io.i0_ap.csr_write.asBool -> csr_write_data(31,0))))
|
||||||
|
|
||||||
|
// *** branch handling ***
|
||||||
|
|
||||||
|
val any_jal = io.i0_ap.jal | //jal
|
||||||
|
io.pp_in.bits.pcall | //branch is a call inst
|
||||||
|
io.pp_in.bits.pja | //branch is a jump always
|
||||||
|
io.pp_in.bits.pret //return inst
|
||||||
|
|
||||||
|
val actual_taken = (io.i0_ap.beq & eq) | (io.i0_ap.bne & ne.asUInt) | (io.i0_ap.blt & lt) | (io.i0_ap.bge & ge) | any_jal
|
||||||
|
|
||||||
|
// pred_correct is for the npc logic
|
||||||
|
// pred_correct indicates not to use the flush_path
|
||||||
|
// for any_jal pred_correct==0
|
||||||
|
io.pred_correct_out := (io.dec_alu.dec_i0_alu_decode_d & io.i0_ap.predict_nt & !actual_taken & !any_jal) | (io.dec_alu.dec_i0_alu_decode_d & io.i0_ap.predict_t & actual_taken & !any_jal)
|
||||||
|
// for any_jal adder output is the flush path
|
||||||
|
io.flush_path_out := Mux(any_jal.asBool, aout(31,1), pcout(31,1))
|
||||||
|
|
||||||
|
// pcall and pret are included here
|
||||||
|
val cond_mispredict = (io.i0_ap.predict_t & !actual_taken) | (io.i0_ap.predict_nt & actual_taken.asUInt)
|
||||||
|
|
||||||
|
// target mispredicts on ret's
|
||||||
|
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
|
||||||
|
|
||||||
|
io.flush_upper_out := (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x & !io.dec_tlu_flush_lower_r
|
||||||
|
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
|
||||||
|
io.flush_final_out := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) | io.dec_tlu_flush_lower_r
|
||||||
|
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
||||||
|
|
||||||
|
val newhist = WireInit(UInt(2.W),0.U)
|
||||||
|
newhist := Cat((io.pp_in.bits.hist(1) & io.pp_in.bits.hist(0)) | (!io.pp_in.bits.hist(0) & actual_taken),//newhist[1]
|
||||||
|
(!io.pp_in.bits.hist(1) & !actual_taken) | (io.pp_in.bits.hist(1) & actual_taken)) //newhist[0]
|
||||||
|
|
||||||
|
io.predict_p_out := io.pp_in
|
||||||
|
io.predict_p_out.bits.misp := !io.flush_upper_x & !io.dec_tlu_flush_lower_r & (cond_mispredict | target_mispredict)// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
|
||||||
|
io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not
|
||||||
|
io.predict_p_out.bits.hist := newhist
|
||||||
|
}
|
||||||
|
|
||||||
|
|
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Reference in New Issue