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Update beh_lib.scala

This commit is contained in:
Junaid Ahmed 2020-09-22 10:26:16 +05:00 committed by GitHub
parent f60e035eeb
commit 698c0fc1a1
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 316 additions and 281 deletions
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159
src/main/scala/lib/beh_lib.scala
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@ -3,23 +3,24 @@ import chisel3._
import chisel3.util._
class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val flop = RegNext(io.din,0.U)
val flop = RegNext(io.din,0.U)
if(SHORT == 1)
{io.dout := io.din}
else
{io.dout := flop}
if(SHORT == 1)
{io.dout := io.din}
else
{io.dout := flop}
}
//println(getVerilog(new rvdff))
//rvdff => use regnext. with Asynchronous
class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing
class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
@ -27,13 +28,16 @@ class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncRe
val sync_ff1 = RegNext(io.din,0.U) //RegNext(io.in,init)
val sync_ff2 = RegNext(sync_ff1,0.U)
if(SHORT == 1)
{ io.dout := io.din }
{io.dout := io.din }
else
{ io.dout := sync_ff2 }
{io.dout := sync_ff2 }
}
class rvlsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val rs1 = Input(UInt(32.W))
@ -49,9 +53,6 @@ class rvlsadder extends Module{ //Done for verification and testing
io.dout := Cat(dout_upper,w1(11,0))
}
class rvbsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val pc = Input(UInt(32.W)) // lsb is not using in code
@ -59,35 +60,28 @@ class rvbsadder extends Module{ //Done for verification and testing
val dout = Output(UInt(31.W))
})
val w1 = Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))& io.pc(31,13)) |
((Fill(19, ~io.offset(12) ^ w1(12))) & (io.pc(31,13)+1.U)) |
((Fill(19, io.offset(12) ^ ~w1(12))) & (io.pc(31,13)-1.U))
io.dout := Cat(dout_upper,w1(11,0))
}
}
class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing
class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
val i:Int = 1
for(i <- 1 to WIDTH-1){
val done = io.din(i-1,0).orR
temp(i-1) := Mux(done ,~io.din(i),io.din(i))
}
io.dout := Cat(temp.asUInt,io.din(0))
}
}
class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing
class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val mask = Input(UInt(WIDTH.W))
val data = Input(UInt(WIDTH.W))
@ -103,12 +97,9 @@ class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification a
for(i <- 1 to WIDTH-1)
{matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
io.match_out := matchvec.asUInt
}
}
class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
val io = IO(new Bundle{
val addr = Input(UInt(32.W))
val in_range = Output(UInt(1.W))
@ -126,33 +117,26 @@ class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
else
io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
}
}
class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing
class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
val parity_out = Output(UInt(1.W))
})
io.parity_out := io.data_in.xorR.asUInt
}
}
class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing
class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
val parity_in = Input (UInt(1.W))
val parity_err = Output(UInt(1.W))
})
io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
}
}
class rvecc_encode extends Module{ //Done for verification and testing
class rvecc_encode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val ecc_out = Output(UInt(7.W))
@ -183,11 +167,9 @@ class rvecc_encode extends Module{ //Done for verification and testing
}
val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
}
}
class rvecc_decode extends Module{ //Done for verification and testing
class rvecc_decode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
val din = Input(UInt(32.W))
@ -226,7 +208,7 @@ class rvecc_decode extends Module{ //Done for verification and testing
}
val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_out := ecc_check
io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
@ -240,14 +222,9 @@ class rvecc_decode extends Module{ //Done for verification and testing
io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
}
}
class rvecc_encode_64 extends Module{ //Done for verification and testing
class rvecc_encode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(64.W))
val ecc_out = Output(UInt(7.W))
@ -282,13 +259,9 @@ class rvecc_encode_64 extends Module{ //Done for verification and testing
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
}
}
class rvecc_decode_64 extends Module{ //Done for verification and testing
class rvecc_decode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
val din = Input(UInt(64.W))
@ -327,10 +300,72 @@ class rvecc_decode_64 extends Module{ //Done for verification and testing
val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
}
////////////////////////////TEC_RV_ICG////////////////////////
class TEC_RV_ICG extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val Q = Output(Clock())
val CK = Input(Clock())
val EN = Input(Bool())
val SE = Input(Bool())
})
addResource("/vsrc/TEC_RV_ICG.v")
}
class rvclkhdr extends Module {
val io = IO(new Bundle {
val l1clk = Output(Clock())
val clk = Input(Clock())
val en = Input(Bool())
val scan_mode = Input(Bool())
})
val clkhdr = { Module(new TEC_RV_ICG) }
io.l1clk := clkhdr.io.Q
clkhdr.io.CK := io.clk
clkhdr.io.EN := io.en
clkhdr.io.SE := io.scan_mode
}
object rvclkhdr {
def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
val cg = Module(new rvclkhdr)
cg.io.clk := clk
cg.io.en := en
cg.io.scan_mode := scan_mode
cg.io.l1clk
}
}
////Instantiation example///////////////Can be use if using class instead of function rvdffe
class my_class extends Module{
val io = IO(new Bundle {
val l1clk = Output(Clock())
val clk = Input(Clock())
val en = Input(Bool())
val scan_mode = Input(Bool())
})
val obj = Module(new rvclkhdr())
io.l1clk := obj.io.l1clk
obj.io.clk := io.clk
obj.io.en := io.en
obj.io.scan_mode := io.scan_mode
}
/*
object main extends App{
chisel3.Driver.execute(args,()=> new my_class)
}*/