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This commit is contained in:
parent
fe348aed59
commit
69dd2153d4
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@ -1,14 +1,14 @@
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[
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[
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_1",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ictag_debug_rd_data",
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"sources":[
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
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"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
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@ -16,14 +16,32 @@
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},
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_0",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
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"sources":[
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_addr",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_way",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
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"~EL2_IC_TAG|EL2_IC_TAG>io_clk_override",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array"
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1713
EL2_IC_TAG.fir
1713
EL2_IC_TAG.fir
File diff suppressed because it is too large
Load Diff
195
EL2_IC_TAG.v
195
EL2_IC_TAG.v
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@ -16,24 +16,31 @@ module EL2_IC_TAG(
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input [70:0] io_ic_debug_wr_data,
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input [70:0] io_ic_debug_wr_data,
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output [1:0] io_ic_rd_hit,
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output [1:0] io_ic_rd_hit,
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output io_ic_tag_perr,
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output io_ic_tag_perr,
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input io_scan_mode,
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input io_scan_mode
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output [25:0] io_test_0,
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output [25:0] io_test_1
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);
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);
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`ifdef RANDOMIZE_MEM_INIT
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`ifdef RANDOMIZE_MEM_INIT
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_1;
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`endif // RANDOMIZE_MEM_INIT
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`endif // RANDOMIZE_MEM_INIT
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_2;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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`endif // RANDOMIZE_REG_INIT
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reg [25:0] tag_mem_0 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
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reg [25:0] tag_mem_0 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_0__T_250_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_0__T_254_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_0__T_254_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_0__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_0__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_0__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_0__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_0__T_238_en; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_0__T_238_en; // @[el2_ifu_ic_mem.scala 97:20]
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reg [25:0] tag_mem_1 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
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reg [25:0] tag_mem_1 [0:127]; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_1__T_250_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_1__T_250_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_1__T_254_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [25:0] tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_1__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire [6:0] tag_mem_1__T_238_addr; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_1__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
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wire tag_mem_1__T_238_mask; // @[el2_ifu_ic_mem.scala 97:20]
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@ -52,54 +59,141 @@ module EL2_IC_TAG(
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wire [1:0] _T_12 = _T_10 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
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wire [1:0] _T_12 = _T_10 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
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wire [1:0] ic_debug_rd_way_en = _T_12 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 79:90]
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wire [1:0] ic_debug_rd_way_en = _T_12 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 79:90]
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wire [1:0] ic_tag_clken = _T_8 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 72:108]
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wire [1:0] ic_tag_clken = _T_8 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 72:108]
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reg ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 74:28]
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reg [18:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 75:30]
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wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
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wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
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wire [31:0] _T_20 = {13'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
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wire [31:0] _T_20 = {13'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
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wire [8:0] _T_124 = {_T_20[16],_T_20[14],_T_20[12],_T_20[10],_T_20[8],_T_20[6],_T_20[5],_T_20[3],_T_20[1]}; // @[el2_lib.scala 255:22]
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wire [8:0] _T_124 = {_T_20[16],_T_20[14],_T_20[12],_T_20[10],_T_20[8],_T_20[6],_T_20[5],_T_20[3],_T_20[1]}; // @[el2_lib.scala 257:22]
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wire [17:0] _T_133 = {_T_20[31],_T_20[30],_T_20[28],_T_20[27],_T_20[25],_T_20[23],_T_20[21],_T_20[20],_T_20[18],_T_124}; // @[el2_lib.scala 255:22]
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wire [17:0] _T_133 = {_T_20[31],_T_20[30],_T_20[28],_T_20[27],_T_20[25],_T_20[23],_T_20[21],_T_20[20],_T_20[18],_T_124}; // @[el2_lib.scala 257:22]
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wire _T_134 = ^_T_133; // @[el2_lib.scala 255:29]
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wire _T_134 = ^_T_133; // @[el2_lib.scala 257:29]
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wire [8:0] _T_142 = {_T_20[15],_T_20[14],_T_20[11],_T_20[10],_T_20[7],_T_20[6],_T_20[4],_T_20[3],_T_20[0]}; // @[el2_lib.scala 255:39]
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wire [8:0] _T_142 = {_T_20[15],_T_20[14],_T_20[11],_T_20[10],_T_20[7],_T_20[6],_T_20[4],_T_20[3],_T_20[0]}; // @[el2_lib.scala 257:39]
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wire [17:0] _T_151 = {_T_20[31],_T_20[29],_T_20[28],_T_20[26],_T_20[25],_T_20[22],_T_20[21],_T_20[19],_T_20[18],_T_142}; // @[el2_lib.scala 255:39]
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wire [17:0] _T_151 = {_T_20[31],_T_20[29],_T_20[28],_T_20[26],_T_20[25],_T_20[22],_T_20[21],_T_20[19],_T_20[18],_T_142}; // @[el2_lib.scala 257:39]
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wire _T_152 = ^_T_151; // @[el2_lib.scala 255:46]
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wire _T_152 = ^_T_151; // @[el2_lib.scala 257:46]
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wire [8:0] _T_160 = {_T_20[15],_T_20[14],_T_20[9],_T_20[8],_T_20[7],_T_20[6],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 255:56]
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wire [8:0] _T_160 = {_T_20[15],_T_20[14],_T_20[9],_T_20[8],_T_20[7],_T_20[6],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 257:56]
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wire [17:0] _T_169 = {_T_20[30],_T_20[29],_T_20[28],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[17],_T_20[16],_T_160}; // @[el2_lib.scala 255:56]
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wire [17:0] _T_169 = {_T_20[30],_T_20[29],_T_20[28],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[17],_T_20[16],_T_160}; // @[el2_lib.scala 257:56]
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wire _T_170 = ^_T_169; // @[el2_lib.scala 255:63]
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wire _T_170 = ^_T_169; // @[el2_lib.scala 257:63]
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wire [6:0] _T_176 = {_T_20[12],_T_20[11],_T_20[10],_T_20[9],_T_20[8],_T_20[7],_T_20[6]}; // @[el2_lib.scala 255:73]
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wire [6:0] _T_176 = {_T_20[12],_T_20[11],_T_20[10],_T_20[9],_T_20[8],_T_20[7],_T_20[6]}; // @[el2_lib.scala 257:73]
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wire [14:0] _T_184 = {_T_20[27],_T_20[26],_T_20[25],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[13],_T_176}; // @[el2_lib.scala 255:73]
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wire [14:0] _T_184 = {_T_20[27],_T_20[26],_T_20[25],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[13],_T_176}; // @[el2_lib.scala 257:73]
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wire _T_185 = ^_T_184; // @[el2_lib.scala 255:80]
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wire _T_185 = ^_T_184; // @[el2_lib.scala 257:80]
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wire [14:0] _T_199 = {_T_20[20],_T_20[19],_T_20[18],_T_20[17],_T_20[16],_T_20[15],_T_20[14],_T_20[13],_T_176}; // @[el2_lib.scala 255:90]
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wire [14:0] _T_199 = {_T_20[20],_T_20[19],_T_20[18],_T_20[17],_T_20[16],_T_20[15],_T_20[14],_T_20[13],_T_176}; // @[el2_lib.scala 257:90]
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wire _T_200 = ^_T_199; // @[el2_lib.scala 255:97]
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wire _T_200 = ^_T_199; // @[el2_lib.scala 257:97]
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wire [5:0] _T_205 = {_T_20[5],_T_20[4],_T_20[3],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 255:107]
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wire [5:0] _T_205 = {_T_20[5],_T_20[4],_T_20[3],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 257:107]
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wire _T_206 = ^_T_205; // @[el2_lib.scala 255:114]
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wire _T_206 = ^_T_205; // @[el2_lib.scala 257:114]
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wire [5:0] _T_211 = {_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire [5:0] _T_211 = {_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire _T_212 = ^_T_20; // @[el2_lib.scala 256:13]
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wire _T_212 = ^_T_20; // @[el2_lib.scala 258:13]
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wire _T_213 = ^_T_211; // @[el2_lib.scala 256:23]
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wire _T_213 = ^_T_211; // @[el2_lib.scala 258:23]
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wire _T_214 = _T_212 ^ _T_213; // @[el2_lib.scala 256:18]
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wire _T_214 = _T_212 ^ _T_213; // @[el2_lib.scala 258:18]
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wire [6:0] ic_tag_ecc = {_T_214,_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire [6:0] ic_tag_ecc = {_T_214,_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire [25:0] _T_221 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
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wire [25:0] _T_221 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
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wire [25:0] _T_226 = {ic_tag_ecc[4:0],2'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
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wire [25:0] _T_226 = {ic_tag_ecc[4:0],2'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
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wire _T_227 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 93:45]
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wire _T_227 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 93:45]
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wire [28:0] ic_rw_addr_q = _T_227 ? {{22'd0}, io_ic_debug_addr[9:3]} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 93:25]
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wire [28:0] ic_rw_addr_q = _T_227 ? {{22'd0}, io_ic_debug_addr[9:3]} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 93:25]
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wire _T_240 = ~ic_tag_wren_q[0]; // @[el2_ifu_ic_mem.scala 110:61]
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reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 95:38]
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wire read_enable_0 = _T_240 & ic_tag_clken[0]; // @[el2_ifu_ic_mem.scala 110:79]
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wire _T_240 = ~ic_tag_wren_q[0]; // @[el2_ifu_ic_mem.scala 102:59]
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wire _T_244 = ~ic_tag_wren_q[1]; // @[el2_ifu_ic_mem.scala 110:61]
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wire read_enable_0 = _T_240 & ic_tag_clken[0]; // @[el2_ifu_ic_mem.scala 102:77]
|
||||||
wire read_enable_1 = _T_244 & ic_tag_clken[1]; // @[el2_ifu_ic_mem.scala 110:79]
|
wire _T_244 = ~ic_tag_wren_q[1]; // @[el2_ifu_ic_mem.scala 102:59]
|
||||||
assign tag_mem_0_ic_tag_data_raw_addr = ic_rw_addr_q[6:0];
|
wire read_enable_1 = _T_244 & ic_tag_clken[1]; // @[el2_ifu_ic_mem.scala 102:77]
|
||||||
assign tag_mem_0_ic_tag_data_raw_data = tag_mem_0[tag_mem_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
wire [25:0] _T_248 = read_enable_0 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [25:0] ic_tag_data_raw_0 = _T_248 & tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 103:87]
|
||||||
|
wire [25:0] _T_252 = read_enable_1 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [25:0] ic_tag_data_raw_1 = _T_252 & tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 103:87]
|
||||||
|
wire [23:0] w_tout_0 = {ic_tag_data_raw_0[25:21],ic_tag_data_raw_0[18:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [23:0] w_tout_1 = {ic_tag_data_raw_1[25:21],ic_tag_data_raw_1[18:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_261 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_ic_mem.scala 111:51]
|
||||||
|
wire _T_262 = _T_261 & ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 111:80]
|
||||||
|
wire [31:0] _T_264 = {11'h0,ic_tag_data_raw_0[20:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_266 = {2'h0,ic_tag_data_raw_0[25:21]}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] _T_373 = {_T_264[31],_T_264[30],_T_264[29],_T_264[28],_T_264[27],_T_264[26]}; // @[el2_lib.scala 290:76]
|
||||||
|
wire _T_374 = ^_T_373; // @[el2_lib.scala 290:83]
|
||||||
|
wire _T_375 = _T_266[5] ^ _T_374; // @[el2_lib.scala 290:71]
|
||||||
|
wire [6:0] _T_382 = {_T_264[17],_T_264[16],_T_264[15],_T_264[14],_T_264[13],_T_264[12],_T_264[11]}; // @[el2_lib.scala 290:103]
|
||||||
|
wire [14:0] _T_390 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_382}; // @[el2_lib.scala 290:103]
|
||||||
|
wire _T_391 = ^_T_390; // @[el2_lib.scala 290:110]
|
||||||
|
wire _T_392 = _T_266[4] ^ _T_391; // @[el2_lib.scala 290:98]
|
||||||
|
wire [6:0] _T_399 = {_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[6],_T_264[5],_T_264[4]}; // @[el2_lib.scala 290:130]
|
||||||
|
wire [14:0] _T_407 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_399}; // @[el2_lib.scala 290:130]
|
||||||
|
wire _T_408 = ^_T_407; // @[el2_lib.scala 290:137]
|
||||||
|
wire _T_409 = _T_266[3] ^ _T_408; // @[el2_lib.scala 290:125]
|
||||||
|
wire [8:0] _T_418 = {_T_264[15],_T_264[14],_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[3],_T_264[2],_T_264[1]}; // @[el2_lib.scala 290:157]
|
||||||
|
wire [17:0] _T_427 = {_T_264[31],_T_264[30],_T_264[29],_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[17],_T_264[16],_T_418}; // @[el2_lib.scala 290:157]
|
||||||
|
wire _T_428 = ^_T_427; // @[el2_lib.scala 290:164]
|
||||||
|
wire _T_429 = _T_266[2] ^ _T_428; // @[el2_lib.scala 290:152]
|
||||||
|
wire [8:0] _T_438 = {_T_264[13],_T_264[12],_T_264[10],_T_264[9],_T_264[6],_T_264[5],_T_264[3],_T_264[2],_T_264[0]}; // @[el2_lib.scala 290:184]
|
||||||
|
wire [17:0] _T_447 = {_T_264[31],_T_264[28],_T_264[27],_T_264[25],_T_264[24],_T_264[21],_T_264[20],_T_264[17],_T_264[16],_T_438}; // @[el2_lib.scala 290:184]
|
||||||
|
wire _T_448 = ^_T_447; // @[el2_lib.scala 290:191]
|
||||||
|
wire _T_449 = _T_266[1] ^ _T_448; // @[el2_lib.scala 290:179]
|
||||||
|
wire [8:0] _T_458 = {_T_264[13],_T_264[11],_T_264[10],_T_264[8],_T_264[6],_T_264[4],_T_264[3],_T_264[1],_T_264[0]}; // @[el2_lib.scala 290:211]
|
||||||
|
wire [17:0] _T_467 = {_T_264[30],_T_264[28],_T_264[26],_T_264[25],_T_264[23],_T_264[21],_T_264[19],_T_264[17],_T_264[15],_T_458}; // @[el2_lib.scala 290:211]
|
||||||
|
wire _T_468 = ^_T_467; // @[el2_lib.scala 290:218]
|
||||||
|
wire _T_469 = _T_266[0] ^ _T_468; // @[el2_lib.scala 290:206]
|
||||||
|
wire [6:0] _T_475 = {1'h0,_T_375,_T_392,_T_409,_T_429,_T_449,_T_469}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_476 = _T_475 != 7'h0; // @[el2_lib.scala 291:44]
|
||||||
|
wire _T_477 = _T_262 & _T_476; // @[el2_lib.scala 291:32]
|
||||||
|
wire ic_tag_single_ecc_error_0 = _T_477 & _T_475[6]; // @[el2_lib.scala 291:53]
|
||||||
|
wire _T_483 = ~_T_475[6]; // @[el2_lib.scala 292:55]
|
||||||
|
wire ic_tag_double_ecc_error_0 = _T_477 & _T_483; // @[el2_lib.scala 292:53]
|
||||||
|
wire [31:0] _T_652 = {11'h0,ic_tag_data_raw_1[20:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [6:0] _T_654 = {2'h0,ic_tag_data_raw_1[25:21]}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] _T_761 = {_T_652[31],_T_652[30],_T_652[29],_T_652[28],_T_652[27],_T_652[26]}; // @[el2_lib.scala 290:76]
|
||||||
|
wire _T_762 = ^_T_761; // @[el2_lib.scala 290:83]
|
||||||
|
wire _T_763 = _T_654[5] ^ _T_762; // @[el2_lib.scala 290:71]
|
||||||
|
wire [6:0] _T_770 = {_T_652[17],_T_652[16],_T_652[15],_T_652[14],_T_652[13],_T_652[12],_T_652[11]}; // @[el2_lib.scala 290:103]
|
||||||
|
wire [14:0] _T_778 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_770}; // @[el2_lib.scala 290:103]
|
||||||
|
wire _T_779 = ^_T_778; // @[el2_lib.scala 290:110]
|
||||||
|
wire _T_780 = _T_654[4] ^ _T_779; // @[el2_lib.scala 290:98]
|
||||||
|
wire [6:0] _T_787 = {_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[6],_T_652[5],_T_652[4]}; // @[el2_lib.scala 290:130]
|
||||||
|
wire [14:0] _T_795 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_787}; // @[el2_lib.scala 290:130]
|
||||||
|
wire _T_796 = ^_T_795; // @[el2_lib.scala 290:137]
|
||||||
|
wire _T_797 = _T_654[3] ^ _T_796; // @[el2_lib.scala 290:125]
|
||||||
|
wire [8:0] _T_806 = {_T_652[15],_T_652[14],_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[3],_T_652[2],_T_652[1]}; // @[el2_lib.scala 290:157]
|
||||||
|
wire [17:0] _T_815 = {_T_652[31],_T_652[30],_T_652[29],_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[17],_T_652[16],_T_806}; // @[el2_lib.scala 290:157]
|
||||||
|
wire _T_816 = ^_T_815; // @[el2_lib.scala 290:164]
|
||||||
|
wire _T_817 = _T_654[2] ^ _T_816; // @[el2_lib.scala 290:152]
|
||||||
|
wire [8:0] _T_826 = {_T_652[13],_T_652[12],_T_652[10],_T_652[9],_T_652[6],_T_652[5],_T_652[3],_T_652[2],_T_652[0]}; // @[el2_lib.scala 290:184]
|
||||||
|
wire [17:0] _T_835 = {_T_652[31],_T_652[28],_T_652[27],_T_652[25],_T_652[24],_T_652[21],_T_652[20],_T_652[17],_T_652[16],_T_826}; // @[el2_lib.scala 290:184]
|
||||||
|
wire _T_836 = ^_T_835; // @[el2_lib.scala 290:191]
|
||||||
|
wire _T_837 = _T_654[1] ^ _T_836; // @[el2_lib.scala 290:179]
|
||||||
|
wire [8:0] _T_846 = {_T_652[13],_T_652[11],_T_652[10],_T_652[8],_T_652[6],_T_652[4],_T_652[3],_T_652[1],_T_652[0]}; // @[el2_lib.scala 290:211]
|
||||||
|
wire [17:0] _T_855 = {_T_652[30],_T_652[28],_T_652[26],_T_652[25],_T_652[23],_T_652[21],_T_652[19],_T_652[17],_T_652[15],_T_846}; // @[el2_lib.scala 290:211]
|
||||||
|
wire _T_856 = ^_T_855; // @[el2_lib.scala 290:218]
|
||||||
|
wire _T_857 = _T_654[0] ^ _T_856; // @[el2_lib.scala 290:206]
|
||||||
|
wire [6:0] _T_863 = {1'h0,_T_763,_T_780,_T_797,_T_817,_T_837,_T_857}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_864 = _T_863 != 7'h0; // @[el2_lib.scala 291:44]
|
||||||
|
wire _T_865 = _T_262 & _T_864; // @[el2_lib.scala 291:32]
|
||||||
|
wire ic_tag_single_ecc_error_1 = _T_865 & _T_863[6]; // @[el2_lib.scala 291:53]
|
||||||
|
wire _T_871 = ~_T_863[6]; // @[el2_lib.scala 292:55]
|
||||||
|
wire ic_tag_double_ecc_error_1 = _T_865 & _T_871; // @[el2_lib.scala 292:53]
|
||||||
|
wire [1:0] _T_1037 = {ic_tag_single_ecc_error_1,ic_tag_single_ecc_error_0}; // @[Cat.scala 29:58]
|
||||||
|
wire [1:0] _T_1038 = {ic_tag_double_ecc_error_1,ic_tag_double_ecc_error_0}; // @[Cat.scala 29:58]
|
||||||
|
wire [1:0] ic_tag_way_perr = _T_1037 | _T_1038; // @[el2_ifu_ic_mem.scala 119:88]
|
||||||
|
wire [25:0] _T_1041 = ic_debug_rd_way_en_ff[0] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [25:0] _T_1042 = _T_1041 & ic_tag_data_raw_0; // @[el2_ifu_ic_mem.scala 123:112]
|
||||||
|
wire [25:0] _T_1045 = ic_debug_rd_way_en_ff[1] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [25:0] _T_1046 = _T_1045 & ic_tag_data_raw_1; // @[el2_ifu_ic_mem.scala 123:112]
|
||||||
|
wire _T_1049 = w_tout_0[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 124:83]
|
||||||
|
wire _T_1051 = _T_1049 & io_ic_tag_valid[0]; // @[el2_ifu_ic_mem.scala 124:100]
|
||||||
|
wire _T_1053 = w_tout_1[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 124:83]
|
||||||
|
wire _T_1055 = _T_1053 & io_ic_tag_valid[1]; // @[el2_ifu_ic_mem.scala 124:100]
|
||||||
|
wire [1:0] _T_1057 = ic_tag_way_perr & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 125:38]
|
||||||
|
assign tag_mem_0__T_250_addr = ic_rw_addr_q[6:0];
|
||||||
|
assign tag_mem_0__T_250_data = tag_mem_0[tag_mem_0__T_250_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
||||||
|
assign tag_mem_0__T_254_addr = ic_rw_addr_q[6:0];
|
||||||
|
assign tag_mem_0__T_254_data = tag_mem_0[tag_mem_0__T_254_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
||||||
assign tag_mem_0__T_238_data = _T_14 ? _T_221 : _T_226;
|
assign tag_mem_0__T_238_data = _T_14 ? _T_221 : _T_226;
|
||||||
assign tag_mem_0__T_238_addr = ic_rw_addr_q[6:0];
|
assign tag_mem_0__T_238_addr = ic_rw_addr_q[6:0];
|
||||||
assign tag_mem_0__T_238_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
|
assign tag_mem_0__T_238_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
|
||||||
assign tag_mem_0__T_238_en = 1'h1;
|
assign tag_mem_0__T_238_en = 1'h1;
|
||||||
assign tag_mem_1_ic_tag_data_raw_addr = ic_rw_addr_q[6:0];
|
assign tag_mem_1__T_250_addr = ic_rw_addr_q[6:0];
|
||||||
assign tag_mem_1_ic_tag_data_raw_data = tag_mem_1[tag_mem_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
assign tag_mem_1__T_250_data = tag_mem_1[tag_mem_1__T_250_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
||||||
|
assign tag_mem_1__T_254_addr = ic_rw_addr_q[6:0];
|
||||||
|
assign tag_mem_1__T_254_data = tag_mem_1[tag_mem_1__T_254_addr]; // @[el2_ifu_ic_mem.scala 97:20]
|
||||||
assign tag_mem_1__T_238_data = _T_14 ? _T_221 : _T_226;
|
assign tag_mem_1__T_238_data = _T_14 ? _T_221 : _T_226;
|
||||||
assign tag_mem_1__T_238_addr = ic_rw_addr_q[6:0];
|
assign tag_mem_1__T_238_addr = ic_rw_addr_q[6:0];
|
||||||
assign tag_mem_1__T_238_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
|
assign tag_mem_1__T_238_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
|
||||||
assign tag_mem_1__T_238_en = 1'h1;
|
assign tag_mem_1__T_238_en = 1'h1;
|
||||||
assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 64:26]
|
assign io_ictag_debug_rd_data = _T_1042 | _T_1046; // @[el2_ifu_ic_mem.scala 64:26 el2_ifu_ic_mem.scala 123:26]
|
||||||
assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 65:16]
|
assign io_ic_rd_hit = {_T_1055,_T_1051}; // @[el2_ifu_ic_mem.scala 65:16 el2_ifu_ic_mem.scala 124:16]
|
||||||
assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 66:18]
|
assign io_ic_tag_perr = |_T_1057; // @[el2_ifu_ic_mem.scala 66:18 el2_ifu_ic_mem.scala 125:18]
|
||||||
assign io_test_0 = read_enable_0 ? tag_mem_0_ic_tag_data_raw_data : 26'h0; // @[el2_ifu_ic_mem.scala 114:18 el2_ifu_ic_mem.scala 116:20]
|
|
||||||
assign io_test_1 = read_enable_1 ? tag_mem_1_ic_tag_data_raw_data : 26'h0; // @[el2_ifu_ic_mem.scala 114:18 el2_ifu_ic_mem.scala 116:20]
|
|
||||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
`define RANDOMIZE
|
`define RANDOMIZE
|
||||||
`endif
|
`endif
|
||||||
|
@ -142,6 +236,14 @@ initial begin
|
||||||
for (initvar = 0; initvar < 128; initvar = initvar+1)
|
for (initvar = 0; initvar < 128; initvar = initvar+1)
|
||||||
tag_mem_1[initvar] = _RAND_1[25:0];
|
tag_mem_1[initvar] = _RAND_1[25:0];
|
||||||
`endif // RANDOMIZE_MEM_INIT
|
`endif // RANDOMIZE_MEM_INIT
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
_RAND_2 = {1{`RANDOM}};
|
||||||
|
ic_rd_en_ff = _RAND_2[0:0];
|
||||||
|
_RAND_3 = {1{`RANDOM}};
|
||||||
|
ic_rw_addr_ff = _RAND_3[18:0];
|
||||||
|
_RAND_4 = {1{`RANDOM}};
|
||||||
|
ic_debug_rd_way_en_ff = _RAND_4[1:0];
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
`endif // RANDOMIZE
|
`endif // RANDOMIZE
|
||||||
end // initial
|
end // initial
|
||||||
`ifdef FIRRTL_AFTER_INITIAL
|
`ifdef FIRRTL_AFTER_INITIAL
|
||||||
|
@ -155,5 +257,20 @@ end // initial
|
||||||
if(tag_mem_1__T_238_en & tag_mem_1__T_238_mask) begin
|
if(tag_mem_1__T_238_en & tag_mem_1__T_238_mask) begin
|
||||||
tag_mem_1[tag_mem_1__T_238_addr] <= tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
|
tag_mem_1[tag_mem_1__T_238_addr] <= tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 97:20]
|
||||||
end
|
end
|
||||||
|
if (reset) begin
|
||||||
|
ic_rd_en_ff <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
ic_rd_en_ff <= io_ic_rd_en;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
ic_rw_addr_ff <= 19'h0;
|
||||||
|
end else begin
|
||||||
|
ic_rw_addr_ff <= io_ic_rw_addr[18:0];
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
ic_debug_rd_way_en_ff <= 2'h0;
|
||||||
|
end else begin
|
||||||
|
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
45248
el2_ifu_bp_ctl.fir
45248
el2_ifu_bp_ctl.fir
File diff suppressed because it is too large
Load Diff
13362
el2_ifu_bp_ctl.v
13362
el2_ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
|
@ -41,6 +41,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
||||||
|
|
||||||
val test1 = Output(UInt())
|
val test1 = Output(UInt())
|
||||||
val test2 = Output(UInt())
|
val test2 = Output(UInt())
|
||||||
|
// val clk_enables = Output(UInt())
|
||||||
})
|
})
|
||||||
|
|
||||||
val TAG_START = 16+BTB_BTAG_SIZE
|
val TAG_START = 16+BTB_BTAG_SIZE
|
||||||
|
@ -380,21 +381,17 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
||||||
Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt)&(bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0))))
|
Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt)&(bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0))))
|
||||||
|
|
||||||
val bht_bank_sel = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>
|
val bht_bank_sel = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>
|
||||||
bht_wr_en0(i) & (bht_wr_addr0(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & (bht_wr_addr0(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B | bht_wr_en2(i) &
|
bht_wr_en0(i) & (bht_wr_addr0(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & (bht_wr_addr0(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B | bht_wr_en2(i) &
|
||||||
(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & (bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B)))
|
(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & (bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B)))
|
||||||
|
|
||||||
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
|
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
|
||||||
val bht_bank_clken = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>
|
|
||||||
(bht_wr_en0(i) & ((bht_wr_addr0===k.U) | BHT_NO_ADDR_MATCH.asBool)) |
|
|
||||||
(bht_wr_en2(i) & ((bht_wr_addr2===k.U) | BHT_NO_ADDR_MATCH.asBool))))
|
|
||||||
|
|
||||||
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
|
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
|
||||||
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(j)(k), 0.U, bht_bank_sel(i)(j)(k)&bht_bank_clken(i)(k))
|
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(j)(k), 0.U, bht_bank_sel(i)(j)(k))
|
||||||
}
|
}
|
||||||
|
|
||||||
bht_bank0_rd_data_f := Mux1H((0 until NUM_BHT_LOOP).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
|
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
|
||||||
bht_bank1_rd_data_f := Mux1H((0 until NUM_BHT_LOOP).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
|
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
|
||||||
bht_bank0_rd_data_p1_f := Mux1H((0 until NUM_BHT_LOOP).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
|
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
|
||||||
}
|
}
|
||||||
|
|
||||||
object ifu_bp extends App {
|
object ifu_bp extends App {
|
||||||
|
|
|
@ -36,12 +36,12 @@ class el2_ifu_ic_mem extends Module with param{
|
||||||
io.ictag_debug_rd_data := 0.U
|
io.ictag_debug_rd_data := 0.U
|
||||||
io.ic_debug_rd_data := 0.U
|
io.ic_debug_rd_data := 0.U
|
||||||
io.ic_rd_data := 0.U
|
io.ic_rd_data := 0.U
|
||||||
//val icache_tag = Module(new kncpa)
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/////////// ICACHE TAG
|
/////////// ICACHE TAG
|
||||||
class EL2_IC_TAG extends Module with el2_lib with param {
|
class EL2_IC_TAG extends Module with el2_lib with param {
|
||||||
val io = IO(new Bundle{
|
val io = IO(new Bundle{
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
val clk_override = Input(Bool())
|
val clk_override = Input(Bool())
|
||||||
val dec_tlu_core_ecc_disable = Input(Bool())
|
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||||
val ic_rw_addr = Input(UInt(29.W)) // 32:3
|
val ic_rw_addr = Input(UInt(29.W)) // 32:3
|
||||||
|
@ -57,17 +57,13 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
||||||
val ic_debug_wr_data = Input(UInt(71.W))
|
val ic_debug_wr_data = Input(UInt(71.W))
|
||||||
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
|
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||||
val ic_tag_perr = Output(Bool())
|
val ic_tag_perr = Output(Bool())
|
||||||
val scan_mode = Input(Bool())
|
|
||||||
val test = Output(Vec(2, UInt()))
|
|
||||||
})
|
})
|
||||||
|
|
||||||
io.ictag_debug_rd_data := 0.U
|
io.ictag_debug_rd_data := 0.U
|
||||||
io.ic_rd_hit := 0.U
|
io.ic_rd_hit := 0.U
|
||||||
io.ic_tag_perr := 0.U
|
io.ic_tag_perr := 0.U
|
||||||
val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||||
val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||||
|
|
||||||
|
|
||||||
val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
|
val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
|
||||||
val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en
|
val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en
|
||||||
|
|
||||||
|
@ -96,29 +92,31 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
||||||
|
|
||||||
val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W)))
|
val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W)))
|
||||||
|
|
||||||
|
val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i))
|
||||||
val mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i))
|
tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec)
|
||||||
tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), mask)
|
|
||||||
val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i))
|
val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i))
|
||||||
val ic_tag_data_raw = tag_mem.read(ic_rw_addr_q)
|
val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i))
|
||||||
|
val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0)))
|
||||||
|
else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0)))
|
||||||
|
val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W)))
|
||||||
|
val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W)))
|
||||||
|
val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
|
||||||
|
val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
|
||||||
for(i<- 0 until ICACHE_NUM_WAYS){
|
for(i<- 0 until ICACHE_NUM_WAYS){
|
||||||
io.test(i) := 0.U
|
val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U)
|
||||||
when(read_enable(i)){
|
else (0.U, 0.U, 0.U, 0.U)
|
||||||
io.test(i) := ic_tag_data_raw(i)}
|
ic_tag_corrected_ecc_unc(i) := decoded_ecc._1
|
||||||
}
|
ic_tag_corrected_data_unc(i) := decoded_ecc._2
|
||||||
|
ic_tag_single_ecc_error(i):= decoded_ecc._3
|
||||||
|
ic_tag_double_ecc_error(i) := decoded_ecc._4
|
||||||
|
}
|
||||||
|
|
||||||
// for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
|
val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_))
|
||||||
// wb_dout(i)(k) := 0.U
|
else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_))
|
||||||
// val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
|
|
||||||
// val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
|
|
||||||
// when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
|
|
||||||
// data_mem(ic_rw_addr_bank_q(k))(k)(i) := ic_sb_wr_data(k)
|
|
||||||
// }.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
|
|
||||||
// wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
|
|
||||||
// }
|
|
||||||
// }
|
|
||||||
|
|
||||||
|
io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_)
|
||||||
|
io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_))
|
||||||
|
io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR()
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -259,17 +259,7 @@ trait el2_lib extends param{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
class rvecc_decode extends Module{ //Done for verification and testing
|
def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= {
|
||||||
val io = IO(new Bundle{
|
|
||||||
val en = Input(UInt(1.W))
|
|
||||||
val din = Input(UInt(32.W))
|
|
||||||
val ecc_in = Input(UInt(7.W))
|
|
||||||
val sed_ded = Input(UInt(1.W))
|
|
||||||
val ecc_out = Output(UInt(7.W))
|
|
||||||
val dout = Output(UInt(32.W))
|
|
||||||
val single_ecc_error = Output(UInt(1.W))
|
|
||||||
val double_ecc_error = Output(UInt(1.W))
|
|
||||||
})
|
|
||||||
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
|
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
|
||||||
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
|
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
|
||||||
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
|
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
|
||||||
|
@ -289,29 +279,28 @@ trait el2_lib extends param{
|
||||||
|
|
||||||
for(i <- 0 to 31)
|
for(i <- 0 to 31)
|
||||||
{
|
{
|
||||||
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
|
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
|
||||||
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
|
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
|
||||||
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
|
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
|
||||||
if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
|
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
|
||||||
if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
|
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
|
||||||
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
|
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
|
||||||
}
|
}
|
||||||
|
|
||||||
val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
|
val ecc_check = Cat((din.xorR ^ ecc_in.xorR) & ~sed_ded ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
|
||||||
io.ecc_out := ecc_check
|
val single_ecc_error = en & (ecc_check=/= 0.U) & ecc_check(6)
|
||||||
|
val double_ecc_error = en & (ecc_check=/= 0.U) & ~ecc_check(6)
|
||||||
io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
|
|
||||||
io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
|
|
||||||
val error_mask = Wire(Vec(39,UInt(1.W)))
|
val error_mask = Wire(Vec(39,UInt(1.W)))
|
||||||
|
|
||||||
for(i <- 1 until 40){
|
for(i <- 1 until 40){
|
||||||
error_mask(i-1) := ecc_check(5,0) === i.asUInt
|
error_mask(i-1) := ecc_check(5,0) === i.asUInt
|
||||||
}
|
}
|
||||||
val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
|
val din_plus_parity = Cat(ecc_in(6), din(31,26), ecc_in(5), din(25,11), ecc_in(4), din(10,4), ecc_in(3), din(3,1), ecc_in(2), din(0), ecc_in(1,0))
|
||||||
val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
|
val dout_plus_parity = Mux(single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
|
||||||
|
|
||||||
io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
|
val dout = Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
|
||||||
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
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val ecc_out = Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
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(ecc_out,dout,single_ecc_error,double_ecc_error)
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}
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}
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def rvecc_encode_64(din:UInt):UInt = {
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def rvecc_encode_64(din:UInt):UInt = {
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Reference in New Issue