diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index e0e01d8d..bed1eaae 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -986,406 +986,407 @@ circuit axi4_to_ahb : skip @[Conditional.scala 39:67] buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 345:11] cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 346:16] - node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:68] - node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 347:75] - node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 347:55] - node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 347:95] - node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:127] - wire _T_448 : UInt<8> - _T_448 <= UInt<8>("h00") - node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:44] - node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 176:51] - node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:75] - node _T_452 = eq(_T_451, UInt<4>("h0f")) @[axi4_to_ahb.scala 176:82] - node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 176:64] - node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:106] - node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 176:113] - node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 176:95] - node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15] - node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_459 = and(UInt<1>("h00"), _T_458) @[axi4_to_ahb.scala 176:24] - node _T_460 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 177:35] - node _T_461 = eq(_T_460, UInt<4>("h0c")) @[axi4_to_ahb.scala 177:42] - node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15] - node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 177:15] - node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 176:128] - node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 178:36] - node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 178:43] - node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 178:67] - node _T_469 = eq(_T_468, UInt<2>("h03")) @[axi4_to_ahb.scala 178:74] - node _T_470 = or(_T_467, _T_469) @[axi4_to_ahb.scala 178:56] - node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15] - node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 178:15] - node _T_474 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 179:37] - node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 179:44] - node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15] - node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 179:17] - node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 178:90] - node _T_480 = or(_T_465, _T_479) @[axi4_to_ahb.scala 177:58] - node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 347:147] - node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 347:38] - node _T_483 = cat(master_addr, _T_482) @[Cat.scala 29:58] - buf_addr_in <= _T_483 @[axi4_to_ahb.scala 347:15] - node _T_484 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 348:27] - buf_tag_in <= _T_484 @[axi4_to_ahb.scala 348:14] - node _T_485 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 349:32] - buf_byteen_in <= _T_485 @[axi4_to_ahb.scala 349:17] - node _T_486 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 350:33] - node _T_487 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 350:59] - node _T_488 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 350:80] - node _T_489 = mux(_T_486, _T_487, _T_488) @[axi4_to_ahb.scala 350:21] - buf_data_in <= _T_489 @[axi4_to_ahb.scala 350:15] - node _T_490 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:52] - node _T_491 = eq(_T_490, UInt<2>("h03")) @[axi4_to_ahb.scala 351:59] - node _T_492 = and(buf_aligned_in, _T_491) @[axi4_to_ahb.scala 351:38] - node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:85] - node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 351:92] - node _T_495 = and(_T_492, _T_494) @[axi4_to_ahb.scala 351:72] - node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 351:112] - node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:144] - wire _T_498 : UInt<8> - _T_498 <= UInt<8>("h00") - node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:43] - node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:50] - node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] - node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 168:25] - node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 169:34] - node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 169:41] - node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 169:63] - node _T_507 = eq(_T_506, UInt<4>("h0f")) @[axi4_to_ahb.scala 169:70] - node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 169:54] - node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15] - node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 169:16] - node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 168:65] - node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:34] - node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:41] - node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:63] - node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 170:70] - node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 170:54] - node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:92] - node _T_519 = eq(_T_518, UInt<4>("h0c")) @[axi4_to_ahb.scala 170:99] - node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 170:83] - node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:121] - node _T_522 = eq(_T_521, UInt<2>("h03")) @[axi4_to_ahb.scala 170:128] - node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 170:112] - node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15] - node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_526 = and(UInt<1>("h01"), _T_525) @[axi4_to_ahb.scala 170:16] - node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 169:86] - node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:164] - node _T_529 = mux(_T_496, _T_527, _T_528) @[axi4_to_ahb.scala 351:21] - buf_size_in <= _T_529 @[axi4_to_ahb.scala 351:15] - node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 352:32] - node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 352:39] - node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:17] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 353:24] - node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 352:51] - node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:50] - node _T_536 = eq(_T_535, UInt<1>("h01")) @[axi4_to_ahb.scala 353:57] - node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 353:36] - node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:84] - node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 353:91] - node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 353:70] - node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 354:18] - node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 354:25] - node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:55] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 354:62] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:90] - node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 354:97] - node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 354:74] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:125] - node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 354:132] - node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 354:109] - node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:161] - node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 354:168] - node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 354:145] - node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:21] - node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 355:28] - node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 354:181] - node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:56] - node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 355:63] - node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 355:40] - node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:92] - node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 355:99] - node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 355:76] - node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 354:38] - node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 353:104] - buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 352:18] - node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 357:39] - node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 357:58] - node _T_567 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:83] - node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58] - node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 357:104] - node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:129] - node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58] - node _T_572 = mux(_T_565, _T_568, _T_571) @[axi4_to_ahb.scala 357:22] - io.ahb_haddr <= _T_572 @[axi4_to_ahb.scala 357:16] - node _T_573 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:39] - node _T_574 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_575 = mux(_T_574, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_576 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 358:93] - node _T_577 = and(_T_575, _T_576) @[axi4_to_ahb.scala 358:80] - node _T_578 = cat(UInt<1>("h00"), _T_577) @[Cat.scala 29:58] - node _T_579 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_581 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 358:148] - node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 358:138] - node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_573, _T_578, _T_583) @[axi4_to_ahb.scala 358:22] - io.ahb_hsize <= _T_584 @[axi4_to_ahb.scala 358:16] + node _T_443 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 347:33] + node _T_444 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:73] + node _T_445 = eq(_T_444, UInt<1>("h01")) @[axi4_to_ahb.scala 347:80] + node _T_446 = and(buf_aligned_in, _T_445) @[axi4_to_ahb.scala 347:60] + node _T_447 = bits(_T_446, 0, 0) @[axi4_to_ahb.scala 347:100] + node _T_448 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:132] + wire _T_449 : UInt<8> + _T_449 <= UInt<8>("h00") + node _T_450 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:44] + node _T_451 = eq(_T_450, UInt<8>("h0ff")) @[axi4_to_ahb.scala 176:51] + node _T_452 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:75] + node _T_453 = eq(_T_452, UInt<4>("h0f")) @[axi4_to_ahb.scala 176:82] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 176:64] + node _T_455 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:106] + node _T_456 = eq(_T_455, UInt<2>("h03")) @[axi4_to_ahb.scala 176:113] + node _T_457 = or(_T_454, _T_456) @[axi4_to_ahb.scala 176:95] + node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(UInt<1>("h00"), _T_459) @[axi4_to_ahb.scala 176:24] + node _T_461 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 177:35] + node _T_462 = eq(_T_461, UInt<4>("h0c")) @[axi4_to_ahb.scala 177:42] + node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] + node _T_464 = mux(_T_463, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_465 = and(UInt<2>("h02"), _T_464) @[axi4_to_ahb.scala 177:15] + node _T_466 = or(_T_460, _T_465) @[axi4_to_ahb.scala 176:128] + node _T_467 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 178:36] + node _T_468 = eq(_T_467, UInt<8>("h0f0")) @[axi4_to_ahb.scala 178:43] + node _T_469 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 178:67] + node _T_470 = eq(_T_469, UInt<2>("h03")) @[axi4_to_ahb.scala 178:74] + node _T_471 = or(_T_468, _T_470) @[axi4_to_ahb.scala 178:56] + node _T_472 = bits(_T_471, 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(UInt<3>("h04"), _T_473) @[axi4_to_ahb.scala 178:15] + node _T_475 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 179:37] + node _T_476 = eq(_T_475, UInt<8>("h0c0")) @[axi4_to_ahb.scala 179:44] + node _T_477 = bits(_T_476, 0, 0) @[Bitwise.scala 72:15] + node _T_478 = mux(_T_477, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_479 = and(UInt<3>("h06"), _T_478) @[axi4_to_ahb.scala 179:17] + node _T_480 = or(_T_474, _T_479) @[axi4_to_ahb.scala 178:90] + node _T_481 = or(_T_466, _T_480) @[axi4_to_ahb.scala 177:58] + node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 347:152] + node _T_483 = mux(_T_447, _T_481, _T_482) @[axi4_to_ahb.scala 347:43] + node _T_484 = cat(_T_443, _T_483) @[Cat.scala 29:58] + buf_addr_in <= _T_484 @[axi4_to_ahb.scala 347:15] + node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 348:27] + buf_tag_in <= _T_485 @[axi4_to_ahb.scala 348:14] + node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 349:32] + buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 349:17] + node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 350:33] + node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 350:59] + node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 350:80] + node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 350:21] + buf_data_in <= _T_490 @[axi4_to_ahb.scala 350:15] + node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:52] + node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 351:59] + node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 351:38] + node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:85] + node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 351:92] + node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 351:72] + node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 351:112] + node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:144] + wire _T_499 : UInt<8> + _T_499 <= UInt<8>("h00") + node _T_500 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 168:43] + node _T_501 = eq(_T_500, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:50] + node _T_502 = bits(_T_501, 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(UInt<2>("h03"), _T_503) @[axi4_to_ahb.scala 168:25] + node _T_505 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 169:34] + node _T_506 = eq(_T_505, UInt<8>("h0f0")) @[axi4_to_ahb.scala 169:41] + node _T_507 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 169:63] + node _T_508 = eq(_T_507, UInt<4>("h0f")) @[axi4_to_ahb.scala 169:70] + node _T_509 = or(_T_506, _T_508) @[axi4_to_ahb.scala 169:54] + node _T_510 = bits(_T_509, 0, 0) @[Bitwise.scala 72:15] + node _T_511 = mux(_T_510, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_512 = and(UInt<2>("h02"), _T_511) @[axi4_to_ahb.scala 169:16] + node _T_513 = or(_T_504, _T_512) @[axi4_to_ahb.scala 168:65] + node _T_514 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 170:34] + node _T_515 = eq(_T_514, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:41] + node _T_516 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 170:63] + node _T_517 = eq(_T_516, UInt<6>("h030")) @[axi4_to_ahb.scala 170:70] + node _T_518 = or(_T_515, _T_517) @[axi4_to_ahb.scala 170:54] + node _T_519 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 170:92] + node _T_520 = eq(_T_519, UInt<4>("h0c")) @[axi4_to_ahb.scala 170:99] + node _T_521 = or(_T_518, _T_520) @[axi4_to_ahb.scala 170:83] + node _T_522 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 170:121] + node _T_523 = eq(_T_522, UInt<2>("h03")) @[axi4_to_ahb.scala 170:128] + node _T_524 = or(_T_521, _T_523) @[axi4_to_ahb.scala 170:112] + node _T_525 = bits(_T_524, 0, 0) @[Bitwise.scala 72:15] + node _T_526 = mux(_T_525, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_527 = and(UInt<1>("h01"), _T_526) @[axi4_to_ahb.scala 170:16] + node _T_528 = or(_T_513, _T_527) @[axi4_to_ahb.scala 169:86] + node _T_529 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:164] + node _T_530 = mux(_T_497, _T_528, _T_529) @[axi4_to_ahb.scala 351:21] + buf_size_in <= _T_530 @[axi4_to_ahb.scala 351:15] + node _T_531 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 352:32] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[axi4_to_ahb.scala 352:39] + node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:17] + node _T_534 = eq(_T_533, UInt<1>("h00")) @[axi4_to_ahb.scala 353:24] + node _T_535 = or(_T_532, _T_534) @[axi4_to_ahb.scala 352:51] + node _T_536 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:50] + node _T_537 = eq(_T_536, UInt<1>("h01")) @[axi4_to_ahb.scala 353:57] + node _T_538 = or(_T_535, _T_537) @[axi4_to_ahb.scala 353:36] + node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:84] + node _T_540 = eq(_T_539, UInt<2>("h02")) @[axi4_to_ahb.scala 353:91] + node _T_541 = or(_T_538, _T_540) @[axi4_to_ahb.scala 353:70] + node _T_542 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 354:18] + node _T_543 = eq(_T_542, UInt<2>("h03")) @[axi4_to_ahb.scala 354:25] + node _T_544 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:55] + node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 354:62] + node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:90] + node _T_547 = eq(_T_546, UInt<4>("h0c")) @[axi4_to_ahb.scala 354:97] + node _T_548 = or(_T_545, _T_547) @[axi4_to_ahb.scala 354:74] + node _T_549 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:125] + node _T_550 = eq(_T_549, UInt<6>("h030")) @[axi4_to_ahb.scala 354:132] + node _T_551 = or(_T_548, _T_550) @[axi4_to_ahb.scala 354:109] + node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:161] + node _T_553 = eq(_T_552, UInt<8>("h0c0")) @[axi4_to_ahb.scala 354:168] + node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 354:145] + node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:21] + node _T_556 = eq(_T_555, UInt<4>("h0f")) @[axi4_to_ahb.scala 355:28] + node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 354:181] + node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:56] + node _T_559 = eq(_T_558, UInt<8>("h0f0")) @[axi4_to_ahb.scala 355:63] + node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 355:40] + node _T_561 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:92] + node _T_562 = eq(_T_561, UInt<8>("h0ff")) @[axi4_to_ahb.scala 355:99] + node _T_563 = or(_T_560, _T_562) @[axi4_to_ahb.scala 355:76] + node _T_564 = and(_T_543, _T_563) @[axi4_to_ahb.scala 354:38] + node _T_565 = or(_T_541, _T_564) @[axi4_to_ahb.scala 353:104] + buf_aligned_in <= _T_565 @[axi4_to_ahb.scala 352:18] + node _T_566 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 357:39] + node _T_567 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 357:58] + node _T_568 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:83] + node _T_569 = cat(_T_567, _T_568) @[Cat.scala 29:58] + node _T_570 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 357:104] + node _T_571 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:129] + node _T_572 = cat(_T_570, _T_571) @[Cat.scala 29:58] + node _T_573 = mux(_T_566, _T_569, _T_572) @[axi4_to_ahb.scala 357:22] + io.ahb_haddr <= _T_573 @[axi4_to_ahb.scala 357:16] + node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:39] + node _T_575 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_576 = mux(_T_575, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 358:93] + node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 358:80] + node _T_579 = cat(UInt<1>("h00"), _T_578) @[Cat.scala 29:58] + node _T_580 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 358:148] + node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 358:138] + node _T_584 = cat(UInt<1>("h00"), _T_583) @[Cat.scala 29:58] + node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 358:22] + io.ahb_hsize <= _T_585 @[axi4_to_ahb.scala 358:16] io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 360:17] io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 361:20] - node _T_585 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 362:47] - node _T_586 = not(_T_585) @[axi4_to_ahb.scala 362:33] - node _T_587 = cat(UInt<1>("h01"), _T_586) @[Cat.scala 29:58] - io.ahb_hprot <= _T_587 @[axi4_to_ahb.scala 362:16] - node _T_588 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 363:40] - node _T_589 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 363:55] - node _T_590 = eq(_T_589, UInt<1>("h01")) @[axi4_to_ahb.scala 363:62] - node _T_591 = mux(_T_588, _T_590, buf_write) @[axi4_to_ahb.scala 363:23] - io.ahb_hwrite <= _T_591 @[axi4_to_ahb.scala 363:17] - node _T_592 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:28] - io.ahb_hwdata <= _T_592 @[axi4_to_ahb.scala 364:17] + node _T_586 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 362:47] + node _T_587 = not(_T_586) @[axi4_to_ahb.scala 362:33] + node _T_588 = cat(UInt<1>("h01"), _T_587) @[Cat.scala 29:58] + io.ahb_hprot <= _T_588 @[axi4_to_ahb.scala 362:16] + node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 363:40] + node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 363:55] + node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 363:62] + node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 363:23] + io.ahb_hwrite <= _T_592 @[axi4_to_ahb.scala 363:17] + node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:28] + io.ahb_hwdata <= _T_593 @[axi4_to_ahb.scala 364:17] slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 366:15] - node _T_593 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 367:43] - node _T_594 = mux(_T_593, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 367:23] - node _T_595 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_597 = and(_T_596, UInt<2>("h02")) @[axi4_to_ahb.scala 367:88] - node _T_598 = cat(_T_594, _T_597) @[Cat.scala 29:58] - slave_opc <= _T_598 @[axi4_to_ahb.scala 367:13] - node _T_599 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 368:41] - node _T_600 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 368:66] - node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58] - node _T_602 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 368:91] - node _T_603 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 368:110] - node _T_604 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 368:131] - node _T_605 = mux(_T_602, _T_603, _T_604) @[axi4_to_ahb.scala 368:79] - node _T_606 = mux(_T_599, _T_601, _T_605) @[axi4_to_ahb.scala 368:21] - slave_rdata <= _T_606 @[axi4_to_ahb.scala 368:15] - node _T_607 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 369:26] - slave_tag <= _T_607 @[axi4_to_ahb.scala 369:13] - node _T_608 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 371:33] - node _T_609 = neq(_T_608, UInt<1>("h00")) @[axi4_to_ahb.scala 371:40] - node _T_610 = and(_T_609, io.ahb_hready) @[axi4_to_ahb.scala 371:52] - node _T_611 = and(_T_610, io.ahb_hwrite) @[axi4_to_ahb.scala 371:68] - last_addr_en <= _T_611 @[axi4_to_ahb.scala 371:16] - node _T_612 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 373:30] - node _T_613 = and(_T_612, master_ready) @[axi4_to_ahb.scala 373:47] - wrbuf_en <= _T_613 @[axi4_to_ahb.scala 373:12] - node _T_614 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 374:34] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 374:50] - wrbuf_data_en <= _T_615 @[axi4_to_ahb.scala 374:17] - node _T_616 = and(master_valid, master_ready) @[axi4_to_ahb.scala 375:34] - node _T_617 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 375:62] - node _T_618 = eq(_T_617, UInt<1>("h01")) @[axi4_to_ahb.scala 375:69] - node _T_619 = and(_T_616, _T_618) @[axi4_to_ahb.scala 375:49] - wrbuf_cmd_sent <= _T_619 @[axi4_to_ahb.scala 375:18] - node _T_620 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 376:33] - node _T_621 = and(wrbuf_cmd_sent, _T_620) @[axi4_to_ahb.scala 376:31] - wrbuf_rst <= _T_621 @[axi4_to_ahb.scala 376:13] - node _T_622 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 378:35] - node _T_623 = and(wrbuf_vld, _T_622) @[axi4_to_ahb.scala 378:33] - node _T_624 = eq(_T_623, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21] - node _T_625 = and(_T_624, master_ready) @[axi4_to_ahb.scala 378:52] - io.axi_awready <= _T_625 @[axi4_to_ahb.scala 378:18] - node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 379:39] - node _T_627 = and(wrbuf_data_vld, _T_626) @[axi4_to_ahb.scala 379:37] - node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 379:20] - node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 379:56] - io.axi_wready <= _T_629 @[axi4_to_ahb.scala 379:17] - node _T_630 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 380:33] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 380:21] - node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 380:51] - io.axi_arready <= _T_632 @[axi4_to_ahb.scala 380:18] + node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 367:43] + node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 367:23] + node _T_596 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 367:88] + node _T_599 = cat(_T_595, _T_598) @[Cat.scala 29:58] + slave_opc <= _T_599 @[axi4_to_ahb.scala 367:13] + node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 368:41] + node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 368:66] + node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] + node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 368:91] + node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 368:110] + node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 368:131] + node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 368:79] + node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 368:21] + slave_rdata <= _T_607 @[axi4_to_ahb.scala 368:15] + node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 369:26] + slave_tag <= _T_608 @[axi4_to_ahb.scala 369:13] + node _T_609 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 371:33] + node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 371:40] + node _T_611 = and(_T_610, io.ahb_hready) @[axi4_to_ahb.scala 371:52] + node _T_612 = and(_T_611, io.ahb_hwrite) @[axi4_to_ahb.scala 371:68] + last_addr_en <= _T_612 @[axi4_to_ahb.scala 371:16] + node _T_613 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 373:30] + node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 373:47] + wrbuf_en <= _T_614 @[axi4_to_ahb.scala 373:12] + node _T_615 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 374:34] + node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 374:50] + wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 374:17] + node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 375:34] + node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 375:62] + node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 375:69] + node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 375:49] + wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 375:18] + node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 376:33] + node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 376:31] + wrbuf_rst <= _T_622 @[axi4_to_ahb.scala 376:13] + node _T_623 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 378:35] + node _T_624 = and(wrbuf_vld, _T_623) @[axi4_to_ahb.scala 378:33] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21] + node _T_626 = and(_T_625, master_ready) @[axi4_to_ahb.scala 378:52] + io.axi_awready <= _T_626 @[axi4_to_ahb.scala 378:18] + node _T_627 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 379:39] + node _T_628 = and(wrbuf_data_vld, _T_627) @[axi4_to_ahb.scala 379:37] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 379:20] + node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 379:56] + io.axi_wready <= _T_630 @[axi4_to_ahb.scala 379:17] + node _T_631 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 380:33] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[axi4_to_ahb.scala 380:21] + node _T_633 = and(_T_632, master_ready) @[axi4_to_ahb.scala 380:51] + io.axi_arready <= _T_633 @[axi4_to_ahb.scala 380:18] io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 381:16] - node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:68] - node _T_634 = mux(_T_633, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 384:52] - node _T_635 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 384:88] - node _T_636 = and(_T_634, _T_635) @[axi4_to_ahb.scala 384:86] - reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 384:48] - _T_637 <= _T_636 @[axi4_to_ahb.scala 384:48] - wrbuf_vld <= _T_637 @[axi4_to_ahb.scala 384:18] - node _T_638 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 385:73] - node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 385:52] - node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 385:99] - node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 385:97] - reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 385:48] - _T_642 <= _T_641 @[axi4_to_ahb.scala 385:48] - wrbuf_data_vld <= _T_642 @[axi4_to_ahb.scala 385:18] - node _T_643 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 387:57] - node _T_644 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 387:91] - reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_644 : @[Reg.scala 28:19] - _T_645 <= _T_643 @[Reg.scala 28:23] + node _T_634 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:68] + node _T_635 = mux(_T_634, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 384:52] + node _T_636 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 384:88] + node _T_637 = and(_T_635, _T_636) @[axi4_to_ahb.scala 384:86] + reg _T_638 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 384:48] + _T_638 <= _T_637 @[axi4_to_ahb.scala 384:48] + wrbuf_vld <= _T_638 @[axi4_to_ahb.scala 384:18] + node _T_639 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 385:73] + node _T_640 = mux(_T_639, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 385:52] + node _T_641 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 385:99] + node _T_642 = and(_T_640, _T_641) @[axi4_to_ahb.scala 385:97] + reg _T_643 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 385:48] + _T_643 <= _T_642 @[axi4_to_ahb.scala 385:48] + wrbuf_data_vld <= _T_643 @[axi4_to_ahb.scala 385:18] + node _T_644 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 387:57] + node _T_645 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 387:91] + reg _T_646 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_645 : @[Reg.scala 28:19] + _T_646 <= _T_644 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_645 @[axi4_to_ahb.scala 387:13] - node _T_646 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 388:60] - node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:88] - reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_647 : @[Reg.scala 28:19] - _T_648 <= _T_646 @[Reg.scala 28:23] + wrbuf_tag <= _T_646 @[axi4_to_ahb.scala 387:13] + node _T_647 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 388:60] + node _T_648 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:88] + reg _T_649 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_648 : @[Reg.scala 28:19] + _T_649 <= _T_647 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_648 @[axi4_to_ahb.scala 388:14] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 390:48] + wrbuf_size <= _T_649 @[axi4_to_ahb.scala 388:14] + node _T_650 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 390:48] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_649 @[el2_lib.scala 511:17] + rvclkhdr_2.io.en <= _T_650 @[el2_lib.scala 511:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_650 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_650 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_650 @[axi4_to_ahb.scala 390:14] - node _T_651 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 391:52] + reg _T_651 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_651 <= io.axi_awaddr @[el2_lib.scala 514:16] + wrbuf_addr <= _T_651 @[axi4_to_ahb.scala 390:14] + node _T_652 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 391:52] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_651 @[el2_lib.scala 511:17] + rvclkhdr_3.io.en <= _T_652 @[el2_lib.scala 511:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_652 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_652 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_652 @[axi4_to_ahb.scala 391:14] - node _T_653 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 394:27] - node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 394:60] - reg _T_655 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_654 : @[Reg.scala 28:19] - _T_655 <= _T_653 @[Reg.scala 28:23] + reg _T_653 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_653 <= io.axi_wdata @[el2_lib.scala 514:16] + wrbuf_data <= _T_653 @[axi4_to_ahb.scala 391:14] + node _T_654 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 394:27] + node _T_655 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 394:60] + reg _T_656 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_655 : @[Reg.scala 28:19] + _T_656 <= _T_654 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_655 @[axi4_to_ahb.scala 393:16] - node _T_656 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 397:27] - node _T_657 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 397:60] - reg _T_658 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_657 : @[Reg.scala 28:19] - _T_658 <= _T_656 @[Reg.scala 28:23] + wrbuf_byteen <= _T_656 @[axi4_to_ahb.scala 393:16] + node _T_657 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 397:27] + node _T_658 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 397:60] + reg _T_659 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_658 : @[Reg.scala 28:19] + _T_659 <= _T_657 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_658 @[axi4_to_ahb.scala 396:17] - node _T_659 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 405:50] - reg _T_660 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= buf_write_in @[Reg.scala 28:23] + last_bus_addr <= _T_659 @[axi4_to_ahb.scala 396:17] + node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 405:50] + reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_660 : @[Reg.scala 28:19] + _T_661 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_660 @[axi4_to_ahb.scala 404:13] - node _T_661 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 408:25] - node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 408:60] - reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_662 : @[Reg.scala 28:19] - _T_663 <= _T_661 @[Reg.scala 28:23] + buf_write <= _T_661 @[axi4_to_ahb.scala 404:13] + node _T_662 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 408:25] + node _T_663 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 408:60] + reg _T_664 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_663 : @[Reg.scala 28:19] + _T_664 <= _T_662 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_663 @[axi4_to_ahb.scala 407:11] - node _T_664 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 411:33] - node _T_665 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 411:52] - node _T_666 = bits(_T_665, 0, 0) @[axi4_to_ahb.scala 411:69] + buf_tag <= _T_664 @[axi4_to_ahb.scala 407:11] + node _T_665 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 411:33] + node _T_666 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 411:52] + node _T_667 = bits(_T_666, 0, 0) @[axi4_to_ahb.scala 411:69] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_666 @[el2_lib.scala 511:17] + rvclkhdr_4.io.en <= _T_667 @[el2_lib.scala 511:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_667 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_667 <= _T_664 @[el2_lib.scala 514:16] - buf_addr <= _T_667 @[axi4_to_ahb.scala 411:12] - node _T_668 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 414:26] - node _T_669 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 414:55] - reg _T_670 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_669 : @[Reg.scala 28:19] - _T_670 <= _T_668 @[Reg.scala 28:23] + reg _T_668 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_668 <= _T_665 @[el2_lib.scala 514:16] + buf_addr <= _T_668 @[axi4_to_ahb.scala 411:12] + node _T_669 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 414:26] + node _T_670 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 414:55] + reg _T_671 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + _T_671 <= _T_669 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_670 @[axi4_to_ahb.scala 413:12] - node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 417:52] - reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= buf_aligned_in @[Reg.scala 28:23] + buf_size <= _T_671 @[axi4_to_ahb.scala 413:12] + node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 417:52] + reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_672 @[axi4_to_ahb.scala 416:15] - node _T_673 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 420:28] - node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 420:57] - reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_674 : @[Reg.scala 28:19] - _T_675 <= _T_673 @[Reg.scala 28:23] + buf_aligned <= _T_673 @[axi4_to_ahb.scala 416:15] + node _T_674 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 420:28] + node _T_675 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 420:57] + reg _T_676 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_675 : @[Reg.scala 28:19] + _T_676 <= _T_674 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_675 @[axi4_to_ahb.scala 419:14] - node _T_676 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 423:33] - node _T_677 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 423:57] - node _T_678 = bits(_T_677, 0, 0) @[axi4_to_ahb.scala 423:80] + buf_byteen <= _T_676 @[axi4_to_ahb.scala 419:14] + node _T_677 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 423:33] + node _T_678 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 423:57] + node _T_679 = bits(_T_678, 0, 0) @[axi4_to_ahb.scala 423:80] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_678 @[el2_lib.scala 511:17] + rvclkhdr_5.io.en <= _T_679 @[el2_lib.scala 511:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_679 <= _T_676 @[el2_lib.scala 514:16] - buf_data <= _T_679 @[axi4_to_ahb.scala 423:12] - node _T_680 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 426:50] - reg _T_681 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_680 : @[Reg.scala 28:19] - _T_681 <= buf_write @[Reg.scala 28:23] + reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_680 <= _T_677 @[el2_lib.scala 514:16] + buf_data <= _T_680 @[axi4_to_ahb.scala 423:12] + node _T_681 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 426:50] + reg _T_682 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_681 : @[Reg.scala 28:19] + _T_682 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_681 @[axi4_to_ahb.scala 425:16] - node _T_682 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 429:22] - node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 429:60] - reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_683 : @[Reg.scala 28:19] - _T_684 <= _T_682 @[Reg.scala 28:23] + slvbuf_write <= _T_682 @[axi4_to_ahb.scala 425:16] + node _T_683 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 429:22] + node _T_684 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 429:60] + reg _T_685 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_684 : @[Reg.scala 28:19] + _T_685 <= _T_683 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_684 @[axi4_to_ahb.scala 428:14] - node _T_685 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 432:59] - reg _T_686 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= slvbuf_error_in @[Reg.scala 28:23] + slvbuf_tag <= _T_685 @[axi4_to_ahb.scala 428:14] + node _T_686 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 432:59] + reg _T_687 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_686 : @[Reg.scala 28:19] + _T_687 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_686 @[axi4_to_ahb.scala 431:16] - node _T_687 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 436:32] - node _T_688 = mux(_T_687, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 436:16] - node _T_689 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 436:52] - node _T_690 = and(_T_688, _T_689) @[axi4_to_ahb.scala 436:50] - reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 436:12] - _T_691 <= _T_690 @[axi4_to_ahb.scala 436:12] - cmd_doneQ <= _T_691 @[axi4_to_ahb.scala 435:13] - node _T_692 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 440:31] - node _T_693 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 440:70] - reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_693 : @[Reg.scala 28:19] - _T_694 <= _T_692 @[Reg.scala 28:23] + slvbuf_error <= _T_687 @[axi4_to_ahb.scala 431:16] + node _T_688 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 436:32] + node _T_689 = mux(_T_688, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 436:16] + node _T_690 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 436:52] + node _T_691 = and(_T_689, _T_690) @[axi4_to_ahb.scala 436:50] + reg _T_692 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 436:12] + _T_692 <= _T_691 @[axi4_to_ahb.scala 436:12] + cmd_doneQ <= _T_692 @[axi4_to_ahb.scala 435:13] + node _T_693 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 440:31] + node _T_694 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 440:70] + reg _T_695 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_694 : @[Reg.scala 28:19] + _T_695 <= _T_693 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_694 @[axi4_to_ahb.scala 439:21] - reg _T_695 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 445:12] - _T_695 <= io.ahb_hready @[axi4_to_ahb.scala 445:12] - ahb_hready_q <= _T_695 @[axi4_to_ahb.scala 444:16] - node _T_696 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 448:26] - reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 448:12] - _T_697 <= _T_696 @[axi4_to_ahb.scala 448:12] - ahb_htrans_q <= _T_697 @[axi4_to_ahb.scala 447:16] - reg _T_698 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 451:12] - _T_698 <= io.ahb_hwrite @[axi4_to_ahb.scala 451:12] - ahb_hwrite_q <= _T_698 @[axi4_to_ahb.scala 450:16] - reg _T_699 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 454:12] - _T_699 <= io.ahb_hresp @[axi4_to_ahb.scala 454:12] - ahb_hresp_q <= _T_699 @[axi4_to_ahb.scala 453:15] - node _T_700 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 457:26] - reg _T_701 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 457:12] - _T_701 <= _T_700 @[axi4_to_ahb.scala 457:12] - ahb_hrdata_q <= _T_701 @[axi4_to_ahb.scala 456:16] - node _T_702 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 460:43] - node _T_703 = or(_T_702, io.clk_override) @[axi4_to_ahb.scala 460:58] - node _T_704 = and(io.bus_clk_en, _T_703) @[axi4_to_ahb.scala 460:30] - buf_clken <= _T_704 @[axi4_to_ahb.scala 460:13] - node _T_705 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 461:69] - node _T_706 = and(io.ahb_hready, _T_705) @[axi4_to_ahb.scala 461:54] - node _T_707 = or(_T_706, io.clk_override) @[axi4_to_ahb.scala 461:74] - node _T_708 = and(io.bus_clk_en, _T_707) @[axi4_to_ahb.scala 461:36] - ahbm_addr_clken <= _T_708 @[axi4_to_ahb.scala 461:19] - node _T_709 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 462:50] - node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 462:60] - node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 462:36] - ahbm_data_clken <= _T_711 @[axi4_to_ahb.scala 462:19] + buf_cmd_byte_ptrQ <= _T_695 @[axi4_to_ahb.scala 439:21] + reg _T_696 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 445:12] + _T_696 <= io.ahb_hready @[axi4_to_ahb.scala 445:12] + ahb_hready_q <= _T_696 @[axi4_to_ahb.scala 444:16] + node _T_697 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 448:26] + reg _T_698 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 448:12] + _T_698 <= _T_697 @[axi4_to_ahb.scala 448:12] + ahb_htrans_q <= _T_698 @[axi4_to_ahb.scala 447:16] + reg _T_699 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 451:12] + _T_699 <= io.ahb_hwrite @[axi4_to_ahb.scala 451:12] + ahb_hwrite_q <= _T_699 @[axi4_to_ahb.scala 450:16] + reg _T_700 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 454:12] + _T_700 <= io.ahb_hresp @[axi4_to_ahb.scala 454:12] + ahb_hresp_q <= _T_700 @[axi4_to_ahb.scala 453:15] + node _T_701 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 457:26] + reg _T_702 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 457:12] + _T_702 <= _T_701 @[axi4_to_ahb.scala 457:12] + ahb_hrdata_q <= _T_702 @[axi4_to_ahb.scala 456:16] + node _T_703 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 460:43] + node _T_704 = or(_T_703, io.clk_override) @[axi4_to_ahb.scala 460:58] + node _T_705 = and(io.bus_clk_en, _T_704) @[axi4_to_ahb.scala 460:30] + buf_clken <= _T_705 @[axi4_to_ahb.scala 460:13] + node _T_706 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 461:69] + node _T_707 = and(io.ahb_hready, _T_706) @[axi4_to_ahb.scala 461:54] + node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 461:74] + node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 461:36] + ahbm_addr_clken <= _T_709 @[axi4_to_ahb.scala 461:19] + node _T_710 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 462:50] + node _T_711 = or(_T_710, io.clk_override) @[axi4_to_ahb.scala 462:60] + node _T_712 = and(io.bus_clk_en, _T_711) @[axi4_to_ahb.scala 462:36] + ahbm_data_clken <= _T_712 @[axi4_to_ahb.scala 462:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 151c9dd1..c32f28cf 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -245,21 +245,21 @@ module axi4_to_ahb( wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 210:32] wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 158:21 axi4_to_ahb.scala 465:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 367:23] + wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 367:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 367:88] - wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58] + wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 367:88] + wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58] wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 211:49] reg slvbuf_tag; // @[Reg.scala 27:20] wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 214:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 368:91] + wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 368:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 468:17] reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 457:12] - wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 368:79] + wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 368:79] wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 221:56] wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 221:91] wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 221:74] @@ -407,73 +407,72 @@ module axi4_to_ahb( wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_88; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_92; // @[Conditional.scala 40:58] - wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 353:24] - wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 352:51] - wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 353:57] - wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 353:36] - wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 353:91] - wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 353:70] - wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 354:25] - wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 354:62] - wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 354:97] - wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 354:74] - wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 354:132] - wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 354:109] - wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 354:168] - wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 354:145] - wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 355:28] - wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 354:181] - wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 355:63] - wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 355:40] - wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 355:99] - wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 355:76] - wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 354:38] - wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 353:104] - wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 347:55] - wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 347:38] - wire [34:0] _T_483 = {master_addr,_T_482}; // @[Cat.scala 29:58] - wire _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 350:33] - wire _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 351:38] - wire _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 351:72] - wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 351:21] - wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 351:15] - wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 358:80] - wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58] - wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_534 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 353:24] + wire _T_535 = _T_101 | _T_534; // @[axi4_to_ahb.scala 352:51] + wire _T_537 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 353:57] + wire _T_538 = _T_535 | _T_537; // @[axi4_to_ahb.scala 353:36] + wire _T_540 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 353:91] + wire _T_541 = _T_538 | _T_540; // @[axi4_to_ahb.scala 353:70] + wire _T_543 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 354:25] + wire _T_545 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 354:62] + wire _T_547 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 354:97] + wire _T_548 = _T_545 | _T_547; // @[axi4_to_ahb.scala 354:74] + wire _T_550 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 354:132] + wire _T_551 = _T_548 | _T_550; // @[axi4_to_ahb.scala 354:109] + wire _T_553 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 354:168] + wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 354:145] + wire _T_556 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 355:28] + wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 354:181] + wire _T_559 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 355:63] + wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 355:40] + wire _T_562 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 355:99] + wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 355:76] + wire _T_564 = _T_543 & _T_563; // @[axi4_to_ahb.scala 354:38] + wire buf_aligned_in = _T_541 | _T_564; // @[axi4_to_ahb.scala 353:104] + wire _T_446 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 347:60] + wire [2:0] _T_483 = _T_446 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 347:43] + wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 350:33] + wire _T_493 = buf_aligned_in & _T_543; // @[axi4_to_ahb.scala 351:38] + wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 351:72] + wire [1:0] _T_530 = _T_496 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 351:21] + wire [31:0] _T_569 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_572 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_530}; // @[axi4_to_ahb.scala 351:15] + wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 358:80] + wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58] + wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 358:138] - wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] - wire _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 362:33] - wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58] + wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 358:138] + wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58] + wire _T_587 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 362:33] + wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 371:40] - wire _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 371:52] - wire last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 371:68] + wire _T_610 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 371:40] + wire _T_611 = _T_610 & io_ahb_hready; // @[axi4_to_ahb.scala 371:52] + wire last_addr_en = _T_611 & io_ahb_hwrite; // @[axi4_to_ahb.scala 371:68] wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 373:47] wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 374:50] wire wrbuf_cmd_sent = _T_143 & _T_49; // @[axi4_to_ahb.scala 375:49] - wire _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 376:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 376:31] - wire _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 378:35] - wire _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 378:33] - wire _T_624 = ~_T_623; // @[axi4_to_ahb.scala 378:21] - wire _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 379:37] - wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 379:20] - wire _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 380:21] - wire _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 384:52] - wire _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 384:88] - wire _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 385:52] + wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 376:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 376:31] + wire _T_623 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 378:35] + wire _T_624 = wrbuf_vld & _T_623; // @[axi4_to_ahb.scala 378:33] + wire _T_625 = ~_T_624; // @[axi4_to_ahb.scala 378:21] + wire _T_628 = wrbuf_data_vld & _T_623; // @[axi4_to_ahb.scala 379:37] + wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 379:20] + wire _T_632 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 380:21] + wire _T_635 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 384:52] + wire _T_636 = ~wrbuf_rst; // @[axi4_to_ahb.scala 384:88] + wire _T_640 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 385:52] reg buf_tag; // @[Reg.scala 27:20] - wire _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 436:52] - wire _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 460:43] - wire _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 460:58] - wire _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 461:54] - wire _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 461:74] - wire _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 462:50] - wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 462:60] + wire _T_690 = ~slave_valid_pre; // @[axi4_to_ahb.scala 436:52] + wire _T_703 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 460:43] + wire _T_704 = _T_703 | io_clk_override; // @[axi4_to_ahb.scala 460:58] + wire _T_707 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 461:54] + wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 461:74] + wire _T_710 = buf_state != 3'h0; // @[axi4_to_ahb.scala 462:50] + wire _T_711 = _T_710 | io_clk_override; // @[axi4_to_ahb.scala 462:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -534,22 +533,22 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 378:18] - assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 379:17] + assign io_axi_awready = _T_625 & master_ready; // @[axi4_to_ahb.scala 378:18] + assign io_axi_wready = _T_629 & master_ready; // @[axi4_to_ahb.scala 379:17] assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 210:17] assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 211:16] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 212:14] - assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 380:18] + assign io_axi_arready = _T_632 & master_ready; // @[axi4_to_ahb.scala 380:18] assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 214:17] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 216:14] - assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 217:16] + assign io_axi_rdata = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 217:16] assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 215:16] assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 381:16] - assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 357:16] + assign io_ahb_haddr = bypass_en ? _T_569 : _T_572; // @[axi4_to_ahb.scala 357:16] assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 360:17] assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 361:20] - assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 362:16] - assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 358:16] + assign io_ahb_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 362:16] + assign io_ahb_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 358:16] assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_89; // @[axi4_to_ahb.scala 227:17 axi4_to_ahb.scala 258:21 axi4_to_ahb.scala 270:21 axi4_to_ahb.scala 285:21 axi4_to_ahb.scala 295:21 axi4_to_ahb.scala 315:21 axi4_to_ahb.scala 329:21] assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 363:17] assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 364:17] @@ -572,16 +571,16 @@ module axi4_to_ahb( assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_703; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_704; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_707; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_710; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_711; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -766,14 +765,14 @@ end // initial if (reset) begin wrbuf_vld <= 1'h0; end else begin - wrbuf_vld <= _T_634 & _T_635; + wrbuf_vld <= _T_635 & _T_636; end end always @(posedge bus_clk or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; end else begin - wrbuf_data_vld <= _T_639 & _T_635; + wrbuf_data_vld <= _T_640 & _T_636; end end always @(posedge ahbm_clk or posedge reset) begin @@ -808,7 +807,7 @@ end // initial if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_274 & _T_689; + cmd_doneQ <= _T_274 & _T_690; end end always @(posedge bus_clk or posedge reset) begin @@ -891,7 +890,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_486) begin + end else if (_T_487) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -908,7 +907,7 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= _T_483[31:0]; + buf_addr <= {master_addr[31:3],_T_483}; end end always @(posedge ahbm_clk or posedge reset) begin diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index d32f1bd4..2ef1bbe3 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -344,7 +344,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config buf_rst := false.B cmd_done_rst := slave_valid_pre - buf_addr_in := Cat(master_addr, Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) + buf_addr_in := Cat(master_addr(31,3),Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) buf_tag_in := master_tag(TAG - 1, 0) buf_byteen_in := wrbuf_byteen(7,0) buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0)) diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class index 4763185a..4756d5aa 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb.class and b/target/scala-2.12/classes/lib/axi4_to_ahb.class differ