QUASAR 2.0 Final

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Laraib Khan 2021-03-03 11:35:11 +05:00
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Quasar

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# Quasar RISC-V Core 1.0 from Lampro Mellon
This repository contains the SweRV-EL2 Core written in CHISEL named "Quasar".
## License
By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).
Files under the [tools](tools/) directory may be available under a different license. Please review individual file for details.
## Background
Quasar is a Chiselified version of EL2 SweRV RISC-V Core.
## Directory Structure
├── configs # Configurations dir
├── design
│ ├── project
│ ├── project
│ └── target
│ ├── snapshots
│ └── default # Where generated configuration files are created
│ ├── src
│ ├── main
│ ├── resources
│ └── vsrc # Blackbox files dir
│ └── scala # Design root dir
│ ├── dbg # Debugger
│ ├── dec # Decode, Registers and Exceptions
│ ├── dmi # DMI block
│ ├── exu # EXU (ALU/MUL/DIV)
│ ├── ifu # Fetch & Branch Prediction
│ ├── include # Bundles file
│ ├── lib # Bridges and Library
│ └── lsu # Load/Store
│ └── test
│ ├── target
│ └── test_run_dir
├── doc # PPA Report
├── generated_rtl # Quasar wrapper
├── testbench
│ ├── asm # Example assembly files
│ └── hex # Canned demo hex files
├── tools # Scripts/Makefiles
├── tracer_logs # generated log files
└── verif
├── LEC
└── sim # Simulation log/dump files
## Dependencies
- Verilator **(4.030 or later)** must be installed on the system if running with verilator.
- Vcs must be installed on the system if running with vcs.
- RISCV tool chain (based on gcc version 7.3 or higher) must be
installed so that it can be used to prepare RISCV binaries to run.
- Sbt **(1.3.13 or later)** must be installed on the system.
## Quickstart guide
1. Clone the repository
2. Setup RV_ROOT to point to the path in your local filesystem
3. Determine your configuration {optional}
4. Run make with $RV_ROOT/tools/Makefile
## Release Notes for this version
Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar.
### Configurations
Quasar can be configured by running the script:
```
$RV_ROOT/configs/quasar.config
```
For detailed help options.
```
$RV_ROOT/configs/quasar.config -h
```
For example, to build with a DCCM of size 64Kb:
```
$RV_ROOT/configs/quasar.config -dccm_size=64
```
This will update the **default** snapshot in `$RV_ROOT/design/snapshots/default/` with parameters for a 64K DCCM.
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
This script derives the following consistent set of include files :
```
$RV_ROOT/design/snapshots/default
├── common_defines.vh # `defines for testbench or design
├── defines.h # defines for C/assembly headers
├── param.vh # Design parameters
├── pdef.vh # Parameter structure
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
└── whisper.json # JSON file for swerv-iss
```
#### 1. Generate scala parameter
```
make -f $RV_ROOT/tools/Makefile conf
```
This script will run `quasar.config` and derives the include file:
```
$RV_ROOT/design/src/main/scala/lib
└── param.scala # Scala design parameters
```
### Running RTL Simulation
while in a work directory:
#### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
Example for bash shell:
```
export RV_ROOT=$(pwd)
```
Example for csh or its derivatives:
```
setenv RV_ROOT /path/to/QUASAR
```
#### 2. Create your specific configuration
*(Skip if default is sufficient)*
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
set BUILD_PATH environment variable:
```
setenv BUILD_PATH snapshots/mybuild
$RV_ROOT/configs/quasar.config [configuration options..] -snapshot=mybuild
```
Snapshots are placed in `$BUILD_PATH` directory.
#### 3. Run sbt
```
make -f $RV_ROOT/tools/Makefile sbt
```
This command will generate the Quasar wrapper in system verilog in the `generated_rtl` directory and runs the `reset_script.py`
* In the reset_script we do a post verilog-generation changes, these changes are as follows:
* Replace `posedge reset` with `negedge reset`
* Replace `if (reset)` with `if (~reset)`
#### 4. Running a simple Hello World program (verilator)
```
make -f $RV_ROOT/tools/Makefile
```
This command will build a verilator model of Quasar with AXI bus, and execute a short sequence of instructions that writes out "HELLO WORLD"
to the bus.
The simulation produces output on the screen like:
```
VerilatorTB: Start of sim
----------------------------------
Hello World from Quasar @LM !!
----------------------------------
TEST_PASSED
Finished : minstret = 437, mcycle = 922
See "exec.log" for execution trace with register updates..
```
The simulation generates following files in `$RV_ROOT/verif/sim`:
`console.log` contains what the cpu writes to the console address of 0xd0580000.
`exec.log` shows instruction trace with GPR updates.
`trace_port.csv` contains a log of the trace port.
Other log files are `dec.log`, `exu.log`, `ifu.log`, `lsu.log` and `pic.log`, generates in `$RV_ROOT/tracer_logs`.
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
You can re-execute simulation using:
```
make -f $RV_ROOT/tools/Makefile verilator
```
The simulation run/build command has following generic form:
```
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
```
where:
```
<simulator> - can be 'verilator' (by default) , 'vcs' - Synopsys VCS. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'.
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default.
TEST_DIR - alternative to test source directory testbench/asm or testbench/tests.
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument for runs on custom configurations.
CONF_PARAMS - allows to provide -set options to quasar.conf script to alter predefined targets parameters.
```
#### Default for VCS/Verilotor
If you want to run default configuration on verilator use the following command
```
make -f $RV_ROOT/tools/Makefile
```
For VCS use
```
make -f $RV_ROOT/tools/Makefile vcs_all
```
Example:
```
make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
```
will build and simulate `testbench/asm/cmark.c` program with verilator.
If you want to compile a test only, you can run:
```
make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
```
The Makefile uses `snapshot/<target>/link.ld` file, generated by quasar.conf script by default to build test executable. User can provide test specific linker file in form `<test_name>.ld` to build the test executable, in the same directory with the test source.
User also can create a test specific makefile in form `<test_name>.makefile`, containing building instructions how to create `program.hex` file used by simulation. The private makefile should be in the same directory as the test source. See examples in `testbench/asm` directory.
*(`program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.
User can build `program.hex` file by any other means and then run simulation with following command:
make -f $RV_ROOT/tools/Makefile <simulator>
Note: You may need to delete `program.hex` file from work directory, when run a new test.
The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
```
hello_world - default tes to run, prints Hello World message to screen and console.log
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
it from there. Runs on QUASAR with AXI4 buses only.
cmark - coremark benchmark running with code and data in external memories
cmark_dccm - the same as above, running data and stack from DCCM (faster)
cmark_iccm - the same as above with preloaded code to ICCM.
```
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.

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# Quasar RISC-V Core 1.0 from Lampro Mellon
## Release Notes
~~~
Initial release DATE
~~~

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# Quasar RISC-V Core from Lampro Mellon
## Configuration
### Contents
Name | Description
---------------------- | ------------------------------
quasar.config | Configuration script for core
quasar_config_gen.py | Python wrapper to run quasar.config
This script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.
A perl hash (*perl_configs.pl*) and a JSON format for SweRV-iss are also generated.
This set of include files :
```
./snapshots/<target>
├── common_defines.vh # `defines for testbench
├── defines.h # #defines for C/assembly headers
├── param.vh # Actual Design parameters
├── pdef.vh # Parameter structure definition
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
├── whisper.json # JSON file for swerv-iss
└── link.ld # Default linker file for tests
```
While the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.
### Targets
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
Target | Description
---------------------- | ------------------------------
default | Default configuration. AXI4 bus interface.
default_ahb | Default configuration, AHB-Lite bus interface
typical_pd | No ICCM, AXI4 bus interface
high_perf | Large BTB/BHT, AXI4 interface
`quasar.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.
**Run `$RV_ROOT/configs/quasar.config -h` for options and settable parameters.**

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#!/usr/bin/env python
from fusesoc.capi2.generator import Generator
import os
import shutil
import subprocess
import sys
import tempfile
if sys.version[0] == '2':
devnull = open(os.devnull, 'w')
else:
from subprocess import DEVNULL as devnull
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"configs/snapshots/default/common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/pdef.vh" : {
"copyto" : "config/pdef.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
tmp_dir = os.path.join(tempfile.mkdtemp(), 'core')
shutil.copytree(script_root, tmp_dir)
cwd = tmp_dir
env = os.environ.copy()
env['RV_ROOT'] = tmp_dir
args = ['configs/quasar.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=cwd, env=env, stdout=devnull)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
for f in filenames:
d = os.path.dirname(f)
if d and not os.path.exists(d):
os.makedirs(d)
shutil.copy2(os.path.join(cwd, f),f)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dbg|dbg>io_dbg_resume_req",
"sources":[
"~dbg|dbg>io_dec_tlu_mpc_halted_only",
"~dbg|dbg>io_core_dbg_cmd_done",
"~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
"~dbg|dbg>io_dbg_dma_dma_dbg_ready",
"~dbg|dbg>io_dbg_bus_clk_en",
"~dbg|dbg>io_sb_axi_r_valid",
"~dbg|dbg>io_sb_axi_r_ready",
"~dbg|dbg>io_sb_axi_b_valid",
"~dbg|dbg>io_sb_axi_b_ready",
"~dbg|dbg>reset",
"~dbg|dbg>io_sb_axi_ar_valid",
"~dbg|dbg>io_sb_axi_ar_ready",
"~dbg|dbg>io_sb_axi_aw_valid",
"~dbg|dbg>io_sb_axi_aw_ready",
"~dbg|dbg>io_sb_axi_w_valid",
"~dbg|dbg>io_sb_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dbg|dbg>io_dbg_core_rst_l",
"sources":[
"~dbg|dbg>io_scan_mode"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
"sources":[
"~dbg|dbg>io_dbg_dma_dma_dbg_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"dbg.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dbg"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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chisel-module-template

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<bytecodeTargetLevel target="1.8">
<module name="chisel-module-template" target="1.8" />
<module name="Quasar" target="1.8" />
</bytecodeTargetLevel>
</component>
</project>

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<option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
<option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
<option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
<option value="$PROJECT_DIR$/top.v" />
</set>
</value>
</entry>
<entry key="RANDOMIZE_MEM_INIT">
<value>
<set>
<option value="$PROJECT_DIR$/el2_dec.v" />
<option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
<option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
<option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
<option value="$PROJECT_DIR$/top.v" />
</set>
</value>
</entry>
<entry key="RANDOMIZE_REG_INIT">
<value>
<set>
<option value="$PROJECT_DIR$/el2_dec.v" />
<option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
<option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
<option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
<option value="$PROJECT_DIR$/top.v" />
</set>
</value>
</entry>
<entry key="SYNTHESIS">
<value>
<set>
<option value="$PROJECT_DIR$/el2_dec.v" />
<option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
<option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
<option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
<option value="$PROJECT_DIR$/top.v" />
</set>
</value>
</entry>
<entry key="VERILATOR">
<value>
<set>
<option value="$PROJECT_DIR$/el2_dec.v" />
<option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
<option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
<option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
<option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
<option value="$PROJECT_DIR$/src/main/resources/vsrc/el2_ifu_iccm_mem.sv" />
<option value="$PROJECT_DIR$/src/main/resources/vsrc/el2_lsu_dccm_mem.sv" />
<option value="$PROJECT_DIR$/top.v" />
</set>
</value>
</entry>
</map>
</option>
<option name="status" value="NORMAL" />
<option name="version" value="640" />
</component>
</project>

View File

@ -0,0 +1,6 @@
<component name="InspectionProjectProfileManager">
<profile version="1.0">
<option name="myName" value="Project Default" />
<inspection_tool class="ScalaStyle" enabled="false" level="WARNING" enabled_by_default="false" />
</profile>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: joda-time:joda-time:2.10.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: junit:junit:4.13:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.antlr:antlr4-runtime:4.7.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.apache.commons:commons-lang3:3.9:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.apache.commons:commons-text:1.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.fusesource.jansi:jansi:1.11:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.hamcrest:hamcrest-core:1.3:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.joda:joda-convert:2.2.0:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
</JAVADOC>
<SOURCES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
</SOURCES>
</library>
</component>

View File

@ -2,12 +2,15 @@
<library name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar">
<CLASSES>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
<root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
</CLASSES>
<JAVADOC>
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View File

@ -2,12 +2,15 @@
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View File

@ -15,9 +15,11 @@
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View File

@ -5,9 +5,11 @@
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View File

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View File

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View File

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View File

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View File

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894
design/.idea/misc.xml Normal file
View File

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<orderEntry type="library" name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar" level="project" />
<orderEntry type="library" name="sbt: junit:junit:4.13:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.yaml:snakeyaml:1.26:jar" level="project" />
<orderEntry type="library" name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang:scala-library:2.12.10:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang:scala-reflect:2.12.10:jar" level="project" />
<orderEntry type="library" name="sbt: org.antlr:antlr4-runtime:4.7.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar" level="project" />
<orderEntry type="sourceFolder" forTests="false" />
<orderEntry type="library" name="sbt: org.scala-sbt:test-interface:1.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.yaml:snakeyaml:1.26:jar" level="project" />
</component>
</module>

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@ -2,7 +2,7 @@
<project version="4">
<component name="ScalaCompilerConfiguration">
<profile name="sbt 1" modules="swerv-chislified-master_3681" />
<profile name="sbt 2" modules="Quasar,chisel-module-template">
<profile name="sbt 2" modules="chisel-module-template">
<parameters>
<parameter value="-Xsource:2.11" />
</parameters>

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@ -1,6 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="$PROJECT_DIR$/.." vcs="Git" />
<mapping directory="$PROJECT_DIR$" vcs="Git" />
</component>
</project>

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@ -3,8 +3,6 @@
def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// If we're building with Scala > 2.11, enable the compile option
// switch to support our anonymous Bundle definitions:
// https://github.com/scala/bug/issues/10047
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
case _ => Seq("-Xsource:2.11")
@ -26,14 +24,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
}
}
name := "Quasar"
organization := "https://www.lampromellon.com/"
name := "QUASAR"
version := "3.3.0"
scalaVersion := "2.12.10"
// Making the main-class
mainClass in (Compile, run) := Some("wrapper")
crossScalaVersions := Seq("2.12.10", "2.11.12")
resolvers ++= Seq(

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@ -0,0 +1,3 @@
/home/users/laraib.khan/Videos/Quasar/design/gated_latch.sv
/home/users/laraib.khan/Videos/Quasar/design/dmi_wrapper.sv
/home/users/laraib.khan/Videos/Quasar/design/mem.sv

547
design/mem.sv Normal file
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@ -0,0 +1,547 @@
//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} iccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} dccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_data_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_tag_ext_in_pkt_t;
module mem#(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH,
parameter DCCM_WIDTH_BITS,
parameter ICACHE_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS_WIDTH,
parameter ICACHE_TAG_BYPASS_ENABLE,
parameter ICACHE_NUM_BYPASS_WIDTH,
parameter ICACHE_BYPASS_ENABLE,
parameter ICACHE_LN_SZ
)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input logic dccm_ext_in_pkt_TEST1_0,
input logic dccm_ext_in_pkt_RME_0,
input logic [3:0] dccm_ext_in_pkt_RM_0,
input logic dccm_ext_in_pkt_LS_0,
input logic dccm_ext_in_pkt_DS_0,
input logic dccm_ext_in_pkt_SD_0,
input logic dccm_ext_in_pkt_TEST_RNM_0,
input logic dccm_ext_in_pkt_BC1_0,
input logic dccm_ext_in_pkt_BC2_0,
input logic dccm_ext_in_pkt_TEST1_1,
input logic dccm_ext_in_pkt_RME_1,
input logic [3:0] dccm_ext_in_pkt_RM_1,
input logic dccm_ext_in_pkt_LS_1,
input logic dccm_ext_in_pkt_DS_1,
input logic dccm_ext_in_pkt_SD_1,
input logic dccm_ext_in_pkt_TEST_RNM_1,
input logic dccm_ext_in_pkt_BC1_1,
input logic dccm_ext_in_pkt_BC2_1,
input logic dccm_ext_in_pkt_TEST1_2,
input logic dccm_ext_in_pkt_RME_2,
input logic [3:0] dccm_ext_in_pkt_RM_2,
input logic dccm_ext_in_pkt_LS_2,
input logic dccm_ext_in_pkt_DS_2,
input logic dccm_ext_in_pkt_SD_2,
input logic dccm_ext_in_pkt_TEST_RNM_2,
input logic dccm_ext_in_pkt_BC1_2,
input logic dccm_ext_in_pkt_BC2_2,
input logic dccm_ext_in_pkt_TEST1_3,
input logic dccm_ext_in_pkt_RME_3,
input logic [3:0] dccm_ext_in_pkt_RM_3,
input logic dccm_ext_in_pkt_LS_3,
input logic dccm_ext_in_pkt_DS_3,
input logic dccm_ext_in_pkt_SD_3,
input logic dccm_ext_in_pkt_TEST_RNM_3,
input logic dccm_ext_in_pkt_BC1_3,
input logic dccm_ext_in_pkt_BC2_3,
//`endif
//ICCM ports
input logic iccm_ext_in_pkt_TEST1_0,
input logic iccm_ext_in_pkt_RME_0,
input logic [3:0] iccm_ext_in_pkt_RM_0,
input logic iccm_ext_in_pkt_LS_0,
input logic iccm_ext_in_pkt_DS_0,
input logic iccm_ext_in_pkt_SD_0,
input logic iccm_ext_in_pkt_TEST_RNM_0,
input logic iccm_ext_in_pkt_BC1_0,
input logic iccm_ext_in_pkt_BC2_0,
input logic iccm_ext_in_pkt_TEST1_1,
input logic iccm_ext_in_pkt_RME_1,
input logic [3:0] iccm_ext_in_pkt_RM_1,
input logic iccm_ext_in_pkt_LS_1,
input logic iccm_ext_in_pkt_DS_1,
input logic iccm_ext_in_pkt_SD_1,
input logic iccm_ext_in_pkt_TEST_RNM_1,
input logic iccm_ext_in_pkt_BC1_1,
input logic iccm_ext_in_pkt_BC2_1,
input logic iccm_ext_in_pkt_TEST1_2,
input logic iccm_ext_in_pkt_RME_2,
input logic [3:0] iccm_ext_in_pkt_RM_2,
input logic iccm_ext_in_pkt_LS_2,
input logic iccm_ext_in_pkt_DS_2,
input logic iccm_ext_in_pkt_SD_2,
input logic iccm_ext_in_pkt_TEST_RNM_2,
input logic iccm_ext_in_pkt_BC1_2,
input logic iccm_ext_in_pkt_BC2_2,
input logic iccm_ext_in_pkt_TEST1_3,
input logic iccm_ext_in_pkt_RME_3,
input logic [3:0] iccm_ext_in_pkt_RM_3,
input logic iccm_ext_in_pkt_LS_3,
input logic iccm_ext_in_pkt_DS_3,
input logic iccm_ext_in_pkt_SD_3,
input logic iccm_ext_in_pkt_TEST_RNM_3,
input logic iccm_ext_in_pkt_BC1_3,
input logic iccm_ext_in_pkt_BC2_3,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
// input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input logic ic_tag_ext_in_pkt_TEST1_0,
input logic ic_tag_ext_in_pkt_RME_0,
input logic [3:0] ic_tag_ext_in_pkt_RM_0,
input logic ic_tag_ext_in_pkt_LS_0,
input logic ic_tag_ext_in_pkt_DS_0,
input logic ic_tag_ext_in_pkt_SD_0,
input logic ic_tag_ext_in_pkt_TEST_RNM_0,
input logic ic_tag_ext_in_pkt_BC1_0,
input logic ic_tag_ext_in_pkt_BC2_0,
input logic ic_tag_ext_in_pkt_TEST1_1,
input logic ic_tag_ext_in_pkt_RME_1,
input logic [3:0] ic_tag_ext_in_pkt_RM_1,
input logic ic_tag_ext_in_pkt_LS_1,
input logic ic_tag_ext_in_pkt_DS_1,
input logic ic_tag_ext_in_pkt_SD_1,
input logic ic_tag_ext_in_pkt_TEST_RNM_1,
input logic ic_tag_ext_in_pkt_BC1_1,
input logic ic_tag_ext_in_pkt_BC2_1,
input logic ic_data_ext_in_pkt_0_TEST1_0,
input logic ic_data_ext_in_pkt_0_RME_0,
input logic [3:0] ic_data_ext_in_pkt_0_RM_0,
input logic ic_data_ext_in_pkt_0_LS_0,
input logic ic_data_ext_in_pkt_0_DS_0,
input logic ic_data_ext_in_pkt_0_SD_0,
input logic ic_data_ext_in_pkt_0_TEST_RNM_0,
input logic ic_data_ext_in_pkt_0_BC1_0,
input logic ic_data_ext_in_pkt_0_BC2_0,
input logic ic_data_ext_in_pkt_0_TEST1_1,
input logic ic_data_ext_in_pkt_0_RME_1,
input logic [3:0] ic_data_ext_in_pkt_0_RM_1,
input logic ic_data_ext_in_pkt_0_LS_1,
input logic ic_data_ext_in_pkt_0_DS_1,
input logic ic_data_ext_in_pkt_0_SD_1,
input logic ic_data_ext_in_pkt_0_TEST_RNM_1,
input logic ic_data_ext_in_pkt_0_BC1_1,
input logic ic_data_ext_in_pkt_0_BC2_1,
input logic ic_data_ext_in_pkt_1_TEST1_0,
input logic ic_data_ext_in_pkt_1_RME_0,
input logic [3:0] ic_data_ext_in_pkt_1_RM_0,
input logic ic_data_ext_in_pkt_1_LS_0,
input logic ic_data_ext_in_pkt_1_DS_0,
input logic ic_data_ext_in_pkt_1_SD_0,
input logic ic_data_ext_in_pkt_1_TEST_RNM_0,
input logic ic_data_ext_in_pkt_1_BC1_0,
input logic ic_data_ext_in_pkt_1_BC2_0,
input logic ic_data_ext_in_pkt_1_TEST1_1,
input logic ic_data_ext_in_pkt_1_RME_1,
input logic [3:0] ic_data_ext_in_pkt_1_RM_1,
input logic ic_data_ext_in_pkt_1_LS_1,
input logic ic_data_ext_in_pkt_1_DS_1,
input logic ic_data_ext_in_pkt_1_SD_1,
input logic ic_data_ext_in_pkt_1_TEST_RNM_1,
input logic ic_data_ext_in_pkt_1_BC1_1,
input logic ic_data_ext_in_pkt_1_BC2_1,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt;
ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt;
assign dccm_ext_in_pkt[0].TEST1 = dccm_ext_in_pkt_TEST1_0;
assign dccm_ext_in_pkt[0].RME = dccm_ext_in_pkt_RME_0;
assign dccm_ext_in_pkt[0].RM = dccm_ext_in_pkt_RM_0[3:0];
assign dccm_ext_in_pkt[0].LS = dccm_ext_in_pkt_LS_0;
assign dccm_ext_in_pkt[0].DS = dccm_ext_in_pkt_DS_0;
assign dccm_ext_in_pkt[0].SD = dccm_ext_in_pkt_SD_0;
assign dccm_ext_in_pkt[0].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_0;
assign dccm_ext_in_pkt[0].BC1 = dccm_ext_in_pkt_BC1_0;
assign dccm_ext_in_pkt[0].BC2 = dccm_ext_in_pkt_BC2_0;
assign dccm_ext_in_pkt[1].TEST1 = dccm_ext_in_pkt_TEST1_1;
assign dccm_ext_in_pkt[1].RME = dccm_ext_in_pkt_RME_1;
assign dccm_ext_in_pkt[1].RM = dccm_ext_in_pkt_RM_1[3:0];
assign dccm_ext_in_pkt[1].LS = dccm_ext_in_pkt_LS_1;
assign dccm_ext_in_pkt[1].DS = dccm_ext_in_pkt_DS_1;
assign dccm_ext_in_pkt[1].SD = dccm_ext_in_pkt_SD_1;
assign dccm_ext_in_pkt[1].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_1;
assign dccm_ext_in_pkt[1].BC1 = dccm_ext_in_pkt_BC1_1;
assign dccm_ext_in_pkt[1].BC2 = dccm_ext_in_pkt_BC2_1;
assign dccm_ext_in_pkt[2].TEST1 = dccm_ext_in_pkt_TEST1_2;
assign dccm_ext_in_pkt[2].RME = dccm_ext_in_pkt_RME_2;
assign dccm_ext_in_pkt[2].RM = dccm_ext_in_pkt_RM_2[3:0];
assign dccm_ext_in_pkt[2].LS = dccm_ext_in_pkt_LS_2;
assign dccm_ext_in_pkt[2].DS = dccm_ext_in_pkt_DS_2;
assign dccm_ext_in_pkt[2].SD = dccm_ext_in_pkt_SD_2;
assign dccm_ext_in_pkt[2].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_2;
assign dccm_ext_in_pkt[2].BC1 = dccm_ext_in_pkt_BC1_2;
assign dccm_ext_in_pkt[2].BC2 = dccm_ext_in_pkt_BC2_2;
assign dccm_ext_in_pkt[3].TEST1 = dccm_ext_in_pkt_TEST1_3;
assign dccm_ext_in_pkt[3].RME = dccm_ext_in_pkt_RME_3;
assign dccm_ext_in_pkt[3].RM = dccm_ext_in_pkt_RM_3[3:0];
assign dccm_ext_in_pkt[3].LS = dccm_ext_in_pkt_LS_3;
assign dccm_ext_in_pkt[3].DS = dccm_ext_in_pkt_DS_3;
assign dccm_ext_in_pkt[3].SD = dccm_ext_in_pkt_SD_3;
assign dccm_ext_in_pkt[3].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_3;
assign dccm_ext_in_pkt[3].BC1 = dccm_ext_in_pkt_BC1_3;
assign dccm_ext_in_pkt[3].BC2 = dccm_ext_in_pkt_BC2_3;
assign iccm_ext_in_pkt[0].TEST1 = iccm_ext_in_pkt_TEST1_0;
assign iccm_ext_in_pkt[0].RME = iccm_ext_in_pkt_RME_0;
assign iccm_ext_in_pkt[0].RM = iccm_ext_in_pkt_RM_0[3:0];
assign iccm_ext_in_pkt[0].LS = iccm_ext_in_pkt_LS_0;
assign iccm_ext_in_pkt[0].DS = iccm_ext_in_pkt_DS_0;
assign iccm_ext_in_pkt[0].SD = iccm_ext_in_pkt_SD_0;
assign iccm_ext_in_pkt[0].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_0;
assign iccm_ext_in_pkt[0].BC1 = iccm_ext_in_pkt_BC1_0;
assign iccm_ext_in_pkt[0].BC2 = iccm_ext_in_pkt_BC2_0;
assign iccm_ext_in_pkt[1].TEST1 = iccm_ext_in_pkt_TEST1_1;
assign iccm_ext_in_pkt[1].RME = iccm_ext_in_pkt_RME_1;
assign iccm_ext_in_pkt[1].RM = iccm_ext_in_pkt_RM_1[3:0];
assign iccm_ext_in_pkt[1].LS = iccm_ext_in_pkt_LS_1;
assign iccm_ext_in_pkt[1].DS = iccm_ext_in_pkt_DS_1;
assign iccm_ext_in_pkt[1].SD = iccm_ext_in_pkt_SD_1;
assign iccm_ext_in_pkt[1].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_1;
assign iccm_ext_in_pkt[1].BC1 = iccm_ext_in_pkt_BC1_1;
assign iccm_ext_in_pkt[1].BC2 = iccm_ext_in_pkt_BC2_1;
assign iccm_ext_in_pkt[2].TEST1 = iccm_ext_in_pkt_TEST1_2;
assign iccm_ext_in_pkt[2].RME = iccm_ext_in_pkt_RME_2;
assign iccm_ext_in_pkt[2].RM = iccm_ext_in_pkt_RM_2[3:0];
assign iccm_ext_in_pkt[2].LS = iccm_ext_in_pkt_LS_2;
assign iccm_ext_in_pkt[2].DS = iccm_ext_in_pkt_DS_2;
assign iccm_ext_in_pkt[2].SD = iccm_ext_in_pkt_SD_2;
assign iccm_ext_in_pkt[2].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_2;
assign iccm_ext_in_pkt[2].BC1 = iccm_ext_in_pkt_BC1_2;
assign iccm_ext_in_pkt[2].BC2 = iccm_ext_in_pkt_BC2_2;
assign iccm_ext_in_pkt[3].TEST1 = iccm_ext_in_pkt_TEST1_3;
assign iccm_ext_in_pkt[3].RME = iccm_ext_in_pkt_RME_3;
assign iccm_ext_in_pkt[3].RM = iccm_ext_in_pkt_RM_3[3:0];
assign iccm_ext_in_pkt[3].LS = iccm_ext_in_pkt_LS_3;
assign iccm_ext_in_pkt[3].DS = iccm_ext_in_pkt_DS_3;
assign iccm_ext_in_pkt[3].SD = iccm_ext_in_pkt_SD_3;
assign iccm_ext_in_pkt[3].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_3;
assign iccm_ext_in_pkt[3].BC1 = iccm_ext_in_pkt_BC1_3;
assign iccm_ext_in_pkt[3].BC2 = iccm_ext_in_pkt_BC2_3;
assign ic_tag_ext_in_pkt[0].TEST1 = ic_tag_ext_in_pkt_TEST1_0;
assign ic_tag_ext_in_pkt[0].RME = ic_tag_ext_in_pkt_RME_0;
assign ic_tag_ext_in_pkt[0].RM = ic_tag_ext_in_pkt_RM_0[3:0];
assign ic_tag_ext_in_pkt[0].LS = ic_tag_ext_in_pkt_LS_0;
assign ic_tag_ext_in_pkt[0].DS = ic_tag_ext_in_pkt_DS_0;
assign ic_tag_ext_in_pkt[0].SD = ic_tag_ext_in_pkt_SD_0;
assign ic_tag_ext_in_pkt[0].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_0;
assign ic_tag_ext_in_pkt[0].BC1 = ic_tag_ext_in_pkt_BC1_0;
assign ic_tag_ext_in_pkt[0].BC2 = ic_tag_ext_in_pkt_BC2_0;
assign ic_tag_ext_in_pkt[1].TEST1 = ic_tag_ext_in_pkt_TEST1_1;
assign ic_tag_ext_in_pkt[1].RME = ic_tag_ext_in_pkt_RME_1;
assign ic_tag_ext_in_pkt[1].RM = ic_tag_ext_in_pkt_RM_1[3:0];
assign ic_tag_ext_in_pkt[1].LS = ic_tag_ext_in_pkt_LS_1;
assign ic_tag_ext_in_pkt[1].DS = ic_tag_ext_in_pkt_DS_1;
assign ic_tag_ext_in_pkt[1].SD = ic_tag_ext_in_pkt_SD_1;
assign ic_tag_ext_in_pkt[1].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_1;
assign ic_tag_ext_in_pkt[1].BC1 = ic_tag_ext_in_pkt_BC1_1;
assign ic_tag_ext_in_pkt[1].BC2 = ic_tag_ext_in_pkt_BC2_1;
// PKT connection
assign ic_data_ext_in_pkt[0][0].TEST1 = ic_data_ext_in_pkt_0_TEST1_0;
assign ic_data_ext_in_pkt[0][0].RME = ic_data_ext_in_pkt_0_RME_0;
assign ic_data_ext_in_pkt[0][0].RM = ic_data_ext_in_pkt_0_RM_0[3:0];
assign ic_data_ext_in_pkt[0][0].LS = ic_data_ext_in_pkt_0_LS_0;
assign ic_data_ext_in_pkt[0][0].DS = ic_data_ext_in_pkt_0_DS_0;
assign ic_data_ext_in_pkt[0][0].SD = ic_data_ext_in_pkt_0_SD_0;
assign ic_data_ext_in_pkt[0][0].TEST_RNM = ic_data_ext_in_pkt_0_TEST_RNM_0;
assign ic_data_ext_in_pkt[0][0].BC1 = ic_data_ext_in_pkt_0_BC1_0;
assign ic_data_ext_in_pkt[0][0].BC2 = ic_data_ext_in_pkt_0_BC2_0;
assign ic_data_ext_in_pkt[0][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[0][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[0][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[0][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[0][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[0][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[0][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[0][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[0][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
assign ic_data_ext_in_pkt[1][0].TEST1 = ic_data_ext_in_pkt_1_TEST1_0;
assign ic_data_ext_in_pkt[1][0].RME = ic_data_ext_in_pkt_1_RME_0;
assign ic_data_ext_in_pkt[1][0].RM = ic_data_ext_in_pkt_1_RM_0[3:0];
assign ic_data_ext_in_pkt[1][0].LS = ic_data_ext_in_pkt_1_LS_0;
assign ic_data_ext_in_pkt[1][0].DS = ic_data_ext_in_pkt_1_DS_0;
assign ic_data_ext_in_pkt[1][0].SD = ic_data_ext_in_pkt_1_SD_0;
assign ic_data_ext_in_pkt[1][0].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_0;
assign ic_data_ext_in_pkt[1][0].BC1 = ic_data_ext_in_pkt_1_BC1_0;
assign ic_data_ext_in_pkt[1][0].BC2 = ic_data_ext_in_pkt_1_BC2_0;
assign ic_data_ext_in_pkt[1][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[1][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[1][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[1][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[1][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[1][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[1][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[1][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[1][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS(ICACHE_NUM_BYPASS),
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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