diff --git a/exu_div_new_3bit_fullshortq.fir b/exu_div_new_3bit_fullshortq.fir index c1976845..5d822a01 100644 --- a/exu_div_new_3bit_fullshortq.fir +++ b/exu_div_new_3bit_fullshortq.fir @@ -9,70 +9,70 @@ circuit exu_div_new_3bit_fullshortq : cls_zeros <= UInt<5>("h00") wire cls_ones : UInt<5> cls_ones <= UInt<5>("h00") - node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 775:54] - node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 775:54] - node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 775:54] - node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 775:54] - node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 775:54] - node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 775:54] - node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 775:54] - node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 775:54] - node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 775:54] - node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 775:54] - node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 775:54] - node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 775:54] - node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 775:54] - node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 775:54] - node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 775:54] - node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 775:54] - node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 775:54] - node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 775:54] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 775:54] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 775:54] - node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 775:54] - node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 775:54] - node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 775:54] - node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 775:54] - node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 775:54] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 775:54] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 775:54] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 775:54] - node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 775:54] - node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 775:54] - node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 775:54] - node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 775:54] - node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] + node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 935:54] + node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 935:54] + node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 935:54] + node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 935:54] + node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 935:54] + node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 935:54] + node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 935:54] + node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 935:54] + node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 935:54] + node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 935:54] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 935:54] + node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 935:54] + node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 935:54] + node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 935:54] + node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 935:54] + node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 935:54] + node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 935:54] + node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 935:54] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 935:54] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 935:54] + node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 935:54] + node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 935:54] + node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 935:54] + node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 935:54] + node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 935:54] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 935:54] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 935:54] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 935:54] + node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 935:54] + node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 935:54] + node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 935:54] + node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 935:54] + node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -138,167 +138,167 @@ circuit exu_div_new_3bit_fullshortq : node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72] wire _T_127 : UInt<5> @[Mux.scala 27:72] _T_127 <= _T_126 @[Mux.scala 27:72] - cls_zeros <= _T_127 @[exu_div_ctl.scala 775:13] - node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 777:18] - node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 777:25] - when _T_129 : @[exu_div_ctl.scala 777:44] - cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 777:55] - skip @[exu_div_ctl.scala 777:44] - else : @[exu_div_ctl.scala 778:15] - node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 778:66] + cls_zeros <= _T_127 @[exu_div_ctl.scala 935:13] + node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 937:18] + node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 937:25] + when _T_129 : @[exu_div_ctl.scala 937:44] + cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 937:55] + skip @[exu_div_ctl.scala 937:44] + else : @[exu_div_ctl.scala 938:15] + node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 938:66] node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 778:76] - node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 778:66] + node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 938:76] + node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 938:66] node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 778:76] - node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 778:66] + node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 938:76] + node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 938:66] node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 778:76] - node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 778:66] + node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 938:76] + node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 938:66] node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 778:76] - node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 778:66] + node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 938:76] + node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 938:66] node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 778:76] - node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 778:66] + node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 938:76] + node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 938:66] node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 778:76] - node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 778:66] + node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 938:76] + node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 938:66] node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 778:76] - node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 778:66] + node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 938:76] + node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 938:66] node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 778:76] - node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 778:66] + node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 938:76] + node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 938:66] node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 778:76] - node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 778:66] + node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 938:76] + node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 938:66] node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 778:76] - node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 778:66] + node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 938:76] + node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 938:66] node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 778:76] - node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 778:66] + node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 938:76] + node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 938:66] node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 778:76] - node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 778:66] + node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 938:76] + node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 938:66] node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 778:76] - node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 778:66] + node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 938:76] + node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 938:66] node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 778:76] - node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 778:66] + node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 938:76] + node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 938:66] node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 778:76] - node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 778:66] + node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 938:76] + node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 938:66] node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 778:76] - node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 778:66] + node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 938:76] + node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 938:66] node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 778:76] - node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 778:66] + node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 938:76] + node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 938:66] node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12] node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 778:76] - node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 778:66] + node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 938:76] + node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 938:66] node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 778:76] - node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 778:66] + node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 938:76] + node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 938:66] node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 778:76] - node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 778:66] + node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 938:76] + node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 938:66] node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12] node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 778:76] - node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 778:66] + node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 938:76] + node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 938:66] node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12] node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 778:76] - node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 778:66] + node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 938:76] + node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 938:66] node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12] node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 778:76] - node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 778:66] + node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 938:76] + node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 938:66] node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 778:76] - node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 778:66] + node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 938:76] + node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 938:66] node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12] node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 778:76] - node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 778:66] + node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 938:76] + node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 938:66] node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 778:76] - node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 778:66] + node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 938:76] + node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 938:66] node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12] node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 778:76] - node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 778:66] + node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 938:76] + node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 938:66] node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 778:76] - node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 778:66] + node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 938:76] + node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 938:66] node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 778:76] - node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 778:66] + node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 938:76] + node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 938:66] node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 778:76] - node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 778:66] + node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 938:76] + node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 938:66] node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 778:76] - node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 778:102] + node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 938:76] + node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 938:102] node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -362,11 +362,11 @@ circuit exu_div_new_3bit_fullshortq : node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72] wire _T_345 : UInt<5> @[Mux.scala 27:72] _T_345 <= _T_344 @[Mux.scala 27:72] - cls_ones <= _T_345 @[exu_div_ctl.scala 778:25] - skip @[exu_div_ctl.scala 778:15] - node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 779:27] - node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 779:16] - io.cls <= _T_347 @[exu_div_ctl.scala 779:10] + cls_ones <= _T_345 @[exu_div_ctl.scala 938:25] + skip @[exu_div_ctl.scala 938:15] + node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 939:27] + node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 939:16] + io.cls <= _T_347 @[exu_div_ctl.scala 939:10] module exu_div_cls_1 : input clock : Clock @@ -377,70 +377,70 @@ circuit exu_div_new_3bit_fullshortq : cls_zeros <= UInt<5>("h00") wire cls_ones : UInt<5> cls_ones <= UInt<5>("h00") - node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 775:54] - node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 775:54] - node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 775:54] - node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 775:54] - node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 775:54] - node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 775:54] - node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 775:54] - node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 775:54] - node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 775:54] - node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 775:54] - node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 775:54] - node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 775:54] - node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 775:54] - node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 775:54] - node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 775:54] - node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 775:54] - node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 775:54] - node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 775:54] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 775:54] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 775:54] - node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 775:54] - node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 775:54] - node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 775:54] - node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 775:54] - node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 775:54] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 775:54] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 775:54] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 775:54] - node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 775:54] - node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 775:54] - node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 775:54] - node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] - node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 775:54] - node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 775:63] + node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 935:54] + node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 935:54] + node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 935:54] + node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 935:54] + node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 935:54] + node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 935:54] + node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 935:54] + node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 935:54] + node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 935:54] + node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 935:54] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 935:54] + node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 935:54] + node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 935:54] + node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 935:54] + node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 935:54] + node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 935:54] + node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 935:54] + node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 935:54] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 935:54] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 935:54] + node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 935:54] + node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 935:54] + node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 935:54] + node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 935:54] + node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 935:54] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 935:54] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 935:54] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 935:54] + node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 935:54] + node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 935:54] + node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 935:54] + node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] + node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 935:54] + node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 935:63] node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -506,167 +506,167 @@ circuit exu_div_new_3bit_fullshortq : node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72] wire _T_127 : UInt<5> @[Mux.scala 27:72] _T_127 <= _T_126 @[Mux.scala 27:72] - cls_zeros <= _T_127 @[exu_div_ctl.scala 775:13] - node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 777:18] - node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 777:25] - when _T_129 : @[exu_div_ctl.scala 777:44] - cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 777:55] - skip @[exu_div_ctl.scala 777:44] - else : @[exu_div_ctl.scala 778:15] - node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 778:66] + cls_zeros <= _T_127 @[exu_div_ctl.scala 935:13] + node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 937:18] + node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 937:25] + when _T_129 : @[exu_div_ctl.scala 937:44] + cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 937:55] + skip @[exu_div_ctl.scala 937:44] + else : @[exu_div_ctl.scala 938:15] + node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 938:66] node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 778:76] - node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 778:66] + node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 938:76] + node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 938:66] node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 778:76] - node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 778:66] + node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 938:76] + node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 938:66] node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 778:76] - node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 778:66] + node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 938:76] + node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 938:66] node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 778:76] - node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 778:66] + node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 938:76] + node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 938:66] node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 778:76] - node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 778:66] + node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 938:76] + node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 938:66] node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 778:76] - node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 778:66] + node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 938:76] + node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 938:66] node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 778:76] - node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 778:66] + node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 938:76] + node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 938:66] node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 778:76] - node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 778:66] + node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 938:76] + node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 938:66] node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 778:76] - node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 778:66] + node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 938:76] + node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 938:66] node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 778:76] - node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 778:66] + node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 938:76] + node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 938:66] node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 778:76] - node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 778:66] + node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 938:76] + node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 938:66] node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 778:76] - node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 778:66] + node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 938:76] + node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 938:66] node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 778:76] - node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 778:66] + node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 938:76] + node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 938:66] node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 778:76] - node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 778:66] + node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 938:76] + node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 938:66] node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 778:76] - node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 778:66] + node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 938:76] + node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 938:66] node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 778:76] - node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 778:66] + node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 938:76] + node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 938:66] node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 778:76] - node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 778:66] + node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 938:76] + node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 938:66] node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12] node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 778:76] - node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 778:66] + node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 938:76] + node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 938:66] node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 778:76] - node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 778:66] + node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 938:76] + node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 938:66] node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 778:76] - node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 778:66] + node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 938:76] + node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 938:66] node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12] node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 778:76] - node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 778:66] + node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 938:76] + node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 938:66] node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12] node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 778:76] - node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 778:66] + node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 938:76] + node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 938:66] node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12] node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 778:76] - node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 778:66] + node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 938:76] + node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 938:66] node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 778:76] - node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 778:66] + node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 938:76] + node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 938:66] node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12] node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 778:76] - node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 778:66] + node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 938:76] + node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 938:66] node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 778:76] - node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 778:66] + node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 938:76] + node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 938:66] node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12] node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 778:76] - node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 778:66] + node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 938:76] + node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 938:66] node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 778:76] - node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 778:66] + node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 938:76] + node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 938:66] node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 778:76] - node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 778:66] + node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 938:76] + node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 938:66] node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 778:76] - node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 778:102] - node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 778:66] + node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 938:76] + node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 938:102] + node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 938:66] node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 778:76] - node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 778:102] + node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 938:76] + node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 938:102] node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -730,11 +730,11 @@ circuit exu_div_new_3bit_fullshortq : node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72] wire _T_345 : UInt<5> @[Mux.scala 27:72] _T_345 <= _T_344 @[Mux.scala 27:72] - cls_ones <= _T_345 @[exu_div_ctl.scala 778:25] - skip @[exu_div_ctl.scala 778:15] - node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 779:27] - node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 779:16] - io.cls <= _T_347 @[exu_div_ctl.scala 779:10] + cls_ones <= _T_345 @[exu_div_ctl.scala 938:25] + skip @[exu_div_ctl.scala 938:15] + node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 939:27] + node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 939:16] + io.cls <= _T_347 @[exu_div_ctl.scala 939:10] extmodule gated_latch : output Q : Clock @@ -1151,165 +1151,165 @@ circuit exu_div_new_3bit_fullshortq : node _T_84 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 628:40] node _T_85 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 628:61] node r_sign_sel = and(_T_84, _T_85) @[exu_div_ctl.scala 628:59] - node _T_86 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 629:61] - node _T_87 = and(running_state, _T_86) @[exu_div_ctl.scala 629:45] - node _T_88 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 629:72] - node r_restore_sel = and(_T_87, _T_88) @[exu_div_ctl.scala 629:70] - node _T_89 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 630:61] - node _T_90 = and(running_state, _T_89) @[exu_div_ctl.scala 630:45] - node _T_91 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:72] - node r_adder1_sel = and(_T_90, _T_91) @[exu_div_ctl.scala 630:70] - node _T_92 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 631:61] - node _T_93 = and(running_state, _T_92) @[exu_div_ctl.scala 631:45] - node _T_94 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 631:72] - node r_adder2_sel = and(_T_93, _T_94) @[exu_div_ctl.scala 631:70] - node _T_95 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 632:61] - node _T_96 = and(running_state, _T_95) @[exu_div_ctl.scala 632:45] - node _T_97 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 632:72] - node r_adder3_sel = and(_T_96, _T_97) @[exu_div_ctl.scala 632:70] - node _T_98 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 633:61] - node _T_99 = and(running_state, _T_98) @[exu_div_ctl.scala 633:45] - node _T_100 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 633:72] - node r_adder4_sel = and(_T_99, _T_100) @[exu_div_ctl.scala 633:70] - node _T_101 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 634:61] - node _T_102 = and(running_state, _T_101) @[exu_div_ctl.scala 634:45] - node _T_103 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 634:72] - node r_adder5_sel = and(_T_102, _T_103) @[exu_div_ctl.scala 634:70] - node _T_104 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 635:61] - node _T_105 = and(running_state, _T_104) @[exu_div_ctl.scala 635:45] - node _T_106 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 635:72] - node r_adder6_sel = and(_T_105, _T_106) @[exu_div_ctl.scala 635:70] - node _T_107 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 636:61] - node _T_108 = and(running_state, _T_107) @[exu_div_ctl.scala 636:45] - node _T_109 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 636:72] - node r_adder7_sel = and(_T_108, _T_109) @[exu_div_ctl.scala 636:70] - node _T_110 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 638:29] - node _T_111 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 638:40] + node _T_86 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 630:70] + node _T_87 = and(running_state, _T_86) @[exu_div_ctl.scala 630:54] + node _T_88 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_0 = and(_T_87, _T_88) @[exu_div_ctl.scala 630:84] + node _T_89 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 630:70] + node _T_90 = and(running_state, _T_89) @[exu_div_ctl.scala 630:54] + node _T_91 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_1 = and(_T_90, _T_91) @[exu_div_ctl.scala 630:84] + node _T_92 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 630:70] + node _T_93 = and(running_state, _T_92) @[exu_div_ctl.scala 630:54] + node _T_94 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_2 = and(_T_93, _T_94) @[exu_div_ctl.scala 630:84] + node _T_95 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 630:70] + node _T_96 = and(running_state, _T_95) @[exu_div_ctl.scala 630:54] + node _T_97 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_3 = and(_T_96, _T_97) @[exu_div_ctl.scala 630:84] + node _T_98 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 630:70] + node _T_99 = and(running_state, _T_98) @[exu_div_ctl.scala 630:54] + node _T_100 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_4 = and(_T_99, _T_100) @[exu_div_ctl.scala 630:84] + node _T_101 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 630:70] + node _T_102 = and(running_state, _T_101) @[exu_div_ctl.scala 630:54] + node _T_103 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_5 = and(_T_102, _T_103) @[exu_div_ctl.scala 630:84] + node _T_104 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 630:70] + node _T_105 = and(running_state, _T_104) @[exu_div_ctl.scala 630:54] + node _T_106 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_6 = and(_T_105, _T_106) @[exu_div_ctl.scala 630:84] + node _T_107 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 630:70] + node _T_108 = and(running_state, _T_107) @[exu_div_ctl.scala 630:54] + node _T_109 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:86] + node r_adder_sel_7 = and(_T_108, _T_109) @[exu_div_ctl.scala 630:84] + node _T_110 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 641:29] + node _T_111 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 641:40] node _T_112 = cat(_T_110, _T_111) @[Cat.scala 29:58] - node _T_113 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 638:55] - node _T_114 = add(_T_112, _T_113) @[exu_div_ctl.scala 638:49] - node adder1_out = tail(_T_114, 1) @[exu_div_ctl.scala 638:49] - node _T_115 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 639:29] - node _T_116 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 639:40] + node _T_113 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 641:55] + node _T_114 = add(_T_112, _T_113) @[exu_div_ctl.scala 641:49] + node adder1_out = tail(_T_114, 1) @[exu_div_ctl.scala 641:49] + node _T_115 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 642:29] + node _T_116 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 642:40] node _T_117 = cat(_T_115, _T_116) @[Cat.scala 29:58] - node _T_118 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 639:59] + node _T_118 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 642:59] node _T_119 = cat(_T_118, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_120 = add(_T_117, _T_119) @[exu_div_ctl.scala 639:49] - node adder2_out = tail(_T_120, 1) @[exu_div_ctl.scala 639:49] - node _T_121 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 640:29] - node _T_122 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 640:40] + node _T_120 = add(_T_117, _T_119) @[exu_div_ctl.scala 642:49] + node adder2_out = tail(_T_120, 1) @[exu_div_ctl.scala 642:49] + node _T_121 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 643:29] + node _T_122 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 643:40] node _T_123 = cat(_T_121, _T_122) @[Cat.scala 29:58] - node _T_124 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 640:59] + node _T_124 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 643:59] node _T_125 = cat(_T_124, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_126 = add(_T_123, _T_125) @[exu_div_ctl.scala 640:49] - node _T_127 = tail(_T_126, 1) @[exu_div_ctl.scala 640:49] - node _T_128 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 640:77] - node _T_129 = add(_T_127, _T_128) @[exu_div_ctl.scala 640:71] - node adder3_out = tail(_T_129, 1) @[exu_div_ctl.scala 640:71] - node _T_130 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 641:29] - node _T_131 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 641:38] - node _T_132 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 641:49] + node _T_126 = add(_T_123, _T_125) @[exu_div_ctl.scala 643:49] + node _T_127 = tail(_T_126, 1) @[exu_div_ctl.scala 643:49] + node _T_128 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 643:77] + node _T_129 = add(_T_127, _T_128) @[exu_div_ctl.scala 643:71] + node adder3_out = tail(_T_129, 1) @[exu_div_ctl.scala 643:71] + node _T_130 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 644:29] + node _T_131 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 644:38] + node _T_132 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 644:49] node _T_133 = cat(_T_130, _T_131) @[Cat.scala 29:58] node _T_134 = cat(_T_133, _T_132) @[Cat.scala 29:58] - node _T_135 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 641:68] + node _T_135 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 644:68] node _T_136 = cat(_T_135, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_137 = add(_T_134, _T_136) @[exu_div_ctl.scala 641:58] - node adder4_out = tail(_T_137, 1) @[exu_div_ctl.scala 641:58] - node _T_138 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 642:29] - node _T_139 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 642:38] - node _T_140 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 642:49] + node _T_137 = add(_T_134, _T_136) @[exu_div_ctl.scala 644:58] + node adder4_out = tail(_T_137, 1) @[exu_div_ctl.scala 644:58] + node _T_138 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 645:29] + node _T_139 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 645:38] + node _T_140 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 645:49] node _T_141 = cat(_T_138, _T_139) @[Cat.scala 29:58] node _T_142 = cat(_T_141, _T_140) @[Cat.scala 29:58] - node _T_143 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 642:68] + node _T_143 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 645:68] node _T_144 = cat(_T_143, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_145 = add(_T_142, _T_144) @[exu_div_ctl.scala 642:58] - node _T_146 = tail(_T_145, 1) @[exu_div_ctl.scala 642:58] - node _T_147 = add(_T_146, b_ff) @[exu_div_ctl.scala 642:85] - node adder5_out = tail(_T_147, 1) @[exu_div_ctl.scala 642:85] - node _T_148 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 643:29] - node _T_149 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 643:38] - node _T_150 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 643:49] + node _T_145 = add(_T_142, _T_144) @[exu_div_ctl.scala 645:58] + node _T_146 = tail(_T_145, 1) @[exu_div_ctl.scala 645:58] + node _T_147 = add(_T_146, b_ff) @[exu_div_ctl.scala 645:85] + node adder5_out = tail(_T_147, 1) @[exu_div_ctl.scala 645:85] + node _T_148 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 646:29] + node _T_149 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 646:38] + node _T_150 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 646:49] node _T_151 = cat(_T_148, _T_149) @[Cat.scala 29:58] node _T_152 = cat(_T_151, _T_150) @[Cat.scala 29:58] - node _T_153 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 643:68] + node _T_153 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 646:68] node _T_154 = cat(_T_153, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_155 = add(_T_152, _T_154) @[exu_div_ctl.scala 643:58] - node _T_156 = tail(_T_155, 1) @[exu_div_ctl.scala 643:58] - node _T_157 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 643:95] + node _T_155 = add(_T_152, _T_154) @[exu_div_ctl.scala 646:58] + node _T_156 = tail(_T_155, 1) @[exu_div_ctl.scala 646:58] + node _T_157 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 646:95] node _T_158 = cat(_T_157, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_159 = add(_T_156, _T_158) @[exu_div_ctl.scala 643:85] - node adder6_out = tail(_T_159, 1) @[exu_div_ctl.scala 643:85] - node _T_160 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 644:29] - node _T_161 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 644:38] - node _T_162 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 644:49] + node _T_159 = add(_T_156, _T_158) @[exu_div_ctl.scala 646:85] + node adder6_out = tail(_T_159, 1) @[exu_div_ctl.scala 646:85] + node _T_160 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 647:29] + node _T_161 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 647:38] + node _T_162 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 647:49] node _T_163 = cat(_T_160, _T_161) @[Cat.scala 29:58] node _T_164 = cat(_T_163, _T_162) @[Cat.scala 29:58] - node _T_165 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 644:68] + node _T_165 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 647:68] node _T_166 = cat(_T_165, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_167 = add(_T_164, _T_166) @[exu_div_ctl.scala 644:58] - node _T_168 = tail(_T_167, 1) @[exu_div_ctl.scala 644:58] - node _T_169 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 644:95] + node _T_167 = add(_T_164, _T_166) @[exu_div_ctl.scala 647:58] + node _T_168 = tail(_T_167, 1) @[exu_div_ctl.scala 647:58] + node _T_169 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 647:95] node _T_170 = cat(_T_169, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_171 = add(_T_168, _T_170) @[exu_div_ctl.scala 644:85] - node _T_172 = tail(_T_171, 1) @[exu_div_ctl.scala 644:85] - node _T_173 = add(_T_172, b_ff) @[exu_div_ctl.scala 644:107] - node adder7_out = tail(_T_173, 1) @[exu_div_ctl.scala 644:107] - node _T_174 = bits(adder7_out, 36, 36) @[exu_div_ctl.scala 645:35] - node _T_175 = eq(_T_174, UInt<1>("h00")) @[exu_div_ctl.scala 645:24] - node _T_176 = xor(_T_175, dividend_sign_ff) @[exu_div_ctl.scala 645:40] - node _T_177 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 645:68] - node _T_178 = eq(_T_177, UInt<1>("h00")) @[exu_div_ctl.scala 645:75] - node _T_179 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 645:98] - node _T_180 = and(_T_178, _T_179) @[exu_div_ctl.scala 645:84] - node _T_181 = or(_T_176, _T_180) @[exu_div_ctl.scala 645:60] - node _T_182 = bits(adder6_out, 36, 36) @[exu_div_ctl.scala 646:34] - node _T_183 = eq(_T_182, UInt<1>("h00")) @[exu_div_ctl.scala 646:23] - node _T_184 = xor(_T_183, dividend_sign_ff) @[exu_div_ctl.scala 646:39] - node _T_185 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 646:67] - node _T_186 = eq(_T_185, UInt<1>("h00")) @[exu_div_ctl.scala 646:74] - node _T_187 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 646:97] - node _T_188 = and(_T_186, _T_187) @[exu_div_ctl.scala 646:83] - node _T_189 = or(_T_184, _T_188) @[exu_div_ctl.scala 646:59] - node _T_190 = bits(adder5_out, 36, 36) @[exu_div_ctl.scala 647:34] - node _T_191 = eq(_T_190, UInt<1>("h00")) @[exu_div_ctl.scala 647:23] - node _T_192 = xor(_T_191, dividend_sign_ff) @[exu_div_ctl.scala 647:39] - node _T_193 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 647:67] - node _T_194 = eq(_T_193, UInt<1>("h00")) @[exu_div_ctl.scala 647:74] - node _T_195 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 647:97] - node _T_196 = and(_T_194, _T_195) @[exu_div_ctl.scala 647:83] - node _T_197 = or(_T_192, _T_196) @[exu_div_ctl.scala 647:59] - node _T_198 = bits(adder4_out, 36, 36) @[exu_div_ctl.scala 648:34] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[exu_div_ctl.scala 648:23] - node _T_200 = xor(_T_199, dividend_sign_ff) @[exu_div_ctl.scala 648:39] - node _T_201 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 648:67] - node _T_202 = eq(_T_201, UInt<1>("h00")) @[exu_div_ctl.scala 648:74] - node _T_203 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 648:97] - node _T_204 = and(_T_202, _T_203) @[exu_div_ctl.scala 648:83] - node _T_205 = or(_T_200, _T_204) @[exu_div_ctl.scala 648:59] - node _T_206 = bits(adder3_out, 35, 35) @[exu_div_ctl.scala 649:34] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[exu_div_ctl.scala 649:23] - node _T_208 = xor(_T_207, dividend_sign_ff) @[exu_div_ctl.scala 649:39] - node _T_209 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 649:67] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[exu_div_ctl.scala 649:74] - node _T_211 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 649:97] - node _T_212 = and(_T_210, _T_211) @[exu_div_ctl.scala 649:83] - node _T_213 = or(_T_208, _T_212) @[exu_div_ctl.scala 649:59] - node _T_214 = bits(adder2_out, 34, 34) @[exu_div_ctl.scala 650:34] - node _T_215 = eq(_T_214, UInt<1>("h00")) @[exu_div_ctl.scala 650:23] - node _T_216 = xor(_T_215, dividend_sign_ff) @[exu_div_ctl.scala 650:39] - node _T_217 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 650:67] - node _T_218 = eq(_T_217, UInt<1>("h00")) @[exu_div_ctl.scala 650:74] - node _T_219 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 650:97] - node _T_220 = and(_T_218, _T_219) @[exu_div_ctl.scala 650:83] - node _T_221 = or(_T_216, _T_220) @[exu_div_ctl.scala 650:59] - node _T_222 = bits(adder1_out, 33, 33) @[exu_div_ctl.scala 651:34] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[exu_div_ctl.scala 651:23] - node _T_224 = xor(_T_223, dividend_sign_ff) @[exu_div_ctl.scala 651:39] - node _T_225 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 651:67] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[exu_div_ctl.scala 651:74] - node _T_227 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 651:97] - node _T_228 = and(_T_226, _T_227) @[exu_div_ctl.scala 651:83] - node _T_229 = or(_T_224, _T_228) @[exu_div_ctl.scala 651:59] + node _T_171 = add(_T_168, _T_170) @[exu_div_ctl.scala 647:85] + node _T_172 = tail(_T_171, 1) @[exu_div_ctl.scala 647:85] + node _T_173 = add(_T_172, b_ff) @[exu_div_ctl.scala 647:107] + node adder7_out = tail(_T_173, 1) @[exu_div_ctl.scala 647:107] + node _T_174 = bits(adder7_out, 36, 36) @[exu_div_ctl.scala 648:35] + node _T_175 = eq(_T_174, UInt<1>("h00")) @[exu_div_ctl.scala 648:24] + node _T_176 = xor(_T_175, dividend_sign_ff) @[exu_div_ctl.scala 648:40] + node _T_177 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 648:68] + node _T_178 = eq(_T_177, UInt<1>("h00")) @[exu_div_ctl.scala 648:75] + node _T_179 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 648:98] + node _T_180 = and(_T_178, _T_179) @[exu_div_ctl.scala 648:84] + node _T_181 = or(_T_176, _T_180) @[exu_div_ctl.scala 648:60] + node _T_182 = bits(adder6_out, 36, 36) @[exu_div_ctl.scala 649:34] + node _T_183 = eq(_T_182, UInt<1>("h00")) @[exu_div_ctl.scala 649:23] + node _T_184 = xor(_T_183, dividend_sign_ff) @[exu_div_ctl.scala 649:39] + node _T_185 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 649:67] + node _T_186 = eq(_T_185, UInt<1>("h00")) @[exu_div_ctl.scala 649:74] + node _T_187 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 649:97] + node _T_188 = and(_T_186, _T_187) @[exu_div_ctl.scala 649:83] + node _T_189 = or(_T_184, _T_188) @[exu_div_ctl.scala 649:59] + node _T_190 = bits(adder5_out, 36, 36) @[exu_div_ctl.scala 650:34] + node _T_191 = eq(_T_190, UInt<1>("h00")) @[exu_div_ctl.scala 650:23] + node _T_192 = xor(_T_191, dividend_sign_ff) @[exu_div_ctl.scala 650:39] + node _T_193 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 650:67] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[exu_div_ctl.scala 650:74] + node _T_195 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 650:97] + node _T_196 = and(_T_194, _T_195) @[exu_div_ctl.scala 650:83] + node _T_197 = or(_T_192, _T_196) @[exu_div_ctl.scala 650:59] + node _T_198 = bits(adder4_out, 36, 36) @[exu_div_ctl.scala 651:34] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[exu_div_ctl.scala 651:23] + node _T_200 = xor(_T_199, dividend_sign_ff) @[exu_div_ctl.scala 651:39] + node _T_201 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 651:67] + node _T_202 = eq(_T_201, UInt<1>("h00")) @[exu_div_ctl.scala 651:74] + node _T_203 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 651:97] + node _T_204 = and(_T_202, _T_203) @[exu_div_ctl.scala 651:83] + node _T_205 = or(_T_200, _T_204) @[exu_div_ctl.scala 651:59] + node _T_206 = bits(adder3_out, 35, 35) @[exu_div_ctl.scala 652:34] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[exu_div_ctl.scala 652:23] + node _T_208 = xor(_T_207, dividend_sign_ff) @[exu_div_ctl.scala 652:39] + node _T_209 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 652:67] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[exu_div_ctl.scala 652:74] + node _T_211 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 652:97] + node _T_212 = and(_T_210, _T_211) @[exu_div_ctl.scala 652:83] + node _T_213 = or(_T_208, _T_212) @[exu_div_ctl.scala 652:59] + node _T_214 = bits(adder2_out, 34, 34) @[exu_div_ctl.scala 653:34] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[exu_div_ctl.scala 653:23] + node _T_216 = xor(_T_215, dividend_sign_ff) @[exu_div_ctl.scala 653:39] + node _T_217 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 653:67] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[exu_div_ctl.scala 653:74] + node _T_219 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 653:97] + node _T_220 = and(_T_218, _T_219) @[exu_div_ctl.scala 653:83] + node _T_221 = or(_T_216, _T_220) @[exu_div_ctl.scala 653:59] + node _T_222 = bits(adder1_out, 33, 33) @[exu_div_ctl.scala 654:34] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[exu_div_ctl.scala 654:23] + node _T_224 = xor(_T_223, dividend_sign_ff) @[exu_div_ctl.scala 654:39] + node _T_225 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 654:67] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[exu_div_ctl.scala 654:74] + node _T_227 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 654:97] + node _T_228 = and(_T_226, _T_227) @[exu_div_ctl.scala 654:83] + node _T_229 = or(_T_224, _T_228) @[exu_div_ctl.scala 654:59] node _T_230 = cat(_T_229, UInt<1>("h00")) @[Cat.scala 29:58] node _T_231 = cat(_T_213, _T_221) @[Cat.scala 29:58] node _T_232 = cat(_T_231, _T_230) @[Cat.scala 29:58] @@ -1317,47 +1317,47 @@ circuit exu_div_new_3bit_fullshortq : node _T_234 = cat(_T_181, _T_189) @[Cat.scala 29:58] node _T_235 = cat(_T_234, _T_233) @[Cat.scala 29:58] node _T_236 = cat(_T_235, _T_232) @[Cat.scala 29:58] - quotient_raw <= _T_236 @[exu_div_ctl.scala 645:16] - node _T_237 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 652:39] - node _T_238 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 652:58] - node _T_239 = or(_T_237, _T_238) @[exu_div_ctl.scala 652:43] - node _T_240 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 652:76] - node _T_241 = or(_T_239, _T_240) @[exu_div_ctl.scala 652:62] - node _T_242 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 652:95] - node _T_243 = or(_T_241, _T_242) @[exu_div_ctl.scala 652:80] - node _T_244 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 653:38] - node _T_245 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 653:57] - node _T_246 = or(_T_244, _T_245) @[exu_div_ctl.scala 653:42] - node _T_247 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 653:76] - node _T_248 = eq(_T_247, UInt<1>("h00")) @[exu_div_ctl.scala 653:63] - node _T_249 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 653:94] - node _T_250 = and(_T_248, _T_249) @[exu_div_ctl.scala 653:80] - node _T_251 = or(_T_246, _T_250) @[exu_div_ctl.scala 653:61] - node _T_252 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 653:114] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[exu_div_ctl.scala 653:101] - node _T_254 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 653:132] - node _T_255 = and(_T_253, _T_254) @[exu_div_ctl.scala 653:118] - node _T_256 = or(_T_251, _T_255) @[exu_div_ctl.scala 653:99] - node _T_257 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 654:38] - node _T_258 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 654:59] - node _T_259 = eq(_T_258, UInt<1>("h00")) @[exu_div_ctl.scala 654:46] - node _T_260 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 654:77] - node _T_261 = and(_T_259, _T_260) @[exu_div_ctl.scala 654:63] - node _T_262 = or(_T_257, _T_261) @[exu_div_ctl.scala 654:42] - node _T_263 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 654:98] - node _T_264 = eq(_T_263, UInt<1>("h00")) @[exu_div_ctl.scala 654:85] - node _T_265 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 654:116] - node _T_266 = and(_T_264, _T_265) @[exu_div_ctl.scala 654:102] - node _T_267 = or(_T_262, _T_266) @[exu_div_ctl.scala 654:82] - node _T_268 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 654:136] - node _T_269 = eq(_T_268, UInt<1>("h00")) @[exu_div_ctl.scala 654:123] - node _T_270 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 654:154] - node _T_271 = and(_T_269, _T_270) @[exu_div_ctl.scala 654:140] - node _T_272 = or(_T_267, _T_271) @[exu_div_ctl.scala 654:121] + quotient_raw <= _T_236 @[exu_div_ctl.scala 648:16] + node _T_237 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 655:39] + node _T_238 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 655:58] + node _T_239 = or(_T_237, _T_238) @[exu_div_ctl.scala 655:43] + node _T_240 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 655:76] + node _T_241 = or(_T_239, _T_240) @[exu_div_ctl.scala 655:62] + node _T_242 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 655:95] + node _T_243 = or(_T_241, _T_242) @[exu_div_ctl.scala 655:80] + node _T_244 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 656:38] + node _T_245 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 656:57] + node _T_246 = or(_T_244, _T_245) @[exu_div_ctl.scala 656:42] + node _T_247 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 656:76] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[exu_div_ctl.scala 656:63] + node _T_249 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 656:94] + node _T_250 = and(_T_248, _T_249) @[exu_div_ctl.scala 656:80] + node _T_251 = or(_T_246, _T_250) @[exu_div_ctl.scala 656:61] + node _T_252 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 656:114] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[exu_div_ctl.scala 656:101] + node _T_254 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 656:132] + node _T_255 = and(_T_253, _T_254) @[exu_div_ctl.scala 656:118] + node _T_256 = or(_T_251, _T_255) @[exu_div_ctl.scala 656:99] + node _T_257 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 657:38] + node _T_258 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 657:59] + node _T_259 = eq(_T_258, UInt<1>("h00")) @[exu_div_ctl.scala 657:46] + node _T_260 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 657:77] + node _T_261 = and(_T_259, _T_260) @[exu_div_ctl.scala 657:63] + node _T_262 = or(_T_257, _T_261) @[exu_div_ctl.scala 657:42] + node _T_263 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 657:98] + node _T_264 = eq(_T_263, UInt<1>("h00")) @[exu_div_ctl.scala 657:85] + node _T_265 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 657:116] + node _T_266 = and(_T_264, _T_265) @[exu_div_ctl.scala 657:102] + node _T_267 = or(_T_262, _T_266) @[exu_div_ctl.scala 657:82] + node _T_268 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 657:136] + node _T_269 = eq(_T_268, UInt<1>("h00")) @[exu_div_ctl.scala 657:123] + node _T_270 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 657:154] + node _T_271 = and(_T_269, _T_270) @[exu_div_ctl.scala 657:140] + node _T_272 = or(_T_267, _T_271) @[exu_div_ctl.scala 657:121] node _T_273 = cat(_T_243, _T_256) @[Cat.scala 29:58] node _T_274 = cat(_T_273, _T_272) @[Cat.scala 29:58] - quotient_new <= _T_274 @[exu_div_ctl.scala 652:18] - node _T_275 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 657:48] + quotient_new <= _T_274 @[exu_div_ctl.scala 655:18] + node _T_275 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 660:48] node _T_276 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_277 = mux(twos_comp_b_sel, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] @@ -1613,17 +1613,17 @@ circuit exu_div_new_3bit_fullshortq : node _T_495 = cat(_T_494, _T_479) @[lib.scala 430:14] node _T_496 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24] node twos_comp_out = cat(_T_495, _T_496) @[Cat.scala 29:58] - node _T_497 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 661:6] - node _T_498 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 661:17] - node _T_499 = and(_T_497, _T_498) @[exu_div_ctl.scala 661:15] - node _T_500 = bits(_T_499, 0, 0) @[exu_div_ctl.scala 661:36] - node _T_501 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 661:79] - node _T_502 = and(io.signed_in, _T_501) @[exu_div_ctl.scala 661:63] - node _T_503 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 661:98] + node _T_497 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 664:6] + node _T_498 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 664:17] + node _T_499 = and(_T_497, _T_498) @[exu_div_ctl.scala 664:15] + node _T_500 = bits(_T_499, 0, 0) @[exu_div_ctl.scala 664:36] + node _T_501 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 664:79] + node _T_502 = and(io.signed_in, _T_501) @[exu_div_ctl.scala 664:63] + node _T_503 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 664:98] node _T_504 = cat(_T_502, _T_503) @[Cat.scala 29:58] - node _T_505 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 662:52] + node _T_505 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 665:52] node _T_506 = cat(_T_505, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_507 = bits(ar_shifted, 32, 0) @[exu_div_ctl.scala 663:54] + node _T_507 = bits(ar_shifted, 32, 0) @[exu_div_ctl.scala 666:54] node _T_508 = mux(_T_500, _T_504, UInt<1>("h00")) @[Mux.scala 27:72] node _T_509 = mux(a_shift, _T_506, UInt<1>("h00")) @[Mux.scala 27:72] node _T_510 = mux(shortq_enable_ff, _T_507, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1631,13 +1631,13 @@ circuit exu_div_new_3bit_fullshortq : node _T_512 = or(_T_511, _T_510) @[Mux.scala 27:72] wire a_in : UInt<33> @[Mux.scala 27:72] a_in <= _T_512 @[Mux.scala 27:72] - node _T_513 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 666:5] - node _T_514 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 666:78] - node _T_515 = and(io.signed_in, _T_514) @[exu_div_ctl.scala 666:63] - node _T_516 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 666:96] + node _T_513 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 669:5] + node _T_514 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 669:78] + node _T_515 = and(io.signed_in, _T_514) @[exu_div_ctl.scala 669:63] + node _T_516 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 669:96] node _T_517 = cat(_T_515, _T_516) @[Cat.scala 29:58] - node _T_518 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 667:50] - node _T_519 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 667:80] + node _T_518 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 670:50] + node _T_519 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 670:80] node _T_520 = cat(_T_518, _T_519) @[Cat.scala 29:58] node _T_521 = mux(_T_513, _T_517, UInt<1>("h00")) @[Mux.scala 27:72] node _T_522 = mux(b_twos_comp, _T_520, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1645,28 +1645,28 @@ circuit exu_div_new_3bit_fullshortq : wire b_in : UInt<33> @[Mux.scala 27:72] b_in <= _T_523 @[Mux.scala 27:72] node _T_524 = mux(UInt<1>("h01"), UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] - node _T_525 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 671:54] - node _T_526 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 671:65] + node _T_525 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 674:55] + node _T_526 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 674:66] node _T_527 = cat(_T_525, _T_526) @[Cat.scala 29:58] - node _T_528 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 672:57] - node _T_529 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 673:57] - node _T_530 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 674:57] - node _T_531 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 675:57] - node _T_532 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 676:57] - node _T_533 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 677:57] - node _T_534 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 678:57] - node _T_535 = bits(ar_shifted, 65, 33) @[exu_div_ctl.scala 679:57] - node _T_536 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 680:59] + node _T_528 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 675:59] + node _T_529 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 676:59] + node _T_530 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 677:59] + node _T_531 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 678:59] + node _T_532 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 679:59] + node _T_533 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 680:59] + node _T_534 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 681:59] + node _T_535 = bits(ar_shifted, 65, 33) @[exu_div_ctl.scala 682:57] + node _T_536 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 683:59] node _T_537 = cat(UInt<1>("h00"), _T_536) @[Cat.scala 29:58] node _T_538 = mux(r_sign_sel, _T_524, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_539 = mux(r_restore_sel, _T_527, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_540 = mux(r_adder1_sel, _T_528, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_541 = mux(r_adder2_sel, _T_529, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_542 = mux(r_adder3_sel, _T_530, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_543 = mux(r_adder4_sel, _T_531, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_544 = mux(r_adder5_sel, _T_532, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_545 = mux(r_adder6_sel, _T_533, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_546 = mux(r_adder7_sel, _T_534, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_539 = mux(r_adder_sel_0, _T_527, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_540 = mux(r_adder_sel_1, _T_528, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_541 = mux(r_adder_sel_2, _T_529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_542 = mux(r_adder_sel_3, _T_530, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_543 = mux(r_adder_sel_4, _T_531, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_544 = mux(r_adder_sel_5, _T_532, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_545 = mux(r_adder_sel_6, _T_533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_546 = mux(r_adder_sel_7, _T_534, UInt<1>("h00")) @[Mux.scala 27:72] node _T_547 = mux(shortq_enable_ff, _T_535, UInt<1>("h00")) @[Mux.scala 27:72] node _T_548 = mux(by_zero_case, _T_537, UInt<1>("h00")) @[Mux.scala 27:72] node _T_549 = or(_T_538, _T_539) @[Mux.scala 27:72] @@ -1681,8 +1681,8 @@ circuit exu_div_new_3bit_fullshortq : node _T_558 = or(_T_557, _T_548) @[Mux.scala 27:72] wire r_in : UInt<33> @[Mux.scala 27:72] r_in <= _T_558 @[Mux.scala 27:72] - node _T_559 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 683:4] - node _T_560 = bits(q_ff, 28, 0) @[exu_div_ctl.scala 683:54] + node _T_559 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 686:4] + node _T_560 = bits(q_ff, 28, 0) @[exu_div_ctl.scala 686:54] node _T_561 = cat(_T_560, quotient_new) @[Cat.scala 29:58] node _T_562 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58] node _T_563 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] @@ -1693,14 +1693,14 @@ circuit exu_div_new_3bit_fullshortq : node _T_568 = or(_T_567, _T_566) @[Mux.scala 27:72] wire q_in : UInt<32> @[Mux.scala 27:72] q_in <= _T_568 @[Mux.scala 27:72] - node _T_569 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 687:30] - node _T_570 = and(finish_ff, _T_569) @[exu_div_ctl.scala 687:28] - io.valid_out <= _T_570 @[exu_div_ctl.scala 687:15] - node _T_571 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 689:6] - node _T_572 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 689:16] - node _T_573 = and(_T_571, _T_572) @[exu_div_ctl.scala 689:14] - node _T_574 = bits(_T_573, 0, 0) @[exu_div_ctl.scala 689:40] - node _T_575 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 690:48] + node _T_569 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 690:30] + node _T_570 = and(finish_ff, _T_569) @[exu_div_ctl.scala 690:28] + io.valid_out <= _T_570 @[exu_div_ctl.scala 690:15] + node _T_571 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 692:6] + node _T_572 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 692:16] + node _T_573 = and(_T_571, _T_572) @[exu_div_ctl.scala 692:14] + node _T_574 = bits(_T_573, 0, 0) @[exu_div_ctl.scala 692:40] + node _T_575 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 693:48] node _T_576 = mux(_T_574, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_577 = mux(rem_ff, _T_575, UInt<1>("h00")) @[Mux.scala 27:72] node _T_578 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72] @@ -1708,531 +1708,531 @@ circuit exu_div_new_3bit_fullshortq : node _T_580 = or(_T_579, _T_578) @[Mux.scala 27:72] wire _T_581 : UInt<32> @[Mux.scala 27:72] _T_581 <= _T_580 @[Mux.scala 27:72] - io.data_out <= _T_581 @[exu_div_ctl.scala 688:15] - node _T_582 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_583 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_584 = eq(_T_583, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_585 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_586 = eq(_T_585, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_587 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_589 = and(_T_584, _T_586) @[exu_div_ctl.scala 695:95] - node _T_590 = and(_T_589, _T_588) @[exu_div_ctl.scala 695:95] - node _T_591 = and(_T_582, _T_590) @[exu_div_ctl.scala 696:11] - node _T_592 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_593 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_594 = eq(_T_593, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_595 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_597 = and(_T_594, _T_596) @[exu_div_ctl.scala 695:95] - node _T_598 = and(_T_592, _T_597) @[exu_div_ctl.scala 696:11] - node _T_599 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 701:38] - node _T_600 = eq(_T_599, UInt<1>("h00")) @[exu_div_ctl.scala 701:33] - node _T_601 = and(_T_598, _T_600) @[exu_div_ctl.scala 701:31] - node _T_602 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_603 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_605 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_606 = eq(_T_605, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_607 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_608 = eq(_T_607, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_609 = and(_T_604, _T_606) @[exu_div_ctl.scala 695:95] - node _T_610 = and(_T_609, _T_608) @[exu_div_ctl.scala 695:95] - node _T_611 = and(_T_602, _T_610) @[exu_div_ctl.scala 696:11] - node _T_612 = or(_T_601, _T_611) @[exu_div_ctl.scala 701:42] - node _T_613 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_614 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_615 = and(_T_613, _T_614) @[exu_div_ctl.scala 694:95] - node _T_616 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_617 = eq(_T_616, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_618 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_620 = and(_T_617, _T_619) @[exu_div_ctl.scala 695:95] - node _T_621 = and(_T_615, _T_620) @[exu_div_ctl.scala 696:11] - node _T_622 = or(_T_612, _T_621) @[exu_div_ctl.scala 701:75] - node _T_623 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_624 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_625 = eq(_T_624, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_626 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_627 = eq(_T_626, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_628 = and(_T_625, _T_627) @[exu_div_ctl.scala 695:95] - node _T_629 = and(_T_623, _T_628) @[exu_div_ctl.scala 696:11] - node _T_630 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 703:38] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[exu_div_ctl.scala 703:33] - node _T_632 = and(_T_629, _T_631) @[exu_div_ctl.scala 703:31] - node _T_633 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_634 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_636 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_637 = eq(_T_636, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_638 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_639 = eq(_T_638, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_640 = and(_T_635, _T_637) @[exu_div_ctl.scala 695:95] - node _T_641 = and(_T_640, _T_639) @[exu_div_ctl.scala 695:95] - node _T_642 = and(_T_633, _T_641) @[exu_div_ctl.scala 696:11] - node _T_643 = or(_T_632, _T_642) @[exu_div_ctl.scala 703:42] - node _T_644 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_645 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_647 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_648 = eq(_T_647, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_649 = and(_T_646, _T_648) @[exu_div_ctl.scala 695:95] - node _T_650 = and(_T_644, _T_649) @[exu_div_ctl.scala 696:11] - node _T_651 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 703:113] - node _T_652 = eq(_T_651, UInt<1>("h00")) @[exu_div_ctl.scala 703:108] - node _T_653 = and(_T_650, _T_652) @[exu_div_ctl.scala 703:106] - node _T_654 = or(_T_643, _T_653) @[exu_div_ctl.scala 703:78] - node _T_655 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_656 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_657 = eq(_T_656, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_658 = and(_T_655, _T_657) @[exu_div_ctl.scala 694:95] - node _T_659 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_660 = eq(_T_659, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_661 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_663 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_664 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 695:58] - node _T_665 = and(_T_660, _T_662) @[exu_div_ctl.scala 695:95] - node _T_666 = and(_T_665, _T_663) @[exu_div_ctl.scala 695:95] - node _T_667 = and(_T_666, _T_664) @[exu_div_ctl.scala 695:95] - node _T_668 = and(_T_658, _T_667) @[exu_div_ctl.scala 696:11] - node _T_669 = or(_T_654, _T_668) @[exu_div_ctl.scala 703:117] - node _T_670 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_671 = eq(_T_670, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_672 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_673 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_674 = and(_T_671, _T_672) @[exu_div_ctl.scala 694:95] - node _T_675 = and(_T_674, _T_673) @[exu_div_ctl.scala 694:95] - node _T_676 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_677 = eq(_T_676, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_678 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_679 = eq(_T_678, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_680 = and(_T_677, _T_679) @[exu_div_ctl.scala 695:95] - node _T_681 = and(_T_675, _T_680) @[exu_div_ctl.scala 696:11] - node _T_682 = or(_T_669, _T_681) @[exu_div_ctl.scala 704:44] - node _T_683 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_684 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_685 = and(_T_683, _T_684) @[exu_div_ctl.scala 694:95] - node _T_686 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_687 = eq(_T_686, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_688 = and(_T_685, _T_687) @[exu_div_ctl.scala 696:11] - node _T_689 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 704:114] - node _T_690 = eq(_T_689, UInt<1>("h00")) @[exu_div_ctl.scala 704:109] - node _T_691 = and(_T_688, _T_690) @[exu_div_ctl.scala 704:107] - node _T_692 = or(_T_682, _T_691) @[exu_div_ctl.scala 704:80] - node _T_693 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_694 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_695 = and(_T_693, _T_694) @[exu_div_ctl.scala 694:95] - node _T_696 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_697 = eq(_T_696, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_698 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_699 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_700 = eq(_T_699, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_701 = and(_T_697, _T_698) @[exu_div_ctl.scala 695:95] - node _T_702 = and(_T_701, _T_700) @[exu_div_ctl.scala 695:95] - node _T_703 = and(_T_695, _T_702) @[exu_div_ctl.scala 696:11] - node _T_704 = or(_T_692, _T_703) @[exu_div_ctl.scala 704:119] - node _T_705 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_706 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_707 = and(_T_705, _T_706) @[exu_div_ctl.scala 694:95] - node _T_708 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_709 = eq(_T_708, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_710 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_712 = and(_T_709, _T_711) @[exu_div_ctl.scala 695:95] - node _T_713 = and(_T_707, _T_712) @[exu_div_ctl.scala 696:11] - node _T_714 = or(_T_704, _T_713) @[exu_div_ctl.scala 705:44] - node _T_715 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_716 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_717 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_718 = and(_T_715, _T_716) @[exu_div_ctl.scala 694:95] - node _T_719 = and(_T_718, _T_717) @[exu_div_ctl.scala 694:95] - node _T_720 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_721 = eq(_T_720, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_722 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_723 = and(_T_721, _T_722) @[exu_div_ctl.scala 695:95] - node _T_724 = and(_T_719, _T_723) @[exu_div_ctl.scala 696:11] - node _T_725 = or(_T_714, _T_724) @[exu_div_ctl.scala 705:79] - node _T_726 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_727 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_728 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_729 = and(_T_726, _T_727) @[exu_div_ctl.scala 694:95] - node _T_730 = and(_T_729, _T_728) @[exu_div_ctl.scala 694:95] - node _T_731 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_732 = eq(_T_731, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_733 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_735 = and(_T_732, _T_734) @[exu_div_ctl.scala 695:95] - node _T_736 = and(_T_730, _T_735) @[exu_div_ctl.scala 696:11] - node _T_737 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_738 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_739 = eq(_T_738, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_740 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_741 = and(_T_737, _T_739) @[exu_div_ctl.scala 694:95] - node _T_742 = and(_T_741, _T_740) @[exu_div_ctl.scala 694:95] - node _T_743 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_744 = eq(_T_743, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_745 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_746 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 695:58] - node _T_747 = and(_T_744, _T_745) @[exu_div_ctl.scala 695:95] - node _T_748 = and(_T_747, _T_746) @[exu_div_ctl.scala 695:95] - node _T_749 = and(_T_742, _T_748) @[exu_div_ctl.scala 696:11] - node _T_750 = or(_T_736, _T_749) @[exu_div_ctl.scala 707:45] - node _T_751 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_752 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_753 = eq(_T_752, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_754 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_755 = eq(_T_754, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_756 = and(_T_753, _T_755) @[exu_div_ctl.scala 695:95] - node _T_757 = and(_T_751, _T_756) @[exu_div_ctl.scala 696:11] - node _T_758 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 707:121] - node _T_759 = eq(_T_758, UInt<1>("h00")) @[exu_div_ctl.scala 707:116] - node _T_760 = and(_T_757, _T_759) @[exu_div_ctl.scala 707:114] - node _T_761 = or(_T_750, _T_760) @[exu_div_ctl.scala 707:86] - node _T_762 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_763 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_764 = eq(_T_763, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_765 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_766 = eq(_T_765, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_767 = and(_T_764, _T_766) @[exu_div_ctl.scala 695:95] - node _T_768 = and(_T_762, _T_767) @[exu_div_ctl.scala 696:11] - node _T_769 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 708:40] - node _T_770 = eq(_T_769, UInt<1>("h00")) @[exu_div_ctl.scala 708:35] - node _T_771 = and(_T_768, _T_770) @[exu_div_ctl.scala 708:33] - node _T_772 = or(_T_761, _T_771) @[exu_div_ctl.scala 707:129] - node _T_773 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_774 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_776 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_778 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_780 = and(_T_775, _T_777) @[exu_div_ctl.scala 695:95] - node _T_781 = and(_T_780, _T_779) @[exu_div_ctl.scala 695:95] - node _T_782 = and(_T_773, _T_781) @[exu_div_ctl.scala 696:11] - node _T_783 = or(_T_772, _T_782) @[exu_div_ctl.scala 708:47] - node _T_784 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_785 = eq(_T_784, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_786 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_787 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:75] - node _T_788 = eq(_T_787, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_789 = and(_T_785, _T_786) @[exu_div_ctl.scala 694:95] - node _T_790 = and(_T_789, _T_788) @[exu_div_ctl.scala 694:95] - node _T_791 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_792 = eq(_T_791, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_793 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_794 = eq(_T_793, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_795 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_796 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 695:58] - node _T_797 = and(_T_792, _T_794) @[exu_div_ctl.scala 695:95] - node _T_798 = and(_T_797, _T_795) @[exu_div_ctl.scala 695:95] - node _T_799 = and(_T_798, _T_796) @[exu_div_ctl.scala 695:95] - node _T_800 = and(_T_790, _T_799) @[exu_div_ctl.scala 696:11] - node _T_801 = or(_T_783, _T_800) @[exu_div_ctl.scala 708:88] - node _T_802 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_803 = eq(_T_802, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_804 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_805 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_806 = and(_T_803, _T_804) @[exu_div_ctl.scala 694:95] - node _T_807 = and(_T_806, _T_805) @[exu_div_ctl.scala 694:95] - node _T_808 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_810 = and(_T_807, _T_809) @[exu_div_ctl.scala 696:11] - node _T_811 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 709:43] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[exu_div_ctl.scala 709:38] - node _T_813 = and(_T_810, _T_812) @[exu_div_ctl.scala 709:36] - node _T_814 = or(_T_801, _T_813) @[exu_div_ctl.scala 708:131] - node _T_815 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_816 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_817 = eq(_T_816, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_818 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_819 = eq(_T_818, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_820 = and(_T_817, _T_819) @[exu_div_ctl.scala 695:95] - node _T_821 = and(_T_815, _T_820) @[exu_div_ctl.scala 696:11] - node _T_822 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 709:83] - node _T_823 = eq(_T_822, UInt<1>("h00")) @[exu_div_ctl.scala 709:78] - node _T_824 = and(_T_821, _T_823) @[exu_div_ctl.scala 709:76] - node _T_825 = or(_T_814, _T_824) @[exu_div_ctl.scala 709:47] - node _T_826 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_827 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_828 = eq(_T_827, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_829 = and(_T_826, _T_828) @[exu_div_ctl.scala 694:95] - node _T_830 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_831 = eq(_T_830, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_832 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_833 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_834 = and(_T_831, _T_832) @[exu_div_ctl.scala 695:95] - node _T_835 = and(_T_834, _T_833) @[exu_div_ctl.scala 695:95] - node _T_836 = and(_T_829, _T_835) @[exu_div_ctl.scala 696:11] - node _T_837 = or(_T_825, _T_836) @[exu_div_ctl.scala 709:88] - node _T_838 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_840 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_841 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_842 = and(_T_839, _T_840) @[exu_div_ctl.scala 694:95] - node _T_843 = and(_T_842, _T_841) @[exu_div_ctl.scala 694:95] - node _T_844 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_845 = eq(_T_844, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_846 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_847 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_848 = eq(_T_847, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_849 = and(_T_845, _T_846) @[exu_div_ctl.scala 695:95] - node _T_850 = and(_T_849, _T_848) @[exu_div_ctl.scala 695:95] - node _T_851 = and(_T_843, _T_850) @[exu_div_ctl.scala 696:11] - node _T_852 = or(_T_837, _T_851) @[exu_div_ctl.scala 709:131] - node _T_853 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_854 = eq(_T_853, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_855 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_856 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_857 = and(_T_854, _T_855) @[exu_div_ctl.scala 694:95] - node _T_858 = and(_T_857, _T_856) @[exu_div_ctl.scala 694:95] - node _T_859 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_861 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_863 = and(_T_860, _T_862) @[exu_div_ctl.scala 695:95] - node _T_864 = and(_T_858, _T_863) @[exu_div_ctl.scala 696:11] - node _T_865 = or(_T_852, _T_864) @[exu_div_ctl.scala 710:47] - node _T_866 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_867 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_868 = eq(_T_867, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_869 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:75] - node _T_870 = eq(_T_869, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_871 = and(_T_866, _T_868) @[exu_div_ctl.scala 694:95] - node _T_872 = and(_T_871, _T_870) @[exu_div_ctl.scala 694:95] - node _T_873 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_875 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_876 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 695:58] - node _T_877 = and(_T_874, _T_875) @[exu_div_ctl.scala 695:95] - node _T_878 = and(_T_877, _T_876) @[exu_div_ctl.scala 695:95] - node _T_879 = and(_T_872, _T_878) @[exu_div_ctl.scala 696:11] - node _T_880 = or(_T_865, _T_879) @[exu_div_ctl.scala 710:88] - node _T_881 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_883 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_884 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_885 = and(_T_882, _T_883) @[exu_div_ctl.scala 694:95] - node _T_886 = and(_T_885, _T_884) @[exu_div_ctl.scala 694:95] - node _T_887 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_888 = eq(_T_887, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_889 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_890 = eq(_T_889, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_891 = and(_T_888, _T_890) @[exu_div_ctl.scala 695:95] - node _T_892 = and(_T_886, _T_891) @[exu_div_ctl.scala 696:11] - node _T_893 = or(_T_880, _T_892) @[exu_div_ctl.scala 710:131] - node _T_894 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_895 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_896 = and(_T_894, _T_895) @[exu_div_ctl.scala 694:95] - node _T_897 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_898 = eq(_T_897, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_899 = and(_T_896, _T_898) @[exu_div_ctl.scala 696:11] - node _T_900 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 711:82] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[exu_div_ctl.scala 711:77] - node _T_902 = and(_T_899, _T_901) @[exu_div_ctl.scala 711:75] - node _T_903 = or(_T_893, _T_902) @[exu_div_ctl.scala 711:47] - node _T_904 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:75] - node _T_905 = eq(_T_904, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_906 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_907 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_908 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_909 = and(_T_905, _T_906) @[exu_div_ctl.scala 694:95] - node _T_910 = and(_T_909, _T_907) @[exu_div_ctl.scala 694:95] - node _T_911 = and(_T_910, _T_908) @[exu_div_ctl.scala 694:95] - node _T_912 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_913 = eq(_T_912, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_914 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_915 = and(_T_913, _T_914) @[exu_div_ctl.scala 695:95] - node _T_916 = and(_T_911, _T_915) @[exu_div_ctl.scala 696:11] - node _T_917 = or(_T_903, _T_916) @[exu_div_ctl.scala 711:88] - node _T_918 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_919 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_920 = and(_T_918, _T_919) @[exu_div_ctl.scala 694:95] - node _T_921 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_922 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_923 = eq(_T_922, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_924 = and(_T_921, _T_923) @[exu_div_ctl.scala 695:95] - node _T_925 = and(_T_920, _T_924) @[exu_div_ctl.scala 696:11] - node _T_926 = or(_T_917, _T_925) @[exu_div_ctl.scala 711:131] - node _T_927 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_928 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_929 = and(_T_927, _T_928) @[exu_div_ctl.scala 694:95] - node _T_930 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_931 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_932 = eq(_T_931, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_933 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_934 = eq(_T_933, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_935 = and(_T_930, _T_932) @[exu_div_ctl.scala 695:95] - node _T_936 = and(_T_935, _T_934) @[exu_div_ctl.scala 695:95] - node _T_937 = and(_T_929, _T_936) @[exu_div_ctl.scala 696:11] - node _T_938 = or(_T_926, _T_937) @[exu_div_ctl.scala 712:47] - node _T_939 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_940 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_941 = and(_T_939, _T_940) @[exu_div_ctl.scala 694:95] - node _T_942 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_943 = eq(_T_942, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_944 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_945 = eq(_T_944, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_946 = and(_T_943, _T_945) @[exu_div_ctl.scala 695:95] - node _T_947 = and(_T_941, _T_946) @[exu_div_ctl.scala 696:11] - node _T_948 = or(_T_938, _T_947) @[exu_div_ctl.scala 712:88] - node _T_949 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_950 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:75] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_952 = and(_T_949, _T_951) @[exu_div_ctl.scala 694:95] - node _T_953 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_955 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:58] - node _T_956 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_957 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 695:58] - node _T_958 = and(_T_954, _T_955) @[exu_div_ctl.scala 695:95] - node _T_959 = and(_T_958, _T_956) @[exu_div_ctl.scala 695:95] - node _T_960 = and(_T_959, _T_957) @[exu_div_ctl.scala 695:95] - node _T_961 = and(_T_952, _T_960) @[exu_div_ctl.scala 696:11] - node _T_962 = or(_T_948, _T_961) @[exu_div_ctl.scala 712:131] - node _T_963 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_964 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_965 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_966 = and(_T_963, _T_964) @[exu_div_ctl.scala 694:95] - node _T_967 = and(_T_966, _T_965) @[exu_div_ctl.scala 694:95] - node _T_968 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_969 = and(_T_967, _T_968) @[exu_div_ctl.scala 696:11] - node _T_970 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 713:84] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[exu_div_ctl.scala 713:79] - node _T_972 = and(_T_969, _T_971) @[exu_div_ctl.scala 713:77] - node _T_973 = or(_T_962, _T_972) @[exu_div_ctl.scala 713:47] - node _T_974 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_975 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_976 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_977 = and(_T_974, _T_975) @[exu_div_ctl.scala 694:95] - node _T_978 = and(_T_977, _T_976) @[exu_div_ctl.scala 694:95] - node _T_979 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_980 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_981 = eq(_T_980, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_982 = and(_T_979, _T_981) @[exu_div_ctl.scala 695:95] - node _T_983 = and(_T_978, _T_982) @[exu_div_ctl.scala 696:11] - node _T_984 = or(_T_973, _T_983) @[exu_div_ctl.scala 713:88] - node _T_985 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_986 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_987 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_988 = and(_T_985, _T_986) @[exu_div_ctl.scala 694:95] - node _T_989 = and(_T_988, _T_987) @[exu_div_ctl.scala 694:95] - node _T_990 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_991 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:75] - node _T_992 = eq(_T_991, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_993 = and(_T_990, _T_992) @[exu_div_ctl.scala 695:95] - node _T_994 = and(_T_989, _T_993) @[exu_div_ctl.scala 696:11] - node _T_995 = or(_T_984, _T_994) @[exu_div_ctl.scala 713:131] - node _T_996 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_997 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:75] - node _T_998 = eq(_T_997, UInt<1>("h00")) @[exu_div_ctl.scala 694:70] - node _T_999 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_1000 = and(_T_996, _T_998) @[exu_div_ctl.scala 694:95] - node _T_1001 = and(_T_1000, _T_999) @[exu_div_ctl.scala 694:95] - node _T_1002 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:75] - node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_1004 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 695:58] - node _T_1005 = and(_T_1003, _T_1004) @[exu_div_ctl.scala 695:95] - node _T_1006 = and(_T_1001, _T_1005) @[exu_div_ctl.scala 696:11] - node _T_1007 = or(_T_995, _T_1006) @[exu_div_ctl.scala 714:47] - node _T_1008 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_1009 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_1010 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_1011 = and(_T_1008, _T_1009) @[exu_div_ctl.scala 694:95] - node _T_1012 = and(_T_1011, _T_1010) @[exu_div_ctl.scala 694:95] - node _T_1013 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_1015 = and(_T_1012, _T_1014) @[exu_div_ctl.scala 696:11] - node _T_1016 = or(_T_1007, _T_1015) @[exu_div_ctl.scala 714:88] - node _T_1017 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_1018 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 694:58] - node _T_1019 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_1020 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 694:58] - node _T_1021 = and(_T_1017, _T_1018) @[exu_div_ctl.scala 694:95] - node _T_1022 = and(_T_1021, _T_1019) @[exu_div_ctl.scala 694:95] - node _T_1023 = and(_T_1022, _T_1020) @[exu_div_ctl.scala 694:95] - node _T_1024 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 695:58] - node _T_1025 = and(_T_1023, _T_1024) @[exu_div_ctl.scala 696:11] - node _T_1026 = or(_T_1016, _T_1025) @[exu_div_ctl.scala 714:131] - node _T_1027 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 694:58] - node _T_1028 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 694:58] - node _T_1029 = and(_T_1027, _T_1028) @[exu_div_ctl.scala 694:95] - node _T_1030 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 695:75] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[exu_div_ctl.scala 695:70] - node _T_1032 = and(_T_1029, _T_1031) @[exu_div_ctl.scala 696:11] - node _T_1033 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 715:81] - node _T_1034 = eq(_T_1033, UInt<1>("h00")) @[exu_div_ctl.scala 715:76] - node _T_1035 = and(_T_1032, _T_1034) @[exu_div_ctl.scala 715:74] - node _T_1036 = or(_T_1026, _T_1035) @[exu_div_ctl.scala 715:47] + io.data_out <= _T_581 @[exu_div_ctl.scala 691:15] + node _T_582 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_583 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_585 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_587 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_589 = and(_T_584, _T_586) @[exu_div_ctl.scala 698:95] + node _T_590 = and(_T_589, _T_588) @[exu_div_ctl.scala 698:95] + node _T_591 = and(_T_582, _T_590) @[exu_div_ctl.scala 699:11] + node _T_592 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_593 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_594 = eq(_T_593, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_595 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_597 = and(_T_594, _T_596) @[exu_div_ctl.scala 698:95] + node _T_598 = and(_T_592, _T_597) @[exu_div_ctl.scala 699:11] + node _T_599 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 704:38] + node _T_600 = eq(_T_599, UInt<1>("h00")) @[exu_div_ctl.scala 704:33] + node _T_601 = and(_T_598, _T_600) @[exu_div_ctl.scala 704:31] + node _T_602 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_603 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_605 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_606 = eq(_T_605, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_607 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_608 = eq(_T_607, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_609 = and(_T_604, _T_606) @[exu_div_ctl.scala 698:95] + node _T_610 = and(_T_609, _T_608) @[exu_div_ctl.scala 698:95] + node _T_611 = and(_T_602, _T_610) @[exu_div_ctl.scala 699:11] + node _T_612 = or(_T_601, _T_611) @[exu_div_ctl.scala 704:42] + node _T_613 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_614 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_615 = and(_T_613, _T_614) @[exu_div_ctl.scala 697:95] + node _T_616 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_618 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_620 = and(_T_617, _T_619) @[exu_div_ctl.scala 698:95] + node _T_621 = and(_T_615, _T_620) @[exu_div_ctl.scala 699:11] + node _T_622 = or(_T_612, _T_621) @[exu_div_ctl.scala 704:75] + node _T_623 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_624 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_626 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_628 = and(_T_625, _T_627) @[exu_div_ctl.scala 698:95] + node _T_629 = and(_T_623, _T_628) @[exu_div_ctl.scala 699:11] + node _T_630 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 706:38] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[exu_div_ctl.scala 706:33] + node _T_632 = and(_T_629, _T_631) @[exu_div_ctl.scala 706:31] + node _T_633 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_634 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_636 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_637 = eq(_T_636, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_638 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_640 = and(_T_635, _T_637) @[exu_div_ctl.scala 698:95] + node _T_641 = and(_T_640, _T_639) @[exu_div_ctl.scala 698:95] + node _T_642 = and(_T_633, _T_641) @[exu_div_ctl.scala 699:11] + node _T_643 = or(_T_632, _T_642) @[exu_div_ctl.scala 706:42] + node _T_644 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_645 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_647 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_648 = eq(_T_647, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_649 = and(_T_646, _T_648) @[exu_div_ctl.scala 698:95] + node _T_650 = and(_T_644, _T_649) @[exu_div_ctl.scala 699:11] + node _T_651 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 706:113] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[exu_div_ctl.scala 706:108] + node _T_653 = and(_T_650, _T_652) @[exu_div_ctl.scala 706:106] + node _T_654 = or(_T_643, _T_653) @[exu_div_ctl.scala 706:78] + node _T_655 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_656 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_657 = eq(_T_656, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_658 = and(_T_655, _T_657) @[exu_div_ctl.scala 697:95] + node _T_659 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_661 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_663 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_664 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 698:58] + node _T_665 = and(_T_660, _T_662) @[exu_div_ctl.scala 698:95] + node _T_666 = and(_T_665, _T_663) @[exu_div_ctl.scala 698:95] + node _T_667 = and(_T_666, _T_664) @[exu_div_ctl.scala 698:95] + node _T_668 = and(_T_658, _T_667) @[exu_div_ctl.scala 699:11] + node _T_669 = or(_T_654, _T_668) @[exu_div_ctl.scala 706:117] + node _T_670 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_671 = eq(_T_670, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_672 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_673 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_674 = and(_T_671, _T_672) @[exu_div_ctl.scala 697:95] + node _T_675 = and(_T_674, _T_673) @[exu_div_ctl.scala 697:95] + node _T_676 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_678 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_679 = eq(_T_678, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_680 = and(_T_677, _T_679) @[exu_div_ctl.scala 698:95] + node _T_681 = and(_T_675, _T_680) @[exu_div_ctl.scala 699:11] + node _T_682 = or(_T_669, _T_681) @[exu_div_ctl.scala 707:44] + node _T_683 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_684 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_685 = and(_T_683, _T_684) @[exu_div_ctl.scala 697:95] + node _T_686 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_687 = eq(_T_686, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_688 = and(_T_685, _T_687) @[exu_div_ctl.scala 699:11] + node _T_689 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 707:114] + node _T_690 = eq(_T_689, UInt<1>("h00")) @[exu_div_ctl.scala 707:109] + node _T_691 = and(_T_688, _T_690) @[exu_div_ctl.scala 707:107] + node _T_692 = or(_T_682, _T_691) @[exu_div_ctl.scala 707:80] + node _T_693 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_694 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_695 = and(_T_693, _T_694) @[exu_div_ctl.scala 697:95] + node _T_696 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_697 = eq(_T_696, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_698 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_699 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_700 = eq(_T_699, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_701 = and(_T_697, _T_698) @[exu_div_ctl.scala 698:95] + node _T_702 = and(_T_701, _T_700) @[exu_div_ctl.scala 698:95] + node _T_703 = and(_T_695, _T_702) @[exu_div_ctl.scala 699:11] + node _T_704 = or(_T_692, _T_703) @[exu_div_ctl.scala 707:119] + node _T_705 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_706 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_707 = and(_T_705, _T_706) @[exu_div_ctl.scala 697:95] + node _T_708 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_709 = eq(_T_708, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_710 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_712 = and(_T_709, _T_711) @[exu_div_ctl.scala 698:95] + node _T_713 = and(_T_707, _T_712) @[exu_div_ctl.scala 699:11] + node _T_714 = or(_T_704, _T_713) @[exu_div_ctl.scala 708:44] + node _T_715 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_716 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_717 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_718 = and(_T_715, _T_716) @[exu_div_ctl.scala 697:95] + node _T_719 = and(_T_718, _T_717) @[exu_div_ctl.scala 697:95] + node _T_720 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_721 = eq(_T_720, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_722 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_723 = and(_T_721, _T_722) @[exu_div_ctl.scala 698:95] + node _T_724 = and(_T_719, _T_723) @[exu_div_ctl.scala 699:11] + node _T_725 = or(_T_714, _T_724) @[exu_div_ctl.scala 708:79] + node _T_726 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_727 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_728 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_729 = and(_T_726, _T_727) @[exu_div_ctl.scala 697:95] + node _T_730 = and(_T_729, _T_728) @[exu_div_ctl.scala 697:95] + node _T_731 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_732 = eq(_T_731, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_733 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_735 = and(_T_732, _T_734) @[exu_div_ctl.scala 698:95] + node _T_736 = and(_T_730, _T_735) @[exu_div_ctl.scala 699:11] + node _T_737 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_738 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_739 = eq(_T_738, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_740 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_741 = and(_T_737, _T_739) @[exu_div_ctl.scala 697:95] + node _T_742 = and(_T_741, _T_740) @[exu_div_ctl.scala 697:95] + node _T_743 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_744 = eq(_T_743, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_745 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_746 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 698:58] + node _T_747 = and(_T_744, _T_745) @[exu_div_ctl.scala 698:95] + node _T_748 = and(_T_747, _T_746) @[exu_div_ctl.scala 698:95] + node _T_749 = and(_T_742, _T_748) @[exu_div_ctl.scala 699:11] + node _T_750 = or(_T_736, _T_749) @[exu_div_ctl.scala 710:45] + node _T_751 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_752 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_753 = eq(_T_752, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_754 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_755 = eq(_T_754, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_756 = and(_T_753, _T_755) @[exu_div_ctl.scala 698:95] + node _T_757 = and(_T_751, _T_756) @[exu_div_ctl.scala 699:11] + node _T_758 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 710:121] + node _T_759 = eq(_T_758, UInt<1>("h00")) @[exu_div_ctl.scala 710:116] + node _T_760 = and(_T_757, _T_759) @[exu_div_ctl.scala 710:114] + node _T_761 = or(_T_750, _T_760) @[exu_div_ctl.scala 710:86] + node _T_762 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_763 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_764 = eq(_T_763, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_765 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_767 = and(_T_764, _T_766) @[exu_div_ctl.scala 698:95] + node _T_768 = and(_T_762, _T_767) @[exu_div_ctl.scala 699:11] + node _T_769 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 711:40] + node _T_770 = eq(_T_769, UInt<1>("h00")) @[exu_div_ctl.scala 711:35] + node _T_771 = and(_T_768, _T_770) @[exu_div_ctl.scala 711:33] + node _T_772 = or(_T_761, _T_771) @[exu_div_ctl.scala 710:129] + node _T_773 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_774 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_776 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_778 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_780 = and(_T_775, _T_777) @[exu_div_ctl.scala 698:95] + node _T_781 = and(_T_780, _T_779) @[exu_div_ctl.scala 698:95] + node _T_782 = and(_T_773, _T_781) @[exu_div_ctl.scala 699:11] + node _T_783 = or(_T_772, _T_782) @[exu_div_ctl.scala 711:47] + node _T_784 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_785 = eq(_T_784, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_786 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_787 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:75] + node _T_788 = eq(_T_787, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_789 = and(_T_785, _T_786) @[exu_div_ctl.scala 697:95] + node _T_790 = and(_T_789, _T_788) @[exu_div_ctl.scala 697:95] + node _T_791 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_792 = eq(_T_791, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_793 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_795 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_796 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 698:58] + node _T_797 = and(_T_792, _T_794) @[exu_div_ctl.scala 698:95] + node _T_798 = and(_T_797, _T_795) @[exu_div_ctl.scala 698:95] + node _T_799 = and(_T_798, _T_796) @[exu_div_ctl.scala 698:95] + node _T_800 = and(_T_790, _T_799) @[exu_div_ctl.scala 699:11] + node _T_801 = or(_T_783, _T_800) @[exu_div_ctl.scala 711:88] + node _T_802 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_803 = eq(_T_802, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_804 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_805 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_806 = and(_T_803, _T_804) @[exu_div_ctl.scala 697:95] + node _T_807 = and(_T_806, _T_805) @[exu_div_ctl.scala 697:95] + node _T_808 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_810 = and(_T_807, _T_809) @[exu_div_ctl.scala 699:11] + node _T_811 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 712:43] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[exu_div_ctl.scala 712:38] + node _T_813 = and(_T_810, _T_812) @[exu_div_ctl.scala 712:36] + node _T_814 = or(_T_801, _T_813) @[exu_div_ctl.scala 711:131] + node _T_815 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_816 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_817 = eq(_T_816, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_818 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_820 = and(_T_817, _T_819) @[exu_div_ctl.scala 698:95] + node _T_821 = and(_T_815, _T_820) @[exu_div_ctl.scala 699:11] + node _T_822 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 712:83] + node _T_823 = eq(_T_822, UInt<1>("h00")) @[exu_div_ctl.scala 712:78] + node _T_824 = and(_T_821, _T_823) @[exu_div_ctl.scala 712:76] + node _T_825 = or(_T_814, _T_824) @[exu_div_ctl.scala 712:47] + node _T_826 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_827 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_828 = eq(_T_827, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_829 = and(_T_826, _T_828) @[exu_div_ctl.scala 697:95] + node _T_830 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_832 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_833 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_834 = and(_T_831, _T_832) @[exu_div_ctl.scala 698:95] + node _T_835 = and(_T_834, _T_833) @[exu_div_ctl.scala 698:95] + node _T_836 = and(_T_829, _T_835) @[exu_div_ctl.scala 699:11] + node _T_837 = or(_T_825, _T_836) @[exu_div_ctl.scala 712:88] + node _T_838 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_840 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_841 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_842 = and(_T_839, _T_840) @[exu_div_ctl.scala 697:95] + node _T_843 = and(_T_842, _T_841) @[exu_div_ctl.scala 697:95] + node _T_844 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_845 = eq(_T_844, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_846 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_847 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_848 = eq(_T_847, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_849 = and(_T_845, _T_846) @[exu_div_ctl.scala 698:95] + node _T_850 = and(_T_849, _T_848) @[exu_div_ctl.scala 698:95] + node _T_851 = and(_T_843, _T_850) @[exu_div_ctl.scala 699:11] + node _T_852 = or(_T_837, _T_851) @[exu_div_ctl.scala 712:131] + node _T_853 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_855 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_856 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_857 = and(_T_854, _T_855) @[exu_div_ctl.scala 697:95] + node _T_858 = and(_T_857, _T_856) @[exu_div_ctl.scala 697:95] + node _T_859 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_861 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_863 = and(_T_860, _T_862) @[exu_div_ctl.scala 698:95] + node _T_864 = and(_T_858, _T_863) @[exu_div_ctl.scala 699:11] + node _T_865 = or(_T_852, _T_864) @[exu_div_ctl.scala 713:47] + node _T_866 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_867 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_868 = eq(_T_867, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_869 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:75] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_871 = and(_T_866, _T_868) @[exu_div_ctl.scala 697:95] + node _T_872 = and(_T_871, _T_870) @[exu_div_ctl.scala 697:95] + node _T_873 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_875 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_876 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 698:58] + node _T_877 = and(_T_874, _T_875) @[exu_div_ctl.scala 698:95] + node _T_878 = and(_T_877, _T_876) @[exu_div_ctl.scala 698:95] + node _T_879 = and(_T_872, _T_878) @[exu_div_ctl.scala 699:11] + node _T_880 = or(_T_865, _T_879) @[exu_div_ctl.scala 713:88] + node _T_881 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_883 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_884 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_885 = and(_T_882, _T_883) @[exu_div_ctl.scala 697:95] + node _T_886 = and(_T_885, _T_884) @[exu_div_ctl.scala 697:95] + node _T_887 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_889 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_890 = eq(_T_889, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_891 = and(_T_888, _T_890) @[exu_div_ctl.scala 698:95] + node _T_892 = and(_T_886, _T_891) @[exu_div_ctl.scala 699:11] + node _T_893 = or(_T_880, _T_892) @[exu_div_ctl.scala 713:131] + node _T_894 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_895 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_896 = and(_T_894, _T_895) @[exu_div_ctl.scala 697:95] + node _T_897 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_899 = and(_T_896, _T_898) @[exu_div_ctl.scala 699:11] + node _T_900 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 714:82] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[exu_div_ctl.scala 714:77] + node _T_902 = and(_T_899, _T_901) @[exu_div_ctl.scala 714:75] + node _T_903 = or(_T_893, _T_902) @[exu_div_ctl.scala 714:47] + node _T_904 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:75] + node _T_905 = eq(_T_904, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_906 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_907 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_908 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_909 = and(_T_905, _T_906) @[exu_div_ctl.scala 697:95] + node _T_910 = and(_T_909, _T_907) @[exu_div_ctl.scala 697:95] + node _T_911 = and(_T_910, _T_908) @[exu_div_ctl.scala 697:95] + node _T_912 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_913 = eq(_T_912, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_914 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_915 = and(_T_913, _T_914) @[exu_div_ctl.scala 698:95] + node _T_916 = and(_T_911, _T_915) @[exu_div_ctl.scala 699:11] + node _T_917 = or(_T_903, _T_916) @[exu_div_ctl.scala 714:88] + node _T_918 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_919 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_920 = and(_T_918, _T_919) @[exu_div_ctl.scala 697:95] + node _T_921 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_922 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_923 = eq(_T_922, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_924 = and(_T_921, _T_923) @[exu_div_ctl.scala 698:95] + node _T_925 = and(_T_920, _T_924) @[exu_div_ctl.scala 699:11] + node _T_926 = or(_T_917, _T_925) @[exu_div_ctl.scala 714:131] + node _T_927 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_928 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_929 = and(_T_927, _T_928) @[exu_div_ctl.scala 697:95] + node _T_930 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_931 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_932 = eq(_T_931, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_933 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_935 = and(_T_930, _T_932) @[exu_div_ctl.scala 698:95] + node _T_936 = and(_T_935, _T_934) @[exu_div_ctl.scala 698:95] + node _T_937 = and(_T_929, _T_936) @[exu_div_ctl.scala 699:11] + node _T_938 = or(_T_926, _T_937) @[exu_div_ctl.scala 715:47] + node _T_939 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_940 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_941 = and(_T_939, _T_940) @[exu_div_ctl.scala 697:95] + node _T_942 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_943 = eq(_T_942, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_944 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_945 = eq(_T_944, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_946 = and(_T_943, _T_945) @[exu_div_ctl.scala 698:95] + node _T_947 = and(_T_941, _T_946) @[exu_div_ctl.scala 699:11] + node _T_948 = or(_T_938, _T_947) @[exu_div_ctl.scala 715:88] + node _T_949 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_950 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:75] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_952 = and(_T_949, _T_951) @[exu_div_ctl.scala 697:95] + node _T_953 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_955 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:58] + node _T_956 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_957 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 698:58] + node _T_958 = and(_T_954, _T_955) @[exu_div_ctl.scala 698:95] + node _T_959 = and(_T_958, _T_956) @[exu_div_ctl.scala 698:95] + node _T_960 = and(_T_959, _T_957) @[exu_div_ctl.scala 698:95] + node _T_961 = and(_T_952, _T_960) @[exu_div_ctl.scala 699:11] + node _T_962 = or(_T_948, _T_961) @[exu_div_ctl.scala 715:131] + node _T_963 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_964 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_965 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_966 = and(_T_963, _T_964) @[exu_div_ctl.scala 697:95] + node _T_967 = and(_T_966, _T_965) @[exu_div_ctl.scala 697:95] + node _T_968 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_969 = and(_T_967, _T_968) @[exu_div_ctl.scala 699:11] + node _T_970 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 716:84] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[exu_div_ctl.scala 716:79] + node _T_972 = and(_T_969, _T_971) @[exu_div_ctl.scala 716:77] + node _T_973 = or(_T_962, _T_972) @[exu_div_ctl.scala 716:47] + node _T_974 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_975 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_976 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_977 = and(_T_974, _T_975) @[exu_div_ctl.scala 697:95] + node _T_978 = and(_T_977, _T_976) @[exu_div_ctl.scala 697:95] + node _T_979 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_980 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_981 = eq(_T_980, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_982 = and(_T_979, _T_981) @[exu_div_ctl.scala 698:95] + node _T_983 = and(_T_978, _T_982) @[exu_div_ctl.scala 699:11] + node _T_984 = or(_T_973, _T_983) @[exu_div_ctl.scala 716:88] + node _T_985 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_986 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_987 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_988 = and(_T_985, _T_986) @[exu_div_ctl.scala 697:95] + node _T_989 = and(_T_988, _T_987) @[exu_div_ctl.scala 697:95] + node _T_990 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_991 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:75] + node _T_992 = eq(_T_991, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_993 = and(_T_990, _T_992) @[exu_div_ctl.scala 698:95] + node _T_994 = and(_T_989, _T_993) @[exu_div_ctl.scala 699:11] + node _T_995 = or(_T_984, _T_994) @[exu_div_ctl.scala 716:131] + node _T_996 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_997 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:75] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[exu_div_ctl.scala 697:70] + node _T_999 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_1000 = and(_T_996, _T_998) @[exu_div_ctl.scala 697:95] + node _T_1001 = and(_T_1000, _T_999) @[exu_div_ctl.scala 697:95] + node _T_1002 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:75] + node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_1004 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 698:58] + node _T_1005 = and(_T_1003, _T_1004) @[exu_div_ctl.scala 698:95] + node _T_1006 = and(_T_1001, _T_1005) @[exu_div_ctl.scala 699:11] + node _T_1007 = or(_T_995, _T_1006) @[exu_div_ctl.scala 717:47] + node _T_1008 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_1009 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_1010 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_1011 = and(_T_1008, _T_1009) @[exu_div_ctl.scala 697:95] + node _T_1012 = and(_T_1011, _T_1010) @[exu_div_ctl.scala 697:95] + node _T_1013 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_1015 = and(_T_1012, _T_1014) @[exu_div_ctl.scala 699:11] + node _T_1016 = or(_T_1007, _T_1015) @[exu_div_ctl.scala 717:88] + node _T_1017 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_1018 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 697:58] + node _T_1019 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_1020 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 697:58] + node _T_1021 = and(_T_1017, _T_1018) @[exu_div_ctl.scala 697:95] + node _T_1022 = and(_T_1021, _T_1019) @[exu_div_ctl.scala 697:95] + node _T_1023 = and(_T_1022, _T_1020) @[exu_div_ctl.scala 697:95] + node _T_1024 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 698:58] + node _T_1025 = and(_T_1023, _T_1024) @[exu_div_ctl.scala 699:11] + node _T_1026 = or(_T_1016, _T_1025) @[exu_div_ctl.scala 717:131] + node _T_1027 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 697:58] + node _T_1028 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 697:58] + node _T_1029 = and(_T_1027, _T_1028) @[exu_div_ctl.scala 697:95] + node _T_1030 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 698:75] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[exu_div_ctl.scala 698:70] + node _T_1032 = and(_T_1029, _T_1031) @[exu_div_ctl.scala 699:11] + node _T_1033 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 718:81] + node _T_1034 = eq(_T_1033, UInt<1>("h00")) @[exu_div_ctl.scala 718:76] + node _T_1035 = and(_T_1032, _T_1034) @[exu_div_ctl.scala 718:74] + node _T_1036 = or(_T_1026, _T_1035) @[exu_div_ctl.scala 718:47] node _T_1037 = cat(_T_725, _T_1036) @[Cat.scala 29:58] node _T_1038 = cat(_T_591, _T_622) @[Cat.scala 29:58] node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 29:58] - smallnum <= _T_1039 @[exu_div_ctl.scala 698:12] - node _T_1040 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 717:49] + smallnum <= _T_1039 @[exu_div_ctl.scala 701:12] + node _T_1040 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 720:49] node shortq_dividend = cat(dividend_sign_ff, _T_1040) @[Cat.scala 29:58] - inst a_enc of exu_div_cls @[exu_div_ctl.scala 718:21] + inst a_enc of exu_div_cls @[exu_div_ctl.scala 721:21] a_enc.clock <= clock a_enc.reset <= reset - a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 719:20] - inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 721:20] + a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 722:20] + inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 724:20] b_enc.clock <= clock b_enc.reset <= reset - node _T_1041 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 722:27] - b_enc.io.operand <= _T_1041 @[exu_div_ctl.scala 722:20] + node _T_1041 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 725:27] + b_enc.io.operand <= _T_1041 @[exu_div_ctl.scala 725:20] node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58] node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58] node _T_1042 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58] node _T_1043 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58] - node _T_1044 = sub(_T_1042, _T_1043) @[exu_div_ctl.scala 727:42] - node _T_1045 = tail(_T_1044, 1) @[exu_div_ctl.scala 727:42] - node _T_1046 = add(_T_1045, UInt<7>("h01")) @[exu_div_ctl.scala 727:62] - node dw_shortq_raw = tail(_T_1046, 1) @[exu_div_ctl.scala 727:62] - node _T_1047 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 728:33] - node _T_1048 = bits(_T_1047, 0, 0) @[exu_div_ctl.scala 728:43] - node _T_1049 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 728:63] - node shortq = mux(_T_1048, UInt<1>("h00"), _T_1049) @[exu_div_ctl.scala 728:19] - node _T_1050 = bits(shortq, 5, 5) @[exu_div_ctl.scala 729:38] - node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[exu_div_ctl.scala 729:31] - node _T_1052 = and(valid_ff, _T_1051) @[exu_div_ctl.scala 729:29] - node _T_1053 = bits(shortq, 4, 2) @[exu_div_ctl.scala 729:52] - node _T_1054 = eq(_T_1053, UInt<3>("h07")) @[exu_div_ctl.scala 729:58] - node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[exu_div_ctl.scala 729:44] - node _T_1056 = and(_T_1052, _T_1055) @[exu_div_ctl.scala 729:42] - node _T_1057 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 729:75] - node _T_1058 = and(_T_1056, _T_1057) @[exu_div_ctl.scala 729:73] - shortq_enable <= _T_1058 @[exu_div_ctl.scala 729:17] - node _T_1059 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 731:58] - node _T_1060 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 731:58] - node _T_1061 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 731:58] - node _T_1062 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 731:58] - node _T_1063 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 731:58] - node _T_1064 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 731:58] - node _T_1065 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 731:58] - node _T_1066 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 731:58] - node _T_1067 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 731:58] - node _T_1068 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 731:58] - node _T_1069 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 731:58] - node _T_1070 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 731:58] - node _T_1071 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 731:58] - node _T_1072 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 731:58] - node _T_1073 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 731:58] - node _T_1074 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 731:58] - node _T_1075 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 731:58] - node _T_1076 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 731:58] - node _T_1077 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 731:58] - node _T_1078 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 731:58] - node _T_1079 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 731:58] - node _T_1080 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 731:58] - node _T_1081 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 731:58] - node _T_1082 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 731:58] - node _T_1083 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 731:58] - node _T_1084 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 731:58] - node _T_1085 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 731:58] - node _T_1086 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 731:58] - node _T_1087 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 731:58] - node _T_1088 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 731:58] - node _T_1089 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 731:58] - node _T_1090 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 731:58] + node _T_1044 = sub(_T_1042, _T_1043) @[exu_div_ctl.scala 730:42] + node _T_1045 = tail(_T_1044, 1) @[exu_div_ctl.scala 730:42] + node _T_1046 = add(_T_1045, UInt<7>("h01")) @[exu_div_ctl.scala 730:62] + node dw_shortq_raw = tail(_T_1046, 1) @[exu_div_ctl.scala 730:62] + node _T_1047 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 731:33] + node _T_1048 = bits(_T_1047, 0, 0) @[exu_div_ctl.scala 731:43] + node _T_1049 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 731:63] + node shortq = mux(_T_1048, UInt<1>("h00"), _T_1049) @[exu_div_ctl.scala 731:19] + node _T_1050 = bits(shortq, 5, 5) @[exu_div_ctl.scala 732:38] + node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[exu_div_ctl.scala 732:31] + node _T_1052 = and(valid_ff, _T_1051) @[exu_div_ctl.scala 732:29] + node _T_1053 = bits(shortq, 4, 2) @[exu_div_ctl.scala 732:52] + node _T_1054 = eq(_T_1053, UInt<3>("h07")) @[exu_div_ctl.scala 732:58] + node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[exu_div_ctl.scala 732:44] + node _T_1056 = and(_T_1052, _T_1055) @[exu_div_ctl.scala 732:42] + node _T_1057 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 732:75] + node _T_1058 = and(_T_1056, _T_1057) @[exu_div_ctl.scala 732:73] + shortq_enable <= _T_1058 @[exu_div_ctl.scala 732:17] + node _T_1059 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 734:58] + node _T_1060 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 734:58] + node _T_1061 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 734:58] + node _T_1062 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 734:58] + node _T_1063 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 734:58] + node _T_1064 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 734:58] + node _T_1065 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 734:58] + node _T_1066 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 734:58] + node _T_1067 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 734:58] + node _T_1068 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 734:58] + node _T_1069 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 734:58] + node _T_1070 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 734:58] + node _T_1071 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 734:58] + node _T_1072 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 734:58] + node _T_1073 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 734:58] + node _T_1074 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 734:58] + node _T_1075 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 734:58] + node _T_1076 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 734:58] + node _T_1077 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 734:58] + node _T_1078 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 734:58] + node _T_1079 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 734:58] + node _T_1080 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 734:58] + node _T_1081 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 734:58] + node _T_1082 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 734:58] + node _T_1083 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 734:58] + node _T_1084 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 734:58] + node _T_1085 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 734:58] + node _T_1086 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 734:58] + node _T_1087 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 734:58] + node _T_1088 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 734:58] + node _T_1089 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 734:58] + node _T_1090 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 734:58] node _T_1091 = mux(_T_1059, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1092 = mux(_T_1060, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1093 = mux(_T_1061, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -2298,19 +2298,19 @@ circuit exu_div_new_3bit_fullshortq : node _T_1153 = or(_T_1152, _T_1122) @[Mux.scala 27:72] wire _T_1154 : UInt<5> @[Mux.scala 27:72] _T_1154 <= _T_1153 @[Mux.scala 27:72] - shortq_decode <= _T_1154 @[exu_div_ctl.scala 731:17] - node _T_1155 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 732:23] - node _T_1156 = mux(_T_1155, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 732:22] - shortq_shift <= _T_1156 @[exu_div_ctl.scala 732:16] - node _T_1157 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:20] - node _T_1158 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:30] - node _T_1159 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:40] - node _T_1160 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:50] + shortq_decode <= _T_1154 @[exu_div_ctl.scala 734:17] + node _T_1155 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 735:23] + node _T_1156 = mux(_T_1155, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 735:22] + shortq_shift <= _T_1156 @[exu_div_ctl.scala 735:16] + node _T_1157 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 736:20] + node _T_1158 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 736:30] + node _T_1159 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 736:40] + node _T_1160 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 736:50] node _T_1161 = cat(_T_1160, b_ff1) @[Cat.scala 29:58] node _T_1162 = cat(_T_1157, _T_1158) @[Cat.scala 29:58] node _T_1163 = cat(_T_1162, _T_1159) @[Cat.scala 29:58] node _T_1164 = cat(_T_1163, _T_1161) @[Cat.scala 29:58] - b_ff <= _T_1164 @[exu_div_ctl.scala 733:8] + b_ff <= _T_1164 @[exu_div_ctl.scala 736:8] inst rvclkhdr of rvclkhdr @[lib.scala 390:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -2321,7 +2321,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1165 <= valid_ff_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - valid_ff <= _T_1165 @[exu_div_ctl.scala 734:12] + valid_ff <= _T_1165 @[exu_div_ctl.scala 737:12] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -2332,7 +2332,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1166 <= control_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - control_ff <= _T_1166 @[exu_div_ctl.scala 735:16] + control_ff <= _T_1166 @[exu_div_ctl.scala 738:16] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -2343,7 +2343,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1167 <= by_zero_case @[Reg.scala 28:23] skip @[Reg.scala 28:19] - by_zero_case_ff <= _T_1167 @[exu_div_ctl.scala 736:19] + by_zero_case_ff <= _T_1167 @[exu_div_ctl.scala 739:19] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -2354,7 +2354,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1168 <= shortq_enable @[Reg.scala 28:23] skip @[Reg.scala 28:19] - shortq_enable_ff <= _T_1168 @[exu_div_ctl.scala 737:20] + shortq_enable_ff <= _T_1168 @[exu_div_ctl.scala 740:20] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -2365,7 +2365,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1169 <= shortq_shift @[Reg.scala 28:23] skip @[Reg.scala 28:19] - shortq_shift_ff <= _T_1169 @[exu_div_ctl.scala 738:19] + shortq_shift_ff <= _T_1169 @[exu_div_ctl.scala 741:19] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -2376,7 +2376,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1170 <= finish @[Reg.scala 28:23] skip @[Reg.scala 28:19] - finish_ff <= _T_1170 @[exu_div_ctl.scala 739:13] + finish_ff <= _T_1170 @[exu_div_ctl.scala 742:13] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -2387,7 +2387,7 @@ circuit exu_div_new_3bit_fullshortq : when misc_enable : @[Reg.scala 28:19] _T_1171 <= count_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - count_ff <= _T_1171 @[exu_div_ctl.scala 740:12] + count_ff <= _T_1171 @[exu_div_ctl.scala 743:12] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -2398,8 +2398,8 @@ circuit exu_div_new_3bit_fullshortq : when a_enable : @[Reg.scala 28:19] _T_1172 <= a_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - a_ff <= _T_1172 @[exu_div_ctl.scala 742:8] - node _T_1173 = bits(b_in, 32, 0) @[exu_div_ctl.scala 743:23] + a_ff <= _T_1172 @[exu_div_ctl.scala 745:8] + node _T_1173 = bits(b_in, 32, 0) @[exu_div_ctl.scala 746:23] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -2410,7 +2410,7 @@ circuit exu_div_new_3bit_fullshortq : when b_enable : @[Reg.scala 28:19] _T_1174 <= _T_1173 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - b_ff1 <= _T_1174 @[exu_div_ctl.scala 743:9] + b_ff1 <= _T_1174 @[exu_div_ctl.scala 746:9] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -2421,7 +2421,7 @@ circuit exu_div_new_3bit_fullshortq : when rq_enable : @[Reg.scala 28:19] _T_1175 <= r_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - r_ff <= _T_1175 @[exu_div_ctl.scala 744:8] + r_ff <= _T_1175 @[exu_div_ctl.scala 747:8] inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -2432,5 +2432,5 @@ circuit exu_div_new_3bit_fullshortq : when rq_enable : @[Reg.scala 28:19] _T_1176 <= q_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - q_ff <= _T_1176 @[exu_div_ctl.scala 745:8] + q_ff <= _T_1176 @[exu_div_ctl.scala 748:8] diff --git a/exu_div_new_3bit_fullshortq.v b/exu_div_new_3bit_fullshortq.v index 91d7c97a..b2cc56bc 100644 --- a/exu_div_new_3bit_fullshortq.v +++ b/exu_div_new_3bit_fullshortq.v @@ -2,37 +2,37 @@ module exu_div_cls( input [32:0] io_operand, output [4:0] io_cls ); - wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 775:63] - wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 775:63] - wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 775:63] - wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 775:63] - wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 775:63] - wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 775:63] - wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 775:63] - wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 775:63] - wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 775:63] - wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 775:63] - wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 775:63] - wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 775:63] - wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 775:63] - wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 775:63] - wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 775:63] - wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 775:63] - wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 775:63] - wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 775:63] - wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 775:63] - wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 775:63] - wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 775:63] - wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 775:63] - wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 775:63] - wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 775:63] - wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 775:63] - wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 775:63] - wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 775:63] - wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 775:63] - wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 775:63] - wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 775:63] - wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 775:63] + wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 935:63] + wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 935:63] + wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 935:63] + wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 935:63] + wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 935:63] + wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 935:63] + wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 935:63] + wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 935:63] + wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 935:63] + wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 935:63] + wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 935:63] + wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 935:63] + wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 935:63] + wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 935:63] + wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 935:63] + wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 935:63] + wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 935:63] + wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 935:63] + wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 935:63] + wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 935:63] + wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 935:63] + wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 935:63] + wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 935:63] + wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 935:63] + wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 935:63] + wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 935:63] + wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 935:63] + wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 935:63] + wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 935:63] + wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 935:63] + wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 935:63] wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] @@ -97,37 +97,37 @@ module exu_div_cls( wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72] wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72] wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72] - wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 777:25] - wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 778:76] - wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 778:76] - wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 778:76] - wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 778:76] - wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 778:76] - wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 778:76] - wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 778:76] - wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 778:76] - wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 778:76] - wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 778:76] - wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 778:76] - wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 778:76] - wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 778:76] - wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 778:76] - wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 778:76] - wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 778:76] - wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 778:76] - wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 778:76] - wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 778:76] - wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 778:76] - wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 778:76] - wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 778:76] - wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 778:76] - wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 778:76] - wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 778:76] - wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 778:76] - wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 778:76] - wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 778:76] - wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 778:76] - wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 778:76] + wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 937:25] + wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 938:76] + wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 938:76] + wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 938:76] + wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 938:76] + wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 938:76] + wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 938:76] + wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 938:76] + wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 938:76] + wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 938:76] + wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 938:76] + wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 938:76] + wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 938:76] + wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 938:76] + wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 938:76] + wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 938:76] + wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 938:76] + wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 938:76] + wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 938:76] + wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 938:76] + wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 938:76] + wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 938:76] + wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 938:76] + wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 938:76] + wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 938:76] + wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 938:76] + wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 938:76] + wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 938:76] + wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 938:76] + wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 938:76] + wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 938:76] wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] @@ -190,8 +190,8 @@ module exu_div_cls( wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72] wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72] wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72] - wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 777:44] - assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 779:10] + wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 937:44] + assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 939:10] endmodule module rvclkhdr( input io_clk, @@ -237,10 +237,10 @@ module exu_div_new_3bit_fullshortq( reg [63:0] _RAND_9; reg [31:0] _RAND_10; `endif // RANDOMIZE_REG_INIT - wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 718:21] - wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 718:21] - wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 721:20] - wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 721:20] + wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 721:21] + wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 721:21] + wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 724:20] + wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 724:20] wire rvclkhdr_io_clk; // @[lib.scala 390:23] wire rvclkhdr_io_en; // @[lib.scala 390:23] wire rvclkhdr_1_io_clk; // @[lib.scala 390:23] @@ -320,15 +320,15 @@ module exu_div_new_3bit_fullshortq( wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 618:80] wire [6:0] _T_1042 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58] wire [6:0] _T_1043 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58] - wire [6:0] _T_1045 = _T_1042 - _T_1043; // @[exu_div_ctl.scala 727:42] - wire [6:0] dw_shortq_raw = _T_1045 + 7'h1; // @[exu_div_ctl.scala 727:62] - wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 728:19] - wire _T_1051 = ~shortq[5]; // @[exu_div_ctl.scala 729:31] - wire _T_1052 = valid_ff & _T_1051; // @[exu_div_ctl.scala 729:29] - wire _T_1054 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 729:58] - wire _T_1055 = ~_T_1054; // @[exu_div_ctl.scala 729:44] - wire _T_1056 = _T_1052 & _T_1055; // @[exu_div_ctl.scala 729:42] - wire shortq_enable = _T_1056 & _T; // @[exu_div_ctl.scala 729:73] + wire [6:0] _T_1045 = _T_1042 - _T_1043; // @[exu_div_ctl.scala 730:42] + wire [6:0] dw_shortq_raw = _T_1045 + 7'h1; // @[exu_div_ctl.scala 730:62] + wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 731:19] + wire _T_1051 = ~shortq[5]; // @[exu_div_ctl.scala 732:31] + wire _T_1052 = valid_ff & _T_1051; // @[exu_div_ctl.scala 732:29] + wire _T_1054 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 732:58] + wire _T_1055 = ~_T_1054; // @[exu_div_ctl.scala 732:44] + wire _T_1056 = _T_1052 & _T_1055; // @[exu_div_ctl.scala 732:42] + wire shortq_enable = _T_1056 & _T; // @[exu_div_ctl.scala 732:73] wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 618:95] wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 618:93] wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] @@ -360,98 +360,98 @@ module exu_div_new_3bit_fullshortq( reg [32:0] r_ff; // @[Reg.scala 27:20] wire [36:0] _T_164 = {r_ff[32],r_ff,a_ff[32:30]}; // @[Cat.scala 29:58] wire [36:0] _T_166 = {b_ff[34:0],2'h0}; // @[Cat.scala 29:58] - wire [36:0] _T_168 = _T_164 + _T_166; // @[exu_div_ctl.scala 644:58] + wire [36:0] _T_168 = _T_164 + _T_166; // @[exu_div_ctl.scala 647:58] wire [36:0] _T_170 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58] - wire [36:0] _T_172 = _T_168 + _T_170; // @[exu_div_ctl.scala 644:85] - wire [36:0] adder7_out = _T_172 + b_ff; // @[exu_div_ctl.scala 644:107] - wire _T_175 = ~adder7_out[36]; // @[exu_div_ctl.scala 645:24] - wire _T_176 = _T_175 ^ control_ff[2]; // @[exu_div_ctl.scala 645:40] - wire _T_178 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 645:75] - wire _T_179 = adder7_out == 37'h0; // @[exu_div_ctl.scala 645:98] - wire _T_180 = _T_178 & _T_179; // @[exu_div_ctl.scala 645:84] - wire _T_181 = _T_176 | _T_180; // @[exu_div_ctl.scala 645:60] - wire _T_183 = ~_T_172[36]; // @[exu_div_ctl.scala 646:23] - wire _T_184 = _T_183 ^ control_ff[2]; // @[exu_div_ctl.scala 646:39] - wire _T_187 = _T_172 == 37'h0; // @[exu_div_ctl.scala 646:97] - wire _T_188 = _T_178 & _T_187; // @[exu_div_ctl.scala 646:83] - wire _T_189 = _T_184 | _T_188; // @[exu_div_ctl.scala 646:59] - wire [36:0] adder5_out = _T_168 + b_ff; // @[exu_div_ctl.scala 642:85] - wire _T_191 = ~adder5_out[36]; // @[exu_div_ctl.scala 647:23] - wire _T_192 = _T_191 ^ control_ff[2]; // @[exu_div_ctl.scala 647:39] - wire _T_195 = adder5_out == 37'h0; // @[exu_div_ctl.scala 647:97] - wire _T_196 = _T_178 & _T_195; // @[exu_div_ctl.scala 647:83] - wire _T_197 = _T_192 | _T_196; // @[exu_div_ctl.scala 647:59] - wire _T_199 = ~_T_168[36]; // @[exu_div_ctl.scala 648:23] - wire _T_200 = _T_199 ^ control_ff[2]; // @[exu_div_ctl.scala 648:39] - wire _T_203 = _T_168 == 37'h0; // @[exu_div_ctl.scala 648:97] - wire _T_204 = _T_178 & _T_203; // @[exu_div_ctl.scala 648:83] - wire _T_205 = _T_200 | _T_204; // @[exu_div_ctl.scala 648:59] + wire [36:0] _T_172 = _T_168 + _T_170; // @[exu_div_ctl.scala 647:85] + wire [36:0] adder7_out = _T_172 + b_ff; // @[exu_div_ctl.scala 647:107] + wire _T_175 = ~adder7_out[36]; // @[exu_div_ctl.scala 648:24] + wire _T_176 = _T_175 ^ control_ff[2]; // @[exu_div_ctl.scala 648:40] + wire _T_178 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 648:75] + wire _T_179 = adder7_out == 37'h0; // @[exu_div_ctl.scala 648:98] + wire _T_180 = _T_178 & _T_179; // @[exu_div_ctl.scala 648:84] + wire _T_181 = _T_176 | _T_180; // @[exu_div_ctl.scala 648:60] + wire _T_183 = ~_T_172[36]; // @[exu_div_ctl.scala 649:23] + wire _T_184 = _T_183 ^ control_ff[2]; // @[exu_div_ctl.scala 649:39] + wire _T_187 = _T_172 == 37'h0; // @[exu_div_ctl.scala 649:97] + wire _T_188 = _T_178 & _T_187; // @[exu_div_ctl.scala 649:83] + wire _T_189 = _T_184 | _T_188; // @[exu_div_ctl.scala 649:59] + wire [36:0] adder5_out = _T_168 + b_ff; // @[exu_div_ctl.scala 645:85] + wire _T_191 = ~adder5_out[36]; // @[exu_div_ctl.scala 650:23] + wire _T_192 = _T_191 ^ control_ff[2]; // @[exu_div_ctl.scala 650:39] + wire _T_195 = adder5_out == 37'h0; // @[exu_div_ctl.scala 650:97] + wire _T_196 = _T_178 & _T_195; // @[exu_div_ctl.scala 650:83] + wire _T_197 = _T_192 | _T_196; // @[exu_div_ctl.scala 650:59] + wire _T_199 = ~_T_168[36]; // @[exu_div_ctl.scala 651:23] + wire _T_200 = _T_199 ^ control_ff[2]; // @[exu_div_ctl.scala 651:39] + wire _T_203 = _T_168 == 37'h0; // @[exu_div_ctl.scala 651:97] + wire _T_204 = _T_178 & _T_203; // @[exu_div_ctl.scala 651:83] + wire _T_205 = _T_200 | _T_204; // @[exu_div_ctl.scala 651:59] wire [35:0] _T_123 = {r_ff,a_ff[32:30]}; // @[Cat.scala 29:58] wire [35:0] _T_125 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58] - wire [35:0] _T_127 = _T_123 + _T_125; // @[exu_div_ctl.scala 640:49] - wire [35:0] adder3_out = _T_127 + b_ff[35:0]; // @[exu_div_ctl.scala 640:71] - wire _T_207 = ~adder3_out[35]; // @[exu_div_ctl.scala 649:23] - wire _T_208 = _T_207 ^ control_ff[2]; // @[exu_div_ctl.scala 649:39] - wire _T_211 = adder3_out == 36'h0; // @[exu_div_ctl.scala 649:97] - wire _T_212 = _T_178 & _T_211; // @[exu_div_ctl.scala 649:83] - wire _T_213 = _T_208 | _T_212; // @[exu_div_ctl.scala 649:59] + wire [35:0] _T_127 = _T_123 + _T_125; // @[exu_div_ctl.scala 643:49] + wire [35:0] adder3_out = _T_127 + b_ff[35:0]; // @[exu_div_ctl.scala 643:71] + wire _T_207 = ~adder3_out[35]; // @[exu_div_ctl.scala 652:23] + wire _T_208 = _T_207 ^ control_ff[2]; // @[exu_div_ctl.scala 652:39] + wire _T_211 = adder3_out == 36'h0; // @[exu_div_ctl.scala 652:97] + wire _T_212 = _T_178 & _T_211; // @[exu_div_ctl.scala 652:83] + wire _T_213 = _T_208 | _T_212; // @[exu_div_ctl.scala 652:59] wire [34:0] _T_117 = {r_ff[31:0],a_ff[32:30]}; // @[Cat.scala 29:58] wire [34:0] _T_119 = {b_ff[33:0],1'h0}; // @[Cat.scala 29:58] - wire [34:0] adder2_out = _T_117 + _T_119; // @[exu_div_ctl.scala 639:49] - wire _T_215 = ~adder2_out[34]; // @[exu_div_ctl.scala 650:23] - wire _T_216 = _T_215 ^ control_ff[2]; // @[exu_div_ctl.scala 650:39] - wire _T_219 = adder2_out == 35'h0; // @[exu_div_ctl.scala 650:97] - wire _T_220 = _T_178 & _T_219; // @[exu_div_ctl.scala 650:83] - wire _T_221 = _T_216 | _T_220; // @[exu_div_ctl.scala 650:59] + wire [34:0] adder2_out = _T_117 + _T_119; // @[exu_div_ctl.scala 642:49] + wire _T_215 = ~adder2_out[34]; // @[exu_div_ctl.scala 653:23] + wire _T_216 = _T_215 ^ control_ff[2]; // @[exu_div_ctl.scala 653:39] + wire _T_219 = adder2_out == 35'h0; // @[exu_div_ctl.scala 653:97] + wire _T_220 = _T_178 & _T_219; // @[exu_div_ctl.scala 653:83] + wire _T_221 = _T_216 | _T_220; // @[exu_div_ctl.scala 653:59] wire [33:0] _T_112 = {r_ff[30:0],a_ff[32:30]}; // @[Cat.scala 29:58] - wire [33:0] adder1_out = _T_112 + b_ff[33:0]; // @[exu_div_ctl.scala 638:49] - wire _T_223 = ~adder1_out[33]; // @[exu_div_ctl.scala 651:23] - wire _T_224 = _T_223 ^ control_ff[2]; // @[exu_div_ctl.scala 651:39] - wire _T_227 = adder1_out == 34'h0; // @[exu_div_ctl.scala 651:97] - wire _T_228 = _T_178 & _T_227; // @[exu_div_ctl.scala 651:83] - wire _T_229 = _T_224 | _T_228; // @[exu_div_ctl.scala 651:59] + wire [33:0] adder1_out = _T_112 + b_ff[33:0]; // @[exu_div_ctl.scala 641:49] + wire _T_223 = ~adder1_out[33]; // @[exu_div_ctl.scala 654:23] + wire _T_224 = _T_223 ^ control_ff[2]; // @[exu_div_ctl.scala 654:39] + wire _T_227 = adder1_out == 34'h0; // @[exu_div_ctl.scala 654:97] + wire _T_228 = _T_178 & _T_227; // @[exu_div_ctl.scala 654:83] + wire _T_229 = _T_224 | _T_228; // @[exu_div_ctl.scala 654:59] wire [7:0] quotient_raw = {_T_181,_T_189,_T_197,_T_205,_T_213,_T_221,_T_229,1'h0}; // @[Cat.scala 29:58] - wire _T_239 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 652:43] - wire _T_241 = _T_239 | quotient_raw[5]; // @[exu_div_ctl.scala 652:62] - wire _T_243 = _T_241 | quotient_raw[4]; // @[exu_div_ctl.scala 652:80] - wire _T_248 = ~quotient_raw[4]; // @[exu_div_ctl.scala 653:63] - wire _T_250 = _T_248 & quotient_raw[3]; // @[exu_div_ctl.scala 653:80] - wire _T_251 = _T_239 | _T_250; // @[exu_div_ctl.scala 653:61] - wire _T_253 = ~quotient_raw[3]; // @[exu_div_ctl.scala 653:101] - wire _T_255 = _T_253 & quotient_raw[2]; // @[exu_div_ctl.scala 653:118] - wire _T_256 = _T_251 | _T_255; // @[exu_div_ctl.scala 653:99] - wire _T_259 = ~quotient_raw[6]; // @[exu_div_ctl.scala 654:46] - wire _T_261 = _T_259 & quotient_raw[5]; // @[exu_div_ctl.scala 654:63] - wire _T_262 = quotient_raw[7] | _T_261; // @[exu_div_ctl.scala 654:42] - wire _T_267 = _T_262 | _T_250; // @[exu_div_ctl.scala 654:82] - wire _T_269 = ~quotient_raw[2]; // @[exu_div_ctl.scala 654:123] - wire _T_271 = _T_269 & quotient_raw[1]; // @[exu_div_ctl.scala 654:140] - wire _T_272 = _T_267 | _T_271; // @[exu_div_ctl.scala 654:121] + wire _T_239 = quotient_raw[7] | quotient_raw[6]; // @[exu_div_ctl.scala 655:43] + wire _T_241 = _T_239 | quotient_raw[5]; // @[exu_div_ctl.scala 655:62] + wire _T_243 = _T_241 | quotient_raw[4]; // @[exu_div_ctl.scala 655:80] + wire _T_248 = ~quotient_raw[4]; // @[exu_div_ctl.scala 656:63] + wire _T_250 = _T_248 & quotient_raw[3]; // @[exu_div_ctl.scala 656:80] + wire _T_251 = _T_239 | _T_250; // @[exu_div_ctl.scala 656:61] + wire _T_253 = ~quotient_raw[3]; // @[exu_div_ctl.scala 656:101] + wire _T_255 = _T_253 & quotient_raw[2]; // @[exu_div_ctl.scala 656:118] + wire _T_256 = _T_251 | _T_255; // @[exu_div_ctl.scala 656:99] + wire _T_259 = ~quotient_raw[6]; // @[exu_div_ctl.scala 657:46] + wire _T_261 = _T_259 & quotient_raw[5]; // @[exu_div_ctl.scala 657:63] + wire _T_262 = quotient_raw[7] | _T_261; // @[exu_div_ctl.scala 657:42] + wire _T_267 = _T_262 | _T_250; // @[exu_div_ctl.scala 657:82] + wire _T_269 = ~quotient_raw[2]; // @[exu_div_ctl.scala 657:123] + wire _T_271 = _T_269 & quotient_raw[1]; // @[exu_div_ctl.scala 657:140] + wire _T_272 = _T_267 | _T_271; // @[exu_div_ctl.scala 657:121] wire [2:0] quotient_new = {_T_243,_T_256,_T_272}; // @[Cat.scala 29:58] - wire _T_86 = quotient_new == 3'h0; // @[exu_div_ctl.scala 629:61] - wire _T_87 = running_state & _T_86; // @[exu_div_ctl.scala 629:45] - wire r_restore_sel = _T_87 & _T_67; // @[exu_div_ctl.scala 629:70] - wire _T_89 = quotient_new == 3'h1; // @[exu_div_ctl.scala 630:61] - wire _T_90 = running_state & _T_89; // @[exu_div_ctl.scala 630:45] - wire r_adder1_sel = _T_90 & _T_67; // @[exu_div_ctl.scala 630:70] - wire _T_92 = quotient_new == 3'h2; // @[exu_div_ctl.scala 631:61] - wire _T_93 = running_state & _T_92; // @[exu_div_ctl.scala 631:45] - wire r_adder2_sel = _T_93 & _T_67; // @[exu_div_ctl.scala 631:70] - wire _T_95 = quotient_new == 3'h3; // @[exu_div_ctl.scala 632:61] - wire _T_96 = running_state & _T_95; // @[exu_div_ctl.scala 632:45] - wire r_adder3_sel = _T_96 & _T_67; // @[exu_div_ctl.scala 632:70] - wire _T_98 = quotient_new == 3'h4; // @[exu_div_ctl.scala 633:61] - wire _T_99 = running_state & _T_98; // @[exu_div_ctl.scala 633:45] - wire r_adder4_sel = _T_99 & _T_67; // @[exu_div_ctl.scala 633:70] - wire _T_101 = quotient_new == 3'h5; // @[exu_div_ctl.scala 634:61] - wire _T_102 = running_state & _T_101; // @[exu_div_ctl.scala 634:45] - wire r_adder5_sel = _T_102 & _T_67; // @[exu_div_ctl.scala 634:70] - wire _T_104 = quotient_new == 3'h6; // @[exu_div_ctl.scala 635:61] - wire _T_105 = running_state & _T_104; // @[exu_div_ctl.scala 635:45] - wire r_adder6_sel = _T_105 & _T_67; // @[exu_div_ctl.scala 635:70] - wire _T_107 = quotient_new == 3'h7; // @[exu_div_ctl.scala 636:61] - wire _T_108 = running_state & _T_107; // @[exu_div_ctl.scala 636:45] - wire r_adder7_sel = _T_108 & _T_67; // @[exu_div_ctl.scala 636:70] + wire _T_86 = quotient_new == 3'h0; // @[exu_div_ctl.scala 630:70] + wire _T_87 = running_state & _T_86; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_0 = _T_87 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_89 = quotient_new == 3'h1; // @[exu_div_ctl.scala 630:70] + wire _T_90 = running_state & _T_89; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_1 = _T_90 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_92 = quotient_new == 3'h2; // @[exu_div_ctl.scala 630:70] + wire _T_93 = running_state & _T_92; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_2 = _T_93 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_95 = quotient_new == 3'h3; // @[exu_div_ctl.scala 630:70] + wire _T_96 = running_state & _T_95; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_3 = _T_96 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_98 = quotient_new == 3'h4; // @[exu_div_ctl.scala 630:70] + wire _T_99 = running_state & _T_98; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_4 = _T_99 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_101 = quotient_new == 3'h5; // @[exu_div_ctl.scala 630:70] + wire _T_102 = running_state & _T_101; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_5 = _T_102 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_104 = quotient_new == 3'h6; // @[exu_div_ctl.scala 630:70] + wire _T_105 = running_state & _T_104; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_6 = _T_105 & _T_67; // @[exu_div_ctl.scala 630:84] + wire _T_107 = quotient_new == 3'h7; // @[exu_div_ctl.scala 630:70] + wire _T_108 = running_state & _T_107; // @[exu_div_ctl.scala 630:54] + wire r_adder_sel_7 = _T_108 & _T_67; // @[exu_div_ctl.scala 630:84] reg [31:0] q_ff; // @[Reg.scala 27:20] wire [31:0] _T_276 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_277 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72] @@ -554,9 +554,9 @@ module exu_div_new_3bit_fullshortq( wire [7:0] _T_486 = {_T_417,_T_411,_T_405,_T_399,_T_393,_T_387,_T_381,_T_375}; // @[lib.scala 430:14] wire [30:0] _T_495 = {_T_465,_T_459,_T_453,_T_447,_T_441,_T_435,_T_429,_T_423,_T_486,_T_479}; // @[lib.scala 430:14] wire [31:0] twos_comp_out = {_T_495,twos_comp_in[0]}; // @[Cat.scala 29:58] - wire _T_497 = ~a_shift; // @[exu_div_ctl.scala 661:6] - wire _T_499 = _T_497 & _T_67; // @[exu_div_ctl.scala 661:15] - wire _T_502 = io_signed_in & io_dividend_in[31]; // @[exu_div_ctl.scala 661:63] + wire _T_497 = ~a_shift; // @[exu_div_ctl.scala 664:6] + wire _T_499 = _T_497 & _T_67; // @[exu_div_ctl.scala 664:15] + wire _T_502 = io_signed_in & io_dividend_in[31]; // @[exu_div_ctl.scala 664:63] wire [32:0] _T_504 = {_T_502,io_dividend_in}; // @[Cat.scala 29:58] wire [32:0] _T_506 = {a_ff[29:0],3'h0}; // @[Cat.scala 29:58] wire [65:0] ar_shifted = _T_72[65:0]; // @[exu_div_ctl.scala 622:28] @@ -565,10 +565,10 @@ module exu_div_new_3bit_fullshortq( wire [32:0] _T_510 = shortq_enable_ff ? ar_shifted[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_511 = _T_508 | _T_509; // @[Mux.scala 27:72] wire [32:0] a_in = _T_511 | _T_510; // @[Mux.scala 27:72] - wire _T_513 = ~b_twos_comp; // @[exu_div_ctl.scala 666:5] - wire _T_515 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 666:63] + wire _T_513 = ~b_twos_comp; // @[exu_div_ctl.scala 669:5] + wire _T_515 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 669:63] wire [32:0] _T_517 = {_T_515,io_divisor_in}; // @[Cat.scala 29:58] - wire _T_518 = ~control_ff[1]; // @[exu_div_ctl.scala 667:50] + wire _T_518 = ~control_ff[1]; // @[exu_div_ctl.scala 670:50] wire [32:0] _T_520 = {_T_518,_T_495,twos_comp_in[0]}; // @[Cat.scala 29:58] wire [32:0] _T_521 = _T_513 ? _T_517 : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_522 = b_twos_comp ? _T_520 : 33'h0; // @[Mux.scala 27:72] @@ -576,14 +576,14 @@ module exu_div_new_3bit_fullshortq( wire [32:0] _T_527 = {r_ff[29:0],a_ff[32:30]}; // @[Cat.scala 29:58] wire [32:0] _T_537 = {1'h0,a_ff[31:0]}; // @[Cat.scala 29:58] wire [32:0] _T_538 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_539 = r_restore_sel ? _T_527 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_540 = r_adder1_sel ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_541 = r_adder2_sel ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_542 = r_adder3_sel ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_543 = r_adder4_sel ? _T_168[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_544 = r_adder5_sel ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_545 = r_adder6_sel ? _T_172[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_546 = r_adder7_sel ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_539 = r_adder_sel_0 ? _T_527 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_540 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_541 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_542 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_543 = r_adder_sel_4 ? _T_168[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_544 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_545 = r_adder_sel_6 ? _T_172[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_546 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_547 = shortq_enable_ff ? ar_shifted[65:33] : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_548 = by_zero_case ? _T_537 : 33'h0; // @[Mux.scala 27:72] wire [32:0] _T_549 = _T_538 | _T_539; // @[Mux.scala 27:72] @@ -597,175 +597,175 @@ module exu_div_new_3bit_fullshortq( wire [32:0] _T_557 = _T_556 | _T_547; // @[Mux.scala 27:72] wire [32:0] r_in = _T_557 | _T_548; // @[Mux.scala 27:72] wire [31:0] _T_561 = {q_ff[28:0],_T_243,_T_256,_T_272}; // @[Cat.scala 29:58] - wire _T_584 = ~b_ff[3]; // @[exu_div_ctl.scala 695:70] - wire _T_586 = ~b_ff[2]; // @[exu_div_ctl.scala 695:70] - wire _T_589 = _T_584 & _T_586; // @[exu_div_ctl.scala 695:95] - wire _T_588 = ~b_ff[1]; // @[exu_div_ctl.scala 695:70] - wire _T_590 = _T_589 & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_591 = a_ff[3] & _T_590; // @[exu_div_ctl.scala 696:11] - wire _T_598 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_600 = ~b_ff[0]; // @[exu_div_ctl.scala 701:33] - wire _T_601 = _T_598 & _T_600; // @[exu_div_ctl.scala 701:31] - wire _T_611 = a_ff[2] & _T_590; // @[exu_div_ctl.scala 696:11] - wire _T_612 = _T_601 | _T_611; // @[exu_div_ctl.scala 701:42] - wire _T_615 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 694:95] - wire _T_621 = _T_615 & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_622 = _T_612 | _T_621; // @[exu_div_ctl.scala 701:75] - wire _T_629 = a_ff[2] & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_632 = _T_629 & _T_600; // @[exu_div_ctl.scala 703:31] - wire _T_642 = a_ff[1] & _T_590; // @[exu_div_ctl.scala 696:11] - wire _T_643 = _T_632 | _T_642; // @[exu_div_ctl.scala 703:42] - wire _T_649 = _T_584 & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_650 = a_ff[3] & _T_649; // @[exu_div_ctl.scala 696:11] - wire _T_653 = _T_650 & _T_600; // @[exu_div_ctl.scala 703:106] - wire _T_654 = _T_643 | _T_653; // @[exu_div_ctl.scala 703:78] - wire _T_657 = ~a_ff[2]; // @[exu_div_ctl.scala 694:70] - wire _T_658 = a_ff[3] & _T_657; // @[exu_div_ctl.scala 694:95] - wire _T_666 = _T_589 & b_ff[1]; // @[exu_div_ctl.scala 695:95] - wire _T_667 = _T_666 & b_ff[0]; // @[exu_div_ctl.scala 695:95] - wire _T_668 = _T_658 & _T_667; // @[exu_div_ctl.scala 696:11] - wire _T_669 = _T_654 | _T_668; // @[exu_div_ctl.scala 703:117] - wire _T_671 = ~a_ff[3]; // @[exu_div_ctl.scala 694:70] - wire _T_674 = _T_671 & a_ff[2]; // @[exu_div_ctl.scala 694:95] - wire _T_675 = _T_674 & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_681 = _T_675 & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_682 = _T_669 | _T_681; // @[exu_div_ctl.scala 704:44] - wire _T_688 = _T_615 & _T_584; // @[exu_div_ctl.scala 696:11] - wire _T_691 = _T_688 & _T_600; // @[exu_div_ctl.scala 704:107] - wire _T_692 = _T_682 | _T_691; // @[exu_div_ctl.scala 704:80] - wire _T_701 = _T_584 & b_ff[2]; // @[exu_div_ctl.scala 695:95] - wire _T_702 = _T_701 & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_703 = _T_615 & _T_702; // @[exu_div_ctl.scala 696:11] - wire _T_704 = _T_692 | _T_703; // @[exu_div_ctl.scala 704:119] - wire _T_707 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_713 = _T_707 & _T_649; // @[exu_div_ctl.scala 696:11] - wire _T_714 = _T_704 | _T_713; // @[exu_div_ctl.scala 705:44] - wire _T_719 = _T_615 & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_724 = _T_719 & _T_701; // @[exu_div_ctl.scala 696:11] - wire _T_725 = _T_714 | _T_724; // @[exu_div_ctl.scala 705:79] - wire _T_729 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_730 = _T_729 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_736 = _T_730 & _T_649; // @[exu_div_ctl.scala 696:11] - wire _T_742 = _T_658 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_747 = _T_584 & b_ff[1]; // @[exu_div_ctl.scala 695:95] - wire _T_748 = _T_747 & b_ff[0]; // @[exu_div_ctl.scala 695:95] - wire _T_749 = _T_742 & _T_748; // @[exu_div_ctl.scala 696:11] - wire _T_750 = _T_736 | _T_749; // @[exu_div_ctl.scala 707:45] - wire _T_757 = a_ff[2] & _T_649; // @[exu_div_ctl.scala 696:11] - wire _T_760 = _T_757 & _T_600; // @[exu_div_ctl.scala 707:114] - wire _T_761 = _T_750 | _T_760; // @[exu_div_ctl.scala 707:86] - wire _T_768 = a_ff[1] & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_771 = _T_768 & _T_600; // @[exu_div_ctl.scala 708:33] - wire _T_772 = _T_761 | _T_771; // @[exu_div_ctl.scala 707:129] - wire _T_782 = a_ff[0] & _T_590; // @[exu_div_ctl.scala 696:11] - wire _T_783 = _T_772 | _T_782; // @[exu_div_ctl.scala 708:47] - wire _T_788 = ~a_ff[1]; // @[exu_div_ctl.scala 694:70] - wire _T_790 = _T_674 & _T_788; // @[exu_div_ctl.scala 694:95] - wire _T_800 = _T_790 & _T_667; // @[exu_div_ctl.scala 696:11] - wire _T_801 = _T_783 | _T_800; // @[exu_div_ctl.scala 708:88] - wire _T_810 = _T_675 & _T_584; // @[exu_div_ctl.scala 696:11] - wire _T_813 = _T_810 & _T_600; // @[exu_div_ctl.scala 709:36] - wire _T_814 = _T_801 | _T_813; // @[exu_div_ctl.scala 708:131] - wire _T_820 = _T_586 & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_821 = a_ff[3] & _T_820; // @[exu_div_ctl.scala 696:11] - wire _T_824 = _T_821 & _T_600; // @[exu_div_ctl.scala 709:76] - wire _T_825 = _T_814 | _T_824; // @[exu_div_ctl.scala 709:47] - wire _T_835 = _T_701 & b_ff[1]; // @[exu_div_ctl.scala 695:95] - wire _T_836 = _T_658 & _T_835; // @[exu_div_ctl.scala 696:11] - wire _T_837 = _T_825 | _T_836; // @[exu_div_ctl.scala 709:88] - wire _T_851 = _T_675 & _T_702; // @[exu_div_ctl.scala 696:11] - wire _T_852 = _T_837 | _T_851; // @[exu_div_ctl.scala 709:131] - wire _T_858 = _T_674 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_864 = _T_858 & _T_649; // @[exu_div_ctl.scala 696:11] - wire _T_865 = _T_852 | _T_864; // @[exu_div_ctl.scala 710:47] - wire _T_872 = _T_658 & _T_788; // @[exu_div_ctl.scala 694:95] - wire _T_878 = _T_701 & b_ff[0]; // @[exu_div_ctl.scala 695:95] - wire _T_879 = _T_872 & _T_878; // @[exu_div_ctl.scala 696:11] - wire _T_880 = _T_865 | _T_879; // @[exu_div_ctl.scala 710:88] - wire _T_885 = _T_657 & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_886 = _T_885 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_892 = _T_886 & _T_589; // @[exu_div_ctl.scala 696:11] - wire _T_893 = _T_880 | _T_892; // @[exu_div_ctl.scala 710:131] - wire _T_899 = _T_615 & _T_588; // @[exu_div_ctl.scala 696:11] - wire _T_902 = _T_899 & _T_600; // @[exu_div_ctl.scala 711:75] - wire _T_903 = _T_893 | _T_902; // @[exu_div_ctl.scala 711:47] - wire _T_911 = _T_675 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_916 = _T_911 & _T_701; // @[exu_div_ctl.scala 696:11] - wire _T_917 = _T_903 | _T_916; // @[exu_div_ctl.scala 711:88] - wire _T_924 = b_ff[3] & _T_586; // @[exu_div_ctl.scala 695:95] - wire _T_925 = _T_615 & _T_924; // @[exu_div_ctl.scala 696:11] - wire _T_926 = _T_917 | _T_925; // @[exu_div_ctl.scala 711:131] - wire _T_936 = _T_924 & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_937 = _T_707 & _T_936; // @[exu_div_ctl.scala 696:11] - wire _T_938 = _T_926 | _T_937; // @[exu_div_ctl.scala 712:47] - wire _T_941 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_947 = _T_941 & _T_820; // @[exu_div_ctl.scala 696:11] - wire _T_948 = _T_938 | _T_947; // @[exu_div_ctl.scala 712:88] - wire _T_952 = a_ff[3] & _T_788; // @[exu_div_ctl.scala 694:95] - wire _T_960 = _T_835 & b_ff[0]; // @[exu_div_ctl.scala 695:95] - wire _T_961 = _T_952 & _T_960; // @[exu_div_ctl.scala 696:11] - wire _T_962 = _T_948 | _T_961; // @[exu_div_ctl.scala 712:131] - wire _T_969 = _T_719 & b_ff[3]; // @[exu_div_ctl.scala 696:11] - wire _T_972 = _T_969 & _T_600; // @[exu_div_ctl.scala 713:77] - wire _T_973 = _T_962 | _T_972; // @[exu_div_ctl.scala 713:47] - wire _T_982 = b_ff[3] & _T_588; // @[exu_div_ctl.scala 695:95] - wire _T_983 = _T_719 & _T_982; // @[exu_div_ctl.scala 696:11] - wire _T_984 = _T_973 | _T_983; // @[exu_div_ctl.scala 713:88] - wire _T_989 = _T_615 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_994 = _T_989 & _T_982; // @[exu_div_ctl.scala 696:11] - wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 713:131] - wire _T_1001 = _T_658 & a_ff[1]; // @[exu_div_ctl.scala 694:95] - wire _T_1006 = _T_1001 & _T_747; // @[exu_div_ctl.scala 696:11] - wire _T_1007 = _T_995 | _T_1006; // @[exu_div_ctl.scala 714:47] - wire _T_1012 = _T_707 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_1015 = _T_1012 & _T_586; // @[exu_div_ctl.scala 696:11] - wire _T_1016 = _T_1007 | _T_1015; // @[exu_div_ctl.scala 714:88] - wire _T_1023 = _T_719 & a_ff[0]; // @[exu_div_ctl.scala 694:95] - wire _T_1025 = _T_1023 & b_ff[3]; // @[exu_div_ctl.scala 696:11] - wire _T_1026 = _T_1016 | _T_1025; // @[exu_div_ctl.scala 714:131] - wire _T_1032 = _T_707 & _T_586; // @[exu_div_ctl.scala 696:11] - wire _T_1035 = _T_1032 & _T_600; // @[exu_div_ctl.scala 715:74] - wire _T_1036 = _T_1026 | _T_1035; // @[exu_div_ctl.scala 715:47] + wire _T_584 = ~b_ff[3]; // @[exu_div_ctl.scala 698:70] + wire _T_586 = ~b_ff[2]; // @[exu_div_ctl.scala 698:70] + wire _T_589 = _T_584 & _T_586; // @[exu_div_ctl.scala 698:95] + wire _T_588 = ~b_ff[1]; // @[exu_div_ctl.scala 698:70] + wire _T_590 = _T_589 & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_591 = a_ff[3] & _T_590; // @[exu_div_ctl.scala 699:11] + wire _T_598 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_600 = ~b_ff[0]; // @[exu_div_ctl.scala 704:33] + wire _T_601 = _T_598 & _T_600; // @[exu_div_ctl.scala 704:31] + wire _T_611 = a_ff[2] & _T_590; // @[exu_div_ctl.scala 699:11] + wire _T_612 = _T_601 | _T_611; // @[exu_div_ctl.scala 704:42] + wire _T_615 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 697:95] + wire _T_621 = _T_615 & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_622 = _T_612 | _T_621; // @[exu_div_ctl.scala 704:75] + wire _T_629 = a_ff[2] & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_632 = _T_629 & _T_600; // @[exu_div_ctl.scala 706:31] + wire _T_642 = a_ff[1] & _T_590; // @[exu_div_ctl.scala 699:11] + wire _T_643 = _T_632 | _T_642; // @[exu_div_ctl.scala 706:42] + wire _T_649 = _T_584 & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_650 = a_ff[3] & _T_649; // @[exu_div_ctl.scala 699:11] + wire _T_653 = _T_650 & _T_600; // @[exu_div_ctl.scala 706:106] + wire _T_654 = _T_643 | _T_653; // @[exu_div_ctl.scala 706:78] + wire _T_657 = ~a_ff[2]; // @[exu_div_ctl.scala 697:70] + wire _T_658 = a_ff[3] & _T_657; // @[exu_div_ctl.scala 697:95] + wire _T_666 = _T_589 & b_ff[1]; // @[exu_div_ctl.scala 698:95] + wire _T_667 = _T_666 & b_ff[0]; // @[exu_div_ctl.scala 698:95] + wire _T_668 = _T_658 & _T_667; // @[exu_div_ctl.scala 699:11] + wire _T_669 = _T_654 | _T_668; // @[exu_div_ctl.scala 706:117] + wire _T_671 = ~a_ff[3]; // @[exu_div_ctl.scala 697:70] + wire _T_674 = _T_671 & a_ff[2]; // @[exu_div_ctl.scala 697:95] + wire _T_675 = _T_674 & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_681 = _T_675 & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_682 = _T_669 | _T_681; // @[exu_div_ctl.scala 707:44] + wire _T_688 = _T_615 & _T_584; // @[exu_div_ctl.scala 699:11] + wire _T_691 = _T_688 & _T_600; // @[exu_div_ctl.scala 707:107] + wire _T_692 = _T_682 | _T_691; // @[exu_div_ctl.scala 707:80] + wire _T_701 = _T_584 & b_ff[2]; // @[exu_div_ctl.scala 698:95] + wire _T_702 = _T_701 & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_703 = _T_615 & _T_702; // @[exu_div_ctl.scala 699:11] + wire _T_704 = _T_692 | _T_703; // @[exu_div_ctl.scala 707:119] + wire _T_707 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_713 = _T_707 & _T_649; // @[exu_div_ctl.scala 699:11] + wire _T_714 = _T_704 | _T_713; // @[exu_div_ctl.scala 708:44] + wire _T_719 = _T_615 & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_724 = _T_719 & _T_701; // @[exu_div_ctl.scala 699:11] + wire _T_725 = _T_714 | _T_724; // @[exu_div_ctl.scala 708:79] + wire _T_729 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_730 = _T_729 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_736 = _T_730 & _T_649; // @[exu_div_ctl.scala 699:11] + wire _T_742 = _T_658 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_747 = _T_584 & b_ff[1]; // @[exu_div_ctl.scala 698:95] + wire _T_748 = _T_747 & b_ff[0]; // @[exu_div_ctl.scala 698:95] + wire _T_749 = _T_742 & _T_748; // @[exu_div_ctl.scala 699:11] + wire _T_750 = _T_736 | _T_749; // @[exu_div_ctl.scala 710:45] + wire _T_757 = a_ff[2] & _T_649; // @[exu_div_ctl.scala 699:11] + wire _T_760 = _T_757 & _T_600; // @[exu_div_ctl.scala 710:114] + wire _T_761 = _T_750 | _T_760; // @[exu_div_ctl.scala 710:86] + wire _T_768 = a_ff[1] & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_771 = _T_768 & _T_600; // @[exu_div_ctl.scala 711:33] + wire _T_772 = _T_761 | _T_771; // @[exu_div_ctl.scala 710:129] + wire _T_782 = a_ff[0] & _T_590; // @[exu_div_ctl.scala 699:11] + wire _T_783 = _T_772 | _T_782; // @[exu_div_ctl.scala 711:47] + wire _T_788 = ~a_ff[1]; // @[exu_div_ctl.scala 697:70] + wire _T_790 = _T_674 & _T_788; // @[exu_div_ctl.scala 697:95] + wire _T_800 = _T_790 & _T_667; // @[exu_div_ctl.scala 699:11] + wire _T_801 = _T_783 | _T_800; // @[exu_div_ctl.scala 711:88] + wire _T_810 = _T_675 & _T_584; // @[exu_div_ctl.scala 699:11] + wire _T_813 = _T_810 & _T_600; // @[exu_div_ctl.scala 712:36] + wire _T_814 = _T_801 | _T_813; // @[exu_div_ctl.scala 711:131] + wire _T_820 = _T_586 & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_821 = a_ff[3] & _T_820; // @[exu_div_ctl.scala 699:11] + wire _T_824 = _T_821 & _T_600; // @[exu_div_ctl.scala 712:76] + wire _T_825 = _T_814 | _T_824; // @[exu_div_ctl.scala 712:47] + wire _T_835 = _T_701 & b_ff[1]; // @[exu_div_ctl.scala 698:95] + wire _T_836 = _T_658 & _T_835; // @[exu_div_ctl.scala 699:11] + wire _T_837 = _T_825 | _T_836; // @[exu_div_ctl.scala 712:88] + wire _T_851 = _T_675 & _T_702; // @[exu_div_ctl.scala 699:11] + wire _T_852 = _T_837 | _T_851; // @[exu_div_ctl.scala 712:131] + wire _T_858 = _T_674 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_864 = _T_858 & _T_649; // @[exu_div_ctl.scala 699:11] + wire _T_865 = _T_852 | _T_864; // @[exu_div_ctl.scala 713:47] + wire _T_872 = _T_658 & _T_788; // @[exu_div_ctl.scala 697:95] + wire _T_878 = _T_701 & b_ff[0]; // @[exu_div_ctl.scala 698:95] + wire _T_879 = _T_872 & _T_878; // @[exu_div_ctl.scala 699:11] + wire _T_880 = _T_865 | _T_879; // @[exu_div_ctl.scala 713:88] + wire _T_885 = _T_657 & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_886 = _T_885 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_892 = _T_886 & _T_589; // @[exu_div_ctl.scala 699:11] + wire _T_893 = _T_880 | _T_892; // @[exu_div_ctl.scala 713:131] + wire _T_899 = _T_615 & _T_588; // @[exu_div_ctl.scala 699:11] + wire _T_902 = _T_899 & _T_600; // @[exu_div_ctl.scala 714:75] + wire _T_903 = _T_893 | _T_902; // @[exu_div_ctl.scala 714:47] + wire _T_911 = _T_675 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_916 = _T_911 & _T_701; // @[exu_div_ctl.scala 699:11] + wire _T_917 = _T_903 | _T_916; // @[exu_div_ctl.scala 714:88] + wire _T_924 = b_ff[3] & _T_586; // @[exu_div_ctl.scala 698:95] + wire _T_925 = _T_615 & _T_924; // @[exu_div_ctl.scala 699:11] + wire _T_926 = _T_917 | _T_925; // @[exu_div_ctl.scala 714:131] + wire _T_936 = _T_924 & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_937 = _T_707 & _T_936; // @[exu_div_ctl.scala 699:11] + wire _T_938 = _T_926 | _T_937; // @[exu_div_ctl.scala 715:47] + wire _T_941 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_947 = _T_941 & _T_820; // @[exu_div_ctl.scala 699:11] + wire _T_948 = _T_938 | _T_947; // @[exu_div_ctl.scala 715:88] + wire _T_952 = a_ff[3] & _T_788; // @[exu_div_ctl.scala 697:95] + wire _T_960 = _T_835 & b_ff[0]; // @[exu_div_ctl.scala 698:95] + wire _T_961 = _T_952 & _T_960; // @[exu_div_ctl.scala 699:11] + wire _T_962 = _T_948 | _T_961; // @[exu_div_ctl.scala 715:131] + wire _T_969 = _T_719 & b_ff[3]; // @[exu_div_ctl.scala 699:11] + wire _T_972 = _T_969 & _T_600; // @[exu_div_ctl.scala 716:77] + wire _T_973 = _T_962 | _T_972; // @[exu_div_ctl.scala 716:47] + wire _T_982 = b_ff[3] & _T_588; // @[exu_div_ctl.scala 698:95] + wire _T_983 = _T_719 & _T_982; // @[exu_div_ctl.scala 699:11] + wire _T_984 = _T_973 | _T_983; // @[exu_div_ctl.scala 716:88] + wire _T_989 = _T_615 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_994 = _T_989 & _T_982; // @[exu_div_ctl.scala 699:11] + wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 716:131] + wire _T_1001 = _T_658 & a_ff[1]; // @[exu_div_ctl.scala 697:95] + wire _T_1006 = _T_1001 & _T_747; // @[exu_div_ctl.scala 699:11] + wire _T_1007 = _T_995 | _T_1006; // @[exu_div_ctl.scala 717:47] + wire _T_1012 = _T_707 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_1015 = _T_1012 & _T_586; // @[exu_div_ctl.scala 699:11] + wire _T_1016 = _T_1007 | _T_1015; // @[exu_div_ctl.scala 717:88] + wire _T_1023 = _T_719 & a_ff[0]; // @[exu_div_ctl.scala 697:95] + wire _T_1025 = _T_1023 & b_ff[3]; // @[exu_div_ctl.scala 699:11] + wire _T_1026 = _T_1016 | _T_1025; // @[exu_div_ctl.scala 717:131] + wire _T_1032 = _T_707 & _T_586; // @[exu_div_ctl.scala 699:11] + wire _T_1035 = _T_1032 & _T_600; // @[exu_div_ctl.scala 718:74] + wire _T_1036 = _T_1026 | _T_1035; // @[exu_div_ctl.scala 718:47] wire [31:0] _T_562 = {28'h0,_T_591,_T_622,_T_725,_T_1036}; // @[Cat.scala 29:58] wire [31:0] _T_564 = _T_77 ? _T_561 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_565 = smallnum_case ? _T_562 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_566 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_567 = _T_564 | _T_565; // @[Mux.scala 27:72] wire [31:0] q_in = _T_567 | _T_566; // @[Mux.scala 27:72] - wire _T_572 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 689:16] - wire _T_573 = _T_30 & _T_572; // @[exu_div_ctl.scala 689:14] + wire _T_572 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 692:16] + wire _T_573 = _T_30 & _T_572; // @[exu_div_ctl.scala 692:14] wire [31:0] _T_576 = _T_573 ? q_ff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_577 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_578 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_579 = _T_576 | _T_577; // @[Mux.scala 27:72] - wire _T_1063 = shortq == 6'h1b; // @[exu_div_ctl.scala 731:58] - wire _T_1064 = shortq == 6'h1a; // @[exu_div_ctl.scala 731:58] - wire _T_1065 = shortq == 6'h19; // @[exu_div_ctl.scala 731:58] - wire _T_1066 = shortq == 6'h18; // @[exu_div_ctl.scala 731:58] - wire _T_1067 = shortq == 6'h17; // @[exu_div_ctl.scala 731:58] - wire _T_1068 = shortq == 6'h16; // @[exu_div_ctl.scala 731:58] - wire _T_1069 = shortq == 6'h15; // @[exu_div_ctl.scala 731:58] - wire _T_1070 = shortq == 6'h14; // @[exu_div_ctl.scala 731:58] - wire _T_1071 = shortq == 6'h13; // @[exu_div_ctl.scala 731:58] - wire _T_1072 = shortq == 6'h12; // @[exu_div_ctl.scala 731:58] - wire _T_1073 = shortq == 6'h11; // @[exu_div_ctl.scala 731:58] - wire _T_1074 = shortq == 6'h10; // @[exu_div_ctl.scala 731:58] - wire _T_1075 = shortq == 6'hf; // @[exu_div_ctl.scala 731:58] - wire _T_1076 = shortq == 6'he; // @[exu_div_ctl.scala 731:58] - wire _T_1077 = shortq == 6'hd; // @[exu_div_ctl.scala 731:58] - wire _T_1078 = shortq == 6'hc; // @[exu_div_ctl.scala 731:58] - wire _T_1079 = shortq == 6'hb; // @[exu_div_ctl.scala 731:58] - wire _T_1080 = shortq == 6'ha; // @[exu_div_ctl.scala 731:58] - wire _T_1081 = shortq == 6'h9; // @[exu_div_ctl.scala 731:58] - wire _T_1082 = shortq == 6'h8; // @[exu_div_ctl.scala 731:58] - wire _T_1083 = shortq == 6'h7; // @[exu_div_ctl.scala 731:58] - wire _T_1084 = shortq == 6'h6; // @[exu_div_ctl.scala 731:58] - wire _T_1085 = shortq == 6'h5; // @[exu_div_ctl.scala 731:58] - wire _T_1086 = shortq == 6'h4; // @[exu_div_ctl.scala 731:58] - wire _T_1087 = shortq == 6'h3; // @[exu_div_ctl.scala 731:58] - wire _T_1088 = shortq == 6'h2; // @[exu_div_ctl.scala 731:58] - wire _T_1089 = shortq == 6'h1; // @[exu_div_ctl.scala 731:58] - wire _T_1090 = shortq == 6'h0; // @[exu_div_ctl.scala 731:58] + wire _T_1063 = shortq == 6'h1b; // @[exu_div_ctl.scala 734:58] + wire _T_1064 = shortq == 6'h1a; // @[exu_div_ctl.scala 734:58] + wire _T_1065 = shortq == 6'h19; // @[exu_div_ctl.scala 734:58] + wire _T_1066 = shortq == 6'h18; // @[exu_div_ctl.scala 734:58] + wire _T_1067 = shortq == 6'h17; // @[exu_div_ctl.scala 734:58] + wire _T_1068 = shortq == 6'h16; // @[exu_div_ctl.scala 734:58] + wire _T_1069 = shortq == 6'h15; // @[exu_div_ctl.scala 734:58] + wire _T_1070 = shortq == 6'h14; // @[exu_div_ctl.scala 734:58] + wire _T_1071 = shortq == 6'h13; // @[exu_div_ctl.scala 734:58] + wire _T_1072 = shortq == 6'h12; // @[exu_div_ctl.scala 734:58] + wire _T_1073 = shortq == 6'h11; // @[exu_div_ctl.scala 734:58] + wire _T_1074 = shortq == 6'h10; // @[exu_div_ctl.scala 734:58] + wire _T_1075 = shortq == 6'hf; // @[exu_div_ctl.scala 734:58] + wire _T_1076 = shortq == 6'he; // @[exu_div_ctl.scala 734:58] + wire _T_1077 = shortq == 6'hd; // @[exu_div_ctl.scala 734:58] + wire _T_1078 = shortq == 6'hc; // @[exu_div_ctl.scala 734:58] + wire _T_1079 = shortq == 6'hb; // @[exu_div_ctl.scala 734:58] + wire _T_1080 = shortq == 6'ha; // @[exu_div_ctl.scala 734:58] + wire _T_1081 = shortq == 6'h9; // @[exu_div_ctl.scala 734:58] + wire _T_1082 = shortq == 6'h8; // @[exu_div_ctl.scala 734:58] + wire _T_1083 = shortq == 6'h7; // @[exu_div_ctl.scala 734:58] + wire _T_1084 = shortq == 6'h6; // @[exu_div_ctl.scala 734:58] + wire _T_1085 = shortq == 6'h5; // @[exu_div_ctl.scala 734:58] + wire _T_1086 = shortq == 6'h4; // @[exu_div_ctl.scala 734:58] + wire _T_1087 = shortq == 6'h3; // @[exu_div_ctl.scala 734:58] + wire _T_1088 = shortq == 6'h2; // @[exu_div_ctl.scala 734:58] + wire _T_1089 = shortq == 6'h1; // @[exu_div_ctl.scala 734:58] + wire _T_1090 = shortq == 6'h0; // @[exu_div_ctl.scala 734:58] wire [1:0] _T_1095 = _T_1063 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_1096 = _T_1064 ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1097 = _T_1065 ? 3'h6 : 3'h0; // @[Mux.scala 27:72] @@ -824,11 +824,11 @@ module exu_div_new_3bit_fullshortq( wire [4:0] _T_1151 = _T_1150 | _T_1120; // @[Mux.scala 27:72] wire [4:0] _T_1152 = _T_1151 | _T_1121; // @[Mux.scala 27:72] wire [4:0] shortq_decode = _T_1152 | _T_1122; // @[Mux.scala 27:72] - exu_div_cls a_enc ( // @[exu_div_ctl.scala 718:21] + exu_div_cls a_enc ( // @[exu_div_ctl.scala 721:21] .io_operand(a_enc_io_operand), .io_cls(a_enc_io_cls) ); - exu_div_cls b_enc ( // @[exu_div_ctl.scala 721:20] + exu_div_cls b_enc ( // @[exu_div_ctl.scala 724:20] .io_operand(b_enc_io_operand), .io_cls(b_enc_io_cls) ); @@ -876,10 +876,10 @@ module exu_div_new_3bit_fullshortq( .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en) ); - assign io_data_out = _T_579 | _T_578; // @[exu_div_ctl.scala 688:15] - assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 687:15] - assign a_enc_io_operand = {control_ff[2],a_ff[31:0]}; // @[exu_div_ctl.scala 719:20] - assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 722:20] + assign io_data_out = _T_579 | _T_578; // @[exu_div_ctl.scala 691:15] + assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 690:15] + assign a_enc_io_operand = {control_ff[2],a_ff[31:0]}; // @[exu_div_ctl.scala 722:20] + assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 725:20] assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18] assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18] diff --git a/src/main/scala/exu/exu_div_ctl.scala b/src/main/scala/exu/exu_div_ctl.scala index 4130f2e7..91255c1c 100644 --- a/src/main/scala/exu/exu_div_ctl.scala +++ b/src/main/scala/exu/exu_div_ctl.scala @@ -626,14 +626,17 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib val b_enable = io.valid_in | b_twos_comp val rq_enable = io.valid_in | valid_ff | running_state val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case - val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff - val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff - val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff - val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff - val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff - val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff - val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff - val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff + + val r_adder_sel = (0 to 7 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff)) + +// val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff +// val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff +// val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff +// val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff +// val r_adder4_sel = running_state & (quotient_new === 4.U) & !shortq_enable_ff +// val r_adder5_sel = running_state & (quotient_new === 5.U) & !shortq_enable_ff +// val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff +// val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0) val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U) @@ -668,14 +671,14 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib )) val r_in = Mux1H (Seq( r_sign_sel -> Fill(33,1.U), - r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)), - r_adder1_sel -> adder1_out(32,0), - r_adder2_sel -> adder2_out(32,0), - r_adder3_sel -> adder3_out(32,0), - r_adder4_sel -> adder4_out(32,0), - r_adder5_sel -> adder5_out(32,0), - r_adder6_sel -> adder6_out(32,0), - r_adder7_sel -> adder7_out(32,0), + r_adder_sel(0) -> Cat(r_ff(29,0),a_ff(32,30)), + r_adder_sel(1) -> adder1_out(32,0), + r_adder_sel(2) -> adder2_out(32,0), + r_adder_sel(3) -> adder3_out(32,0), + r_adder_sel(4) -> adder4_out(32,0), + r_adder_sel(5) -> adder5_out(32,0), + r_adder_sel(6) -> adder6_out(32,0), + r_adder_sel(7) -> adder7_out(32,0), shortq_enable_ff -> ar_shifted(65,33), by_zero_case -> Cat(0.U,a_ff(31,0)) )) @@ -746,24 +749,181 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib } +class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib { + val io = IO(new Bundle { + val scan_mode = Input(Bool()) + val cancel = Input(Bool()) + val valid_in = Input(Bool()) + val signed_in = Input(Bool()) + val rem_in = Input(Bool()) + val dividend_in = Input(UInt(32.W)) + val divisor_in = Input(UInt(32.W)) + val data_out = Output(UInt(32.W)) + val valid_out = Output(UInt(1.W)) + }) + io.data_out := 0.U + io.valid_out :=0.U +} +// val valid_ff = WireInit(Bool(),init=false.B) +// val finish_ff = WireInit(Bool(),init=false.B) +// val control_ff = WireInit(0.U(3.W)) +// val count_ff = WireInit(0.U(7.W)) +// val smallnum = WireInit(0.U(4.W)) +// val a_ff = WireInit(0.U(32.W)) +// val b_ff1 = WireInit(0.U(33.W)) +// val b_ff = WireInit(0.U(38.W)) +// val q_ff = WireInit(0.U(32.W)) +// val r_ff = WireInit(0.U(33.W)) +// val quotient_raw = WireInit(0.U(16.W)) +// val quotient_new = WireInit(0.U(4.W)) +// val shortq_enable = WireInit(Bool(),init=false.B) +// val shortq_enable_ff = WireInit(Bool(),init=false.B) +// val by_zero_case_ff = WireInit(Bool(),init=false.B) +// val ar_shifted = WireInit(0.U(65.W)) +// val shortq_shift = WireInit(0.U(5.W)) +// val shortq_decode = WireInit(0.U(5.W)) +// val shortq_shift_ff = WireInit(0.U(5.W)) +// val valid_ff_in = io.valid_in & !io.cancel +// val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in)) +// val dividend_sign_ff = control_ff(2) +// val divisor_sign_ff = control_ff(1) +// val rem_ff = control_ff(0) +// val by_zero_case = valid_ff & (b_ff(31,0) === 0.U) +// +// val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) | +// ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) +// val running_state = count_ff.orR() | shortq_enable_ff +// val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff +// val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U) +// val finish = finish_raw & !io.cancel +// val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable +// val count_in = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff)) +// val a_enable = io.valid_in | running_state +// val a_shift = running_state & !shortq_enable_ff +// ar_shifted := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff +// val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff) +// val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff) +// val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff +// val b_enable = io.valid_in | b_twos_comp +// val rq_enable = io.valid_in | valid_ff | running_state +// val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case +// +// val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & ~shortq_enable_ff)) +// +// val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0) +// val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U) +// val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0) +// val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) +// val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff +// val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) +// val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff +// quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)), +// (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)), +// (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)), +// (!adder4_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder4_out === 0.U)), +// (!adder3_out(35) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)), +// (!adder2_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)), +// (!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U) +// quotient_new := Cat ((quotient_raw(7) | quotient_raw(6) | quotient_raw(5) | quotient_raw(4)), +// (quotient_raw(7) | quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))), +// (quotient_raw(7) | (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1)))) +// val twos_comp_in = Mux1H(Seq ( +// twos_comp_q_sel -> q_ff, +// twos_comp_b_sel -> b_ff(31,0) +// )) +// val twos_comp_out = rvtwoscomp(twos_comp_in) +// val a_in = Mux1H(Seq ( +// (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)), +// a_shift -> Cat(a_ff(29,0),0.U(3.W)), +// shortq_enable_ff -> ar_shifted(32,0) +// )) +// val b_in = Mux1H(Seq ( +// !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), +// b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) +// )) +// val r_in = Mux1H (Seq( +// r_sign_sel -> Fill(33,1.U), +// r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)), +// r_adder1_sel -> adder1_out(32,0), +// r_adder2_sel -> adder2_out(32,0), +// r_adder3_sel -> adder3_out(32,0), +// r_adder4_sel -> adder4_out(32,0), +// r_adder5_sel -> adder5_out(32,0), +// r_adder6_sel -> adder6_out(32,0), +// r_adder7_sel -> adder7_out(32,0), +// shortq_enable_ff -> ar_shifted(65,33), +// by_zero_case -> Cat(0.U,a_ff(31,0)) +// )) +// val q_in = Mux1H (Seq( +// !valid_ff -> Cat(q_ff(28,0),quotient_new), +// smallnum_case -> Cat(0.U(28.W),smallnum), +// by_zero_case -> Fill(32,1.U) +// )) +// io.valid_out := finish_ff & !io.cancel +// io.data_out := Mux1H(Seq( +// (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff, +// rem_ff -> r_ff(31,0), +// twos_comp_q_sel -> twos_comp_out +// )) +// def pat1(x : List[Int], y : List[Int]) = { +// val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_) +// val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_) +// pat_a & pat_b +// } +// smallnum := Cat( +// pat1(List(3),List(-3, -2, -1)), +// +// pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)), +// +// pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) | +// pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) | +// pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)), +// +// pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) | +// pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) | +// pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) | +// pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) | +// pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) | +// pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) | +// pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) | +// pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) | +// pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0)) +// +// val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0)) +// val a_enc = Module(new exu_div_cls) +// a_enc.io.operand := shortq_dividend +// val dw_a_enc1 = a_enc.io.cls +// val b_enc = Module(new exu_div_cls) +// b_enc.io.operand := b_ff(32,0) +// val dw_b_enc1 = b_enc.io.cls +// val dw_a_enc = Cat (0.U, dw_a_enc1) +// val dw_b_enc = Cat (0.U, dw_b_enc1) +// +// val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) +// val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) +// shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel +// val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0) +// shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U)) +// shortq_shift := Mux(!shortq_enable,0.U,shortq_decode) +// b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1) +// valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) +// control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) +// by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) +// shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) +// shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) +// finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) +// count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) +// +// a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) +// b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) +// r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) +// q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) +// +//} object div_main4 extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_3bit_fullshortq())) } -class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib { - val io = IO(new Bundle{ - val scan_mode = Input(Bool()) - val cancel = Input(Bool()) - val valid_in = Input(Bool()) - val signed_in = Input(Bool()) - val rem_in = Input(Bool()) - val dividend_in = Input(UInt(32.W)) - val divisor_in = Input(UInt(32.W)) - val data_out = Output(UInt(32.W)) - val valid_out = Output(UInt(1.W)) - }) - io.data_out :=5.U - io.valid_out :=1.U -} + class exu_div_cls extends Module{ val io= IO(new Bundle{ val operand = Input(UInt(33.W)) diff --git a/target/scala-2.12/classes/exu/div_main4$.class b/target/scala-2.12/classes/exu/div_main4$.class index adf42c12..95da22f7 100644 Binary files a/target/scala-2.12/classes/exu/div_main4$.class and b/target/scala-2.12/classes/exu/div_main4$.class differ diff --git a/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class b/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class index 2fc06ce7..496b2373 100644 Binary files a/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class and b/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class b/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class index 06e6f913..4a2efbe0 100644 Binary files a/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class and b/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class differ diff --git a/target/scala-2.12/classes/exu/exu_div_cls.class b/target/scala-2.12/classes/exu/exu_div_cls.class index 4fe5dd5b..28d633f9 100644 Binary files a/target/scala-2.12/classes/exu/exu_div_cls.class and b/target/scala-2.12/classes/exu/exu_div_cls.class differ diff --git a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class index 76dfede5..d2a28ef5 100644 Binary files a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class and b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class differ diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class index 50abf2e9..5411df79 100644 Binary files a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class and b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class differ