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Async reset done in IFC

This commit is contained in:
waleed-lm 2020-09-30 22:28:23 +05:00
parent 7fde0caae0
commit 6bdc75f842
15 changed files with 813 additions and 362 deletions
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7
EL2_IC_DATA.anno.json
View File

@ -3,10 +3,15 @@
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en"
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{

75
EL2_IC_DATA.fir
View File

@ -3,7 +3,7 @@ circuit EL2_IC_DATA :
module EL2_IC_DATA :
input clock : Clock
input reset : UInt<1>
output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, test : UInt}
output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip test_in : UInt<71>, test : UInt}
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23]
@ -183,4 +183,77 @@ circuit EL2_IC_DATA :
node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 239:84]
io.test <= ic_rw_addr_bank_q[1] @[el2_ifu_ic_mem.scala 241:11]
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 246:21]
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:50]
node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 248:29]
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
when _T_138 : @[el2_ifu_ic_mem.scala 248:62]
infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_139[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
skip @[el2_ifu_ic_mem.scala 248:62]
else : @[el2_ifu_ic_mem.scala 250:69]
node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 250:36]
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_144 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:26]
io.test <= _T_145[0][0] @[el2_ifu_ic_mem.scala 251:15]
skip @[el2_ifu_ic_mem.scala 250:69]
node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:50]
node _T_148 = and(_T_146, _T_147) @[el2_ifu_ic_mem.scala 248:29]
node _T_149 = bits(_T_148, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
when _T_149 : @[el2_ifu_ic_mem.scala 248:62]
infer mport _T_150 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_150[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
skip @[el2_ifu_ic_mem.scala 248:62]
else : @[el2_ifu_ic_mem.scala 250:69]
node _T_151 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_153 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
node _T_154 = and(_T_152, _T_153) @[el2_ifu_ic_mem.scala 250:36]
node _T_155 = bits(_T_154, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_155 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_156 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:26]
io.test <= _T_156[1][0] @[el2_ifu_ic_mem.scala 251:15]
skip @[el2_ifu_ic_mem.scala 250:69]
node _T_157 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
node _T_158 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:50]
node _T_159 = and(_T_157, _T_158) @[el2_ifu_ic_mem.scala 248:29]
node _T_160 = bits(_T_159, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
when _T_160 : @[el2_ifu_ic_mem.scala 248:62]
infer mport _T_161 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_161[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
skip @[el2_ifu_ic_mem.scala 248:62]
else : @[el2_ifu_ic_mem.scala 250:69]
node _T_162 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 250:36]
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_166 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:26]
io.test <= _T_167[0][1] @[el2_ifu_ic_mem.scala 251:15]
skip @[el2_ifu_ic_mem.scala 250:69]
node _T_168 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
node _T_169 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:50]
node _T_170 = and(_T_168, _T_169) @[el2_ifu_ic_mem.scala 248:29]
node _T_171 = bits(_T_170, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
when _T_171 : @[el2_ifu_ic_mem.scala 248:62]
infer mport _T_172 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_172[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
skip @[el2_ifu_ic_mem.scala 248:62]
else : @[el2_ifu_ic_mem.scala 250:69]
node _T_173 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 250:36]
node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_177 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:26]
io.test <= _T_178[1][1] @[el2_ifu_ic_mem.scala 251:15]
skip @[el2_ifu_ic_mem.scala 250:69]

371
EL2_IC_DATA.v
View File

@ -21,14 +21,381 @@ module EL2_IC_DATA(
input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit,
input io_scan_mode,
output [8:0] io_test
input [70:0] io_test_in,
output [70:0] io_test
);
`ifdef RANDOMIZE_MEM_INIT
reg [95:0] _RAND_0;
reg [95:0] _RAND_1;
reg [95:0] _RAND_2;
reg [95:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_0__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_0__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_0_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_0_1__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_0_1__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_0__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_0__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
wire [70:0] data_mem_1_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
wire [8:0] data_mem_1_1__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
wire data_mem_1_1__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 200:70]
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 201:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 201:94]
wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 206:45]
wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58]
wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 206:25]
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 208:79]
wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 211:113]
wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 211:38]
wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 211:17]
wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 211:38]
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 211:17]
wire _T_37 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 215:16]
wire _T_42 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 216:91]
wire _T_56 = ic_rw_addr_q[2] & _T_42; // @[Mux.scala 27:72]
wire _T_59 = _T_37 | _T_56; // @[Mux.scala 27:72]
wire _T_113 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 223:74]
wire _T_114 = ~_T_113; // @[el2_ifu_ic_mem.scala 223:61]
wire _T_115 = io_ic_debug_rd_en & _T_114; // @[el2_ifu_ic_mem.scala 223:58]
wire ic_rd_en_with_debug = io_ic_rd_en | _T_115; // @[el2_ifu_ic_mem.scala 223:38]
wire _T_63 = _T_59 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 218:117]
wire _T_87 = _T_37 & _T_42; // @[Mux.scala 27:72]
wire _T_90 = ic_rw_addr_q[2] | _T_87; // @[Mux.scala 27:72]
wire _T_92 = _T_90 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 218:117]
wire [1:0] ic_b_rden = {_T_92,_T_63}; // @[Cat.scala 29:58]
wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_98 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
wire _T_100 = _T_98 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 221:43]
wire _T_102 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
wire _T_104 = _T_102 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 221:43]
wire [1:0] ic_bank_way_clken_0 = {_T_100,_T_104}; // @[Cat.scala 29:58]
wire _T_106 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
wire _T_108 = _T_106 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 221:43]
wire _T_110 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
wire _T_112 = _T_110 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 221:43]
wire [1:0] ic_bank_way_clken_1 = {_T_108,_T_112}; // @[Cat.scala 29:58]
wire _T_121 = _T_56 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 225:86]
wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 225:108]
wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 227:40]
wire [8:0] _T_129 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:29]
wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36]
wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : {{62'd0}, ic_rw_addr_q[11:3]}; // @[el2_ifu_ic_mem.scala 250:69]
wire [70:0] _GEN_13 = _T_137 ? {{62'd0}, ic_rw_addr_q[11:3]} : _GEN_3; // @[el2_ifu_ic_mem.scala 248:62]
wire _T_148 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:29]
wire _T_152 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_154 = _T_152 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36]
wire [70:0] _GEN_17 = _T_154 ? data_mem_1_0__T_156_data : _GEN_13; // @[el2_ifu_ic_mem.scala 250:69]
wire [70:0] _GEN_27 = _T_148 ? _GEN_13 : _GEN_17; // @[el2_ifu_ic_mem.scala 248:62]
wire _T_159 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:29]
wire _T_163 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_165 = _T_163 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36]
wire [70:0] _GEN_31 = _T_165 ? data_mem_0_1__T_167_data : _GEN_27; // @[el2_ifu_ic_mem.scala 250:69]
wire [70:0] _GEN_41 = _T_159 ? _GEN_27 : _GEN_31; // @[el2_ifu_ic_mem.scala 248:62]
wire _T_170 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:29]
wire _T_174 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_176 = _T_174 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36]
wire [70:0] _GEN_45 = _T_176 ? data_mem_1_1__T_178_data : _GEN_41; // @[el2_ifu_ic_mem.scala 250:69]
assign data_mem_0_0__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_0__T_156_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_156_data = data_mem_0_0[data_mem_0_0__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_0__T_167_data = data_mem_0_0[data_mem_0_0__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_0__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_178_data = data_mem_0_0[data_mem_0_0__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_0__T_139_data = io_test_in;
assign data_mem_0_0__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_0__T_139_mask = 1'h1;
assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_0_0__T_150_data = 71'h0;
assign data_mem_0_0__T_150_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_150_mask = 1'h0;
assign data_mem_0_0__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_0_0__T_161_data = 71'h0;
assign data_mem_0_0__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_0__T_161_mask = 1'h0;
assign data_mem_0_0__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_0_0__T_172_data = 71'h0;
assign data_mem_0_0__T_172_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_172_mask = 1'h0;
assign data_mem_0_0__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_0_1__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_1__T_156_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_156_data = data_mem_0_1[data_mem_0_1__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_1__T_167_data = data_mem_0_1[data_mem_0_1__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_1__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_178_data = data_mem_0_1[data_mem_0_1__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_0_1__T_139_data = 71'h0;
assign data_mem_0_1__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_1__T_139_mask = 1'h0;
assign data_mem_0_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_0_1__T_150_data = 71'h0;
assign data_mem_0_1__T_150_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_150_mask = 1'h0;
assign data_mem_0_1__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_0_1__T_161_data = io_test_in;
assign data_mem_0_1__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_1__T_161_mask = 1'h1;
assign data_mem_0_1__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_0_1__T_172_data = 71'h0;
assign data_mem_0_1__T_172_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_172_mask = 1'h0;
assign data_mem_0_1__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_0__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_0__T_156_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_156_data = data_mem_1_0[data_mem_1_0__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_0__T_167_data = data_mem_1_0[data_mem_1_0__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_0__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_178_data = data_mem_1_0[data_mem_1_0__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_0__T_139_data = 71'h0;
assign data_mem_1_0__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_0__T_139_mask = 1'h0;
assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_1_0__T_150_data = io_test_in;
assign data_mem_1_0__T_150_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_150_mask = 1'h1;
assign data_mem_1_0__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_1_0__T_161_data = 71'h0;
assign data_mem_1_0__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_0__T_161_mask = 1'h0;
assign data_mem_1_0__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_1_0__T_172_data = 71'h0;
assign data_mem_1_0__T_172_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_172_mask = 1'h0;
assign data_mem_1_0__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_1__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_1__T_156_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_156_data = data_mem_1_1[data_mem_1_1__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_1__T_167_data = data_mem_1_1[data_mem_1_1__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_178_data = data_mem_1_1[data_mem_1_1__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
assign data_mem_1_1__T_139_data = 71'h0;
assign data_mem_1_1__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_1__T_139_mask = 1'h0;
assign data_mem_1_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_1_1__T_150_data = 71'h0;
assign data_mem_1_1__T_150_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_150_mask = 1'h0;
assign data_mem_1_1__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_1_1__T_161_data = 71'h0;
assign data_mem_1_1__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_1_1__T_161_mask = 1'h0;
assign data_mem_1_1__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_1_1__T_172_data = io_test_in;
assign data_mem_1_1__T_172_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_172_mask = 1'h1;
assign data_mem_1_1__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17]
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
assign io_test = ic_rw_addr_q[11:3]; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 209:11 el2_ifu_ic_mem.scala 241:11]
assign io_test = _T_170 ? _GEN_41 : _GEN_45; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 209:11 el2_ifu_ic_mem.scala 241:11 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_0[initvar] = _RAND_0[70:0];
_RAND_1 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_1[initvar] = _RAND_1[70:0];
_RAND_2 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_0[initvar] = _RAND_2[70:0];
_RAND_3 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_1[initvar] = _RAND_3[70:0];
`endif // RANDOMIZE_MEM_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin
data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_0__T_150_en & data_mem_0_0__T_150_mask) begin
data_mem_0_0[data_mem_0_0__T_150_addr] <= data_mem_0_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_0__T_161_en & data_mem_0_0__T_161_mask) begin
data_mem_0_0[data_mem_0_0__T_161_addr] <= data_mem_0_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_0__T_172_en & data_mem_0_0__T_172_mask) begin
data_mem_0_0[data_mem_0_0__T_172_addr] <= data_mem_0_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin
data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_1__T_150_en & data_mem_0_1__T_150_mask) begin
data_mem_0_1[data_mem_0_1__T_150_addr] <= data_mem_0_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_1__T_161_en & data_mem_0_1__T_161_mask) begin
data_mem_0_1[data_mem_0_1__T_161_addr] <= data_mem_0_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_0_1__T_172_en & data_mem_0_1__T_172_mask) begin
data_mem_0_1[data_mem_0_1__T_172_addr] <= data_mem_0_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin
data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_0__T_150_en & data_mem_1_0__T_150_mask) begin
data_mem_1_0[data_mem_1_0__T_150_addr] <= data_mem_1_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_0__T_161_en & data_mem_1_0__T_161_mask) begin
data_mem_1_0[data_mem_1_0__T_161_addr] <= data_mem_1_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_0__T_172_en & data_mem_1_0__T_172_mask) begin
data_mem_1_0[data_mem_1_0__T_172_addr] <= data_mem_1_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin
data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_1__T_150_en & data_mem_1_1__T_150_mask) begin
data_mem_1_1[data_mem_1_1__T_150_addr] <= data_mem_1_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_1__T_161_en & data_mem_1_1__T_161_mask) begin
data_mem_1_1[data_mem_1_1__T_161_addr] <= data_mem_1_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
end
if(data_mem_1_1__T_172_en & data_mem_1_1__T_172_mask) begin
data_mem_1_1[data_mem_1_1__T_172_addr] <= data_mem_1_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
end
end
endmodule

424
el2_ifu_ifc_ctl.fir
View File

@ -5,9 +5,11 @@ circuit el2_ifu_ifc_ctl :
input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<32>
wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32>
wire fetch_addr_next_0 : UInt<1>
fetch_addr_next_0 <= UInt<1>("h00")
wire fetch_addr_next : UInt<31>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
@ -45,31 +47,31 @@ circuit el2_ifu_ifc_ctl :
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 61:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 62:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 62:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 62:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 64:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 64:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 64:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 66:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 66:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 66:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 67:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 67:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 71:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 72:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:22]
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
@ -77,190 +79,192 @@ circuit el2_ifu_ifc_ctl :
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<32> @[Mux.scala 27:72]
wire _T_24 : UInt<31> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 71:24]
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctl.scala 78:13]
node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctl.scala 79:47]
node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 79:75]
node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctl.scala 79:30]
node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 80:45]
node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 80:51]
node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctl.scala 80:51]
node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58]
fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_31 = not(idle) @[el2_ifu_ifc_ctl.scala 83:30]
io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctl.scala 83:27]
node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 85:91]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:70]
node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctl.scala 85:68]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:53]
node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctl.scala 85:51]
node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:5]
node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctl.scala 85:114]
node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:18]
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 86:16]
node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:39]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 86:37]
io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctl.scala 85:23]
node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 88:37]
fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctl.scala 88:15]
node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:34]
node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctl.scala 90:32]
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:49]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctl.scala 90:47]
miss_f <= _T_47 @[el2_ifu_ifc_ctl.scala 90:10]
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 92:39]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:63]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 92:61]
node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:76]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 92:74]
node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:86]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 92:84]
mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctl.scala 92:16]
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 94:35]
goto_idle <= _T_55 @[el2_ifu_ifc_ctl.scala 94:13]
node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 96:38]
node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctl.scala 96:36]
node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctl.scala 96:67]
leave_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 96:14]
node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:29]
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:23]
node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 98:40]
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctl.scala 98:44]
node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:55]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 98:53]
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 99:11]
node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:17]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 99:15]
node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:33]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 99:31]
node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctl.scala 98:67]
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:23]
node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctl.scala 101:34]
node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 101:56]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:62]
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctl.scala 101:60]
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctl.scala 101:48]
node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 103:19]
_T_77 <= _T_76 @[el2_ifu_ifc_ctl.scala 103:19]
state <= _T_77 @[el2_ifu_ifc_ctl.scala 103:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 105:12]
node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:38]
node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctl.scala 107:36]
node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:61]
node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctl.scala 107:81]
node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctl.scala 107:58]
node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 108:25]
node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctl.scala 107:92]
fb_right <= _T_84 @[el2_ifu_ifc_ctl.scala 107:12]
node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 110:39]
node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctl.scala 110:59]
node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctl.scala 110:36]
fb_right2 <= _T_87 @[el2_ifu_ifc_ctl.scala 110:13]
node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 111:56]
node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:35]
node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctl.scala 111:33]
node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:80]
node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctl.scala 111:78]
fb_left <= _T_92 @[el2_ifu_ifc_ctl.scala 111:11]
node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 113:37]
node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctl.scala 114:28]
node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 114:62]
node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctl.scala 115:29]
node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 115:63]
node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctl.scala 116:27]
node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 116:51]
node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:6]
node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:18]
node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctl.scala 117:16]
node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:30]
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 117:28]
node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:43]
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 117:41]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctl.scala 117:53]
node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 117:73]
node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:38]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:83]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:62]
node _T_30 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:129]
node _T_31 = and(_T_29, _T_30) @[el2_ifu_ifc_ctl.scala 78:108]
fetch_addr_next_0 <= _T_31 @[el2_ifu_ifc_ctl.scala 78:21]
node _T_32 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_32 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_33 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_33 @[el2_ifu_ifc_ctl.scala 82:27]
node _T_34 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
node _T_36 = and(fb_full_f_ns, _T_35) @[el2_ifu_ifc_ctl.scala 84:68]
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
node _T_38 = and(io.ifc_fetch_req_bf_raw, _T_37) @[el2_ifu_ifc_ctl.scala 84:51]
node _T_39 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 84:114]
node _T_41 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 85:16]
node _T_43 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctl.scala 85:37]
io.ifc_fetch_req_bf <= _T_44 @[el2_ifu_ifc_ctl.scala 84:23]
node _T_45 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
fetch_bf_en <= _T_45 @[el2_ifu_ifc_ctl.scala 87:15]
node _T_46 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
node _T_47 = and(io.ifc_fetch_req_f, _T_46) @[el2_ifu_ifc_ctl.scala 89:32]
node _T_48 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
node _T_49 = and(_T_47, _T_48) @[el2_ifu_ifc_ctl.scala 89:47]
miss_f <= _T_49 @[el2_ifu_ifc_ctl.scala 89:10]
node _T_50 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
node _T_51 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 91:61]
node _T_53 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 91:74]
node _T_55 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctl.scala 91:84]
mb_empty_mod <= _T_56 @[el2_ifu_ifc_ctl.scala 91:16]
node _T_57 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
goto_idle <= _T_57 @[el2_ifu_ifc_ctl.scala 93:13]
node _T_58 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
node _T_59 = and(io.exu_flush_final, _T_58) @[el2_ifu_ifc_ctl.scala 95:36]
node _T_60 = and(_T_59, idle) @[el2_ifu_ifc_ctl.scala 95:67]
leave_idle <= _T_60 @[el2_ifu_ifc_ctl.scala 95:14]
node _T_61 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
node _T_63 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
node _T_64 = and(_T_62, _T_63) @[el2_ifu_ifc_ctl.scala 97:33]
node _T_65 = and(_T_64, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
node _T_66 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
node _T_67 = and(_T_65, _T_66) @[el2_ifu_ifc_ctl.scala 97:53]
node _T_68 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
node _T_69 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 98:15]
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctl.scala 98:31]
node next_state_1 = or(_T_67, _T_72) @[el2_ifu_ifc_ctl.scala 97:67]
node _T_73 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
node _T_74 = and(_T_73, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
node _T_75 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
node _T_76 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctl.scala 100:60]
node next_state_0 = or(_T_74, _T_77) @[el2_ifu_ifc_ctl.scala 100:48]
node _T_78 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_79 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
_T_79 <= _T_78 @[el2_ifu_ifc_ctl.scala 102:19]
state <= _T_79 @[el2_ifu_ifc_ctl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
node _T_80 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
node _T_81 = and(io.ifu_fb_consume1, _T_80) @[el2_ifu_ifc_ctl.scala 106:36]
node _T_82 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
node _T_83 = or(_T_82, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
node _T_84 = and(_T_81, _T_83) @[el2_ifu_ifc_ctl.scala 106:58]
node _T_85 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
node _T_86 = or(_T_84, _T_85) @[el2_ifu_ifc_ctl.scala 106:92]
fb_right <= _T_86 @[el2_ifu_ifc_ctl.scala 106:12]
node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
node _T_89 = and(io.ifu_fb_consume2, _T_88) @[el2_ifu_ifc_ctl.scala 109:36]
fb_right2 <= _T_89 @[el2_ifu_ifc_ctl.scala 109:13]
node _T_90 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
node _T_92 = and(io.ifc_fetch_req_f, _T_91) @[el2_ifu_ifc_ctl.scala 110:33]
node _T_93 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
node _T_94 = and(_T_92, _T_93) @[el2_ifu_ifc_ctl.scala 110:78]
fb_left <= _T_94 @[el2_ifu_ifc_ctl.scala 110:11]
node _T_95 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
node _T_96 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
node _T_97 = and(_T_96, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
node _T_98 = bits(_T_97, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
node _T_99 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
node _T_100 = cat(UInt<1>("h00"), _T_99) @[Cat.scala 29:58]
node _T_101 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_102 = and(_T_101, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_103 = bits(_T_102, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
node _T_104 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
node _T_105 = cat(UInt<2>("h00"), _T_104) @[Cat.scala 29:58]
node _T_106 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_107 = and(_T_106, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
node _T_109 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_111 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_112 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_114 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 116:28]
node _T_116 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctl.scala 116:41]
node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
node _T_119 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
node _T_120 = mux(_T_95, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = mux(_T_98, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_103, _T_105, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_108, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_125 = or(_T_120, _T_121) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
wire _T_127 : UInt<4> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
fb_write_ns <= _T_127 @[el2_ifu_ifc_ctl.scala 113:15]
node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 120:38]
reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 120:26]
_T_129 <= _T_128 @[el2_ifu_ifc_ctl.scala 120:26]
fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 120:16]
node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 122:17]
idle <= _T_130 @[el2_ifu_ifc_ctl.scala 122:8]
node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 123:16]
wfm <= _T_131 @[el2_ifu_ifc_ctl.scala 123:7]
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 125:30]
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 125:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 126:26]
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 127:24]
_T_133 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 127:24]
fb_write_f <= _T_133 @[el2_ifu_ifc_ctl.scala 127:14]
node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 130:40]
node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 130:61]
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 130:19]
node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctl.scala 130:17]
node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctl.scala 130:84]
node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctl.scala 129:60]
node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctl.scala 129:33]
io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctl.scala 129:26]
node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 211:25]
node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 211:47]
node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 214:14]
node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 135:25]
node _T_144 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:30]
node _T_145 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 137:39]
node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:18]
node _T_147 = and(fb_full_f, _T_146) @[el2_ifu_ifc_ctl.scala 137:16]
node _T_148 = or(_T_144, _T_147) @[el2_ifu_ifc_ctl.scala 136:53]
node _T_149 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:13]
node _T_150 = and(wfm, _T_149) @[el2_ifu_ifc_ctl.scala 138:11]
node _T_151 = or(_T_148, _T_150) @[el2_ifu_ifc_ctl.scala 137:62]
node _T_152 = or(_T_151, idle) @[el2_ifu_ifc_ctl.scala 138:35]
node _T_153 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:46]
node _T_154 = and(_T_152, _T_153) @[el2_ifu_ifc_ctl.scala 138:44]
node _T_155 = or(_T_154, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 138:67]
io.ifc_dma_access_ok <= _T_155 @[el2_ifu_ifc_ctl.scala 136:24]
node _T_156 = not(iccm_acc_in_range_bf) @[el2_ifu_ifc_ctl.scala 140:33]
node _T_157 = and(_T_156, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 140:55]
io.ifc_region_acc_fault_bf <= _T_157 @[el2_ifu_ifc_ctl.scala 140:30]
node _T_158 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 141:78]
node _T_159 = cat(_T_158, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_160 = dshr(io.dec_tlu_mrac_ff, _T_159) @[el2_ifu_ifc_ctl.scala 141:53]
node _T_161 = bits(_T_160, 0, 0) @[el2_ifu_ifc_ctl.scala 141:53]
node _T_162 = not(_T_161) @[el2_ifu_ifc_ctl.scala 141:34]
io.ifc_fetch_uncacheable_bf <= _T_162 @[el2_ifu_ifc_ctl.scala 141:31]
reg _T_163 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 143:32]
_T_163 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 143:32]
io.ifc_fetch_req_f <= _T_163 @[el2_ifu_ifc_ctl.scala 143:22]
node _T_164 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 145:88]
reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
wire _T_129 : UInt<4> @[Mux.scala 27:72]
_T_129 <= _T_128 @[Mux.scala 27:72]
fb_write_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 112:15]
node _T_130 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
reg _T_131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
_T_131 <= _T_130 @[el2_ifu_ifc_ctl.scala 119:26]
fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctl.scala 119:16]
node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
idle <= _T_132 @[el2_ifu_ifc_ctl.scala 121:8]
node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
wfm <= _T_133 @[el2_ifu_ifc_ctl.scala 122:7]
node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctl.scala 124:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
_T_135 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
fb_write_f <= _T_135 @[el2_ifu_ifc_ctl.scala 126:14]
node _T_136 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
node _T_137 = or(_T_136, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
node _T_138 = eq(_T_137, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
node _T_139 = and(fb_full_f, _T_138) @[el2_ifu_ifc_ctl.scala 129:17]
node _T_140 = or(_T_139, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
node _T_141 = and(io.ifc_fetch_req_bf_raw, _T_140) @[el2_ifu_ifc_ctl.scala 128:60]
node _T_142 = or(wfm, _T_141) @[el2_ifu_ifc_ctl.scala 128:33]
io.ifu_pmu_fetch_stall <= _T_142 @[el2_ifu_ifc_ctl.scala 128:26]
node _T_143 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_144 = bits(_T_143, 31, 28) @[el2_lib.scala 211:25]
node iccm_acc_in_region_bf = eq(_T_144, UInt<4>("h0e")) @[el2_lib.scala 211:47]
node _T_145 = bits(_T_143, 31, 16) @[el2_lib.scala 214:14]
node iccm_acc_in_range_bf = eq(_T_145, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
node _T_146 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
node _T_147 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
node _T_149 = and(fb_full_f, _T_148) @[el2_ifu_ifc_ctl.scala 136:16]
node _T_150 = or(_T_146, _T_149) @[el2_ifu_ifc_ctl.scala 135:53]
node _T_151 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
node _T_152 = and(wfm, _T_151) @[el2_ifu_ifc_ctl.scala 137:11]
node _T_153 = or(_T_150, _T_152) @[el2_ifu_ifc_ctl.scala 136:62]
node _T_154 = or(_T_153, idle) @[el2_ifu_ifc_ctl.scala 137:35]
node _T_155 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
node _T_156 = and(_T_154, _T_155) @[el2_ifu_ifc_ctl.scala 137:44]
node _T_157 = or(_T_156, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
io.ifc_dma_access_ok <= _T_157 @[el2_ifu_ifc_ctl.scala 135:24]
node _T_158 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
node _T_159 = and(_T_158, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
io.ifc_region_acc_fault_bf <= _T_159 @[el2_ifu_ifc_ctl.scala 139:30]
node _T_160 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_162 = dshr(io.dec_tlu_mrac_ff, _T_161) @[el2_ifu_ifc_ctl.scala 140:53]
node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
node _T_164 = not(_T_163) @[el2_ifu_ifc_ctl.scala 140:34]
io.ifc_fetch_uncacheable_bf <= _T_164 @[el2_ifu_ifc_ctl.scala 140:31]
reg _T_165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
_T_165 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
io.ifc_fetch_req_f <= _T_165 @[el2_ifu_ifc_ctl.scala 142:22]
node _T_166 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_166 : @[Reg.scala 28:19]
_T_167 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_165 @[el2_ifu_ifc_ctl.scala 145:23]
io.ifc_fetch_addr_f <= _T_167 @[el2_ifu_ifc_ctl.scala 144:23]

265
el2_ifu_ifc_ctl.v
View File

@ -37,134 +37,133 @@ module el2_ifu_ifc_ctl(
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 61:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 64:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 66:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 66:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 66:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 66:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 66:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 67:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 80:51]
wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58]
wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctl.scala 80:19]
wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:62]
wire fetch_addr_next_0 = _T_29 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:108]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72]
wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 103:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 122:17]
wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 85:91]
wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctl.scala 85:70]
wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 107:38]
wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctl.scala 107:36]
wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 90:32]
wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctl.scala 90:47]
wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 107:81]
wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctl.scala 107:58]
wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 108:25]
wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctl.scala 107:92]
wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 114:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 127:24]
wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctl.scala 110:36]
wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72]
wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 111:56]
wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctl.scala 111:35]
wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctl.scala 111:33]
wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 111:80]
wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctl.scala 111:78]
wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 116:16]
wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 117:18]
wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctl.scala 117:16]
wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 117:30]
wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctl.scala 117:28]
wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 117:43]
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 117:41]
wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 125:30]
wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctl.scala 85:68]
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 85:53]
wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctl.scala 85:51]
wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 86:5]
wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctl.scala 85:114]
wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 86:18]
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 86:16]
wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 86:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 88:37]
wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 92:39]
wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctl.scala 92:61]
wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctl.scala 92:74]
wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 92:86]
wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctl.scala 92:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 94:35]
wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctl.scala 96:36]
wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctl.scala 96:67]
wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 98:23]
wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctl.scala 98:33]
wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctl.scala 98:44]
wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 98:55]
wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctl.scala 98:53]
wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 99:17]
wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctl.scala 99:15]
wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctl.scala 99:31]
wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctl.scala 98:67]
wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctl.scala 101:34]
wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctl.scala 101:60]
wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctl.scala 101:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 123:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 126:26]
wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 130:61]
wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctl.scala 130:19]
wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctl.scala 130:17]
wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctl.scala 130:84]
wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctl.scala 129:60]
wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_141[31:28] == 4'he; // @[el2_lib.scala 211:47]
wire iccm_acc_in_range_bf = _T_141[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
wire _T_144 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 136:30]
wire _T_147 = fb_full_f & _T_33; // @[el2_ifu_ifc_ctl.scala 137:16]
wire _T_148 = _T_144 | _T_147; // @[el2_ifu_ifc_ctl.scala 136:53]
wire _T_149 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 138:13]
wire _T_150 = wfm & _T_149; // @[el2_ifu_ifc_ctl.scala 138:11]
wire _T_151 = _T_148 | _T_150; // @[el2_ifu_ifc_ctl.scala 137:62]
wire _T_152 = _T_151 | idle; // @[el2_ifu_ifc_ctl.scala 138:35]
wire _T_154 = _T_152 & _T_2; // @[el2_ifu_ifc_ctl.scala 138:44]
wire _T_156 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 140:33]
wire [4:0] _T_159 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_160 = io_dec_tlu_mrac_ff >> _T_159; // @[el2_ifu_ifc_ctl.scala 141:53]
reg _T_163; // @[el2_ifu_ifc_ctl.scala 143:32]
reg [30:0] _T_165; // @[Reg.scala 27:20]
assign io_ifc_fetch_addr_f = _T_165; // @[el2_ifu_ifc_ctl.scala 145:23]
assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctl.scala 71:24]
assign io_ifc_fetch_req_f = _T_163; // @[el2_ifu_ifc_ctl.scala 143:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctl.scala 129:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_160[0]; // @[el2_ifu_ifc_ctl.scala 141:31]
assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 83:27]
assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 135:25]
assign io_ifc_region_acc_fault_bf = _T_156 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 140:30]
assign io_ifc_dma_access_ok = _T_154 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 136:24]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
wire _T_34 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 84:70]
wire [3:0] _T_120 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_80 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
wire _T_81 = io_ifu_fb_consume1 & _T_80; // @[el2_ifu_ifc_ctl.scala 106:36]
wire _T_47 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
wire miss_f = _T_47 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
wire _T_83 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
wire _T_84 = _T_81 & _T_83; // @[el2_ifu_ifc_ctl.scala 106:58]
wire _T_85 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
wire fb_right = _T_84 | _T_85; // @[el2_ifu_ifc_ctl.scala 106:92]
wire _T_97 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
wire [3:0] _T_100 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_121 = _T_97 ? _T_100 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_125 = _T_120 | _T_121; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_83; // @[el2_ifu_ifc_ctl.scala 109:36]
wire _T_102 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
wire [3:0] _T_105 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_122 = _T_102 ? _T_105 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
wire _T_90 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
wire _T_91 = ~_T_90; // @[el2_ifu_ifc_ctl.scala 110:35]
wire _T_92 = io_ifc_fetch_req_f & _T_91; // @[el2_ifu_ifc_ctl.scala 110:33]
wire _T_93 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
wire fb_left = _T_92 & _T_93; // @[el2_ifu_ifc_ctl.scala 110:78]
wire _T_107 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_110 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_107 ? _T_110 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
wire _T_112 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
wire _T_113 = _T_2 & _T_112; // @[el2_ifu_ifc_ctl.scala 116:16]
wire _T_114 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 116:28]
wire _T_116 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctl.scala 116:41]
wire [3:0] _T_124 = _T_117 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_127 | _T_124; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
wire _T_36 = fb_full_f_ns & _T_35; // @[el2_ifu_ifc_ctl.scala 84:68]
wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctl.scala 84:53]
wire _T_38 = io_ifc_fetch_req_bf_raw & _T_37; // @[el2_ifu_ifc_ctl.scala 84:51]
wire _T_39 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 84:114]
wire _T_41 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
wire _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:16]
wire _T_43 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
wire _T_50 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
wire _T_52 = _T_50 & _T_39; // @[el2_ifu_ifc_ctl.scala 91:61]
wire _T_54 = _T_52 & _T_93; // @[el2_ifu_ifc_ctl.scala 91:74]
wire _T_55 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
wire mb_empty_mod = _T_54 & _T_55; // @[el2_ifu_ifc_ctl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
wire _T_59 = io_exu_flush_final & _T_43; // @[el2_ifu_ifc_ctl.scala 95:36]
wire leave_idle = _T_59 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
wire _T_62 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
wire _T_64 = _T_62 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
wire _T_65 = _T_64 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
wire _T_66 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
wire _T_67 = _T_65 & _T_66; // @[el2_ifu_ifc_ctl.scala 97:53]
wire _T_69 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
wire _T_70 = state[1] & _T_69; // @[el2_ifu_ifc_ctl.scala 98:15]
wire _T_72 = _T_70 & _T_66; // @[el2_ifu_ifc_ctl.scala 98:31]
wire next_state_1 = _T_67 | _T_72; // @[el2_ifu_ifc_ctl.scala 97:67]
wire _T_74 = _T_66 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
wire _T_77 = state[0] & _T_66; // @[el2_ifu_ifc_ctl.scala 100:60]
wire next_state_0 = _T_74 | _T_77; // @[el2_ifu_ifc_ctl.scala 100:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
wire _T_137 = _T_34 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
wire _T_138 = ~_T_137; // @[el2_ifu_ifc_ctl.scala 129:19]
wire _T_139 = fb_full_f & _T_138; // @[el2_ifu_ifc_ctl.scala 129:17]
wire _T_140 = _T_139 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
wire _T_141 = io_ifc_fetch_req_bf_raw & _T_140; // @[el2_ifu_ifc_ctl.scala 128:60]
wire [31:0] _T_143 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_143[31:28] == 4'he; // @[el2_lib.scala 211:47]
wire iccm_acc_in_range_bf = _T_143[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
wire _T_146 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
wire _T_149 = fb_full_f & _T_35; // @[el2_ifu_ifc_ctl.scala 136:16]
wire _T_150 = _T_146 | _T_149; // @[el2_ifu_ifc_ctl.scala 135:53]
wire _T_151 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
wire _T_152 = wfm & _T_151; // @[el2_ifu_ifc_ctl.scala 137:11]
wire _T_153 = _T_150 | _T_152; // @[el2_ifu_ifc_ctl.scala 136:62]
wire _T_154 = _T_153 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
wire _T_156 = _T_154 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
wire _T_158 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
wire [4:0] _T_161 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_162 = io_dec_tlu_mrac_ff >> _T_161; // @[el2_ifu_ifc_ctl.scala 140:53]
reg _T_165; // @[el2_ifu_ifc_ctl.scala 142:32]
reg [30:0] _T_167; // @[Reg.scala 27:20]
assign io_ifc_fetch_addr_f = _T_167; // @[el2_ifu_ifc_ctl.scala 144:23]
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
assign io_ifc_fetch_req_f = _T_165; // @[el2_ifu_ifc_ctl.scala 142:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_141; // @[el2_ifu_ifc_ctl.scala 128:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_162[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
assign io_ifc_fetch_req_bf = _T_42 & _T_43; // @[el2_ifu_ifc_ctl.scala 84:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
assign io_ifc_iccm_access_bf = _T_143[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
assign io_ifc_region_acc_fault_bf = _T_158 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
assign io_ifc_dma_access_ok = _T_156 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -211,9 +210,9 @@ initial begin
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_163 = _RAND_5[0:0];
_T_165 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_165 = _RAND_6[30:0];
_T_167 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
@ -231,10 +230,10 @@ initial begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_163 = 1'h0;
_T_165 = 1'h0;
end
if (reset) begin
_T_165 = 31'h0;
_T_167 = 31'h0;
end
`endif // RANDOMIZE
end // initial
@ -253,7 +252,7 @@ end // initial
if (reset) begin
miss_a <= 1'h0;
end else begin
miss_a <= _T_45 & _T_2;
miss_a <= _T_47 & _T_2;
end
end
always @(posedge clock or posedge reset) begin
@ -267,7 +266,7 @@ end // initial
if (reset) begin
fb_write_f <= 4'h0;
end else begin
fb_write_f <= _T_125 | _T_122;
fb_write_f <= _T_127 | _T_124;
end
end
always @(posedge clock or posedge reset) begin
@ -279,16 +278,16 @@ end // initial
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_163 <= 1'h0;
_T_165 <= 1'h0;
end else begin
_T_163 <= io_ifc_fetch_req_bf;
_T_165 <= io_ifc_fetch_req_bf;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_165 <= 31'h0;
_T_167 <= 31'h0;
end else if (fetch_bf_en) begin
_T_165 <= io_ifc_fetch_addr_bf;
_T_167 <= io_ifc_fetch_addr_bf;
end
end
endmodule

18
src/main/scala/ifu/el2_ifu_ic_mem.scala
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@ -186,7 +186,7 @@ class EL2_IC_DATA extends Module with el2_lib {
val ic_sel_premux_data = Input(Bool())
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val scan_mode = Input(UInt(1.W))
val test_in = Input(UInt(71.W))
val test = Output(UInt())
// val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W))))
})
@ -243,12 +243,16 @@ class EL2_IC_DATA extends Module with el2_lib {
//////////////////////////////////////////// Memory stated
val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
// val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
// for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
// when((ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
// data_mem()
// }
// }
val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
// val
when((ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
io.test := data_mem(ic_rw_addr_bank_q(k))(k)(i)
}
}
// val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
// ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))
// for(i<-1 until ICACHE_NUM_WAYS){

15
src/main/scala/ifu/el2_ifu_ifc_ctl.scala
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@ -35,8 +35,9 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val ifc_dma_access_ok = Output(Bool())
})
val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U)
val fetch_addr_next = WireInit(UInt(32.W), init = 0.U)
val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U)
val fetch_addr_next_0 = WireInit(Bool(), 0.U)
val fetch_addr_next = WireInit(UInt(31.W), init = 0.U)
val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
val fb_write_f = WireInit(UInt(4.W), init = 0.U)
val fb_full_f_ns = WireInit(Bool(), init = 0.U)
@ -73,12 +74,10 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
//io.test_out := io.ifc_fetch_addr_bf
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := (address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
val fetch_addr_next_1 = Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0))
fetch_addr_next := Cat(io.ifc_fetch_addr_f(30,1)+1.U, 0.U) //|
//Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
io.ifc_fetch_req_bf_raw := ~idle
@ -137,7 +136,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
io.ifc_region_acc_fault_bf := ~iccm_acc_in_range_bf & iccm_acc_in_region_bf
io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)

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target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module
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target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class
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target/scala-2.12/classes/ifu/ifu_ic$.class
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target/scala-2.12/classes/ifu/ifu_ifc$.class
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