From 6cc820187215a5ca2313b8731a97bc7a93bc48e3 Mon Sep 17 00:00:00 2001
From: waleed-lm <waleed.ehsan@lampromellon.com>
Date: Mon, 28 Sep 2020 17:52:50 +0500
Subject: [PATCH] IFC

---
 el2_ifu_ifc_ctrl.fir                          | 318 +++++++++---------
 el2_ifu_ifc_ctrl.v                            | 160 +++++----
 src/main/scala/ifu/el2_ifu_ifc_ctrl.scala     |   4 +-
 .../classes/ifu/el2_ifu_ifc_ctrl.class        | Bin 111812 -> 110417 bytes
 4 files changed, 238 insertions(+), 244 deletions(-)

diff --git a/el2_ifu_ifc_ctrl.fir b/el2_ifu_ifc_ctrl.fir
index a478018e..77e0d691 100644
--- a/el2_ifu_ifc_ctrl.fir
+++ b/el2_ifu_ifc_ctrl.fir
@@ -86,170 +86,166 @@ circuit el2_ifu_ifc_ctrl :
     _T_27 <= _T_26 @[Mux.scala 27:72]
     io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 81:24]
     line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 88:13]
-    node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 90:46]
-    node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 90:52]
-    node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 90:52]
-    node _T_31 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:25]
-    node _T_32 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:53]
-    node _T_33 = mux(_T_31, UInt<1>("h00"), _T_32) @[el2_ifu_ifc_ctrl.scala 91:8]
-    node _T_34 = or(_T_30, _T_33) @[el2_ifu_ifc_ctrl.scala 90:58]
-    fetch_addr_next <= _T_34 @[el2_ifu_ifc_ctrl.scala 90:19]
-    node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
-    io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 93:27]
-    node _T_36 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
-    node _T_37 = not(_T_36) @[el2_ifu_ifc_ctrl.scala 95:70]
-    node _T_38 = and(fb_full_f_ns, _T_37) @[el2_ifu_ifc_ctrl.scala 95:68]
-    node _T_39 = not(_T_38) @[el2_ifu_ifc_ctrl.scala 95:53]
-    node _T_40 = and(io.ifc_fetch_req_bf_raw, _T_39) @[el2_ifu_ifc_ctrl.scala 95:51]
-    node _T_41 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 96:5]
-    node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 95:114]
-    node _T_43 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 96:18]
-    node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctrl.scala 96:16]
-    node _T_45 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 96:39]
-    node _T_46 = and(_T_44, _T_45) @[el2_ifu_ifc_ctrl.scala 96:37]
-    io.ifc_fetch_req_bf <= _T_46 @[el2_ifu_ifc_ctrl.scala 95:23]
-    node _T_47 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 98:37]
-    fetch_bf_en <= _T_47 @[el2_ifu_ifc_ctrl.scala 98:15]
-    node _T_48 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 100:34]
-    node _T_49 = and(io.ifc_fetch_req_f, _T_48) @[el2_ifu_ifc_ctrl.scala 100:32]
-    node _T_50 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 100:49]
-    node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 100:47]
-    miss_f <= _T_51 @[el2_ifu_ifc_ctrl.scala 100:10]
-    node _T_52 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 102:39]
-    node _T_53 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:63]
-    node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 102:61]
-    node _T_55 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 102:76]
-    node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctrl.scala 102:74]
-    node _T_57 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 102:86]
-    node _T_58 = and(_T_56, _T_57) @[el2_ifu_ifc_ctrl.scala 102:84]
-    mb_empty_mod <= _T_58 @[el2_ifu_ifc_ctrl.scala 102:16]
-    node _T_59 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 104:35]
-    goto_idle <= _T_59 @[el2_ifu_ifc_ctrl.scala 104:13]
-    node _T_60 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:38]
-    node _T_61 = and(io.exu_flush_final, _T_60) @[el2_ifu_ifc_ctrl.scala 106:36]
-    node _T_62 = and(_T_61, idle) @[el2_ifu_ifc_ctrl.scala 106:67]
-    leave_idle <= _T_62 @[el2_ifu_ifc_ctrl.scala 106:14]
-    node _T_63 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 108:29]
-    node _T_64 = not(_T_63) @[el2_ifu_ifc_ctrl.scala 108:23]
-    node _T_65 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 108:40]
-    node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 108:33]
-    node _T_67 = and(_T_66, miss_f) @[el2_ifu_ifc_ctrl.scala 108:44]
-    node _T_68 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 108:55]
-    node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 108:53]
-    node _T_70 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 109:11]
-    node _T_71 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 109:17]
-    node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 109:15]
-    node _T_73 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 109:33]
-    node _T_74 = and(_T_72, _T_73) @[el2_ifu_ifc_ctrl.scala 109:31]
-    node next_state_1 = or(_T_69, _T_74) @[el2_ifu_ifc_ctrl.scala 108:67]
-    node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:23]
-    node _T_76 = and(_T_75, leave_idle) @[el2_ifu_ifc_ctrl.scala 111:34]
-    node _T_77 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 111:56]
-    node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:62]
-    node _T_79 = and(_T_77, _T_78) @[el2_ifu_ifc_ctrl.scala 111:60]
-    node next_state_0 = or(_T_76, _T_79) @[el2_ifu_ifc_ctrl.scala 111:48]
-    node _T_80 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
-    reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
-    _T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 113:19]
-    state <= _T_81 @[el2_ifu_ifc_ctrl.scala 113:9]
+    node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 90:42]
+    node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 90:48]
+    node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 90:48]
+    fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctrl.scala 90:19]
+    node _T_31 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
+    io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctrl.scala 93:27]
+    node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
+    node _T_33 = not(_T_32) @[el2_ifu_ifc_ctrl.scala 95:70]
+    node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctrl.scala 95:68]
+    node _T_35 = not(_T_34) @[el2_ifu_ifc_ctrl.scala 95:53]
+    node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctrl.scala 95:51]
+    node _T_37 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 96:5]
+    node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctrl.scala 95:114]
+    node _T_39 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 96:18]
+    node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctrl.scala 96:16]
+    node _T_41 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 96:39]
+    node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 96:37]
+    io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctrl.scala 95:23]
+    node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 98:37]
+    fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctrl.scala 98:15]
+    node _T_44 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 100:34]
+    node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctrl.scala 100:32]
+    node _T_46 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 100:49]
+    node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 100:47]
+    miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 100:10]
+    node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 102:39]
+    node _T_49 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:63]
+    node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 102:61]
+    node _T_51 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 102:76]
+    node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 102:74]
+    node _T_53 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 102:86]
+    node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 102:84]
+    mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctrl.scala 102:16]
+    node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 104:35]
+    goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 104:13]
+    node _T_56 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:38]
+    node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctrl.scala 106:36]
+    node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctrl.scala 106:67]
+    leave_idle <= _T_58 @[el2_ifu_ifc_ctrl.scala 106:14]
+    node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 108:29]
+    node _T_60 = not(_T_59) @[el2_ifu_ifc_ctrl.scala 108:23]
+    node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 108:40]
+    node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 108:33]
+    node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctrl.scala 108:44]
+    node _T_64 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 108:55]
+    node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctrl.scala 108:53]
+    node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 109:11]
+    node _T_67 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 109:17]
+    node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctrl.scala 109:15]
+    node _T_69 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 109:33]
+    node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctrl.scala 109:31]
+    node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctrl.scala 108:67]
+    node _T_71 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:23]
+    node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctrl.scala 111:34]
+    node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 111:56]
+    node _T_74 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:62]
+    node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 111:60]
+    node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 111:48]
+    node _T_76 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
+    reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
+    _T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 113:19]
+    state <= _T_77 @[el2_ifu_ifc_ctrl.scala 113:9]
     flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 118:12]
-    node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 120:38]
-    node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 120:36]
-    node _T_84 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 120:61]
-    node _T_85 = or(_T_84, miss_f) @[el2_ifu_ifc_ctrl.scala 120:81]
-    node _T_86 = and(_T_83, _T_85) @[el2_ifu_ifc_ctrl.scala 120:58]
-    node _T_87 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:25]
-    node _T_88 = or(_T_86, _T_87) @[el2_ifu_ifc_ctrl.scala 120:92]
-    fb_right <= _T_88 @[el2_ifu_ifc_ctrl.scala 120:12]
-    node _T_89 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 123:39]
-    node _T_90 = or(_T_89, miss_f) @[el2_ifu_ifc_ctrl.scala 123:59]
-    node _T_91 = and(io.ifu_fb_consume2, _T_90) @[el2_ifu_ifc_ctrl.scala 123:36]
-    fb_right2 <= _T_91 @[el2_ifu_ifc_ctrl.scala 123:13]
-    node _T_92 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 124:56]
-    node _T_93 = not(_T_92) @[el2_ifu_ifc_ctrl.scala 124:35]
-    node _T_94 = and(io.ifc_fetch_req_f, _T_93) @[el2_ifu_ifc_ctrl.scala 124:33]
-    node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 124:80]
-    node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 124:78]
-    fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 124:11]
-    node _T_97 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 126:37]
-    node _T_98 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 127:6]
-    node _T_99 = and(_T_98, fb_right) @[el2_ifu_ifc_ctrl.scala 127:16]
-    node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:28]
-    node _T_101 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 127:62]
-    node _T_102 = cat(UInt<1>("h00"), _T_101) @[Cat.scala 29:58]
-    node _T_103 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
-    node _T_104 = and(_T_103, fb_right2) @[el2_ifu_ifc_ctrl.scala 128:16]
-    node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:29]
-    node _T_106 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 128:63]
-    node _T_107 = cat(UInt<2>("h00"), _T_106) @[Cat.scala 29:58]
-    node _T_108 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
-    node _T_109 = and(_T_108, fb_left) @[el2_ifu_ifc_ctrl.scala 129:16]
-    node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:27]
-    node _T_111 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 129:51]
-    node _T_112 = cat(_T_111, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_113 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
-    node _T_114 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 130:18]
-    node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 130:16]
-    node _T_116 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 130:30]
-    node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 130:28]
-    node _T_118 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 130:43]
-    node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 130:41]
-    node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:53]
-    node _T_121 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 130:73]
-    node _T_122 = mux(_T_97, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_123 = mux(_T_100, _T_102, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_124 = mux(_T_105, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_125 = mux(_T_110, _T_112, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_126 = mux(_T_120, _T_121, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_127 = or(_T_122, _T_123) @[Mux.scala 27:72]
-    node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
-    node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
-    node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72]
-    wire _T_131 : UInt<4> @[Mux.scala 27:72]
-    _T_131 <= _T_130 @[Mux.scala 27:72]
-    fb_write_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 126:15]
-    node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 133:38]
-    reg _T_133 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 133:26]
-    _T_133 <= _T_132 @[el2_ifu_ifc_ctrl.scala 133:26]
-    fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 133:16]
-    node _T_134 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 135:17]
-    idle <= _T_134 @[el2_ifu_ifc_ctrl.scala 135:8]
-    node _T_135 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 136:16]
-    wfm <= _T_135 @[el2_ifu_ifc_ctrl.scala 136:7]
-    node _T_136 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 138:30]
-    fb_full_f_ns <= _T_136 @[el2_ifu_ifc_ctrl.scala 138:16]
+    node _T_78 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 120:38]
+    node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctrl.scala 120:36]
+    node _T_80 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 120:61]
+    node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctrl.scala 120:81]
+    node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctrl.scala 120:58]
+    node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:25]
+    node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctrl.scala 120:92]
+    fb_right <= _T_84 @[el2_ifu_ifc_ctrl.scala 120:12]
+    node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 123:39]
+    node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctrl.scala 123:59]
+    node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctrl.scala 123:36]
+    fb_right2 <= _T_87 @[el2_ifu_ifc_ctrl.scala 123:13]
+    node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 124:56]
+    node _T_89 = not(_T_88) @[el2_ifu_ifc_ctrl.scala 124:35]
+    node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctrl.scala 124:33]
+    node _T_91 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 124:80]
+    node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctrl.scala 124:78]
+    fb_left <= _T_92 @[el2_ifu_ifc_ctrl.scala 124:11]
+    node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 126:37]
+    node _T_94 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 127:6]
+    node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctrl.scala 127:16]
+    node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:28]
+    node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 127:62]
+    node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
+    node _T_99 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
+    node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctrl.scala 128:16]
+    node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:29]
+    node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 128:63]
+    node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
+    node _T_104 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
+    node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctrl.scala 129:16]
+    node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:27]
+    node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 129:51]
+    node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_109 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
+    node _T_110 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 130:18]
+    node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctrl.scala 130:16]
+    node _T_112 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 130:30]
+    node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctrl.scala 130:28]
+    node _T_114 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 130:43]
+    node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 130:41]
+    node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:53]
+    node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 130:73]
+    node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_121 = mux(_T_106, _T_108, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_122 = mux(_T_116, _T_117, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_123 = or(_T_118, _T_119) @[Mux.scala 27:72]
+    node _T_124 = or(_T_123, _T_120) @[Mux.scala 27:72]
+    node _T_125 = or(_T_124, _T_121) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
+    wire _T_127 : UInt<4> @[Mux.scala 27:72]
+    _T_127 <= _T_126 @[Mux.scala 27:72]
+    fb_write_ns <= _T_127 @[el2_ifu_ifc_ctrl.scala 126:15]
+    node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 133:38]
+    reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 133:26]
+    _T_129 <= _T_128 @[el2_ifu_ifc_ctrl.scala 133:26]
+    fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctrl.scala 133:16]
+    node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 135:17]
+    idle <= _T_130 @[el2_ifu_ifc_ctrl.scala 135:8]
+    node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 136:16]
+    wfm <= _T_131 @[el2_ifu_ifc_ctrl.scala 136:7]
+    node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 138:30]
+    fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctrl.scala 138:16]
     reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 139:26]
     fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 139:26]
-    reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:24]
-    _T_137 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 140:24]
-    fb_write_f <= _T_137 @[el2_ifu_ifc_ctrl.scala 140:14]
-    node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
-    node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
-    node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 143:5]
-    node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 142:75]
-    node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
-    node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 142:60]
-    node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 142:33]
-    io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 142:26]
-    node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 214:25]
-    node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 214:47]
-    node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 217:14]
-    node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
+    reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:24]
+    _T_133 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 140:24]
+    fb_write_f <= _T_133 @[el2_ifu_ifc_ctrl.scala 140:14]
+    node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
+    node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
+    node _T_136 = not(_T_135) @[el2_ifu_ifc_ctrl.scala 143:5]
+    node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctrl.scala 142:75]
+    node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
+    node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctrl.scala 142:60]
+    node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctrl.scala 142:33]
+    io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctrl.scala 142:26]
+    node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 214:25]
+    node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 214:47]
+    node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 217:14]
+    node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
     io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
-    node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
-    node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 150:53]
-    node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
-    node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 150:34]
-    io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 150:31]
-    reg _T_153 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 154:32]
-    _T_153 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 154:32]
-    io.ifc_fetch_req_f <= _T_153 @[el2_ifu_ifc_ctrl.scala 154:22]
-    node _T_154 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 157:88]
-    reg _T_155 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_154 : @[Reg.scala 28:19]
-      _T_155 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
+    node _T_144 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
+    node _T_145 = cat(_T_144, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_146 = dshr(io.dec_tlu_mrac_ff, _T_145) @[el2_ifu_ifc_ctrl.scala 150:53]
+    node _T_147 = bits(_T_146, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
+    node _T_148 = not(_T_147) @[el2_ifu_ifc_ctrl.scala 150:34]
+    io.ifc_fetch_uncacheable_bf <= _T_148 @[el2_ifu_ifc_ctrl.scala 150:31]
+    reg _T_149 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 154:32]
+    _T_149 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 154:32]
+    io.ifc_fetch_req_f <= _T_149 @[el2_ifu_ifc_ctrl.scala 154:22]
+    node _T_150 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 157:88]
+    reg _T_151 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_150 : @[Reg.scala 28:19]
+      _T_151 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.ifc_fetch_addr_f <= _T_155 @[el2_ifu_ifc_ctrl.scala 157:23]
+    io.ifc_fetch_addr_f <= _T_151 @[el2_ifu_ifc_ctrl.scala 157:23]
     
diff --git a/el2_ifu_ifc_ctrl.v b/el2_ifu_ifc_ctrl.v
index 223202da..7611b90c 100644
--- a/el2_ifu_ifc_ctrl.v
+++ b/el2_ifu_ifc_ctrl.v
@@ -53,93 +53,91 @@ module el2_ifu_ifc_ctrl(
   wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_21 = io_sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_22 = io_sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
-  wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 90:52]
-  wire [29:0] _GEN_1 = {{29'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 90:58]
-  wire [29:0] _T_34 = _T_30 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 90:58]
-  wire [31:0] fetch_addr_next = {{2'd0}, _T_34}; // @[el2_ifu_ifc_ctrl.scala 90:19]
+  wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 90:48]
+  wire [31:0] fetch_addr_next = {{2'd0}, _T_30}; // @[el2_ifu_ifc_ctrl.scala 90:19]
   wire [31:0] _T_23 = io_sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
   wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
-  wire [31:0] _GEN_2 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
-  wire [31:0] _T_26 = _GEN_2 | _T_23; // @[Mux.scala 27:72]
+  wire [31:0] _GEN_1 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
+  wire [31:0] _T_26 = _GEN_1 | _T_23; // @[Mux.scala 27:72]
   reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
   wire  idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 135:17]
-  wire  _T_36 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
-  wire  _T_37 = ~_T_36; // @[el2_ifu_ifc_ctrl.scala 95:70]
-  wire [3:0] _T_122 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
-  wire  _T_82 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 120:38]
-  wire  _T_83 = io_ifu_fb_consume1 & _T_82; // @[el2_ifu_ifc_ctrl.scala 120:36]
-  wire  _T_49 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
-  wire  miss_f = _T_49 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
-  wire  _T_85 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 120:81]
-  wire  _T_86 = _T_83 & _T_85; // @[el2_ifu_ifc_ctrl.scala 120:58]
-  wire  _T_87 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 121:25]
-  wire  fb_right = _T_86 | _T_87; // @[el2_ifu_ifc_ctrl.scala 120:92]
-  wire  _T_99 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 127:16]
+  wire  _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
+  wire  _T_33 = ~_T_32; // @[el2_ifu_ifc_ctrl.scala 95:70]
+  wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
+  wire  _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 120:38]
+  wire  _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctrl.scala 120:36]
+  wire  _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
+  wire  miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
+  wire  _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 120:81]
+  wire  _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctrl.scala 120:58]
+  wire  _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 121:25]
+  wire  fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctrl.scala 120:92]
+  wire  _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 127:16]
   reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 140:24]
-  wire [3:0] _T_102 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_123 = _T_99 ? _T_102 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_127 = _T_122 | _T_123; // @[Mux.scala 27:72]
-  wire  fb_right2 = io_ifu_fb_consume2 & _T_85; // @[el2_ifu_ifc_ctrl.scala 123:36]
-  wire  _T_104 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 128:16]
-  wire [3:0] _T_107 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_124 = _T_104 ? _T_107 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
-  wire  _T_92 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 124:56]
-  wire  _T_93 = ~_T_92; // @[el2_ifu_ifc_ctrl.scala 124:35]
-  wire  _T_94 = io_ifc_fetch_req_f & _T_93; // @[el2_ifu_ifc_ctrl.scala 124:33]
-  wire  _T_95 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 124:80]
-  wire  fb_left = _T_94 & _T_95; // @[el2_ifu_ifc_ctrl.scala 124:78]
-  wire  _T_109 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 129:16]
-  wire [3:0] _T_112 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
-  wire [3:0] _T_125 = _T_109 ? _T_112 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_129 = _T_128 | _T_125; // @[Mux.scala 27:72]
-  wire  _T_114 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 130:18]
-  wire  _T_115 = _T_2 & _T_114; // @[el2_ifu_ifc_ctrl.scala 130:16]
-  wire  _T_116 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 130:30]
-  wire  _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctrl.scala 130:28]
-  wire  _T_118 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 130:43]
-  wire  _T_119 = _T_117 & _T_118; // @[el2_ifu_ifc_ctrl.scala 130:41]
-  wire [3:0] _T_126 = _T_119 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] fb_write_ns = _T_129 | _T_126; // @[Mux.scala 27:72]
+  wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72]
+  wire  fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctrl.scala 123:36]
+  wire  _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 128:16]
+  wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72]
+  wire  _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 124:56]
+  wire  _T_89 = ~_T_88; // @[el2_ifu_ifc_ctrl.scala 124:35]
+  wire  _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctrl.scala 124:33]
+  wire  _T_91 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 124:80]
+  wire  fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctrl.scala 124:78]
+  wire  _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 129:16]
+  wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
+  wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
+  wire  _T_110 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 130:18]
+  wire  _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctrl.scala 130:16]
+  wire  _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 130:30]
+  wire  _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctrl.scala 130:28]
+  wire  _T_114 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 130:43]
+  wire  _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctrl.scala 130:41]
+  wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72]
   wire  fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 138:30]
-  wire  _T_38 = fb_full_f_ns & _T_37; // @[el2_ifu_ifc_ctrl.scala 95:68]
-  wire  _T_39 = ~_T_38; // @[el2_ifu_ifc_ctrl.scala 95:53]
-  wire  _T_40 = io_ifc_fetch_req_bf_raw & _T_39; // @[el2_ifu_ifc_ctrl.scala 95:51]
-  wire  _T_41 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 96:5]
-  wire  _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 95:114]
-  wire  _T_43 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 96:18]
-  wire  _T_44 = _T_42 & _T_43; // @[el2_ifu_ifc_ctrl.scala 96:16]
-  wire  _T_45 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 96:39]
+  wire  _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctrl.scala 95:68]
+  wire  _T_35 = ~_T_34; // @[el2_ifu_ifc_ctrl.scala 95:53]
+  wire  _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctrl.scala 95:51]
+  wire  _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 96:5]
+  wire  _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctrl.scala 95:114]
+  wire  _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 96:18]
+  wire  _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctrl.scala 96:16]
+  wire  _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 96:39]
   wire  fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 98:37]
   wire  goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 104:35]
-  wire  _T_61 = io_exu_flush_final & _T_45; // @[el2_ifu_ifc_ctrl.scala 106:36]
-  wire  leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 106:67]
-  wire  _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 108:55]
-  wire  _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 111:34]
-  wire  _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 111:60]
-  wire  next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 111:48]
-  wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
+  wire  _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctrl.scala 106:36]
+  wire  leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctrl.scala 106:67]
+  wire  _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 108:55]
+  wire  _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 111:34]
+  wire  _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 111:60]
+  wire  next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 111:48]
+  wire [1:0] _T_76 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
   wire  wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 136:16]
   reg  fb_full_f; // @[el2_ifu_ifc_ctrl.scala 139:26]
-  wire  _T_139 = _T_36 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
-  wire  _T_140 = ~_T_139; // @[el2_ifu_ifc_ctrl.scala 143:5]
-  wire  _T_141 = fb_full_f & _T_140; // @[el2_ifu_ifc_ctrl.scala 142:75]
-  wire  _T_142 = _T_141 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
-  wire  _T_143 = io_ifc_fetch_req_bf_raw & _T_142; // @[el2_ifu_ifc_ctrl.scala 142:60]
-  wire [31:0] _T_145 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
-  wire [4:0] _T_149 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_150 = io_dec_tlu_mrac_ff >> _T_149; // @[el2_ifu_ifc_ctrl.scala 150:53]
-  reg  _T_153; // @[el2_ifu_ifc_ctrl.scala 154:32]
-  reg [30:0] _T_155; // @[Reg.scala 27:20]
-  assign io_ifc_fetch_addr_f = _T_155; // @[el2_ifu_ifc_ctrl.scala 157:23]
+  wire  _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
+  wire  _T_136 = ~_T_135; // @[el2_ifu_ifc_ctrl.scala 143:5]
+  wire  _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctrl.scala 142:75]
+  wire  _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
+  wire  _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctrl.scala 142:60]
+  wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
+  wire [4:0] _T_145 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_146 = io_dec_tlu_mrac_ff >> _T_145; // @[el2_ifu_ifc_ctrl.scala 150:53]
+  reg  _T_149; // @[el2_ifu_ifc_ctrl.scala 154:32]
+  reg [30:0] _T_151; // @[Reg.scala 27:20]
+  assign io_ifc_fetch_addr_f = _T_151; // @[el2_ifu_ifc_ctrl.scala 157:23]
   assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 81:24]
-  assign io_ifc_fetch_req_f = _T_153; // @[el2_ifu_ifc_ctrl.scala 154:22]
-  assign io_ifu_pmu_fetch_stall = wfm | _T_143; // @[el2_ifu_ifc_ctrl.scala 142:26]
-  assign io_ifc_fetch_uncacheable_bf = ~_T_150[0]; // @[el2_ifu_ifc_ctrl.scala 150:31]
-  assign io_ifc_fetch_req_bf = _T_44 & _T_45; // @[el2_ifu_ifc_ctrl.scala 95:23]
+  assign io_ifc_fetch_req_f = _T_149; // @[el2_ifu_ifc_ctrl.scala 154:22]
+  assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctrl.scala 142:26]
+  assign io_ifc_fetch_uncacheable_bf = ~_T_146[0]; // @[el2_ifu_ifc_ctrl.scala 150:31]
+  assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 95:23]
   assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
-  assign io_ifc_iccm_access_bf = _T_145[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 149:25]
+  assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 149:25]
   assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:30]
   assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:24]
   assign io_sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 76:23]
@@ -189,9 +187,9 @@ initial begin
   _RAND_3 = {1{`RANDOM}};
   fb_full_f = _RAND_3[0:0];
   _RAND_4 = {1{`RANDOM}};
-  _T_153 = _RAND_4[0:0];
+  _T_149 = _RAND_4[0:0];
   _RAND_5 = {1{`RANDOM}};
-  _T_155 = _RAND_5[30:0];
+  _T_151 = _RAND_5[30:0];
 `endif // RANDOMIZE_REG_INIT
   `endif // RANDOMIZE
 end // initial
@@ -208,7 +206,7 @@ end // initial
     if (reset) begin
       state <= 2'h0;
     end else begin
-      state <= _T_80;
+      state <= _T_76;
     end
     if (reset) begin
       fb_write_f <= 4'h0;
@@ -221,14 +219,14 @@ end // initial
       fb_full_f <= fb_full_f_ns;
     end
     if (reset) begin
-      _T_153 <= 1'h0;
+      _T_149 <= 1'h0;
     end else begin
-      _T_153 <= io_ifc_fetch_req_bf;
+      _T_149 <= io_ifc_fetch_req_bf;
     end
     if (reset) begin
-      _T_155 <= 31'h0;
+      _T_151 <= 31'h0;
     end else if (fetch_bf_en) begin
-      _T_155 <= io_ifc_fetch_addr_bf;
+      _T_151 <= io_ifc_fetch_addr_bf;
     end
   end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
index 12483384..7adeb91f 100644
--- a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
+++ b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
@@ -87,8 +87,8 @@ val io = IO(new Bundle{
 
   line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
 
-  fetch_addr_next := Cat((io.ifc_fetch_addr_f(30,1)+1.U) |
-    Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
+  fetch_addr_next := io.ifc_fetch_addr_f(30,1)+1.U //|
+    //Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
 
   io.ifc_fetch_req_bf_raw := ~idle
 
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class
index 4c011ce0289e24ac4f8bdc07a5ca4835793dbddb..ef7b06d2e034c7d415dd7a102360c04080fc0e02 100644
GIT binary patch
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