IMC DONE
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@ -319,14 +319,6 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
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]
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]
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},
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_data",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_1",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_0"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",
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23528
el2_ifu_mem_ctl.fir
23528
el2_ifu_mem_ctl.fir
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10360
el2_ifu_mem_ctl.v
10360
el2_ifu_mem_ctl.v
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@ -126,10 +126,6 @@ class mem_ctl_bundle extends Bundle with el2_lib{
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val scan_mode = Input(Bool())
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val scan_mode = Input(Bool())
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val data = Output(UInt())
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val ic_miss_buff_half = Output(UInt())
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val ic_wr_ecc = Output(UInt())
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//val miss_buff_data = Output(UInt())
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}
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}
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class el2_ifu_mem_ctl extends Module with el2_lib {
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class el2_ifu_mem_ctl extends Module with el2_lib {
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val io = IO(new mem_ctl_bundle)
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val io = IO(new mem_ctl_bundle)
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@ -347,11 +343,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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val m2 = Module(new rvecc_encode_64())
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val m2 = Module(new rvecc_encode_64())
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m1.io.din := ifu_bus_rdata_ff
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m1.io.din := ifu_bus_rdata_ff
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ic_wr_ecc := m1.io.ecc_out
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ic_wr_ecc := m1.io.ecc_out
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io.ic_wr_ecc := m1.io.ecc_out
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val ic_miss_buff_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ic_miss_buff_half)
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val ic_miss_buff_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ic_miss_buff_half)
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m2.io.din := ic_miss_buff_half
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m2.io.din := ic_miss_buff_half
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ic_miss_buff_ecc := m2.io.ecc_out
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ic_miss_buff_ecc := m2.io.ecc_out
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io.data := Cat(io.ic_wr_data(1),io.ic_wr_data(0))
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val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
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val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
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io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
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io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
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io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
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io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
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@ -369,7 +363,6 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff, if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half),
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ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff, if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half),
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Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
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Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
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io.ic_miss_buff_half := ic_miss_buff_half
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val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
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val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
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val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
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val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
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val reset_beat_cnt = WireInit(Bool(), 0.U)
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val reset_beat_cnt = WireInit(Bool(), 0.U)
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