IMC DONE

el2_ifu_mem_ctl.anno.json

@@ -319,14 +319,6 @@
       "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_data",
-    "sources":[
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_1",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_0"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -126,10 +126,6 @@ class mem_ctl_bundle extends Bundle with el2_lib{
   val iccm_buf_correct_ecc = Output(Bool())
   val iccm_correction_state = Output(Bool())
   val scan_mode = Input(Bool())
-  val data = Output(UInt())
-  val ic_miss_buff_half = Output(UInt())
-  val ic_wr_ecc = Output(UInt())
-  //val miss_buff_data = Output(UInt())
 }
 class el2_ifu_mem_ctl extends Module with el2_lib {
   val io = IO(new mem_ctl_bundle)
@@ -347,11 +343,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val m2 = Module(new rvecc_encode_64())
   m1.io.din := ifu_bus_rdata_ff
   ic_wr_ecc := m1.io.ecc_out
-  io.ic_wr_ecc := m1.io.ecc_out
   val ic_miss_buff_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ic_miss_buff_half)
   m2.io.din := ic_miss_buff_half
   ic_miss_buff_ecc := m2.io.ecc_out
-  io.data := Cat(io.ic_wr_data(1),io.ic_wr_data(0))
   val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
   io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
   io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
@@ -369,7 +363,6 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff,  if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half),
     Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
 
-  io.ic_miss_buff_half := ic_miss_buff_half
   val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
   val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
   val reset_beat_cnt = WireInit(Bool(), 0.U)