IMC DONE

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -632,7 +632,11 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
   val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
   io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
-  val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
+  val m1 = Module(new rvecc_encode)
+  m1.io.din := io.dma_mem_wdata(31,0)
+  val m2 = Module(new rvecc_encode)
+  m2.io.din := io.dma_mem_wdata(63,32)
+  val dma_mem_ecc = Cat(m2.io.ecc_out, m1.io.ecc_out)
   val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
   io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
     Cat(dma_mem_ecc(13,7),io.dma_mem_wdata(63,32), dma_mem_ecc(6,0), io.dma_mem_wdata(31,0)))

src/main/scala/lib/el2_lib.scala

@@ -268,6 +268,40 @@ trait el2_lib extends param{
     Cat(din.xorR ^ w6.xorR, w6)
   }
 
+  class rvecc_encode extends Module{   //Done for verification and testing
+    val io      =  IO(new Bundle{
+      val din     =  Input(UInt(32.W))
+      val ecc_out =  Output(UInt(7.W))
+    })
+    val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
+    val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
+    val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
+    val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+    val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+    val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
+
+    val w0 = Wire(Vec(18,UInt(1.W)))
+    val w1 = Wire(Vec(18,UInt(1.W)))
+    val w2 = Wire(Vec(18,UInt(1.W)))
+    val w3 = Wire(Vec(15,UInt(1.W)))
+    val w4 = Wire(Vec(15,UInt(1.W)))
+    val w5 = Wire(Vec(6, UInt(1.W)))
+    var j = 0;var k = 0;var m = 0;
+    var x = 0;var y = 0;var z = 0;
+
+    for(i <- 0 to 31)
+    {
+      if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+      if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+      if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+      if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
+      if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
+      if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
+    }
+    val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
+    io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
+  }
+
 
   def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= {
     val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)