From 7033394ff17d47a1c599b265cde308d4c257eba6 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 10 Dec 2020 10:30:08 +0500 Subject: [PATCH] Only 1 obj --- quasar_wrapper.fir | 594 +++++------ quasar_wrapper.v | 974 +++++++++--------- src/main/scala/dec/dec.scala | 4 - src/main/scala/ifu/ifu.scala | 5 - src/main/scala/lib/ahb_to_axi4.scala | 5 +- src/main/scala/mem.scala | 6 +- src/main/scala/pic_ctrl.scala | 5 - src/main/scala/quasar.scala | 2 - src/main/scala/quasar_wrapper.scala | 158 ++- target/scala-2.12/classes/QUASAR_Wrp$.class | Bin 3859 -> 3859 bytes .../classes/QUASAR_Wrp$delayedInit$body.class | Bin 729 -> 729 bytes target/scala-2.12/classes/dec/dec_main$.class | Bin 3844 -> 0 bytes .../dec/dec_main$delayedInit$body.class | Bin 730 -> 0 bytes target/scala-2.12/classes/dec/dec_main.class | Bin 773 -> 0 bytes target/scala-2.12/classes/ifu/ifu$.class | Bin 3819 -> 0 bytes .../classes/ifu/ifu$delayedInit$body.class | Bin 700 -> 0 bytes target/scala-2.12/classes/ifu/ifu.class | Bin 121827 -> 121341 bytes target/scala-2.12/classes/lib/AHB_main$.class | Bin 3903 -> 0 bytes .../lib/AHB_main$delayedInit$body.class | Bin 738 -> 0 bytes target/scala-2.12/classes/lib/AHB_main.class | Bin 781 -> 0 bytes target/scala-2.12/classes/mem/mem$.class | Bin 3837 -> 0 bytes .../classes/mem/mem$delayedInit$body.class | Bin 700 -> 0 bytes target/scala-2.12/classes/mem/mem.class | Bin 741 -> 0 bytes target/scala-2.12/classes/pic_main$.class | Bin 3872 -> 0 bytes .../classes/pic_main$delayedInit$body.class | Bin 711 -> 0 bytes target/scala-2.12/classes/pic_main.class | Bin 771 -> 0 bytes target/scala-2.12/classes/quasar.class | Bin 202229 -> 202229 bytes .../scala-2.12/classes/quasar_wrapper.class | Bin 94077 -> 93877 bytes 28 files changed, 857 insertions(+), 896 deletions(-) delete mode 100644 target/scala-2.12/classes/dec/dec_main$.class delete mode 100644 target/scala-2.12/classes/dec/dec_main$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/dec/dec_main.class delete mode 100644 target/scala-2.12/classes/ifu/ifu$.class delete mode 100644 target/scala-2.12/classes/ifu/ifu$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/lib/AHB_main$.class delete mode 100644 target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/lib/AHB_main.class delete mode 100644 target/scala-2.12/classes/mem/mem$.class delete mode 100644 target/scala-2.12/classes/mem/mem$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/mem/mem.class delete mode 100644 target/scala-2.12/classes/pic_main$.class delete mode 100644 target/scala-2.12/classes/pic_main$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/pic_main.class diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index c4e30559..35649429 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -64248,7 +64248,7 @@ circuit quasar_wrapper : io.iccm_dma_rdata <= mem_ctl.io.iccm_dma_rdata @[ifu.scala 115:21] io.iccm_dma_rtag <= mem_ctl.io.iccm_dma_rtag @[ifu.scala 116:20] io.iccm_ready <= mem_ctl.io.iccm_ready @[ifu.scala 117:17] - io.iccm_dma_sb_error <= mem_ctl.io.iccm_dma_sb_error @[ifu.scala 119:24] + io.iccm_dma_sb_error <= mem_ctl.io.iccm_dma_sb_error @[ifu.scala 118:24] module dec_ib_ctl : input clock : Clock @@ -114627,35 +114627,35 @@ circuit quasar_wrapper : io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 480:22] io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 481:18] skip @[quasar.scala 296:26] - else : @[quasar.scala 485:17] - io.haddr <= UInt<1>("h00") @[quasar.scala 487:18] - io.hburst <= UInt<1>("h00") @[quasar.scala 488:19] - io.hmastlock <= UInt<1>("h00") @[quasar.scala 489:22] - io.hprot <= UInt<1>("h00") @[quasar.scala 490:18] - io.hsize <= UInt<1>("h00") @[quasar.scala 491:18] - io.htrans <= UInt<1>("h00") @[quasar.scala 492:19] - io.hwrite <= UInt<1>("h00") @[quasar.scala 493:19] - io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 496:22] - io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 497:23] - io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 498:26] - io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 499:22] - io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 500:22] - io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 501:23] - io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 502:23] - io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 503:23] - io.sb_haddr <= UInt<1>("h00") @[quasar.scala 505:21] - io.sb_hburst <= UInt<1>("h00") @[quasar.scala 506:22] - io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 507:25] - io.sb_hprot <= UInt<1>("h00") @[quasar.scala 508:21] - io.sb_hsize <= UInt<1>("h00") @[quasar.scala 509:21] - io.sb_htrans <= UInt<1>("h00") @[quasar.scala 510:22] - io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 511:22] - io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 512:22] - io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 514:23] - io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 515:26] - io.dma_hresp <= UInt<1>("h00") @[quasar.scala 516:22] - skip @[quasar.scala 485:17] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 518:20] + else : @[quasar.scala 483:17] + io.haddr <= UInt<1>("h00") @[quasar.scala 485:18] + io.hburst <= UInt<1>("h00") @[quasar.scala 486:19] + io.hmastlock <= UInt<1>("h00") @[quasar.scala 487:22] + io.hprot <= UInt<1>("h00") @[quasar.scala 488:18] + io.hsize <= UInt<1>("h00") @[quasar.scala 489:18] + io.htrans <= UInt<1>("h00") @[quasar.scala 490:19] + io.hwrite <= UInt<1>("h00") @[quasar.scala 491:19] + io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 494:22] + io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 495:23] + io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 496:26] + io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 497:22] + io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 498:22] + io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 499:23] + io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 500:23] + io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 501:23] + io.sb_haddr <= UInt<1>("h00") @[quasar.scala 503:21] + io.sb_hburst <= UInt<1>("h00") @[quasar.scala 504:22] + io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 505:25] + io.sb_hprot <= UInt<1>("h00") @[quasar.scala 506:21] + io.sb_hsize <= UInt<1>("h00") @[quasar.scala 507:21] + io.sb_htrans <= UInt<1>("h00") @[quasar.scala 508:22] + io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 509:22] + io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 510:22] + io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 512:23] + io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 513:26] + io.dma_hresp <= UInt<1>("h00") @[quasar.scala 514:22] + skip @[quasar.scala 483:17] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 516:20] module quasar_wrapper : input clock : Clock @@ -114688,282 +114688,282 @@ circuit quasar_wrapper : dmi_wrapper.tms is invalid dmi_wrapper.tck is invalid dmi_wrapper.trst_n is invalid - inst swerv of quasar @[quasar_wrapper.scala 80:21] - swerv.clock <= clock - swerv.reset <= reset + inst core of quasar @[quasar_wrapper.scala 80:20] + core.clock <= clock + core.reset <= reset dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25] dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22] dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22] dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22] dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27] dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26] - dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26] + dmi_wrapper.rd_data <= core.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26] dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29] - swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:26] - swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:25] - swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:23] - swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:26] - swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:27] + core.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:25] + core.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:24] + core.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:22] + core.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:25] + core.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:26] io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15] - mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 99:28] - mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 100:27] - mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35] - swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15] - swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15] - mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15] - mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 102:15] - mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 102:15] + mem.dccm_clk_override <= core.io.dccm_clk_override @[quasar_wrapper.scala 99:28] + mem.icm_clk_override <= core.io.icm_clk_override @[quasar_wrapper.scala 100:27] + mem.dec_tlu_core_ecc_disable <= core.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35] + core.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15] + core.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15] + mem.dccm.wr_data_hi <= core.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15] + mem.dccm.wr_data_lo <= core.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15] + mem.dccm.rd_addr_hi <= core.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15] + mem.dccm.rd_addr_lo <= core.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15] + mem.dccm.wr_addr_hi <= core.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15] + mem.dccm.wr_addr_lo <= core.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15] + mem.dccm.rden <= core.io.dccm.rden @[quasar_wrapper.scala 102:15] + mem.dccm.wren <= core.io.dccm.wren @[quasar_wrapper.scala 102:15] mem.rst_l <= reset @[quasar_wrapper.scala 103:16] mem.clk <= clock @[quasar_wrapper.scala 104:14] mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:22] - mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 108:15] - mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 108:15] - mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 108:15] - mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 108:15] - mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 108:15] - mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 108:15] - swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:15] - swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:15] - swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:15] - swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:15] - swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:15] - swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:15] - swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:15] - mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 108:15] - mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 108:15] - mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 108:15] - mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 108:15] - mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 108:15] - mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 108:15] - mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 108:15] - mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 108:15] - swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:17] - swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:17] - mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 109:17] - mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 109:17] - mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 109:17] - mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 109:17] - mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 109:17] - mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:17] - mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 109:17] - swerv.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:22] - swerv.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:19] - swerv.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:21] - swerv.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:23] - swerv.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:22] - swerv.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:23] - swerv.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:19] - swerv.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:18] - swerv.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:22] - swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:22] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:22] - swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:20] - swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:20] - swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:20] - swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:27] - swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:26] - swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 129:20] - swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:31] - swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:30] - swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:30] - swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:20] - io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:20] - io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:20] - io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:20] - io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:20] - io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:20] - io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:20] - io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:20] - io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:20] - swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:20] - swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:20] - io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:20] - io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:20] - io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:20] - io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:20] - io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:20] - io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:20] - io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:20] - io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:20] - swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:20] - swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:19] - io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:19] - io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:19] - io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 144:19] - io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:19] - io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:19] - io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:19] - io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:19] - io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:19] - swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:19] - io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:20] - io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:20] - io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:20] - io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:20] - io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:20] - io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:20] - io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:20] - io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:20] - io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:20] - io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:20] - swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:20] - io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:20] - swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:21] - swerv.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:22] - swerv.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:23] - swerv.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:26] - swerv.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:22] - swerv.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:22] - swerv.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:23] - swerv.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:23] - swerv.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:23] - swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:25] - swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 178:27] - swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 179:27] - swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 180:27] - swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 181:27] - swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 183:22] - swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 184:21] - swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 185:26] - io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 189:19] - io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 189:19] - io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 192:21] - io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 193:24] - io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 194:20] - io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 195:26] - io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 197:25] - io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 198:24] - io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 199:25] - io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 201:23] - io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 202:23] - io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 203:23] - io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 204:23] - io.dma_hrdata <= swerv.io.dma_hrdata @[quasar_wrapper.scala 211:17] - io.dma_hreadyout <= swerv.io.dma_hreadyout @[quasar_wrapper.scala 212:20] - io.dma_hresp <= swerv.io.dma_hresp @[quasar_wrapper.scala 213:16] + core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:21] + mem.ic.sel_premux_data <= core.io.ic.sel_premux_data @[quasar_wrapper.scala 108:14] + mem.ic.premux_data <= core.io.ic.premux_data @[quasar_wrapper.scala 108:14] + mem.ic.debug_way <= core.io.ic.debug_way @[quasar_wrapper.scala 108:14] + mem.ic.debug_tag_array <= core.io.ic.debug_tag_array @[quasar_wrapper.scala 108:14] + mem.ic.debug_wr_en <= core.io.ic.debug_wr_en @[quasar_wrapper.scala 108:14] + mem.ic.debug_rd_en <= core.io.ic.debug_rd_en @[quasar_wrapper.scala 108:14] + core.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:14] + core.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:14] + core.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:14] + core.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:14] + core.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:14] + core.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:14] + core.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:14] + mem.ic.debug_addr <= core.io.ic.debug_addr @[quasar_wrapper.scala 108:14] + mem.ic.debug_wr_data <= core.io.ic.debug_wr_data @[quasar_wrapper.scala 108:14] + mem.ic.wr_data[0] <= core.io.ic.wr_data[0] @[quasar_wrapper.scala 108:14] + mem.ic.wr_data[1] <= core.io.ic.wr_data[1] @[quasar_wrapper.scala 108:14] + mem.ic.rd_en <= core.io.ic.rd_en @[quasar_wrapper.scala 108:14] + mem.ic.wr_en <= core.io.ic.wr_en @[quasar_wrapper.scala 108:14] + mem.ic.tag_valid <= core.io.ic.tag_valid @[quasar_wrapper.scala 108:14] + mem.ic.rw_addr <= core.io.ic.rw_addr @[quasar_wrapper.scala 108:14] + core.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:16] + core.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:16] + mem.iccm.wr_data <= core.io.iccm.wr_data @[quasar_wrapper.scala 109:16] + mem.iccm.wr_size <= core.io.iccm.wr_size @[quasar_wrapper.scala 109:16] + mem.iccm.rden <= core.io.iccm.rden @[quasar_wrapper.scala 109:16] + mem.iccm.wren <= core.io.iccm.wren @[quasar_wrapper.scala 109:16] + mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 109:16] + mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:16] + mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 109:16] + core.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:21] + core.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:18] + core.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:20] + core.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:22] + core.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:21] + core.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:22] + core.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:18] + core.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:17] + core.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:21] + core.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:21] + core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] + core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] + core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] + core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19] + core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26] + core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25] + core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19] + core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30] + core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29] + core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29] + core.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:19] + io.lsu_axi.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:19] + io.lsu_axi.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:19] + io.lsu_axi.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:19] + io.lsu_axi.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:19] + io.lsu_axi.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:19] + io.lsu_axi.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:19] + io.lsu_axi.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:19] + io.lsu_axi.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:19] + core.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:19] + core.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:19] + io.ifu_axi.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:19] + io.ifu_axi.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:19] + io.ifu_axi.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:19] + io.ifu_axi.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:19] + io.ifu_axi.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:19] + io.ifu_axi.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:19] + io.ifu_axi.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:19] + io.ifu_axi.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:19] + core.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:19] + core.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:18] + core.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:18] + core.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:18] + core.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:18] + core.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:18] + io.sb_axi.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:18] + io.sb_axi.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:18] + core.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:18] + core.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:18] + core.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:18] + core.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:18] + io.sb_axi.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 144:18] + io.sb_axi.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:18] + io.sb_axi.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:18] + io.sb_axi.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:18] + io.sb_axi.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 144:18] + core.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:18] + io.sb_axi.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:18] + core.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:18] + io.dma_axi.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:19] + io.dma_axi.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:19] + io.dma_axi.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:19] + io.dma_axi.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:19] + io.dma_axi.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 148:19] + core.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:19] + core.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:19] + io.dma_axi.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:19] + io.dma_axi.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:19] + io.dma_axi.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:19] + io.dma_axi.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 148:19] + core.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:19] + core.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:19] + core.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:19] + core.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:19] + core.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:19] + io.dma_axi.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:19] + core.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:19] + io.dma_axi.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:19] + core.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:20] + core.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:21] + core.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:22] + core.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:25] + core.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:21] + core.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:21] + core.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:22] + core.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:22] + core.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:22] + core.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:24] + core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 162:26] + core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 163:26] + core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 164:26] + core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 165:26] + core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 167:21] + core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 168:20] + core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 169:25] + io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 173:19] + io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 173:19] + io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 176:21] + io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 177:24] + io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 178:20] + io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 179:26] + io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 181:25] + io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 182:24] + io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 183:25] + io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 185:23] + io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 186:23] + io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 187:23] + io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 188:23] + io.dma_hrdata <= core.io.dma_hrdata @[quasar_wrapper.scala 195:17] + io.dma_hreadyout <= core.io.dma_hreadyout @[quasar_wrapper.scala 196:20] + io.dma_hresp <= core.io.dma_hresp @[quasar_wrapper.scala 197:16] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 899d97f5..7c3227b3 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -45055,7 +45055,7 @@ module ifu( assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] assign io_iccm_dma_rtag = mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 116:20] assign io_iccm_ready = mem_ctl_io_iccm_ready; // @[ifu.scala 117:17] - assign io_iccm_dma_sb_error = mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 119:24] + assign io_iccm_dma_sb_error = mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 118:24] assign mem_ctl_clock = clock; assign mem_ctl_reset = reset; assign mem_ctl_io_free_clk = io_free_clk; // @[ifu.scala 91:23] @@ -83138,9 +83138,9 @@ module quasar( assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 146:15] assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 146:15] assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 146:15] - assign io_dma_hrdata = ahb_to_axi4_io_ahb_hrdata; // @[quasar.scala 479:19 quasar.scala 514:23] - assign io_dma_hreadyout = ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 480:22 quasar.scala 515:26] - assign io_dma_hresp = ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 481:18 quasar.scala 516:22] + assign io_dma_hrdata = ahb_to_axi4_io_ahb_hrdata; // @[quasar.scala 479:19 quasar.scala 512:23] + assign io_dma_hreadyout = ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 480:22 quasar.scala 513:26] + assign io_dma_hresp = ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 481:18 quasar.scala 514:22] assign ifu_clock = clock; assign ifu_reset = io_core_rst_l; // @[quasar.scala 135:13] assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 140:26] @@ -83872,152 +83872,152 @@ module quasar_wrapper( wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:27] wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 79:27] wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 79:27] - wire swerv_clock; // @[quasar_wrapper.scala 80:21] - wire swerv_reset; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] - wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_ifu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_ifu_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] - wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] - wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 80:21] - wire swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 80:21] - wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 80:21] - wire swerv_io_nmi_int; // @[quasar_wrapper.scala 80:21] - wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 80:21] - wire swerv_io_core_rst_l; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 80:21] - wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 80:21] - wire swerv_io_icm_clk_override; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 80:21] - wire swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 80:21] - wire swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 80:21] - wire swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 80:21] - wire swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 80:21] - wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 80:21] - wire swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 80:21] - wire swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 80:21] - wire swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dccm_wren; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dccm_rden; // @[quasar_wrapper.scala 80:21] - wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 80:21] - wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 80:21] - wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 80:21] - wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 80:21] - wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 80:21] - wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 80:21] - wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 80:21] - wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 80:21] - wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_rd_en; // @[quasar_wrapper.scala 80:21] - wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 80:21] - wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 80:21] - wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 80:21] - wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 80:21] - wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 80:21] - wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 80:21] - wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 80:21] - wire swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 80:21] - wire swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 80:21] - wire swerv_io_iccm_wren; // @[quasar_wrapper.scala 80:21] - wire swerv_io_iccm_rden; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 80:21] - wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 80:21] - wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_hsel; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_dma_haddr; // @[quasar_wrapper.scala 80:21] - wire [2:0] swerv_io_dma_hsize; // @[quasar_wrapper.scala 80:21] - wire [1:0] swerv_io_dma_htrans; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_hwrite; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_dma_hwdata; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 80:21] - wire [63:0] swerv_io_dma_hrdata; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_hreadyout; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_hresp; // @[quasar_wrapper.scala 80:21] - wire swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 80:21] - wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 80:21] - wire swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 80:21] - wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 80:21] - wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 80:21] - wire swerv_io_timer_int; // @[quasar_wrapper.scala 80:21] - wire swerv_io_soft_int; // @[quasar_wrapper.scala 80:21] - wire swerv_io_scan_mode; // @[quasar_wrapper.scala 80:21] + wire core_clock; // @[quasar_wrapper.scala 80:20] + wire core_reset; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] + wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_ifu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_ifu_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_aw_bits_id; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 80:20] + wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_b_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_ar_bits_id; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:20] + wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 80:20] + wire core_io_sb_axi_r_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 80:20] + wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 80:20] + wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 80:20] + wire core_io_nmi_int; // @[quasar_wrapper.scala 80:20] + wire [30:0] core_io_nmi_vec; // @[quasar_wrapper.scala 80:20] + wire core_io_core_rst_l; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 80:20] + wire [4:0] core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 80:20] + wire core_io_dccm_clk_override; // @[quasar_wrapper.scala 80:20] + wire core_io_icm_clk_override; // @[quasar_wrapper.scala 80:20] + wire core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 80:20] + wire core_io_i_cpu_halt_req; // @[quasar_wrapper.scala 80:20] + wire core_io_i_cpu_run_req; // @[quasar_wrapper.scala 80:20] + wire core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 80:20] + wire core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 80:20] + wire core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 80:20] + wire core_io_o_debug_mode_status; // @[quasar_wrapper.scala 80:20] + wire [27:0] core_io_core_id; // @[quasar_wrapper.scala 80:20] + wire core_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 80:20] + wire core_io_mpc_debug_run_req; // @[quasar_wrapper.scala 80:20] + wire core_io_mpc_reset_run_req; // @[quasar_wrapper.scala 80:20] + wire core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 80:20] + wire core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 80:20] + wire core_io_debug_brkpt_status; // @[quasar_wrapper.scala 80:20] + wire core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 80:20] + wire core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 80:20] + wire core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 80:20] + wire core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 80:20] + wire core_io_dccm_wren; // @[quasar_wrapper.scala 80:20] + wire core_io_dccm_rden; // @[quasar_wrapper.scala 80:20] + wire [15:0] core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 80:20] + wire [15:0] core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 80:20] + wire [15:0] core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 80:20] + wire [15:0] core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 80:20] + wire [38:0] core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 80:20] + wire [38:0] core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 80:20] + wire [38:0] core_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 80:20] + wire [38:0] core_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 80:20] + wire [30:0] core_io_ic_rw_addr; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_ic_tag_valid; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_ic_wr_en; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_rd_en; // @[quasar_wrapper.scala 80:20] + wire [70:0] core_io_ic_wr_data_0; // @[quasar_wrapper.scala 80:20] + wire [70:0] core_io_ic_wr_data_1; // @[quasar_wrapper.scala 80:20] + wire [70:0] core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 80:20] + wire [9:0] core_io_ic_debug_addr; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_ic_rd_data; // @[quasar_wrapper.scala 80:20] + wire [70:0] core_io_ic_debug_rd_data; // @[quasar_wrapper.scala 80:20] + wire [25:0] core_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_ic_eccerr; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_ic_rd_hit; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_tag_perr; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_ic_debug_way; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_ic_premux_data; // @[quasar_wrapper.scala 80:20] + wire core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 80:20] + wire [14:0] core_io_iccm_rw_addr; // @[quasar_wrapper.scala 80:20] + wire core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 80:20] + wire core_io_iccm_correction_state; // @[quasar_wrapper.scala 80:20] + wire core_io_iccm_wren; // @[quasar_wrapper.scala 80:20] + wire core_io_iccm_rden; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_iccm_wr_size; // @[quasar_wrapper.scala 80:20] + wire [77:0] core_io_iccm_wr_data; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_iccm_rd_data; // @[quasar_wrapper.scala 80:20] + wire [77:0] core_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_hsel; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_dma_haddr; // @[quasar_wrapper.scala 80:20] + wire [2:0] core_io_dma_hsize; // @[quasar_wrapper.scala 80:20] + wire [1:0] core_io_dma_htrans; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_hwrite; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_dma_hwdata; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_hreadyin; // @[quasar_wrapper.scala 80:20] + wire [63:0] core_io_dma_hrdata; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_hreadyout; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_hresp; // @[quasar_wrapper.scala 80:20] + wire core_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 80:20] + wire core_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 80:20] + wire core_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 80:20] + wire core_io_dma_bus_clk_en; // @[quasar_wrapper.scala 80:20] + wire core_io_dmi_reg_en; // @[quasar_wrapper.scala 80:20] + wire [6:0] core_io_dmi_reg_addr; // @[quasar_wrapper.scala 80:20] + wire core_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 80:20] + wire [31:0] core_io_dmi_reg_wdata; // @[quasar_wrapper.scala 80:20] + wire [30:0] core_io_extintsrc_req; // @[quasar_wrapper.scala 80:20] + wire core_io_timer_int; // @[quasar_wrapper.scala 80:20] + wire core_io_soft_int; // @[quasar_wrapper.scala 80:20] + wire core_io_scan_mode; // @[quasar_wrapper.scala 80:20] mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 78:19] .clk(mem_clk), .rst_l(mem_rst_l), @@ -84083,305 +84083,305 @@ module quasar_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - quasar swerv ( // @[quasar_wrapper.scala 80:21] - .clock(swerv_clock), - .reset(swerv_reset), - .io_lsu_axi_aw_valid(swerv_io_lsu_axi_aw_valid), - .io_lsu_axi_aw_bits_id(swerv_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(swerv_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(swerv_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(swerv_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(swerv_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_valid(swerv_io_lsu_axi_w_valid), - .io_lsu_axi_w_bits_data(swerv_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(swerv_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_ready(swerv_io_lsu_axi_b_ready), - .io_lsu_axi_ar_valid(swerv_io_lsu_axi_ar_valid), - .io_lsu_axi_ar_bits_id(swerv_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(swerv_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(swerv_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(swerv_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(swerv_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_ready(swerv_io_lsu_axi_r_ready), - .io_ifu_axi_aw_valid(swerv_io_ifu_axi_aw_valid), - .io_ifu_axi_aw_bits_id(swerv_io_ifu_axi_aw_bits_id), - .io_ifu_axi_w_valid(swerv_io_ifu_axi_w_valid), - .io_ifu_axi_w_bits_data(swerv_io_ifu_axi_w_bits_data), - .io_ifu_axi_b_ready(swerv_io_ifu_axi_b_ready), - .io_ifu_axi_ar_valid(swerv_io_ifu_axi_ar_valid), - .io_ifu_axi_ar_bits_id(swerv_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(swerv_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(swerv_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_ready(swerv_io_ifu_axi_r_ready), - .io_sb_axi_aw_valid(swerv_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_id(swerv_io_sb_axi_aw_bits_id), - .io_sb_axi_aw_bits_addr(swerv_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(swerv_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(swerv_io_sb_axi_aw_bits_size), - .io_sb_axi_w_valid(swerv_io_sb_axi_w_valid), - .io_sb_axi_w_bits_data(swerv_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(swerv_io_sb_axi_w_bits_strb), - .io_sb_axi_b_ready(swerv_io_sb_axi_b_ready), - .io_sb_axi_ar_valid(swerv_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_id(swerv_io_sb_axi_ar_bits_id), - .io_sb_axi_ar_bits_addr(swerv_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(swerv_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(swerv_io_sb_axi_ar_bits_size), - .io_sb_axi_r_ready(swerv_io_sb_axi_r_ready), - .io_dma_axi_aw_ready(swerv_io_dma_axi_aw_ready), - .io_dma_axi_w_ready(swerv_io_dma_axi_w_ready), - .io_dma_axi_b_valid(swerv_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(swerv_io_dma_axi_b_bits_resp), - .io_dma_axi_ar_ready(swerv_io_dma_axi_ar_ready), - .io_dma_axi_ar_valid(swerv_io_dma_axi_ar_valid), - .io_dma_axi_r_valid(swerv_io_dma_axi_r_valid), - .io_dma_axi_r_bits_data(swerv_io_dma_axi_r_bits_data), - .io_dma_axi_r_bits_resp(swerv_io_dma_axi_r_bits_resp), - .io_dbg_rst_l(swerv_io_dbg_rst_l), - .io_rst_vec(swerv_io_rst_vec), - .io_nmi_int(swerv_io_nmi_int), - .io_nmi_vec(swerv_io_nmi_vec), - .io_core_rst_l(swerv_io_core_rst_l), - .io_rv_trace_pkt_rv_i_valid_ip(swerv_io_rv_trace_pkt_rv_i_valid_ip), - .io_rv_trace_pkt_rv_i_insn_ip(swerv_io_rv_trace_pkt_rv_i_insn_ip), - .io_rv_trace_pkt_rv_i_address_ip(swerv_io_rv_trace_pkt_rv_i_address_ip), - .io_rv_trace_pkt_rv_i_exception_ip(swerv_io_rv_trace_pkt_rv_i_exception_ip), - .io_rv_trace_pkt_rv_i_ecause_ip(swerv_io_rv_trace_pkt_rv_i_ecause_ip), - .io_rv_trace_pkt_rv_i_interrupt_ip(swerv_io_rv_trace_pkt_rv_i_interrupt_ip), - .io_rv_trace_pkt_rv_i_tval_ip(swerv_io_rv_trace_pkt_rv_i_tval_ip), - .io_dccm_clk_override(swerv_io_dccm_clk_override), - .io_icm_clk_override(swerv_io_icm_clk_override), - .io_dec_tlu_core_ecc_disable(swerv_io_dec_tlu_core_ecc_disable), - .io_i_cpu_halt_req(swerv_io_i_cpu_halt_req), - .io_i_cpu_run_req(swerv_io_i_cpu_run_req), - .io_o_cpu_halt_ack(swerv_io_o_cpu_halt_ack), - .io_o_cpu_halt_status(swerv_io_o_cpu_halt_status), - .io_o_cpu_run_ack(swerv_io_o_cpu_run_ack), - .io_o_debug_mode_status(swerv_io_o_debug_mode_status), - .io_core_id(swerv_io_core_id), - .io_mpc_debug_halt_req(swerv_io_mpc_debug_halt_req), - .io_mpc_debug_run_req(swerv_io_mpc_debug_run_req), - .io_mpc_reset_run_req(swerv_io_mpc_reset_run_req), - .io_mpc_debug_halt_ack(swerv_io_mpc_debug_halt_ack), - .io_mpc_debug_run_ack(swerv_io_mpc_debug_run_ack), - .io_debug_brkpt_status(swerv_io_debug_brkpt_status), - .io_dec_tlu_perfcnt0(swerv_io_dec_tlu_perfcnt0), - .io_dec_tlu_perfcnt1(swerv_io_dec_tlu_perfcnt1), - .io_dec_tlu_perfcnt2(swerv_io_dec_tlu_perfcnt2), - .io_dec_tlu_perfcnt3(swerv_io_dec_tlu_perfcnt3), - .io_dccm_wren(swerv_io_dccm_wren), - .io_dccm_rden(swerv_io_dccm_rden), - .io_dccm_wr_addr_lo(swerv_io_dccm_wr_addr_lo), - .io_dccm_wr_addr_hi(swerv_io_dccm_wr_addr_hi), - .io_dccm_rd_addr_lo(swerv_io_dccm_rd_addr_lo), - .io_dccm_rd_addr_hi(swerv_io_dccm_rd_addr_hi), - .io_dccm_wr_data_lo(swerv_io_dccm_wr_data_lo), - .io_dccm_wr_data_hi(swerv_io_dccm_wr_data_hi), - .io_dccm_rd_data_lo(swerv_io_dccm_rd_data_lo), - .io_dccm_rd_data_hi(swerv_io_dccm_rd_data_hi), - .io_ic_rw_addr(swerv_io_ic_rw_addr), - .io_ic_tag_valid(swerv_io_ic_tag_valid), - .io_ic_wr_en(swerv_io_ic_wr_en), - .io_ic_rd_en(swerv_io_ic_rd_en), - .io_ic_wr_data_0(swerv_io_ic_wr_data_0), - .io_ic_wr_data_1(swerv_io_ic_wr_data_1), - .io_ic_debug_wr_data(swerv_io_ic_debug_wr_data), - .io_ic_debug_addr(swerv_io_ic_debug_addr), - .io_ic_rd_data(swerv_io_ic_rd_data), - .io_ic_debug_rd_data(swerv_io_ic_debug_rd_data), - .io_ic_tag_debug_rd_data(swerv_io_ic_tag_debug_rd_data), - .io_ic_eccerr(swerv_io_ic_eccerr), - .io_ic_rd_hit(swerv_io_ic_rd_hit), - .io_ic_tag_perr(swerv_io_ic_tag_perr), - .io_ic_debug_rd_en(swerv_io_ic_debug_rd_en), - .io_ic_debug_wr_en(swerv_io_ic_debug_wr_en), - .io_ic_debug_tag_array(swerv_io_ic_debug_tag_array), - .io_ic_debug_way(swerv_io_ic_debug_way), - .io_ic_premux_data(swerv_io_ic_premux_data), - .io_ic_sel_premux_data(swerv_io_ic_sel_premux_data), - .io_iccm_rw_addr(swerv_io_iccm_rw_addr), - .io_iccm_buf_correct_ecc(swerv_io_iccm_buf_correct_ecc), - .io_iccm_correction_state(swerv_io_iccm_correction_state), - .io_iccm_wren(swerv_io_iccm_wren), - .io_iccm_rden(swerv_io_iccm_rden), - .io_iccm_wr_size(swerv_io_iccm_wr_size), - .io_iccm_wr_data(swerv_io_iccm_wr_data), - .io_iccm_rd_data(swerv_io_iccm_rd_data), - .io_iccm_rd_data_ecc(swerv_io_iccm_rd_data_ecc), - .io_dma_hsel(swerv_io_dma_hsel), - .io_dma_haddr(swerv_io_dma_haddr), - .io_dma_hsize(swerv_io_dma_hsize), - .io_dma_htrans(swerv_io_dma_htrans), - .io_dma_hwrite(swerv_io_dma_hwrite), - .io_dma_hwdata(swerv_io_dma_hwdata), - .io_dma_hreadyin(swerv_io_dma_hreadyin), - .io_dma_hrdata(swerv_io_dma_hrdata), - .io_dma_hreadyout(swerv_io_dma_hreadyout), - .io_dma_hresp(swerv_io_dma_hresp), - .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en), - .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en), - .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en), - .io_dma_bus_clk_en(swerv_io_dma_bus_clk_en), - .io_dmi_reg_en(swerv_io_dmi_reg_en), - .io_dmi_reg_addr(swerv_io_dmi_reg_addr), - .io_dmi_reg_wr_en(swerv_io_dmi_reg_wr_en), - .io_dmi_reg_wdata(swerv_io_dmi_reg_wdata), - .io_extintsrc_req(swerv_io_extintsrc_req), - .io_timer_int(swerv_io_timer_int), - .io_soft_int(swerv_io_soft_int), - .io_scan_mode(swerv_io_scan_mode) + quasar core ( // @[quasar_wrapper.scala 80:20] + .clock(core_clock), + .reset(core_reset), + .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), + .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), + .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), + .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), + .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), + .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), + .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), + .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), + .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), + .io_lsu_axi_b_ready(core_io_lsu_axi_b_ready), + .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), + .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), + .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), + .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), + .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), + .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), + .io_lsu_axi_r_ready(core_io_lsu_axi_r_ready), + .io_ifu_axi_aw_valid(core_io_ifu_axi_aw_valid), + .io_ifu_axi_aw_bits_id(core_io_ifu_axi_aw_bits_id), + .io_ifu_axi_w_valid(core_io_ifu_axi_w_valid), + .io_ifu_axi_w_bits_data(core_io_ifu_axi_w_bits_data), + .io_ifu_axi_b_ready(core_io_ifu_axi_b_ready), + .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), + .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), + .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), + .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), + .io_ifu_axi_r_ready(core_io_ifu_axi_r_ready), + .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_id(core_io_sb_axi_aw_bits_id), + .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), + .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), + .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), + .io_sb_axi_w_valid(core_io_sb_axi_w_valid), + .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), + .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), + .io_sb_axi_b_ready(core_io_sb_axi_b_ready), + .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_id(core_io_sb_axi_ar_bits_id), + .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), + .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), + .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), + .io_sb_axi_r_ready(core_io_sb_axi_r_ready), + .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), + .io_dma_axi_w_ready(core_io_dma_axi_w_ready), + .io_dma_axi_b_valid(core_io_dma_axi_b_valid), + .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), + .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), + .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), + .io_dma_axi_r_valid(core_io_dma_axi_r_valid), + .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), + .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), + .io_dbg_rst_l(core_io_dbg_rst_l), + .io_rst_vec(core_io_rst_vec), + .io_nmi_int(core_io_nmi_int), + .io_nmi_vec(core_io_nmi_vec), + .io_core_rst_l(core_io_core_rst_l), + .io_rv_trace_pkt_rv_i_valid_ip(core_io_rv_trace_pkt_rv_i_valid_ip), + .io_rv_trace_pkt_rv_i_insn_ip(core_io_rv_trace_pkt_rv_i_insn_ip), + .io_rv_trace_pkt_rv_i_address_ip(core_io_rv_trace_pkt_rv_i_address_ip), + .io_rv_trace_pkt_rv_i_exception_ip(core_io_rv_trace_pkt_rv_i_exception_ip), + .io_rv_trace_pkt_rv_i_ecause_ip(core_io_rv_trace_pkt_rv_i_ecause_ip), + .io_rv_trace_pkt_rv_i_interrupt_ip(core_io_rv_trace_pkt_rv_i_interrupt_ip), + .io_rv_trace_pkt_rv_i_tval_ip(core_io_rv_trace_pkt_rv_i_tval_ip), + .io_dccm_clk_override(core_io_dccm_clk_override), + .io_icm_clk_override(core_io_icm_clk_override), + .io_dec_tlu_core_ecc_disable(core_io_dec_tlu_core_ecc_disable), + .io_i_cpu_halt_req(core_io_i_cpu_halt_req), + .io_i_cpu_run_req(core_io_i_cpu_run_req), + .io_o_cpu_halt_ack(core_io_o_cpu_halt_ack), + .io_o_cpu_halt_status(core_io_o_cpu_halt_status), + .io_o_cpu_run_ack(core_io_o_cpu_run_ack), + .io_o_debug_mode_status(core_io_o_debug_mode_status), + .io_core_id(core_io_core_id), + .io_mpc_debug_halt_req(core_io_mpc_debug_halt_req), + .io_mpc_debug_run_req(core_io_mpc_debug_run_req), + .io_mpc_reset_run_req(core_io_mpc_reset_run_req), + .io_mpc_debug_halt_ack(core_io_mpc_debug_halt_ack), + .io_mpc_debug_run_ack(core_io_mpc_debug_run_ack), + .io_debug_brkpt_status(core_io_debug_brkpt_status), + .io_dec_tlu_perfcnt0(core_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(core_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(core_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(core_io_dec_tlu_perfcnt3), + .io_dccm_wren(core_io_dccm_wren), + .io_dccm_rden(core_io_dccm_rden), + .io_dccm_wr_addr_lo(core_io_dccm_wr_addr_lo), + .io_dccm_wr_addr_hi(core_io_dccm_wr_addr_hi), + .io_dccm_rd_addr_lo(core_io_dccm_rd_addr_lo), + .io_dccm_rd_addr_hi(core_io_dccm_rd_addr_hi), + .io_dccm_wr_data_lo(core_io_dccm_wr_data_lo), + .io_dccm_wr_data_hi(core_io_dccm_wr_data_hi), + .io_dccm_rd_data_lo(core_io_dccm_rd_data_lo), + .io_dccm_rd_data_hi(core_io_dccm_rd_data_hi), + .io_ic_rw_addr(core_io_ic_rw_addr), + .io_ic_tag_valid(core_io_ic_tag_valid), + .io_ic_wr_en(core_io_ic_wr_en), + .io_ic_rd_en(core_io_ic_rd_en), + .io_ic_wr_data_0(core_io_ic_wr_data_0), + .io_ic_wr_data_1(core_io_ic_wr_data_1), + .io_ic_debug_wr_data(core_io_ic_debug_wr_data), + .io_ic_debug_addr(core_io_ic_debug_addr), + .io_ic_rd_data(core_io_ic_rd_data), + .io_ic_debug_rd_data(core_io_ic_debug_rd_data), + .io_ic_tag_debug_rd_data(core_io_ic_tag_debug_rd_data), + .io_ic_eccerr(core_io_ic_eccerr), + .io_ic_rd_hit(core_io_ic_rd_hit), + .io_ic_tag_perr(core_io_ic_tag_perr), + .io_ic_debug_rd_en(core_io_ic_debug_rd_en), + .io_ic_debug_wr_en(core_io_ic_debug_wr_en), + .io_ic_debug_tag_array(core_io_ic_debug_tag_array), + .io_ic_debug_way(core_io_ic_debug_way), + .io_ic_premux_data(core_io_ic_premux_data), + .io_ic_sel_premux_data(core_io_ic_sel_premux_data), + .io_iccm_rw_addr(core_io_iccm_rw_addr), + .io_iccm_buf_correct_ecc(core_io_iccm_buf_correct_ecc), + .io_iccm_correction_state(core_io_iccm_correction_state), + .io_iccm_wren(core_io_iccm_wren), + .io_iccm_rden(core_io_iccm_rden), + .io_iccm_wr_size(core_io_iccm_wr_size), + .io_iccm_wr_data(core_io_iccm_wr_data), + .io_iccm_rd_data(core_io_iccm_rd_data), + .io_iccm_rd_data_ecc(core_io_iccm_rd_data_ecc), + .io_dma_hsel(core_io_dma_hsel), + .io_dma_haddr(core_io_dma_haddr), + .io_dma_hsize(core_io_dma_hsize), + .io_dma_htrans(core_io_dma_htrans), + .io_dma_hwrite(core_io_dma_hwrite), + .io_dma_hwdata(core_io_dma_hwdata), + .io_dma_hreadyin(core_io_dma_hreadyin), + .io_dma_hrdata(core_io_dma_hrdata), + .io_dma_hreadyout(core_io_dma_hreadyout), + .io_dma_hresp(core_io_dma_hresp), + .io_lsu_bus_clk_en(core_io_lsu_bus_clk_en), + .io_ifu_bus_clk_en(core_io_ifu_bus_clk_en), + .io_dbg_bus_clk_en(core_io_dbg_bus_clk_en), + .io_dma_bus_clk_en(core_io_dma_bus_clk_en), + .io_dmi_reg_en(core_io_dmi_reg_en), + .io_dmi_reg_addr(core_io_dmi_reg_addr), + .io_dmi_reg_wr_en(core_io_dmi_reg_wr_en), + .io_dmi_reg_wdata(core_io_dmi_reg_wdata), + .io_extintsrc_req(core_io_extintsrc_req), + .io_timer_int(core_io_timer_int), + .io_soft_int(core_io_soft_int), + .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:20] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 138:20] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:20] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 141:20] - assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:19] - assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:19] - assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_b_bits_id = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_r_bits_id = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 148:20] - assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 148:20] - assign io_dma_hrdata = swerv_io_dma_hrdata; // @[quasar_wrapper.scala 211:17] - assign io_dma_hreadyout = swerv_io_dma_hreadyout; // @[quasar_wrapper.scala 212:20] - assign io_dma_hresp = swerv_io_dma_hresp; // @[quasar_wrapper.scala 213:16] - assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 201:23] - assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 202:23] - assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 203:23] - assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 204:23] + assign io_lsu_axi_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:19] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 138:19] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:19] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 141:19] + assign io_sb_axi_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:18] + assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:18] + assign io_dma_axi_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_b_bits_id = 1'h0; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_r_bits_id = 1'h0; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 148:19] + assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 148:19] + assign io_dma_hrdata = core_io_dma_hrdata; // @[quasar_wrapper.scala 195:17] + assign io_dma_hreadyout = core_io_dma_hreadyout; // @[quasar_wrapper.scala 196:20] + assign io_dma_hresp = core_io_dma_hresp; // @[quasar_wrapper.scala 197:16] + assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 185:23] + assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 186:23] + assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 187:23] + assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 188:23] assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 96:15] - assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 197:25] - assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 198:24] - assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 199:25] - assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 192:21] - assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 193:24] - assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 195:26] - assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 194:20] - assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 189:19] - assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 189:19] + assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 181:25] + assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 182:24] + assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 183:25] + assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 176:21] + assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 177:24] + assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 179:26] + assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 178:20] + assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 173:19] + assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 173:19] assign mem_clk = clock; // @[quasar_wrapper.scala 104:14] assign mem_rst_l = reset; // @[quasar_wrapper.scala 103:16] - assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 99:28] - assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 100:27] - assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 101:35] - assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 102:15] - assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 102:15] - assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 109:17] - assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 109:17] - assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 108:15] - assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 108:15] - assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 108:15] - assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 108:15] - assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 108:15] - assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 108:15] - assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 108:15] - assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 108:15] - assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 108:15] + assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 99:28] + assign mem_icm_clk_override = core_io_icm_clk_override; // @[quasar_wrapper.scala 100:27] + assign mem_dec_tlu_core_ecc_disable = core_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 101:35] + assign mem_dccm_wren = core_io_dccm_wren; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rden = core_io_dccm_rden; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_addr_lo = core_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_addr_hi = core_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rd_addr_lo = core_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rd_addr_hi = core_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_data_lo = core_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_data_hi = core_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 102:15] + assign mem_iccm_rw_addr = core_io_iccm_rw_addr; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_buf_correct_ecc = core_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_correction_state = core_io_iccm_correction_state; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_wren = core_io_iccm_wren; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_rden = core_io_iccm_rden; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_wr_size = core_io_iccm_wr_size; // @[quasar_wrapper.scala 109:16] + assign mem_iccm_wr_data = core_io_iccm_wr_data; // @[quasar_wrapper.scala 109:16] + assign mem_ic_rw_addr = core_io_ic_rw_addr; // @[quasar_wrapper.scala 108:14] + assign mem_ic_tag_valid = core_io_ic_tag_valid; // @[quasar_wrapper.scala 108:14] + assign mem_ic_wr_en = core_io_ic_wr_en; // @[quasar_wrapper.scala 108:14] + assign mem_ic_rd_en = core_io_ic_rd_en; // @[quasar_wrapper.scala 108:14] + assign mem_ic_wr_data_0 = core_io_ic_wr_data_0; // @[quasar_wrapper.scala 108:14] + assign mem_ic_wr_data_1 = core_io_ic_wr_data_1; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_wr_data = core_io_ic_debug_wr_data; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_addr = core_io_ic_debug_addr; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_rd_en = core_io_ic_debug_rd_en; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_wr_en = core_io_ic_debug_wr_en; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_tag_array = core_io_ic_debug_tag_array; // @[quasar_wrapper.scala 108:14] + assign mem_ic_debug_way = core_io_ic_debug_way; // @[quasar_wrapper.scala 108:14] + assign mem_ic_premux_data = core_io_ic_premux_data; // @[quasar_wrapper.scala 108:14] + assign mem_ic_sel_premux_data = core_io_ic_sel_premux_data; // @[quasar_wrapper.scala 108:14] assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 105:20] assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 81:25] assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 82:22] @@ -84391,46 +84391,46 @@ module quasar_wrapper( assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 85:27] assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 86:26] assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 87:26] - assign swerv_clock = clock; - assign swerv_reset = reset; - assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 148:20] - assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 107:22 quasar_wrapper.scala 121:22] - assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:20] - assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:20] - assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:20] - assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:27] - assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:26] - assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:20] - assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:31] - assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:30] - assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:30] - assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 102:15] - assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 102:15] - assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 108:15] - assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 108:15] - assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 108:15] - assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 108:15] - assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 108:15] - assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 108:15] - assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 109:17] - assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 109:17] - assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 151:21] - assign swerv_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 152:22] - assign swerv_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 156:22] - assign swerv_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 157:23] - assign swerv_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 158:23] - assign swerv_io_dma_hwdata = io_dma_hwdata; // @[quasar_wrapper.scala 159:23] - assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 160:25] - assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 178:27] - assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 179:27] - assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 180:27] - assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 181:27] - assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 93:23] - assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 92:25] - assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 94:26] - assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 91:26] - assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 185:26] - assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 183:22] - assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 184:21] - assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 119:22] + assign core_clock = clock; + assign core_reset = reset; + assign core_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 148:19] + assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 107:21 quasar_wrapper.scala 121:21] + assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] + assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] + assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:19] + assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:26] + assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:25] + assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:19] + assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:30] + assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:29] + assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:29] + assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 102:15] + assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 102:15] + assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 108:14] + assign core_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 108:14] + assign core_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 108:14] + assign core_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 108:14] + assign core_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 108:14] + assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 108:14] + assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 109:16] + assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 109:16] + assign core_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 151:20] + assign core_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 152:21] + assign core_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 156:21] + assign core_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 157:22] + assign core_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 158:22] + assign core_io_dma_hwdata = io_dma_hwdata; // @[quasar_wrapper.scala 159:22] + assign core_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 160:24] + assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 162:26] + assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 163:26] + assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 164:26] + assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 165:26] + assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 93:22] + assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 92:24] + assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 94:25] + assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 91:25] + assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 169:25] + assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 167:21] + assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 168:20] + assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 119:21] endmodule diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index 211d38bc..2856bb52 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -302,8 +302,4 @@ class dec extends Module with param with RequireAsyncReset{ // debug command read data io.dec_dbg_rddata := decode.io.dec_i0_wdata_r -} - -object dec_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new dec())) } \ No newline at end of file diff --git a/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala index cfb1895c..87944d78 100644 --- a/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -115,10 +115,5 @@ class ifu extends Module with lib with RequireAsyncReset { io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag io.iccm_ready := mem_ctl.io.iccm_ready - io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error - -} -object ifu extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new ifu())) } diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 7d106d36..2b75019d 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -222,7 +222,4 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) -} -object AHB_main extends App { - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))} +} \ No newline at end of file diff --git a/src/main/scala/mem.scala b/src/main/scala/mem.scala index a9e5702f..435f3871 100644 --- a/src/main/scala/mem.scala +++ b/src/main/scala/mem.scala @@ -68,8 +68,4 @@ class blackbox_mem extends Module with lib { val io = IO(new Mem_bundle) val it = Module(new quasar.mem) io <> it.io -} - -object mem extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new blackbox_mem)) -} +} \ No newline at end of file diff --git a/src/main/scala/pic_ctrl.scala b/src/main/scala/pic_ctrl.scala index 195085d7..416d5e2f 100644 --- a/src/main/scala/pic_ctrl.scala +++ b/src/main/scala/pic_ctrl.scala @@ -404,9 +404,4 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { } -} - -object pic_main extends App{ - println("Generating Verilog...") - println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl())) } \ No newline at end of file diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 38816098..b8f0a22f 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -479,8 +479,6 @@ class quasar extends Module with RequireAsyncReset with lib { io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp -// io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata -// io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata } .otherwise{ // AHB Signals diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala index 0849f34c..a694850d 100644 --- a/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -77,140 +77,124 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { }) val mem = Module(new quasar.mem()) val dmi_wrapper = Module(new dmi_wrapper()) - val swerv = Module(new quasar()) + val core = Module(new quasar()) dmi_wrapper.io.trst_n := io.jtag_trst_n dmi_wrapper.io.tck := io.jtag_tck dmi_wrapper.io.tms := io.jtag_tms dmi_wrapper.io.tdi := io.jtag_tdi dmi_wrapper.io.core_clk := clock dmi_wrapper.io.jtag_id := io.jtag_id - dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata + dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata dmi_wrapper.io.core_rst_n := io.dbg_rst_l - swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data - swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr - swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en - swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en - swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset + core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data + core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr + core.io.dmi_reg_en := dmi_wrapper.io.reg_en + core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en + core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset io.jtag_tdo := dmi_wrapper.io.tdo // Memory signals - mem.io.dccm_clk_override := swerv.io.dccm_clk_override - mem.io.icm_clk_override := swerv.io.icm_clk_override - mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable - mem.io.dccm <> swerv.io.dccm + mem.io.dccm_clk_override := core.io.dccm_clk_override + mem.io.icm_clk_override := core.io.icm_clk_override + mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable + mem.io.dccm <> core.io.dccm mem.io.rst_l := reset mem.io.clk := clock mem.io.scan_mode := io.scan_mode // Memory outputs - swerv.io.dbg_rst_l := io.dbg_rst_l - swerv.io.ic <> mem.io.ic - swerv.io.iccm <> mem.io.iccm - swerv.io.sb_hready := 0.U - swerv.io.hrdata := 0.U - swerv.io.sb_hresp := 0.U - swerv.io.lsu_hrdata := 0.U - swerv.io.lsu_hresp := 0.U - swerv.io.lsu_hready := 0.U - swerv.io.hready := 0.U - swerv.io.hresp := 0.U - swerv.io.sb_hrdata := 0.U - swerv.io.scan_mode := io.scan_mode + core.io.dbg_rst_l := io.dbg_rst_l + core.io.ic <> mem.io.ic + core.io.iccm <> mem.io.iccm + core.io.sb_hready := 0.U + core.io.hrdata := 0.U + core.io.sb_hresp := 0.U + core.io.lsu_hrdata := 0.U + core.io.lsu_hresp := 0.U + core.io.lsu_hready := 0.U + core.io.hready := 0.U + core.io.hresp := 0.U + core.io.sb_hrdata := 0.U + core.io.scan_mode := io.scan_mode // SweRV Inputs - swerv.io.dbg_rst_l := io.dbg_rst_l - swerv.io.rst_vec := io.rst_vec - swerv.io.nmi_int := io.nmi_int - swerv.io.nmi_vec := io.nmi_vec + core.io.dbg_rst_l := io.dbg_rst_l + core.io.rst_vec := io.rst_vec + core.io.nmi_int := io.nmi_int + core.io.nmi_vec := io.nmi_vec // external halt/run interface - swerv.io.i_cpu_halt_req := io.i_cpu_halt_req - swerv.io.i_cpu_run_req := io.i_cpu_run_req - swerv.io.core_id := io.core_id + core.io.i_cpu_halt_req := io.i_cpu_halt_req + core.io.i_cpu_run_req := io.i_cpu_run_req + core.io.core_id := io.core_id // external MPC halt/run interface - swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req - swerv.io.mpc_debug_run_req := io.mpc_debug_run_req - swerv.io.mpc_reset_run_req := io.mpc_reset_run_req + core.io.mpc_debug_halt_req := io.mpc_debug_halt_req + core.io.mpc_debug_run_req := io.mpc_debug_run_req + core.io.mpc_reset_run_req := io.mpc_reset_run_req //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels - swerv.io.lsu_axi <> io.lsu_axi + core.io.lsu_axi <> io.lsu_axi //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels - swerv.io.ifu_axi <> io.ifu_axi + core.io.ifu_axi <> io.ifu_axi //-------------------------- SB AXI signals-------------------------- // AXI Write Channels - swerv.io.sb_axi <> io.sb_axi + core.io.sb_axi <> io.sb_axi //-------------------------- DMA AXI signals-------------------------- // AXI Write Channels - swerv.io.dma_axi <> io.dma_axi + core.io.dma_axi <> io.dma_axi // DMA Slave - swerv.io.dma_hsel := io.dma_hsel - swerv.io.dma_haddr := io.dma_haddr - swerv.io.dma_hburst := io.dma_hburst - swerv.io.dma_hmastlock := io.dma_hmastlock - swerv.io.dma_hprot := io.dma_hprot - swerv.io.dma_hsize := io.dma_hsize - swerv.io.dma_htrans := io.dma_htrans - swerv.io.dma_hwrite := io.dma_hwrite - swerv.io.dma_hwdata := io.dma_hwdata - swerv.io.dma_hreadyin := io.dma_hreadyin + core.io.dma_hsel := io.dma_hsel + core.io.dma_haddr := io.dma_haddr + core.io.dma_hburst := io.dma_hburst + core.io.dma_hmastlock := io.dma_hmastlock + core.io.dma_hprot := io.dma_hprot + core.io.dma_hsize := io.dma_hsize + core.io.dma_htrans := io.dma_htrans + core.io.dma_hwrite := io.dma_hwrite + core.io.dma_hwdata := io.dma_hwdata + core.io.dma_hreadyin := io.dma_hreadyin - swerv.io.lsu_bus_clk_en - swerv.io.ifu_bus_clk_en - swerv.io.dbg_bus_clk_en - swerv.io.dma_bus_clk_en + core.io.lsu_bus_clk_en := io.lsu_bus_clk_en + core.io.ifu_bus_clk_en := io.ifu_bus_clk_en + core.io.dbg_bus_clk_en := io.dbg_bus_clk_en + core.io.dma_bus_clk_en := io.dma_bus_clk_en - swerv.io.dmi_reg_en - swerv.io.dmi_reg_addr - swerv.io.dmi_reg_wr_en - swerv.io.dmi_reg_wdata - swerv.io.dmi_hard_reset - - swerv.io.extintsrc_req - swerv.io.timer_int - swerv.io.soft_int - swerv.io.scan_mode - - swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en - swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en - swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en - swerv.io.dma_bus_clk_en := io.dma_bus_clk_en - - swerv.io.timer_int := io.timer_int - swerv.io.soft_int := io.soft_int - swerv.io.extintsrc_req := io.extintsrc_req + core.io.timer_int := io.timer_int + core.io.soft_int := io.soft_int + core.io.extintsrc_req := io.extintsrc_req // Outputs - val core_rst_l = swerv.io.core_rst_l - io.rv_trace_pkt := swerv.io.rv_trace_pkt + val core_rst_l = core.io.core_rst_l + io.rv_trace_pkt := core.io.rv_trace_pkt // external halt/run interface - io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack - io.o_cpu_halt_status := swerv.io.o_cpu_halt_status - io.o_cpu_run_ack := swerv.io.o_cpu_run_ack - io.o_debug_mode_status := swerv.io.o_debug_mode_status + io.o_cpu_halt_ack := core.io.o_cpu_halt_ack + io.o_cpu_halt_status := core.io.o_cpu_halt_status + io.o_cpu_run_ack := core.io.o_cpu_run_ack + io.o_debug_mode_status := core.io.o_debug_mode_status - io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack - io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack - io.debug_brkpt_status := swerv.io.debug_brkpt_status + io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := core.io.mpc_debug_run_ack + io.debug_brkpt_status := core.io.debug_brkpt_status - io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0 - io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1 - io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2 - io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3 + io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels // DMA Slave - io.dma_hrdata := swerv.io.dma_hrdata - io.dma_hreadyout := swerv.io.dma_hreadyout - io.dma_hresp := swerv.io.dma_hresp + io.dma_hrdata := core.io.dma_hrdata + io.dma_hreadyout := core.io.dma_hreadyout + io.dma_hresp := core.io.dma_hresp } object QUASAR_Wrp extends App { diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 56baf53a29ae6355d11074b0ab3b7a0e9a12312a..269d4e31dc280f4d2677e3f8cae4079247873cc3 100644 GIT binary patch delta 99 zcmbO%H(74O4KBtLlW%g_0!ag2@yUAJo={dlw-u0eirWTAvhzUXB`3%6SOEFcd0fG& iBqx94u>`YX7*9^_<@IGf$)L_~V)A|73ZQ5N-);b_k0N^j delta 99 zcmbO%H(74O4KBtTlW%g_0!ag2@yUAJo={dlw-u0eirWTAvhzUXB`3%6SOEFcd0fG& iBqx94u>`YX7;jGQ<@IH~$)L_~WAc683ZQ5N-);cVKO;*3 diff --git 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