diff --git a/EL2_IC_TAG.fir b/EL2_IC_TAG.fir index 0c4dbfcd..a7e33f79 100644 --- a/EL2_IC_TAG.fir +++ b/EL2_IC_TAG.fir @@ -3,19 +3,45 @@ circuit EL2_IC_TAG : module EL2_IC_TAG : input clock : Clock input reset : UInt<1> - output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<29>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>, test : UInt} + output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<32>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>, test : UInt} - node _T = bits(io.ic_rw_addr, 5, 4) @[el2_ifu_ic_mem.scala 68:69] - wire _T_1 : UInt<1>[1] @[el2_lib.scala 39:24] - _T_1[0] <= UInt<1>("h01") @[el2_lib.scala 39:24] - node _T_2 = eq(_T, _T_1[0]) @[el2_ifu_ic_mem.scala 68:92] - wire _T_3 : UInt<1>[2] @[el2_lib.scala 39:24] - _T_3[0] <= _T_2 @[el2_lib.scala 39:24] - _T_3[1] <= _T_2 @[el2_lib.scala 39:24] + node _T = bits(io.ic_rw_addr, 5, 4) @[el2_ifu_ic_mem.scala 68:70] + wire _T_1 : UInt<1>[1] @[el2_lib.scala 40:24] + _T_1[0] <= UInt<1>("h01") @[el2_lib.scala 40:24] + node _T_2 = eq(_T, _T_1[0]) @[el2_ifu_ic_mem.scala 68:93] + wire _T_3 : UInt<1>[2] @[el2_lib.scala 40:24] + _T_3[0] <= _T_2 @[el2_lib.scala 40:24] + _T_3[1] <= _T_2 @[el2_lib.scala 40:24] node _T_4 = cat(_T_3[0], _T_3[1]) @[Cat.scala 29:58] - node ic_tag_wren = and(io.ic_wr_en, _T_4) @[el2_ifu_ic_mem.scala 68:32] - io.test <= ic_tag_wren @[el2_ifu_ic_mem.scala 72:10] - io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 73:18] - io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 74:16] - io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 75:26] + node ic_tag_wren = and(io.ic_wr_en, _T_4) @[el2_ifu_ic_mem.scala 68:33] + node _T_5 = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 70:68] + wire _T_6 : UInt<1>[2] @[el2_lib.scala 40:24] + _T_6[0] <= _T_5 @[el2_lib.scala 40:24] + _T_6[1] <= _T_5 @[el2_lib.scala 40:24] + node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58] + node ic_debug_rd_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 70:93] + node _T_8 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 71:68] + wire _T_9 : UInt<1>[2] @[el2_lib.scala 40:24] + _T_9[0] <= _T_8 @[el2_lib.scala 40:24] + _T_9[1] <= _T_8 @[el2_lib.scala 40:24] + node _T_10 = cat(_T_9[0], _T_9[1]) @[Cat.scala 29:58] + node ic_debug_wr_way_en = and(_T_10, io.ic_debug_way) @[el2_ifu_ic_mem.scala 71:93] + node _T_11 = or(io.ic_rd_en, io.clk_override) @[el2_ifu_ic_mem.scala 72:55] + wire _T_12 : UInt<1>[2] @[el2_lib.scala 40:24] + _T_12[0] <= _T_11 @[el2_lib.scala 40:24] + _T_12[1] <= _T_11 @[el2_lib.scala 40:24] + node _T_13 = cat(_T_12[0], _T_12[1]) @[Cat.scala 29:58] + node _T_14 = or(_T_13, io.ic_wr_en) @[el2_ifu_ic_mem.scala 72:74] + node _T_15 = or(_T_14, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 72:88] + node ic_tag_clken = or(_T_15, ic_debug_rd_way_en) @[el2_ifu_ic_mem.scala 72:109] + reg ic_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 74:28] + ic_rd_en_ff <= io.ic_rd_en @[el2_ifu_ic_mem.scala 74:28] + node _T_16 = bits(io.ic_rw_addr, 31, 13) @[el2_ifu_ic_mem.scala 75:44] + reg ic_rw_addr_ff : UInt, clock @[el2_ifu_ic_mem.scala 75:30] + ic_rw_addr_ff <= _T_16 @[el2_ifu_ic_mem.scala 75:30] + node ic_tag_wren_q = or(ic_tag_wren, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 77:35] + io.test <= ic_tag_wren @[el2_ifu_ic_mem.scala 80:10] + io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 81:18] + io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 82:16] + io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 83:26] diff --git a/EL2_IC_TAG.v b/EL2_IC_TAG.v index cf9ee518..cf8d19c3 100644 --- a/EL2_IC_TAG.v +++ b/EL2_IC_TAG.v @@ -5,7 +5,7 @@ module EL2_IC_TAG( input io_rst_l, input io_clk_override, input io_dec_tlu_core_ecc_disable, - input [28:0] io_ic_rw_addr, + input [31:0] io_ic_rw_addr, input [1:0] io_ic_wr_en, input [1:0] io_ic_tag_valid, input io_ic_rd_en, @@ -21,10 +21,10 @@ module EL2_IC_TAG( input io_scan_mode, output [1:0] io_test ); - wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 68:92] + wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 68:93] wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58] - assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 75:26] - assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 74:16] - assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 73:18] - assign io_test = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 72:10] + assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 83:26] + assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 82:16] + assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 81:18] + assign io_test = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 80:10] endmodule diff --git a/rvdffs.anno.json b/rvdffs.anno.json new file mode 100644 index 00000000..658bbb95 --- /dev/null +++ b/rvdffs.anno.json @@ -0,0 +1,18 @@ +[ + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"rvdffs" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/rvdffs.fir b/rvdffs.fir new file mode 100644 index 00000000..396604c2 --- /dev/null +++ b/rvdffs.fir @@ -0,0 +1,78 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit rvdffs : + module rvdffs : + input clock : Clock + input reset : UInt<1> + output io : {flip din : UInt<32>, flip en : UInt<1>, flip clear : UInt<1>, out : UInt} + + wire _T : UInt<1>[32] @[el2_lib.scala 40:24] + _T[0] <= io.clear @[el2_lib.scala 40:24] + _T[1] <= io.clear @[el2_lib.scala 40:24] + _T[2] <= io.clear @[el2_lib.scala 40:24] + _T[3] <= io.clear @[el2_lib.scala 40:24] + _T[4] <= io.clear @[el2_lib.scala 40:24] + _T[5] <= io.clear @[el2_lib.scala 40:24] + _T[6] <= io.clear @[el2_lib.scala 40:24] + _T[7] <= io.clear @[el2_lib.scala 40:24] + _T[8] <= io.clear @[el2_lib.scala 40:24] + _T[9] <= io.clear @[el2_lib.scala 40:24] + _T[10] <= io.clear @[el2_lib.scala 40:24] + _T[11] <= io.clear @[el2_lib.scala 40:24] + _T[12] <= io.clear @[el2_lib.scala 40:24] + _T[13] <= io.clear @[el2_lib.scala 40:24] + _T[14] <= io.clear @[el2_lib.scala 40:24] + _T[15] <= io.clear @[el2_lib.scala 40:24] + _T[16] <= io.clear @[el2_lib.scala 40:24] + _T[17] <= io.clear @[el2_lib.scala 40:24] + _T[18] <= io.clear @[el2_lib.scala 40:24] + _T[19] <= io.clear @[el2_lib.scala 40:24] + _T[20] <= io.clear @[el2_lib.scala 40:24] + _T[21] <= io.clear @[el2_lib.scala 40:24] + _T[22] <= io.clear @[el2_lib.scala 40:24] + _T[23] <= io.clear @[el2_lib.scala 40:24] + _T[24] <= io.clear @[el2_lib.scala 40:24] + _T[25] <= io.clear @[el2_lib.scala 40:24] + _T[26] <= io.clear @[el2_lib.scala 40:24] + _T[27] <= io.clear @[el2_lib.scala 40:24] + _T[28] <= io.clear @[el2_lib.scala 40:24] + _T[29] <= io.clear @[el2_lib.scala 40:24] + _T[30] <= io.clear @[el2_lib.scala 40:24] + _T[31] <= io.clear @[el2_lib.scala 40:24] + node _T_1 = cat(_T[0], _T[1]) @[Cat.scala 29:58] + node _T_2 = cat(_T_1, _T[2]) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, _T[3]) @[Cat.scala 29:58] + node _T_4 = cat(_T_3, _T[4]) @[Cat.scala 29:58] + node _T_5 = cat(_T_4, _T[5]) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T[6]) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T[7]) @[Cat.scala 29:58] + node _T_8 = cat(_T_7, _T[8]) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, _T[9]) @[Cat.scala 29:58] + node _T_10 = cat(_T_9, _T[10]) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T[11]) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T[12]) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T[13]) @[Cat.scala 29:58] + node _T_14 = cat(_T_13, _T[14]) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T[15]) @[Cat.scala 29:58] + node _T_16 = cat(_T_15, _T[16]) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, _T[17]) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T[18]) @[Cat.scala 29:58] + node _T_19 = cat(_T_18, _T[19]) @[Cat.scala 29:58] + node _T_20 = cat(_T_19, _T[20]) @[Cat.scala 29:58] + node _T_21 = cat(_T_20, _T[21]) @[Cat.scala 29:58] + node _T_22 = cat(_T_21, _T[22]) @[Cat.scala 29:58] + node _T_23 = cat(_T_22, _T[23]) @[Cat.scala 29:58] + node _T_24 = cat(_T_23, _T[24]) @[Cat.scala 29:58] + node _T_25 = cat(_T_24, _T[25]) @[Cat.scala 29:58] + node _T_26 = cat(_T_25, _T[26]) @[Cat.scala 29:58] + node _T_27 = cat(_T_26, _T[27]) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, _T[28]) @[Cat.scala 29:58] + node _T_29 = cat(_T_28, _T[29]) @[Cat.scala 29:58] + node _T_30 = cat(_T_29, _T[30]) @[Cat.scala 29:58] + node _T_31 = cat(_T_30, _T[31]) @[Cat.scala 29:58] + node _T_32 = and(io.din, _T_31) @[el2_ifu_ic_mem.scala 93:30] + reg _T_33 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.en : @[Reg.scala 28:19] + _T_33 <= _T_32 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.out <= _T_33 @[el2_ifu_ic_mem.scala 93:10] + diff --git a/rvdffs.v b/rvdffs.v new file mode 100644 index 00000000..a4788128 --- /dev/null +++ b/rvdffs.v @@ -0,0 +1,70 @@ +module rvdffs( + input clock, + input reset, + input [31:0] io_din, + input io_en, + input io_clear, + output [31:0] io_out +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire [9:0] _T_9 = {io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58] + wire [18:0] _T_18 = {_T_9,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58] + wire [27:0] _T_27 = {_T_18,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58] + wire [31:0] _T_31 = {_T_27,io_clear,io_clear,io_clear,io_clear}; // @[Cat.scala 29:58] + wire [31:0] _T_32 = io_din & _T_31; // @[el2_ifu_ic_mem.scala 93:30] + reg [31:0] _T_33; // @[Reg.scala 27:20] + assign io_out = _T_33; // @[el2_ifu_ic_mem.scala 93:10] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_33 = _RAND_0[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock) begin + if (reset) begin + _T_33 <= 32'h0; + end else if (io_en) begin + _T_33 <= _T_32; + end + end +endmodule diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala index b458a472..b7157929 100644 --- a/src/main/scala/ifu/el2_ifu_ic_mem.scala +++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala @@ -46,7 +46,7 @@ class EL2_IC_TAG extends Module with el2_lib with param { val rst_l = Input(Bool()) val clk_override = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool()) - val ic_rw_addr = Input(UInt(29.W)) + val ic_rw_addr = Input(UInt(32.W)) // TODO : In SV we have 31:3 what should we do here val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_rd_en = Input(Bool()) @@ -76,11 +76,13 @@ class EL2_IC_TAG extends Module with el2_lib with param { val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en + io.test:= ic_tag_wren io.ic_tag_perr := 0.U io.ic_rd_hit := 0.U io.ictag_debug_rd_data := 0.U } + object ifu_ic extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG())) } \ No newline at end of file diff --git a/src/main/scala/lib/GCD.scala b/src/main/scala/lib/GCD.scala index 6a0f200c..7cb03f12 100644 --- a/src/main/scala/lib/GCD.scala +++ b/src/main/scala/lib/GCD.scala @@ -2,7 +2,7 @@ package lib import chisel3._ import chisel3.util._ - +/* /////////////////////////////////////////////////////////////// class rvdff(val Width:Int = 1, val short:Int = 0) extends Module with RequireAsyncReset { val io = IO(new Bundle { @@ -120,4 +120,4 @@ class exp extends Module{ } //////////////////////////////////////////////////////////////// -//println((new chisel3.stage.ChiselStage).emitVerilog(new exp)) \ No newline at end of file +//println((new chisel3.stage.ChiselStage).emitVerilog(new exp))*/ \ No newline at end of file diff --git a/src/main/scala/lib/beh_lib.scala b/src/main/scala/lib/beh_lib.scala index 51175ec3..ec4a1131 100644 --- a/src/main/scala/lib/beh_lib.scala +++ b/src/main/scala/lib/beh_lib.scala @@ -18,6 +18,25 @@ else {io.dout := flop} } +class rvdffsc extends Module with el2_lib { + val io = IO(new Bundle{ + val din = Input(UInt(32.W)) + val en = Input(Bool()) + val clear = Input(Bool()) + val out = Output(UInt()) + }) + io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en) +} + +class rvdffs extends Module with el2_lib { + val io = IO(new Bundle{ + val din = Input(UInt(32.W)) + val en = Input(Bool()) + val clear = Input(Bool()) + val out = Output(UInt()) + }) + io.out := RegEnable(io.din, 0.U, io.en) +} class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing val io = IO(new Bundle{ @@ -186,7 +205,7 @@ class rvecc_encode extends Module{ //Done for verification and testing } - +// Make generator and then make it a method class rvecc_decode extends Module{ //Done for verification and testing val io = IO(new Bundle{ val en = Input(UInt(1.W)) diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala index 3417232d..b6c9677e 100644 --- a/src/main/scala/lib/el2_lib.scala +++ b/src/main/scala/lib/el2_lib.scala @@ -38,4 +38,38 @@ trait el2_lib extends param{ def repl(b:Int, a:UInt) : UInt = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) + + + + + // Move rvecc_encode to a proper trait + def rvecc_encode(din:UInt) = { //Done for verification and testing + val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1) + val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1) + val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0) + val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0) + val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0) + val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) + val w0 = Wire(Vec(18,UInt(1.W))) + val w1 = Wire(Vec(18,UInt(1.W))) + val w2 = Wire(Vec(18,UInt(1.W))) + val w3 = Wire(Vec(15,UInt(1.W))) + val w4 = Wire(Vec(15,UInt(1.W))) + val w5 = Wire(Vec(6, UInt(1.W))) + var j = 0;var k = 0;var m = 0; + var x = 0;var y = 0;var z = 0 + + for(i <- 0 to 31) + { + if(mask0(i)==1) {w0(j) := din(i); j = j +1 } + if(mask1(i)==1) {w1(k) := din(i); k = k +1 } + if(mask2(i)==1) {w2(m) := din(i); m = m +1 } + if(mask3(i)==1) {w3(x) := din(i); x = x +1 } + if(mask4(i)==1) {w4(y) := din(i); y = y +1 } + if(mask5(i)==1) {w5(z) := din(i); z = z +1 } + } + val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR)) + Cat(din.xorR ^ w6.xorR, w6) + } + } diff --git a/src/test/scala/lib/Tester.scala b/src/test/scala/lib/Tester.scala index dcf36414..227cde7e 100644 --- a/src/test/scala/lib/Tester.scala +++ b/src/test/scala/lib/Tester.scala @@ -3,7 +3,7 @@ import java.io.File import chisel3.iotesters import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} - +/* class Tester(c: encoder_generator) extends PeekPokeTester(c) { poke(c.io.in, 1) @@ -29,3 +29,4 @@ object GCDMain extends App { c => new Tester(c) } } +*/ \ No newline at end of file diff --git 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