Clk enable removed from predictor

This commit is contained in:
waleed-lm 2020-10-07 09:35:34 +05:00
parent c1491ee7dd
commit 714376af0a
13 changed files with 9072 additions and 9719 deletions

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

18
el2_ifu_mem_ctl.anno.json Normal file
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@ -0,0 +1,18 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_ifu_mem_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

83
el2_ifu_mem_ctl.fir Normal file
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_mem_ctl :
module el2_ifu_mem_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>}
io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 126:20]
io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 127:20]
io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:24]
io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:25]
io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:21]
io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:19]
io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:20]
io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:21]
io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:23]
io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:22]
io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:22]
io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:21]
io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:18]
io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:20]
io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:19]
io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:21]
io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:19]
io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:19]
io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:20]
io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:21]
io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:19]
io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:18]
io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:20]
io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:22]
io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:19]
io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:20]
io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:21]
io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:19]
io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:24]
io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:21]
io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:20]
io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:19]
io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:16]
io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:16]
io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:14]
io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:14]
io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:22]
io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:26]
io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:18]
io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:18]
io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:15]
io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:15]
io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:18]
io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:18]
io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:14]
io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:23]
io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:28]
io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:28]
io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:20]
io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:27]
io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:23]
io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:20]
io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:15]
io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:24]
io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:32]
io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:26]
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:27]
io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:18]
io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:22]

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el2_ifu_mem_ctl.v Normal file
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module el2_ifu_mem_ctl(
input clock,
input reset,
input io_free_clk,
input io_active_clk,
input io_exu_flush_final,
input io_dec_tlu_flush_lower_wb,
input io_dec_tlu_flush_err_wb,
input io_dec_tlu_i0_commit_cmt,
input io_dec_tlu_force_halt,
input [30:0] io_ifc_fetch_addr_bf,
input io_ifc_fetch_uncacheable_bf,
input io_ifc_fetch_req_bf,
input io_ifc_fetch_req_bf_raw,
input io_ifc_iccm_access_bf,
input io_ifc_region_acc_fault_bf,
input io_ifc_dma_access_ok,
input io_dec_tlu_fence_i_wb,
input io_ifu_bp_hit_taken_f,
input io_ifu_bp_inst_mask_f,
output io_ifu_miss_state_idle,
output io_ifu_ic_mb_empty,
output io_ic_dma_active,
output io_ic_write_stall,
output io_ifu_pmu_ic_miss,
output io_ifu_pmu_ic_hit,
output io_ifu_pmu_bus_error,
output io_ifu_pmu_bus_busy,
output io_ifu_pmu_bus_trxn,
output io_ifu_axi_awvalid,
output [2:0] io_ifu_axi_awid,
output [31:0] io_ifu_axi_awaddr,
output [3:0] io_ifu_axi_awregion,
output [7:0] io_ifu_axi_awlen,
output [2:0] io_ifu_axi_awsize,
output [1:0] io_ifu_axi_awburst,
output io_ifu_axi_awlock,
output [3:0] io_ifu_axi_awcache,
output [2:0] io_ifu_axi_awprot,
output [3:0] io_ifu_axi_awqos,
output io_ifu_axi_wvalid,
output [63:0] io_ifu_axi_wdata,
output [7:0] io_ifu_axi_wstrb,
output io_ifu_axi_wlast,
output io_ifu_axi_bready,
output io_ifu_axi_arvalid,
input io_ifu_axi_arready,
output [2:0] io_ifu_axi_arid,
output [31:0] io_ifu_axi_araddr,
output [3:0] io_ifu_axi_arregion,
output [7:0] io_ifu_axi_arlen,
output [2:0] io_ifu_axi_arsize,
output [1:0] io_ifu_axi_arburst,
output io_ifu_axi_arlock,
output [3:0] io_ifu_axi_arcache,
output [2:0] io_ifu_axi_arprot,
output [3:0] io_ifu_axi_arqos,
input io_ifu_axi_rvalid,
output io_ifu_axi_rready,
input [2:0] io_ifu_axi_rid,
input [63:0] io_ifu_axi_rdata,
input [1:0] io_ifu_axi_rresp,
input io_ifu_bus_clk_en,
input io_dma_iccm_req,
input [31:0] io_dma_mem_addr,
input [2:0] io_dma_mem_sz,
input io_dma_mem_write,
input [63:0] io_dma_mem_wdata,
input [2:0] io_dma_mem_tag,
output io_iccm_dma_ecc_error,
output io_iccm_dma_rvalid,
output [63:0] io_iccm_dma_rdata,
output [2:0] io_iccm_dma_rtag,
output io_iccm_ready,
output [30:0] io_ic_rw_addr,
output [1:0] io_ic_wr_en,
output io_ic_rd_en,
output [70:0] io_ic_wr_data_0,
output [70:0] io_ic_wr_data_1,
input [63:0] io_ic_rd_data,
input [70:0] io_ic_debug_rd_data,
input [25:0] io_ictag_debug_rd_data,
output [70:0] io_ic_debug_wr_data,
output [70:0] io_ifu_ic_debug_rd_data,
input [1:0] io_ic_eccerr,
input [1:0] io_ic_parerr,
output [9:0] io_ic_debug_addr,
output io_ic_debug_rd_en,
output io_ic_debug_wr_en,
output io_ic_debug_tag_array,
output [1:0] io_ic_debug_way,
output [1:0] io_ic_tag_valid,
input [1:0] io_ic_rd_hit,
input io_ic_tag_perr,
output [14:0] io_iccm_rw_addr,
output io_iccm_wren,
output io_iccm_rden,
output [77:0] io_iccm_wr_data,
output [2:0] io_iccm_wr_size,
input [63:0] io_iccm_rd_data,
input [77:0] io_iccm_rd_data_ecc,
input [1:0] io_ifu_fetch_val,
output io_ic_hit_f,
output io_ic_access_fault_f,
output [1:0] io_ic_access_fault_type_f,
output io_iccm_rd_ecc_single_err,
output io_iccm_rd_ecc_double_err,
output io_ic_error_start,
output io_ifu_async_error_start,
output io_iccm_dma_sb_error,
output [1:0] io_ic_fetch_val_f,
output [31:0] io_ic_data_f,
output [63:0] io_ic_premux_data,
output io_ic_sel_premux_data,
input [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata,
input [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics,
input io_dec_tlu_ic_diag_pkt_icache_rd_valid,
input io_dec_tlu_ic_diag_pkt_icache_wr_valid,
input io_dec_tlu_core_ecc_disable,
output io_ifu_ic_debug_rd_data_valid,
output io_iccm_buf_correct_ecc,
output io_iccm_correction_state
);
assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 129:25]
assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 130:21]
assign io_ic_dma_active = 1'h0; // @[el2_ifu_mem_ctl.scala 131:19]
assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 132:20]
assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 133:21]
assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 135:23]
assign io_ifu_pmu_bus_busy = 1'h0; // @[el2_ifu_mem_ctl.scala 136:22]
assign io_ifu_pmu_bus_trxn = 1'h0; // @[el2_ifu_mem_ctl.scala 137:22]
assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:21]
assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 139:18]
assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 140:20]
assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 199:22]
assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 141:19]
assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 142:20]
assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 143:21]
assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 144:20]
assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 145:21]
assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 146:20]
assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 147:19]
assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 148:20]
assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 149:19]
assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 150:19]
assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 151:19]
assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 152:20]
assign io_ifu_axi_arvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 153:21]
assign io_ifu_axi_arid = 3'h0; // @[el2_ifu_mem_ctl.scala 155:18]
assign io_ifu_axi_araddr = 32'h0; // @[el2_ifu_mem_ctl.scala 156:20]
assign io_ifu_axi_arregion = 4'h0; // @[el2_ifu_mem_ctl.scala 157:22]
assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 158:19]
assign io_ifu_axi_arsize = 3'h0; // @[el2_ifu_mem_ctl.scala 159:20]
assign io_ifu_axi_arburst = 2'h0; // @[el2_ifu_mem_ctl.scala 160:21]
assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 161:20]
assign io_ifu_axi_arcache = 4'h0; // @[el2_ifu_mem_ctl.scala 162:21]
assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 163:20]
assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 164:19]
assign io_ifu_axi_rready = 1'h0; // @[el2_ifu_mem_ctl.scala 165:20]
assign io_iccm_dma_ecc_error = 1'h0; // @[el2_ifu_mem_ctl.scala 166:24]
assign io_iccm_dma_rvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 167:21]
assign io_iccm_dma_rdata = 64'h0; // @[el2_ifu_mem_ctl.scala 168:20]
assign io_iccm_dma_rtag = 3'h0; // @[el2_ifu_mem_ctl.scala 169:19]
assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 170:16]
assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 171:16]
assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 172:14]
assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 173:14]
assign io_ic_wr_data_0 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
assign io_ic_wr_data_1 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
assign io_ic_debug_wr_data = 71'h0; // @[el2_ifu_mem_ctl.scala 175:22]
assign io_ifu_ic_debug_rd_data = 71'h0; // @[el2_ifu_mem_ctl.scala 176:26]
assign io_ic_debug_addr = 10'h0; // @[el2_ifu_mem_ctl.scala 154:19]
assign io_ic_debug_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 126:20]
assign io_ic_debug_wr_en = 1'h0; // @[el2_ifu_mem_ctl.scala 127:20]
assign io_ic_debug_tag_array = 1'h0; // @[el2_ifu_mem_ctl.scala 128:24]
assign io_ic_debug_way = 2'h0; // @[el2_ifu_mem_ctl.scala 198:18]
assign io_ic_tag_valid = 2'h0; // @[el2_ifu_mem_ctl.scala 177:18]
assign io_iccm_rw_addr = 15'h0; // @[el2_ifu_mem_ctl.scala 178:18]
assign io_iccm_wren = 1'h0; // @[el2_ifu_mem_ctl.scala 179:15]
assign io_iccm_rden = 1'h0; // @[el2_ifu_mem_ctl.scala 180:15]
assign io_iccm_wr_data = 78'h0; // @[el2_ifu_mem_ctl.scala 181:18]
assign io_iccm_wr_size = 3'h0; // @[el2_ifu_mem_ctl.scala 182:18]
assign io_ic_hit_f = 1'h0; // @[el2_ifu_mem_ctl.scala 183:14]
assign io_ic_access_fault_f = 1'h0; // @[el2_ifu_mem_ctl.scala 184:23]
assign io_ic_access_fault_type_f = 2'h0; // @[el2_ifu_mem_ctl.scala 185:28]
assign io_iccm_rd_ecc_single_err = 1'h0; // @[el2_ifu_mem_ctl.scala 186:28]
assign io_iccm_rd_ecc_double_err = 1'h0; // @[el2_ifu_mem_ctl.scala 187:28]
assign io_ic_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 188:20]
assign io_ifu_async_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 189:27]
assign io_iccm_dma_sb_error = 1'h0; // @[el2_ifu_mem_ctl.scala 190:23]
assign io_ic_fetch_val_f = 2'h0; // @[el2_ifu_mem_ctl.scala 191:20]
assign io_ic_data_f = 32'h0; // @[el2_ifu_mem_ctl.scala 192:15]
assign io_ic_premux_data = 64'h0; // @[el2_ifu_mem_ctl.scala 193:20]
assign io_ic_sel_premux_data = 1'h0; // @[el2_ifu_mem_ctl.scala 194:24]
assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 195:32]
assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 196:26]
assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 197:27]
endmodule

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@ -393,7 +393,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W)))) val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){ for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(j)(k), 0.U, bht_bank_sel(i)(j)(k)&bht_bank_clken(i)(k)) bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(j)(k), 0.U, bht_bank_sel(i)(j)(k))
} }
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))

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@ -0,0 +1,205 @@
package ifu
import chisel3._
import chisel3.util._
import lib._
import include._
import scala.math.pow
class el2_ifu_mem_ctl extends Module with el2_lib {
val io = IO(new Bundle {
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val exu_flush_final = Input(Bool())
val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_err_wb = Input(Bool())
val dec_tlu_i0_commit_cmt = Input(Bool())
val dec_tlu_force_halt = Input(Bool())
val ifc_fetch_addr_bf = Input(UInt(31.W))
val ifc_fetch_uncacheable_bf = Input(Bool())
val ifc_fetch_req_bf = Input(Bool())
val ifc_fetch_req_bf_raw = Input(Bool())
val ifc_iccm_access_bf = Input(Bool())
val ifc_region_acc_fault_bf = Input(Bool())
val ifc_dma_access_ok = Input(Bool())
val dec_tlu_fence_i_wb = Input(Bool())
val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_inst_mask_f = Input(Bool())
val ifu_miss_state_idle = Output(Bool())
val ifu_ic_mb_empty = Output(Bool())
val ic_dma_active = Output(Bool())
val ic_write_stall = Output(Bool())
val ifu_pmu_ic_miss = Output(Bool())
val ifu_pmu_ic_hit = Output(Bool())
val ifu_pmu_bus_error = Output(Bool())
val ifu_pmu_bus_busy = Output(Bool())
val ifu_pmu_bus_trxn = Output(Bool())
val ifu_axi_awvalid = Output(Bool())
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_awaddr = Output(UInt(32.W))
val ifu_axi_awregion = Output(UInt(4.W))
val ifu_axi_awlen = Output(UInt(8.W))
val ifu_axi_awsize = Output(UInt(3.W))
val ifu_axi_awburst = Output(UInt(2.W))
val ifu_axi_awlock = Output(Bool())
val ifu_axi_awcache = Output(UInt(4.W))
val ifu_axi_awprot = Output(UInt(3.W))
val ifu_axi_awqos = Output(UInt(4.W))
val ifu_axi_wvalid = Output(Bool())
val ifu_axi_wdata = Output(UInt(64.W))
val ifu_axi_wstrb = Output(UInt(8.W))
val ifu_axi_wlast = Output(Bool())
val ifu_axi_bready = Output(Bool())
val ifu_axi_arvalid = Output(Bool())
val ifu_axi_arready = Input(Bool())
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
val ifu_axi_araddr = Output(UInt(32.W))
val ifu_axi_arregion = Output(UInt(4.W))
val ifu_axi_arlen = Output(UInt(8.W))
val ifu_axi_arsize = Output(UInt(3.W))
val ifu_axi_arburst = Output(UInt(2.W))
val ifu_axi_arlock = Output(Bool())
val ifu_axi_arcache = Output(UInt(4.W))
val ifu_axi_arprot = Output(UInt(3.W))
val ifu_axi_arqos = Output(UInt(4.W))
val ifu_axi_rvalid = Input(Bool())
val ifu_axi_rready = Output(Bool())
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
val ifu_axi_rdata = Input(UInt(64.W))
val ifu_axi_rresp = Input(UInt(2.W))
val ifu_bus_clk_en = Input(Bool())
val dma_iccm_req = Input(Bool())
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W))
val dma_mem_write = Input(Bool())
val dma_mem_wdata = Input(UInt(64.W))
val dma_mem_tag = Input(UInt(3.W))
val iccm_dma_ecc_error = Output(Bool())
val iccm_dma_rvalid = Output(Bool())
val iccm_dma_rdata = Output(UInt(64.W))
val iccm_dma_rtag = Output(UInt(3.W))
val iccm_ready = Output(Bool())
val ic_rw_addr = Output(UInt(31.W))
val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Output(Bool())
val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
val ic_rd_data = Input(UInt(64.W))
val ic_debug_rd_data = Input(UInt(71.W))
val ictag_debug_rd_data = Input(UInt(26.W))
val ic_debug_wr_data = Output(UInt(71.W))
val ifu_ic_debug_rd_data = Output(UInt(71.W))
val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W))
val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W))
val ic_debug_rd_en = Output(Bool())
val ic_debug_wr_en = Output(Bool())
val ic_debug_tag_array = Output(Bool())
val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Input(Bool())
val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W))
val iccm_wren = Output(Bool())
val iccm_rden = Output(Bool())
val iccm_wr_data = Output(UInt(78.W))
val iccm_wr_size = Output(UInt(3.W))
val iccm_rd_data = Input(UInt(64.W))
val iccm_rd_data_ecc = Input(UInt(78.W))
val ifu_fetch_val = Input(UInt(2.W))
val ic_hit_f = Output(Bool())
val ic_access_fault_f = Output(Bool())
val ic_access_fault_type_f = Output(UInt(2.W))
val iccm_rd_ecc_single_err = Output(Bool())
val iccm_rd_ecc_double_err = Output(Bool())
val ic_error_start = Output(Bool())
val ifu_async_error_start = Output(Bool())
val iccm_dma_sb_error = Output(Bool())
val ic_fetch_val_f = Output(UInt(2.W))
val ic_data_f = Output(UInt(32.W))
val ic_premux_data = Output(UInt(64.W))
val ic_sel_premux_data = Output(Bool())
val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t)
val dec_tlu_core_ecc_disable = Input(Bool())
val ifu_ic_debug_rd_data_valid = Output(Bool())
val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool())
})
io.ic_debug_rd_en:=0.U
io.ic_debug_wr_en:=0.U
io.ic_debug_tag_array:=0.U
io.ifu_miss_state_idle:=0.U
io.ifu_ic_mb_empty:=0.U
io.ic_dma_active:=0.U
io.ic_write_stall:=0.U
io.ifu_pmu_ic_miss:=0.U
io.ifu_pmu_ic_hit:=0.U
io.ifu_pmu_bus_error:=0.U
io.ifu_pmu_bus_busy:=0.U
io.ifu_pmu_bus_trxn:=0.U
io.ifu_axi_awvalid:=0.U
io.ifu_axi_awid:=0.U
io.ifu_axi_awaddr:=0.U
io.ifu_axi_awlen:=0.U
io.ifu_axi_awsize:=0.U
io.ifu_axi_awburst:=0.U
io.ifu_axi_awlock:=0.U
io.ifu_axi_awcache:=0.U
io.ifu_axi_awprot:=0.U
io.ifu_axi_awqos:=0.U
io.ifu_axi_wvalid:=0.U
io.ifu_axi_wdata:=0.U
io.ifu_axi_wstrb:=0.U
io.ifu_axi_wlast:=0.U
io.ifu_axi_bready:=0.U
io.ifu_axi_arvalid:=0.U
io.ic_debug_addr:=0.U
io.ifu_axi_arid:=0.U
io.ifu_axi_araddr:=0.U
io.ifu_axi_arregion:=0.U
io.ifu_axi_arlen:=0.U
io.ifu_axi_arsize:=0.U
io.ifu_axi_arburst:=0.U
io.ifu_axi_arlock:=0.U
io.ifu_axi_arcache:=0.U
io.ifu_axi_arprot:=0.U
io.ifu_axi_arqos:=0.U
io.ifu_axi_rready:=0.U
io.iccm_dma_ecc_error:=0.U
io.iccm_dma_rvalid:=0.U
io.iccm_dma_rdata:=0.U
io.iccm_dma_rtag:=0.U
io.iccm_ready:=0.U
io.ic_rw_addr:=0.U
io.ic_wr_en:=0.U
io.ic_rd_en:=0.U
io.ic_wr_data:=(0 until ICACHE_BANKS_WAY).map(i=>0.U) // TODO
io.ic_debug_wr_data:=0.U
io.ifu_ic_debug_rd_data:=0.U
io.ic_tag_valid:=0.U
io.iccm_rw_addr:=0.U
io.iccm_wren:=0.U
io.iccm_rden:=0.U
io.iccm_wr_data:=0.U
io.iccm_wr_size:=0.U
io.ic_hit_f:=0.U
io.ic_access_fault_f:=0.U
io.ic_access_fault_type_f:=0.U
io.iccm_rd_ecc_single_err:=0.U
io.iccm_rd_ecc_double_err:=0.U
io.ic_error_start:=0.U
io.ifu_async_error_start:=0.U
io.iccm_dma_sb_error:=0.U
io.ic_fetch_val_f:=0.U
io.ic_data_f:=0.U
io.ic_premux_data:=0.U
io.ic_sel_premux_data:=0.U
io.ifu_ic_debug_rd_data_valid:=0.U
io.iccm_buf_correct_ecc:=0.U
io.iccm_correction_state:=0.U
io.ic_debug_way:=0.U
io.ifu_axi_awregion:=0.U
}
object ifu_mem extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
}

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