bus_intf added

This commit is contained in:
​Laraib Khan 2020-12-29 11:47:28 +05:00
parent 119a9ad388
commit 722fb8bdc0
7 changed files with 6879 additions and 6866 deletions

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File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -200,3 +200,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
} }
} }
object bus_intf extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
}

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