bus_intf added

2020-12-29 11:47:28 +05:00 · 2020-12-29 11:47:28 +05:00 · 722fb8bdc0
parent 119a9ad388
commit 722fb8bdc0
7 changed files with 6879 additions and 6866 deletions
--- a/lsu_bus_buffer.fir
+++ b/lsu_bus_buffer.fir
--- a/lsu_bus_intf.fir
+++ b/lsu_bus_intf.fir
--- a/lsu_bus_intf.v
+++ b/lsu_bus_intf.v
--- a/src/main/scala/lsu/lsu_bus_intf.scala
+++ b/src/main/scala/lsu/lsu_bus_intf.scala
@ -200,3 +200,6 @@ class  lsu_bus_intf extends Module with RequireAsyncReset with lib {
    ldst_byteen_r     := RegNext(ldst_byteen_m, init = 0.U(4.W))
  }
 }
+object bus_intf extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
+}
--- a/target/scala-2.12/classes/lsu/bus_intf$.class
+++ b/target/scala-2.12/classes/lsu/bus_intf$.class
--- a/target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class
+++ b/target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class
--- a/target/scala-2.12/classes/lsu/bus_intf.class
+++ b/target/scala-2.12/classes/lsu/bus_intf.class