diff --git a/el2_ifu_bp_ctl.fir b/el2_ifu_bp_ctl.fir
index 6db16fc9..3708213e 100644
--- a/el2_ifu_bp_ctl.fir
+++ b/el2_ifu_bp_ctl.fir
@@ -90,14 +90,14 @@ circuit el2_ifu_bp_ctl :
     node _T_38 = and(_T_37, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 122:87]
     node _T_39 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 122:123]
     node fetch_mp_collision_p1_f = and(_T_38, _T_39) @[el2_ifu_bp_ctl.scala 122:108]
-    reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 124:30]
-    leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 124:30]
-    reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 125:33]
-    dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 125:33]
-    reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 126:29]
-    exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 126:29]
-    reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 127:35]
-    exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 127:35]
+    reg leak_one_f_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 124:56]
+    leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 124:56]
+    reg dec_tlu_way_wb_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 125:59]
+    dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 125:59]
+    reg exu_mp_way_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 126:55]
+    exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 126:55]
+    reg exu_flush_final_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 127:61]
+    exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 127:61]
     node _T_40 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 130:47]
     node _T_41 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 130:93]
     node _T_42 = or(_T_40, _T_41) @[el2_ifu_bp_ctl.scala 130:76]
diff --git a/el2_ifu_bp_ctl.v b/el2_ifu_bp_ctl.v
index 5a81bb3a..e9ed3c5e 100644
--- a/el2_ifu_bp_ctl.v
+++ b/el2_ifu_bp_ctl.v
@@ -1089,7 +1089,7 @@ module el2_ifu_bp_ctl(
   reg [31:0] _RAND_1038;
 `endif // RANDOMIZE_REG_INIT
   wire  _T_40 = io_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 130:47]
-  reg  leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 124:30]
+  reg  leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 124:56]
   wire  _T_41 = leak_one_f_d1 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 130:93]
   wire  leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 130:76]
   wire  _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 69:46]
@@ -2129,7 +2129,7 @@ module el2_ifu_bp_ctl(
   wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[el2_lib.scala 177:111]
   wire  _T_45 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 133:97]
   wire  _T_46 = btb_bank0_rd_data_way0_f[0] & _T_45; // @[el2_ifu_bp_ctl.scala 133:55]
-  reg  dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 125:33]
+  reg  dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 125:59]
   wire [6:0] btb_error_addr_wb = io_exu_i0_br_index_r[6:0]; // @[el2_ifu_bp_ctl.scala 92:21]
   wire [7:0] _GEN_1034 = {{1'd0}, btb_error_addr_wb}; // @[el2_ifu_bp_ctl.scala 111:72]
   wire  _T_19 = _GEN_1034 == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 111:72]
@@ -6839,8 +6839,8 @@ module el2_ifu_bp_ctl(
   wire  _T_38 = _T_37 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 122:87]
   wire  _T_39 = io_exu_mp_index == btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 122:123]
   wire  fetch_mp_collision_p1_f = _T_38 & _T_39; // @[el2_ifu_bp_ctl.scala 122:108]
-  reg  exu_mp_way_f; // @[el2_ifu_bp_ctl.scala 126:29]
-  reg  exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 127:35]
+  reg  exu_mp_way_f; // @[el2_ifu_bp_ctl.scala 126:55]
+  reg  exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 127:61]
   wire [255:0] mp_wrindex_dec = 256'h1 << io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 180:28]
   wire [255:0] fetch_wrindex_dec = 256'h1 << btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 182:31]
   wire [255:0] fetch_wrindex_p1_dec = 256'h1 << btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 184:34]
@@ -15918,7 +15918,7 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       leak_one_f_d1 <= 1'h0;
     end else begin
@@ -17717,7 +17717,7 @@ end // initial
       btb_bank0_rd_data_way0_out_255 <= btb_wr_data;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       dec_tlu_way_wb_f <= 1'h0;
     end else begin
@@ -25155,14 +25155,14 @@ end // initial
       end
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       exu_mp_way_f <= 1'h0;
     end else begin
       exu_mp_way_f <= io_exu_mp_pkt_way;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_active_clk or posedge reset) begin
     if (reset) begin
       exu_flush_final_d1 <= 1'h0;
     end else begin
diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
index 8671b4ac..7366203a 100644
--- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
@@ -121,10 +121,10 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
   val fetch_mp_collision_f = (io.exu_mp_btag === fetch_rd_tag_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_f)
   val fetch_mp_collision_p1_f = (io.exu_mp_btag === fetch_rd_tag_p1_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_p1_f)
 
-  val leak_one_f_d1 = RegNext(leak_one_f, init = 0.U)
-  val dec_tlu_way_wb_f = RegNext(dec_tlu_way_wb, init = 0.U)
-  val exu_mp_way_f = RegNext(exu_mp_way, init = 0.U)
-  val exu_flush_final_d1 = RegNext(io.exu_flush_final, init = 0.U)
+  val leak_one_f_d1 = withClock(io.active_clk) {RegNext(leak_one_f, init = 0.U)}
+  val dec_tlu_way_wb_f = withClock(io.active_clk) {RegNext(dec_tlu_way_wb, init = 0.U)}
+  val exu_mp_way_f = withClock(io.active_clk) {RegNext(exu_mp_way, init = 0.U)}
+  val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)}
 
   // TODO
   leak_one_f := (io.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & io.dec_tlu_flush_lower_wb)
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
index 297db66f..092b646c 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class differ