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ahb to axi update

This commit is contained in:
​Laraib Khan 2020-12-02 15:07:54 +05:00
parent cf771bdcf4
commit 76f0c4f9a9
6 changed files with 107 additions and 107 deletions
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128
ahb_to_axi4.fir
View File

@ -258,8 +258,8 @@ circuit ahb_to_axi4 :
buf_state_en <= _T_21 @[ahb_to_axi4.scala 132:22] buf_state_en <= _T_21 @[ahb_to_axi4.scala 132:22]
node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 133:25] node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 133:25]
node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 133:72] node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 133:72]
node _T_24 = eq(_T_23, UInt<1>("h01")) @[ahb_to_axi4.scala 133:79] node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 133:79]
node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 133:92] node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 133:97]
node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 133:55] node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 133:55]
node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 133:40] node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 133:40]
node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 133:38] node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 133:38]
@ -455,88 +455,88 @@ circuit ahb_to_axi4 :
node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 189:50] node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 189:50]
node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 189:48] node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 189:48]
cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 189:33] cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 189:33]
node _T_155 = and(UInt<1>("h01"), cmdbuf_rst) @[ahb_to_axi4.scala 193:26] node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 191:88]
node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 193:87] node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 191:68]
reg _T_157 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 191:112]
when _T_156 : @[Reg.scala 28:19] node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 191:110]
_T_157 <= _T_155 @[Reg.scala 28:23] reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 191:63]
skip @[Reg.scala 28:19] _T_159 <= _T_158 @[ahb_to_axi4.scala 191:63]
cmdbuf_vld <= _T_157 @[ahb_to_axi4.scala 192:33] cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 191:33]
node _T_158 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 197:57] node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:57]
reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_158 : @[Reg.scala 28:19]
_T_159 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_write <= _T_159 @[ahb_to_axi4.scala 196:33]
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 200:56]
reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_160 : @[Reg.scala 28:19] when _T_160 : @[Reg.scala 28:19]
_T_161 <= ahb_hsize_q @[Reg.scala 28:23] _T_161 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_size <= _T_161 @[ahb_to_axi4.scala 199:33] cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 194:33]
node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 203:57] node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 198:56]
reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_162 : @[Reg.scala 28:19] when _T_162 : @[Reg.scala 28:19]
_T_163 <= master_wstrb @[Reg.scala 28:23] _T_163 <= ahb_hsize_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_163 @[ahb_to_axi4.scala 202:33] cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 197:33]
node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 206:59] node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 201:57]
reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 200:33]
node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 204:59]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18] rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_164 @[el2_lib.scala 511:17] rvclkhdr_3.io.en <= _T_166 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_165 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_165 <= ahb_haddr_q @[el2_lib.scala 514:16] _T_167 <= ahb_haddr_q @[el2_lib.scala 514:16]
cmdbuf_addr <= _T_165 @[ahb_to_axi4.scala 206:17] cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 204:17]
node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 207:62] node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 205:62]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= bus_clk @[el2_lib.scala 510:18] rvclkhdr_4.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_4.io.en <= _T_166 @[el2_lib.scala 511:17] rvclkhdr_4.io.en <= _T_168 @[el2_lib.scala 511:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_167 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_167 <= io.ahb_hwdata @[el2_lib.scala 514:16] _T_169 <= io.ahb_hwdata @[el2_lib.scala 514:16]
cmdbuf_wdata <= _T_167 @[ahb_to_axi4.scala 207:18] cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 205:18]
node _T_168 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 210:43] node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 208:43]
io.axi_awvalid <= _T_168 @[ahb_to_axi4.scala 210:29] io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 208:29]
io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 211:29] io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 209:29]
io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 212:29] io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 210:29]
node _T_169 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 213:55] node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 211:55]
node _T_170 = cat(UInt<1>("h00"), _T_169) @[Cat.scala 29:58] node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58]
io.axi_awsize <= _T_170 @[ahb_to_axi4.scala 213:29] io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 211:29]
node _T_171 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_awprot <= _T_171 @[ahb_to_axi4.scala 214:29] io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 212:29]
node _T_172 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_awlen <= _T_172 @[ahb_to_axi4.scala 215:29] io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 213:29]
io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 216:29] io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 214:29]
node _T_173 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 218:43] node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 216:43]
io.axi_wvalid <= _T_173 @[ahb_to_axi4.scala 218:29] io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 216:29]
io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 219:29] io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 217:29]
io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 220:29] io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 218:29]
io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 221:29] io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 219:29]
io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 223:29] io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 221:29]
node _T_174 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 225:45] node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 223:45]
node _T_175 = and(cmdbuf_vld, _T_174) @[ahb_to_axi4.scala 225:43] node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 223:43]
io.axi_arvalid <= _T_175 @[ahb_to_axi4.scala 225:29] io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 223:29]
io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 226:29] io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 224:29]
io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 227:29] io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 225:29]
node _T_176 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 228:55] node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 226:55]
node _T_177 = cat(UInt<1>("h00"), _T_176) @[Cat.scala 29:58] node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58]
io.axi_arsize <= _T_177 @[ahb_to_axi4.scala 228:29] io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 226:29]
node _T_178 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_arprot <= _T_178 @[ahb_to_axi4.scala 229:29] io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 227:29]
node _T_179 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_arlen <= _T_179 @[ahb_to_axi4.scala 230:29] io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 228:29]
io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 231:29] io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 229:29]
io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 233:29] io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 231:29]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_5.clock <= clock rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_5.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_5.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 236:29] bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 234:29]

80
ahb_to_axi4.v
View File

@ -120,8 +120,8 @@ module ahb_to_axi4(
wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 131:43] wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 131:43]
wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 131:80] wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 131:80]
wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 131:78] wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 131:78]
wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 236:29] wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 234:29]
reg cmdbuf_vld; // @[Reg.scala 27:20] reg cmdbuf_vld; // @[ahb_to_axi4.scala 191:63]
wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 189:68] wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 189:68]
wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 189:104] wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 189:104]
wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 189:86] wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 189:86]
@ -130,7 +130,7 @@ module ahb_to_axi4(
wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 132:26] wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 132:26]
wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 132:39] wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 132:39]
wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 133:79] wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 133:79]
wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 133:92] wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 133:97]
wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 133:55] wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 133:55]
wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 133:40] wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 133:40]
wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 133:38] wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 133:38]
@ -163,21 +163,21 @@ module ahb_to_axi4(
wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 150:62] wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 150:62]
wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80] wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80]
wire [8:0] _GEN_24 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 150:72] wire [8:0] _GEN_23 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 150:72]
wire [8:0] _T_57 = _GEN_24 & _T_56; // @[ahb_to_axi4.scala 150:72] wire [8:0] _T_57 = _GEN_23 & _T_56; // @[ahb_to_axi4.scala 150:72]
wire [8:0] _GEN_25 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 149:111] wire [8:0] _GEN_24 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 149:111]
wire [8:0] _T_58 = _GEN_25 | _T_57; // @[ahb_to_axi4.scala 149:111] wire [8:0] _T_58 = _GEN_24 | _T_57; // @[ahb_to_axi4.scala 149:111]
wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 151:62] wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 151:62]
wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 151:80] wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 151:80]
wire [10:0] _GEN_26 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 151:72] wire [10:0] _GEN_25 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 151:72]
wire [10:0] _T_65 = _GEN_26 & _T_64; // @[ahb_to_axi4.scala 151:72] wire [10:0] _T_65 = _GEN_25 & _T_64; // @[ahb_to_axi4.scala 151:72]
wire [10:0] _GEN_27 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 150:111] wire [10:0] _GEN_26 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 150:111]
wire [10:0] _T_66 = _GEN_27 | _T_65; // @[ahb_to_axi4.scala 150:111] wire [10:0] _T_66 = _GEN_26 | _T_65; // @[ahb_to_axi4.scala 150:111]
wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 152:62] wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 152:62]
wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_28 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 151:111] wire [10:0] _GEN_27 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 151:111]
wire [10:0] _T_72 = _T_66 | _GEN_28; // @[ahb_to_axi4.scala 151:111] wire [10:0] _T_72 = _T_66 | _GEN_27; // @[ahb_to_axi4.scala 151:111]
reg ahb_hready_q; // @[ahb_to_axi4.scala 174:62] reg ahb_hready_q; // @[ahb_to_axi4.scala 174:62]
wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 155:68] wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 155:68]
reg ahb_hresp_q; // @[ahb_to_axi4.scala 173:62] reg ahb_hresp_q; // @[ahb_to_axi4.scala 173:62]
@ -222,12 +222,14 @@ module ahb_to_axi4(
wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 188:109] wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 188:109]
wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 188:142] wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 188:142]
wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 188:126] wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 188:126]
reg [2:0] _T_161; // @[Reg.scala 27:20] wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 191:68]
wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 191:112]
reg [2:0] _T_163; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 149:33] wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 149:33]
reg [31:0] cmdbuf_addr; // @[el2_lib.scala 514:16] reg [31:0] cmdbuf_addr; // @[el2_lib.scala 514:16]
reg [63:0] cmdbuf_wdata; // @[el2_lib.scala 514:16] reg [63:0] cmdbuf_wdata; // @[el2_lib.scala 514:16]
wire [1:0] cmdbuf_size = _T_161[1:0]; // @[ahb_to_axi4.scala 199:33] wire [1:0] cmdbuf_size = _T_163[1:0]; // @[ahb_to_axi4.scala 197:33]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -264,24 +266,24 @@ module ahb_to_axi4(
.io_en(rvclkhdr_5_io_en), .io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode) .io_scan_mode(rvclkhdr_5_io_scan_mode)
); );
assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 210:29] assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 208:29]
assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 212:29] assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 210:29]
assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 213:29] assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 211:29]
assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 214:29] assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 212:29]
assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 215:29] assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 213:29]
assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 216:29] assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 214:29]
assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 218:29] assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 216:29]
assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 219:29] assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 217:29]
assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 220:29] assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 218:29]
assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 221:29] assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 219:29]
assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 223:29] assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 221:29]
assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 225:29] assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 223:29]
assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 227:29] assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 225:29]
assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 228:29] assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 226:29]
assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 229:29] assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 227:29]
assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 230:29] assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 228:29]
assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 231:29] assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 229:29]
assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 233:29] assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 231:29]
assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 158:33] assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 158:33]
assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 155:33] assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 155:33]
assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 159:33] assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 159:33]
@ -361,7 +363,7 @@ initial begin
_RAND_10 = {1{`RANDOM}}; _RAND_10 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_10[0:0]; ahb_hwrite_q = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}}; _RAND_11 = {1{`RANDOM}};
_T_161 = _RAND_11[2:0]; _T_163 = _RAND_11[2:0];
_RAND_12 = {1{`RANDOM}}; _RAND_12 = {1{`RANDOM}};
cmdbuf_wstrb = _RAND_12[7:0]; cmdbuf_wstrb = _RAND_12[7:0];
_RAND_13 = {1{`RANDOM}}; _RAND_13 = {1{`RANDOM}};
@ -403,7 +405,7 @@ initial begin
ahb_hwrite_q = 1'h0; ahb_hwrite_q = 1'h0;
end end
if (reset) begin if (reset) begin
_T_161 = 3'h0; _T_163 = 3'h0;
end end
if (reset) begin if (reset) begin
cmdbuf_wstrb = 8'h0; cmdbuf_wstrb = 8'h0;
@ -459,8 +461,8 @@ end // initial
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
cmdbuf_vld <= 1'h0; cmdbuf_vld <= 1'h0;
end else if (cmdbuf_wr_en) begin end else begin
cmdbuf_vld <= cmdbuf_rst; cmdbuf_vld <= _T_156 & _T_157;
end end
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
@ -527,9 +529,9 @@ end // initial
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_161 <= 3'h0; _T_163 <= 3'h0;
end else if (cmdbuf_wr_en) begin end else if (cmdbuf_wr_en) begin
_T_161 <= ahb_hsize_q; _T_163 <= ahb_hsize_q;
end end
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin

6
src/main/scala/lib/ahb_to_axi4.scala
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@ -130,7 +130,7 @@ class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
is(wr) { // Write command recieved last cycle is(wr) { // Write command recieved last cycle
buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd)) buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd))
buf_state_en := (!cmdbuf_full | io.ahb_hresp) buf_state_en := (!cmdbuf_full | io.ahb_hresp)
cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now. cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
} }
is(rd) { // Read command recieved last cycle. is(rd) { // Read command recieved last cycle.
buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data
@ -187,10 +187,8 @@ class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write) cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write)
cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready))) cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
//rvdffsc //rvdffsc
cmdbuf_vld := withClock(bus_clk) { cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
RegEnable("b1".U & Fill("b1".U.getWidth, cmdbuf_rst), 0.U, cmdbuf_wr_en.asBool())}
//dffs //dffs
cmdbuf_write := withClock(bus_clk) { cmdbuf_write := withClock(bus_clk) {

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target/scala-2.12/classes/lib/AHB_main$.class
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target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class
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target/scala-2.12/classes/lib/ahb_to_axi4.class
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