IMC DONE
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@ -34,19 +34,6 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_test",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_en",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wr_valid",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall",
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@ -141,14 +128,6 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_tagv_mb_in",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_valid",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
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4854
el2_ifu_mem_ctl.fir
4854
el2_ifu_mem_ctl.fir
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Load Diff
3570
el2_ifu_mem_ctl.v
3570
el2_ifu_mem_ctl.v
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Load Diff
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@ -126,11 +126,11 @@ class mem_ctl_bundle extends Bundle with el2_lib{
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val scan_mode = Input(Bool())
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val valids = Output(UInt())
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val tagv_mb_in = Output(UInt())
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val test = Output(UInt())
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val test_way_status_out = Output(UInt())
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val test_way_status_clken = Output(UInt())
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// val valids = Output(UInt())
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// val tagv_mb_in = Output(UInt())
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// val test = Output(UInt())
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// val test_way_status_out = Output(UInt())
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// val test_way_status_clken = Output(UInt())
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}
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class el2_ifu_mem_ctl extends Module with el2_lib {
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val io = IO(new mem_ctl_bundle)
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@ -717,7 +717,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
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if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
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io.test := way_status_new_w_debug
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// io.test := way_status_new_w_debug
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val way_status_new_ff = withClock(io.free_clk) {
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RegNext(way_status_new_w_debug, 0.U)
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}
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@ -727,9 +727,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
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way_status_out((8 * i) + j) := RegEnable(way_status_new_ff, 0.U, ((ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff) & way_status_clken(i))
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val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
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io.test_way_status_out := test_way_status_out
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// io.test_way_status_out := test_way_status_out
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val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
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io.test_way_status_clken := test_way_status_clken
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//io.test_way_status_clken := test_way_status_clken
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way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
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val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
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io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
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@ -753,8 +753,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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reset_all_tags).reverse.reduce(Cat(_, _)))
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// val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
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val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
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io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
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(0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
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// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
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// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
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for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
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ic_tag_valid_out(j)((32 * i) + k) := RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
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@ -851,7 +851,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
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io.tagv_mb_in := tagv_mb_in
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// io.tagv_mb_in := tagv_mb_in
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}
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object ifu_mem extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
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