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Extra modules deleted

This commit is contained in:
​Laraib Khan 2021-01-08 09:21:34 +05:00
parent 1c84acbbfc
commit 7881351a25
46 changed files with 0 additions and 59807 deletions
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30
el2_exu_div_existing_1bit_cheapshortq.anno.json
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@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_existing_1bit_cheapshortq|el2_exu_div_existing_1bit_cheapshortq>io_valid_out",
"sources":[
"~el2_exu_div_existing_1bit_cheapshortq|el2_exu_div_existing_1bit_cheapshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_div_existing_1bit_cheapshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_existing_1bit_cheapshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2244
el2_exu_div_existing_1bit_cheapshortq.fir
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File diff suppressed because it is too large Load Diff

938
el2_exu_div_existing_1bit_cheapshortq.v
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@ -1,938 +0,0 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module el2_exu_div_existing_1bit_cheapshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
wire rvclkhdr_11_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_11_io_en; // @[lib.scala 390:23]
wire rvclkhdr_12_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_12_io_en; // @[lib.scala 390:23]
wire rvclkhdr_13_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_13_io_en; // @[lib.scala 390:23]
wire rvclkhdr_14_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_14_io_en; // @[lib.scala 390:23]
wire _T = ~io_cancel; // @[exu_div_ctl.scala 127:30]
reg valid_ff_x; // @[Reg.scala 27:20]
wire valid_x = valid_ff_x & _T; // @[exu_div_ctl.scala 127:28]
reg [32:0] q_ff; // @[Reg.scala 27:20]
wire _T_2 = q_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:34]
reg [32:0] m_ff; // @[Reg.scala 27:20]
wire _T_4 = m_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:57]
wire _T_5 = _T_2 & _T_4; // @[exu_div_ctl.scala 133:43]
wire _T_7 = m_ff[31:0] != 32'h0; // @[exu_div_ctl.scala 133:80]
wire _T_8 = _T_5 & _T_7; // @[exu_div_ctl.scala 133:66]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 133:91]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 133:89]
wire _T_11 = _T_10 & valid_x; // @[exu_div_ctl.scala 133:99]
wire _T_13 = q_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 134:18]
wire _T_16 = _T_13 & _T_7; // @[exu_div_ctl.scala 134:27]
wire _T_18 = _T_16 & _T_9; // @[exu_div_ctl.scala 134:50]
wire _T_19 = _T_18 & valid_x; // @[exu_div_ctl.scala 134:60]
wire smallnum_case = _T_11 | _T_19; // @[exu_div_ctl.scala 133:110]
wire _T_23 = ~m_ff[3]; // @[exu_div_ctl.scala 138:69]
wire _T_25 = ~m_ff[2]; // @[exu_div_ctl.scala 138:69]
wire _T_27 = ~m_ff[1]; // @[exu_div_ctl.scala 138:69]
wire _T_28 = _T_23 & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_29 = _T_28 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_30 = q_ff[3] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_37 = q_ff[3] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_39 = ~m_ff[0]; // @[exu_div_ctl.scala 145:32]
wire _T_40 = _T_37 & _T_39; // @[exu_div_ctl.scala 145:30]
wire _T_50 = q_ff[2] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_51 = _T_40 | _T_50; // @[exu_div_ctl.scala 145:41]
wire _T_54 = q_ff[3] & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_60 = _T_54 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_61 = _T_51 | _T_60; // @[exu_div_ctl.scala 145:73]
wire _T_68 = q_ff[2] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_71 = _T_68 & _T_39; // @[exu_div_ctl.scala 147:30]
wire _T_81 = q_ff[1] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_82 = _T_71 | _T_81; // @[exu_div_ctl.scala 147:41]
wire _T_88 = _T_23 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_89 = q_ff[3] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_92 = _T_89 & _T_39; // @[exu_div_ctl.scala 147:103]
wire _T_93 = _T_82 | _T_92; // @[exu_div_ctl.scala 147:76]
wire _T_96 = ~q_ff[2]; // @[exu_div_ctl.scala 137:69]
wire _T_97 = q_ff[3] & _T_96; // @[exu_div_ctl.scala 137:94]
wire _T_105 = _T_28 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_106 = _T_105 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_107 = _T_97 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_108 = _T_93 | _T_107; // @[exu_div_ctl.scala 147:114]
wire _T_110 = ~q_ff[3]; // @[exu_div_ctl.scala 137:69]
wire _T_113 = _T_110 & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_114 = _T_113 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_120 = _T_114 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_121 = _T_108 | _T_120; // @[exu_div_ctl.scala 148:43]
wire _T_127 = _T_54 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_130 = _T_127 & _T_39; // @[exu_div_ctl.scala 148:104]
wire _T_131 = _T_121 | _T_130; // @[exu_div_ctl.scala 148:78]
wire _T_140 = _T_23 & m_ff[2]; // @[exu_div_ctl.scala 138:94]
wire _T_141 = _T_140 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_142 = _T_54 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_143 = _T_131 | _T_142; // @[exu_div_ctl.scala 148:116]
wire _T_146 = q_ff[3] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_152 = _T_146 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_153 = _T_143 | _T_152; // @[exu_div_ctl.scala 149:43]
wire _T_158 = _T_54 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_163 = _T_158 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_164 = _T_153 | _T_163; // @[exu_div_ctl.scala 149:77]
wire _T_168 = q_ff[2] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_169 = _T_168 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_175 = _T_169 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_181 = _T_97 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_186 = _T_23 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_187 = _T_186 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_188 = _T_181 & _T_187; // @[exu_div_ctl.scala 139:10]
wire _T_189 = _T_175 | _T_188; // @[exu_div_ctl.scala 151:44]
wire _T_196 = q_ff[2] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_199 = _T_196 & _T_39; // @[exu_div_ctl.scala 151:111]
wire _T_200 = _T_189 | _T_199; // @[exu_div_ctl.scala 151:84]
wire _T_207 = q_ff[1] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_210 = _T_207 & _T_39; // @[exu_div_ctl.scala 152:32]
wire _T_211 = _T_200 | _T_210; // @[exu_div_ctl.scala 151:126]
wire _T_221 = q_ff[0] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_222 = _T_211 | _T_221; // @[exu_div_ctl.scala 152:46]
wire _T_227 = ~q_ff[1]; // @[exu_div_ctl.scala 137:69]
wire _T_229 = _T_113 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_239 = _T_229 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_240 = _T_222 | _T_239; // @[exu_div_ctl.scala 152:86]
wire _T_249 = _T_114 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_252 = _T_249 & _T_39; // @[exu_div_ctl.scala 153:35]
wire _T_253 = _T_240 | _T_252; // @[exu_div_ctl.scala 152:128]
wire _T_259 = _T_25 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_260 = q_ff[3] & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_263 = _T_260 & _T_39; // @[exu_div_ctl.scala 153:74]
wire _T_264 = _T_253 | _T_263; // @[exu_div_ctl.scala 153:46]
wire _T_274 = _T_140 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_275 = _T_97 & _T_274; // @[exu_div_ctl.scala 139:10]
wire _T_276 = _T_264 | _T_275; // @[exu_div_ctl.scala 153:86]
wire _T_290 = _T_114 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_291 = _T_276 | _T_290; // @[exu_div_ctl.scala 153:128]
wire _T_297 = _T_113 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_303 = _T_297 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_304 = _T_291 | _T_303; // @[exu_div_ctl.scala 154:46]
wire _T_311 = _T_97 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_317 = _T_140 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_318 = _T_311 & _T_317; // @[exu_div_ctl.scala 139:10]
wire _T_319 = _T_304 | _T_318; // @[exu_div_ctl.scala 154:86]
wire _T_324 = _T_96 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_325 = _T_324 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_331 = _T_325 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_332 = _T_319 | _T_331; // @[exu_div_ctl.scala 154:128]
wire _T_338 = _T_54 & _T_27; // @[exu_div_ctl.scala 139:10]
wire _T_341 = _T_338 & _T_39; // @[exu_div_ctl.scala 155:73]
wire _T_342 = _T_332 | _T_341; // @[exu_div_ctl.scala 155:46]
wire _T_350 = _T_114 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_355 = _T_350 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_356 = _T_342 | _T_355; // @[exu_div_ctl.scala 155:86]
wire _T_363 = m_ff[3] & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_364 = _T_54 & _T_363; // @[exu_div_ctl.scala 139:10]
wire _T_365 = _T_356 | _T_364; // @[exu_div_ctl.scala 155:128]
wire _T_375 = _T_363 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_376 = _T_146 & _T_375; // @[exu_div_ctl.scala 139:10]
wire _T_377 = _T_365 | _T_376; // @[exu_div_ctl.scala 156:46]
wire _T_380 = q_ff[3] & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_386 = _T_380 & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_387 = _T_377 | _T_386; // @[exu_div_ctl.scala 156:86]
wire _T_391 = q_ff[3] & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_399 = _T_274 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_400 = _T_391 & _T_399; // @[exu_div_ctl.scala 139:10]
wire _T_401 = _T_387 | _T_400; // @[exu_div_ctl.scala 156:128]
wire _T_408 = _T_158 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_411 = _T_408 & _T_39; // @[exu_div_ctl.scala 157:75]
wire _T_412 = _T_401 | _T_411; // @[exu_div_ctl.scala 157:46]
wire _T_421 = m_ff[3] & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_422 = _T_158 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_423 = _T_412 | _T_422; // @[exu_div_ctl.scala 157:86]
wire _T_428 = _T_54 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_433 = _T_428 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_434 = _T_423 | _T_433; // @[exu_div_ctl.scala 157:128]
wire _T_440 = _T_97 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_445 = _T_440 & _T_186; // @[exu_div_ctl.scala 139:10]
wire _T_446 = _T_434 | _T_445; // @[exu_div_ctl.scala 158:46]
wire _T_451 = _T_146 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_454 = _T_451 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_455 = _T_446 | _T_454; // @[exu_div_ctl.scala 158:86]
wire _T_462 = _T_158 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_464 = _T_462 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_465 = _T_455 | _T_464; // @[exu_div_ctl.scala 158:128]
wire _T_471 = _T_146 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_474 = _T_471 & _T_39; // @[exu_div_ctl.scala 159:72]
wire _T_475 = _T_465 | _T_474; // @[exu_div_ctl.scala 159:46]
wire [3:0] smallnum = {_T_30,_T_61,_T_164,_T_475}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_479 = sign_ff & q_ff[31]; // @[exu_div_ctl.scala 168:34]
wire [32:0] short_dividend = {_T_479,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_484 = ~short_dividend[32]; // @[exu_div_ctl.scala 173:7]
wire _T_487 = short_dividend[31:24] != 8'h0; // @[exu_div_ctl.scala 173:60]
wire _T_492 = short_dividend[31:23] != 9'h1ff; // @[exu_div_ctl.scala 174:59]
wire _T_493 = _T_484 & _T_487; // @[Mux.scala 27:72]
wire _T_494 = short_dividend[32] & _T_492; // @[Mux.scala 27:72]
wire _T_495 = _T_493 | _T_494; // @[Mux.scala 27:72]
wire _T_502 = short_dividend[23:16] != 8'h0; // @[exu_div_ctl.scala 177:60]
wire _T_507 = short_dividend[22:15] != 8'hff; // @[exu_div_ctl.scala 178:59]
wire _T_508 = _T_484 & _T_502; // @[Mux.scala 27:72]
wire _T_509 = short_dividend[32] & _T_507; // @[Mux.scala 27:72]
wire _T_510 = _T_508 | _T_509; // @[Mux.scala 27:72]
wire _T_517 = short_dividend[15:8] != 8'h0; // @[exu_div_ctl.scala 181:59]
wire _T_522 = short_dividend[14:7] != 8'hff; // @[exu_div_ctl.scala 182:58]
wire _T_523 = _T_484 & _T_517; // @[Mux.scala 27:72]
wire _T_524 = short_dividend[32] & _T_522; // @[Mux.scala 27:72]
wire _T_525 = _T_523 | _T_524; // @[Mux.scala 27:72]
wire [4:0] a_cls = {2'h0,_T_495,_T_510,_T_525}; // @[Cat.scala 29:58]
wire _T_531 = ~m_ff[32]; // @[exu_div_ctl.scala 187:7]
wire _T_534 = m_ff[31:24] != 8'h0; // @[exu_div_ctl.scala 187:40]
wire _T_539 = m_ff[31:24] != 8'hff; // @[exu_div_ctl.scala 188:39]
wire _T_540 = _T_531 & _T_534; // @[Mux.scala 27:72]
wire _T_541 = m_ff[32] & _T_539; // @[Mux.scala 27:72]
wire _T_542 = _T_540 | _T_541; // @[Mux.scala 27:72]
wire _T_549 = m_ff[23:16] != 8'h0; // @[exu_div_ctl.scala 191:40]
wire _T_554 = m_ff[23:16] != 8'hff; // @[exu_div_ctl.scala 192:39]
wire _T_555 = _T_531 & _T_549; // @[Mux.scala 27:72]
wire _T_556 = m_ff[32] & _T_554; // @[Mux.scala 27:72]
wire _T_557 = _T_555 | _T_556; // @[Mux.scala 27:72]
wire _T_564 = m_ff[15:8] != 8'h0; // @[exu_div_ctl.scala 195:39]
wire _T_569 = m_ff[15:8] != 8'hff; // @[exu_div_ctl.scala 196:38]
wire _T_570 = _T_531 & _T_564; // @[Mux.scala 27:72]
wire _T_571 = m_ff[32] & _T_569; // @[Mux.scala 27:72]
wire _T_572 = _T_570 | _T_571; // @[Mux.scala 27:72]
wire [4:0] b_cls = {2'h0,_T_542,_T_557,_T_572}; // @[Cat.scala 29:58]
wire _T_577 = a_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 200:19]
wire _T_580 = _T_577 & b_cls[2]; // @[exu_div_ctl.scala 200:34]
wire _T_582 = a_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 201:21]
wire _T_585 = _T_582 & b_cls[2]; // @[exu_div_ctl.scala 201:36]
wire _T_586 = _T_580 | _T_585; // @[exu_div_ctl.scala 200:65]
wire _T_588 = a_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 202:21]
wire _T_591 = _T_588 & b_cls[2]; // @[exu_div_ctl.scala 202:36]
wire _T_592 = _T_586 | _T_591; // @[exu_div_ctl.scala 201:67]
wire _T_596 = b_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 203:50]
wire _T_597 = _T_582 & _T_596; // @[exu_div_ctl.scala 203:36]
wire _T_598 = _T_592 | _T_597; // @[exu_div_ctl.scala 202:67]
wire _T_603 = _T_588 & _T_596; // @[exu_div_ctl.scala 204:36]
wire _T_604 = _T_598 | _T_603; // @[exu_div_ctl.scala 203:67]
wire _T_608 = b_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 205:50]
wire _T_609 = _T_588 & _T_608; // @[exu_div_ctl.scala 205:36]
wire _T_610 = _T_604 | _T_609; // @[exu_div_ctl.scala 204:67]
wire _T_615 = a_cls[2] & b_cls[2]; // @[exu_div_ctl.scala 207:34]
wire _T_620 = _T_577 & _T_596; // @[exu_div_ctl.scala 208:36]
wire _T_621 = _T_615 | _T_620; // @[exu_div_ctl.scala 207:65]
wire _T_626 = _T_582 & _T_608; // @[exu_div_ctl.scala 209:36]
wire _T_627 = _T_621 | _T_626; // @[exu_div_ctl.scala 208:67]
wire _T_631 = b_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 210:50]
wire _T_632 = _T_588 & _T_631; // @[exu_div_ctl.scala 210:36]
wire _T_633 = _T_627 | _T_632; // @[exu_div_ctl.scala 209:67]
wire _T_638 = a_cls[2] & _T_596; // @[exu_div_ctl.scala 212:34]
wire _T_643 = _T_577 & _T_608; // @[exu_div_ctl.scala 213:36]
wire _T_644 = _T_638 | _T_643; // @[exu_div_ctl.scala 212:65]
wire _T_649 = _T_582 & _T_631; // @[exu_div_ctl.scala 214:36]
wire _T_650 = _T_644 | _T_649; // @[exu_div_ctl.scala 213:67]
wire _T_655 = a_cls[2] & _T_608; // @[exu_div_ctl.scala 216:34]
wire _T_660 = _T_577 & _T_631; // @[exu_div_ctl.scala 217:36]
wire _T_661 = _T_655 | _T_660; // @[exu_div_ctl.scala 216:65]
wire [3:0] shortq_raw = {_T_610,_T_633,_T_650,_T_661}; // @[Cat.scala 29:58]
wire _T_666 = valid_ff_x & _T_7; // @[exu_div_ctl.scala 220:35]
wire _T_667 = shortq_raw != 4'h0; // @[exu_div_ctl.scala 220:78]
wire shortq_enable = _T_666 & _T_667; // @[exu_div_ctl.scala 220:64]
wire [3:0] _T_669 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_670 = _T_669 & shortq_raw; // @[exu_div_ctl.scala 221:57]
wire [5:0] shortq_shift = {2'h0,_T_670}; // @[Cat.scala 29:58]
reg [5:0] _T_1520; // @[Reg.scala 27:20]
wire [3:0] shortq_shift_xx = _T_1520[3:0]; // @[exu_div_ctl.scala 277:21]
wire [4:0] _T_679 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_680 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_681 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_682 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_683 = _T_679 | _T_680; // @[Mux.scala 27:72]
wire [4:0] _T_684 = _T_683 | _T_681; // @[Mux.scala 27:72]
wire [4:0] _GEN_15 = {{1'd0}, _T_682}; // @[Mux.scala 27:72]
wire [4:0] _T_685 = _T_684 | _GEN_15; // @[Mux.scala 27:72]
wire [5:0] shortq_shift_ff = {1'h0,_T_685}; // @[Cat.scala 29:58]
reg [5:0] count; // @[Reg.scala 27:20]
wire _T_688 = count == 6'h20; // @[exu_div_ctl.scala 230:55]
wire _T_689 = count == 6'h21; // @[exu_div_ctl.scala 230:76]
wire _T_690 = _T_9 ? _T_688 : _T_689; // @[exu_div_ctl.scala 230:39]
wire finish = smallnum_case | _T_690; // @[exu_div_ctl.scala 230:34]
reg run_state; // @[Reg.scala 27:20]
wire _T_691 = io_valid_in | run_state; // @[exu_div_ctl.scala 231:32]
wire _T_692 = _T_691 | finish; // @[exu_div_ctl.scala 231:44]
reg finish_ff; // @[Reg.scala 27:20]
wire div_clken = _T_692 | finish_ff; // @[exu_div_ctl.scala 231:53]
wire _T_694 = ~finish; // @[exu_div_ctl.scala 232:48]
wire _T_695 = _T_691 & _T_694; // @[exu_div_ctl.scala 232:46]
wire run_in = _T_695 & _T; // @[exu_div_ctl.scala 232:56]
wire _T_698 = run_state & _T_694; // @[exu_div_ctl.scala 233:35]
wire _T_700 = _T_698 & _T; // @[exu_div_ctl.scala 233:45]
wire _T_701 = ~shortq_enable; // @[exu_div_ctl.scala 233:60]
wire _T_702 = _T_700 & _T_701; // @[exu_div_ctl.scala 233:58]
wire [5:0] _T_704 = _T_702 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_706 = {1'h0,shortq_shift_ff[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_708 = count + _T_706; // @[exu_div_ctl.scala 233:86]
wire [5:0] _T_710 = _T_708 + 6'h1; // @[exu_div_ctl.scala 233:118]
wire [5:0] count_in = _T_704 & _T_710; // @[exu_div_ctl.scala 233:77]
wire _T_714 = io_divisor_in != 32'h0; // @[exu_div_ctl.scala 235:50]
wire sign_eff = io_signed_in & _T_714; // @[exu_div_ctl.scala 235:33]
wire _T_715 = ~run_state; // @[exu_div_ctl.scala 238:6]
wire [32:0] _T_717 = {1'h0,io_dividend_in}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire _T_718 = valid_ff_x | shortq_enable_ff; // @[exu_div_ctl.scala 239:30]
wire _T_719 = run_state & _T_718; // @[exu_div_ctl.scala 239:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_743 = sign_ff & dividend_neg_ff; // @[exu_div_ctl.scala 243:32]
wire _T_928 = |q_ff[30:0]; // @[lib.scala 428:35]
wire _T_930 = ~q_ff[31]; // @[lib.scala 428:40]
wire _T_932 = _T_928 ? _T_930 : q_ff[31]; // @[lib.scala 428:23]
wire _T_922 = |q_ff[29:0]; // @[lib.scala 428:35]
wire _T_924 = ~q_ff[30]; // @[lib.scala 428:40]
wire _T_926 = _T_922 ? _T_924 : q_ff[30]; // @[lib.scala 428:23]
wire _T_916 = |q_ff[28:0]; // @[lib.scala 428:35]
wire _T_918 = ~q_ff[29]; // @[lib.scala 428:40]
wire _T_920 = _T_916 ? _T_918 : q_ff[29]; // @[lib.scala 428:23]
wire _T_910 = |q_ff[27:0]; // @[lib.scala 428:35]
wire _T_912 = ~q_ff[28]; // @[lib.scala 428:40]
wire _T_914 = _T_910 ? _T_912 : q_ff[28]; // @[lib.scala 428:23]
wire _T_904 = |q_ff[26:0]; // @[lib.scala 428:35]
wire _T_906 = ~q_ff[27]; // @[lib.scala 428:40]
wire _T_908 = _T_904 ? _T_906 : q_ff[27]; // @[lib.scala 428:23]
wire _T_898 = |q_ff[25:0]; // @[lib.scala 428:35]
wire _T_900 = ~q_ff[26]; // @[lib.scala 428:40]
wire _T_902 = _T_898 ? _T_900 : q_ff[26]; // @[lib.scala 428:23]
wire _T_892 = |q_ff[24:0]; // @[lib.scala 428:35]
wire _T_894 = ~q_ff[25]; // @[lib.scala 428:40]
wire _T_896 = _T_892 ? _T_894 : q_ff[25]; // @[lib.scala 428:23]
wire _T_886 = |q_ff[23:0]; // @[lib.scala 428:35]
wire _T_888 = ~q_ff[24]; // @[lib.scala 428:40]
wire _T_890 = _T_886 ? _T_888 : q_ff[24]; // @[lib.scala 428:23]
wire _T_880 = |q_ff[22:0]; // @[lib.scala 428:35]
wire _T_882 = ~q_ff[23]; // @[lib.scala 428:40]
wire _T_884 = _T_880 ? _T_882 : q_ff[23]; // @[lib.scala 428:23]
wire _T_874 = |q_ff[21:0]; // @[lib.scala 428:35]
wire _T_876 = ~q_ff[22]; // @[lib.scala 428:40]
wire _T_878 = _T_874 ? _T_876 : q_ff[22]; // @[lib.scala 428:23]
wire _T_868 = |q_ff[20:0]; // @[lib.scala 428:35]
wire _T_870 = ~q_ff[21]; // @[lib.scala 428:40]
wire _T_872 = _T_868 ? _T_870 : q_ff[21]; // @[lib.scala 428:23]
wire _T_862 = |q_ff[19:0]; // @[lib.scala 428:35]
wire _T_864 = ~q_ff[20]; // @[lib.scala 428:40]
wire _T_866 = _T_862 ? _T_864 : q_ff[20]; // @[lib.scala 428:23]
wire _T_856 = |q_ff[18:0]; // @[lib.scala 428:35]
wire _T_858 = ~q_ff[19]; // @[lib.scala 428:40]
wire _T_860 = _T_856 ? _T_858 : q_ff[19]; // @[lib.scala 428:23]
wire _T_850 = |q_ff[17:0]; // @[lib.scala 428:35]
wire _T_852 = ~q_ff[18]; // @[lib.scala 428:40]
wire _T_854 = _T_850 ? _T_852 : q_ff[18]; // @[lib.scala 428:23]
wire _T_844 = |q_ff[16:0]; // @[lib.scala 428:35]
wire _T_846 = ~q_ff[17]; // @[lib.scala 428:40]
wire _T_848 = _T_844 ? _T_846 : q_ff[17]; // @[lib.scala 428:23]
wire _T_838 = |q_ff[15:0]; // @[lib.scala 428:35]
wire _T_840 = ~q_ff[16]; // @[lib.scala 428:40]
wire _T_842 = _T_838 ? _T_840 : q_ff[16]; // @[lib.scala 428:23]
wire [7:0] _T_953 = {_T_884,_T_878,_T_872,_T_866,_T_860,_T_854,_T_848,_T_842}; // @[lib.scala 430:14]
wire _T_832 = |q_ff[14:0]; // @[lib.scala 428:35]
wire _T_834 = ~q_ff[15]; // @[lib.scala 428:40]
wire _T_836 = _T_832 ? _T_834 : q_ff[15]; // @[lib.scala 428:23]
wire _T_826 = |q_ff[13:0]; // @[lib.scala 428:35]
wire _T_828 = ~q_ff[14]; // @[lib.scala 428:40]
wire _T_830 = _T_826 ? _T_828 : q_ff[14]; // @[lib.scala 428:23]
wire _T_820 = |q_ff[12:0]; // @[lib.scala 428:35]
wire _T_822 = ~q_ff[13]; // @[lib.scala 428:40]
wire _T_824 = _T_820 ? _T_822 : q_ff[13]; // @[lib.scala 428:23]
wire _T_814 = |q_ff[11:0]; // @[lib.scala 428:35]
wire _T_816 = ~q_ff[12]; // @[lib.scala 428:40]
wire _T_818 = _T_814 ? _T_816 : q_ff[12]; // @[lib.scala 428:23]
wire _T_808 = |q_ff[10:0]; // @[lib.scala 428:35]
wire _T_810 = ~q_ff[11]; // @[lib.scala 428:40]
wire _T_812 = _T_808 ? _T_810 : q_ff[11]; // @[lib.scala 428:23]
wire _T_802 = |q_ff[9:0]; // @[lib.scala 428:35]
wire _T_804 = ~q_ff[10]; // @[lib.scala 428:40]
wire _T_806 = _T_802 ? _T_804 : q_ff[10]; // @[lib.scala 428:23]
wire _T_796 = |q_ff[8:0]; // @[lib.scala 428:35]
wire _T_798 = ~q_ff[9]; // @[lib.scala 428:40]
wire _T_800 = _T_796 ? _T_798 : q_ff[9]; // @[lib.scala 428:23]
wire _T_790 = |q_ff[7:0]; // @[lib.scala 428:35]
wire _T_792 = ~q_ff[8]; // @[lib.scala 428:40]
wire _T_794 = _T_790 ? _T_792 : q_ff[8]; // @[lib.scala 428:23]
wire _T_784 = |q_ff[6:0]; // @[lib.scala 428:35]
wire _T_786 = ~q_ff[7]; // @[lib.scala 428:40]
wire _T_788 = _T_784 ? _T_786 : q_ff[7]; // @[lib.scala 428:23]
wire _T_778 = |q_ff[5:0]; // @[lib.scala 428:35]
wire _T_780 = ~q_ff[6]; // @[lib.scala 428:40]
wire _T_782 = _T_778 ? _T_780 : q_ff[6]; // @[lib.scala 428:23]
wire _T_772 = |q_ff[4:0]; // @[lib.scala 428:35]
wire _T_774 = ~q_ff[5]; // @[lib.scala 428:40]
wire _T_776 = _T_772 ? _T_774 : q_ff[5]; // @[lib.scala 428:23]
wire _T_766 = |q_ff[3:0]; // @[lib.scala 428:35]
wire _T_768 = ~q_ff[4]; // @[lib.scala 428:40]
wire _T_770 = _T_766 ? _T_768 : q_ff[4]; // @[lib.scala 428:23]
wire _T_760 = |q_ff[2:0]; // @[lib.scala 428:35]
wire _T_762 = ~q_ff[3]; // @[lib.scala 428:40]
wire _T_764 = _T_760 ? _T_762 : q_ff[3]; // @[lib.scala 428:23]
wire _T_754 = |q_ff[1:0]; // @[lib.scala 428:35]
wire _T_756 = ~q_ff[2]; // @[lib.scala 428:40]
wire _T_758 = _T_754 ? _T_756 : q_ff[2]; // @[lib.scala 428:23]
wire _T_748 = |q_ff[0]; // @[lib.scala 428:35]
wire _T_750 = ~q_ff[1]; // @[lib.scala 428:40]
wire _T_752 = _T_748 ? _T_750 : q_ff[1]; // @[lib.scala 428:23]
wire [6:0] _T_938 = {_T_788,_T_782,_T_776,_T_770,_T_764,_T_758,_T_752}; // @[lib.scala 430:14]
wire [14:0] _T_946 = {_T_836,_T_830,_T_824,_T_818,_T_812,_T_806,_T_800,_T_794,_T_938}; // @[lib.scala 430:14]
wire [30:0] _T_962 = {_T_932,_T_926,_T_920,_T_914,_T_908,_T_902,_T_896,_T_890,_T_953,_T_946}; // @[lib.scala 430:14]
wire [31:0] _T_964 = {_T_962,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_743 ? _T_964 : q_ff[31:0]; // @[exu_div_ctl.scala 243:22]
wire [32:0] _T_1000 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_1012 = _T_689 & rem_ff; // @[exu_div_ctl.scala 257:41]
reg [32:0] a_ff; // @[Reg.scala 27:20]
wire rem_correct = _T_1012 & a_ff[32]; // @[exu_div_ctl.scala 257:50]
wire [32:0] _T_985 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_974 = ~rem_correct; // @[exu_div_ctl.scala 248:6]
wire _T_975 = ~shortq_enable_ff; // @[exu_div_ctl.scala 248:21]
wire _T_976 = _T_974 & _T_975; // @[exu_div_ctl.scala 248:19]
wire [32:0] _T_980 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_986 = _T_976 ? _T_980 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_988 = _T_985 | _T_986; // @[Mux.scala 27:72]
wire _T_982 = _T_974 & shortq_enable_ff; // @[exu_div_ctl.scala 249:19]
wire [64:0] _T_970 = {33'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [95:0] _GEN_16 = {{31'd0}, _T_970}; // @[exu_div_ctl.scala 245:47]
wire [95:0] _T_972 = _GEN_16 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 245:47]
wire [64:0] a_eff_shift = _T_972[64:0]; // @[exu_div_ctl.scala 245:15]
wire [32:0] _T_987 = _T_982 ? a_eff_shift[64:32] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_988 | _T_987; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_1000 & a_eff; // @[exu_div_ctl.scala 252:33]
wire _T_1009 = a_ff[32] | rem_correct; // @[exu_div_ctl.scala 256:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[exu_div_ctl.scala 254:48]
wire add = _T_1009 ^ m_already_comp; // @[exu_div_ctl.scala 256:36]
wire [32:0] _T_968 = ~m_ff; // @[exu_div_ctl.scala 244:35]
wire [32:0] m_eff = add ? m_ff : _T_968; // @[exu_div_ctl.scala 244:15]
wire [32:0] _T_1002 = a_shift + m_eff; // @[exu_div_ctl.scala 253:41]
wire _T_1003 = ~add; // @[exu_div_ctl.scala 253:65]
wire [32:0] _T_1004 = {32'h0,_T_1003}; // @[Cat.scala 29:58]
wire [32:0] _T_1006 = _T_1002 + _T_1004; // @[exu_div_ctl.scala 253:49]
wire [32:0] a_in = _T_1000 & _T_1006; // @[exu_div_ctl.scala 253:30]
wire _T_723 = ~a_in[32]; // @[exu_div_ctl.scala 239:85]
wire [32:0] _T_724 = {dividend_eff,_T_723}; // @[Cat.scala 29:58]
wire [63:0] _GEN_17 = {{31'd0}, _T_724}; // @[exu_div_ctl.scala 239:96]
wire [63:0] _T_726 = _GEN_17 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 239:96]
wire _T_728 = ~_T_718; // @[exu_div_ctl.scala 240:18]
wire _T_729 = run_state & _T_728; // @[exu_div_ctl.scala 240:16]
wire [32:0] _T_734 = {q_ff[31:0],_T_723}; // @[Cat.scala 29:58]
wire [32:0] _T_735 = _T_715 ? _T_717 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_736 = _T_719 ? _T_726 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_737 = _T_729 ? _T_734 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_18 = {{31'd0}, _T_735}; // @[Mux.scala 27:72]
wire [63:0] _T_738 = _GEN_18 | _T_736; // @[Mux.scala 27:72]
wire [63:0] _GEN_19 = {{31'd0}, _T_737}; // @[Mux.scala 27:72]
wire [63:0] _T_739 = _T_738 | _GEN_19; // @[Mux.scala 27:72]
wire _T_742 = run_state & _T_701; // @[exu_div_ctl.scala 242:48]
wire qff_enable = io_valid_in | _T_742; // @[exu_div_ctl.scala 242:35]
wire _T_993 = count != 6'h21; // @[exu_div_ctl.scala 251:73]
wire _T_994 = _T_742 & _T_993; // @[exu_div_ctl.scala 251:64]
wire _T_995 = io_valid_in | _T_994; // @[exu_div_ctl.scala 251:34]
wire aff_enable = _T_995 | rem_correct; // @[exu_div_ctl.scala 251:89]
wire _T_1015 = dividend_neg_ff ^ divisor_neg_ff; // @[exu_div_ctl.scala 258:50]
wire _T_1016 = sign_ff & _T_1015; // @[exu_div_ctl.scala 258:31]
wire [31:0] q_ff_eff = _T_1016 ? _T_964 : q_ff[31:0]; // @[exu_div_ctl.scala 258:21]
wire _T_1244 = |a_ff[0]; // @[lib.scala 428:35]
wire _T_1246 = ~a_ff[1]; // @[lib.scala 428:40]
wire _T_1248 = _T_1244 ? _T_1246 : a_ff[1]; // @[lib.scala 428:23]
wire _T_1250 = |a_ff[1:0]; // @[lib.scala 428:35]
wire _T_1252 = ~a_ff[2]; // @[lib.scala 428:40]
wire _T_1254 = _T_1250 ? _T_1252 : a_ff[2]; // @[lib.scala 428:23]
wire _T_1256 = |a_ff[2:0]; // @[lib.scala 428:35]
wire _T_1258 = ~a_ff[3]; // @[lib.scala 428:40]
wire _T_1260 = _T_1256 ? _T_1258 : a_ff[3]; // @[lib.scala 428:23]
wire _T_1262 = |a_ff[3:0]; // @[lib.scala 428:35]
wire _T_1264 = ~a_ff[4]; // @[lib.scala 428:40]
wire _T_1266 = _T_1262 ? _T_1264 : a_ff[4]; // @[lib.scala 428:23]
wire _T_1268 = |a_ff[4:0]; // @[lib.scala 428:35]
wire _T_1270 = ~a_ff[5]; // @[lib.scala 428:40]
wire _T_1272 = _T_1268 ? _T_1270 : a_ff[5]; // @[lib.scala 428:23]
wire _T_1274 = |a_ff[5:0]; // @[lib.scala 428:35]
wire _T_1276 = ~a_ff[6]; // @[lib.scala 428:40]
wire _T_1278 = _T_1274 ? _T_1276 : a_ff[6]; // @[lib.scala 428:23]
wire _T_1280 = |a_ff[6:0]; // @[lib.scala 428:35]
wire _T_1282 = ~a_ff[7]; // @[lib.scala 428:40]
wire _T_1284 = _T_1280 ? _T_1282 : a_ff[7]; // @[lib.scala 428:23]
wire _T_1286 = |a_ff[7:0]; // @[lib.scala 428:35]
wire _T_1288 = ~a_ff[8]; // @[lib.scala 428:40]
wire _T_1290 = _T_1286 ? _T_1288 : a_ff[8]; // @[lib.scala 428:23]
wire _T_1292 = |a_ff[8:0]; // @[lib.scala 428:35]
wire _T_1294 = ~a_ff[9]; // @[lib.scala 428:40]
wire _T_1296 = _T_1292 ? _T_1294 : a_ff[9]; // @[lib.scala 428:23]
wire _T_1298 = |a_ff[9:0]; // @[lib.scala 428:35]
wire _T_1300 = ~a_ff[10]; // @[lib.scala 428:40]
wire _T_1302 = _T_1298 ? _T_1300 : a_ff[10]; // @[lib.scala 428:23]
wire _T_1304 = |a_ff[10:0]; // @[lib.scala 428:35]
wire _T_1306 = ~a_ff[11]; // @[lib.scala 428:40]
wire _T_1308 = _T_1304 ? _T_1306 : a_ff[11]; // @[lib.scala 428:23]
wire _T_1310 = |a_ff[11:0]; // @[lib.scala 428:35]
wire _T_1312 = ~a_ff[12]; // @[lib.scala 428:40]
wire _T_1314 = _T_1310 ? _T_1312 : a_ff[12]; // @[lib.scala 428:23]
wire _T_1316 = |a_ff[12:0]; // @[lib.scala 428:35]
wire _T_1318 = ~a_ff[13]; // @[lib.scala 428:40]
wire _T_1320 = _T_1316 ? _T_1318 : a_ff[13]; // @[lib.scala 428:23]
wire _T_1322 = |a_ff[13:0]; // @[lib.scala 428:35]
wire _T_1324 = ~a_ff[14]; // @[lib.scala 428:40]
wire _T_1326 = _T_1322 ? _T_1324 : a_ff[14]; // @[lib.scala 428:23]
wire _T_1328 = |a_ff[14:0]; // @[lib.scala 428:35]
wire _T_1330 = ~a_ff[15]; // @[lib.scala 428:40]
wire _T_1332 = _T_1328 ? _T_1330 : a_ff[15]; // @[lib.scala 428:23]
wire _T_1334 = |a_ff[15:0]; // @[lib.scala 428:35]
wire _T_1336 = ~a_ff[16]; // @[lib.scala 428:40]
wire _T_1338 = _T_1334 ? _T_1336 : a_ff[16]; // @[lib.scala 428:23]
wire _T_1340 = |a_ff[16:0]; // @[lib.scala 428:35]
wire _T_1342 = ~a_ff[17]; // @[lib.scala 428:40]
wire _T_1344 = _T_1340 ? _T_1342 : a_ff[17]; // @[lib.scala 428:23]
wire _T_1346 = |a_ff[17:0]; // @[lib.scala 428:35]
wire _T_1348 = ~a_ff[18]; // @[lib.scala 428:40]
wire _T_1350 = _T_1346 ? _T_1348 : a_ff[18]; // @[lib.scala 428:23]
wire _T_1352 = |a_ff[18:0]; // @[lib.scala 428:35]
wire _T_1354 = ~a_ff[19]; // @[lib.scala 428:40]
wire _T_1356 = _T_1352 ? _T_1354 : a_ff[19]; // @[lib.scala 428:23]
wire _T_1358 = |a_ff[19:0]; // @[lib.scala 428:35]
wire _T_1360 = ~a_ff[20]; // @[lib.scala 428:40]
wire _T_1362 = _T_1358 ? _T_1360 : a_ff[20]; // @[lib.scala 428:23]
wire _T_1364 = |a_ff[20:0]; // @[lib.scala 428:35]
wire _T_1366 = ~a_ff[21]; // @[lib.scala 428:40]
wire _T_1368 = _T_1364 ? _T_1366 : a_ff[21]; // @[lib.scala 428:23]
wire _T_1370 = |a_ff[21:0]; // @[lib.scala 428:35]
wire _T_1372 = ~a_ff[22]; // @[lib.scala 428:40]
wire _T_1374 = _T_1370 ? _T_1372 : a_ff[22]; // @[lib.scala 428:23]
wire _T_1376 = |a_ff[22:0]; // @[lib.scala 428:35]
wire _T_1378 = ~a_ff[23]; // @[lib.scala 428:40]
wire _T_1380 = _T_1376 ? _T_1378 : a_ff[23]; // @[lib.scala 428:23]
wire _T_1382 = |a_ff[23:0]; // @[lib.scala 428:35]
wire _T_1384 = ~a_ff[24]; // @[lib.scala 428:40]
wire _T_1386 = _T_1382 ? _T_1384 : a_ff[24]; // @[lib.scala 428:23]
wire _T_1388 = |a_ff[24:0]; // @[lib.scala 428:35]
wire _T_1390 = ~a_ff[25]; // @[lib.scala 428:40]
wire _T_1392 = _T_1388 ? _T_1390 : a_ff[25]; // @[lib.scala 428:23]
wire _T_1394 = |a_ff[25:0]; // @[lib.scala 428:35]
wire _T_1396 = ~a_ff[26]; // @[lib.scala 428:40]
wire _T_1398 = _T_1394 ? _T_1396 : a_ff[26]; // @[lib.scala 428:23]
wire _T_1400 = |a_ff[26:0]; // @[lib.scala 428:35]
wire _T_1402 = ~a_ff[27]; // @[lib.scala 428:40]
wire _T_1404 = _T_1400 ? _T_1402 : a_ff[27]; // @[lib.scala 428:23]
wire _T_1406 = |a_ff[27:0]; // @[lib.scala 428:35]
wire _T_1408 = ~a_ff[28]; // @[lib.scala 428:40]
wire _T_1410 = _T_1406 ? _T_1408 : a_ff[28]; // @[lib.scala 428:23]
wire _T_1412 = |a_ff[28:0]; // @[lib.scala 428:35]
wire _T_1414 = ~a_ff[29]; // @[lib.scala 428:40]
wire _T_1416 = _T_1412 ? _T_1414 : a_ff[29]; // @[lib.scala 428:23]
wire _T_1418 = |a_ff[29:0]; // @[lib.scala 428:35]
wire _T_1420 = ~a_ff[30]; // @[lib.scala 428:40]
wire _T_1422 = _T_1418 ? _T_1420 : a_ff[30]; // @[lib.scala 428:23]
wire _T_1424 = |a_ff[30:0]; // @[lib.scala 428:35]
wire _T_1426 = ~a_ff[31]; // @[lib.scala 428:40]
wire _T_1428 = _T_1424 ? _T_1426 : a_ff[31]; // @[lib.scala 428:23]
wire [6:0] _T_1434 = {_T_1284,_T_1278,_T_1272,_T_1266,_T_1260,_T_1254,_T_1248}; // @[lib.scala 430:14]
wire [14:0] _T_1442 = {_T_1332,_T_1326,_T_1320,_T_1314,_T_1308,_T_1302,_T_1296,_T_1290,_T_1434}; // @[lib.scala 430:14]
wire [7:0] _T_1449 = {_T_1380,_T_1374,_T_1368,_T_1362,_T_1356,_T_1350,_T_1344,_T_1338}; // @[lib.scala 430:14]
wire [30:0] _T_1458 = {_T_1428,_T_1422,_T_1416,_T_1410,_T_1404,_T_1398,_T_1392,_T_1386,_T_1449,_T_1442}; // @[lib.scala 430:14]
wire [31:0] _T_1460 = {_T_1458,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_743 ? _T_1460 : a_ff[31:0]; // @[exu_div_ctl.scala 259:21]
reg smallnum_case_ff; // @[Reg.scala 27:20]
reg [3:0] smallnum_ff; // @[Reg.scala 27:20]
wire [31:0] _T_1463 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1465 = ~smallnum_case_ff; // @[exu_div_ctl.scala 264:6]
wire _T_1467 = _T_1465 & _T_9; // @[exu_div_ctl.scala 264:24]
wire [31:0] _T_1469 = smallnum_case_ff ? _T_1463 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1470 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1471 = _T_1467 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1472 = _T_1469 | _T_1470; // @[Mux.scala 27:72]
wire _T_1476 = io_valid_in & _T; // @[exu_div_ctl.scala 266:38]
wire _T_1480 = finish & _T; // @[exu_div_ctl.scala 267:32]
wire _T_1488 = io_valid_in & io_dividend_in[31]; // @[exu_div_ctl.scala 270:44]
wire _T_1489 = ~io_valid_in; // @[exu_div_ctl.scala 270:69]
wire _T_1490 = _T_1489 & dividend_neg_ff; // @[exu_div_ctl.scala 270:82]
wire _T_1491 = _T_1488 | _T_1490; // @[exu_div_ctl.scala 270:66]
wire _T_1495 = io_valid_in & io_divisor_in[31]; // @[exu_div_ctl.scala 271:43]
wire _T_1497 = _T_1489 & divisor_neg_ff; // @[exu_div_ctl.scala 271:80]
wire _T_1498 = _T_1495 | _T_1497; // @[exu_div_ctl.scala 271:64]
wire _T_1501 = io_valid_in & sign_eff; // @[exu_div_ctl.scala 272:36]
wire _T_1503 = _T_1489 & sign_ff; // @[exu_div_ctl.scala 272:64]
wire _T_1504 = _T_1501 | _T_1503; // @[exu_div_ctl.scala 272:48]
wire _T_1507 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 273:35]
wire _T_1509 = _T_1489 & rem_ff; // @[exu_div_ctl.scala 273:64]
wire _T_1510 = _T_1507 | _T_1509; // @[exu_div_ctl.scala 273:48]
wire [32:0] q_in = _T_739[32:0]; // @[exu_div_ctl.scala 237:8]
wire _T_1526 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 281:35]
wire [32:0] _T_1528 = {_T_1526,io_divisor_in}; // @[Cat.scala 29:58]
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
rvclkhdr rvclkhdr_11 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en)
);
rvclkhdr rvclkhdr_12 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_12_io_clk),
.io_en(rvclkhdr_12_io_en)
);
rvclkhdr rvclkhdr_13 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_13_io_clk),
.io_en(rvclkhdr_13_io_en)
);
rvclkhdr rvclkhdr_14 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_14_io_clk),
.io_en(rvclkhdr_14_io_en)
);
assign io_data_out = _T_1472 | _T_1471; // @[exu_div_ctl.scala 261:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 234:17]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_11_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_12_io_en = io_valid_in | _T_742; // @[lib.scala 393:17]
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_13_io_en = _T_995 | rem_correct; // @[lib.scala 393:17]
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_14_io_en = io_valid_in; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_1520 = _RAND_5[5:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
_T_1520 = 6'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else if (div_clken) begin
valid_ff_x <= _T_1476;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else if (qff_enable) begin
q_ff <= q_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else if (io_valid_in) begin
m_ff <= _T_1528;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (div_clken) begin
rem_ff <= _T_1510;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (div_clken) begin
sign_ff <= _T_1504;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_1520 <= 6'h0;
end else if (div_clken) begin
_T_1520 <= shortq_shift;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else if (div_clken) begin
count <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else if (div_clken) begin
run_state <= run_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (div_clken) begin
finish_ff <= _T_1480;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (div_clken) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (div_clken) begin
dividend_neg_ff <= _T_1491;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else if (aff_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (div_clken) begin
divisor_neg_ff <= _T_1498;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else if (div_clken) begin
smallnum_case_ff <= smallnum_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else if (div_clken) begin
smallnum_ff <= smallnum;
end
end
endmodule

30
el2_exu_div_new_1bit_fullshortq.anno.json
View File

@ -1,30 +0,0 @@
[
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"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_new_1bit_fullshortq|el2_exu_div_new_1bit_fullshortq>io_valid_out",
"sources":[
"~el2_exu_div_new_1bit_fullshortq|el2_exu_div_new_1bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
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"target":"el2_exu_div_new_1bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
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},
{
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2110
el2_exu_div_new_1bit_fullshortq.fir
View File

File diff suppressed because it is too large Load Diff

905
el2_exu_div_new_1bit_fullshortq.v
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@ -1,905 +0,0 @@
module el2_exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 511:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 511:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 511:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 511:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 511:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 511:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 511:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 511:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 511:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 511:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 511:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 511:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 511:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 511:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 511:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 511:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 511:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 511:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 511:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 511:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 511:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 511:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 511:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 511:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 511:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 511:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 511:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 511:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 511:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 511:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 511:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_128 = io_operand == 33'hffffffff; // @[exu_div_ctl.scala 513:19]
wire _T_136 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 514:76]
wire _T_141 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 514:76]
wire _T_146 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 514:76]
wire _T_151 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 514:76]
wire _T_156 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 514:76]
wire _T_161 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 514:76]
wire _T_166 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 514:76]
wire _T_171 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 514:76]
wire _T_176 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 514:76]
wire _T_181 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 514:76]
wire _T_186 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 514:76]
wire _T_191 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 514:76]
wire _T_196 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 514:76]
wire _T_201 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 514:76]
wire _T_206 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 514:76]
wire _T_211 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 514:76]
wire _T_216 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 514:76]
wire _T_221 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 514:76]
wire _T_226 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_231 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_236 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_241 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 514:76]
wire _T_246 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_251 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_256 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_261 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_266 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_271 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_276 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_281 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 514:76]
wire [1:0] _T_285 = _T_141 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_286 = _T_146 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_287 = _T_151 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_156 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_161 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_166 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_291 = _T_171 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_176 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_181 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_186 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_191 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_196 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_201 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_206 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_299 = _T_211 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_216 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_221 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_226 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_231 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_236 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_241 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_246 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_251 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_256 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_261 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_266 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_271 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_276 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_281 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_136}; // @[Mux.scala 27:72]
wire [1:0] _T_315 = _GEN_5 | _T_285; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _T_315 | _T_286; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_316}; // @[Mux.scala 27:72]
wire [2:0] _T_317 = _GEN_6 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _T_317 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_320}; // @[Mux.scala 27:72]
wire [3:0] _T_321 = _GEN_7 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _T_321 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_328}; // @[Mux.scala 27:72]
wire [4:0] _T_329 = _GEN_8 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _T_329 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_128 ? 5'h1f : _T_343; // @[exu_div_ctl.scala 513:38]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 515:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module el2_exu_div_new_1bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 429:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 429:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 432:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 432:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire dividend_sign_ff = control_ff[2]; // @[exu_div_ctl.scala 343:40]
wire divisor_sign_ff = control_ff[1]; // @[exu_div_ctl.scala 344:40]
wire rem_ff = control_ff[0]; // @[exu_div_ctl.scala 345:40]
reg [32:0] b_ff; // @[Reg.scala 27:20]
wire _T_1 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 346:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_1; // @[exu_div_ctl.scala 346:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_3 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:37]
wire _T_5 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:60]
wire _T_6 = _T_3 & _T_5; // @[exu_div_ctl.scala 347:46]
wire _T_7 = ~by_zero_case; // @[exu_div_ctl.scala 347:71]
wire _T_8 = _T_6 & _T_7; // @[exu_div_ctl.scala 347:69]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 347:87]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 347:85]
wire _T_11 = _T_10 & valid_ff; // @[exu_div_ctl.scala 347:95]
wire _T_12 = ~io_cancel; // @[exu_div_ctl.scala 347:108]
wire _T_13 = _T_11 & _T_12; // @[exu_div_ctl.scala 347:106]
wire _T_15 = a_ff == 32'h0; // @[exu_div_ctl.scala 348:18]
wire _T_17 = _T_15 & _T_7; // @[exu_div_ctl.scala 348:27]
wire _T_19 = _T_17 & _T_9; // @[exu_div_ctl.scala 348:43]
wire _T_20 = _T_19 & valid_ff; // @[exu_div_ctl.scala 348:53]
wire _T_22 = _T_20 & _T_12; // @[exu_div_ctl.scala 348:64]
wire smallnum_case = _T_13 | _T_22; // @[exu_div_ctl.scala 347:120]
wire valid_ff_in = io_valid_in & _T_12; // @[exu_div_ctl.scala 349:43]
wire _T_24 = ~io_valid_in; // @[exu_div_ctl.scala 350:35]
wire _T_26 = _T_24 & dividend_sign_ff; // @[exu_div_ctl.scala 350:48]
wire _T_27 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 350:80]
wire _T_29 = _T_27 & io_dividend_in[31]; // @[exu_div_ctl.scala 350:96]
wire _T_30 = _T_26 | _T_29; // @[exu_div_ctl.scala 350:65]
wire _T_33 = _T_24 & divisor_sign_ff; // @[exu_div_ctl.scala 350:133]
wire _T_36 = _T_27 & io_divisor_in[31]; // @[exu_div_ctl.scala 350:181]
wire _T_37 = _T_33 | _T_36; // @[exu_div_ctl.scala 350:150]
wire _T_40 = _T_24 & rem_ff; // @[exu_div_ctl.scala 350:218]
wire _T_41 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 350:250]
wire _T_42 = _T_40 | _T_41; // @[exu_div_ctl.scala 350:235]
wire [2:0] control_in = {_T_30,_T_37,_T_42}; // @[Cat.scala 29:58]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 351:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 351:45]
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 352:43]
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 352:54]
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 352:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 352:82]
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 353:45]
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 353:72]
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 353:60]
wire finish = finish_raw & _T_12; // @[exu_div_ctl.scala 354:41]
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 355:40]
wire _T_52 = ~finish; // @[exu_div_ctl.scala 355:59]
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 355:57]
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 355:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 355:67]
wire _T_57 = _T_55 & _T_12; // @[exu_div_ctl.scala 355:80]
wire [6:0] _T_841 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_842 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_844 = _T_841 - _T_842; // @[exu_div_ctl.scala 437:41]
wire [7:0] _T_847 = {{1'd0}, _T_844}; // @[exu_div_ctl.scala 437:61]
wire [6:0] dw_shortq_raw = _T_847[6:0]; // @[exu_div_ctl.scala 437:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 438:19]
wire _T_852 = ~shortq[5]; // @[exu_div_ctl.scala 439:31]
wire _T_853 = valid_ff & _T_852; // @[exu_div_ctl.scala 439:29]
wire _T_855 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 439:58]
wire _T_856 = ~_T_855; // @[exu_div_ctl.scala 439:44]
wire _T_857 = _T_853 & _T_856; // @[exu_div_ctl.scala 439:42]
wire shortq_enable = _T_857 & _T_12; // @[exu_div_ctl.scala 439:74]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 355:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 355:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h1; // @[exu_div_ctl.scala 356:63]
reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 356:83]
wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 356:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 357:43]
wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 358:47]
wire a_shift = running_state & _T_67; // @[exu_div_ctl.scala 358:45]
wire [31:0] _T_69 = dividend_sign_ff ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_70 = {_T_69,a_ff}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 359:68]
wire [94:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 359:68]
wire _T_72 = dividend_sign_ff ^ divisor_sign_ff; // @[exu_div_ctl.scala 360:61]
wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 360:42]
wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 360:40]
wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 362:30]
wire _T_78 = _T_76 & _T_9; // @[exu_div_ctl.scala 362:40]
wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 362:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 362:92]
wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 362:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 363:43]
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 364:54]
wire _T_83 = valid_ff & dividend_sign_ff; // @[exu_div_ctl.scala 365:40]
wire r_sign_sel = _T_83 & _T_7; // @[exu_div_ctl.scala 365:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [32:0] _T_360 = {r_ff,a_ff[31]}; // @[Cat.scala 29:58]
wire [32:0] adder_out = _T_360 + b_ff; // @[exu_div_ctl.scala 395:35]
wire _T_364 = ~adder_out[32]; // @[exu_div_ctl.scala 396:20]
wire _T_365 = _T_364 ^ dividend_sign_ff; // @[exu_div_ctl.scala 396:35]
wire _T_367 = a_ff[30:0] == 31'h0; // @[exu_div_ctl.scala 396:70]
wire _T_368 = adder_out == 33'h0; // @[exu_div_ctl.scala 396:92]
wire _T_369 = _T_367 & _T_368; // @[exu_div_ctl.scala 396:79]
wire quotient_set = _T_365 | _T_369; // @[exu_div_ctl.scala 396:55]
wire _T_85 = ~quotient_set; // @[exu_div_ctl.scala 366:47]
wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 366:45]
wire r_restore_sel = _T_86 & _T_67; // @[exu_div_ctl.scala 366:61]
wire _T_88 = running_state & quotient_set; // @[exu_div_ctl.scala 367:45]
wire r_adder_sel = _T_88 & _T_67; // @[exu_div_ctl.scala 367:61]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_91 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_92 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_91 | _T_92; // @[Mux.scala 27:72]
wire _T_96 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_98 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_100 = _T_96 ? _T_98 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_102 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_104 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_106 = _T_102 ? _T_104 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_108 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_110 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_112 = _T_108 ? _T_110 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_114 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_116 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_118 = _T_114 ? _T_116 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_120 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_122 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_124 = _T_120 ? _T_122 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_126 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_128 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_130 = _T_126 ? _T_128 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_132 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_134 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_136 = _T_132 ? _T_134 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_138 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_140 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_142 = _T_138 ? _T_140 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_144 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_146 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_148 = _T_144 ? _T_146 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_150 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_152 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_154 = _T_150 ? _T_152 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_156 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_158 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_160 = _T_156 ? _T_158 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_162 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_164 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_166 = _T_162 ? _T_164 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_168 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_170 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_172 = _T_168 ? _T_170 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_174 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_176 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_178 = _T_174 ? _T_176 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_180 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_182 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_184 = _T_180 ? _T_182 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_186 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_188 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_190 = _T_186 ? _T_188 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_192 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_194 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_196 = _T_192 ? _T_194 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_198 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_200 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_202 = _T_198 ? _T_200 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_204 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_206 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_208 = _T_204 ? _T_206 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_210 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_212 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_214 = _T_210 ? _T_212 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_216 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_218 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_220 = _T_216 ? _T_218 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_222 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_224 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_226 = _T_222 ? _T_224 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_228 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_230 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_232 = _T_228 ? _T_230 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_234 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_236 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_238 = _T_234 ? _T_236 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_240 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_242 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_244 = _T_240 ? _T_242 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_246 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_248 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_250 = _T_246 ? _T_248 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_252 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_254 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_256 = _T_252 ? _T_254 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_258 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_260 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_262 = _T_258 ? _T_260 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_264 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_266 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_268 = _T_264 ? _T_266 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_270 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_272 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_274 = _T_270 ? _T_272 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_276 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_278 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_280 = _T_276 ? _T_278 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_286 = {_T_136,_T_130,_T_124,_T_118,_T_112,_T_106,_T_100}; // @[lib.scala 430:14]
wire [14:0] _T_294 = {_T_184,_T_178,_T_172,_T_166,_T_160,_T_154,_T_148,_T_142,_T_286}; // @[lib.scala 430:14]
wire [7:0] _T_301 = {_T_232,_T_226,_T_220,_T_214,_T_208,_T_202,_T_196,_T_190}; // @[lib.scala 430:14]
wire [30:0] _T_310 = {_T_280,_T_274,_T_268,_T_262,_T_256,_T_250,_T_244,_T_238,_T_301,_T_294}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_312 = ~a_shift; // @[exu_div_ctl.scala 375:6]
wire _T_314 = _T_312 & _T_67; // @[exu_div_ctl.scala 375:15]
wire [31:0] _T_317 = {a_ff[30:0],1'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_71[63:0]; // @[exu_div_ctl.scala 359:28]
wire [31:0] _T_319 = _T_314 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_320 = a_shift ? _T_317 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_321 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_322 = _T_319 | _T_320; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_322 | _T_321; // @[Mux.scala 27:72]
wire _T_324 = ~b_twos_comp; // @[exu_div_ctl.scala 380:5]
wire _T_326 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 380:63]
wire [32:0] _T_328 = {_T_326,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_329 = ~divisor_sign_ff; // @[exu_div_ctl.scala 381:50]
wire [32:0] _T_331 = {_T_329,_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_332 = _T_324 ? _T_328 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_333 = b_twos_comp ? _T_331 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_332 | _T_333; // @[Mux.scala 27:72]
wire [31:0] _T_337 = {r_ff[30:0],a_ff[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_340 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_341 = r_restore_sel ? _T_337 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_342 = r_adder_sel ? adder_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_343 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_344 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_345 = _T_340 | _T_341; // @[Mux.scala 27:72]
wire [31:0] _T_346 = _T_345 | _T_342; // @[Mux.scala 27:72]
wire [31:0] _T_347 = _T_346 | _T_343; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_347 | _T_344; // @[Mux.scala 27:72]
wire [31:0] _T_351 = {q_ff[30:0],quotient_set}; // @[Cat.scala 29:58]
wire _T_385 = ~b_ff[3]; // @[exu_div_ctl.scala 405:70]
wire _T_387 = ~b_ff[2]; // @[exu_div_ctl.scala 405:70]
wire _T_390 = _T_385 & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_389 = ~b_ff[1]; // @[exu_div_ctl.scala 405:70]
wire _T_391 = _T_390 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_392 = a_ff[3] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_399 = a_ff[3] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_401 = ~b_ff[0]; // @[exu_div_ctl.scala 412:33]
wire _T_402 = _T_399 & _T_401; // @[exu_div_ctl.scala 412:31]
wire _T_412 = a_ff[2] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_413 = _T_402 | _T_412; // @[exu_div_ctl.scala 412:42]
wire _T_416 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_422 = _T_416 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_423 = _T_413 | _T_422; // @[exu_div_ctl.scala 412:75]
wire _T_430 = a_ff[2] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_433 = _T_430 & _T_401; // @[exu_div_ctl.scala 414:31]
wire _T_443 = a_ff[1] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_444 = _T_433 | _T_443; // @[exu_div_ctl.scala 414:42]
wire _T_450 = _T_385 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_451 = a_ff[3] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_454 = _T_451 & _T_401; // @[exu_div_ctl.scala 414:106]
wire _T_455 = _T_444 | _T_454; // @[exu_div_ctl.scala 414:78]
wire _T_458 = ~a_ff[2]; // @[exu_div_ctl.scala 404:70]
wire _T_459 = a_ff[3] & _T_458; // @[exu_div_ctl.scala 404:95]
wire _T_467 = _T_390 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_468 = _T_467 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_469 = _T_459 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_470 = _T_455 | _T_469; // @[exu_div_ctl.scala 414:117]
wire _T_472 = ~a_ff[3]; // @[exu_div_ctl.scala 404:70]
wire _T_475 = _T_472 & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_476 = _T_475 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_482 = _T_476 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_483 = _T_470 | _T_482; // @[exu_div_ctl.scala 415:44]
wire _T_489 = _T_416 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_492 = _T_489 & _T_401; // @[exu_div_ctl.scala 415:107]
wire _T_493 = _T_483 | _T_492; // @[exu_div_ctl.scala 415:80]
wire _T_502 = _T_385 & b_ff[2]; // @[exu_div_ctl.scala 405:95]
wire _T_503 = _T_502 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_504 = _T_416 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_505 = _T_493 | _T_504; // @[exu_div_ctl.scala 415:119]
wire _T_508 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_514 = _T_508 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_515 = _T_505 | _T_514; // @[exu_div_ctl.scala 416:44]
wire _T_520 = _T_416 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_525 = _T_520 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_526 = _T_515 | _T_525; // @[exu_div_ctl.scala 416:79]
wire _T_530 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_531 = _T_530 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_537 = _T_531 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_543 = _T_459 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_548 = _T_385 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_549 = _T_548 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_550 = _T_543 & _T_549; // @[exu_div_ctl.scala 406:11]
wire _T_551 = _T_537 | _T_550; // @[exu_div_ctl.scala 418:45]
wire _T_558 = a_ff[2] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_561 = _T_558 & _T_401; // @[exu_div_ctl.scala 418:114]
wire _T_562 = _T_551 | _T_561; // @[exu_div_ctl.scala 418:86]
wire _T_569 = a_ff[1] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_572 = _T_569 & _T_401; // @[exu_div_ctl.scala 419:33]
wire _T_573 = _T_562 | _T_572; // @[exu_div_ctl.scala 418:129]
wire _T_583 = a_ff[0] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_584 = _T_573 | _T_583; // @[exu_div_ctl.scala 419:47]
wire _T_589 = ~a_ff[1]; // @[exu_div_ctl.scala 404:70]
wire _T_591 = _T_475 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_601 = _T_591 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_602 = _T_584 | _T_601; // @[exu_div_ctl.scala 419:88]
wire _T_611 = _T_476 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_614 = _T_611 & _T_401; // @[exu_div_ctl.scala 420:36]
wire _T_615 = _T_602 | _T_614; // @[exu_div_ctl.scala 419:131]
wire _T_621 = _T_387 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_622 = a_ff[3] & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_625 = _T_622 & _T_401; // @[exu_div_ctl.scala 420:76]
wire _T_626 = _T_615 | _T_625; // @[exu_div_ctl.scala 420:47]
wire _T_636 = _T_502 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_637 = _T_459 & _T_636; // @[exu_div_ctl.scala 406:11]
wire _T_638 = _T_626 | _T_637; // @[exu_div_ctl.scala 420:88]
wire _T_652 = _T_476 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_653 = _T_638 | _T_652; // @[exu_div_ctl.scala 420:131]
wire _T_659 = _T_475 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_665 = _T_659 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_666 = _T_653 | _T_665; // @[exu_div_ctl.scala 421:47]
wire _T_673 = _T_459 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_679 = _T_502 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_680 = _T_673 & _T_679; // @[exu_div_ctl.scala 406:11]
wire _T_681 = _T_666 | _T_680; // @[exu_div_ctl.scala 421:88]
wire _T_686 = _T_458 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_687 = _T_686 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_693 = _T_687 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_694 = _T_681 | _T_693; // @[exu_div_ctl.scala 421:131]
wire _T_700 = _T_416 & _T_389; // @[exu_div_ctl.scala 406:11]
wire _T_703 = _T_700 & _T_401; // @[exu_div_ctl.scala 422:75]
wire _T_704 = _T_694 | _T_703; // @[exu_div_ctl.scala 422:47]
wire _T_712 = _T_476 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_717 = _T_712 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_718 = _T_704 | _T_717; // @[exu_div_ctl.scala 422:88]
wire _T_725 = b_ff[3] & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_726 = _T_416 & _T_725; // @[exu_div_ctl.scala 406:11]
wire _T_727 = _T_718 | _T_726; // @[exu_div_ctl.scala 422:131]
wire _T_737 = _T_725 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_738 = _T_508 & _T_737; // @[exu_div_ctl.scala 406:11]
wire _T_739 = _T_727 | _T_738; // @[exu_div_ctl.scala 423:47]
wire _T_742 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_748 = _T_742 & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_749 = _T_739 | _T_748; // @[exu_div_ctl.scala 423:88]
wire _T_753 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_761 = _T_636 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_762 = _T_753 & _T_761; // @[exu_div_ctl.scala 406:11]
wire _T_763 = _T_749 | _T_762; // @[exu_div_ctl.scala 423:131]
wire _T_770 = _T_520 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_773 = _T_770 & _T_401; // @[exu_div_ctl.scala 424:77]
wire _T_774 = _T_763 | _T_773; // @[exu_div_ctl.scala 424:47]
wire _T_783 = b_ff[3] & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_784 = _T_520 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_785 = _T_774 | _T_784; // @[exu_div_ctl.scala 424:88]
wire _T_790 = _T_416 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_795 = _T_790 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_796 = _T_785 | _T_795; // @[exu_div_ctl.scala 424:131]
wire _T_802 = _T_459 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_807 = _T_802 & _T_548; // @[exu_div_ctl.scala 406:11]
wire _T_808 = _T_796 | _T_807; // @[exu_div_ctl.scala 425:47]
wire _T_813 = _T_508 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_816 = _T_813 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_817 = _T_808 | _T_816; // @[exu_div_ctl.scala 425:88]
wire _T_824 = _T_520 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_826 = _T_824 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_827 = _T_817 | _T_826; // @[exu_div_ctl.scala 425:131]
wire _T_833 = _T_508 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_836 = _T_833 & _T_401; // @[exu_div_ctl.scala 426:74]
wire _T_837 = _T_827 | _T_836; // @[exu_div_ctl.scala 426:47]
wire [31:0] _T_352 = {28'h0,_T_392,_T_423,_T_526,_T_837}; // @[Cat.scala 29:58]
wire [31:0] _T_354 = _T_76 ? _T_351 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_355 = smallnum_case ? _T_352 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_356 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_357 = _T_354 | _T_355; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_357 | _T_356; // @[Mux.scala 27:72]
wire _T_374 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 399:16]
wire _T_375 = _T_9 & _T_374; // @[exu_div_ctl.scala 399:14]
wire [31:0] _T_377 = _T_375 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_378 = rem_ff ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_379 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_380 = _T_377 | _T_378; // @[Mux.scala 27:72]
wire [4:0] _T_863 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 440:57]
el2_exu_div_cls a_enc ( // @[exu_div_ctl.scala 429:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
el2_exu_div_cls b_enc ( // @[exu_div_ctl.scala 432:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_380 | _T_379; // @[exu_div_ctl.scala 398:15]
assign io_valid_out = finish_ff & _T_12; // @[exu_div_ctl.scala 397:16]
assign a_enc_io_operand = {dividend_sign_ff,a_ff}; // @[exu_div_ctl.scala 430:20]
assign b_enc_io_operand = b_ff; // @[exu_div_ctl.scala 433:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
shortq_shift_ff = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_shift_ff = 5'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff <= 33'h0;
end else if (b_enable) begin
b_ff <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_ff <= 5'h0;
end else if (misc_enable) begin
if (_T_58) begin
shortq_shift_ff <= 5'h0;
end else begin
shortq_shift_ff <= _T_863;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

30
exu_div_new_1bit_fullshortq.anno.json
View File

@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_1bit_fullshortq|exu_div_new_1bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_1bit_fullshortq|exu_div_new_1bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_1bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_1bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2110
exu_div_new_1bit_fullshortq.fir
View File

File diff suppressed because it is too large Load Diff

904
exu_div_new_1bit_fullshortq.v
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@ -1,904 +0,0 @@
module exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 510:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 510:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 510:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 510:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 510:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 510:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 510:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 510:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 510:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 510:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 510:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 510:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 510:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 510:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 510:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 510:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 510:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 510:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 510:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 510:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 510:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 510:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 510:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 510:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 510:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 510:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 510:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 510:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 510:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 510:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 510:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 512:25]
wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 513:76]
wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 513:76]
wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 513:76]
wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 513:76]
wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 513:76]
wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 513:76]
wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 513:76]
wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 513:76]
wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 513:76]
wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 513:76]
wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 513:76]
wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 513:76]
wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 513:76]
wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 513:76]
wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 513:76]
wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 513:76]
wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 513:76]
wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 513:76]
wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 513:76]
wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 513:76]
wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 512:44]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 514:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_div_new_1bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 429:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 429:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 432:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 432:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire dividend_sign_ff = control_ff[2]; // @[exu_div_ctl.scala 343:40]
wire divisor_sign_ff = control_ff[1]; // @[exu_div_ctl.scala 344:40]
wire rem_ff = control_ff[0]; // @[exu_div_ctl.scala 345:40]
reg [32:0] b_ff; // @[Reg.scala 27:20]
wire _T_1 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 346:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_1; // @[exu_div_ctl.scala 346:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_3 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:37]
wire _T_5 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:60]
wire _T_6 = _T_3 & _T_5; // @[exu_div_ctl.scala 347:46]
wire _T_7 = ~by_zero_case; // @[exu_div_ctl.scala 347:71]
wire _T_8 = _T_6 & _T_7; // @[exu_div_ctl.scala 347:69]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 347:87]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 347:85]
wire _T_11 = _T_10 & valid_ff; // @[exu_div_ctl.scala 347:95]
wire _T_12 = ~io_cancel; // @[exu_div_ctl.scala 347:108]
wire _T_13 = _T_11 & _T_12; // @[exu_div_ctl.scala 347:106]
wire _T_15 = a_ff == 32'h0; // @[exu_div_ctl.scala 348:18]
wire _T_17 = _T_15 & _T_7; // @[exu_div_ctl.scala 348:27]
wire _T_19 = _T_17 & _T_9; // @[exu_div_ctl.scala 348:43]
wire _T_20 = _T_19 & valid_ff; // @[exu_div_ctl.scala 348:53]
wire _T_22 = _T_20 & _T_12; // @[exu_div_ctl.scala 348:64]
wire smallnum_case = _T_13 | _T_22; // @[exu_div_ctl.scala 347:120]
wire valid_ff_in = io_valid_in & _T_12; // @[exu_div_ctl.scala 349:43]
wire _T_24 = ~io_valid_in; // @[exu_div_ctl.scala 350:35]
wire _T_26 = _T_24 & dividend_sign_ff; // @[exu_div_ctl.scala 350:48]
wire _T_27 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 350:80]
wire _T_29 = _T_27 & io_dividend_in[31]; // @[exu_div_ctl.scala 350:96]
wire _T_30 = _T_26 | _T_29; // @[exu_div_ctl.scala 350:65]
wire _T_33 = _T_24 & divisor_sign_ff; // @[exu_div_ctl.scala 350:133]
wire _T_36 = _T_27 & io_divisor_in[31]; // @[exu_div_ctl.scala 350:181]
wire _T_37 = _T_33 | _T_36; // @[exu_div_ctl.scala 350:150]
wire _T_40 = _T_24 & rem_ff; // @[exu_div_ctl.scala 350:218]
wire _T_41 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 350:250]
wire _T_42 = _T_40 | _T_41; // @[exu_div_ctl.scala 350:235]
wire [2:0] control_in = {_T_30,_T_37,_T_42}; // @[Cat.scala 29:58]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 351:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 351:45]
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 352:43]
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 352:54]
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 352:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 352:82]
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 353:45]
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 353:72]
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 353:60]
wire finish = finish_raw & _T_12; // @[exu_div_ctl.scala 354:41]
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 355:40]
wire _T_52 = ~finish; // @[exu_div_ctl.scala 355:59]
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 355:57]
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 355:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 355:67]
wire _T_57 = _T_55 & _T_12; // @[exu_div_ctl.scala 355:80]
wire [6:0] _T_841 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_842 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_844 = _T_841 - _T_842; // @[exu_div_ctl.scala 437:41]
wire [6:0] dw_shortq_raw = _T_844 + 7'h1; // @[exu_div_ctl.scala 437:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 438:19]
wire _T_850 = ~shortq[5]; // @[exu_div_ctl.scala 439:31]
wire _T_851 = valid_ff & _T_850; // @[exu_div_ctl.scala 439:29]
wire _T_853 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 439:58]
wire _T_854 = ~_T_853; // @[exu_div_ctl.scala 439:44]
wire _T_855 = _T_851 & _T_854; // @[exu_div_ctl.scala 439:42]
wire shortq_enable = _T_855 & _T_12; // @[exu_div_ctl.scala 439:74]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 355:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 355:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h1; // @[exu_div_ctl.scala 356:63]
reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 356:83]
wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 356:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 357:43]
wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 358:47]
wire a_shift = running_state & _T_67; // @[exu_div_ctl.scala 358:45]
wire [31:0] _T_69 = dividend_sign_ff ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_70 = {_T_69,a_ff}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 359:68]
wire [94:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 359:68]
wire _T_72 = dividend_sign_ff ^ divisor_sign_ff; // @[exu_div_ctl.scala 360:61]
wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 360:42]
wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 360:40]
wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 362:30]
wire _T_78 = _T_76 & _T_9; // @[exu_div_ctl.scala 362:40]
wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 362:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 362:92]
wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 362:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 363:43]
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 364:54]
wire _T_83 = valid_ff & dividend_sign_ff; // @[exu_div_ctl.scala 365:40]
wire r_sign_sel = _T_83 & _T_7; // @[exu_div_ctl.scala 365:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [32:0] _T_360 = {r_ff,a_ff[31]}; // @[Cat.scala 29:58]
wire [32:0] adder_out = _T_360 + b_ff; // @[exu_div_ctl.scala 395:35]
wire _T_364 = ~adder_out[32]; // @[exu_div_ctl.scala 396:20]
wire _T_365 = _T_364 ^ dividend_sign_ff; // @[exu_div_ctl.scala 396:35]
wire _T_367 = a_ff[30:0] == 31'h0; // @[exu_div_ctl.scala 396:70]
wire _T_368 = adder_out == 33'h0; // @[exu_div_ctl.scala 396:92]
wire _T_369 = _T_367 & _T_368; // @[exu_div_ctl.scala 396:79]
wire quotient_set = _T_365 | _T_369; // @[exu_div_ctl.scala 396:55]
wire _T_85 = ~quotient_set; // @[exu_div_ctl.scala 366:47]
wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 366:45]
wire r_restore_sel = _T_86 & _T_67; // @[exu_div_ctl.scala 366:61]
wire _T_88 = running_state & quotient_set; // @[exu_div_ctl.scala 367:45]
wire r_adder_sel = _T_88 & _T_67; // @[exu_div_ctl.scala 367:61]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_91 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_92 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_91 | _T_92; // @[Mux.scala 27:72]
wire _T_96 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_98 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_100 = _T_96 ? _T_98 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_102 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_104 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_106 = _T_102 ? _T_104 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_108 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_110 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_112 = _T_108 ? _T_110 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_114 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_116 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_118 = _T_114 ? _T_116 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_120 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_122 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_124 = _T_120 ? _T_122 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_126 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_128 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_130 = _T_126 ? _T_128 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_132 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_134 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_136 = _T_132 ? _T_134 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_138 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_140 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_142 = _T_138 ? _T_140 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_144 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_146 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_148 = _T_144 ? _T_146 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_150 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_152 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_154 = _T_150 ? _T_152 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_156 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_158 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_160 = _T_156 ? _T_158 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_162 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_164 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_166 = _T_162 ? _T_164 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_168 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_170 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_172 = _T_168 ? _T_170 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_174 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_176 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_178 = _T_174 ? _T_176 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_180 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_182 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_184 = _T_180 ? _T_182 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_186 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_188 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_190 = _T_186 ? _T_188 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_192 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_194 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_196 = _T_192 ? _T_194 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_198 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_200 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_202 = _T_198 ? _T_200 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_204 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_206 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_208 = _T_204 ? _T_206 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_210 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_212 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_214 = _T_210 ? _T_212 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_216 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_218 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_220 = _T_216 ? _T_218 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_222 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_224 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_226 = _T_222 ? _T_224 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_228 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_230 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_232 = _T_228 ? _T_230 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_234 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_236 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_238 = _T_234 ? _T_236 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_240 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_242 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_244 = _T_240 ? _T_242 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_246 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_248 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_250 = _T_246 ? _T_248 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_252 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_254 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_256 = _T_252 ? _T_254 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_258 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_260 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_262 = _T_258 ? _T_260 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_264 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_266 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_268 = _T_264 ? _T_266 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_270 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_272 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_274 = _T_270 ? _T_272 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_276 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_278 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_280 = _T_276 ? _T_278 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_286 = {_T_136,_T_130,_T_124,_T_118,_T_112,_T_106,_T_100}; // @[lib.scala 430:14]
wire [14:0] _T_294 = {_T_184,_T_178,_T_172,_T_166,_T_160,_T_154,_T_148,_T_142,_T_286}; // @[lib.scala 430:14]
wire [7:0] _T_301 = {_T_232,_T_226,_T_220,_T_214,_T_208,_T_202,_T_196,_T_190}; // @[lib.scala 430:14]
wire [30:0] _T_310 = {_T_280,_T_274,_T_268,_T_262,_T_256,_T_250,_T_244,_T_238,_T_301,_T_294}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_312 = ~a_shift; // @[exu_div_ctl.scala 375:6]
wire _T_314 = _T_312 & _T_67; // @[exu_div_ctl.scala 375:15]
wire [31:0] _T_317 = {a_ff[30:0],1'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_71[63:0]; // @[exu_div_ctl.scala 359:28]
wire [31:0] _T_319 = _T_314 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_320 = a_shift ? _T_317 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_321 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_322 = _T_319 | _T_320; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_322 | _T_321; // @[Mux.scala 27:72]
wire _T_324 = ~b_twos_comp; // @[exu_div_ctl.scala 380:5]
wire _T_326 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 380:63]
wire [32:0] _T_328 = {_T_326,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_329 = ~divisor_sign_ff; // @[exu_div_ctl.scala 381:50]
wire [32:0] _T_331 = {_T_329,_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_332 = _T_324 ? _T_328 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_333 = b_twos_comp ? _T_331 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_332 | _T_333; // @[Mux.scala 27:72]
wire [31:0] _T_337 = {r_ff[30:0],a_ff[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_340 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_341 = r_restore_sel ? _T_337 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_342 = r_adder_sel ? adder_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_343 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_344 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_345 = _T_340 | _T_341; // @[Mux.scala 27:72]
wire [31:0] _T_346 = _T_345 | _T_342; // @[Mux.scala 27:72]
wire [31:0] _T_347 = _T_346 | _T_343; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_347 | _T_344; // @[Mux.scala 27:72]
wire [31:0] _T_351 = {q_ff[30:0],quotient_set}; // @[Cat.scala 29:58]
wire _T_385 = ~b_ff[3]; // @[exu_div_ctl.scala 405:70]
wire _T_387 = ~b_ff[2]; // @[exu_div_ctl.scala 405:70]
wire _T_390 = _T_385 & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_389 = ~b_ff[1]; // @[exu_div_ctl.scala 405:70]
wire _T_391 = _T_390 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_392 = a_ff[3] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_399 = a_ff[3] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_401 = ~b_ff[0]; // @[exu_div_ctl.scala 412:33]
wire _T_402 = _T_399 & _T_401; // @[exu_div_ctl.scala 412:31]
wire _T_412 = a_ff[2] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_413 = _T_402 | _T_412; // @[exu_div_ctl.scala 412:42]
wire _T_416 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_422 = _T_416 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_423 = _T_413 | _T_422; // @[exu_div_ctl.scala 412:75]
wire _T_430 = a_ff[2] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_433 = _T_430 & _T_401; // @[exu_div_ctl.scala 414:31]
wire _T_443 = a_ff[1] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_444 = _T_433 | _T_443; // @[exu_div_ctl.scala 414:42]
wire _T_450 = _T_385 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_451 = a_ff[3] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_454 = _T_451 & _T_401; // @[exu_div_ctl.scala 414:106]
wire _T_455 = _T_444 | _T_454; // @[exu_div_ctl.scala 414:78]
wire _T_458 = ~a_ff[2]; // @[exu_div_ctl.scala 404:70]
wire _T_459 = a_ff[3] & _T_458; // @[exu_div_ctl.scala 404:95]
wire _T_467 = _T_390 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_468 = _T_467 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_469 = _T_459 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_470 = _T_455 | _T_469; // @[exu_div_ctl.scala 414:117]
wire _T_472 = ~a_ff[3]; // @[exu_div_ctl.scala 404:70]
wire _T_475 = _T_472 & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_476 = _T_475 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_482 = _T_476 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_483 = _T_470 | _T_482; // @[exu_div_ctl.scala 415:44]
wire _T_489 = _T_416 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_492 = _T_489 & _T_401; // @[exu_div_ctl.scala 415:107]
wire _T_493 = _T_483 | _T_492; // @[exu_div_ctl.scala 415:80]
wire _T_502 = _T_385 & b_ff[2]; // @[exu_div_ctl.scala 405:95]
wire _T_503 = _T_502 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_504 = _T_416 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_505 = _T_493 | _T_504; // @[exu_div_ctl.scala 415:119]
wire _T_508 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_514 = _T_508 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_515 = _T_505 | _T_514; // @[exu_div_ctl.scala 416:44]
wire _T_520 = _T_416 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_525 = _T_520 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_526 = _T_515 | _T_525; // @[exu_div_ctl.scala 416:79]
wire _T_530 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_531 = _T_530 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_537 = _T_531 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_543 = _T_459 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_548 = _T_385 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_549 = _T_548 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_550 = _T_543 & _T_549; // @[exu_div_ctl.scala 406:11]
wire _T_551 = _T_537 | _T_550; // @[exu_div_ctl.scala 418:45]
wire _T_558 = a_ff[2] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_561 = _T_558 & _T_401; // @[exu_div_ctl.scala 418:114]
wire _T_562 = _T_551 | _T_561; // @[exu_div_ctl.scala 418:86]
wire _T_569 = a_ff[1] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_572 = _T_569 & _T_401; // @[exu_div_ctl.scala 419:33]
wire _T_573 = _T_562 | _T_572; // @[exu_div_ctl.scala 418:129]
wire _T_583 = a_ff[0] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_584 = _T_573 | _T_583; // @[exu_div_ctl.scala 419:47]
wire _T_589 = ~a_ff[1]; // @[exu_div_ctl.scala 404:70]
wire _T_591 = _T_475 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_601 = _T_591 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_602 = _T_584 | _T_601; // @[exu_div_ctl.scala 419:88]
wire _T_611 = _T_476 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_614 = _T_611 & _T_401; // @[exu_div_ctl.scala 420:36]
wire _T_615 = _T_602 | _T_614; // @[exu_div_ctl.scala 419:131]
wire _T_621 = _T_387 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_622 = a_ff[3] & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_625 = _T_622 & _T_401; // @[exu_div_ctl.scala 420:76]
wire _T_626 = _T_615 | _T_625; // @[exu_div_ctl.scala 420:47]
wire _T_636 = _T_502 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_637 = _T_459 & _T_636; // @[exu_div_ctl.scala 406:11]
wire _T_638 = _T_626 | _T_637; // @[exu_div_ctl.scala 420:88]
wire _T_652 = _T_476 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_653 = _T_638 | _T_652; // @[exu_div_ctl.scala 420:131]
wire _T_659 = _T_475 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_665 = _T_659 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_666 = _T_653 | _T_665; // @[exu_div_ctl.scala 421:47]
wire _T_673 = _T_459 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_679 = _T_502 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_680 = _T_673 & _T_679; // @[exu_div_ctl.scala 406:11]
wire _T_681 = _T_666 | _T_680; // @[exu_div_ctl.scala 421:88]
wire _T_686 = _T_458 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_687 = _T_686 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_693 = _T_687 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_694 = _T_681 | _T_693; // @[exu_div_ctl.scala 421:131]
wire _T_700 = _T_416 & _T_389; // @[exu_div_ctl.scala 406:11]
wire _T_703 = _T_700 & _T_401; // @[exu_div_ctl.scala 422:75]
wire _T_704 = _T_694 | _T_703; // @[exu_div_ctl.scala 422:47]
wire _T_712 = _T_476 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_717 = _T_712 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_718 = _T_704 | _T_717; // @[exu_div_ctl.scala 422:88]
wire _T_725 = b_ff[3] & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_726 = _T_416 & _T_725; // @[exu_div_ctl.scala 406:11]
wire _T_727 = _T_718 | _T_726; // @[exu_div_ctl.scala 422:131]
wire _T_737 = _T_725 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_738 = _T_508 & _T_737; // @[exu_div_ctl.scala 406:11]
wire _T_739 = _T_727 | _T_738; // @[exu_div_ctl.scala 423:47]
wire _T_742 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_748 = _T_742 & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_749 = _T_739 | _T_748; // @[exu_div_ctl.scala 423:88]
wire _T_753 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_761 = _T_636 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_762 = _T_753 & _T_761; // @[exu_div_ctl.scala 406:11]
wire _T_763 = _T_749 | _T_762; // @[exu_div_ctl.scala 423:131]
wire _T_770 = _T_520 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_773 = _T_770 & _T_401; // @[exu_div_ctl.scala 424:77]
wire _T_774 = _T_763 | _T_773; // @[exu_div_ctl.scala 424:47]
wire _T_783 = b_ff[3] & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_784 = _T_520 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_785 = _T_774 | _T_784; // @[exu_div_ctl.scala 424:88]
wire _T_790 = _T_416 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_795 = _T_790 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_796 = _T_785 | _T_795; // @[exu_div_ctl.scala 424:131]
wire _T_802 = _T_459 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_807 = _T_802 & _T_548; // @[exu_div_ctl.scala 406:11]
wire _T_808 = _T_796 | _T_807; // @[exu_div_ctl.scala 425:47]
wire _T_813 = _T_508 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_816 = _T_813 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_817 = _T_808 | _T_816; // @[exu_div_ctl.scala 425:88]
wire _T_824 = _T_520 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_826 = _T_824 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_827 = _T_817 | _T_826; // @[exu_div_ctl.scala 425:131]
wire _T_833 = _T_508 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_836 = _T_833 & _T_401; // @[exu_div_ctl.scala 426:74]
wire _T_837 = _T_827 | _T_836; // @[exu_div_ctl.scala 426:47]
wire [31:0] _T_352 = {28'h0,_T_392,_T_423,_T_526,_T_837}; // @[Cat.scala 29:58]
wire [31:0] _T_354 = _T_76 ? _T_351 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_355 = smallnum_case ? _T_352 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_356 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_357 = _T_354 | _T_355; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_357 | _T_356; // @[Mux.scala 27:72]
wire _T_374 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 399:16]
wire _T_375 = _T_9 & _T_374; // @[exu_div_ctl.scala 399:14]
wire [31:0] _T_377 = _T_375 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_378 = rem_ff ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_379 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_380 = _T_377 | _T_378; // @[Mux.scala 27:72]
wire [4:0] _T_861 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 440:57]
exu_div_cls a_enc ( // @[exu_div_ctl.scala 429:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
exu_div_cls b_enc ( // @[exu_div_ctl.scala 432:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_380 | _T_379; // @[exu_div_ctl.scala 398:15]
assign io_valid_out = finish_ff & _T_12; // @[exu_div_ctl.scala 397:16]
assign a_enc_io_operand = {dividend_sign_ff,a_ff}; // @[exu_div_ctl.scala 430:20]
assign b_enc_io_operand = b_ff; // @[exu_div_ctl.scala 433:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
shortq_shift_ff = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_shift_ff = 5'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff <= 33'h0;
end else if (b_enable) begin
b_ff <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_ff <= 5'h0;
end else if (misc_enable) begin
if (_T_58) begin
shortq_shift_ff <= 5'h0;
end else begin
shortq_shift_ff <= _T_861;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

30
exu_div_new_2bit_fullshortq.anno.json
View File

@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_2bit_fullshortq|exu_div_new_2bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_2bit_fullshortq|exu_div_new_2bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_2bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_2bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2189
exu_div_new_2bit_fullshortq.fir
View File

File diff suppressed because it is too large Load Diff

935
exu_div_new_2bit_fullshortq.v
View File

@ -1,935 +0,0 @@
module exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 655:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 655:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 655:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 655:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 655:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 655:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 655:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 655:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 655:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 655:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 655:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 655:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 655:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 655:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 655:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 655:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 655:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 655:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 655:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 655:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 655:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 655:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 655:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 655:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 655:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 655:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 655:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 655:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 655:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 655:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 655:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 657:25]
wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 658:76]
wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 658:76]
wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 658:76]
wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 658:76]
wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 658:76]
wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 658:76]
wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 658:76]
wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 658:76]
wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 658:76]
wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 658:76]
wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 658:76]
wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 658:76]
wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 658:76]
wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 658:76]
wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 658:76]
wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 658:76]
wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 658:76]
wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 658:76]
wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 658:76]
wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 658:76]
wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 657:44]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 659:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_div_new_2bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 584:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 584:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 587:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 587:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
wire _T = ~io_cancel; // @[exu_div_ctl.scala 488:35]
wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 488:33]
wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 489:35]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 489:48]
wire _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 489:80]
wire _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 489:96]
wire _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 489:65]
wire _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 489:133]
wire _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 489:181]
wire _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 489:150]
wire _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 489:218]
wire _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 489:250]
wire _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 489:235]
wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58]
reg [32:0] b_ff1; // @[Reg.scala 27:20]
wire [34:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58]
wire _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 493:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 493:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 495:37]
wire _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 495:60]
wire _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 495:46]
wire _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 495:71]
wire _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 495:69]
wire _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 495:87]
wire _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 495:85]
wire _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 495:95]
wire _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 495:106]
wire _T_36 = a_ff == 32'h0; // @[exu_div_ctl.scala 496:18]
wire _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 496:27]
wire _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 496:43]
wire _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 496:53]
wire _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 496:64]
wire smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 495:120]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 497:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 497:45]
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 498:43]
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 498:54]
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 498:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 498:82]
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 499:45]
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 499:72]
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 499:60]
wire finish = finish_raw & _T; // @[exu_div_ctl.scala 500:41]
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 501:40]
wire _T_52 = ~finish; // @[exu_div_ctl.scala 501:59]
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 501:57]
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 501:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 501:67]
wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 501:80]
wire [6:0] _T_905 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_906 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_908 = _T_905 - _T_906; // @[exu_div_ctl.scala 592:41]
wire [6:0] dw_shortq_raw = _T_908 + 7'h1; // @[exu_div_ctl.scala 592:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 593:19]
wire _T_914 = ~shortq[5]; // @[exu_div_ctl.scala 594:31]
wire _T_915 = valid_ff & _T_914; // @[exu_div_ctl.scala 594:29]
wire _T_917 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 594:58]
wire _T_918 = ~_T_917; // @[exu_div_ctl.scala 594:44]
wire _T_919 = _T_915 & _T_918; // @[exu_div_ctl.scala 594:42]
wire shortq_enable = _T_919 & _T; // @[exu_div_ctl.scala 594:74]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 501:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 501:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h2; // @[exu_div_ctl.scala 502:63]
reg [3:0] _T_935; // @[Reg.scala 27:20]
wire [4:0] shortq_shift_ff = {_T_935,1'h0}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = {2'h0,shortq_shift_ff[4:1],1'h0}; // @[Cat.scala 29:58]
wire [6:0] _T_68 = _T_63 + _T_66; // @[exu_div_ctl.scala 502:83]
wire [6:0] count_in = _T_60 & _T_68; // @[exu_div_ctl.scala 502:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 503:43]
wire _T_69 = ~shortq_enable_ff; // @[exu_div_ctl.scala 504:47]
wire a_shift = running_state & _T_69; // @[exu_div_ctl.scala 504:45]
wire [31:0] _T_71 = control_ff[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_72 = {_T_71,a_ff}; // @[Cat.scala 29:58]
wire [4:0] _T_74 = {shortq_shift_ff[4:1],1'h0}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_72}; // @[exu_div_ctl.scala 505:68]
wire [94:0] _T_75 = _GEN_11 << _T_74; // @[exu_div_ctl.scala 505:68]
wire _T_76 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 506:61]
wire _T_77 = ~_T_76; // @[exu_div_ctl.scala 506:42]
wire b_twos_comp = valid_ff & _T_77; // @[exu_div_ctl.scala 506:40]
wire _T_80 = ~valid_ff; // @[exu_div_ctl.scala 508:30]
wire _T_82 = _T_80 & _T_30; // @[exu_div_ctl.scala 508:40]
wire _T_84 = _T_82 & _T_76; // @[exu_div_ctl.scala 508:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_85 = ~by_zero_case_ff; // @[exu_div_ctl.scala 508:92]
wire twos_comp_q_sel = _T_84 & _T_85; // @[exu_div_ctl.scala 508:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 509:43]
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 510:54]
wire _T_87 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 511:40]
wire r_sign_sel = _T_87 & _T_28; // @[exu_div_ctl.scala 511:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [34:0] _T_116 = {r_ff[31],r_ff,a_ff[31:30]}; // @[Cat.scala 29:58]
wire [34:0] _T_118 = {b_ff[33:0],1'h0}; // @[Cat.scala 29:58]
wire [34:0] _T_120 = _T_116 + _T_118; // @[exu_div_ctl.scala 518:57]
wire [34:0] adder3_out = _T_120 + b_ff; // @[exu_div_ctl.scala 518:79]
wire _T_123 = ~adder3_out[34]; // @[exu_div_ctl.scala 519:24]
wire _T_124 = _T_123 ^ control_ff[2]; // @[exu_div_ctl.scala 519:40]
wire _T_126 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 519:75]
wire _T_127 = adder3_out == 35'h0; // @[exu_div_ctl.scala 519:98]
wire _T_128 = _T_126 & _T_127; // @[exu_div_ctl.scala 519:84]
wire _T_129 = _T_124 | _T_128; // @[exu_div_ctl.scala 519:60]
wire [33:0] _T_108 = {r_ff,a_ff[31:30]}; // @[Cat.scala 29:58]
wire [33:0] _T_110 = {b_ff[32:0],1'h0}; // @[Cat.scala 29:58]
wire [33:0] adder2_out = _T_108 + _T_110; // @[exu_div_ctl.scala 517:48]
wire _T_131 = ~adder2_out[33]; // @[exu_div_ctl.scala 520:6]
wire _T_132 = _T_131 ^ control_ff[2]; // @[exu_div_ctl.scala 520:22]
wire _T_135 = adder2_out == 34'h0; // @[exu_div_ctl.scala 520:80]
wire _T_136 = _T_126 & _T_135; // @[exu_div_ctl.scala 520:66]
wire _T_137 = _T_132 | _T_136; // @[exu_div_ctl.scala 520:42]
wire [32:0] _T_103 = {r_ff[30:0],a_ff[31:30]}; // @[Cat.scala 29:58]
wire [32:0] adder1_out = _T_103 + b_ff[32:0]; // @[exu_div_ctl.scala 516:48]
wire _T_139 = ~adder1_out[32]; // @[exu_div_ctl.scala 521:6]
wire _T_140 = _T_139 ^ control_ff[2]; // @[exu_div_ctl.scala 521:22]
wire _T_143 = adder1_out == 33'h0; // @[exu_div_ctl.scala 521:80]
wire _T_144 = _T_126 & _T_143; // @[exu_div_ctl.scala 521:66]
wire _T_145 = _T_140 | _T_144; // @[exu_div_ctl.scala 521:42]
wire [3:0] quotient_raw = {_T_129,_T_137,_T_145,1'h0}; // @[Cat.scala 29:58]
wire _T_151 = quotient_raw[3] | quotient_raw[2]; // @[exu_div_ctl.scala 522:41]
wire _T_154 = ~quotient_raw[2]; // @[exu_div_ctl.scala 522:82]
wire _T_156 = _T_154 & quotient_raw[1]; // @[exu_div_ctl.scala 522:99]
wire _T_157 = quotient_raw[3] | _T_156; // @[exu_div_ctl.scala 522:80]
wire [1:0] quotient_new = {_T_151,_T_157}; // @[Cat.scala 29:58]
wire _T_89 = quotient_new == 2'h0; // @[exu_div_ctl.scala 512:61]
wire _T_90 = running_state & _T_89; // @[exu_div_ctl.scala 512:45]
wire r_restore_sel = _T_90 & _T_69; // @[exu_div_ctl.scala 512:70]
wire _T_92 = quotient_new == 2'h1; // @[exu_div_ctl.scala 513:61]
wire _T_93 = running_state & _T_92; // @[exu_div_ctl.scala 513:45]
wire r_adder1_sel = _T_93 & _T_69; // @[exu_div_ctl.scala 513:70]
wire _T_95 = quotient_new == 2'h2; // @[exu_div_ctl.scala 514:61]
wire _T_96 = running_state & _T_95; // @[exu_div_ctl.scala 514:45]
wire r_adder2_sel = _T_96 & _T_69; // @[exu_div_ctl.scala 514:70]
wire _T_98 = quotient_new == 2'h3; // @[exu_div_ctl.scala 515:61]
wire _T_99 = running_state & _T_98; // @[exu_div_ctl.scala 515:45]
wire r_adder3_sel = _T_99 & _T_69; // @[exu_div_ctl.scala 515:70]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_160 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_161 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_160 | _T_161; // @[Mux.scala 27:72]
wire _T_165 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_167 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_169 = _T_165 ? _T_167 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_171 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_173 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_175 = _T_171 ? _T_173 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_177 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_179 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_181 = _T_177 ? _T_179 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_183 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_185 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_187 = _T_183 ? _T_185 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_189 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_191 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_193 = _T_189 ? _T_191 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_195 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_197 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_199 = _T_195 ? _T_197 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_201 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_203 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_205 = _T_201 ? _T_203 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_207 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_209 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_211 = _T_207 ? _T_209 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_213 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_215 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_217 = _T_213 ? _T_215 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_219 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_221 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_223 = _T_219 ? _T_221 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_225 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_227 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_229 = _T_225 ? _T_227 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_231 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_233 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_235 = _T_231 ? _T_233 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_237 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_239 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_241 = _T_237 ? _T_239 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_243 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_245 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_247 = _T_243 ? _T_245 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_249 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_251 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_253 = _T_249 ? _T_251 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_255 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_257 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_259 = _T_255 ? _T_257 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_261 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_263 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_265 = _T_261 ? _T_263 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_267 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_269 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_271 = _T_267 ? _T_269 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_273 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_275 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_277 = _T_273 ? _T_275 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_279 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_281 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_283 = _T_279 ? _T_281 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_285 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_287 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_289 = _T_285 ? _T_287 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_291 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_293 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_295 = _T_291 ? _T_293 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_297 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_299 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_301 = _T_297 ? _T_299 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_303 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_305 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_307 = _T_303 ? _T_305 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_309 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_311 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_313 = _T_309 ? _T_311 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_315 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_317 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_319 = _T_315 ? _T_317 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_321 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_323 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_325 = _T_321 ? _T_323 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_327 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_329 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_331 = _T_327 ? _T_329 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_333 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_335 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_337 = _T_333 ? _T_335 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_339 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_341 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_343 = _T_339 ? _T_341 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_345 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_347 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_349 = _T_345 ? _T_347 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_355 = {_T_205,_T_199,_T_193,_T_187,_T_181,_T_175,_T_169}; // @[lib.scala 430:14]
wire [14:0] _T_363 = {_T_253,_T_247,_T_241,_T_235,_T_229,_T_223,_T_217,_T_211,_T_355}; // @[lib.scala 430:14]
wire [7:0] _T_370 = {_T_301,_T_295,_T_289,_T_283,_T_277,_T_271,_T_265,_T_259}; // @[lib.scala 430:14]
wire [30:0] _T_379 = {_T_349,_T_343,_T_337,_T_331,_T_325,_T_319,_T_313,_T_307,_T_370,_T_363}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_379,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_381 = ~a_shift; // @[exu_div_ctl.scala 530:6]
wire _T_383 = _T_381 & _T_69; // @[exu_div_ctl.scala 530:15]
wire [31:0] _T_386 = {a_ff[29:0],2'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_75[63:0]; // @[exu_div_ctl.scala 505:28]
wire [31:0] _T_388 = _T_383 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_389 = a_shift ? _T_386 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_390 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_391 = _T_388 | _T_389; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_391 | _T_390; // @[Mux.scala 27:72]
wire _T_393 = ~b_twos_comp; // @[exu_div_ctl.scala 536:5]
wire _T_395 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 536:63]
wire [32:0] _T_397 = {_T_395,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_398 = ~control_ff[1]; // @[exu_div_ctl.scala 537:49]
wire [32:0] _T_400 = {_T_398,_T_379,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_401 = _T_393 ? _T_397 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_402 = b_twos_comp ? _T_400 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_401 | _T_402; // @[Mux.scala 27:72]
wire [31:0] _T_406 = {r_ff[29:0],a_ff[31:30]}; // @[Cat.scala 29:58]
wire [31:0] _T_411 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_412 = r_restore_sel ? _T_406 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_413 = r_adder1_sel ? adder1_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_414 = r_adder2_sel ? adder2_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_415 = r_adder3_sel ? adder3_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_416 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_417 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_418 = _T_411 | _T_412; // @[Mux.scala 27:72]
wire [31:0] _T_419 = _T_418 | _T_413; // @[Mux.scala 27:72]
wire [31:0] _T_420 = _T_419 | _T_414; // @[Mux.scala 27:72]
wire [31:0] _T_421 = _T_420 | _T_415; // @[Mux.scala 27:72]
wire [31:0] _T_422 = _T_421 | _T_416; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_422 | _T_417; // @[Mux.scala 27:72]
wire [31:0] _T_426 = {q_ff[29:0],_T_151,_T_157}; // @[Cat.scala 29:58]
wire _T_448 = ~b_ff[3]; // @[exu_div_ctl.scala 561:70]
wire _T_450 = ~b_ff[2]; // @[exu_div_ctl.scala 561:70]
wire _T_453 = _T_448 & _T_450; // @[exu_div_ctl.scala 561:95]
wire _T_452 = ~b_ff[1]; // @[exu_div_ctl.scala 561:70]
wire _T_454 = _T_453 & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_455 = a_ff[3] & _T_454; // @[exu_div_ctl.scala 562:11]
wire _T_462 = a_ff[3] & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_464 = ~b_ff[0]; // @[exu_div_ctl.scala 567:33]
wire _T_465 = _T_462 & _T_464; // @[exu_div_ctl.scala 567:31]
wire _T_475 = a_ff[2] & _T_454; // @[exu_div_ctl.scala 562:11]
wire _T_476 = _T_465 | _T_475; // @[exu_div_ctl.scala 567:42]
wire _T_479 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 560:95]
wire _T_485 = _T_479 & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_486 = _T_476 | _T_485; // @[exu_div_ctl.scala 567:75]
wire _T_493 = a_ff[2] & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_496 = _T_493 & _T_464; // @[exu_div_ctl.scala 569:31]
wire _T_506 = a_ff[1] & _T_454; // @[exu_div_ctl.scala 562:11]
wire _T_507 = _T_496 | _T_506; // @[exu_div_ctl.scala 569:42]
wire _T_513 = _T_448 & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_514 = a_ff[3] & _T_513; // @[exu_div_ctl.scala 562:11]
wire _T_517 = _T_514 & _T_464; // @[exu_div_ctl.scala 569:106]
wire _T_518 = _T_507 | _T_517; // @[exu_div_ctl.scala 569:78]
wire _T_521 = ~a_ff[2]; // @[exu_div_ctl.scala 560:70]
wire _T_522 = a_ff[3] & _T_521; // @[exu_div_ctl.scala 560:95]
wire _T_530 = _T_453 & b_ff[1]; // @[exu_div_ctl.scala 561:95]
wire _T_531 = _T_530 & b_ff[0]; // @[exu_div_ctl.scala 561:95]
wire _T_532 = _T_522 & _T_531; // @[exu_div_ctl.scala 562:11]
wire _T_533 = _T_518 | _T_532; // @[exu_div_ctl.scala 569:117]
wire _T_535 = ~a_ff[3]; // @[exu_div_ctl.scala 560:70]
wire _T_538 = _T_535 & a_ff[2]; // @[exu_div_ctl.scala 560:95]
wire _T_539 = _T_538 & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_545 = _T_539 & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_546 = _T_533 | _T_545; // @[exu_div_ctl.scala 570:44]
wire _T_552 = _T_479 & _T_448; // @[exu_div_ctl.scala 562:11]
wire _T_555 = _T_552 & _T_464; // @[exu_div_ctl.scala 570:107]
wire _T_556 = _T_546 | _T_555; // @[exu_div_ctl.scala 570:80]
wire _T_565 = _T_448 & b_ff[2]; // @[exu_div_ctl.scala 561:95]
wire _T_566 = _T_565 & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_567 = _T_479 & _T_566; // @[exu_div_ctl.scala 562:11]
wire _T_568 = _T_556 | _T_567; // @[exu_div_ctl.scala 570:119]
wire _T_571 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_577 = _T_571 & _T_513; // @[exu_div_ctl.scala 562:11]
wire _T_578 = _T_568 | _T_577; // @[exu_div_ctl.scala 571:44]
wire _T_583 = _T_479 & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_588 = _T_583 & _T_565; // @[exu_div_ctl.scala 562:11]
wire _T_589 = _T_578 | _T_588; // @[exu_div_ctl.scala 571:79]
wire _T_593 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_594 = _T_593 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_600 = _T_594 & _T_513; // @[exu_div_ctl.scala 562:11]
wire _T_606 = _T_522 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_611 = _T_448 & b_ff[1]; // @[exu_div_ctl.scala 561:95]
wire _T_612 = _T_611 & b_ff[0]; // @[exu_div_ctl.scala 561:95]
wire _T_613 = _T_606 & _T_612; // @[exu_div_ctl.scala 562:11]
wire _T_614 = _T_600 | _T_613; // @[exu_div_ctl.scala 573:45]
wire _T_621 = a_ff[2] & _T_513; // @[exu_div_ctl.scala 562:11]
wire _T_624 = _T_621 & _T_464; // @[exu_div_ctl.scala 573:114]
wire _T_625 = _T_614 | _T_624; // @[exu_div_ctl.scala 573:86]
wire _T_632 = a_ff[1] & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_635 = _T_632 & _T_464; // @[exu_div_ctl.scala 574:33]
wire _T_636 = _T_625 | _T_635; // @[exu_div_ctl.scala 573:129]
wire _T_646 = a_ff[0] & _T_454; // @[exu_div_ctl.scala 562:11]
wire _T_647 = _T_636 | _T_646; // @[exu_div_ctl.scala 574:47]
wire _T_652 = ~a_ff[1]; // @[exu_div_ctl.scala 560:70]
wire _T_654 = _T_538 & _T_652; // @[exu_div_ctl.scala 560:95]
wire _T_664 = _T_654 & _T_531; // @[exu_div_ctl.scala 562:11]
wire _T_665 = _T_647 | _T_664; // @[exu_div_ctl.scala 574:88]
wire _T_674 = _T_539 & _T_448; // @[exu_div_ctl.scala 562:11]
wire _T_677 = _T_674 & _T_464; // @[exu_div_ctl.scala 575:36]
wire _T_678 = _T_665 | _T_677; // @[exu_div_ctl.scala 574:131]
wire _T_684 = _T_450 & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_685 = a_ff[3] & _T_684; // @[exu_div_ctl.scala 562:11]
wire _T_688 = _T_685 & _T_464; // @[exu_div_ctl.scala 575:76]
wire _T_689 = _T_678 | _T_688; // @[exu_div_ctl.scala 575:47]
wire _T_699 = _T_565 & b_ff[1]; // @[exu_div_ctl.scala 561:95]
wire _T_700 = _T_522 & _T_699; // @[exu_div_ctl.scala 562:11]
wire _T_701 = _T_689 | _T_700; // @[exu_div_ctl.scala 575:88]
wire _T_715 = _T_539 & _T_566; // @[exu_div_ctl.scala 562:11]
wire _T_716 = _T_701 | _T_715; // @[exu_div_ctl.scala 575:131]
wire _T_722 = _T_538 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_728 = _T_722 & _T_513; // @[exu_div_ctl.scala 562:11]
wire _T_729 = _T_716 | _T_728; // @[exu_div_ctl.scala 576:47]
wire _T_736 = _T_522 & _T_652; // @[exu_div_ctl.scala 560:95]
wire _T_742 = _T_565 & b_ff[0]; // @[exu_div_ctl.scala 561:95]
wire _T_743 = _T_736 & _T_742; // @[exu_div_ctl.scala 562:11]
wire _T_744 = _T_729 | _T_743; // @[exu_div_ctl.scala 576:88]
wire _T_749 = _T_521 & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_750 = _T_749 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_756 = _T_750 & _T_453; // @[exu_div_ctl.scala 562:11]
wire _T_757 = _T_744 | _T_756; // @[exu_div_ctl.scala 576:131]
wire _T_763 = _T_479 & _T_452; // @[exu_div_ctl.scala 562:11]
wire _T_766 = _T_763 & _T_464; // @[exu_div_ctl.scala 577:75]
wire _T_767 = _T_757 | _T_766; // @[exu_div_ctl.scala 577:47]
wire _T_775 = _T_539 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_780 = _T_775 & _T_565; // @[exu_div_ctl.scala 562:11]
wire _T_781 = _T_767 | _T_780; // @[exu_div_ctl.scala 577:88]
wire _T_788 = b_ff[3] & _T_450; // @[exu_div_ctl.scala 561:95]
wire _T_789 = _T_479 & _T_788; // @[exu_div_ctl.scala 562:11]
wire _T_790 = _T_781 | _T_789; // @[exu_div_ctl.scala 577:131]
wire _T_800 = _T_788 & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_801 = _T_571 & _T_800; // @[exu_div_ctl.scala 562:11]
wire _T_802 = _T_790 | _T_801; // @[exu_div_ctl.scala 578:47]
wire _T_805 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_811 = _T_805 & _T_684; // @[exu_div_ctl.scala 562:11]
wire _T_812 = _T_802 | _T_811; // @[exu_div_ctl.scala 578:88]
wire _T_816 = a_ff[3] & _T_652; // @[exu_div_ctl.scala 560:95]
wire _T_824 = _T_699 & b_ff[0]; // @[exu_div_ctl.scala 561:95]
wire _T_825 = _T_816 & _T_824; // @[exu_div_ctl.scala 562:11]
wire _T_826 = _T_812 | _T_825; // @[exu_div_ctl.scala 578:131]
wire _T_833 = _T_583 & b_ff[3]; // @[exu_div_ctl.scala 562:11]
wire _T_836 = _T_833 & _T_464; // @[exu_div_ctl.scala 579:77]
wire _T_837 = _T_826 | _T_836; // @[exu_div_ctl.scala 579:47]
wire _T_846 = b_ff[3] & _T_452; // @[exu_div_ctl.scala 561:95]
wire _T_847 = _T_583 & _T_846; // @[exu_div_ctl.scala 562:11]
wire _T_848 = _T_837 | _T_847; // @[exu_div_ctl.scala 579:88]
wire _T_853 = _T_479 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_858 = _T_853 & _T_846; // @[exu_div_ctl.scala 562:11]
wire _T_859 = _T_848 | _T_858; // @[exu_div_ctl.scala 579:131]
wire _T_865 = _T_522 & a_ff[1]; // @[exu_div_ctl.scala 560:95]
wire _T_870 = _T_865 & _T_611; // @[exu_div_ctl.scala 562:11]
wire _T_871 = _T_859 | _T_870; // @[exu_div_ctl.scala 580:47]
wire _T_876 = _T_571 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_879 = _T_876 & _T_450; // @[exu_div_ctl.scala 562:11]
wire _T_880 = _T_871 | _T_879; // @[exu_div_ctl.scala 580:88]
wire _T_887 = _T_583 & a_ff[0]; // @[exu_div_ctl.scala 560:95]
wire _T_889 = _T_887 & b_ff[3]; // @[exu_div_ctl.scala 562:11]
wire _T_890 = _T_880 | _T_889; // @[exu_div_ctl.scala 580:131]
wire _T_896 = _T_571 & _T_450; // @[exu_div_ctl.scala 562:11]
wire _T_899 = _T_896 & _T_464; // @[exu_div_ctl.scala 581:74]
wire _T_900 = _T_890 | _T_899; // @[exu_div_ctl.scala 581:47]
wire [31:0] _T_427 = {28'h0,_T_455,_T_486,_T_589,_T_900}; // @[Cat.scala 29:58]
wire [31:0] _T_429 = _T_80 ? _T_426 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_430 = smallnum_case ? _T_427 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_431 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_432 = _T_429 | _T_430; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_432 | _T_431; // @[Mux.scala 27:72]
wire _T_437 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 555:16]
wire _T_438 = _T_30 & _T_437; // @[exu_div_ctl.scala 555:14]
wire [31:0] _T_440 = _T_438 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_441 = control_ff[0] ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_442 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_443 = _T_440 | _T_441; // @[Mux.scala 27:72]
wire [4:0] _T_925 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 595:57]
wire [4:0] shortq_shift = _T_58 ? 5'h0 : _T_925; // @[exu_div_ctl.scala 595:25]
exu_div_cls a_enc ( // @[exu_div_ctl.scala 584:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
exu_div_cls b_enc ( // @[exu_div_ctl.scala 587:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_443 | _T_442; // @[exu_div_ctl.scala 554:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 553:16]
assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 585:20]
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 588:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff1 = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
_T_935 = _RAND_7[3:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff1 = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
_T_935 = 4'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff1 <= 33'h0;
end else if (b_enable) begin
b_ff1 <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_935 <= 4'h0;
end else if (misc_enable) begin
_T_935 <= shortq_shift[4:1];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

30
exu_div_new_3bit_fullshortq.anno.json
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@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_3bit_fullshortq|exu_div_new_3bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_3bit_fullshortq|exu_div_new_3bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_3bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_3bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2436
exu_div_new_3bit_fullshortq.fir
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1083
exu_div_new_3bit_fullshortq.v
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30
exu_div_new_4bit_fullshortq.anno.json
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@ -1,30 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_4bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_4bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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exu_div_new_4bit_fullshortq.v
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111
lsu_addrcheck.anno.json
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@ -1,111 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_fir_nondccm_access_error_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_fast_int",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_misaligned_fault_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_store",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_load",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_by",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_half",
"~lsu_addrcheck|lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_access_fault_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_rs1_region_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_exc_mscause_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_misaligned_fault_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_dma",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_addr_external_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_store",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_load",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_by",
"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_word",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_half",
"~lsu_addrcheck|lsu_addrcheck>io_rs1_region_d",
"~lsu_addrcheck|lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_in_dccm_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_addr_in_pic_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_addrcheck|lsu_addrcheck>io_fir_dccm_access_error_d",
"sources":[
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_bits_fast_int",
"~lsu_addrcheck|lsu_addrcheck>io_lsu_pkt_d_valid",
"~lsu_addrcheck|lsu_addrcheck>io_start_addr_d",
"~lsu_addrcheck|lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_addrcheck"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

253
lsu_addrcheck.fir
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@ -1,253 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_addrcheck :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]

193
lsu_addrcheck.v
View File

@ -1,193 +0,0 @@
module lsu_addrcheck(
input clock,
input reset,
input io_lsu_c2_m_clk,
input [31:0] io_start_addr_d,
input [31:0] io_end_addr_d,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_d_bits_fast_int,
input io_lsu_pkt_d_bits_by,
input io_lsu_pkt_d_bits_half,
input io_lsu_pkt_d_bits_word,
input io_lsu_pkt_d_bits_dword,
input io_lsu_pkt_d_bits_load,
input io_lsu_pkt_d_bits_store,
input io_lsu_pkt_d_bits_unsign,
input io_lsu_pkt_d_bits_dma,
input io_lsu_pkt_d_bits_store_data_bypass_d,
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
input io_lsu_pkt_d_bits_store_data_bypass_m,
input [31:0] io_dec_tlu_mrac_ff,
input [3:0] io_rs1_region_d,
input [31:0] io_rs1_d,
output io_is_sideeffects_m,
output io_addr_in_dccm_d,
output io_addr_in_pic_d,
output io_addr_external_d,
output io_access_fault_d,
output io_misaligned_fault_d,
output [3:0] io_exc_mscause_d,
output io_fir_dccm_access_error_d,
output io_fir_nondccm_access_error_d,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45]
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60]
wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55]
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91]
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50]
wire _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121]
wire _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62]
wire _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60]
wire _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137]
wire _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185]
wire is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158]
wire _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80]
wire _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56]
wire _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138]
wire _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116]
wire _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90]
wire is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148]
wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56]
wire _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88]
wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56]
wire _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88]
wire _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153]
wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56]
wire _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88]
wire _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153]
wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56]
wire _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88]
wire _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153]
wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57]
wire _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89]
wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58]
wire _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90]
wire _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154]
wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58]
wire _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90]
wire _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155]
wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58]
wire _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90]
wire _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155]
wire non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7]
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57]
wire _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76]
wire _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92]
wire _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90]
wire picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51]
wire _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87]
wire _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64]
wire _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62]
wire _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57]
wire _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36]
wire _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34]
wire _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112]
wire _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29]
wire _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85]
wire _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29]
wire unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85]
wire _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33]
wire _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64]
wire mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62]
wire _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49]
wire _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70]
wire _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92]
wire _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118]
wire _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141]
wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164]
wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120]
wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80]
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35]
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61]
wire _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59]
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57]
wire _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90]
wire _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57]
wire _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113]
wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80]
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39]
wire _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66]
wire _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64]
wire _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120]
wire _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118]
wire _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88]
wire _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142]
wire _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66]
wire _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36]
wire _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95]
reg _T_201; // @[lsu_addrcheck.scala 121:60]
assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50]
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32]
assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32]
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30]
assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21]
assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25]
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21]
assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31]
assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_201 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_201 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
if (reset) begin
_T_201 <= 1'h0;
end else begin
_T_201 <= _T_32 & _T_33;
end
end
endmodule

183
lsu_bus_buffer.anno.json
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@ -1,183 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data",
"sources":[
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_bus_buffer.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_bus_buffer"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

6552
lsu_bus_buffer.fir
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4626
lsu_bus_buffer.v
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113
lsu_bus_intf.anno.json
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@ -1,113 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_store_data_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load",
"~lsu_bus_intf|lsu_bus_intf>io_flush_m_up",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid",
"~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d",
"~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m",
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_bus_intf.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_bus_intf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

7199
lsu_bus_intf.fir
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5244
lsu_bus_intf.v
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43
lsu_clkdomain.anno.json
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@ -1,43 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_busm_clken",
"sources":[
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_empty_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_obuf_c1_clken",
"sources":[
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_pend_any",
"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_clkdomain.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_clkdomain"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

443
lsu_clkdomain.fir
View File

@ -1,443 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_clkdomain :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_11 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_clkdomain :
input clock : Clock
input reset : AsyncReset
output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36]
wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36]
wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36]
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47]
node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65]
node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51]
node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70]
node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47]
node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66]
node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47]
node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66]
node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49]
node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76]
node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49]
node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76]
node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55]
node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77]
node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107]
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49]
node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62]
node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80]
node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99]
io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30]
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32]
node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61]
node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79]
node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103]
node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48]
node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69]
node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90]
node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114]
node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112]
node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145]
node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143]
node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169]
node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50]
node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72]
node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25]
node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54]
node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72]
node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91]
io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21]
reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62]
_T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62]
lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26]
reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67]
_T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67]
lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26]
reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
_T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:60]
inst rvclkhdr of rvclkhdr @[lib.scala 352:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 353:17]
rvclkhdr.io.en <= _T_29 @[lib.scala 354:16]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:60]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 352:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_1.io.en <= _T_30 @[lib.scala 354:16]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:60]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_2.io.en <= _T_31 @[lib.scala 354:16]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:60]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_3.io.en <= _T_32 @[lib.scala 354:16]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:66]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:22]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_4.io.en <= _T_33 @[lib.scala 354:16]
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:66]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:22]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_5.io.en <= _T_34 @[lib.scala 354:16]
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:64]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_6.io.en <= _T_35 @[lib.scala 354:16]
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_7.io.en <= _T_36 @[lib.scala 354:16]
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66]
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 352:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_9.io.en <= _T_38 @[lib.scala 354:16]
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 343:22]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 344:17]
rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63]
inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 352:22]
rvclkhdr_11.clock <= clock
rvclkhdr_11.reset <= reset
rvclkhdr_11.io.clk <= clock @[lib.scala 353:17]
rvclkhdr_11.io.en <= _T_40 @[lib.scala 354:16]
rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]

348
lsu_clkdomain.v
View File

@ -1,348 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module lsu_clkdomain(
input clock,
input reset,
input io_active_clk,
input io_clk_override,
input io_dec_tlu_force_halt,
input io_dma_dccm_req,
input io_ldst_stbuf_reqvld_r,
input io_stbuf_reqvld_any,
input io_stbuf_reqvld_flushed_any,
input io_lsu_busreq_r,
input io_lsu_bus_buffer_pend_any,
input io_lsu_bus_buffer_empty_any,
input io_lsu_stbuf_empty_any,
input io_lsu_bus_clk_en,
input io_lsu_p_valid,
input io_lsu_p_bits_fast_int,
input io_lsu_p_bits_by,
input io_lsu_p_bits_half,
input io_lsu_p_bits_word,
input io_lsu_p_bits_dword,
input io_lsu_p_bits_load,
input io_lsu_p_bits_store,
input io_lsu_p_bits_unsign,
input io_lsu_p_bits_dma,
input io_lsu_p_bits_store_data_bypass_d,
input io_lsu_p_bits_load_ldst_bypass_d,
input io_lsu_p_bits_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_d_bits_fast_int,
input io_lsu_pkt_d_bits_by,
input io_lsu_pkt_d_bits_half,
input io_lsu_pkt_d_bits_word,
input io_lsu_pkt_d_bits_dword,
input io_lsu_pkt_d_bits_load,
input io_lsu_pkt_d_bits_store,
input io_lsu_pkt_d_bits_unsign,
input io_lsu_pkt_d_bits_dma,
input io_lsu_pkt_d_bits_store_data_bypass_d,
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
input io_lsu_pkt_d_bits_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
output io_lsu_bus_obuf_c1_clken,
output io_lsu_busm_clken,
output io_lsu_c1_m_clk,
output io_lsu_c1_r_clk,
output io_lsu_c2_m_clk,
output io_lsu_c2_r_clk,
output io_lsu_store_c1_m_clk,
output io_lsu_store_c1_r_clk,
output io_lsu_stbuf_c1_clk,
output io_lsu_bus_obuf_c1_clk,
output io_lsu_bus_ibuf_c1_clk,
output io_lsu_bus_buf_c1_clk,
output io_lsu_busm_clk,
output io_lsu_free_c2_clk,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_io_en; // @[lib.scala 352:22]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_1_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_1_io_en; // @[lib.scala 352:22]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_2_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_2_io_en; // @[lib.scala 352:22]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_3_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_3_io_en; // @[lib.scala 352:22]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_4_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_4_io_en; // @[lib.scala 352:22]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_5_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_5_io_en; // @[lib.scala 352:22]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_6_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_6_io_en; // @[lib.scala 352:22]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_7_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_7_io_en; // @[lib.scala 352:22]
wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_8_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_8_io_en; // @[lib.scala 343:22]
wire rvclkhdr_9_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_9_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_9_io_en; // @[lib.scala 352:22]
wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_10_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_10_io_en; // @[lib.scala 343:22]
wire rvclkhdr_11_io_l1clk; // @[lib.scala 352:22]
wire rvclkhdr_11_io_clk; // @[lib.scala 352:22]
wire rvclkhdr_11_io_en; // @[lib.scala 352:22]
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 64:47]
wire lsu_c1_m_clken = _T | io_clk_override; // @[lsu_clkdomain.scala 64:65]
reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 84:67]
wire _T_1 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 65:51]
wire lsu_c1_r_clken = _T_1 | io_clk_override; // @[lsu_clkdomain.scala 65:70]
wire _T_2 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 67:47]
reg lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 85:67]
wire _T_3 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 68:47]
wire _T_4 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[lsu_clkdomain.scala 70:49]
wire _T_5 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[lsu_clkdomain.scala 71:49]
wire _T_6 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[lsu_clkdomain.scala 72:55]
wire _T_7 = _T_6 | io_stbuf_reqvld_flushed_any; // @[lsu_clkdomain.scala 72:77]
wire _T_8 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:62]
wire _T_9 = _T_8 | io_clk_override; // @[lsu_clkdomain.scala 74:80]
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32]
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61]
wire _T_13 = _T_12 | io_dec_tlu_force_halt; // @[lsu_clkdomain.scala 75:79]
wire _T_14 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[lsu_clkdomain.scala 77:48]
wire _T_15 = _T_14 | io_lsu_pkt_m_valid; // @[lsu_clkdomain.scala 77:69]
wire _T_16 = _T_15 | io_lsu_pkt_r_valid; // @[lsu_clkdomain.scala 77:90]
wire _T_18 = _T_16 | _T_11; // @[lsu_clkdomain.scala 77:112]
wire _T_19 = ~io_lsu_stbuf_empty_any; // @[lsu_clkdomain.scala 77:145]
wire _T_20 = _T_18 | _T_19; // @[lsu_clkdomain.scala 77:143]
wire lsu_free_c1_clken = _T_20 | io_clk_override; // @[lsu_clkdomain.scala 77:169]
reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 82:62]
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
rvclkhdr rvclkhdr ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22]
.io_l1clk(rvclkhdr_10_io_l1clk),
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
rvclkhdr rvclkhdr_11 ( // @[lib.scala 352:22]
.io_l1clk(rvclkhdr_11_io_l1clk),
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en)
);
assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30]
assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21]
assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[lsu_clkdomain.scala 87:26]
assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[lsu_clkdomain.scala 88:26]
assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[lsu_clkdomain.scala 89:26]
assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[lsu_clkdomain.scala 90:26]
assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 91:26]
assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 92:26]
assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 93:26]
assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 95:26]
assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 94:26]
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 96:26]
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 97:26]
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 98:26]
assign rvclkhdr_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_8_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 354:16]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_10_io_en = io_lsu_busm_clken; // @[lib.scala 345:16]
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 353:17]
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 354:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
lsu_c1_m_clken_q = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
lsu_c1_r_clken_q = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
lsu_free_c1_clken_q = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
lsu_c1_m_clken_q = 1'h0;
end
if (reset) begin
lsu_c1_r_clken_q = 1'h0;
end
if (reset) begin
lsu_free_c1_clken_q = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
lsu_c1_m_clken_q <= 1'h0;
end else begin
lsu_c1_m_clken_q <= _T | io_clk_override;
end
end
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
lsu_c1_r_clken_q <= 1'h0;
end else begin
lsu_c1_r_clken_q <= _T_1 | io_clk_override;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
lsu_free_c1_clken_q <= 1'h0;
end else begin
lsu_free_c1_clken_q <= _T_20 | io_clk_override;
end
end
endmodule

386
lsu_dccm_ctl.anno.json
View File

@ -1,386 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rtag",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_mem_tag_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_dma",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_dccm_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2253
lsu_dccm_ctl.fir
View File

File diff suppressed because it is too large Load Diff

1293
lsu_dccm_ctl.v
View File

File diff suppressed because it is too large Load Diff

339
lsu_ecc.anno.json
View File

@ -1,339 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_single_ecc_error_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_single_ecc_error_hi_r",
"~lsu_ecc|lsu_ecc>io_single_ecc_error_lo_r",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_ecc_hi",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_hi_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_hi",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_double_ecc_error_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_ecc_lo_r_ff",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_single_ecc_error_hi_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_lo_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_single_ecc_error_lo_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_hi_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_lo_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_ecc_hi_r_ff",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_hi_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_hi",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_sec_data_hi_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_single_ecc_error_m",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_ecc_lo",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_stbuf_ecc_any",
"sources":[
"~lsu_ecc|lsu_ecc>io_sec_data_lo_r_ff",
"~lsu_ecc|lsu_ecc>io_ld_single_ecc_error_r_ff",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wdata_lo",
"~lsu_ecc|lsu_ecc>io_stbuf_data_any",
"~lsu_ecc|lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_ecc|lsu_ecc>io_lsu_double_ecc_error_r",
"sources":[
"~lsu_ecc|lsu_ecc>io_dec_tlu_core_ecc_disable",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_dma",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_hi_m",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_data_ecc_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_r",
"~lsu_ecc|lsu_ecc>io_lsu_dccm_rden_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_hi_m",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_r",
"~lsu_ecc|lsu_ecc>io_addr_in_dccm_m",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_r",
"~lsu_ecc|lsu_ecc>io_dccm_rdata_lo_m",
"~lsu_ecc|lsu_ecc>io_lsu_addr_r",
"~lsu_ecc|lsu_ecc>io_end_addr_r",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_valid",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_valid",
"~lsu_ecc|lsu_ecc>io_lsu_addr_m",
"~lsu_ecc|lsu_ecc>io_end_addr_m",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_r_bits_store",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_load",
"~lsu_ecc|lsu_ecc>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_ecc.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_ecc"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1670
lsu_ecc.fir
View File

File diff suppressed because it is too large Load Diff

674
lsu_ecc.v
View File

@ -1,674 +0,0 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
endmodule
module lsu_ecc(
input clock,
input reset,
input io_lsu_c2_r_clk,
input io_clk_override,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_lsu_pkt_r_bits_fast_int,
input io_lsu_pkt_r_bits_by,
input io_lsu_pkt_r_bits_half,
input io_lsu_pkt_r_bits_word,
input io_lsu_pkt_r_bits_dword,
input io_lsu_pkt_r_bits_load,
input io_lsu_pkt_r_bits_store,
input io_lsu_pkt_r_bits_unsign,
input io_lsu_pkt_r_bits_dma,
input io_lsu_pkt_r_bits_store_data_bypass_d,
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
input io_lsu_pkt_r_bits_store_data_bypass_m,
input [31:0] io_stbuf_data_any,
input io_dec_tlu_core_ecc_disable,
input io_lsu_dccm_rden_r,
input io_addr_in_dccm_r,
input [15:0] io_lsu_addr_r,
input [15:0] io_end_addr_r,
input [15:0] io_lsu_addr_m,
input [15:0] io_end_addr_m,
input [31:0] io_dccm_rdata_hi_r,
input [31:0] io_dccm_rdata_lo_r,
input [31:0] io_dccm_rdata_hi_m,
input [31:0] io_dccm_rdata_lo_m,
input [6:0] io_dccm_data_ecc_hi_r,
input [6:0] io_dccm_data_ecc_lo_r,
input [6:0] io_dccm_data_ecc_hi_m,
input [6:0] io_dccm_data_ecc_lo_m,
input io_ld_single_ecc_error_r,
input io_ld_single_ecc_error_r_ff,
input io_lsu_dccm_rden_m,
input io_addr_in_dccm_m,
input io_dma_dccm_wen,
input [31:0] io_dma_dccm_wdata_lo,
input [31:0] io_dma_dccm_wdata_hi,
input io_scan_mode,
output [31:0] io_sec_data_hi_r,
output [31:0] io_sec_data_lo_r,
output [31:0] io_sec_data_hi_m,
output [31:0] io_sec_data_lo_m,
output [31:0] io_sec_data_hi_r_ff,
output [31:0] io_sec_data_lo_r_ff,
output [6:0] io_dma_dccm_wdata_ecc_hi,
output [6:0] io_dma_dccm_wdata_ecc_lo,
output [6:0] io_stbuf_ecc_any,
output [6:0] io_sec_data_ecc_hi_r_ff,
output [6:0] io_sec_data_ecc_lo_r_ff,
output io_single_ecc_error_hi_r,
output io_single_ecc_error_lo_r,
output io_lsu_single_ecc_error_r,
output io_lsu_double_ecc_error_r,
output io_lsu_single_ecc_error_m,
output io_lsu_double_ecc_error_m
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_io_en; // @[lib.scala 368:23]
wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_en; // @[lib.scala 368:23]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_en; // @[lib.scala 368:23]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_en; // @[lib.scala 368:23]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30]
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44]
wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35]
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76]
wire _T_107 = ^_T_106; // @[lib.scala 193:83]
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71]
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103]
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103]
wire _T_124 = ^_T_123; // @[lib.scala 193:110]
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98]
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130]
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130]
wire _T_141 = ^_T_140; // @[lib.scala 193:137]
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125]
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157]
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157]
wire _T_161 = ^_T_160; // @[lib.scala 193:164]
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152]
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184]
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184]
wire _T_181 = ^_T_180; // @[lib.scala 193:191]
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179]
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211]
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211]
wire _T_201 = ^_T_200; // @[lib.scala 193:218]
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206]
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44]
wire _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48]
wire _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65]
wire _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39]
wire _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92]
wire is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112]
wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39]
wire _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48]
wire _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33]
wire is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73]
wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32]
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53]
wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55]
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53]
wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41]
wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41]
wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41]
wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41]
wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41]
wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41]
wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41]
wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41]
wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41]
wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41]
wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41]
wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41]
wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41]
wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41]
wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41]
wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41]
wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41]
wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41]
wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41]
wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41]
wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41]
wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41]
wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41]
wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41]
wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41]
wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41]
wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41]
wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41]
wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41]
wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41]
wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41]
wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41]
wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41]
wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41]
wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41]
wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41]
wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41]
wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41]
wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41]
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69]
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69]
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69]
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69]
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76]
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31]
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30]
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44]
wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35]
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76]
wire _T_485 = ^_T_484; // @[lib.scala 193:83]
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71]
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103]
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103]
wire _T_502 = ^_T_501; // @[lib.scala 193:110]
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98]
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130]
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130]
wire _T_519 = ^_T_518; // @[lib.scala 193:137]
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125]
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157]
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157]
wire _T_539 = ^_T_538; // @[lib.scala 193:164]
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152]
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184]
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184]
wire _T_559 = ^_T_558; // @[lib.scala 193:191]
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179]
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211]
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211]
wire _T_579 = ^_T_578; // @[lib.scala 193:218]
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206]
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44]
wire is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33]
wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32]
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53]
wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55]
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53]
wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41]
wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41]
wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41]
wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41]
wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41]
wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41]
wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41]
wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41]
wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41]
wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41]
wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41]
wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41]
wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41]
wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41]
wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41]
wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41]
wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41]
wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41]
wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41]
wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41]
wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41]
wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41]
wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41]
wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41]
wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41]
wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41]
wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41]
wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41]
wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41]
wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41]
wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41]
wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41]
wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41]
wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41]
wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41]
wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41]
wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41]
wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41]
wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41]
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69]
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69]
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69]
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69]
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69]
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76]
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31]
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
wire [31:0] _T_1159 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 148:87]
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1159; // @[lsu_ecc.scala 148:27]
wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74]
wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74]
wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74]
wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74]
wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74]
wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74]
wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74]
wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74]
wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74]
wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74]
wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74]
wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74]
wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74]
wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74]
wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74]
wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74]
wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74]
wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74]
wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74]
wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74]
wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74]
wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74]
wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74]
wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74]
wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74]
wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74]
wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74]
wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74]
wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74]
wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74]
wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74]
wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74]
wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74]
wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74]
wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74]
wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74]
wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74]
wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74]
wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74]
wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58]
wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13]
wire _T_936 = ^_T_934; // @[lib.scala 127:23]
wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18]
wire [31:0] _T_1163 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : 32'h0; // @[lsu_ecc.scala 149:87]
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1163; // @[lsu_ecc.scala 149:27]
wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74]
wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74]
wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74]
wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74]
wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74]
wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74]
wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74]
wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74]
wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74]
wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74]
wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74]
wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74]
wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74]
wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74]
wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74]
wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74]
wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74]
wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74]
wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74]
wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74]
wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74]
wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74]
wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74]
wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74]
wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74]
wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74]
wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74]
wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74]
wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74]
wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74]
wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74]
wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74]
wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74]
wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74]
wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74]
wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74]
wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74]
wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74]
wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74]
wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58]
wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13]
wire _T_1118 = ^_T_1116; // @[lib.scala 127:23]
wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18]
reg _T_1149; // @[lsu_ecc.scala 140:72]
reg _T_1150; // @[lsu_ecc.scala 141:72]
reg _T_1151; // @[lsu_ecc.scala 142:72]
reg _T_1152; // @[lsu_ecc.scala 143:72]
reg [31:0] _T_1154; // @[lib.scala 374:16]
reg [31:0] _T_1156; // @[lib.scala 374:16]
reg [31:0] _T_1166; // @[lib.scala 374:16]
reg [31:0] _T_1168; // @[lib.scala 374:16]
rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34]
assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34]
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27]
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27]
assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23]
assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23]
assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28]
assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[lsu_ecc.scala 154:28]
assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28]
assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28]
assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28]
assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62]
assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62]
assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62]
assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62]
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33]
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33]
assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1149 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
_T_1150 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
_T_1151 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
_T_1152 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_1154 = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
_T_1156 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
_T_1166 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
_T_1168 = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1149 = 1'h0;
end
if (reset) begin
_T_1150 = 1'h0;
end
if (reset) begin
_T_1151 = 1'h0;
end
if (reset) begin
_T_1152 = 1'h0;
end
if (reset) begin
_T_1154 = 32'h0;
end
if (reset) begin
_T_1156 = 32'h0;
end
if (reset) begin
_T_1166 = 32'h0;
end
if (reset) begin
_T_1168 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1149 <= 1'h0;
end else begin
_T_1149 <= io_lsu_single_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1150 <= 1'h0;
end else begin
_T_1150 <= io_lsu_double_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1151 <= 1'h0;
end else begin
_T_1151 <= _T_588 & _T_586[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1152 <= 1'h0;
end else begin
_T_1152 <= _T_210 & _T_208[6];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
_T_1154 <= 32'h0;
end else begin
_T_1154 <= io_sec_data_hi_m;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
_T_1156 <= 32'h0;
end else begin
_T_1156 <= io_sec_data_lo_m;
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
_T_1166 <= 32'h0;
end else begin
_T_1166 <= io_sec_data_hi_r;
end
end
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
_T_1168 <= 32'h0;
end else begin
_T_1168 <= io_sec_data_lo_r;
end
end
endmodule

333
lsu_lsc_ctl.anno.json
View File

@ -1,333 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_lsc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

958
lsu_lsc_ctl.fir
View File

@ -1,958 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_lsc_ctl :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 370:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 370:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire end_addr_pre_m : UInt<29>
end_addr_pre_m <= UInt<29>("h00")
wire end_addr_pre_r : UInt<29>
end_addr_pre_r <= UInt<29>("h00")
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29]
node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 101:51]
node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39]
node _T_10 = tail(_T_9, 1) @[lib.scala 92:39]
node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50]
node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46]
node _T_14 = not(_T_13) @[lib.scala 93:33]
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58]
node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
node _T_20 = not(_T_19) @[lib.scala 94:18]
node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34]
node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30]
node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54]
node _T_27 = tail(_T_26, 1) @[lib.scala 94:54]
node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41]
node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72]
node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34]
node _T_32 = not(_T_31) @[lib.scala 95:31]
node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29]
node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54]
node _T_38 = tail(_T_37, 1) @[lib.scala 95:54]
node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41]
node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61]
node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22]
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_44 = and(_T_43, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_47 = and(_T_46, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
node _T_48 = or(_T_44, _T_47) @[lsu_lsc_ctl.scala 109:70]
node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_51 = and(_T_50, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
node addr_offset_d = or(_T_48, _T_51) @[lsu_lsc_ctl.scala 110:52]
node _T_52 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
node _T_53 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_56 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58]
node _T_58 = add(_T_54, _T_57) @[lsu_lsc_ctl.scala 113:60]
node end_addr_offset_d = tail(_T_58, 1) @[lsu_lsc_ctl.scala 113:60]
node _T_59 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
node _T_60 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_63 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58]
node _T_65 = add(_T_59, _T_64) @[lsu_lsc_ctl.scala 114:39]
node full_end_addr_d = tail(_T_65, 1) @[lsu_lsc_ctl.scala 114:39]
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
addrcheck.clock <= clock
addrcheck.reset <= reset
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
node _T_66 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
addrcheck.io.rs1_region_d <= _T_66 @[lsu_lsc_ctl.scala 126:42]
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
wire exc_mscause_r : UInt<4>
exc_mscause_r <= UInt<4>("h00")
wire fir_dccm_access_error_r : UInt<1>
fir_dccm_access_error_r <= UInt<1>("h00")
wire fir_nondccm_access_error_r : UInt<1>
fir_nondccm_access_error_r <= UInt<1>("h00")
wire access_fault_r : UInt<1>
access_fault_r <= UInt<1>("h00")
wire misaligned_fault_r : UInt<1>
misaligned_fault_r <= UInt<1>("h00")
wire lsu_fir_error_m : UInt<2>
lsu_fir_error_m <= UInt<2>("h00")
wire fir_dccm_access_error_m : UInt<1>
fir_dccm_access_error_m <= UInt<1>("h00")
wire fir_nondccm_access_error_m : UInt<1>
fir_nondccm_access_error_m <= UInt<1>("h00")
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
_T_67 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
fir_dccm_access_error_m <= _T_67 @[lsu_lsc_ctl.scala 152:38]
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
_T_68 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
fir_nondccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 153:38]
node _T_69 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
io.lsu_exc_m <= _T_69 @[lsu_lsc_ctl.scala 155:16]
node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[lsu_lsc_ctl.scala 156:62]
node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
node _T_73 = and(_T_71, _T_72) @[lsu_lsc_ctl.scala 156:92]
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
io.lsu_single_ecc_error_incr <= _T_74 @[lsu_lsc_ctl.scala 156:32]
node _T_75 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 178:46]
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 178:67]
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 178:96]
node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:119]
node _T_79 = and(_T_77, _T_78) @[lsu_lsc_ctl.scala 178:117]
node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:144]
node _T_81 = and(_T_79, _T_80) @[lsu_lsc_ctl.scala 178:142]
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:174]
node _T_83 = and(_T_81, _T_82) @[lsu_lsc_ctl.scala 178:172]
lsu_error_pkt_m.valid <= _T_83 @[lsu_lsc_ctl.scala 178:27]
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:75]
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[lsu_lsc_ctl.scala 179:73]
node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:101]
node _T_87 = and(_T_85, _T_86) @[lsu_lsc_ctl.scala 179:99]
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[lsu_lsc_ctl.scala 179:43]
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 180:43]
node _T_88 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 181:46]
lsu_error_pkt_m.bits.exc_type <= _T_88 @[lsu_lsc_ctl.scala 181:43]
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:80]
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[lsu_lsc_ctl.scala 182:78]
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:102]
node _T_92 = and(_T_90, _T_91) @[lsu_lsc_ctl.scala 182:100]
node _T_93 = eq(_T_92, UInt<1>("h01")) @[lsu_lsc_ctl.scala 182:118]
node _T_94 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 182:149]
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[lsu_lsc_ctl.scala 182:49]
lsu_error_pkt_m.bits.mscause <= _T_95 @[lsu_lsc_ctl.scala 182:43]
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 183:59]
lsu_error_pkt_m.bits.addr <= _T_96 @[lsu_lsc_ctl.scala 183:43]
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:72]
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:117]
node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 184:166]
node _T_100 = bits(_T_99, 0, 0) @[lsu_lsc_ctl.scala 184:195]
node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 184:137]
node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[lsu_lsc_ctl.scala 184:92]
node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[lsu_lsc_ctl.scala 184:44]
lsu_fir_error_m <= _T_103 @[lsu_lsc_ctl.scala 184:38]
node _T_104 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 185:73]
node _T_105 = or(_T_104, io.clk_override) @[lsu_lsc_ctl.scala 185:113]
node _T_106 = bits(_T_105, 0, 0) @[lib.scala 8:44]
node _T_107 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 387:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 389:18]
rvclkhdr.io.en <= _T_106 @[lib.scala 390:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 391:24]
wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 393:33]
_T_108.bits.addr <= UInt<32>("h00") @[lib.scala 393:33]
_T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 393:33]
_T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 393:33]
_T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 393:33]
_T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 393:33]
_T_108.valid <= UInt<1>("h00") @[lib.scala 393:33]
reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 393:16]
_T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 393:16]
_T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 393:16]
_T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 393:16]
_T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 393:16]
_T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 393:16]
_T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 393:16]
io.lsu_error_pkt_r.bits.addr <= _T_109.bits.addr @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.mscause <= _T_109.bits.mscause @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.exc_type <= _T_109.bits.exc_type @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.inst_type <= _T_109.bits.inst_type @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_109.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:24]
io.lsu_error_pkt_r.valid <= _T_109.valid @[lsu_lsc_ctl.scala 185:24]
reg _T_110 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:83]
_T_110 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 186:83]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110 @[lsu_lsc_ctl.scala 186:46]
reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67]
_T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67]
io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30]
reg _T_112 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:75]
_T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:75]
io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 188:38]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27]
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27]
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27]
node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30]
dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 196:27]
node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62]
dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 197:27]
node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62]
dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 198:27]
node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62]
dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 199:27]
node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56]
node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62]
dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 200:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
lsu_ld_datafn_corr_r <= UInt<32>("h00")
wire lsu_ld_datafn_m : UInt<32>
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50]
node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.stack <= _T_123.bits.stack @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20]
node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64]
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 213:61]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45]
node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 213:43]
node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90]
io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 213:24]
node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 214:65]
node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 214:47]
lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 214:24]
node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68]
node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 215:65]
node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49]
node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 215:47]
lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 215:24]
wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
_T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
_T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.stack <= _T_138.bits.stack @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 217:28]
wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65]
_T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65]
_T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.stack <= _T_140.bits.stack @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 218:28]
reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
_T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65]
io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 219:28]
reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65]
_T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65]
io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 220:28]
node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59]
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100]
node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58]
node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 222:66]
node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63]
node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91]
node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 223:34]
node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73]
node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95]
node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114]
node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 224:34]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
_T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 227:24]
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
_T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 228:24]
node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27]
node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
_T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114]
node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17]
node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27]
node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
reg _T_164 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
_T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114]
node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17]
node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_1.io.en <= _T_169 @[lib.scala 380:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_171 <= _T_166 @[lib.scala 383:16]
end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 231:18]
node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69]
node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_2.io.en <= _T_175 @[lib.scala 380:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_177 <= _T_172 @[lib.scala 383:16]
end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 232:18]
reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
_T_178 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
io.addr_in_dccm_m <= _T_178 @[lsu_lsc_ctl.scala 233:24]
reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
_T_179 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
io.addr_in_dccm_r <= _T_179 @[lsu_lsc_ctl.scala 234:24]
reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
_T_180 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
io.addr_in_pic_m <= _T_180 @[lsu_lsc_ctl.scala 235:24]
reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
_T_181 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
io.addr_in_pic_r <= _T_181 @[lsu_lsc_ctl.scala 236:24]
reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
_T_182 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
io.addr_external_m <= _T_182 @[lsu_lsc_ctl.scala 237:24]
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
node _T_183 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
node _T_184 = bits(_T_183, 0, 0) @[lib.scala 8:44]
node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_3.io.en <= _T_184 @[lib.scala 380:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16]
node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 242:28]
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 246:41]
node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 246:94]
node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 246:108]
io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 246:19]
node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15]
node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 247:59]
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
node _T_199 = mux(_T_198, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 247:89]
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 247:29]
node _T_201 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 268:53]
node _T_202 = mux(_T_201, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 268:33]
lsu_ld_datafn_m <= _T_202 @[lsu_lsc_ctl.scala 268:27]
node _T_203 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 269:49]
node _T_204 = mux(_T_203, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 269:33]
lsu_ld_datafn_corr_r <= _T_204 @[lsu_lsc_ctl.scala 269:27]
node _T_205 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 270:66]
node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_208 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 270:125]
node _T_209 = cat(UInt<24>("h00"), _T_208) @[Cat.scala 29:58]
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 270:94]
node _T_211 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 271:43]
node _T_212 = bits(_T_211, 0, 0) @[Bitwise.scala 72:15]
node _T_213 = mux(_T_212, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_214 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 271:102]
node _T_215 = cat(UInt<16>("h00"), _T_214) @[Cat.scala 29:58]
node _T_216 = and(_T_213, _T_215) @[lsu_lsc_ctl.scala 271:71]
node _T_217 = or(_T_210, _T_216) @[lsu_lsc_ctl.scala 270:133]
node _T_218 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
node _T_219 = and(_T_218, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 272:43]
node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 72:15]
node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_222 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 272:102]
node _T_223 = bits(_T_222, 0, 0) @[Bitwise.scala 72:15]
node _T_224 = mux(_T_223, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_225 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 272:125]
node _T_226 = cat(_T_224, _T_225) @[Cat.scala 29:58]
node _T_227 = and(_T_221, _T_226) @[lsu_lsc_ctl.scala 272:71]
node _T_228 = or(_T_217, _T_227) @[lsu_lsc_ctl.scala 271:114]
node _T_229 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 273:17]
node _T_230 = and(_T_229, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 273:43]
node _T_231 = bits(_T_230, 0, 0) @[Bitwise.scala 72:15]
node _T_232 = mux(_T_231, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_233 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 273:101]
node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 72:15]
node _T_235 = mux(_T_234, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_236 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 273:125]
node _T_237 = cat(_T_235, _T_236) @[Cat.scala 29:58]
node _T_238 = and(_T_232, _T_237) @[lsu_lsc_ctl.scala 273:71]
node _T_239 = or(_T_228, _T_238) @[lsu_lsc_ctl.scala 272:134]
node _T_240 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_242 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 274:60]
node _T_243 = and(_T_241, _T_242) @[lsu_lsc_ctl.scala 274:43]
node _T_244 = or(_T_239, _T_243) @[lsu_lsc_ctl.scala 273:134]
io.lsu_result_m <= _T_244 @[lsu_lsc_ctl.scala 270:27]
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 275:66]
node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_248 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 275:130]
node _T_249 = cat(UInt<24>("h00"), _T_248) @[Cat.scala 29:58]
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 275:94]
node _T_251 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 276:43]
node _T_252 = bits(_T_251, 0, 0) @[Bitwise.scala 72:15]
node _T_253 = mux(_T_252, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_254 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 276:107]
node _T_255 = cat(UInt<16>("h00"), _T_254) @[Cat.scala 29:58]
node _T_256 = and(_T_253, _T_255) @[lsu_lsc_ctl.scala 276:71]
node _T_257 = or(_T_250, _T_256) @[lsu_lsc_ctl.scala 275:138]
node _T_258 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
node _T_259 = and(_T_258, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 277:43]
node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15]
node _T_261 = mux(_T_260, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_262 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 277:107]
node _T_263 = bits(_T_262, 0, 0) @[Bitwise.scala 72:15]
node _T_264 = mux(_T_263, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_265 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 277:135]
node _T_266 = cat(_T_264, _T_265) @[Cat.scala 29:58]
node _T_267 = and(_T_261, _T_266) @[lsu_lsc_ctl.scala 277:71]
node _T_268 = or(_T_257, _T_267) @[lsu_lsc_ctl.scala 276:119]
node _T_269 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
node _T_270 = and(_T_269, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 278:43]
node _T_271 = bits(_T_270, 0, 0) @[Bitwise.scala 72:15]
node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_273 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 278:106]
node _T_274 = bits(_T_273, 0, 0) @[Bitwise.scala 72:15]
node _T_275 = mux(_T_274, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_276 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 278:135]
node _T_277 = cat(_T_275, _T_276) @[Cat.scala 29:58]
node _T_278 = and(_T_272, _T_277) @[lsu_lsc_ctl.scala 278:71]
node _T_279 = or(_T_268, _T_278) @[lsu_lsc_ctl.scala 277:144]
node _T_280 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_281 = mux(_T_280, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_282 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 279:65]
node _T_283 = and(_T_281, _T_282) @[lsu_lsc_ctl.scala 279:43]
node _T_284 = or(_T_279, _T_283) @[lsu_lsc_ctl.scala 278:144]
io.lsu_result_corr_r <= _T_284 @[lsu_lsc_ctl.scala 275:27]

1446
lsu_lsc_ctl.v
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142
lsu_stbuf.anno.json
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@ -1,142 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwddata_lo_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_data_lo_r",
"~lsu_stbuf|lsu_stbuf>io_store_data_hi_r",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwddata_hi_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_data_lo_r",
"~lsu_stbuf|lsu_stbuf>io_store_data_hi_r",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_r",
"~lsu_stbuf|lsu_stbuf>io_end_addr_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dword",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_word",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_by",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_stbuf_reqvld_any",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_store",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_valid",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_end_addr_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_lsu_stbuf_full_any",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_dec_lsu_valid_raw_d",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_d",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_r",
"~lsu_stbuf|lsu_stbuf>io_ldst_dual_m",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_store",
"~lsu_stbuf|lsu_stbuf>io_addr_in_dccm_m",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_dma",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_valid",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_m_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_stbuf|lsu_stbuf>io_ldst_stbuf_reqvld_r",
"sources":[
"~lsu_stbuf|lsu_stbuf>io_store_stbuf_reqvld_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_commit_r",
"~lsu_stbuf|lsu_stbuf>io_lsu_pkt_r_bits_dma"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_stbuf.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_stbuf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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lsu_stbuf.fir
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lsu_stbuf.v
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lsu_trigger.anno.json
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@ -1,56 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_trigger|lsu_trigger>io_lsu_trigger_match_m",
"sources":[
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_valid",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_store",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_store",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_dma",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_load",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_store",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_load",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_select",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_m",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_0_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_1_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_3_match_pkt",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_tdata2",
"~lsu_trigger|lsu_trigger>io_trigger_pkt_any_2_match_pkt",
"~lsu_trigger|lsu_trigger>io_lsu_addr_m",
"~lsu_trigger|lsu_trigger>io_store_data_m",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_word",
"~lsu_trigger|lsu_trigger>io_lsu_pkt_m_bits_half"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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lsu_trigger.fir
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lsu_trigger.v
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@ -1,645 +0,0 @@
module lsu_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_pkt,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_pkt,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_pkt,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_pkt,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_m_bits_fast_int,
input io_lsu_pkt_m_bits_by,
input io_lsu_pkt_m_bits_half,
input io_lsu_pkt_m_bits_word,
input io_lsu_pkt_m_bits_dword,
input io_lsu_pkt_m_bits_load,
input io_lsu_pkt_m_bits_store,
input io_lsu_pkt_m_bits_unsign,
input io_lsu_pkt_m_bits_dma,
input io_lsu_pkt_m_bits_store_data_bypass_d,
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
input io_lsu_pkt_m_bits_store_data_bypass_m,
input [31:0] io_lsu_addr_m,
input [31:0] io_store_data_m,
output [3:0] io_lsu_trigger_match_m
);
wire _T = io_trigger_pkt_any_0_m | io_trigger_pkt_any_1_m; // @[lsu_trigger.scala 16:73]
wire _T_1 = _T | io_trigger_pkt_any_2_m; // @[lsu_trigger.scala 16:73]
wire trigger_enable = _T_1 | io_trigger_pkt_any_3_m; // @[lsu_trigger.scala 16:73]
wire [15:0] _T_4 = io_lsu_pkt_m_bits_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
wire [15:0] _T_6 = _T_4 & io_store_data_m[31:16]; // @[lsu_trigger.scala 17:66]
wire _T_7 = io_lsu_pkt_m_bits_half | io_lsu_pkt_m_bits_word; // @[lsu_trigger.scala 17:124]
wire [7:0] _T_9 = _T_7 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_11 = _T_9 & io_store_data_m[15:8]; // @[lsu_trigger.scala 17:151]
wire [31:0] store_data_trigger_m = {_T_6,_T_11,io_store_data_m[7:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_15 = trigger_enable ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] ldst_addr_trigger_m = io_lsu_addr_m & _T_15; // @[lsu_trigger.scala 18:43]
wire _T_17 = ~io_trigger_pkt_any_0_select; // @[lsu_trigger.scala 19:53]
wire _T_18 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_20 = _T_17 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_18 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_0 = _T_20 | _T_21; // @[Mux.scala 27:72]
wire _T_24 = ~io_trigger_pkt_any_1_select; // @[lsu_trigger.scala 19:53]
wire _T_25 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_27 = _T_24 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_28 = _T_25 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_1 = _T_27 | _T_28; // @[Mux.scala 27:72]
wire _T_31 = ~io_trigger_pkt_any_2_select; // @[lsu_trigger.scala 19:53]
wire _T_32 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_34 = _T_31 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_35 = _T_32 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_2 = _T_34 | _T_35; // @[Mux.scala 27:72]
wire _T_38 = ~io_trigger_pkt_any_3_select; // @[lsu_trigger.scala 19:53]
wire _T_39 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[lsu_trigger.scala 19:143]
wire [31:0] _T_41 = _T_38 ? ldst_addr_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_42 = _T_39 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lsu_match_data_3 = _T_41 | _T_42; // @[Mux.scala 27:72]
wire _T_44 = ~io_lsu_pkt_m_bits_dma; // @[lsu_trigger.scala 20:70]
wire _T_45 = io_lsu_pkt_m_valid & _T_44; // @[lsu_trigger.scala 20:68]
wire _T_46 = _T_45 & trigger_enable; // @[lsu_trigger.scala 20:93]
wire _T_47 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_48 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_50 = _T_48 & _T_17; // @[lsu_trigger.scala 21:58]
wire _T_51 = _T_47 | _T_50; // @[lsu_trigger.scala 20:168]
wire _T_52 = _T_46 & _T_51; // @[lsu_trigger.scala 20:110]
wire _T_55 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45]
wire _T_56 = ~_T_55; // @[lib.scala 101:39]
wire _T_57 = io_trigger_pkt_any_0_match_pkt & _T_56; // @[lib.scala 101:37]
wire _T_60 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52]
wire _T_61 = _T_57 | _T_60; // @[lib.scala 102:41]
wire _T_63 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36]
wire _T_64 = _T_63 & _T_57; // @[lib.scala 104:41]
wire _T_67 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78]
wire _T_68 = _T_64 | _T_67; // @[lib.scala 104:23]
wire _T_70 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_71 = _T_70 & _T_57; // @[lib.scala 104:41]
wire _T_74 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78]
wire _T_75 = _T_71 | _T_74; // @[lib.scala 104:23]
wire _T_77 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_78 = _T_77 & _T_57; // @[lib.scala 104:41]
wire _T_81 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78]
wire _T_82 = _T_78 | _T_81; // @[lib.scala 104:23]
wire _T_84 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_85 = _T_84 & _T_57; // @[lib.scala 104:41]
wire _T_88 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78]
wire _T_89 = _T_85 | _T_88; // @[lib.scala 104:23]
wire _T_91 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_92 = _T_91 & _T_57; // @[lib.scala 104:41]
wire _T_95 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78]
wire _T_96 = _T_92 | _T_95; // @[lib.scala 104:23]
wire _T_98 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_99 = _T_98 & _T_57; // @[lib.scala 104:41]
wire _T_102 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78]
wire _T_103 = _T_99 | _T_102; // @[lib.scala 104:23]
wire _T_105 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_106 = _T_105 & _T_57; // @[lib.scala 104:41]
wire _T_109 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78]
wire _T_110 = _T_106 | _T_109; // @[lib.scala 104:23]
wire _T_112 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_113 = _T_112 & _T_57; // @[lib.scala 104:41]
wire _T_116 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78]
wire _T_117 = _T_113 | _T_116; // @[lib.scala 104:23]
wire _T_119 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_120 = _T_119 & _T_57; // @[lib.scala 104:41]
wire _T_123 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78]
wire _T_124 = _T_120 | _T_123; // @[lib.scala 104:23]
wire _T_126 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_127 = _T_126 & _T_57; // @[lib.scala 104:41]
wire _T_130 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78]
wire _T_131 = _T_127 | _T_130; // @[lib.scala 104:23]
wire _T_133 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_134 = _T_133 & _T_57; // @[lib.scala 104:41]
wire _T_137 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78]
wire _T_138 = _T_134 | _T_137; // @[lib.scala 104:23]
wire _T_140 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_141 = _T_140 & _T_57; // @[lib.scala 104:41]
wire _T_144 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78]
wire _T_145 = _T_141 | _T_144; // @[lib.scala 104:23]
wire _T_147 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_148 = _T_147 & _T_57; // @[lib.scala 104:41]
wire _T_151 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78]
wire _T_152 = _T_148 | _T_151; // @[lib.scala 104:23]
wire _T_154 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_155 = _T_154 & _T_57; // @[lib.scala 104:41]
wire _T_158 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78]
wire _T_159 = _T_155 | _T_158; // @[lib.scala 104:23]
wire _T_161 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_162 = _T_161 & _T_57; // @[lib.scala 104:41]
wire _T_165 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78]
wire _T_166 = _T_162 | _T_165; // @[lib.scala 104:23]
wire _T_168 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_169 = _T_168 & _T_57; // @[lib.scala 104:41]
wire _T_172 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78]
wire _T_173 = _T_169 | _T_172; // @[lib.scala 104:23]
wire _T_175 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_176 = _T_175 & _T_57; // @[lib.scala 104:41]
wire _T_179 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78]
wire _T_180 = _T_176 | _T_179; // @[lib.scala 104:23]
wire _T_182 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_183 = _T_182 & _T_57; // @[lib.scala 104:41]
wire _T_186 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78]
wire _T_187 = _T_183 | _T_186; // @[lib.scala 104:23]
wire _T_189 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_190 = _T_189 & _T_57; // @[lib.scala 104:41]
wire _T_193 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78]
wire _T_194 = _T_190 | _T_193; // @[lib.scala 104:23]
wire _T_196 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_197 = _T_196 & _T_57; // @[lib.scala 104:41]
wire _T_200 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78]
wire _T_201 = _T_197 | _T_200; // @[lib.scala 104:23]
wire _T_203 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_204 = _T_203 & _T_57; // @[lib.scala 104:41]
wire _T_207 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78]
wire _T_208 = _T_204 | _T_207; // @[lib.scala 104:23]
wire _T_210 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_211 = _T_210 & _T_57; // @[lib.scala 104:41]
wire _T_214 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78]
wire _T_215 = _T_211 | _T_214; // @[lib.scala 104:23]
wire _T_217 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_218 = _T_217 & _T_57; // @[lib.scala 104:41]
wire _T_221 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78]
wire _T_222 = _T_218 | _T_221; // @[lib.scala 104:23]
wire _T_224 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_225 = _T_224 & _T_57; // @[lib.scala 104:41]
wire _T_228 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78]
wire _T_229 = _T_225 | _T_228; // @[lib.scala 104:23]
wire _T_231 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_232 = _T_231 & _T_57; // @[lib.scala 104:41]
wire _T_235 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78]
wire _T_236 = _T_232 | _T_235; // @[lib.scala 104:23]
wire _T_238 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_239 = _T_238 & _T_57; // @[lib.scala 104:41]
wire _T_242 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78]
wire _T_243 = _T_239 | _T_242; // @[lib.scala 104:23]
wire _T_245 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_246 = _T_245 & _T_57; // @[lib.scala 104:41]
wire _T_249 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78]
wire _T_250 = _T_246 | _T_249; // @[lib.scala 104:23]
wire _T_252 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_253 = _T_252 & _T_57; // @[lib.scala 104:41]
wire _T_256 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78]
wire _T_257 = _T_253 | _T_256; // @[lib.scala 104:23]
wire _T_259 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_260 = _T_259 & _T_57; // @[lib.scala 104:41]
wire _T_263 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78]
wire _T_264 = _T_260 | _T_263; // @[lib.scala 104:23]
wire _T_266 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_267 = _T_266 & _T_57; // @[lib.scala 104:41]
wire _T_270 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78]
wire _T_271 = _T_267 | _T_270; // @[lib.scala 104:23]
wire _T_273 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_274 = _T_273 & _T_57; // @[lib.scala 104:41]
wire _T_277 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78]
wire _T_278 = _T_274 | _T_277; // @[lib.scala 104:23]
wire [7:0] _T_285 = {_T_110,_T_103,_T_96,_T_89,_T_82,_T_75,_T_68,_T_61}; // @[lib.scala 105:14]
wire [15:0] _T_293 = {_T_166,_T_159,_T_152,_T_145,_T_138,_T_131,_T_124,_T_117,_T_285}; // @[lib.scala 105:14]
wire [7:0] _T_300 = {_T_222,_T_215,_T_208,_T_201,_T_194,_T_187,_T_180,_T_173}; // @[lib.scala 105:14]
wire [31:0] _T_309 = {_T_278,_T_271,_T_264,_T_257,_T_250,_T_243,_T_236,_T_229,_T_300,_T_293}; // @[lib.scala 105:14]
wire _T_310 = &_T_309; // @[lib.scala 105:25]
wire _T_311 = _T_52 & _T_310; // @[lsu_trigger.scala 21:92]
wire _T_315 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_316 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_318 = _T_316 & _T_24; // @[lsu_trigger.scala 21:58]
wire _T_319 = _T_315 | _T_318; // @[lsu_trigger.scala 20:168]
wire _T_320 = _T_46 & _T_319; // @[lsu_trigger.scala 20:110]
wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45]
wire _T_324 = ~_T_323; // @[lib.scala 101:39]
wire _T_325 = io_trigger_pkt_any_1_match_pkt & _T_324; // @[lib.scala 101:37]
wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52]
wire _T_329 = _T_325 | _T_328; // @[lib.scala 102:41]
wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36]
wire _T_332 = _T_331 & _T_325; // @[lib.scala 104:41]
wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78]
wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23]
wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_339 = _T_338 & _T_325; // @[lib.scala 104:41]
wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78]
wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23]
wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_346 = _T_345 & _T_325; // @[lib.scala 104:41]
wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78]
wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23]
wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_353 = _T_352 & _T_325; // @[lib.scala 104:41]
wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78]
wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23]
wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_360 = _T_359 & _T_325; // @[lib.scala 104:41]
wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78]
wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23]
wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_367 = _T_366 & _T_325; // @[lib.scala 104:41]
wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78]
wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23]
wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_374 = _T_373 & _T_325; // @[lib.scala 104:41]
wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78]
wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23]
wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_381 = _T_380 & _T_325; // @[lib.scala 104:41]
wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78]
wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23]
wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_388 = _T_387 & _T_325; // @[lib.scala 104:41]
wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78]
wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23]
wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_395 = _T_394 & _T_325; // @[lib.scala 104:41]
wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78]
wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23]
wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_402 = _T_401 & _T_325; // @[lib.scala 104:41]
wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78]
wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23]
wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_409 = _T_408 & _T_325; // @[lib.scala 104:41]
wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78]
wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23]
wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_416 = _T_415 & _T_325; // @[lib.scala 104:41]
wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78]
wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23]
wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_423 = _T_422 & _T_325; // @[lib.scala 104:41]
wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78]
wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23]
wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_430 = _T_429 & _T_325; // @[lib.scala 104:41]
wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78]
wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23]
wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_437 = _T_436 & _T_325; // @[lib.scala 104:41]
wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78]
wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23]
wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_444 = _T_443 & _T_325; // @[lib.scala 104:41]
wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78]
wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23]
wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_451 = _T_450 & _T_325; // @[lib.scala 104:41]
wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78]
wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23]
wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_458 = _T_457 & _T_325; // @[lib.scala 104:41]
wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78]
wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23]
wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_465 = _T_464 & _T_325; // @[lib.scala 104:41]
wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78]
wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23]
wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_472 = _T_471 & _T_325; // @[lib.scala 104:41]
wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78]
wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23]
wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_479 = _T_478 & _T_325; // @[lib.scala 104:41]
wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78]
wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23]
wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_486 = _T_485 & _T_325; // @[lib.scala 104:41]
wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78]
wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23]
wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_493 = _T_492 & _T_325; // @[lib.scala 104:41]
wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78]
wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23]
wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_500 = _T_499 & _T_325; // @[lib.scala 104:41]
wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78]
wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23]
wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_507 = _T_506 & _T_325; // @[lib.scala 104:41]
wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78]
wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23]
wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_514 = _T_513 & _T_325; // @[lib.scala 104:41]
wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78]
wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23]
wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_521 = _T_520 & _T_325; // @[lib.scala 104:41]
wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78]
wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23]
wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_528 = _T_527 & _T_325; // @[lib.scala 104:41]
wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78]
wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23]
wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_535 = _T_534 & _T_325; // @[lib.scala 104:41]
wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78]
wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23]
wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_542 = _T_541 & _T_325; // @[lib.scala 104:41]
wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78]
wire _T_546 = _T_542 | _T_545; // @[lib.scala 104:23]
wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[lib.scala 105:14]
wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[lib.scala 105:14]
wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[lib.scala 105:14]
wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[lib.scala 105:14]
wire _T_578 = &_T_577; // @[lib.scala 105:25]
wire _T_579 = _T_320 & _T_578; // @[lsu_trigger.scala 21:92]
wire _T_583 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_586 = _T_584 & _T_31; // @[lsu_trigger.scala 21:58]
wire _T_587 = _T_583 | _T_586; // @[lsu_trigger.scala 20:168]
wire _T_588 = _T_46 & _T_587; // @[lsu_trigger.scala 20:110]
wire _T_591 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45]
wire _T_592 = ~_T_591; // @[lib.scala 101:39]
wire _T_593 = io_trigger_pkt_any_2_match_pkt & _T_592; // @[lib.scala 101:37]
wire _T_596 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52]
wire _T_597 = _T_593 | _T_596; // @[lib.scala 102:41]
wire _T_599 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36]
wire _T_600 = _T_599 & _T_593; // @[lib.scala 104:41]
wire _T_603 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78]
wire _T_604 = _T_600 | _T_603; // @[lib.scala 104:23]
wire _T_606 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_607 = _T_606 & _T_593; // @[lib.scala 104:41]
wire _T_610 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78]
wire _T_611 = _T_607 | _T_610; // @[lib.scala 104:23]
wire _T_613 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_614 = _T_613 & _T_593; // @[lib.scala 104:41]
wire _T_617 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78]
wire _T_618 = _T_614 | _T_617; // @[lib.scala 104:23]
wire _T_620 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_621 = _T_620 & _T_593; // @[lib.scala 104:41]
wire _T_624 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78]
wire _T_625 = _T_621 | _T_624; // @[lib.scala 104:23]
wire _T_627 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_628 = _T_627 & _T_593; // @[lib.scala 104:41]
wire _T_631 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78]
wire _T_632 = _T_628 | _T_631; // @[lib.scala 104:23]
wire _T_634 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_635 = _T_634 & _T_593; // @[lib.scala 104:41]
wire _T_638 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78]
wire _T_639 = _T_635 | _T_638; // @[lib.scala 104:23]
wire _T_641 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_642 = _T_641 & _T_593; // @[lib.scala 104:41]
wire _T_645 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78]
wire _T_646 = _T_642 | _T_645; // @[lib.scala 104:23]
wire _T_648 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_649 = _T_648 & _T_593; // @[lib.scala 104:41]
wire _T_652 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78]
wire _T_653 = _T_649 | _T_652; // @[lib.scala 104:23]
wire _T_655 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_656 = _T_655 & _T_593; // @[lib.scala 104:41]
wire _T_659 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78]
wire _T_660 = _T_656 | _T_659; // @[lib.scala 104:23]
wire _T_662 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_663 = _T_662 & _T_593; // @[lib.scala 104:41]
wire _T_666 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78]
wire _T_667 = _T_663 | _T_666; // @[lib.scala 104:23]
wire _T_669 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_670 = _T_669 & _T_593; // @[lib.scala 104:41]
wire _T_673 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78]
wire _T_674 = _T_670 | _T_673; // @[lib.scala 104:23]
wire _T_676 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_677 = _T_676 & _T_593; // @[lib.scala 104:41]
wire _T_680 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78]
wire _T_681 = _T_677 | _T_680; // @[lib.scala 104:23]
wire _T_683 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_684 = _T_683 & _T_593; // @[lib.scala 104:41]
wire _T_687 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78]
wire _T_688 = _T_684 | _T_687; // @[lib.scala 104:23]
wire _T_690 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_691 = _T_690 & _T_593; // @[lib.scala 104:41]
wire _T_694 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78]
wire _T_695 = _T_691 | _T_694; // @[lib.scala 104:23]
wire _T_697 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_698 = _T_697 & _T_593; // @[lib.scala 104:41]
wire _T_701 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78]
wire _T_702 = _T_698 | _T_701; // @[lib.scala 104:23]
wire _T_704 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_705 = _T_704 & _T_593; // @[lib.scala 104:41]
wire _T_708 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78]
wire _T_709 = _T_705 | _T_708; // @[lib.scala 104:23]
wire _T_711 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_712 = _T_711 & _T_593; // @[lib.scala 104:41]
wire _T_715 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78]
wire _T_716 = _T_712 | _T_715; // @[lib.scala 104:23]
wire _T_718 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_719 = _T_718 & _T_593; // @[lib.scala 104:41]
wire _T_722 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78]
wire _T_723 = _T_719 | _T_722; // @[lib.scala 104:23]
wire _T_725 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_726 = _T_725 & _T_593; // @[lib.scala 104:41]
wire _T_729 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78]
wire _T_730 = _T_726 | _T_729; // @[lib.scala 104:23]
wire _T_732 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_733 = _T_732 & _T_593; // @[lib.scala 104:41]
wire _T_736 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78]
wire _T_737 = _T_733 | _T_736; // @[lib.scala 104:23]
wire _T_739 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_740 = _T_739 & _T_593; // @[lib.scala 104:41]
wire _T_743 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78]
wire _T_744 = _T_740 | _T_743; // @[lib.scala 104:23]
wire _T_746 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_747 = _T_746 & _T_593; // @[lib.scala 104:41]
wire _T_750 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78]
wire _T_751 = _T_747 | _T_750; // @[lib.scala 104:23]
wire _T_753 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_754 = _T_753 & _T_593; // @[lib.scala 104:41]
wire _T_757 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78]
wire _T_758 = _T_754 | _T_757; // @[lib.scala 104:23]
wire _T_760 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_761 = _T_760 & _T_593; // @[lib.scala 104:41]
wire _T_764 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78]
wire _T_765 = _T_761 | _T_764; // @[lib.scala 104:23]
wire _T_767 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_768 = _T_767 & _T_593; // @[lib.scala 104:41]
wire _T_771 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78]
wire _T_772 = _T_768 | _T_771; // @[lib.scala 104:23]
wire _T_774 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_775 = _T_774 & _T_593; // @[lib.scala 104:41]
wire _T_778 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78]
wire _T_779 = _T_775 | _T_778; // @[lib.scala 104:23]
wire _T_781 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_782 = _T_781 & _T_593; // @[lib.scala 104:41]
wire _T_785 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78]
wire _T_786 = _T_782 | _T_785; // @[lib.scala 104:23]
wire _T_788 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_789 = _T_788 & _T_593; // @[lib.scala 104:41]
wire _T_792 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78]
wire _T_793 = _T_789 | _T_792; // @[lib.scala 104:23]
wire _T_795 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_796 = _T_795 & _T_593; // @[lib.scala 104:41]
wire _T_799 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78]
wire _T_800 = _T_796 | _T_799; // @[lib.scala 104:23]
wire _T_802 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_803 = _T_802 & _T_593; // @[lib.scala 104:41]
wire _T_806 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78]
wire _T_807 = _T_803 | _T_806; // @[lib.scala 104:23]
wire _T_809 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_810 = _T_809 & _T_593; // @[lib.scala 104:41]
wire _T_813 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78]
wire _T_814 = _T_810 | _T_813; // @[lib.scala 104:23]
wire [7:0] _T_821 = {_T_646,_T_639,_T_632,_T_625,_T_618,_T_611,_T_604,_T_597}; // @[lib.scala 105:14]
wire [15:0] _T_829 = {_T_702,_T_695,_T_688,_T_681,_T_674,_T_667,_T_660,_T_653,_T_821}; // @[lib.scala 105:14]
wire [7:0] _T_836 = {_T_758,_T_751,_T_744,_T_737,_T_730,_T_723,_T_716,_T_709}; // @[lib.scala 105:14]
wire [31:0] _T_845 = {_T_814,_T_807,_T_800,_T_793,_T_786,_T_779,_T_772,_T_765,_T_836,_T_829}; // @[lib.scala 105:14]
wire _T_846 = &_T_845; // @[lib.scala 105:25]
wire _T_847 = _T_588 & _T_846; // @[lsu_trigger.scala 21:92]
wire _T_851 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 20:142]
wire _T_852 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 21:33]
wire _T_854 = _T_852 & _T_38; // @[lsu_trigger.scala 21:58]
wire _T_855 = _T_851 | _T_854; // @[lsu_trigger.scala 20:168]
wire _T_856 = _T_46 & _T_855; // @[lsu_trigger.scala 20:110]
wire _T_859 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45]
wire _T_860 = ~_T_859; // @[lib.scala 101:39]
wire _T_861 = io_trigger_pkt_any_3_match_pkt & _T_860; // @[lib.scala 101:37]
wire _T_864 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52]
wire _T_865 = _T_861 | _T_864; // @[lib.scala 102:41]
wire _T_867 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36]
wire _T_868 = _T_867 & _T_861; // @[lib.scala 104:41]
wire _T_871 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78]
wire _T_872 = _T_868 | _T_871; // @[lib.scala 104:23]
wire _T_874 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36]
wire _T_875 = _T_874 & _T_861; // @[lib.scala 104:41]
wire _T_878 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78]
wire _T_879 = _T_875 | _T_878; // @[lib.scala 104:23]
wire _T_881 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36]
wire _T_882 = _T_881 & _T_861; // @[lib.scala 104:41]
wire _T_885 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78]
wire _T_886 = _T_882 | _T_885; // @[lib.scala 104:23]
wire _T_888 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36]
wire _T_889 = _T_888 & _T_861; // @[lib.scala 104:41]
wire _T_892 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78]
wire _T_893 = _T_889 | _T_892; // @[lib.scala 104:23]
wire _T_895 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36]
wire _T_896 = _T_895 & _T_861; // @[lib.scala 104:41]
wire _T_899 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78]
wire _T_900 = _T_896 | _T_899; // @[lib.scala 104:23]
wire _T_902 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36]
wire _T_903 = _T_902 & _T_861; // @[lib.scala 104:41]
wire _T_906 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78]
wire _T_907 = _T_903 | _T_906; // @[lib.scala 104:23]
wire _T_909 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36]
wire _T_910 = _T_909 & _T_861; // @[lib.scala 104:41]
wire _T_913 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78]
wire _T_914 = _T_910 | _T_913; // @[lib.scala 104:23]
wire _T_916 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36]
wire _T_917 = _T_916 & _T_861; // @[lib.scala 104:41]
wire _T_920 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78]
wire _T_921 = _T_917 | _T_920; // @[lib.scala 104:23]
wire _T_923 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36]
wire _T_924 = _T_923 & _T_861; // @[lib.scala 104:41]
wire _T_927 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78]
wire _T_928 = _T_924 | _T_927; // @[lib.scala 104:23]
wire _T_930 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36]
wire _T_931 = _T_930 & _T_861; // @[lib.scala 104:41]
wire _T_934 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78]
wire _T_935 = _T_931 | _T_934; // @[lib.scala 104:23]
wire _T_937 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36]
wire _T_938 = _T_937 & _T_861; // @[lib.scala 104:41]
wire _T_941 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78]
wire _T_942 = _T_938 | _T_941; // @[lib.scala 104:23]
wire _T_944 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36]
wire _T_945 = _T_944 & _T_861; // @[lib.scala 104:41]
wire _T_948 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78]
wire _T_949 = _T_945 | _T_948; // @[lib.scala 104:23]
wire _T_951 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36]
wire _T_952 = _T_951 & _T_861; // @[lib.scala 104:41]
wire _T_955 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78]
wire _T_956 = _T_952 | _T_955; // @[lib.scala 104:23]
wire _T_958 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36]
wire _T_959 = _T_958 & _T_861; // @[lib.scala 104:41]
wire _T_962 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78]
wire _T_963 = _T_959 | _T_962; // @[lib.scala 104:23]
wire _T_965 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36]
wire _T_966 = _T_965 & _T_861; // @[lib.scala 104:41]
wire _T_969 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78]
wire _T_970 = _T_966 | _T_969; // @[lib.scala 104:23]
wire _T_972 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36]
wire _T_973 = _T_972 & _T_861; // @[lib.scala 104:41]
wire _T_976 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78]
wire _T_977 = _T_973 | _T_976; // @[lib.scala 104:23]
wire _T_979 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36]
wire _T_980 = _T_979 & _T_861; // @[lib.scala 104:41]
wire _T_983 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78]
wire _T_984 = _T_980 | _T_983; // @[lib.scala 104:23]
wire _T_986 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36]
wire _T_987 = _T_986 & _T_861; // @[lib.scala 104:41]
wire _T_990 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78]
wire _T_991 = _T_987 | _T_990; // @[lib.scala 104:23]
wire _T_993 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36]
wire _T_994 = _T_993 & _T_861; // @[lib.scala 104:41]
wire _T_997 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78]
wire _T_998 = _T_994 | _T_997; // @[lib.scala 104:23]
wire _T_1000 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36]
wire _T_1001 = _T_1000 & _T_861; // @[lib.scala 104:41]
wire _T_1004 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78]
wire _T_1005 = _T_1001 | _T_1004; // @[lib.scala 104:23]
wire _T_1007 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36]
wire _T_1008 = _T_1007 & _T_861; // @[lib.scala 104:41]
wire _T_1011 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78]
wire _T_1012 = _T_1008 | _T_1011; // @[lib.scala 104:23]
wire _T_1014 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36]
wire _T_1015 = _T_1014 & _T_861; // @[lib.scala 104:41]
wire _T_1018 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78]
wire _T_1019 = _T_1015 | _T_1018; // @[lib.scala 104:23]
wire _T_1021 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36]
wire _T_1022 = _T_1021 & _T_861; // @[lib.scala 104:41]
wire _T_1025 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78]
wire _T_1026 = _T_1022 | _T_1025; // @[lib.scala 104:23]
wire _T_1028 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36]
wire _T_1029 = _T_1028 & _T_861; // @[lib.scala 104:41]
wire _T_1032 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78]
wire _T_1033 = _T_1029 | _T_1032; // @[lib.scala 104:23]
wire _T_1035 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36]
wire _T_1036 = _T_1035 & _T_861; // @[lib.scala 104:41]
wire _T_1039 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78]
wire _T_1040 = _T_1036 | _T_1039; // @[lib.scala 104:23]
wire _T_1042 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36]
wire _T_1043 = _T_1042 & _T_861; // @[lib.scala 104:41]
wire _T_1046 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78]
wire _T_1047 = _T_1043 | _T_1046; // @[lib.scala 104:23]
wire _T_1049 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36]
wire _T_1050 = _T_1049 & _T_861; // @[lib.scala 104:41]
wire _T_1053 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78]
wire _T_1054 = _T_1050 | _T_1053; // @[lib.scala 104:23]
wire _T_1056 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36]
wire _T_1057 = _T_1056 & _T_861; // @[lib.scala 104:41]
wire _T_1060 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78]
wire _T_1061 = _T_1057 | _T_1060; // @[lib.scala 104:23]
wire _T_1063 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36]
wire _T_1064 = _T_1063 & _T_861; // @[lib.scala 104:41]
wire _T_1067 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78]
wire _T_1068 = _T_1064 | _T_1067; // @[lib.scala 104:23]
wire _T_1070 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36]
wire _T_1071 = _T_1070 & _T_861; // @[lib.scala 104:41]
wire _T_1074 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78]
wire _T_1075 = _T_1071 | _T_1074; // @[lib.scala 104:23]
wire _T_1077 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36]
wire _T_1078 = _T_1077 & _T_861; // @[lib.scala 104:41]
wire _T_1081 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78]
wire _T_1082 = _T_1078 | _T_1081; // @[lib.scala 104:23]
wire [7:0] _T_1089 = {_T_914,_T_907,_T_900,_T_893,_T_886,_T_879,_T_872,_T_865}; // @[lib.scala 105:14]
wire [15:0] _T_1097 = {_T_970,_T_963,_T_956,_T_949,_T_942,_T_935,_T_928,_T_921,_T_1089}; // @[lib.scala 105:14]
wire [7:0] _T_1104 = {_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_991,_T_984,_T_977}; // @[lib.scala 105:14]
wire [31:0] _T_1113 = {_T_1082,_T_1075,_T_1068,_T_1061,_T_1054,_T_1047,_T_1040,_T_1033,_T_1104,_T_1097}; // @[lib.scala 105:14]
wire _T_1114 = &_T_1113; // @[lib.scala 105:25]
wire _T_1115 = _T_856 & _T_1114; // @[lsu_trigger.scala 21:92]
wire [2:0] _T_1117 = {_T_1115,_T_847,_T_579}; // @[Cat.scala 29:58]
assign io_lsu_trigger_match_m = {_T_1117,_T_311}; // @[lsu_trigger.scala 20:25]
endmodule

13
untitled/untitled.iml
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@ -1,13 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<module type="JAVA_MODULE" version="4">
<component name="NewModuleRootManager">
<output-test url="test" />
<exclude-output />
<content url="file://$MODULE_DIR$">
<sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
</content>
<orderEntry type="inheritedJdk" />
<orderEntry type="sourceFolder" forTests="false" />
<orderEntry type="library" name="sbt: org.scala-lang:scala-library:2.12.10:jar" level="project" />
</component>
</module>