Aligner Updated

el2_ifu_aln_ctl.fir

@@ -2440,7 +2440,7 @@ circuit el2_ifu_aln_ctl :
     node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 218:26]
     node f0prett = bits(misc0eff, 50, 18) @[el2_ifu_aln_ctl.scala 219:25]
     node f0poffset = bits(misc0eff, 17, 5) @[el2_ifu_aln_ctl.scala 220:27]
-    node f0fghr = bits(misc0eff, 4, 0) @[el2_ifu_aln_ctl.scala 221:24]
+    node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 221:24]
     node _T_225 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:37]
     node _T_226 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:58]
     node _T_227 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:77]

el2_ifu_aln_ctl.v

@@ -817,7 +817,7 @@ module el2_ifu_aln_ctl(
   wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 218:26]
   wire [32:0] f0prett = misc0eff[50:18]; // @[el2_ifu_aln_ctl.scala 219:25]
   wire [12:0] f0poffset = misc0eff[17:5]; // @[el2_ifu_aln_ctl.scala 220:27]
-  wire [4:0] f0fghr = misc0eff[4:0]; // @[el2_ifu_aln_ctl.scala 221:24]
+  wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24]
   wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58]
   wire [23:0] _T_253 = {brdata2,brdata1}; // @[Cat.scala 29:58]
   wire [23:0] _T_256 = {brdata0,brdata2}; // @[Cat.scala 29:58]
@@ -984,7 +984,7 @@ module el2_ifu_aln_ctl(
   assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22]
   assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22]
   assign io_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22]
-  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : {{3'd0}, f0fghr}; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
+  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
   assign io_ifu_i0_bp_btag = _T_738 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 59:21 el2_ifu_aln_ctl.scala 404:21]
   assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
   assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]

src/main/scala/ifu/el2_ifu_aln_ctl.scala

@@ -218,7 +218,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
   val f0ictype = misc0eff(MHI-2, MHI-3)
   val f0prett = misc0eff(MHI-4,MHI-36)
   val f0poffset = misc0eff(MHI-37, MHI-49)
-  val f0fghr = misc0eff(MHI-50, 0)
+  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
 
   brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
     io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),